1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright (c) 2021 Western Digital Corporation or its affiliates. |
4 | * Copyright (c) 2022 Ventana Micro Systems Inc. |
5 | */ |
6 | |
7 | #include <linux/linkage.h> |
8 | #include <linux/cfi_types.h> |
9 | #include <asm/asm.h> |
10 | #include <asm/asm-offsets.h> |
11 | #include <asm/assembler.h> |
12 | #include <asm/csr.h> |
13 | #include <asm/xip_fixup.h> |
14 | |
15 | .text |
16 | .altmacro |
17 | .option norelax |
18 | |
19 | SYM_FUNC_START(__cpu_suspend_enter) |
20 | /* Save registers (except A0 and T0-T6) */ |
21 | REG_S ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0) |
22 | REG_S sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0) |
23 | REG_S gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0) |
24 | REG_S tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0) |
25 | REG_S s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0) |
26 | REG_S s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0) |
27 | REG_S a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0) |
28 | REG_S a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0) |
29 | REG_S a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0) |
30 | REG_S a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0) |
31 | REG_S a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0) |
32 | REG_S a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0) |
33 | REG_S a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0) |
34 | REG_S s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0) |
35 | REG_S s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0) |
36 | REG_S s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0) |
37 | REG_S s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0) |
38 | REG_S s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0) |
39 | REG_S s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0) |
40 | REG_S s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0) |
41 | REG_S s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0) |
42 | REG_S s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0) |
43 | REG_S s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0) |
44 | |
45 | /* Save CSRs */ |
46 | csrr t0, CSR_EPC |
47 | REG_S t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0) |
48 | csrr t0, CSR_STATUS |
49 | REG_S t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0) |
50 | csrr t0, CSR_TVAL |
51 | REG_S t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0) |
52 | csrr t0, CSR_CAUSE |
53 | REG_S t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0) |
54 | |
55 | /* Return non-zero value */ |
56 | li a0, 1 |
57 | |
58 | /* Return to C code */ |
59 | ret |
60 | SYM_FUNC_END(__cpu_suspend_enter) |
61 | |
62 | SYM_TYPED_FUNC_START(__cpu_resume_enter) |
63 | /* Load the global pointer */ |
64 | load_global_pointer |
65 | |
66 | #ifdef CONFIG_MMU |
67 | /* Save A0 and A1 */ |
68 | add t0, a0, zero |
69 | add t1, a1, zero |
70 | |
71 | /* Enable MMU */ |
72 | la a0, swapper_pg_dir |
73 | XIP_FIXUP_OFFSET a0 |
74 | call relocate_enable_mmu |
75 | |
76 | /* Restore A0 and A1 */ |
77 | add a0, t0, zero |
78 | add a1, t1, zero |
79 | #endif |
80 | |
81 | /* Make A0 point to suspend context */ |
82 | add a0, a1, zero |
83 | |
84 | /* Restore CSRs */ |
85 | suspend_restore_csrs |
86 | |
87 | /* Restore registers (except A0 and T0-T6) */ |
88 | suspend_restore_regs |
89 | |
90 | /* Return zero value */ |
91 | add a0, zero, zero |
92 | |
93 | /* Return to C code */ |
94 | ret |
95 | SYM_FUNC_END(__cpu_resume_enter) |
96 | |