| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2019 Western Digital Corporation or its affiliates. |
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| 4 | * |
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| 5 | * Authors: |
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| 6 | * Anup Patel <anup.patel@wdc.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #include <linux/linkage.h> |
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| 10 | #include <asm/asm.h> |
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| 11 | #include <asm/asm-offsets.h> |
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| 12 | #include <asm/csr.h> |
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| 13 | |
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| 14 | .text |
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| 15 | .altmacro |
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| 16 | .option norelax |
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| 17 | |
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| 18 | SYM_FUNC_START(__kvm_riscv_switch_to) |
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| 19 | /* Save Host GPRs (except A0 and T0-T6) */ |
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| 20 | REG_S ra, (KVM_ARCH_HOST_RA)(a0) |
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| 21 | REG_S sp, (KVM_ARCH_HOST_SP)(a0) |
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| 22 | REG_S gp, (KVM_ARCH_HOST_GP)(a0) |
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| 23 | REG_S tp, (KVM_ARCH_HOST_TP)(a0) |
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| 24 | REG_S s0, (KVM_ARCH_HOST_S0)(a0) |
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| 25 | REG_S s1, (KVM_ARCH_HOST_S1)(a0) |
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| 26 | REG_S a1, (KVM_ARCH_HOST_A1)(a0) |
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| 27 | REG_S a2, (KVM_ARCH_HOST_A2)(a0) |
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| 28 | REG_S a3, (KVM_ARCH_HOST_A3)(a0) |
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| 29 | REG_S a4, (KVM_ARCH_HOST_A4)(a0) |
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| 30 | REG_S a5, (KVM_ARCH_HOST_A5)(a0) |
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| 31 | REG_S a6, (KVM_ARCH_HOST_A6)(a0) |
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| 32 | REG_S a7, (KVM_ARCH_HOST_A7)(a0) |
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| 33 | REG_S s2, (KVM_ARCH_HOST_S2)(a0) |
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| 34 | REG_S s3, (KVM_ARCH_HOST_S3)(a0) |
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| 35 | REG_S s4, (KVM_ARCH_HOST_S4)(a0) |
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| 36 | REG_S s5, (KVM_ARCH_HOST_S5)(a0) |
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| 37 | REG_S s6, (KVM_ARCH_HOST_S6)(a0) |
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| 38 | REG_S s7, (KVM_ARCH_HOST_S7)(a0) |
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| 39 | REG_S s8, (KVM_ARCH_HOST_S8)(a0) |
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| 40 | REG_S s9, (KVM_ARCH_HOST_S9)(a0) |
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| 41 | REG_S s10, (KVM_ARCH_HOST_S10)(a0) |
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| 42 | REG_S s11, (KVM_ARCH_HOST_S11)(a0) |
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| 43 | |
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| 44 | /* Load Guest CSR values */ |
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| 45 | REG_L t0, (KVM_ARCH_GUEST_SSTATUS)(a0) |
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| 46 | REG_L t1, (KVM_ARCH_GUEST_HSTATUS)(a0) |
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| 47 | REG_L t2, (KVM_ARCH_GUEST_SCOUNTEREN)(a0) |
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| 48 | la t4, .Lkvm_switch_return |
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| 49 | REG_L t5, (KVM_ARCH_GUEST_SEPC)(a0) |
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| 50 | |
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| 51 | /* Save Host and Restore Guest SSTATUS */ |
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| 52 | csrrw t0, CSR_SSTATUS, t0 |
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| 53 | |
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| 54 | /* Save Host and Restore Guest HSTATUS */ |
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| 55 | csrrw t1, CSR_HSTATUS, t1 |
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| 56 | |
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| 57 | /* Save Host and Restore Guest SCOUNTEREN */ |
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| 58 | csrrw t2, CSR_SCOUNTEREN, t2 |
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| 59 | |
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| 60 | /* Save Host STVEC and change it to return path */ |
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| 61 | csrrw t4, CSR_STVEC, t4 |
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| 62 | |
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| 63 | /* Save Host SSCRATCH and change it to struct kvm_vcpu_arch pointer */ |
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| 64 | csrrw t3, CSR_SSCRATCH, a0 |
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| 65 | |
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| 66 | /* Restore Guest SEPC */ |
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| 67 | csrw CSR_SEPC, t5 |
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| 68 | |
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| 69 | /* Store Host CSR values */ |
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| 70 | REG_S t0, (KVM_ARCH_HOST_SSTATUS)(a0) |
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| 71 | REG_S t1, (KVM_ARCH_HOST_HSTATUS)(a0) |
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| 72 | REG_S t2, (KVM_ARCH_HOST_SCOUNTEREN)(a0) |
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| 73 | REG_S t3, (KVM_ARCH_HOST_SSCRATCH)(a0) |
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| 74 | REG_S t4, (KVM_ARCH_HOST_STVEC)(a0) |
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| 75 | |
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| 76 | /* Restore Guest GPRs (except A0) */ |
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| 77 | REG_L ra, (KVM_ARCH_GUEST_RA)(a0) |
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| 78 | REG_L sp, (KVM_ARCH_GUEST_SP)(a0) |
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| 79 | REG_L gp, (KVM_ARCH_GUEST_GP)(a0) |
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| 80 | REG_L tp, (KVM_ARCH_GUEST_TP)(a0) |
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| 81 | REG_L t0, (KVM_ARCH_GUEST_T0)(a0) |
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| 82 | REG_L t1, (KVM_ARCH_GUEST_T1)(a0) |
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| 83 | REG_L t2, (KVM_ARCH_GUEST_T2)(a0) |
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| 84 | REG_L s0, (KVM_ARCH_GUEST_S0)(a0) |
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| 85 | REG_L s1, (KVM_ARCH_GUEST_S1)(a0) |
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| 86 | REG_L a1, (KVM_ARCH_GUEST_A1)(a0) |
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| 87 | REG_L a2, (KVM_ARCH_GUEST_A2)(a0) |
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| 88 | REG_L a3, (KVM_ARCH_GUEST_A3)(a0) |
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| 89 | REG_L a4, (KVM_ARCH_GUEST_A4)(a0) |
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| 90 | REG_L a5, (KVM_ARCH_GUEST_A5)(a0) |
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| 91 | REG_L a6, (KVM_ARCH_GUEST_A6)(a0) |
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| 92 | REG_L a7, (KVM_ARCH_GUEST_A7)(a0) |
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| 93 | REG_L s2, (KVM_ARCH_GUEST_S2)(a0) |
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| 94 | REG_L s3, (KVM_ARCH_GUEST_S3)(a0) |
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| 95 | REG_L s4, (KVM_ARCH_GUEST_S4)(a0) |
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| 96 | REG_L s5, (KVM_ARCH_GUEST_S5)(a0) |
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| 97 | REG_L s6, (KVM_ARCH_GUEST_S6)(a0) |
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| 98 | REG_L s7, (KVM_ARCH_GUEST_S7)(a0) |
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| 99 | REG_L s8, (KVM_ARCH_GUEST_S8)(a0) |
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| 100 | REG_L s9, (KVM_ARCH_GUEST_S9)(a0) |
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| 101 | REG_L s10, (KVM_ARCH_GUEST_S10)(a0) |
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| 102 | REG_L s11, (KVM_ARCH_GUEST_S11)(a0) |
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| 103 | REG_L t3, (KVM_ARCH_GUEST_T3)(a0) |
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| 104 | REG_L t4, (KVM_ARCH_GUEST_T4)(a0) |
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| 105 | REG_L t5, (KVM_ARCH_GUEST_T5)(a0) |
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| 106 | REG_L t6, (KVM_ARCH_GUEST_T6)(a0) |
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| 107 | |
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| 108 | /* Restore Guest A0 */ |
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| 109 | REG_L a0, (KVM_ARCH_GUEST_A0)(a0) |
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| 110 | |
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| 111 | /* Resume Guest */ |
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| 112 | sret |
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| 113 | |
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| 114 | /* Back to Host */ |
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| 115 | .align 2 |
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| 116 | .Lkvm_switch_return: |
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| 117 | /* Swap Guest A0 with SSCRATCH */ |
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| 118 | csrrw a0, CSR_SSCRATCH, a0 |
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| 119 | |
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| 120 | /* Save Guest GPRs (except A0) */ |
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| 121 | REG_S ra, (KVM_ARCH_GUEST_RA)(a0) |
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| 122 | REG_S sp, (KVM_ARCH_GUEST_SP)(a0) |
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| 123 | REG_S gp, (KVM_ARCH_GUEST_GP)(a0) |
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| 124 | REG_S tp, (KVM_ARCH_GUEST_TP)(a0) |
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| 125 | REG_S t0, (KVM_ARCH_GUEST_T0)(a0) |
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| 126 | REG_S t1, (KVM_ARCH_GUEST_T1)(a0) |
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| 127 | REG_S t2, (KVM_ARCH_GUEST_T2)(a0) |
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| 128 | REG_S s0, (KVM_ARCH_GUEST_S0)(a0) |
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| 129 | REG_S s1, (KVM_ARCH_GUEST_S1)(a0) |
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| 130 | REG_S a1, (KVM_ARCH_GUEST_A1)(a0) |
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| 131 | REG_S a2, (KVM_ARCH_GUEST_A2)(a0) |
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| 132 | REG_S a3, (KVM_ARCH_GUEST_A3)(a0) |
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| 133 | REG_S a4, (KVM_ARCH_GUEST_A4)(a0) |
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| 134 | REG_S a5, (KVM_ARCH_GUEST_A5)(a0) |
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| 135 | REG_S a6, (KVM_ARCH_GUEST_A6)(a0) |
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| 136 | REG_S a7, (KVM_ARCH_GUEST_A7)(a0) |
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| 137 | REG_S s2, (KVM_ARCH_GUEST_S2)(a0) |
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| 138 | REG_S s3, (KVM_ARCH_GUEST_S3)(a0) |
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| 139 | REG_S s4, (KVM_ARCH_GUEST_S4)(a0) |
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| 140 | REG_S s5, (KVM_ARCH_GUEST_S5)(a0) |
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| 141 | REG_S s6, (KVM_ARCH_GUEST_S6)(a0) |
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| 142 | REG_S s7, (KVM_ARCH_GUEST_S7)(a0) |
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| 143 | REG_S s8, (KVM_ARCH_GUEST_S8)(a0) |
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| 144 | REG_S s9, (KVM_ARCH_GUEST_S9)(a0) |
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| 145 | REG_S s10, (KVM_ARCH_GUEST_S10)(a0) |
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| 146 | REG_S s11, (KVM_ARCH_GUEST_S11)(a0) |
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| 147 | REG_S t3, (KVM_ARCH_GUEST_T3)(a0) |
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| 148 | REG_S t4, (KVM_ARCH_GUEST_T4)(a0) |
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| 149 | REG_S t5, (KVM_ARCH_GUEST_T5)(a0) |
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| 150 | REG_S t6, (KVM_ARCH_GUEST_T6)(a0) |
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| 151 | |
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| 152 | /* Load Host CSR values */ |
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| 153 | REG_L t1, (KVM_ARCH_HOST_STVEC)(a0) |
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| 154 | REG_L t2, (KVM_ARCH_HOST_SSCRATCH)(a0) |
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| 155 | REG_L t3, (KVM_ARCH_HOST_SCOUNTEREN)(a0) |
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| 156 | REG_L t4, (KVM_ARCH_HOST_HSTATUS)(a0) |
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| 157 | REG_L t5, (KVM_ARCH_HOST_SSTATUS)(a0) |
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| 158 | |
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| 159 | /* Save Guest SEPC */ |
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| 160 | csrr t0, CSR_SEPC |
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| 161 | |
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| 162 | /* Save Guest A0 and Restore Host SSCRATCH */ |
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| 163 | csrrw t2, CSR_SSCRATCH, t2 |
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| 164 | |
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| 165 | /* Restore Host STVEC */ |
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| 166 | csrw CSR_STVEC, t1 |
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| 167 | |
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| 168 | /* Save Guest and Restore Host SCOUNTEREN */ |
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| 169 | csrrw t3, CSR_SCOUNTEREN, t3 |
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| 170 | |
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| 171 | /* Save Guest and Restore Host HSTATUS */ |
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| 172 | csrrw t4, CSR_HSTATUS, t4 |
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| 173 | |
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| 174 | /* Save Guest and Restore Host SSTATUS */ |
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| 175 | csrrw t5, CSR_SSTATUS, t5 |
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| 176 | |
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| 177 | /* Store Guest CSR values */ |
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| 178 | REG_S t0, (KVM_ARCH_GUEST_SEPC)(a0) |
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| 179 | REG_S t2, (KVM_ARCH_GUEST_A0)(a0) |
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| 180 | REG_S t3, (KVM_ARCH_GUEST_SCOUNTEREN)(a0) |
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| 181 | REG_S t4, (KVM_ARCH_GUEST_HSTATUS)(a0) |
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| 182 | REG_S t5, (KVM_ARCH_GUEST_SSTATUS)(a0) |
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| 183 | |
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| 184 | /* Restore Host GPRs (except A0 and T0-T6) */ |
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| 185 | REG_L ra, (KVM_ARCH_HOST_RA)(a0) |
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| 186 | REG_L sp, (KVM_ARCH_HOST_SP)(a0) |
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| 187 | REG_L gp, (KVM_ARCH_HOST_GP)(a0) |
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| 188 | REG_L tp, (KVM_ARCH_HOST_TP)(a0) |
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| 189 | REG_L s0, (KVM_ARCH_HOST_S0)(a0) |
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| 190 | REG_L s1, (KVM_ARCH_HOST_S1)(a0) |
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| 191 | REG_L a1, (KVM_ARCH_HOST_A1)(a0) |
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| 192 | REG_L a2, (KVM_ARCH_HOST_A2)(a0) |
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| 193 | REG_L a3, (KVM_ARCH_HOST_A3)(a0) |
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| 194 | REG_L a4, (KVM_ARCH_HOST_A4)(a0) |
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| 195 | REG_L a5, (KVM_ARCH_HOST_A5)(a0) |
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| 196 | REG_L a6, (KVM_ARCH_HOST_A6)(a0) |
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| 197 | REG_L a7, (KVM_ARCH_HOST_A7)(a0) |
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| 198 | REG_L s2, (KVM_ARCH_HOST_S2)(a0) |
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| 199 | REG_L s3, (KVM_ARCH_HOST_S3)(a0) |
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| 200 | REG_L s4, (KVM_ARCH_HOST_S4)(a0) |
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| 201 | REG_L s5, (KVM_ARCH_HOST_S5)(a0) |
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| 202 | REG_L s6, (KVM_ARCH_HOST_S6)(a0) |
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| 203 | REG_L s7, (KVM_ARCH_HOST_S7)(a0) |
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| 204 | REG_L s8, (KVM_ARCH_HOST_S8)(a0) |
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| 205 | REG_L s9, (KVM_ARCH_HOST_S9)(a0) |
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| 206 | REG_L s10, (KVM_ARCH_HOST_S10)(a0) |
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| 207 | REG_L s11, (KVM_ARCH_HOST_S11)(a0) |
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| 208 | |
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| 209 | /* Return to C code */ |
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| 210 | ret |
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| 211 | SYM_FUNC_END(__kvm_riscv_switch_to) |
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| 212 | |
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| 213 | SYM_CODE_START(__kvm_riscv_unpriv_trap) |
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| 214 | /* |
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| 215 | * We assume that faulting unpriv load/store instruction is |
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| 216 | * 4-byte long and blindly increment SEPC by 4. |
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| 217 | * |
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| 218 | * The trap details will be saved at address pointed by 'A0' |
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| 219 | * register and we use 'A1' register as temporary. |
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| 220 | */ |
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| 221 | csrr a1, CSR_SEPC |
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| 222 | REG_S a1, (KVM_ARCH_TRAP_SEPC)(a0) |
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| 223 | addi a1, a1, 4 |
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| 224 | csrw CSR_SEPC, a1 |
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| 225 | csrr a1, CSR_SCAUSE |
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| 226 | REG_S a1, (KVM_ARCH_TRAP_SCAUSE)(a0) |
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| 227 | csrr a1, CSR_STVAL |
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| 228 | REG_S a1, (KVM_ARCH_TRAP_STVAL)(a0) |
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| 229 | csrr a1, CSR_HTVAL |
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| 230 | REG_S a1, (KVM_ARCH_TRAP_HTVAL)(a0) |
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| 231 | csrr a1, CSR_HTINST |
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| 232 | REG_S a1, (KVM_ARCH_TRAP_HTINST)(a0) |
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| 233 | sret |
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| 234 | SYM_CODE_END(__kvm_riscv_unpriv_trap) |
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| 235 | |
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| 236 | #ifdef CONFIG_FPU |
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| 237 | SYM_FUNC_START(__kvm_riscv_fp_f_save) |
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| 238 | csrr t2, CSR_SSTATUS |
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| 239 | li t1, SR_FS |
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| 240 | csrs CSR_SSTATUS, t1 |
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| 241 | frcsr t0 |
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| 242 | fsw f0, KVM_ARCH_FP_F_F0(a0) |
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| 243 | fsw f1, KVM_ARCH_FP_F_F1(a0) |
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| 244 | fsw f2, KVM_ARCH_FP_F_F2(a0) |
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| 245 | fsw f3, KVM_ARCH_FP_F_F3(a0) |
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| 246 | fsw f4, KVM_ARCH_FP_F_F4(a0) |
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| 247 | fsw f5, KVM_ARCH_FP_F_F5(a0) |
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| 248 | fsw f6, KVM_ARCH_FP_F_F6(a0) |
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| 249 | fsw f7, KVM_ARCH_FP_F_F7(a0) |
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| 250 | fsw f8, KVM_ARCH_FP_F_F8(a0) |
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| 251 | fsw f9, KVM_ARCH_FP_F_F9(a0) |
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| 252 | fsw f10, KVM_ARCH_FP_F_F10(a0) |
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| 253 | fsw f11, KVM_ARCH_FP_F_F11(a0) |
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| 254 | fsw f12, KVM_ARCH_FP_F_F12(a0) |
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| 255 | fsw f13, KVM_ARCH_FP_F_F13(a0) |
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| 256 | fsw f14, KVM_ARCH_FP_F_F14(a0) |
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| 257 | fsw f15, KVM_ARCH_FP_F_F15(a0) |
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| 258 | fsw f16, KVM_ARCH_FP_F_F16(a0) |
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| 259 | fsw f17, KVM_ARCH_FP_F_F17(a0) |
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| 260 | fsw f18, KVM_ARCH_FP_F_F18(a0) |
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| 261 | fsw f19, KVM_ARCH_FP_F_F19(a0) |
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| 262 | fsw f20, KVM_ARCH_FP_F_F20(a0) |
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| 263 | fsw f21, KVM_ARCH_FP_F_F21(a0) |
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| 264 | fsw f22, KVM_ARCH_FP_F_F22(a0) |
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| 265 | fsw f23, KVM_ARCH_FP_F_F23(a0) |
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| 266 | fsw f24, KVM_ARCH_FP_F_F24(a0) |
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| 267 | fsw f25, KVM_ARCH_FP_F_F25(a0) |
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| 268 | fsw f26, KVM_ARCH_FP_F_F26(a0) |
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| 269 | fsw f27, KVM_ARCH_FP_F_F27(a0) |
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| 270 | fsw f28, KVM_ARCH_FP_F_F28(a0) |
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| 271 | fsw f29, KVM_ARCH_FP_F_F29(a0) |
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| 272 | fsw f30, KVM_ARCH_FP_F_F30(a0) |
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| 273 | fsw f31, KVM_ARCH_FP_F_F31(a0) |
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| 274 | sw t0, KVM_ARCH_FP_F_FCSR(a0) |
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| 275 | csrw CSR_SSTATUS, t2 |
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| 276 | ret |
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| 277 | SYM_FUNC_END(__kvm_riscv_fp_f_save) |
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| 278 | |
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| 279 | SYM_FUNC_START(__kvm_riscv_fp_d_save) |
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| 280 | csrr t2, CSR_SSTATUS |
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| 281 | li t1, SR_FS |
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| 282 | csrs CSR_SSTATUS, t1 |
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| 283 | frcsr t0 |
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| 284 | fsd f0, KVM_ARCH_FP_D_F0(a0) |
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| 285 | fsd f1, KVM_ARCH_FP_D_F1(a0) |
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| 286 | fsd f2, KVM_ARCH_FP_D_F2(a0) |
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| 287 | fsd f3, KVM_ARCH_FP_D_F3(a0) |
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| 288 | fsd f4, KVM_ARCH_FP_D_F4(a0) |
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| 289 | fsd f5, KVM_ARCH_FP_D_F5(a0) |
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| 290 | fsd f6, KVM_ARCH_FP_D_F6(a0) |
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| 291 | fsd f7, KVM_ARCH_FP_D_F7(a0) |
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| 292 | fsd f8, KVM_ARCH_FP_D_F8(a0) |
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| 293 | fsd f9, KVM_ARCH_FP_D_F9(a0) |
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| 294 | fsd f10, KVM_ARCH_FP_D_F10(a0) |
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| 295 | fsd f11, KVM_ARCH_FP_D_F11(a0) |
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| 296 | fsd f12, KVM_ARCH_FP_D_F12(a0) |
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| 297 | fsd f13, KVM_ARCH_FP_D_F13(a0) |
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| 298 | fsd f14, KVM_ARCH_FP_D_F14(a0) |
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| 299 | fsd f15, KVM_ARCH_FP_D_F15(a0) |
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| 300 | fsd f16, KVM_ARCH_FP_D_F16(a0) |
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| 301 | fsd f17, KVM_ARCH_FP_D_F17(a0) |
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| 302 | fsd f18, KVM_ARCH_FP_D_F18(a0) |
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| 303 | fsd f19, KVM_ARCH_FP_D_F19(a0) |
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| 304 | fsd f20, KVM_ARCH_FP_D_F20(a0) |
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| 305 | fsd f21, KVM_ARCH_FP_D_F21(a0) |
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| 306 | fsd f22, KVM_ARCH_FP_D_F22(a0) |
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| 307 | fsd f23, KVM_ARCH_FP_D_F23(a0) |
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| 308 | fsd f24, KVM_ARCH_FP_D_F24(a0) |
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| 309 | fsd f25, KVM_ARCH_FP_D_F25(a0) |
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| 310 | fsd f26, KVM_ARCH_FP_D_F26(a0) |
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| 311 | fsd f27, KVM_ARCH_FP_D_F27(a0) |
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| 312 | fsd f28, KVM_ARCH_FP_D_F28(a0) |
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| 313 | fsd f29, KVM_ARCH_FP_D_F29(a0) |
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| 314 | fsd f30, KVM_ARCH_FP_D_F30(a0) |
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| 315 | fsd f31, KVM_ARCH_FP_D_F31(a0) |
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| 316 | sw t0, KVM_ARCH_FP_D_FCSR(a0) |
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| 317 | csrw CSR_SSTATUS, t2 |
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| 318 | ret |
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| 319 | SYM_FUNC_END(__kvm_riscv_fp_d_save) |
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| 320 | |
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| 321 | SYM_FUNC_START(__kvm_riscv_fp_f_restore) |
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| 322 | csrr t2, CSR_SSTATUS |
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| 323 | li t1, SR_FS |
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| 324 | lw t0, KVM_ARCH_FP_F_FCSR(a0) |
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| 325 | csrs CSR_SSTATUS, t1 |
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| 326 | flw f0, KVM_ARCH_FP_F_F0(a0) |
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| 327 | flw f1, KVM_ARCH_FP_F_F1(a0) |
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| 328 | flw f2, KVM_ARCH_FP_F_F2(a0) |
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| 329 | flw f3, KVM_ARCH_FP_F_F3(a0) |
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| 330 | flw f4, KVM_ARCH_FP_F_F4(a0) |
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| 331 | flw f5, KVM_ARCH_FP_F_F5(a0) |
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| 332 | flw f6, KVM_ARCH_FP_F_F6(a0) |
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| 333 | flw f7, KVM_ARCH_FP_F_F7(a0) |
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| 334 | flw f8, KVM_ARCH_FP_F_F8(a0) |
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| 335 | flw f9, KVM_ARCH_FP_F_F9(a0) |
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| 336 | flw f10, KVM_ARCH_FP_F_F10(a0) |
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| 337 | flw f11, KVM_ARCH_FP_F_F11(a0) |
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| 338 | flw f12, KVM_ARCH_FP_F_F12(a0) |
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| 339 | flw f13, KVM_ARCH_FP_F_F13(a0) |
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| 340 | flw f14, KVM_ARCH_FP_F_F14(a0) |
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| 341 | flw f15, KVM_ARCH_FP_F_F15(a0) |
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| 342 | flw f16, KVM_ARCH_FP_F_F16(a0) |
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| 343 | flw f17, KVM_ARCH_FP_F_F17(a0) |
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| 344 | flw f18, KVM_ARCH_FP_F_F18(a0) |
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| 345 | flw f19, KVM_ARCH_FP_F_F19(a0) |
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| 346 | flw f20, KVM_ARCH_FP_F_F20(a0) |
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| 347 | flw f21, KVM_ARCH_FP_F_F21(a0) |
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| 348 | flw f22, KVM_ARCH_FP_F_F22(a0) |
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| 349 | flw f23, KVM_ARCH_FP_F_F23(a0) |
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| 350 | flw f24, KVM_ARCH_FP_F_F24(a0) |
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| 351 | flw f25, KVM_ARCH_FP_F_F25(a0) |
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| 352 | flw f26, KVM_ARCH_FP_F_F26(a0) |
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| 353 | flw f27, KVM_ARCH_FP_F_F27(a0) |
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| 354 | flw f28, KVM_ARCH_FP_F_F28(a0) |
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| 355 | flw f29, KVM_ARCH_FP_F_F29(a0) |
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| 356 | flw f30, KVM_ARCH_FP_F_F30(a0) |
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| 357 | flw f31, KVM_ARCH_FP_F_F31(a0) |
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| 358 | fscsr t0 |
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| 359 | csrw CSR_SSTATUS, t2 |
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| 360 | ret |
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| 361 | SYM_FUNC_END(__kvm_riscv_fp_f_restore) |
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| 362 | |
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| 363 | SYM_FUNC_START(__kvm_riscv_fp_d_restore) |
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| 364 | csrr t2, CSR_SSTATUS |
|---|
| 365 | li t1, SR_FS |
|---|
| 366 | lw t0, KVM_ARCH_FP_D_FCSR(a0) |
|---|
| 367 | csrs CSR_SSTATUS, t1 |
|---|
| 368 | fld f0, KVM_ARCH_FP_D_F0(a0) |
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| 369 | fld f1, KVM_ARCH_FP_D_F1(a0) |
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| 370 | fld f2, KVM_ARCH_FP_D_F2(a0) |
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| 371 | fld f3, KVM_ARCH_FP_D_F3(a0) |
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| 372 | fld f4, KVM_ARCH_FP_D_F4(a0) |
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| 373 | fld f5, KVM_ARCH_FP_D_F5(a0) |
|---|
| 374 | fld f6, KVM_ARCH_FP_D_F6(a0) |
|---|
| 375 | fld f7, KVM_ARCH_FP_D_F7(a0) |
|---|
| 376 | fld f8, KVM_ARCH_FP_D_F8(a0) |
|---|
| 377 | fld f9, KVM_ARCH_FP_D_F9(a0) |
|---|
| 378 | fld f10, KVM_ARCH_FP_D_F10(a0) |
|---|
| 379 | fld f11, KVM_ARCH_FP_D_F11(a0) |
|---|
| 380 | fld f12, KVM_ARCH_FP_D_F12(a0) |
|---|
| 381 | fld f13, KVM_ARCH_FP_D_F13(a0) |
|---|
| 382 | fld f14, KVM_ARCH_FP_D_F14(a0) |
|---|
| 383 | fld f15, KVM_ARCH_FP_D_F15(a0) |
|---|
| 384 | fld f16, KVM_ARCH_FP_D_F16(a0) |
|---|
| 385 | fld f17, KVM_ARCH_FP_D_F17(a0) |
|---|
| 386 | fld f18, KVM_ARCH_FP_D_F18(a0) |
|---|
| 387 | fld f19, KVM_ARCH_FP_D_F19(a0) |
|---|
| 388 | fld f20, KVM_ARCH_FP_D_F20(a0) |
|---|
| 389 | fld f21, KVM_ARCH_FP_D_F21(a0) |
|---|
| 390 | fld f22, KVM_ARCH_FP_D_F22(a0) |
|---|
| 391 | fld f23, KVM_ARCH_FP_D_F23(a0) |
|---|
| 392 | fld f24, KVM_ARCH_FP_D_F24(a0) |
|---|
| 393 | fld f25, KVM_ARCH_FP_D_F25(a0) |
|---|
| 394 | fld f26, KVM_ARCH_FP_D_F26(a0) |
|---|
| 395 | fld f27, KVM_ARCH_FP_D_F27(a0) |
|---|
| 396 | fld f28, KVM_ARCH_FP_D_F28(a0) |
|---|
| 397 | fld f29, KVM_ARCH_FP_D_F29(a0) |
|---|
| 398 | fld f30, KVM_ARCH_FP_D_F30(a0) |
|---|
| 399 | fld f31, KVM_ARCH_FP_D_F31(a0) |
|---|
| 400 | fscsr t0 |
|---|
| 401 | csrw CSR_SSTATUS, t2 |
|---|
| 402 | ret |
|---|
| 403 | SYM_FUNC_END(__kvm_riscv_fp_d_restore) |
|---|
| 404 | #endif |
|---|
| 405 | |
|---|
