1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Perf PMU sysfs events attributes for available CPU-measurement counters |
4 | * |
5 | */ |
6 | |
7 | #include <linux/slab.h> |
8 | #include <linux/perf_event.h> |
9 | #include <asm/cpu_mf.h> |
10 | |
11 | |
12 | /* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */ |
13 | |
14 | CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000); |
15 | CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001); |
16 | CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002); |
17 | CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003); |
18 | CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020); |
19 | CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021); |
20 | CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022); |
21 | CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023); |
22 | CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024); |
23 | CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025); |
24 | CPUMF_EVENT_ATTR(cf_fvn1, L1D_DIR_WRITES, 0x0004); |
25 | CPUMF_EVENT_ATTR(cf_fvn1, L1D_PENALTY_CYCLES, 0x0005); |
26 | CPUMF_EVENT_ATTR(cf_fvn3, CPU_CYCLES, 0x0000); |
27 | CPUMF_EVENT_ATTR(cf_fvn3, INSTRUCTIONS, 0x0001); |
28 | CPUMF_EVENT_ATTR(cf_fvn3, L1I_DIR_WRITES, 0x0002); |
29 | CPUMF_EVENT_ATTR(cf_fvn3, L1I_PENALTY_CYCLES, 0x0003); |
30 | CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES, 0x0020); |
31 | CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS, 0x0021); |
32 | CPUMF_EVENT_ATTR(cf_fvn3, L1D_DIR_WRITES, 0x0004); |
33 | CPUMF_EVENT_ATTR(cf_fvn3, L1D_PENALTY_CYCLES, 0x0005); |
34 | CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_FUNCTIONS, 0x0040); |
35 | CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_CYCLES, 0x0041); |
36 | CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS, 0x0042); |
37 | CPUMF_EVENT_ATTR(cf_svn_12345, PRNG_BLOCKED_CYCLES, 0x0043); |
38 | CPUMF_EVENT_ATTR(cf_svn_12345, SHA_FUNCTIONS, 0x0044); |
39 | CPUMF_EVENT_ATTR(cf_svn_12345, SHA_CYCLES, 0x0045); |
40 | CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS, 0x0046); |
41 | CPUMF_EVENT_ATTR(cf_svn_12345, SHA_BLOCKED_CYCLES, 0x0047); |
42 | CPUMF_EVENT_ATTR(cf_svn_12345, DEA_FUNCTIONS, 0x0048); |
43 | CPUMF_EVENT_ATTR(cf_svn_12345, DEA_CYCLES, 0x0049); |
44 | CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS, 0x004a); |
45 | CPUMF_EVENT_ATTR(cf_svn_12345, DEA_BLOCKED_CYCLES, 0x004b); |
46 | CPUMF_EVENT_ATTR(cf_svn_12345, AES_FUNCTIONS, 0x004c); |
47 | CPUMF_EVENT_ATTR(cf_svn_12345, AES_CYCLES, 0x004d); |
48 | CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS, 0x004e); |
49 | CPUMF_EVENT_ATTR(cf_svn_12345, AES_BLOCKED_CYCLES, 0x004f); |
50 | CPUMF_EVENT_ATTR(cf_svn_6, ECC_FUNCTION_COUNT, 0x0050); |
51 | CPUMF_EVENT_ATTR(cf_svn_6, ECC_CYCLES_COUNT, 0x0051); |
52 | CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT, 0x0052); |
53 | CPUMF_EVENT_ATTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT, 0x0053); |
54 | CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080); |
55 | CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081); |
56 | CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082); |
57 | CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083); |
58 | CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084); |
59 | CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085); |
60 | CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086); |
61 | CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087); |
62 | CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088); |
63 | CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089); |
64 | CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a); |
65 | CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b); |
66 | CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c); |
67 | CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d); |
68 | CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e); |
69 | CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091); |
70 | CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092); |
71 | CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093); |
72 | CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080); |
73 | CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081); |
74 | CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082); |
75 | CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083); |
76 | CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085); |
77 | CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086); |
78 | CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087); |
79 | CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088); |
80 | CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089); |
81 | CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a); |
82 | CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b); |
83 | CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c); |
84 | CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d); |
85 | CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e); |
86 | CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f); |
87 | CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090); |
88 | CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091); |
89 | CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092); |
90 | CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093); |
91 | CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094); |
92 | CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096); |
93 | CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098); |
94 | CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099); |
95 | CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b); |
96 | CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080); |
97 | CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081); |
98 | CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082); |
99 | CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083); |
100 | CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084); |
101 | CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085); |
102 | CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087); |
103 | CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089); |
104 | CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a); |
105 | CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b); |
106 | CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c); |
107 | CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d); |
108 | CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e); |
109 | CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f); |
110 | CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090); |
111 | CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091); |
112 | CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092); |
113 | CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093); |
114 | CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094); |
115 | CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095); |
116 | CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096); |
117 | CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097); |
118 | CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098); |
119 | CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099); |
120 | CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a); |
121 | CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b); |
122 | CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c); |
123 | CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d); |
124 | CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e); |
125 | CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f); |
126 | CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0); |
127 | CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1); |
128 | CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1); |
129 | CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2); |
130 | CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3); |
131 | CPUMF_EVENT_ATTR(cf_z13, L1D_RO_EXCL_WRITES, 0x0080); |
132 | CPUMF_EVENT_ATTR(cf_z13, DTLB1_WRITES, 0x0081); |
133 | CPUMF_EVENT_ATTR(cf_z13, DTLB1_MISSES, 0x0082); |
134 | CPUMF_EVENT_ATTR(cf_z13, DTLB1_HPAGE_WRITES, 0x0083); |
135 | CPUMF_EVENT_ATTR(cf_z13, DTLB1_GPAGE_WRITES, 0x0084); |
136 | CPUMF_EVENT_ATTR(cf_z13, L1D_L2D_SOURCED_WRITES, 0x0085); |
137 | CPUMF_EVENT_ATTR(cf_z13, ITLB1_WRITES, 0x0086); |
138 | CPUMF_EVENT_ATTR(cf_z13, ITLB1_MISSES, 0x0087); |
139 | CPUMF_EVENT_ATTR(cf_z13, L1I_L2I_SOURCED_WRITES, 0x0088); |
140 | CPUMF_EVENT_ATTR(cf_z13, TLB2_PTE_WRITES, 0x0089); |
141 | CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES, 0x008a); |
142 | CPUMF_EVENT_ATTR(cf_z13, TLB2_CRSTE_WRITES, 0x008b); |
143 | CPUMF_EVENT_ATTR(cf_z13, TX_C_TEND, 0x008c); |
144 | CPUMF_EVENT_ATTR(cf_z13, TX_NC_TEND, 0x008d); |
145 | CPUMF_EVENT_ATTR(cf_z13, L1C_TLB1_MISSES, 0x008f); |
146 | CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090); |
147 | CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0091); |
148 | CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES, 0x0092); |
149 | CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV, 0x0093); |
150 | CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES, 0x0094); |
151 | CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x0095); |
152 | CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV, 0x0096); |
153 | CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES, 0x0097); |
154 | CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x0098); |
155 | CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x0099); |
156 | CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x009a); |
157 | CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x009b); |
158 | CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x009c); |
159 | CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x009d); |
160 | CPUMF_EVENT_ATTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES, 0x009e); |
161 | CPUMF_EVENT_ATTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES, 0x009f); |
162 | CPUMF_EVENT_ATTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES, 0x00a0); |
163 | CPUMF_EVENT_ATTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES, 0x00a1); |
164 | CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2); |
165 | CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a3); |
166 | CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES, 0x00a4); |
167 | CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV, 0x00a5); |
168 | CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES, 0x00a6); |
169 | CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00a7); |
170 | CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV, 0x00a8); |
171 | CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES, 0x00a9); |
172 | CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES, 0x00aa); |
173 | CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV, 0x00ab); |
174 | CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES, 0x00ac); |
175 | CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES, 0x00ad); |
176 | CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV, 0x00ae); |
177 | CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES, 0x00af); |
178 | CPUMF_EVENT_ATTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES, 0x00b0); |
179 | CPUMF_EVENT_ATTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES, 0x00b1); |
180 | CPUMF_EVENT_ATTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES, 0x00b2); |
181 | CPUMF_EVENT_ATTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES, 0x00b3); |
182 | CPUMF_EVENT_ATTR(cf_z13, TX_NC_TABORT, 0x00da); |
183 | CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db); |
184 | CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc); |
185 | CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0); |
186 | CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1); |
187 | CPUMF_EVENT_ATTR(cf_z14, L1D_RO_EXCL_WRITES, 0x0080); |
188 | CPUMF_EVENT_ATTR(cf_z14, DTLB2_WRITES, 0x0081); |
189 | CPUMF_EVENT_ATTR(cf_z14, DTLB2_MISSES, 0x0082); |
190 | CPUMF_EVENT_ATTR(cf_z14, DTLB2_HPAGE_WRITES, 0x0083); |
191 | CPUMF_EVENT_ATTR(cf_z14, DTLB2_GPAGE_WRITES, 0x0084); |
192 | CPUMF_EVENT_ATTR(cf_z14, L1D_L2D_SOURCED_WRITES, 0x0085); |
193 | CPUMF_EVENT_ATTR(cf_z14, ITLB2_WRITES, 0x0086); |
194 | CPUMF_EVENT_ATTR(cf_z14, ITLB2_MISSES, 0x0087); |
195 | CPUMF_EVENT_ATTR(cf_z14, L1I_L2I_SOURCED_WRITES, 0x0088); |
196 | CPUMF_EVENT_ATTR(cf_z14, TLB2_PTE_WRITES, 0x0089); |
197 | CPUMF_EVENT_ATTR(cf_z14, TLB2_CRSTE_WRITES, 0x008a); |
198 | CPUMF_EVENT_ATTR(cf_z14, TLB2_ENGINES_BUSY, 0x008b); |
199 | CPUMF_EVENT_ATTR(cf_z14, TX_C_TEND, 0x008c); |
200 | CPUMF_EVENT_ATTR(cf_z14, TX_NC_TEND, 0x008d); |
201 | CPUMF_EVENT_ATTR(cf_z14, L1C_TLB2_MISSES, 0x008f); |
202 | CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090); |
203 | CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091); |
204 | CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092); |
205 | CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093); |
206 | CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094); |
207 | CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095); |
208 | CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096); |
209 | CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097); |
210 | CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098); |
211 | CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099); |
212 | CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a); |
213 | CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b); |
214 | CPUMF_EVENT_ATTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c); |
215 | CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d); |
216 | CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e); |
217 | CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2); |
218 | CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3); |
219 | CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4); |
220 | CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5); |
221 | CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6); |
222 | CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7); |
223 | CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8); |
224 | CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9); |
225 | CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa); |
226 | CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab); |
227 | CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac); |
228 | CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad); |
229 | CPUMF_EVENT_ATTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae); |
230 | CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af); |
231 | CPUMF_EVENT_ATTR(cf_z14, BCD_DFP_EXECUTION_SLOTS, 0x00e0); |
232 | CPUMF_EVENT_ATTR(cf_z14, VX_BCD_EXECUTION_SLOTS, 0x00e1); |
233 | CPUMF_EVENT_ATTR(cf_z14, DECIMAL_INSTRUCTIONS, 0x00e2); |
234 | CPUMF_EVENT_ATTR(cf_z14, LAST_HOST_TRANSLATIONS, 0x00e8); |
235 | CPUMF_EVENT_ATTR(cf_z14, TX_NC_TABORT, 0x00f3); |
236 | CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4); |
237 | CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5); |
238 | CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0); |
239 | CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1); |
240 | |
241 | CPUMF_EVENT_ATTR(cf_z15, L1D_RO_EXCL_WRITES, 0x0080); |
242 | CPUMF_EVENT_ATTR(cf_z15, DTLB2_WRITES, 0x0081); |
243 | CPUMF_EVENT_ATTR(cf_z15, DTLB2_MISSES, 0x0082); |
244 | CPUMF_EVENT_ATTR(cf_z15, DTLB2_HPAGE_WRITES, 0x0083); |
245 | CPUMF_EVENT_ATTR(cf_z15, DTLB2_GPAGE_WRITES, 0x0084); |
246 | CPUMF_EVENT_ATTR(cf_z15, L1D_L2D_SOURCED_WRITES, 0x0085); |
247 | CPUMF_EVENT_ATTR(cf_z15, ITLB2_WRITES, 0x0086); |
248 | CPUMF_EVENT_ATTR(cf_z15, ITLB2_MISSES, 0x0087); |
249 | CPUMF_EVENT_ATTR(cf_z15, L1I_L2I_SOURCED_WRITES, 0x0088); |
250 | CPUMF_EVENT_ATTR(cf_z15, TLB2_PTE_WRITES, 0x0089); |
251 | CPUMF_EVENT_ATTR(cf_z15, TLB2_CRSTE_WRITES, 0x008a); |
252 | CPUMF_EVENT_ATTR(cf_z15, TLB2_ENGINES_BUSY, 0x008b); |
253 | CPUMF_EVENT_ATTR(cf_z15, TX_C_TEND, 0x008c); |
254 | CPUMF_EVENT_ATTR(cf_z15, TX_NC_TEND, 0x008d); |
255 | CPUMF_EVENT_ATTR(cf_z15, L1C_TLB2_MISSES, 0x008f); |
256 | CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090); |
257 | CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091); |
258 | CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092); |
259 | CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093); |
260 | CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094); |
261 | CPUMF_EVENT_ATTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095); |
262 | CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096); |
263 | CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097); |
264 | CPUMF_EVENT_ATTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098); |
265 | CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099); |
266 | CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a); |
267 | CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b); |
268 | CPUMF_EVENT_ATTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c); |
269 | CPUMF_EVENT_ATTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d); |
270 | CPUMF_EVENT_ATTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e); |
271 | CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2); |
272 | CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3); |
273 | CPUMF_EVENT_ATTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4); |
274 | CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5); |
275 | CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6); |
276 | CPUMF_EVENT_ATTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7); |
277 | CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8); |
278 | CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9); |
279 | CPUMF_EVENT_ATTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa); |
280 | CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab); |
281 | CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac); |
282 | CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad); |
283 | CPUMF_EVENT_ATTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae); |
284 | CPUMF_EVENT_ATTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af); |
285 | CPUMF_EVENT_ATTR(cf_z15, BCD_DFP_EXECUTION_SLOTS, 0x00e0); |
286 | CPUMF_EVENT_ATTR(cf_z15, VX_BCD_EXECUTION_SLOTS, 0x00e1); |
287 | CPUMF_EVENT_ATTR(cf_z15, DECIMAL_INSTRUCTIONS, 0x00e2); |
288 | CPUMF_EVENT_ATTR(cf_z15, LAST_HOST_TRANSLATIONS, 0x00e8); |
289 | CPUMF_EVENT_ATTR(cf_z15, TX_NC_TABORT, 0x00f3); |
290 | CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_NO_SPECIAL, 0x00f4); |
291 | CPUMF_EVENT_ATTR(cf_z15, TX_C_TABORT_SPECIAL, 0x00f5); |
292 | CPUMF_EVENT_ATTR(cf_z15, DFLT_ACCESS, 0x00f7); |
293 | CPUMF_EVENT_ATTR(cf_z15, DFLT_CYCLES, 0x00fc); |
294 | CPUMF_EVENT_ATTR(cf_z15, DFLT_CC, 0x00108); |
295 | CPUMF_EVENT_ATTR(cf_z15, DFLT_CCFINISH, 0x00109); |
296 | CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0); |
297 | CPUMF_EVENT_ATTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1); |
298 | CPUMF_EVENT_ATTR(cf_z16, L1D_RO_EXCL_WRITES, 0x0080); |
299 | CPUMF_EVENT_ATTR(cf_z16, DTLB2_WRITES, 0x0081); |
300 | CPUMF_EVENT_ATTR(cf_z16, DTLB2_MISSES, 0x0082); |
301 | CPUMF_EVENT_ATTR(cf_z16, CRSTE_1MB_WRITES, 0x0083); |
302 | CPUMF_EVENT_ATTR(cf_z16, DTLB2_GPAGE_WRITES, 0x0084); |
303 | CPUMF_EVENT_ATTR(cf_z16, ITLB2_WRITES, 0x0086); |
304 | CPUMF_EVENT_ATTR(cf_z16, ITLB2_MISSES, 0x0087); |
305 | CPUMF_EVENT_ATTR(cf_z16, TLB2_PTE_WRITES, 0x0089); |
306 | CPUMF_EVENT_ATTR(cf_z16, TLB2_CRSTE_WRITES, 0x008a); |
307 | CPUMF_EVENT_ATTR(cf_z16, TLB2_ENGINES_BUSY, 0x008b); |
308 | CPUMF_EVENT_ATTR(cf_z16, TX_C_TEND, 0x008c); |
309 | CPUMF_EVENT_ATTR(cf_z16, TX_NC_TEND, 0x008d); |
310 | CPUMF_EVENT_ATTR(cf_z16, L1C_TLB2_MISSES, 0x008f); |
311 | CPUMF_EVENT_ATTR(cf_z16, DCW_REQ, 0x0091); |
312 | CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_IV, 0x0092); |
313 | CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_CHIP_HIT, 0x0093); |
314 | CPUMF_EVENT_ATTR(cf_z16, DCW_REQ_DRAWER_HIT, 0x0094); |
315 | CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP, 0x0095); |
316 | CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_IV, 0x0096); |
317 | CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_CHIP_HIT, 0x0097); |
318 | CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_DRAWER_HIT, 0x0098); |
319 | CPUMF_EVENT_ATTR(cf_z16, DCW_ON_MODULE, 0x0099); |
320 | CPUMF_EVENT_ATTR(cf_z16, DCW_ON_DRAWER, 0x009a); |
321 | CPUMF_EVENT_ATTR(cf_z16, DCW_OFF_DRAWER, 0x009b); |
322 | CPUMF_EVENT_ATTR(cf_z16, DCW_ON_CHIP_MEMORY, 0x009c); |
323 | CPUMF_EVENT_ATTR(cf_z16, DCW_ON_MODULE_MEMORY, 0x009d); |
324 | CPUMF_EVENT_ATTR(cf_z16, DCW_ON_DRAWER_MEMORY, 0x009e); |
325 | CPUMF_EVENT_ATTR(cf_z16, DCW_OFF_DRAWER_MEMORY, 0x009f); |
326 | CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_IV, 0x00a0); |
327 | CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_CHIP_HIT, 0x00a1); |
328 | CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_MODULE_DRAWER_HIT, 0x00a2); |
329 | CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_IV, 0x00a3); |
330 | CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_CHIP_HIT, 0x00a4); |
331 | CPUMF_EVENT_ATTR(cf_z16, IDCW_ON_DRAWER_DRAWER_HIT, 0x00a5); |
332 | CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_IV, 0x00a6); |
333 | CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_CHIP_HIT, 0x00a7); |
334 | CPUMF_EVENT_ATTR(cf_z16, IDCW_OFF_DRAWER_DRAWER_HIT, 0x00a8); |
335 | CPUMF_EVENT_ATTR(cf_z16, ICW_REQ, 0x00a9); |
336 | CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_IV, 0x00aa); |
337 | CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_CHIP_HIT, 0x00ab); |
338 | CPUMF_EVENT_ATTR(cf_z16, ICW_REQ_DRAWER_HIT, 0x00ac); |
339 | CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP, 0x00ad); |
340 | CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_IV, 0x00ae); |
341 | CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_CHIP_HIT, 0x00af); |
342 | CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_DRAWER_HIT, 0x00b0); |
343 | CPUMF_EVENT_ATTR(cf_z16, ICW_ON_MODULE, 0x00b1); |
344 | CPUMF_EVENT_ATTR(cf_z16, ICW_ON_DRAWER, 0x00b2); |
345 | CPUMF_EVENT_ATTR(cf_z16, ICW_OFF_DRAWER, 0x00b3); |
346 | CPUMF_EVENT_ATTR(cf_z16, ICW_ON_CHIP_MEMORY, 0x00b4); |
347 | CPUMF_EVENT_ATTR(cf_z16, ICW_ON_MODULE_MEMORY, 0x00b5); |
348 | CPUMF_EVENT_ATTR(cf_z16, ICW_ON_DRAWER_MEMORY, 0x00b6); |
349 | CPUMF_EVENT_ATTR(cf_z16, ICW_OFF_DRAWER_MEMORY, 0x00b7); |
350 | CPUMF_EVENT_ATTR(cf_z16, BCD_DFP_EXECUTION_SLOTS, 0x00e0); |
351 | CPUMF_EVENT_ATTR(cf_z16, VX_BCD_EXECUTION_SLOTS, 0x00e1); |
352 | CPUMF_EVENT_ATTR(cf_z16, DECIMAL_INSTRUCTIONS, 0x00e2); |
353 | CPUMF_EVENT_ATTR(cf_z16, LAST_HOST_TRANSLATIONS, 0x00e8); |
354 | CPUMF_EVENT_ATTR(cf_z16, TX_NC_TABORT, 0x00f4); |
355 | CPUMF_EVENT_ATTR(cf_z16, TX_C_TABORT_NO_SPECIAL, 0x00f5); |
356 | CPUMF_EVENT_ATTR(cf_z16, TX_C_TABORT_SPECIAL, 0x00f6); |
357 | CPUMF_EVENT_ATTR(cf_z16, DFLT_ACCESS, 0x00f8); |
358 | CPUMF_EVENT_ATTR(cf_z16, DFLT_CYCLES, 0x00fd); |
359 | CPUMF_EVENT_ATTR(cf_z16, SORTL, 0x0100); |
360 | CPUMF_EVENT_ATTR(cf_z16, DFLT_CC, 0x0109); |
361 | CPUMF_EVENT_ATTR(cf_z16, DFLT_CCFINISH, 0x010a); |
362 | CPUMF_EVENT_ATTR(cf_z16, NNPA_INVOCATIONS, 0x010b); |
363 | CPUMF_EVENT_ATTR(cf_z16, NNPA_COMPLETIONS, 0x010c); |
364 | CPUMF_EVENT_ATTR(cf_z16, NNPA_WAIT_LOCK, 0x010d); |
365 | CPUMF_EVENT_ATTR(cf_z16, NNPA_HOLD_LOCK, 0x010e); |
366 | CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0); |
367 | CPUMF_EVENT_ATTR(cf_z16, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1); |
368 | |
369 | static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = { |
370 | CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES), |
371 | CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS), |
372 | CPUMF_EVENT_PTR(cf_fvn1, L1I_DIR_WRITES), |
373 | CPUMF_EVENT_PTR(cf_fvn1, L1I_PENALTY_CYCLES), |
374 | CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES), |
375 | CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS), |
376 | CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES), |
377 | CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES), |
378 | CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES), |
379 | CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES), |
380 | CPUMF_EVENT_PTR(cf_fvn1, L1D_DIR_WRITES), |
381 | CPUMF_EVENT_PTR(cf_fvn1, L1D_PENALTY_CYCLES), |
382 | NULL, |
383 | }; |
384 | |
385 | static struct attribute *cpumcf_fvn3_pmu_event_attr[] __initdata = { |
386 | CPUMF_EVENT_PTR(cf_fvn3, CPU_CYCLES), |
387 | CPUMF_EVENT_PTR(cf_fvn3, INSTRUCTIONS), |
388 | CPUMF_EVENT_PTR(cf_fvn3, L1I_DIR_WRITES), |
389 | CPUMF_EVENT_PTR(cf_fvn3, L1I_PENALTY_CYCLES), |
390 | CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES), |
391 | CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS), |
392 | CPUMF_EVENT_PTR(cf_fvn3, L1D_DIR_WRITES), |
393 | CPUMF_EVENT_PTR(cf_fvn3, L1D_PENALTY_CYCLES), |
394 | NULL, |
395 | }; |
396 | |
397 | static struct attribute *cpumcf_svn_12345_pmu_event_attr[] __initdata = { |
398 | CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS), |
399 | CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES), |
400 | CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS), |
401 | CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES), |
402 | CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS), |
403 | CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES), |
404 | CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS), |
405 | CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES), |
406 | CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS), |
407 | CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES), |
408 | CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS), |
409 | CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES), |
410 | CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS), |
411 | CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES), |
412 | CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS), |
413 | CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES), |
414 | NULL, |
415 | }; |
416 | |
417 | static struct attribute *cpumcf_svn_67_pmu_event_attr[] __initdata = { |
418 | CPUMF_EVENT_PTR(cf_svn_12345, PRNG_FUNCTIONS), |
419 | CPUMF_EVENT_PTR(cf_svn_12345, PRNG_CYCLES), |
420 | CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_FUNCTIONS), |
421 | CPUMF_EVENT_PTR(cf_svn_12345, PRNG_BLOCKED_CYCLES), |
422 | CPUMF_EVENT_PTR(cf_svn_12345, SHA_FUNCTIONS), |
423 | CPUMF_EVENT_PTR(cf_svn_12345, SHA_CYCLES), |
424 | CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_FUNCTIONS), |
425 | CPUMF_EVENT_PTR(cf_svn_12345, SHA_BLOCKED_CYCLES), |
426 | CPUMF_EVENT_PTR(cf_svn_12345, DEA_FUNCTIONS), |
427 | CPUMF_EVENT_PTR(cf_svn_12345, DEA_CYCLES), |
428 | CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_FUNCTIONS), |
429 | CPUMF_EVENT_PTR(cf_svn_12345, DEA_BLOCKED_CYCLES), |
430 | CPUMF_EVENT_PTR(cf_svn_12345, AES_FUNCTIONS), |
431 | CPUMF_EVENT_PTR(cf_svn_12345, AES_CYCLES), |
432 | CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_FUNCTIONS), |
433 | CPUMF_EVENT_PTR(cf_svn_12345, AES_BLOCKED_CYCLES), |
434 | CPUMF_EVENT_PTR(cf_svn_6, ECC_FUNCTION_COUNT), |
435 | CPUMF_EVENT_PTR(cf_svn_6, ECC_CYCLES_COUNT), |
436 | CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_FUNCTION_COUNT), |
437 | CPUMF_EVENT_PTR(cf_svn_6, ECC_BLOCKED_CYCLES_COUNT), |
438 | NULL, |
439 | }; |
440 | |
441 | static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = { |
442 | CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES), |
443 | CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES), |
444 | CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES), |
445 | CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES), |
446 | CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES), |
447 | CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES), |
448 | CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES), |
449 | CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES), |
450 | CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES), |
451 | CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES), |
452 | CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES), |
453 | CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES), |
454 | CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES), |
455 | CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES), |
456 | CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES), |
457 | CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES), |
458 | CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES), |
459 | CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT), |
460 | NULL, |
461 | }; |
462 | |
463 | static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = { |
464 | CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES), |
465 | CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES), |
466 | CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES), |
467 | CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES), |
468 | CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT), |
469 | CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES), |
470 | CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES), |
471 | CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES), |
472 | CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES), |
473 | CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES), |
474 | CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES), |
475 | CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES), |
476 | CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES), |
477 | CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES), |
478 | CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES), |
479 | CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES), |
480 | CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES), |
481 | CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES), |
482 | CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES), |
483 | CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES), |
484 | CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES), |
485 | CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES), |
486 | CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES), |
487 | CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES), |
488 | NULL, |
489 | }; |
490 | |
491 | static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = { |
492 | CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES), |
493 | CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES), |
494 | CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES), |
495 | CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES), |
496 | CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES), |
497 | CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES), |
498 | CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES), |
499 | CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES), |
500 | CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES), |
501 | CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES), |
502 | CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES), |
503 | CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES), |
504 | CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES), |
505 | CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES), |
506 | CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES), |
507 | CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES), |
508 | CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES), |
509 | CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES), |
510 | CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES), |
511 | CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND), |
512 | CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV), |
513 | CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV), |
514 | CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV), |
515 | CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES), |
516 | CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES), |
517 | CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES), |
518 | CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES), |
519 | CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES), |
520 | CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND), |
521 | CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV), |
522 | CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV), |
523 | CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV), |
524 | CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT), |
525 | CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL), |
526 | CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL), |
527 | NULL, |
528 | }; |
529 | |
530 | static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = { |
531 | CPUMF_EVENT_PTR(cf_z13, L1D_RO_EXCL_WRITES), |
532 | CPUMF_EVENT_PTR(cf_z13, DTLB1_WRITES), |
533 | CPUMF_EVENT_PTR(cf_z13, DTLB1_MISSES), |
534 | CPUMF_EVENT_PTR(cf_z13, DTLB1_HPAGE_WRITES), |
535 | CPUMF_EVENT_PTR(cf_z13, DTLB1_GPAGE_WRITES), |
536 | CPUMF_EVENT_PTR(cf_z13, L1D_L2D_SOURCED_WRITES), |
537 | CPUMF_EVENT_PTR(cf_z13, ITLB1_WRITES), |
538 | CPUMF_EVENT_PTR(cf_z13, ITLB1_MISSES), |
539 | CPUMF_EVENT_PTR(cf_z13, L1I_L2I_SOURCED_WRITES), |
540 | CPUMF_EVENT_PTR(cf_z13, TLB2_PTE_WRITES), |
541 | CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_HPAGE_WRITES), |
542 | CPUMF_EVENT_PTR(cf_z13, TLB2_CRSTE_WRITES), |
543 | CPUMF_EVENT_PTR(cf_z13, TX_C_TEND), |
544 | CPUMF_EVENT_PTR(cf_z13, TX_NC_TEND), |
545 | CPUMF_EVENT_PTR(cf_z13, L1C_TLB1_MISSES), |
546 | CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES), |
547 | CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_L3_SOURCED_WRITES_IV), |
548 | CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L4_SOURCED_WRITES), |
549 | CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES_IV), |
550 | CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_L3_SOURCED_WRITES), |
551 | CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L4_SOURCED_WRITES), |
552 | CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES_IV), |
553 | CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_L3_SOURCED_WRITES), |
554 | CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES), |
555 | CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV), |
556 | CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES), |
557 | CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES), |
558 | CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV), |
559 | CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES), |
560 | CPUMF_EVENT_PTR(cf_z13, L1D_ONNODE_MEM_SOURCED_WRITES), |
561 | CPUMF_EVENT_PTR(cf_z13, L1D_ONDRAWER_MEM_SOURCED_WRITES), |
562 | CPUMF_EVENT_PTR(cf_z13, L1D_OFFDRAWER_MEM_SOURCED_WRITES), |
563 | CPUMF_EVENT_PTR(cf_z13, L1D_ONCHIP_MEM_SOURCED_WRITES), |
564 | CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES), |
565 | CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_L3_SOURCED_WRITES_IV), |
566 | CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L4_SOURCED_WRITES), |
567 | CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES_IV), |
568 | CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_L3_SOURCED_WRITES), |
569 | CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L4_SOURCED_WRITES), |
570 | CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES_IV), |
571 | CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_L3_SOURCED_WRITES), |
572 | CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES), |
573 | CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV), |
574 | CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES), |
575 | CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES), |
576 | CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV), |
577 | CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES), |
578 | CPUMF_EVENT_PTR(cf_z13, L1I_ONNODE_MEM_SOURCED_WRITES), |
579 | CPUMF_EVENT_PTR(cf_z13, L1I_ONDRAWER_MEM_SOURCED_WRITES), |
580 | CPUMF_EVENT_PTR(cf_z13, L1I_OFFDRAWER_MEM_SOURCED_WRITES), |
581 | CPUMF_EVENT_PTR(cf_z13, L1I_ONCHIP_MEM_SOURCED_WRITES), |
582 | CPUMF_EVENT_PTR(cf_z13, TX_NC_TABORT), |
583 | CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_NO_SPECIAL), |
584 | CPUMF_EVENT_PTR(cf_z13, TX_C_TABORT_SPECIAL), |
585 | CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE), |
586 | CPUMF_EVENT_PTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE), |
587 | NULL, |
588 | }; |
589 | |
590 | static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = { |
591 | CPUMF_EVENT_PTR(cf_z14, L1D_RO_EXCL_WRITES), |
592 | CPUMF_EVENT_PTR(cf_z14, DTLB2_WRITES), |
593 | CPUMF_EVENT_PTR(cf_z14, DTLB2_MISSES), |
594 | CPUMF_EVENT_PTR(cf_z14, DTLB2_HPAGE_WRITES), |
595 | CPUMF_EVENT_PTR(cf_z14, DTLB2_GPAGE_WRITES), |
596 | CPUMF_EVENT_PTR(cf_z14, L1D_L2D_SOURCED_WRITES), |
597 | CPUMF_EVENT_PTR(cf_z14, ITLB2_WRITES), |
598 | CPUMF_EVENT_PTR(cf_z14, ITLB2_MISSES), |
599 | CPUMF_EVENT_PTR(cf_z14, L1I_L2I_SOURCED_WRITES), |
600 | CPUMF_EVENT_PTR(cf_z14, TLB2_PTE_WRITES), |
601 | CPUMF_EVENT_PTR(cf_z14, TLB2_CRSTE_WRITES), |
602 | CPUMF_EVENT_PTR(cf_z14, TLB2_ENGINES_BUSY), |
603 | CPUMF_EVENT_PTR(cf_z14, TX_C_TEND), |
604 | CPUMF_EVENT_PTR(cf_z14, TX_NC_TEND), |
605 | CPUMF_EVENT_PTR(cf_z14, L1C_TLB2_MISSES), |
606 | CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES), |
607 | CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES), |
608 | CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV), |
609 | CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES), |
610 | CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES), |
611 | CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV), |
612 | CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES), |
613 | CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES), |
614 | CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV), |
615 | CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES), |
616 | CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES), |
617 | CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV), |
618 | CPUMF_EVENT_PTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES), |
619 | CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES), |
620 | CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO), |
621 | CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES), |
622 | CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES), |
623 | CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV), |
624 | CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES), |
625 | CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES), |
626 | CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV), |
627 | CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES), |
628 | CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES), |
629 | CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV), |
630 | CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES), |
631 | CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES), |
632 | CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV), |
633 | CPUMF_EVENT_PTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES), |
634 | CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES), |
635 | CPUMF_EVENT_PTR(cf_z14, BCD_DFP_EXECUTION_SLOTS), |
636 | CPUMF_EVENT_PTR(cf_z14, VX_BCD_EXECUTION_SLOTS), |
637 | CPUMF_EVENT_PTR(cf_z14, DECIMAL_INSTRUCTIONS), |
638 | CPUMF_EVENT_PTR(cf_z14, LAST_HOST_TRANSLATIONS), |
639 | CPUMF_EVENT_PTR(cf_z14, TX_NC_TABORT), |
640 | CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_NO_SPECIAL), |
641 | CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_SPECIAL), |
642 | CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE), |
643 | CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE), |
644 | NULL, |
645 | }; |
646 | |
647 | static struct attribute *cpumcf_z15_pmu_event_attr[] __initdata = { |
648 | CPUMF_EVENT_PTR(cf_z15, L1D_RO_EXCL_WRITES), |
649 | CPUMF_EVENT_PTR(cf_z15, DTLB2_WRITES), |
650 | CPUMF_EVENT_PTR(cf_z15, DTLB2_MISSES), |
651 | CPUMF_EVENT_PTR(cf_z15, DTLB2_HPAGE_WRITES), |
652 | CPUMF_EVENT_PTR(cf_z15, DTLB2_GPAGE_WRITES), |
653 | CPUMF_EVENT_PTR(cf_z15, L1D_L2D_SOURCED_WRITES), |
654 | CPUMF_EVENT_PTR(cf_z15, ITLB2_WRITES), |
655 | CPUMF_EVENT_PTR(cf_z15, ITLB2_MISSES), |
656 | CPUMF_EVENT_PTR(cf_z15, L1I_L2I_SOURCED_WRITES), |
657 | CPUMF_EVENT_PTR(cf_z15, TLB2_PTE_WRITES), |
658 | CPUMF_EVENT_PTR(cf_z15, TLB2_CRSTE_WRITES), |
659 | CPUMF_EVENT_PTR(cf_z15, TLB2_ENGINES_BUSY), |
660 | CPUMF_EVENT_PTR(cf_z15, TX_C_TEND), |
661 | CPUMF_EVENT_PTR(cf_z15, TX_NC_TEND), |
662 | CPUMF_EVENT_PTR(cf_z15, L1C_TLB2_MISSES), |
663 | CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES), |
664 | CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_MEMORY_SOURCED_WRITES), |
665 | CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_IV), |
666 | CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES), |
667 | CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES), |
668 | CPUMF_EVENT_PTR(cf_z15, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV), |
669 | CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES), |
670 | CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES), |
671 | CPUMF_EVENT_PTR(cf_z15, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV), |
672 | CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES), |
673 | CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES), |
674 | CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV), |
675 | CPUMF_EVENT_PTR(cf_z15, L1D_ONDRAWER_L4_SOURCED_WRITES), |
676 | CPUMF_EVENT_PTR(cf_z15, L1D_OFFDRAWER_L4_SOURCED_WRITES), |
677 | CPUMF_EVENT_PTR(cf_z15, L1D_ONCHIP_L3_SOURCED_WRITES_RO), |
678 | CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES), |
679 | CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_MEMORY_SOURCED_WRITES), |
680 | CPUMF_EVENT_PTR(cf_z15, L1I_ONCHIP_L3_SOURCED_WRITES_IV), |
681 | CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES), |
682 | CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES), |
683 | CPUMF_EVENT_PTR(cf_z15, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV), |
684 | CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES), |
685 | CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES), |
686 | CPUMF_EVENT_PTR(cf_z15, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV), |
687 | CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES), |
688 | CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES), |
689 | CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV), |
690 | CPUMF_EVENT_PTR(cf_z15, L1I_ONDRAWER_L4_SOURCED_WRITES), |
691 | CPUMF_EVENT_PTR(cf_z15, L1I_OFFDRAWER_L4_SOURCED_WRITES), |
692 | CPUMF_EVENT_PTR(cf_z15, BCD_DFP_EXECUTION_SLOTS), |
693 | CPUMF_EVENT_PTR(cf_z15, VX_BCD_EXECUTION_SLOTS), |
694 | CPUMF_EVENT_PTR(cf_z15, DECIMAL_INSTRUCTIONS), |
695 | CPUMF_EVENT_PTR(cf_z15, LAST_HOST_TRANSLATIONS), |
696 | CPUMF_EVENT_PTR(cf_z15, TX_NC_TABORT), |
697 | CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_NO_SPECIAL), |
698 | CPUMF_EVENT_PTR(cf_z15, TX_C_TABORT_SPECIAL), |
699 | CPUMF_EVENT_PTR(cf_z15, DFLT_ACCESS), |
700 | CPUMF_EVENT_PTR(cf_z15, DFLT_CYCLES), |
701 | CPUMF_EVENT_PTR(cf_z15, DFLT_CC), |
702 | CPUMF_EVENT_PTR(cf_z15, DFLT_CCFINISH), |
703 | CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_ONE_THR_ACTIVE), |
704 | CPUMF_EVENT_PTR(cf_z15, MT_DIAG_CYCLES_TWO_THR_ACTIVE), |
705 | NULL, |
706 | }; |
707 | |
708 | static struct attribute *cpumcf_z16_pmu_event_attr[] __initdata = { |
709 | CPUMF_EVENT_PTR(cf_z16, L1D_RO_EXCL_WRITES), |
710 | CPUMF_EVENT_PTR(cf_z16, DTLB2_WRITES), |
711 | CPUMF_EVENT_PTR(cf_z16, DTLB2_MISSES), |
712 | CPUMF_EVENT_PTR(cf_z16, CRSTE_1MB_WRITES), |
713 | CPUMF_EVENT_PTR(cf_z16, DTLB2_GPAGE_WRITES), |
714 | CPUMF_EVENT_PTR(cf_z16, ITLB2_WRITES), |
715 | CPUMF_EVENT_PTR(cf_z16, ITLB2_MISSES), |
716 | CPUMF_EVENT_PTR(cf_z16, TLB2_PTE_WRITES), |
717 | CPUMF_EVENT_PTR(cf_z16, TLB2_CRSTE_WRITES), |
718 | CPUMF_EVENT_PTR(cf_z16, TLB2_ENGINES_BUSY), |
719 | CPUMF_EVENT_PTR(cf_z16, TX_C_TEND), |
720 | CPUMF_EVENT_PTR(cf_z16, TX_NC_TEND), |
721 | CPUMF_EVENT_PTR(cf_z16, L1C_TLB2_MISSES), |
722 | CPUMF_EVENT_PTR(cf_z16, DCW_REQ), |
723 | CPUMF_EVENT_PTR(cf_z16, DCW_REQ_IV), |
724 | CPUMF_EVENT_PTR(cf_z16, DCW_REQ_CHIP_HIT), |
725 | CPUMF_EVENT_PTR(cf_z16, DCW_REQ_DRAWER_HIT), |
726 | CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP), |
727 | CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_IV), |
728 | CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_CHIP_HIT), |
729 | CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_DRAWER_HIT), |
730 | CPUMF_EVENT_PTR(cf_z16, DCW_ON_MODULE), |
731 | CPUMF_EVENT_PTR(cf_z16, DCW_ON_DRAWER), |
732 | CPUMF_EVENT_PTR(cf_z16, DCW_OFF_DRAWER), |
733 | CPUMF_EVENT_PTR(cf_z16, DCW_ON_CHIP_MEMORY), |
734 | CPUMF_EVENT_PTR(cf_z16, DCW_ON_MODULE_MEMORY), |
735 | CPUMF_EVENT_PTR(cf_z16, DCW_ON_DRAWER_MEMORY), |
736 | CPUMF_EVENT_PTR(cf_z16, DCW_OFF_DRAWER_MEMORY), |
737 | CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_IV), |
738 | CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_CHIP_HIT), |
739 | CPUMF_EVENT_PTR(cf_z16, IDCW_ON_MODULE_DRAWER_HIT), |
740 | CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_IV), |
741 | CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_CHIP_HIT), |
742 | CPUMF_EVENT_PTR(cf_z16, IDCW_ON_DRAWER_DRAWER_HIT), |
743 | CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_IV), |
744 | CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_CHIP_HIT), |
745 | CPUMF_EVENT_PTR(cf_z16, IDCW_OFF_DRAWER_DRAWER_HIT), |
746 | CPUMF_EVENT_PTR(cf_z16, ICW_REQ), |
747 | CPUMF_EVENT_PTR(cf_z16, ICW_REQ_IV), |
748 | CPUMF_EVENT_PTR(cf_z16, ICW_REQ_CHIP_HIT), |
749 | CPUMF_EVENT_PTR(cf_z16, ICW_REQ_DRAWER_HIT), |
750 | CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP), |
751 | CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_IV), |
752 | CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_CHIP_HIT), |
753 | CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_DRAWER_HIT), |
754 | CPUMF_EVENT_PTR(cf_z16, ICW_ON_MODULE), |
755 | CPUMF_EVENT_PTR(cf_z16, ICW_ON_DRAWER), |
756 | CPUMF_EVENT_PTR(cf_z16, ICW_OFF_DRAWER), |
757 | CPUMF_EVENT_PTR(cf_z16, ICW_ON_CHIP_MEMORY), |
758 | CPUMF_EVENT_PTR(cf_z16, ICW_ON_MODULE_MEMORY), |
759 | CPUMF_EVENT_PTR(cf_z16, ICW_ON_DRAWER_MEMORY), |
760 | CPUMF_EVENT_PTR(cf_z16, ICW_OFF_DRAWER_MEMORY), |
761 | CPUMF_EVENT_PTR(cf_z16, BCD_DFP_EXECUTION_SLOTS), |
762 | CPUMF_EVENT_PTR(cf_z16, VX_BCD_EXECUTION_SLOTS), |
763 | CPUMF_EVENT_PTR(cf_z16, DECIMAL_INSTRUCTIONS), |
764 | CPUMF_EVENT_PTR(cf_z16, LAST_HOST_TRANSLATIONS), |
765 | CPUMF_EVENT_PTR(cf_z16, TX_NC_TABORT), |
766 | CPUMF_EVENT_PTR(cf_z16, TX_C_TABORT_NO_SPECIAL), |
767 | CPUMF_EVENT_PTR(cf_z16, TX_C_TABORT_SPECIAL), |
768 | CPUMF_EVENT_PTR(cf_z16, DFLT_ACCESS), |
769 | CPUMF_EVENT_PTR(cf_z16, DFLT_CYCLES), |
770 | CPUMF_EVENT_PTR(cf_z16, SORTL), |
771 | CPUMF_EVENT_PTR(cf_z16, DFLT_CC), |
772 | CPUMF_EVENT_PTR(cf_z16, DFLT_CCFINISH), |
773 | CPUMF_EVENT_PTR(cf_z16, NNPA_INVOCATIONS), |
774 | CPUMF_EVENT_PTR(cf_z16, NNPA_COMPLETIONS), |
775 | CPUMF_EVENT_PTR(cf_z16, NNPA_WAIT_LOCK), |
776 | CPUMF_EVENT_PTR(cf_z16, NNPA_HOLD_LOCK), |
777 | CPUMF_EVENT_PTR(cf_z16, MT_DIAG_CYCLES_ONE_THR_ACTIVE), |
778 | CPUMF_EVENT_PTR(cf_z16, MT_DIAG_CYCLES_TWO_THR_ACTIVE), |
779 | NULL, |
780 | }; |
781 | |
782 | /* END: CPUM_CF COUNTER DEFINITIONS ===================================== */ |
783 | |
784 | static struct attribute_group cpumcf_pmu_events_group = { |
785 | .name = "events" , |
786 | }; |
787 | |
788 | PMU_FORMAT_ATTR(event, "config:0-63" ); |
789 | |
790 | static struct attribute *cpumcf_pmu_format_attr[] = { |
791 | &format_attr_event.attr, |
792 | NULL, |
793 | }; |
794 | |
795 | static struct attribute_group cpumcf_pmu_format_group = { |
796 | .name = "format" , |
797 | .attrs = cpumcf_pmu_format_attr, |
798 | }; |
799 | |
800 | static const struct attribute_group *cpumcf_pmu_attr_groups[] = { |
801 | &cpumcf_pmu_events_group, |
802 | &cpumcf_pmu_format_group, |
803 | NULL, |
804 | }; |
805 | |
806 | |
807 | static __init struct attribute **merge_attr(struct attribute **a, |
808 | struct attribute **b, |
809 | struct attribute **c) |
810 | { |
811 | struct attribute **new; |
812 | int j, i; |
813 | |
814 | for (j = 0; a[j]; j++) |
815 | ; |
816 | for (i = 0; b[i]; i++) |
817 | j++; |
818 | for (i = 0; c[i]; i++) |
819 | j++; |
820 | j++; |
821 | |
822 | new = kmalloc_array(n: j, size: sizeof(struct attribute *), GFP_KERNEL); |
823 | if (!new) |
824 | return NULL; |
825 | j = 0; |
826 | for (i = 0; a[i]; i++) |
827 | new[j++] = a[i]; |
828 | for (i = 0; b[i]; i++) |
829 | new[j++] = b[i]; |
830 | for (i = 0; c[i]; i++) |
831 | new[j++] = c[i]; |
832 | new[j] = NULL; |
833 | |
834 | return new; |
835 | } |
836 | |
837 | __init const struct attribute_group **cpumf_cf_event_group(void) |
838 | { |
839 | struct attribute **combined, **model, **cfvn, **csvn; |
840 | struct attribute *none[] = { NULL }; |
841 | struct cpumf_ctr_info ci; |
842 | struct cpuid cpu_id; |
843 | |
844 | /* Determine generic counters set(s) */ |
845 | qctri(&ci); |
846 | switch (ci.cfvn) { |
847 | case 1: |
848 | cfvn = cpumcf_fvn1_pmu_event_attr; |
849 | break; |
850 | case 3: |
851 | cfvn = cpumcf_fvn3_pmu_event_attr; |
852 | break; |
853 | default: |
854 | cfvn = none; |
855 | } |
856 | |
857 | /* Determine version specific crypto set */ |
858 | switch (ci.csvn) { |
859 | case 1 ... 5: |
860 | csvn = cpumcf_svn_12345_pmu_event_attr; |
861 | break; |
862 | case 6 ... 7: |
863 | csvn = cpumcf_svn_67_pmu_event_attr; |
864 | break; |
865 | default: |
866 | csvn = none; |
867 | } |
868 | |
869 | /* Determine model-specific counter set(s) */ |
870 | get_cpu_id(&cpu_id); |
871 | switch (cpu_id.machine) { |
872 | case 0x2097: |
873 | case 0x2098: |
874 | model = cpumcf_z10_pmu_event_attr; |
875 | break; |
876 | case 0x2817: |
877 | case 0x2818: |
878 | model = cpumcf_z196_pmu_event_attr; |
879 | break; |
880 | case 0x2827: |
881 | case 0x2828: |
882 | model = cpumcf_zec12_pmu_event_attr; |
883 | break; |
884 | case 0x2964: |
885 | case 0x2965: |
886 | model = cpumcf_z13_pmu_event_attr; |
887 | break; |
888 | case 0x3906: |
889 | case 0x3907: |
890 | model = cpumcf_z14_pmu_event_attr; |
891 | break; |
892 | case 0x8561: |
893 | case 0x8562: |
894 | model = cpumcf_z15_pmu_event_attr; |
895 | break; |
896 | case 0x3931: |
897 | case 0x3932: |
898 | model = cpumcf_z16_pmu_event_attr; |
899 | break; |
900 | default: |
901 | model = none; |
902 | break; |
903 | } |
904 | |
905 | combined = merge_attr(a: cfvn, b: csvn, c: model); |
906 | if (combined) |
907 | cpumcf_pmu_events_group.attrs = combined; |
908 | return cpumcf_pmu_attr_groups; |
909 | } |
910 | |