1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * trampoline.S: SMP cpu boot-up trampoline code. |
4 | * |
5 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) |
6 | * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) |
7 | */ |
8 | |
9 | #include <asm/head.h> |
10 | #include <asm/psr.h> |
11 | #include <asm/page.h> |
12 | #include <asm/asi.h> |
13 | #include <asm/ptrace.h> |
14 | #include <asm/vaddrs.h> |
15 | #include <asm/contregs.h> |
16 | #include <asm/thread_info.h> |
17 | |
18 | .globl sun4m_cpu_startup |
19 | .globl sun4d_cpu_startup |
20 | |
21 | .align 4 |
22 | |
23 | /* When we start up a cpu for the first time it enters this routine. |
24 | * This initializes the chip from whatever state the prom left it |
25 | * in and sets PIL in %psr to 15, no irqs. |
26 | */ |
27 | |
28 | sun4m_cpu_startup: |
29 | cpu1_startup: |
30 | sethi %hi(trapbase_cpu1), %g3 |
31 | b 1f |
32 | or %g3, %lo(trapbase_cpu1), %g3 |
33 | |
34 | cpu2_startup: |
35 | sethi %hi(trapbase_cpu2), %g3 |
36 | b 1f |
37 | or %g3, %lo(trapbase_cpu2), %g3 |
38 | |
39 | cpu3_startup: |
40 | sethi %hi(trapbase_cpu3), %g3 |
41 | b 1f |
42 | or %g3, %lo(trapbase_cpu3), %g3 |
43 | |
44 | 1: |
45 | /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */ |
46 | set (PSR_PIL | PSR_S | PSR_PS), %g1 |
47 | wr %g1, 0x0, %psr ! traps off though |
48 | WRITE_PAUSE |
49 | |
50 | /* Our %wim is one behind CWP */ |
51 | mov 2, %g1 |
52 | wr %g1, 0x0, %wim |
53 | WRITE_PAUSE |
54 | |
55 | /* This identifies "this cpu". */ |
56 | wr %g3, 0x0, %tbr |
57 | WRITE_PAUSE |
58 | |
59 | /* Give ourselves a stack and curptr. */ |
60 | set current_set, %g5 |
61 | srl %g3, 10, %g4 |
62 | and %g4, 0xc, %g4 |
63 | ld [%g5 + %g4], %g6 |
64 | |
65 | sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp |
66 | or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp |
67 | add %g6, %sp, %sp |
68 | |
69 | /* Turn on traps (PSR_ET). */ |
70 | rd %psr, %g1 |
71 | wr %g1, PSR_ET, %psr ! traps on |
72 | WRITE_PAUSE |
73 | |
74 | /* Init our caches, etc. */ |
75 | set poke_srmmu, %g5 |
76 | ld [%g5], %g5 |
77 | call %g5 |
78 | nop |
79 | |
80 | /* Start this processor. */ |
81 | call smp_callin |
82 | nop |
83 | |
84 | b,a smp_panic |
85 | |
86 | .text |
87 | .align 4 |
88 | |
89 | smp_panic: |
90 | call cpu_panic |
91 | nop |
92 | |
93 | /* CPUID in bootbus can be found at PA 0xff0140000 */ |
94 | #define SUN4D_BOOTBUS_CPUID 0xf0140000 |
95 | |
96 | .align 4 |
97 | |
98 | sun4d_cpu_startup: |
99 | /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */ |
100 | set (PSR_PIL | PSR_S | PSR_PS), %g1 |
101 | wr %g1, 0x0, %psr ! traps off though |
102 | WRITE_PAUSE |
103 | |
104 | /* Our %wim is one behind CWP */ |
105 | mov 2, %g1 |
106 | wr %g1, 0x0, %wim |
107 | WRITE_PAUSE |
108 | |
109 | /* Set tbr - we use just one trap table. */ |
110 | set trapbase, %g1 |
111 | wr %g1, 0x0, %tbr |
112 | WRITE_PAUSE |
113 | |
114 | /* Get our CPU id out of bootbus */ |
115 | set SUN4D_BOOTBUS_CPUID, %g3 |
116 | lduba [%g3] ASI_M_CTL, %g3 |
117 | and %g3, 0xf8, %g3 |
118 | srl %g3, 3, %g1 |
119 | sta %g1, [%g0] ASI_M_VIKING_TMP1 |
120 | |
121 | /* Give ourselves a stack and curptr. */ |
122 | set current_set, %g5 |
123 | srl %g3, 1, %g4 |
124 | ld [%g5 + %g4], %g6 |
125 | |
126 | sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp |
127 | or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp |
128 | add %g6, %sp, %sp |
129 | |
130 | /* Turn on traps (PSR_ET). */ |
131 | rd %psr, %g1 |
132 | wr %g1, PSR_ET, %psr ! traps on |
133 | WRITE_PAUSE |
134 | |
135 | /* Init our caches, etc. */ |
136 | set poke_srmmu, %g5 |
137 | ld [%g5], %g5 |
138 | call %g5 |
139 | nop |
140 | |
141 | /* Start this processor. */ |
142 | call smp_callin |
143 | nop |
144 | |
145 | b,a smp_panic |
146 | |
147 | .align 4 |
148 | .global leon_smp_cpu_startup, smp_penguin_ctable |
149 | |
150 | leon_smp_cpu_startup: |
151 | |
152 | set smp_penguin_ctable,%g1 |
153 | ld [%g1+4],%g1 |
154 | srl %g1,4,%g1 |
155 | set 0x00000100,%g5 /* SRMMU_CTXTBL_PTR */ |
156 | sta %g1, [%g5] ASI_LEON_MMUREGS |
157 | |
158 | /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */ |
159 | set (PSR_PIL | PSR_S | PSR_PS), %g1 |
160 | wr %g1, 0x0, %psr ! traps off though |
161 | WRITE_PAUSE |
162 | |
163 | /* Our %wim is one behind CWP */ |
164 | mov 2, %g1 |
165 | wr %g1, 0x0, %wim |
166 | WRITE_PAUSE |
167 | |
168 | /* Set tbr - we use just one trap table. */ |
169 | set trapbase, %g1 |
170 | wr %g1, 0x0, %tbr |
171 | WRITE_PAUSE |
172 | |
173 | /* Get our CPU id */ |
174 | rd %asr17,%g3 |
175 | |
176 | /* Give ourselves a stack and curptr. */ |
177 | set current_set, %g5 |
178 | srl %g3, 28, %g4 |
179 | sll %g4, 2, %g4 |
180 | ld [%g5 + %g4], %g6 |
181 | |
182 | sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp |
183 | or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp |
184 | add %g6, %sp, %sp |
185 | |
186 | /* Turn on traps (PSR_ET). */ |
187 | rd %psr, %g1 |
188 | wr %g1, PSR_ET, %psr ! traps on |
189 | WRITE_PAUSE |
190 | |
191 | /* Init our caches, etc. */ |
192 | set poke_srmmu, %g5 |
193 | ld [%g5], %g5 |
194 | call %g5 |
195 | nop |
196 | |
197 | /* Start this processor. */ |
198 | call smp_callin |
199 | nop |
200 | |
201 | b,a smp_panic |
202 | |