| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* winfixup.S: Handle cases where user stack pointer is found to be bogus. |
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| 3 | * |
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| 4 | * Copyright (C) 1997, 2006 David S. Miller (davem@davemloft.net) |
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| 5 | */ |
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| 6 | |
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| 7 | #include <asm/asi.h> |
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| 8 | #include <asm/head.h> |
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| 9 | #include <asm/page.h> |
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| 10 | #include <asm/ptrace.h> |
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| 11 | #include <asm/processor.h> |
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| 12 | #include <asm/spitfire.h> |
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| 13 | #include <asm/thread_info.h> |
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| 14 | |
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| 15 | .text |
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| 16 | |
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| 17 | /* It used to be the case that these register window fault |
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| 18 | * handlers could run via the save and restore instructions |
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| 19 | * done by the trap entry and exit code. They now do the |
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| 20 | * window spill/fill by hand, so that case no longer can occur. |
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| 21 | */ |
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| 22 | |
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| 23 | .align 32 |
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| 24 | fill_fixup: |
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| 25 | TRAP_LOAD_THREAD_REG(%g6, %g1) |
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| 26 | rdpr %tstate, %g1 |
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| 27 | and %g1, TSTATE_CWP, %g1 |
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| 28 | or %g4, FAULT_CODE_WINFIXUP, %g4 |
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| 29 | stb %g4, [%g6 + TI_FAULT_CODE] |
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| 30 | stx %g5, [%g6 + TI_FAULT_ADDR] |
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| 31 | wrpr %g1, %cwp |
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| 32 | ba,pt %xcc, etrap |
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| 33 | rd %pc, %g7 |
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| 34 | call do_sparc64_fault |
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| 35 | add %sp, PTREGS_OFF, %o0 |
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| 36 | ba,a,pt %xcc, rtrap |
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| 37 | |
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| 38 | /* Be very careful about usage of the trap globals here. |
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| 39 | * You cannot touch %g5 as that has the fault information. |
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| 40 | */ |
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| 41 | spill_fixup: |
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| 42 | spill_fixup_mna: |
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| 43 | spill_fixup_dax: |
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| 44 | TRAP_LOAD_THREAD_REG(%g6, %g1) |
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| 45 | ldx [%g6 + TI_FLAGS], %g1 |
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| 46 | andcc %sp, 0x1, %g0 |
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| 47 | movne %icc, 0, %g1 |
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| 48 | andcc %g1, _TIF_32BIT, %g0 |
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| 49 | ldub [%g6 + TI_WSAVED], %g1 |
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| 50 | sll %g1, 3, %g3 |
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| 51 | add %g6, %g3, %g3 |
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| 52 | stx %sp, [%g3 + TI_RWIN_SPTRS] |
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| 53 | sll %g1, 7, %g3 |
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| 54 | bne,pt %xcc, 1f |
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| 55 | add %g6, %g3, %g3 |
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| 56 | stx %l0, [%g3 + TI_REG_WINDOW + 0x00] |
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| 57 | stx %l1, [%g3 + TI_REG_WINDOW + 0x08] |
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| 58 | stx %l2, [%g3 + TI_REG_WINDOW + 0x10] |
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| 59 | stx %l3, [%g3 + TI_REG_WINDOW + 0x18] |
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| 60 | stx %l4, [%g3 + TI_REG_WINDOW + 0x20] |
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| 61 | stx %l5, [%g3 + TI_REG_WINDOW + 0x28] |
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| 62 | stx %l6, [%g3 + TI_REG_WINDOW + 0x30] |
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| 63 | stx %l7, [%g3 + TI_REG_WINDOW + 0x38] |
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| 64 | stx %i0, [%g3 + TI_REG_WINDOW + 0x40] |
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| 65 | stx %i1, [%g3 + TI_REG_WINDOW + 0x48] |
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| 66 | stx %i2, [%g3 + TI_REG_WINDOW + 0x50] |
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| 67 | stx %i3, [%g3 + TI_REG_WINDOW + 0x58] |
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| 68 | stx %i4, [%g3 + TI_REG_WINDOW + 0x60] |
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| 69 | stx %i5, [%g3 + TI_REG_WINDOW + 0x68] |
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| 70 | stx %i6, [%g3 + TI_REG_WINDOW + 0x70] |
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| 71 | ba,pt %xcc, 2f |
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| 72 | stx %i7, [%g3 + TI_REG_WINDOW + 0x78] |
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| 73 | 1: stw %l0, [%g3 + TI_REG_WINDOW + 0x00] |
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| 74 | stw %l1, [%g3 + TI_REG_WINDOW + 0x04] |
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| 75 | stw %l2, [%g3 + TI_REG_WINDOW + 0x08] |
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| 76 | stw %l3, [%g3 + TI_REG_WINDOW + 0x0c] |
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| 77 | stw %l4, [%g3 + TI_REG_WINDOW + 0x10] |
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| 78 | stw %l5, [%g3 + TI_REG_WINDOW + 0x14] |
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| 79 | stw %l6, [%g3 + TI_REG_WINDOW + 0x18] |
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| 80 | stw %l7, [%g3 + TI_REG_WINDOW + 0x1c] |
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| 81 | stw %i0, [%g3 + TI_REG_WINDOW + 0x20] |
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| 82 | stw %i1, [%g3 + TI_REG_WINDOW + 0x24] |
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| 83 | stw %i2, [%g3 + TI_REG_WINDOW + 0x28] |
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| 84 | stw %i3, [%g3 + TI_REG_WINDOW + 0x2c] |
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| 85 | stw %i4, [%g3 + TI_REG_WINDOW + 0x30] |
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| 86 | stw %i5, [%g3 + TI_REG_WINDOW + 0x34] |
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| 87 | stw %i6, [%g3 + TI_REG_WINDOW + 0x38] |
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| 88 | stw %i7, [%g3 + TI_REG_WINDOW + 0x3c] |
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| 89 | 2: add %g1, 1, %g1 |
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| 90 | stb %g1, [%g6 + TI_WSAVED] |
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| 91 | rdpr %tstate, %g1 |
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| 92 | andcc %g1, TSTATE_PRIV, %g0 |
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| 93 | saved |
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| 94 | be,pn %xcc, 1f |
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| 95 | and %g1, TSTATE_CWP, %g1 |
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| 96 | retry |
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| 97 | 1: mov FAULT_CODE_WRITE | FAULT_CODE_DTLB | FAULT_CODE_WINFIXUP, %g4 |
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| 98 | stb %g4, [%g6 + TI_FAULT_CODE] |
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| 99 | stx %g5, [%g6 + TI_FAULT_ADDR] |
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| 100 | wrpr %g1, %cwp |
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| 101 | ba,pt %xcc, etrap |
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| 102 | rd %pc, %g7 |
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| 103 | call do_sparc64_fault |
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| 104 | add %sp, PTREGS_OFF, %o0 |
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| 105 | ba,a,pt %xcc, rtrap |
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| 106 | |
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| 107 | winfix_mna: |
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| 108 | andn %g3, 0x7f, %g3 |
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| 109 | add %g3, 0x78, %g3 |
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| 110 | wrpr %g3, %tnpc |
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| 111 | done |
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| 112 | |
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| 113 | fill_fixup_mna: |
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| 114 | rdpr %tstate, %g1 |
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| 115 | and %g1, TSTATE_CWP, %g1 |
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| 116 | wrpr %g1, %cwp |
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| 117 | ba,pt %xcc, etrap |
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| 118 | rd %pc, %g7 |
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| 119 | sethi %hi(tlb_type), %g1 |
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| 120 | lduw [%g1 + %lo(tlb_type)], %g1 |
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| 121 | cmp %g1, 3 |
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| 122 | bne,pt %icc, 1f |
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| 123 | add %sp, PTREGS_OFF, %o0 |
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| 124 | mov %l4, %o2 |
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| 125 | call sun4v_do_mna |
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| 126 | mov %l5, %o1 |
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| 127 | ba,a,pt %xcc, rtrap |
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| 128 | 1: mov %l4, %o1 |
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| 129 | mov %l5, %o2 |
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| 130 | call mem_address_unaligned |
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| 131 | nop |
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| 132 | ba,a,pt %xcc, rtrap |
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| 133 | |
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| 134 | winfix_dax: |
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| 135 | andn %g3, 0x7f, %g3 |
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| 136 | add %g3, 0x74, %g3 |
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| 137 | wrpr %g3, %tnpc |
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| 138 | done |
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| 139 | |
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| 140 | fill_fixup_dax: |
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| 141 | rdpr %tstate, %g1 |
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| 142 | and %g1, TSTATE_CWP, %g1 |
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| 143 | wrpr %g1, %cwp |
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| 144 | ba,pt %xcc, etrap |
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| 145 | rd %pc, %g7 |
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| 146 | sethi %hi(tlb_type), %g1 |
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| 147 | mov %l4, %o1 |
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| 148 | lduw [%g1 + %lo(tlb_type)], %g1 |
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| 149 | mov %l5, %o2 |
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| 150 | cmp %g1, 3 |
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| 151 | bne,pt %icc, 1f |
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| 152 | add %sp, PTREGS_OFF, %o0 |
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| 153 | call sun4v_data_access_exception |
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| 154 | nop |
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| 155 | ba,a,pt %xcc, rtrap |
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| 156 | nop |
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| 157 | 1: call spitfire_data_access_exception |
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| 158 | nop |
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| 159 | ba,a,pt %xcc, rtrap |
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| 160 | nop |
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| 161 | |
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