| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * VISsave.S: Code for saving FPU register state for |
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| 4 | * VIS routines. One should not call this directly, |
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| 5 | * but use macros provided in <asm/visasm.h>. |
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| 6 | * |
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| 7 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) |
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| 8 | */ |
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| 9 | |
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| 10 | #include <linux/export.h> |
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| 11 | #include <linux/linkage.h> |
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| 12 | |
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| 13 | #include <asm/asi.h> |
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| 14 | #include <asm/page.h> |
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| 15 | #include <asm/ptrace.h> |
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| 16 | #include <asm/visasm.h> |
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| 17 | #include <asm/thread_info.h> |
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| 18 | |
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| 19 | /* On entry: %o5=current FPRS value, %g7 is callers address */ |
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| 20 | /* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */ |
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| 21 | |
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| 22 | /* Nothing special need be done here to handle pre-emption, this |
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| 23 | * FPU save/restore mechanism is already preemption safe. |
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| 24 | */ |
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| 25 | .text |
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| 26 | .align 32 |
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| 27 | ENTRY(VISenter) |
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| 28 | ldub [%g6 + TI_FPDEPTH], %g1 |
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| 29 | brnz,a,pn %g1, 1f |
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| 30 | cmp %g1, 1 |
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| 31 | stb %g0, [%g6 + TI_FPSAVED] |
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| 32 | stx %fsr, [%g6 + TI_XFSR] |
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| 33 | 9: jmpl %g7 + %g0, %g0 |
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| 34 | nop |
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| 35 | 1: bne,pn %icc, 2f |
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| 36 | |
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| 37 | srl %g1, 1, %g1 |
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| 38 | vis1: ldub [%g6 + TI_FPSAVED], %g3 |
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| 39 | stx %fsr, [%g6 + TI_XFSR] |
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| 40 | or %g3, %o5, %g3 |
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| 41 | stb %g3, [%g6 + TI_FPSAVED] |
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| 42 | rd %gsr, %g3 |
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| 43 | clr %g1 |
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| 44 | ba,pt %xcc, 3f |
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| 45 | |
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| 46 | stx %g3, [%g6 + TI_GSR] |
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| 47 | 2: add %g6, %g1, %g3 |
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| 48 | mov FPRS_DU | FPRS_DL | FPRS_FEF, %o5 |
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| 49 | sll %g1, 3, %g1 |
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| 50 | stb %o5, [%g3 + TI_FPSAVED] |
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| 51 | rd %gsr, %g2 |
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| 52 | add %g6, %g1, %g3 |
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| 53 | stx %g2, [%g3 + TI_GSR] |
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| 54 | |
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| 55 | add %g6, %g1, %g2 |
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| 56 | stx %fsr, [%g2 + TI_XFSR] |
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| 57 | sll %g1, 5, %g1 |
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| 58 | 3: andcc %o5, FPRS_DL|FPRS_DU, %g0 |
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| 59 | be,pn %icc, 9b |
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| 60 | add %g6, TI_FPREGS, %g2 |
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| 61 | andcc %o5, FPRS_DL, %g0 |
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| 62 | |
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| 63 | be,pn %icc, 4f |
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| 64 | add %g6, TI_FPREGS+0x40, %g3 |
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| 65 | membar #Sync |
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| 66 | stda %f0, [%g2 + %g1] ASI_BLK_P |
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| 67 | stda %f16, [%g3 + %g1] ASI_BLK_P |
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| 68 | membar #Sync |
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| 69 | andcc %o5, FPRS_DU, %g0 |
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| 70 | be,pn %icc, 5f |
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| 71 | 4: add %g1, 128, %g1 |
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| 72 | membar #Sync |
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| 73 | stda %f32, [%g2 + %g1] ASI_BLK_P |
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| 74 | |
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| 75 | stda %f48, [%g3 + %g1] ASI_BLK_P |
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| 76 | 5: membar #Sync |
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| 77 | ba,pt %xcc, 80f |
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| 78 | nop |
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| 79 | |
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| 80 | .align 32 |
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| 81 | 80: jmpl %g7 + %g0, %g0 |
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| 82 | nop |
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| 83 | ENDPROC(VISenter) |
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| 84 | EXPORT_SYMBOL(VISenter) |
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| 85 | |
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