1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * swift.S: MicroSparc-II mmu/cache operations. |
4 | * |
5 | * Copyright (C) 1999 David S. Miller (davem@redhat.com) |
6 | */ |
7 | |
8 | #include <asm/psr.h> |
9 | #include <asm/asi.h> |
10 | #include <asm/page.h> |
11 | #include <asm/pgtsrmmu.h> |
12 | #include <asm/asm-offsets.h> |
13 | |
14 | .text |
15 | .align 4 |
16 | |
17 | #if 1 /* XXX screw this, I can't get the VAC flushes working |
18 | * XXX reliably... -DaveM |
19 | */ |
20 | .globl swift_flush_cache_all, swift_flush_cache_mm |
21 | .globl swift_flush_cache_range, swift_flush_cache_page |
22 | .globl swift_flush_page_for_dma |
23 | .globl swift_flush_page_to_ram |
24 | |
25 | swift_flush_cache_all: |
26 | swift_flush_cache_mm: |
27 | swift_flush_cache_range: |
28 | swift_flush_cache_page: |
29 | swift_flush_page_for_dma: |
30 | swift_flush_page_to_ram: |
31 | sethi %hi(0x2000), %o0 |
32 | 1: subcc %o0, 0x10, %o0 |
33 | add %o0, %o0, %o1 |
34 | sta %g0, [%o0] ASI_M_DATAC_TAG |
35 | bne 1b |
36 | sta %g0, [%o1] ASI_M_TXTC_TAG |
37 | retl |
38 | nop |
39 | #else |
40 | |
41 | .globl swift_flush_cache_all |
42 | swift_flush_cache_all: |
43 | WINDOW_FLUSH(%g4, %g5) |
44 | |
45 | /* Just clear out all the tags. */ |
46 | sethi %hi(16 * 1024), %o0 |
47 | 1: subcc %o0, 16, %o0 |
48 | sta %g0, [%o0] ASI_M_TXTC_TAG |
49 | bne 1b |
50 | sta %g0, [%o0] ASI_M_DATAC_TAG |
51 | retl |
52 | nop |
53 | |
54 | .globl swift_flush_cache_mm |
55 | swift_flush_cache_mm: |
56 | ld [%o0 + AOFF_mm_context], %g2 |
57 | cmp %g2, -1 |
58 | be swift_flush_cache_mm_out |
59 | WINDOW_FLUSH(%g4, %g5) |
60 | rd %psr, %g1 |
61 | andn %g1, PSR_ET, %g3 |
62 | wr %g3, 0x0, %psr |
63 | nop |
64 | nop |
65 | mov SRMMU_CTX_REG, %g7 |
66 | lda [%g7] ASI_M_MMUREGS, %g5 |
67 | sta %g2, [%g7] ASI_M_MMUREGS |
68 | |
69 | #if 1 |
70 | sethi %hi(0x2000), %o0 |
71 | 1: subcc %o0, 0x10, %o0 |
72 | sta %g0, [%o0] ASI_M_FLUSH_CTX |
73 | bne 1b |
74 | nop |
75 | #else |
76 | clr %o0 |
77 | or %g0, 2048, %g7 |
78 | or %g0, 2048, %o1 |
79 | add %o1, 2048, %o2 |
80 | add %o2, 2048, %o3 |
81 | mov 16, %o4 |
82 | add %o4, 2048, %o5 |
83 | add %o5, 2048, %g2 |
84 | add %g2, 2048, %g3 |
85 | 1: sta %g0, [%o0 ] ASI_M_FLUSH_CTX |
86 | sta %g0, [%o0 + %o1] ASI_M_FLUSH_CTX |
87 | sta %g0, [%o0 + %o2] ASI_M_FLUSH_CTX |
88 | sta %g0, [%o0 + %o3] ASI_M_FLUSH_CTX |
89 | sta %g0, [%o0 + %o4] ASI_M_FLUSH_CTX |
90 | sta %g0, [%o0 + %o5] ASI_M_FLUSH_CTX |
91 | sta %g0, [%o0 + %g2] ASI_M_FLUSH_CTX |
92 | sta %g0, [%o0 + %g3] ASI_M_FLUSH_CTX |
93 | subcc %g7, 32, %g7 |
94 | bne 1b |
95 | add %o0, 32, %o0 |
96 | #endif |
97 | |
98 | mov SRMMU_CTX_REG, %g7 |
99 | sta %g5, [%g7] ASI_M_MMUREGS |
100 | wr %g1, 0x0, %psr |
101 | nop |
102 | nop |
103 | swift_flush_cache_mm_out: |
104 | retl |
105 | nop |
106 | |
107 | .globl swift_flush_cache_range |
108 | swift_flush_cache_range: |
109 | ld [%o0 + VMA_VM_MM], %o0 |
110 | sub %o2, %o1, %o2 |
111 | sethi %hi(4096), %o3 |
112 | cmp %o2, %o3 |
113 | bgu swift_flush_cache_mm |
114 | nop |
115 | b 70f |
116 | nop |
117 | |
118 | .globl swift_flush_cache_page |
119 | swift_flush_cache_page: |
120 | ld [%o0 + VMA_VM_MM], %o0 |
121 | 70: |
122 | ld [%o0 + AOFF_mm_context], %g2 |
123 | cmp %g2, -1 |
124 | be swift_flush_cache_page_out |
125 | WINDOW_FLUSH(%g4, %g5) |
126 | rd %psr, %g1 |
127 | andn %g1, PSR_ET, %g3 |
128 | wr %g3, 0x0, %psr |
129 | nop |
130 | nop |
131 | mov SRMMU_CTX_REG, %g7 |
132 | lda [%g7] ASI_M_MMUREGS, %g5 |
133 | sta %g2, [%g7] ASI_M_MMUREGS |
134 | |
135 | andn %o1, (PAGE_SIZE - 1), %o1 |
136 | #if 1 |
137 | sethi %hi(0x1000), %o0 |
138 | 1: subcc %o0, 0x10, %o0 |
139 | sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE |
140 | bne 1b |
141 | nop |
142 | #else |
143 | or %g0, 512, %g7 |
144 | or %g0, 512, %o0 |
145 | add %o0, 512, %o2 |
146 | add %o2, 512, %o3 |
147 | add %o3, 512, %o4 |
148 | add %o4, 512, %o5 |
149 | add %o5, 512, %g3 |
150 | add %g3, 512, %g4 |
151 | 1: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE |
152 | sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE |
153 | sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE |
154 | sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE |
155 | sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE |
156 | sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE |
157 | sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE |
158 | sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE |
159 | subcc %g7, 16, %g7 |
160 | bne 1b |
161 | add %o1, 16, %o1 |
162 | #endif |
163 | |
164 | mov SRMMU_CTX_REG, %g7 |
165 | sta %g5, [%g7] ASI_M_MMUREGS |
166 | wr %g1, 0x0, %psr |
167 | nop |
168 | nop |
169 | swift_flush_cache_page_out: |
170 | retl |
171 | nop |
172 | |
173 | /* Swift is write-thru, however it is not |
174 | * I/O nor TLB-walk coherent. Also it has |
175 | * caches which are virtually indexed and tagged. |
176 | */ |
177 | .globl swift_flush_page_for_dma |
178 | .globl swift_flush_page_to_ram |
179 | swift_flush_page_for_dma: |
180 | swift_flush_page_to_ram: |
181 | andn %o0, (PAGE_SIZE - 1), %o1 |
182 | #if 1 |
183 | sethi %hi(0x1000), %o0 |
184 | 1: subcc %o0, 0x10, %o0 |
185 | sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE |
186 | bne 1b |
187 | nop |
188 | #else |
189 | or %g0, 512, %g7 |
190 | or %g0, 512, %o0 |
191 | add %o0, 512, %o2 |
192 | add %o2, 512, %o3 |
193 | add %o3, 512, %o4 |
194 | add %o4, 512, %o5 |
195 | add %o5, 512, %g3 |
196 | add %g3, 512, %g4 |
197 | 1: sta %g0, [%o1 ] ASI_M_FLUSH_PAGE |
198 | sta %g0, [%o1 + %o0] ASI_M_FLUSH_PAGE |
199 | sta %g0, [%o1 + %o2] ASI_M_FLUSH_PAGE |
200 | sta %g0, [%o1 + %o3] ASI_M_FLUSH_PAGE |
201 | sta %g0, [%o1 + %o4] ASI_M_FLUSH_PAGE |
202 | sta %g0, [%o1 + %o5] ASI_M_FLUSH_PAGE |
203 | sta %g0, [%o1 + %g3] ASI_M_FLUSH_PAGE |
204 | sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE |
205 | subcc %g7, 16, %g7 |
206 | bne 1b |
207 | add %o1, 16, %o1 |
208 | #endif |
209 | retl |
210 | nop |
211 | #endif |
212 | |
213 | .globl swift_flush_sig_insns |
214 | swift_flush_sig_insns: |
215 | flush %o1 |
216 | retl |
217 | flush %o1 + 4 |
218 | |
219 | .globl swift_flush_tlb_mm |
220 | .globl swift_flush_tlb_range |
221 | .globl swift_flush_tlb_all |
222 | swift_flush_tlb_range: |
223 | ld [%o0 + VMA_VM_MM], %o0 |
224 | swift_flush_tlb_mm: |
225 | ld [%o0 + AOFF_mm_context], %g2 |
226 | cmp %g2, -1 |
227 | be swift_flush_tlb_all_out |
228 | swift_flush_tlb_all: |
229 | mov 0x400, %o1 |
230 | sta %g0, [%o1] ASI_M_FLUSH_PROBE |
231 | swift_flush_tlb_all_out: |
232 | retl |
233 | nop |
234 | |
235 | .globl swift_flush_tlb_page |
236 | swift_flush_tlb_page: |
237 | ld [%o0 + VMA_VM_MM], %o0 |
238 | mov SRMMU_CTX_REG, %g1 |
239 | ld [%o0 + AOFF_mm_context], %o3 |
240 | andn %o1, (PAGE_SIZE - 1), %o1 |
241 | cmp %o3, -1 |
242 | be swift_flush_tlb_page_out |
243 | nop |
244 | #if 1 |
245 | mov 0x400, %o1 |
246 | sta %g0, [%o1] ASI_M_FLUSH_PROBE |
247 | #else |
248 | lda [%g1] ASI_M_MMUREGS, %g5 |
249 | sta %o3, [%g1] ASI_M_MMUREGS |
250 | sta %g0, [%o1] ASI_M_FLUSH_PAGE /* rem. virt. cache. prot. */ |
251 | sta %g0, [%o1] ASI_M_FLUSH_PROBE |
252 | sta %g5, [%g1] ASI_M_MMUREGS |
253 | #endif |
254 | swift_flush_tlb_page_out: |
255 | retl |
256 | nop |
257 | |