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| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
|---|---|
| 2 | #ifndef _ASM_X86_AGP_H |
| 3 | #define _ASM_X86_AGP_H |
| 4 | |
| 5 | #include <linux/pgtable.h> |
| 6 | #include <asm/cacheflush.h> |
| 7 | |
| 8 | /* |
| 9 | * Functions to keep the agpgart mappings coherent with the MMU. The |
| 10 | * GART gives the CPU a physical alias of pages in memory. The alias |
| 11 | * region is mapped uncacheable. Make sure there are no conflicting |
| 12 | * mappings with different cacheability attributes for the same |
| 13 | * page. This avoids data corruption on some CPUs. |
| 14 | */ |
| 15 | |
| 16 | #define map_page_into_agp(page) set_pages_uc(page, 1) |
| 17 | #define unmap_page_from_agp(page) set_pages_wb(page, 1) |
| 18 | |
| 19 | /* |
| 20 | * Could use CLFLUSH here if the cpu supports it. But then it would |
| 21 | * need to be called for each cacheline of the whole page so it may |
| 22 | * not be worth it. Would need a page for it. |
| 23 | */ |
| 24 | #define flush_agp_cache() wbinvd() |
| 25 | |
| 26 | #endif /* _ASM_X86_AGP_H */ |
| 27 |
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