1/* SPDX-License-Identifier: GPL-2.0 */
2
3/*
4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional
5 * Specification (TLFS):
6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7 */
8
9#ifndef _ASM_X86_HYPERV_TLFS_H
10#define _ASM_X86_HYPERV_TLFS_H
11
12#include <linux/types.h>
13#include <asm/page.h>
14/*
15 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
16 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures).
17 */
18#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
19#define HYPERV_CPUID_INTERFACE 0x40000001
20#define HYPERV_CPUID_VERSION 0x40000002
21#define HYPERV_CPUID_FEATURES 0x40000003
22#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004
23#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005
24#define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007
25#define HYPERV_CPUID_NESTED_FEATURES 0x4000000A
26#define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C
27
28#define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081
29#define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */
30
31#define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082
32/* Support for the extended IOAPIC RTE format */
33#define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2)
34
35#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000
36#define HYPERV_CPUID_MIN 0x40000005
37#define HYPERV_CPUID_MAX 0x4000ffff
38
39/*
40 * Group D Features. The bit assignments are custom to each architecture.
41 * On x86/x64 these are HYPERV_CPUID_FEATURES.EDX bits.
42 */
43/* The MWAIT instruction is available (per section MONITOR / MWAIT) */
44#define HV_X64_MWAIT_AVAILABLE BIT(0)
45/* Guest debugging support is available */
46#define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1)
47/* Performance Monitor support is available*/
48#define HV_X64_PERF_MONITOR_AVAILABLE BIT(2)
49/* Support for physical CPU dynamic partitioning events is available*/
50#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3)
51/*
52 * Support for passing hypercall input parameter block via XMM
53 * registers is available
54 */
55#define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4)
56/* Support for a virtual guest idle state is available */
57#define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5)
58/* Frequency MSRs available */
59#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8)
60/* Crash MSR available */
61#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10)
62/* Support for debug MSRs available */
63#define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11)
64/* Support for extended gva ranges for flush hypercalls available */
65#define HV_FEATURE_EXT_GVA_RANGES_FLUSH BIT(14)
66/*
67 * Support for returning hypercall output block via XMM
68 * registers is available
69 */
70#define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15)
71/* stimer Direct Mode is available */
72#define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19)
73
74/*
75 * Implementation recommendations. Indicates which behaviors the hypervisor
76 * recommends the OS implement for optimal performance.
77 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits.
78 */
79/*
80 * Recommend using hypercall for address space switches rather
81 * than MOV to CR3 instruction
82 */
83#define HV_X64_AS_SWITCH_RECOMMENDED BIT(0)
84/* Recommend using hypercall for local TLB flushes rather
85 * than INVLPG or MOV to CR3 instructions */
86#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1)
87/*
88 * Recommend using hypercall for remote TLB flushes rather
89 * than inter-processor interrupts
90 */
91#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2)
92/*
93 * Recommend using MSRs for accessing APIC registers
94 * EOI, ICR and TPR rather than their memory-mapped counterparts
95 */
96#define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3)
97/* Recommend using the hypervisor-provided MSR to initiate a system RESET */
98#define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4)
99/*
100 * Recommend using relaxed timing for this partition. If used,
101 * the VM should disable any watchdog timeouts that rely on the
102 * timely delivery of external interrupts
103 */
104#define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5)
105
106/*
107 * Recommend not using Auto End-Of-Interrupt feature
108 */
109#define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9)
110
111/*
112 * Recommend using cluster IPI hypercalls.
113 */
114#define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10)
115
116/* Recommend using the newer ExProcessorMasks interface */
117#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11)
118
119/* Indicates that the hypervisor is nested within a Hyper-V partition. */
120#define HV_X64_HYPERV_NESTED BIT(12)
121
122/* Recommend using enlightened VMCS */
123#define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14)
124
125/* Use hypercalls for MMIO config space access */
126#define HV_X64_USE_MMIO_HYPERCALLS BIT(21)
127
128/*
129 * CPU management features identification.
130 * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits.
131 */
132#define HV_X64_START_LOGICAL_PROCESSOR BIT(0)
133#define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1)
134#define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2)
135#define HV_X64_RESERVED_IDENTITY_BIT BIT(31)
136
137/*
138 * Virtual processor will never share a physical core with another virtual
139 * processor, except for virtual processors that are reported as sibling SMT
140 * threads.
141 */
142#define HV_X64_NO_NONARCH_CORESHARING BIT(18)
143
144/* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */
145#define HV_X64_NESTED_DIRECT_FLUSH BIT(17)
146#define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18)
147#define HV_X64_NESTED_MSR_BITMAP BIT(19)
148
149/* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */
150#define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL BIT(0)
151
152/*
153 * This is specific to AMD and specifies that enlightened TLB flush is
154 * supported. If guest opts in to this feature, ASID invalidations only
155 * flushes gva -> hpa mapping entries. To flush the TLB entries derived
156 * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace
157 * or HvFlushGuestPhysicalAddressList).
158 */
159#define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22)
160
161/* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */
162#define HV_PARAVISOR_PRESENT BIT(0)
163
164/* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */
165#define HV_ISOLATION_TYPE GENMASK(3, 0)
166#define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5)
167#define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6)
168
169enum hv_isolation_type {
170 HV_ISOLATION_TYPE_NONE = 0,
171 HV_ISOLATION_TYPE_VBS = 1,
172 HV_ISOLATION_TYPE_SNP = 2,
173 HV_ISOLATION_TYPE_TDX = 3
174};
175
176/* Hyper-V specific model specific registers (MSRs) */
177
178/* MSR used to identify the guest OS. */
179#define HV_X64_MSR_GUEST_OS_ID 0x40000000
180
181/* MSR used to setup pages used to communicate with the hypervisor. */
182#define HV_X64_MSR_HYPERCALL 0x40000001
183
184/* MSR used to provide vcpu index */
185#define HV_REGISTER_VP_INDEX 0x40000002
186
187/* MSR used to reset the guest OS. */
188#define HV_X64_MSR_RESET 0x40000003
189
190/* MSR used to provide vcpu runtime in 100ns units */
191#define HV_X64_MSR_VP_RUNTIME 0x40000010
192
193/* MSR used to read the per-partition time reference counter */
194#define HV_REGISTER_TIME_REF_COUNT 0x40000020
195
196/* A partition's reference time stamp counter (TSC) page */
197#define HV_REGISTER_REFERENCE_TSC 0x40000021
198
199/* MSR used to retrieve the TSC frequency */
200#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
201
202/* MSR used to retrieve the local APIC timer frequency */
203#define HV_X64_MSR_APIC_FREQUENCY 0x40000023
204
205/* Define the virtual APIC registers */
206#define HV_X64_MSR_EOI 0x40000070
207#define HV_X64_MSR_ICR 0x40000071
208#define HV_X64_MSR_TPR 0x40000072
209#define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073
210
211/* Define synthetic interrupt controller model specific registers. */
212#define HV_REGISTER_SCONTROL 0x40000080
213#define HV_REGISTER_SVERSION 0x40000081
214#define HV_REGISTER_SIEFP 0x40000082
215#define HV_REGISTER_SIMP 0x40000083
216#define HV_REGISTER_EOM 0x40000084
217#define HV_REGISTER_SINT0 0x40000090
218#define HV_REGISTER_SINT1 0x40000091
219#define HV_REGISTER_SINT2 0x40000092
220#define HV_REGISTER_SINT3 0x40000093
221#define HV_REGISTER_SINT4 0x40000094
222#define HV_REGISTER_SINT5 0x40000095
223#define HV_REGISTER_SINT6 0x40000096
224#define HV_REGISTER_SINT7 0x40000097
225#define HV_REGISTER_SINT8 0x40000098
226#define HV_REGISTER_SINT9 0x40000099
227#define HV_REGISTER_SINT10 0x4000009A
228#define HV_REGISTER_SINT11 0x4000009B
229#define HV_REGISTER_SINT12 0x4000009C
230#define HV_REGISTER_SINT13 0x4000009D
231#define HV_REGISTER_SINT14 0x4000009E
232#define HV_REGISTER_SINT15 0x4000009F
233
234/*
235 * Define synthetic interrupt controller model specific registers for
236 * nested hypervisor.
237 */
238#define HV_REGISTER_NESTED_SCONTROL 0x40001080
239#define HV_REGISTER_NESTED_SVERSION 0x40001081
240#define HV_REGISTER_NESTED_SIEFP 0x40001082
241#define HV_REGISTER_NESTED_SIMP 0x40001083
242#define HV_REGISTER_NESTED_EOM 0x40001084
243#define HV_REGISTER_NESTED_SINT0 0x40001090
244
245/*
246 * Synthetic Timer MSRs. Four timers per vcpu.
247 */
248#define HV_REGISTER_STIMER0_CONFIG 0x400000B0
249#define HV_REGISTER_STIMER0_COUNT 0x400000B1
250#define HV_REGISTER_STIMER1_CONFIG 0x400000B2
251#define HV_REGISTER_STIMER1_COUNT 0x400000B3
252#define HV_REGISTER_STIMER2_CONFIG 0x400000B4
253#define HV_REGISTER_STIMER2_COUNT 0x400000B5
254#define HV_REGISTER_STIMER3_CONFIG 0x400000B6
255#define HV_REGISTER_STIMER3_COUNT 0x400000B7
256
257/* Hyper-V guest idle MSR */
258#define HV_X64_MSR_GUEST_IDLE 0x400000F0
259
260/* Hyper-V guest crash notification MSR's */
261#define HV_REGISTER_CRASH_P0 0x40000100
262#define HV_REGISTER_CRASH_P1 0x40000101
263#define HV_REGISTER_CRASH_P2 0x40000102
264#define HV_REGISTER_CRASH_P3 0x40000103
265#define HV_REGISTER_CRASH_P4 0x40000104
266#define HV_REGISTER_CRASH_CTL 0x40000105
267
268/* TSC emulation after migration */
269#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106
270#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107
271#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108
272
273/* TSC invariant control */
274#define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118
275
276/* HV_X64_MSR_TSC_INVARIANT_CONTROL bits */
277#define HV_EXPOSE_INVARIANT_TSC BIT_ULL(0)
278
279/* Register name aliases for temporary compatibility */
280#define HV_X64_MSR_STIMER0_COUNT HV_REGISTER_STIMER0_COUNT
281#define HV_X64_MSR_STIMER0_CONFIG HV_REGISTER_STIMER0_CONFIG
282#define HV_X64_MSR_STIMER1_COUNT HV_REGISTER_STIMER1_COUNT
283#define HV_X64_MSR_STIMER1_CONFIG HV_REGISTER_STIMER1_CONFIG
284#define HV_X64_MSR_STIMER2_COUNT HV_REGISTER_STIMER2_COUNT
285#define HV_X64_MSR_STIMER2_CONFIG HV_REGISTER_STIMER2_CONFIG
286#define HV_X64_MSR_STIMER3_COUNT HV_REGISTER_STIMER3_COUNT
287#define HV_X64_MSR_STIMER3_CONFIG HV_REGISTER_STIMER3_CONFIG
288#define HV_X64_MSR_SCONTROL HV_REGISTER_SCONTROL
289#define HV_X64_MSR_SVERSION HV_REGISTER_SVERSION
290#define HV_X64_MSR_SIMP HV_REGISTER_SIMP
291#define HV_X64_MSR_SIEFP HV_REGISTER_SIEFP
292#define HV_X64_MSR_VP_INDEX HV_REGISTER_VP_INDEX
293#define HV_X64_MSR_EOM HV_REGISTER_EOM
294#define HV_X64_MSR_SINT0 HV_REGISTER_SINT0
295#define HV_X64_MSR_SINT15 HV_REGISTER_SINT15
296#define HV_X64_MSR_CRASH_P0 HV_REGISTER_CRASH_P0
297#define HV_X64_MSR_CRASH_P1 HV_REGISTER_CRASH_P1
298#define HV_X64_MSR_CRASH_P2 HV_REGISTER_CRASH_P2
299#define HV_X64_MSR_CRASH_P3 HV_REGISTER_CRASH_P3
300#define HV_X64_MSR_CRASH_P4 HV_REGISTER_CRASH_P4
301#define HV_X64_MSR_CRASH_CTL HV_REGISTER_CRASH_CTL
302#define HV_X64_MSR_TIME_REF_COUNT HV_REGISTER_TIME_REF_COUNT
303#define HV_X64_MSR_REFERENCE_TSC HV_REGISTER_REFERENCE_TSC
304
305/*
306 * Registers are only accessible via HVCALL_GET_VP_REGISTERS hvcall and
307 * there is not associated MSR address.
308 */
309#define HV_X64_REGISTER_VSM_VP_STATUS 0x000D0003
310#define HV_X64_VTL_MASK GENMASK(3, 0)
311
312/* Hyper-V memory host visibility */
313enum hv_mem_host_visibility {
314 VMBUS_PAGE_NOT_VISIBLE = 0,
315 VMBUS_PAGE_VISIBLE_READ_ONLY = 1,
316 VMBUS_PAGE_VISIBLE_READ_WRITE = 3
317};
318
319/* HvCallModifySparseGpaPageHostVisibility hypercall */
320#define HV_MAX_MODIFY_GPA_REP_COUNT ((PAGE_SIZE / sizeof(u64)) - 2)
321struct hv_gpa_range_for_visibility {
322 u64 partition_id;
323 u32 host_visibility:2;
324 u32 reserved0:30;
325 u32 reserved1;
326 u64 gpa_page_list[HV_MAX_MODIFY_GPA_REP_COUNT];
327} __packed;
328
329/*
330 * Declare the MSR used to setup pages used to communicate with the hypervisor.
331 */
332union hv_x64_msr_hypercall_contents {
333 u64 as_uint64;
334 struct {
335 u64 enable:1;
336 u64 reserved:11;
337 u64 guest_physical_address:52;
338 } __packed;
339};
340
341union hv_vp_assist_msr_contents {
342 u64 as_uint64;
343 struct {
344 u64 enable:1;
345 u64 reserved:11;
346 u64 pfn:52;
347 } __packed;
348};
349
350struct hv_reenlightenment_control {
351 __u64 vector:8;
352 __u64 reserved1:8;
353 __u64 enabled:1;
354 __u64 reserved2:15;
355 __u64 target_vp:32;
356} __packed;
357
358struct hv_tsc_emulation_control {
359 __u64 enabled:1;
360 __u64 reserved:63;
361} __packed;
362
363struct hv_tsc_emulation_status {
364 __u64 inprogress:1;
365 __u64 reserved:63;
366} __packed;
367
368#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001
369#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
370#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \
371 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
372
373#define HV_X64_MSR_CRASH_PARAMS \
374 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
375
376#define HV_IPI_LOW_VECTOR 0x10
377#define HV_IPI_HIGH_VECTOR 0xff
378
379#define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001
380#define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12
381#define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \
382 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
383
384/* Hyper-V Enlightened VMCS version mask in nested features CPUID */
385#define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff
386
387#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001
388#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12
389
390/* Number of XMM registers used in hypercall input/output */
391#define HV_HYPERCALL_MAX_XMM_REGISTERS 6
392
393struct hv_nested_enlightenments_control {
394 struct {
395 __u32 directhypercall:1;
396 __u32 reserved:31;
397 } features;
398 struct {
399 __u32 inter_partition_comm:1;
400 __u32 reserved:31;
401 } hypercallControls;
402} __packed;
403
404/* Define virtual processor assist page structure. */
405struct hv_vp_assist_page {
406 __u32 apic_assist;
407 __u32 reserved1;
408 __u32 vtl_entry_reason;
409 __u32 vtl_reserved;
410 __u64 vtl_ret_x64rax;
411 __u64 vtl_ret_x64rcx;
412 struct hv_nested_enlightenments_control nested_control;
413 __u8 enlighten_vmentry;
414 __u8 reserved2[7];
415 __u64 current_nested_vmcs;
416 __u8 synthetic_time_unhalted_timer_expired;
417 __u8 reserved3[7];
418 __u8 virtualization_fault_information[40];
419 __u8 reserved4[8];
420 __u8 intercept_message[256];
421 __u8 vtl_ret_actions[256];
422} __packed;
423
424struct hv_enlightened_vmcs {
425 u32 revision_id;
426 u32 abort;
427
428 u16 host_es_selector;
429 u16 host_cs_selector;
430 u16 host_ss_selector;
431 u16 host_ds_selector;
432 u16 host_fs_selector;
433 u16 host_gs_selector;
434 u16 host_tr_selector;
435
436 u16 padding16_1;
437
438 u64 host_ia32_pat;
439 u64 host_ia32_efer;
440
441 u64 host_cr0;
442 u64 host_cr3;
443 u64 host_cr4;
444
445 u64 host_ia32_sysenter_esp;
446 u64 host_ia32_sysenter_eip;
447 u64 host_rip;
448 u32 host_ia32_sysenter_cs;
449
450 u32 pin_based_vm_exec_control;
451 u32 vm_exit_controls;
452 u32 secondary_vm_exec_control;
453
454 u64 io_bitmap_a;
455 u64 io_bitmap_b;
456 u64 msr_bitmap;
457
458 u16 guest_es_selector;
459 u16 guest_cs_selector;
460 u16 guest_ss_selector;
461 u16 guest_ds_selector;
462 u16 guest_fs_selector;
463 u16 guest_gs_selector;
464 u16 guest_ldtr_selector;
465 u16 guest_tr_selector;
466
467 u32 guest_es_limit;
468 u32 guest_cs_limit;
469 u32 guest_ss_limit;
470 u32 guest_ds_limit;
471 u32 guest_fs_limit;
472 u32 guest_gs_limit;
473 u32 guest_ldtr_limit;
474 u32 guest_tr_limit;
475 u32 guest_gdtr_limit;
476 u32 guest_idtr_limit;
477
478 u32 guest_es_ar_bytes;
479 u32 guest_cs_ar_bytes;
480 u32 guest_ss_ar_bytes;
481 u32 guest_ds_ar_bytes;
482 u32 guest_fs_ar_bytes;
483 u32 guest_gs_ar_bytes;
484 u32 guest_ldtr_ar_bytes;
485 u32 guest_tr_ar_bytes;
486
487 u64 guest_es_base;
488 u64 guest_cs_base;
489 u64 guest_ss_base;
490 u64 guest_ds_base;
491 u64 guest_fs_base;
492 u64 guest_gs_base;
493 u64 guest_ldtr_base;
494 u64 guest_tr_base;
495 u64 guest_gdtr_base;
496 u64 guest_idtr_base;
497
498 u64 padding64_1[3];
499
500 u64 vm_exit_msr_store_addr;
501 u64 vm_exit_msr_load_addr;
502 u64 vm_entry_msr_load_addr;
503
504 u64 cr3_target_value0;
505 u64 cr3_target_value1;
506 u64 cr3_target_value2;
507 u64 cr3_target_value3;
508
509 u32 page_fault_error_code_mask;
510 u32 page_fault_error_code_match;
511
512 u32 cr3_target_count;
513 u32 vm_exit_msr_store_count;
514 u32 vm_exit_msr_load_count;
515 u32 vm_entry_msr_load_count;
516
517 u64 tsc_offset;
518 u64 virtual_apic_page_addr;
519 u64 vmcs_link_pointer;
520
521 u64 guest_ia32_debugctl;
522 u64 guest_ia32_pat;
523 u64 guest_ia32_efer;
524
525 u64 guest_pdptr0;
526 u64 guest_pdptr1;
527 u64 guest_pdptr2;
528 u64 guest_pdptr3;
529
530 u64 guest_pending_dbg_exceptions;
531 u64 guest_sysenter_esp;
532 u64 guest_sysenter_eip;
533
534 u32 guest_activity_state;
535 u32 guest_sysenter_cs;
536
537 u64 cr0_guest_host_mask;
538 u64 cr4_guest_host_mask;
539 u64 cr0_read_shadow;
540 u64 cr4_read_shadow;
541 u64 guest_cr0;
542 u64 guest_cr3;
543 u64 guest_cr4;
544 u64 guest_dr7;
545
546 u64 host_fs_base;
547 u64 host_gs_base;
548 u64 host_tr_base;
549 u64 host_gdtr_base;
550 u64 host_idtr_base;
551 u64 host_rsp;
552
553 u64 ept_pointer;
554
555 u16 virtual_processor_id;
556 u16 padding16_2[3];
557
558 u64 padding64_2[5];
559 u64 guest_physical_address;
560
561 u32 vm_instruction_error;
562 u32 vm_exit_reason;
563 u32 vm_exit_intr_info;
564 u32 vm_exit_intr_error_code;
565 u32 idt_vectoring_info_field;
566 u32 idt_vectoring_error_code;
567 u32 vm_exit_instruction_len;
568 u32 vmx_instruction_info;
569
570 u64 exit_qualification;
571 u64 exit_io_instruction_ecx;
572 u64 exit_io_instruction_esi;
573 u64 exit_io_instruction_edi;
574 u64 exit_io_instruction_eip;
575
576 u64 guest_linear_address;
577 u64 guest_rsp;
578 u64 guest_rflags;
579
580 u32 guest_interruptibility_info;
581 u32 cpu_based_vm_exec_control;
582 u32 exception_bitmap;
583 u32 vm_entry_controls;
584 u32 vm_entry_intr_info_field;
585 u32 vm_entry_exception_error_code;
586 u32 vm_entry_instruction_len;
587 u32 tpr_threshold;
588
589 u64 guest_rip;
590
591 u32 hv_clean_fields;
592 u32 padding32_1;
593 u32 hv_synthetic_controls;
594 struct {
595 u32 nested_flush_hypercall:1;
596 u32 msr_bitmap:1;
597 u32 reserved:30;
598 } __packed hv_enlightenments_control;
599 u32 hv_vp_id;
600 u32 padding32_2;
601 u64 hv_vm_id;
602 u64 partition_assist_page;
603 u64 padding64_4[4];
604 u64 guest_bndcfgs;
605 u64 guest_ia32_perf_global_ctrl;
606 u64 guest_ia32_s_cet;
607 u64 guest_ssp;
608 u64 guest_ia32_int_ssp_table_addr;
609 u64 guest_ia32_lbr_ctl;
610 u64 padding64_5[2];
611 u64 xss_exit_bitmap;
612 u64 encls_exiting_bitmap;
613 u64 host_ia32_perf_global_ctrl;
614 u64 tsc_multiplier;
615 u64 host_ia32_s_cet;
616 u64 host_ssp;
617 u64 host_ia32_int_ssp_table_addr;
618 u64 padding64_6;
619} __packed;
620
621#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0
622#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0)
623#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1)
624#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2)
625#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3)
626#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4)
627#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5)
628#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6)
629#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7)
630#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8)
631#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9)
632#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10)
633#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11)
634#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12)
635#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13)
636#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14)
637#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15)
638
639#define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF
640
641/*
642 * Note, Hyper-V isn't actually stealing bit 28 from Intel, just abusing it by
643 * pairing it with architecturally impossible exit reasons. Bit 28 is set only
644 * on SMI exits to a SMI transfer monitor (STM) and if and only if a MTF VM-Exit
645 * is pending. I.e. it will never be set by hardware for non-SMI exits (there
646 * are only three), nor will it ever be set unless the VMM is an STM.
647 */
648#define HV_VMX_SYNTHETIC_EXIT_REASON_TRAP_AFTER_FLUSH 0x10000031
649
650/*
651 * Hyper-V uses the software reserved 32 bytes in VMCB control area to expose
652 * SVM enlightenments to guests.
653 */
654struct hv_vmcb_enlightenments {
655 struct __packed hv_enlightenments_control {
656 u32 nested_flush_hypercall:1;
657 u32 msr_bitmap:1;
658 u32 enlightened_npt_tlb: 1;
659 u32 reserved:29;
660 } __packed hv_enlightenments_control;
661 u32 hv_vp_id;
662 u64 hv_vm_id;
663 u64 partition_assist_page;
664 u64 reserved;
665} __packed;
666
667/*
668 * Hyper-V uses the software reserved clean bit in VMCB.
669 */
670#define HV_VMCB_NESTED_ENLIGHTENMENTS 31
671
672/* Synthetic VM-Exit */
673#define HV_SVM_EXITCODE_ENL 0xf0000000
674#define HV_SVM_ENL_EXITCODE_TRAP_AFTER_FLUSH (1)
675
676struct hv_partition_assist_pg {
677 u32 tlb_lock_count;
678};
679
680enum hv_interrupt_type {
681 HV_X64_INTERRUPT_TYPE_FIXED = 0x0000,
682 HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001,
683 HV_X64_INTERRUPT_TYPE_SMI = 0x0002,
684 HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003,
685 HV_X64_INTERRUPT_TYPE_NMI = 0x0004,
686 HV_X64_INTERRUPT_TYPE_INIT = 0x0005,
687 HV_X64_INTERRUPT_TYPE_SIPI = 0x0006,
688 HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007,
689 HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008,
690 HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009,
691 HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A,
692};
693
694union hv_msi_address_register {
695 u32 as_uint32;
696 struct {
697 u32 reserved1:2;
698 u32 destination_mode:1;
699 u32 redirection_hint:1;
700 u32 reserved2:8;
701 u32 destination_id:8;
702 u32 msi_base:12;
703 };
704} __packed;
705
706union hv_msi_data_register {
707 u32 as_uint32;
708 struct {
709 u32 vector:8;
710 u32 delivery_mode:3;
711 u32 reserved1:3;
712 u32 level_assert:1;
713 u32 trigger_mode:1;
714 u32 reserved2:16;
715 };
716} __packed;
717
718/* HvRetargetDeviceInterrupt hypercall */
719union hv_msi_entry {
720 u64 as_uint64;
721 struct {
722 union hv_msi_address_register address;
723 union hv_msi_data_register data;
724 } __packed;
725};
726
727struct hv_x64_segment_register {
728 u64 base;
729 u32 limit;
730 u16 selector;
731 union {
732 struct {
733 u16 segment_type : 4;
734 u16 non_system_segment : 1;
735 u16 descriptor_privilege_level : 2;
736 u16 present : 1;
737 u16 reserved : 4;
738 u16 available : 1;
739 u16 _long : 1;
740 u16 _default : 1;
741 u16 granularity : 1;
742 } __packed;
743 u16 attributes;
744 };
745} __packed;
746
747struct hv_x64_table_register {
748 u16 pad[3];
749 u16 limit;
750 u64 base;
751} __packed;
752
753struct hv_init_vp_context {
754 u64 rip;
755 u64 rsp;
756 u64 rflags;
757
758 struct hv_x64_segment_register cs;
759 struct hv_x64_segment_register ds;
760 struct hv_x64_segment_register es;
761 struct hv_x64_segment_register fs;
762 struct hv_x64_segment_register gs;
763 struct hv_x64_segment_register ss;
764 struct hv_x64_segment_register tr;
765 struct hv_x64_segment_register ldtr;
766
767 struct hv_x64_table_register idtr;
768 struct hv_x64_table_register gdtr;
769
770 u64 efer;
771 u64 cr0;
772 u64 cr3;
773 u64 cr4;
774 u64 msr_cr_pat;
775} __packed;
776
777union hv_input_vtl {
778 u8 as_uint8;
779 struct {
780 u8 target_vtl: 4;
781 u8 use_target_vtl: 1;
782 u8 reserved_z: 3;
783 };
784} __packed;
785
786struct hv_enable_vp_vtl {
787 u64 partition_id;
788 u32 vp_index;
789 union hv_input_vtl target_vtl;
790 u8 mbz0;
791 u16 mbz1;
792 struct hv_init_vp_context vp_context;
793} __packed;
794
795struct hv_get_vp_from_apic_id_in {
796 u64 partition_id;
797 union hv_input_vtl target_vtl;
798 u8 res[7];
799 u32 apic_ids[];
800} __packed;
801
802#include <asm-generic/hyperv-tlfs.h>
803
804#endif
805

source code of linux/arch/x86/include/asm/hyperv-tlfs.h