| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef _ASM_X86_INTEL_FAMILY_H |
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| 3 | #define _ASM_X86_INTEL_FAMILY_H |
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| 4 | |
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| 5 | /* |
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| 6 | * "Big Core" Processors (Branded as Core, Xeon, etc...) |
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| 7 | * |
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| 8 | * While adding a new CPUID for a new microarchitecture, add a new |
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| 9 | * group to keep logically sorted out in chronological order. Within |
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| 10 | * that group keep the CPUID for the variants sorted by model number. |
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| 11 | * |
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| 12 | * The defined symbol names have the following form: |
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| 13 | * INTEL_{OPTFAMILY}_{MICROARCH}{OPTDIFF} |
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| 14 | * where: |
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| 15 | * OPTFAMILY Describes the family of CPUs that this belongs to. Default |
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| 16 | * is assumed to be "_CORE" (and should be omitted). Other values |
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| 17 | * currently in use are _ATOM and _XEON_PHI |
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| 18 | * MICROARCH Is the code name for the micro-architecture for this core. |
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| 19 | * N.B. Not the platform name. |
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| 20 | * OPTDIFF If needed, a short string to differentiate by market segment. |
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| 21 | * |
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| 22 | * Common OPTDIFFs: |
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| 23 | * |
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| 24 | * - regular client parts |
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| 25 | * _L - regular mobile parts |
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| 26 | * _G - parts with extra graphics on |
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| 27 | * _X - regular server parts |
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| 28 | * _D - micro server parts |
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| 29 | * _N,_P - other mobile parts |
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| 30 | * _H - premium mobile parts |
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| 31 | * _S - other client parts |
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| 32 | * |
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| 33 | * Historical OPTDIFFs: |
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| 34 | * |
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| 35 | * _EP - 2 socket server parts |
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| 36 | * _EX - 4+ socket server parts |
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| 37 | * |
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| 38 | * The #define line may optionally include a comment including platform or core |
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| 39 | * names. An exception is made for skylake/kabylake where steppings seem to have gotten |
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| 40 | * their own names :-( |
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| 41 | */ |
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| 42 | |
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| 43 | #define IFM(_fam, _model) VFM_MAKE(X86_VENDOR_INTEL, _fam, _model) |
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| 44 | |
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| 45 | /* Wildcard match so X86_MATCH_VFM(ANY) works */ |
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| 46 | #define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY) |
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| 47 | |
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| 48 | /* Family 5 */ |
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| 49 | #define INTEL_FAM5_START IFM(5, 0x00) /* Notational marker, also P5 A-step */ |
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| 50 | #define INTEL_PENTIUM_75 IFM(5, 0x02) /* P54C */ |
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| 51 | #define INTEL_PENTIUM_MMX IFM(5, 0x04) /* P55C */ |
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| 52 | #define INTEL_QUARK_X1000 IFM(5, 0x09) /* Quark X1000 SoC */ |
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| 53 | |
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| 54 | /* Family 6 */ |
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| 55 | #define INTEL_PENTIUM_PRO IFM(6, 0x01) |
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| 56 | #define INTEL_PENTIUM_II_KLAMATH IFM(6, 0x03) |
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| 57 | #define INTEL_PENTIUM_III_DESCHUTES IFM(6, 0x05) |
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| 58 | #define INTEL_PENTIUM_III_TUALATIN IFM(6, 0x0B) |
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| 59 | #define INTEL_PENTIUM_M_DOTHAN IFM(6, 0x0D) |
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| 60 | |
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| 61 | #define INTEL_CORE_YONAH IFM(6, 0x0E) |
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| 62 | |
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| 63 | #define INTEL_CORE2_MEROM IFM(6, 0x0F) |
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| 64 | #define INTEL_CORE2_MEROM_L IFM(6, 0x16) |
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| 65 | #define INTEL_CORE2_PENRYN IFM(6, 0x17) |
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| 66 | #define INTEL_CORE2_DUNNINGTON IFM(6, 0x1D) |
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| 67 | |
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| 68 | #define INTEL_NEHALEM IFM(6, 0x1E) |
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| 69 | #define INTEL_NEHALEM_G IFM(6, 0x1F) /* Auburndale / Havendale */ |
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| 70 | #define INTEL_NEHALEM_EP IFM(6, 0x1A) |
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| 71 | #define INTEL_NEHALEM_EX IFM(6, 0x2E) |
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| 72 | |
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| 73 | #define INTEL_WESTMERE IFM(6, 0x25) |
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| 74 | #define INTEL_WESTMERE_EP IFM(6, 0x2C) |
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| 75 | #define INTEL_WESTMERE_EX IFM(6, 0x2F) |
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| 76 | |
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| 77 | #define INTEL_SANDYBRIDGE IFM(6, 0x2A) |
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| 78 | #define INTEL_SANDYBRIDGE_X IFM(6, 0x2D) |
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| 79 | #define INTEL_IVYBRIDGE IFM(6, 0x3A) |
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| 80 | #define INTEL_IVYBRIDGE_X IFM(6, 0x3E) |
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| 81 | |
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| 82 | #define INTEL_HASWELL IFM(6, 0x3C) |
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| 83 | #define INTEL_HASWELL_X IFM(6, 0x3F) |
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| 84 | #define INTEL_HASWELL_L IFM(6, 0x45) |
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| 85 | #define INTEL_HASWELL_G IFM(6, 0x46) |
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| 86 | |
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| 87 | #define INTEL_BROADWELL IFM(6, 0x3D) |
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| 88 | #define INTEL_BROADWELL_G IFM(6, 0x47) |
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| 89 | #define INTEL_BROADWELL_X IFM(6, 0x4F) |
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| 90 | #define INTEL_BROADWELL_D IFM(6, 0x56) |
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| 91 | |
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| 92 | #define INTEL_SKYLAKE_L IFM(6, 0x4E) /* Sky Lake */ |
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| 93 | #define INTEL_SKYLAKE IFM(6, 0x5E) /* Sky Lake */ |
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| 94 | #define INTEL_SKYLAKE_X IFM(6, 0x55) /* Sky Lake */ |
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| 95 | /* CASCADELAKE_X 0x55 Sky Lake -- s: 7 */ |
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| 96 | /* COOPERLAKE_X 0x55 Sky Lake -- s: 11 */ |
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| 97 | |
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| 98 | #define INTEL_KABYLAKE_L IFM(6, 0x8E) /* Sky Lake */ |
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| 99 | /* AMBERLAKE_L 0x8E Sky Lake -- s: 9 */ |
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| 100 | /* COFFEELAKE_L 0x8E Sky Lake -- s: 10 */ |
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| 101 | /* WHISKEYLAKE_L 0x8E Sky Lake -- s: 11,12 */ |
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| 102 | |
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| 103 | #define INTEL_KABYLAKE IFM(6, 0x9E) /* Sky Lake */ |
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| 104 | /* COFFEELAKE 0x9E Sky Lake -- s: 10-13 */ |
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| 105 | |
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| 106 | #define INTEL_COMETLAKE IFM(6, 0xA5) /* Sky Lake */ |
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| 107 | #define INTEL_COMETLAKE_L IFM(6, 0xA6) /* Sky Lake */ |
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| 108 | |
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| 109 | #define INTEL_CANNONLAKE_L IFM(6, 0x66) /* Palm Cove */ |
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| 110 | |
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| 111 | #define INTEL_ICELAKE_X IFM(6, 0x6A) /* Sunny Cove */ |
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| 112 | #define INTEL_ICELAKE_D IFM(6, 0x6C) /* Sunny Cove */ |
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| 113 | #define INTEL_ICELAKE IFM(6, 0x7D) /* Sunny Cove */ |
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| 114 | #define INTEL_ICELAKE_L IFM(6, 0x7E) /* Sunny Cove */ |
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| 115 | #define INTEL_ICELAKE_NNPI IFM(6, 0x9D) /* Sunny Cove */ |
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| 116 | |
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| 117 | #define INTEL_ROCKETLAKE IFM(6, 0xA7) /* Cypress Cove */ |
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| 118 | |
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| 119 | #define INTEL_TIGERLAKE_L IFM(6, 0x8C) /* Willow Cove */ |
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| 120 | #define INTEL_TIGERLAKE IFM(6, 0x8D) /* Willow Cove */ |
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| 121 | |
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| 122 | #define INTEL_SAPPHIRERAPIDS_X IFM(6, 0x8F) /* Golden Cove */ |
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| 123 | |
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| 124 | #define INTEL_EMERALDRAPIDS_X IFM(6, 0xCF) /* Raptor Cove */ |
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| 125 | |
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| 126 | #define INTEL_GRANITERAPIDS_X IFM(6, 0xAD) /* Redwood Cove */ |
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| 127 | #define INTEL_GRANITERAPIDS_D IFM(6, 0xAE) |
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| 128 | |
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| 129 | #define INTEL_BARTLETTLAKE IFM(6, 0xD7) /* Raptor Cove */ |
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| 130 | |
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| 131 | /* "Hybrid" Processors (P-Core/E-Core) */ |
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| 132 | |
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| 133 | #define INTEL_LAKEFIELD IFM(6, 0x8A) /* Sunny Cove / Tremont */ |
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| 134 | |
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| 135 | #define INTEL_ALDERLAKE IFM(6, 0x97) /* Golden Cove / Gracemont */ |
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| 136 | #define INTEL_ALDERLAKE_L IFM(6, 0x9A) /* Golden Cove / Gracemont */ |
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| 137 | |
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| 138 | #define INTEL_RAPTORLAKE IFM(6, 0xB7) /* Raptor Cove / Enhanced Gracemont */ |
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| 139 | #define INTEL_RAPTORLAKE_P IFM(6, 0xBA) |
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| 140 | #define INTEL_RAPTORLAKE_S IFM(6, 0xBF) |
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| 141 | |
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| 142 | #define INTEL_METEORLAKE IFM(6, 0xAC) /* Redwood Cove / Crestmont */ |
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| 143 | #define INTEL_METEORLAKE_L IFM(6, 0xAA) |
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| 144 | |
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| 145 | #define INTEL_ARROWLAKE_H IFM(6, 0xC5) /* Lion Cove / Skymont */ |
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| 146 | #define INTEL_ARROWLAKE IFM(6, 0xC6) |
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| 147 | #define INTEL_ARROWLAKE_U IFM(6, 0xB5) |
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| 148 | |
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| 149 | #define INTEL_LUNARLAKE_M IFM(6, 0xBD) /* Lion Cove / Skymont */ |
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| 150 | |
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| 151 | #define INTEL_PANTHERLAKE_L IFM(6, 0xCC) /* Cougar Cove / Crestmont */ |
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| 152 | |
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| 153 | /* "Small Core" Processors (Atom/E-Core) */ |
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| 154 | |
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| 155 | #define INTEL_ATOM_BONNELL IFM(6, 0x1C) /* Diamondville, Pineview */ |
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| 156 | #define INTEL_ATOM_BONNELL_MID IFM(6, 0x26) /* Silverthorne, Lincroft */ |
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| 157 | |
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| 158 | #define INTEL_ATOM_SALTWELL IFM(6, 0x36) /* Cedarview */ |
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| 159 | #define INTEL_ATOM_SALTWELL_MID IFM(6, 0x27) /* Penwell */ |
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| 160 | #define INTEL_ATOM_SALTWELL_TABLET IFM(6, 0x35) /* Cloverview */ |
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| 161 | |
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| 162 | #define INTEL_ATOM_SILVERMONT IFM(6, 0x37) /* Bay Trail, Valleyview */ |
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| 163 | #define INTEL_ATOM_SILVERMONT_D IFM(6, 0x4D) /* Avaton, Rangely */ |
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| 164 | #define INTEL_ATOM_SILVERMONT_MID IFM(6, 0x4A) /* Merriefield */ |
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| 165 | #define INTEL_ATOM_SILVERMONT_MID2 IFM(6, 0x5A) /* Anniedale */ |
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| 166 | |
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| 167 | #define INTEL_ATOM_AIRMONT IFM(6, 0x4C) /* Cherry Trail, Braswell */ |
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| 168 | #define INTEL_ATOM_AIRMONT_NP IFM(6, 0x75) /* Lightning Mountain */ |
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| 169 | |
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| 170 | #define INTEL_ATOM_GOLDMONT IFM(6, 0x5C) /* Apollo Lake */ |
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| 171 | #define INTEL_ATOM_GOLDMONT_D IFM(6, 0x5F) /* Denverton */ |
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| 172 | |
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| 173 | /* Note: the micro-architecture is "Goldmont Plus" */ |
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| 174 | #define INTEL_ATOM_GOLDMONT_PLUS IFM(6, 0x7A) /* Gemini Lake */ |
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| 175 | |
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| 176 | #define INTEL_ATOM_TREMONT_D IFM(6, 0x86) /* Jacobsville */ |
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| 177 | #define INTEL_ATOM_TREMONT IFM(6, 0x96) /* Elkhart Lake */ |
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| 178 | #define INTEL_ATOM_TREMONT_L IFM(6, 0x9C) /* Jasper Lake */ |
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| 179 | |
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| 180 | #define INTEL_ATOM_GRACEMONT IFM(6, 0xBE) /* Alderlake N */ |
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| 181 | |
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| 182 | #define INTEL_ATOM_CRESTMONT_X IFM(6, 0xAF) /* Sierra Forest */ |
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| 183 | #define INTEL_ATOM_CRESTMONT IFM(6, 0xB6) /* Grand Ridge */ |
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| 184 | |
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| 185 | #define INTEL_ATOM_DARKMONT_X IFM(6, 0xDD) /* Clearwater Forest */ |
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| 186 | |
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| 187 | /* Xeon Phi */ |
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| 188 | |
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| 189 | #define INTEL_XEON_PHI_KNL IFM(6, 0x57) /* Knights Landing */ |
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| 190 | #define INTEL_XEON_PHI_KNM IFM(6, 0x85) /* Knights Mill */ |
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| 191 | |
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| 192 | /* Notational marker denoting the last Family 6 model */ |
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| 193 | #define INTEL_FAM6_LAST IFM(6, 0xFF) |
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| 194 | |
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| 195 | /* Family 15 - NetBurst */ |
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| 196 | #define INTEL_P4_WILLAMETTE IFM(15, 0x01) /* Also Xeon Foster */ |
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| 197 | #define INTEL_P4_PRESCOTT IFM(15, 0x03) |
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| 198 | #define INTEL_P4_PRESCOTT_2M IFM(15, 0x04) |
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| 199 | #define INTEL_P4_CEDARMILL IFM(15, 0x06) /* Also Xeon Dempsey */ |
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| 200 | |
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| 201 | /* Family 19 */ |
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| 202 | #define INTEL_PANTHERCOVE_X IFM(19, 0x01) /* Diamond Rapids */ |
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| 203 | |
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| 204 | /* |
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| 205 | * Intel CPU core types |
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| 206 | * |
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| 207 | * CPUID.1AH.EAX[31:0] uniquely identifies the microarchitecture |
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| 208 | * of the core. Bits 31-24 indicates its core type (Core or Atom) |
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| 209 | * and Bits [23:0] indicates the native model ID of the core. |
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| 210 | * Core type and native model ID are defined in below enumerations. |
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| 211 | */ |
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| 212 | enum intel_cpu_type { |
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| 213 | INTEL_CPU_TYPE_UNKNOWN, |
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| 214 | INTEL_CPU_TYPE_ATOM = 0x20, |
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| 215 | INTEL_CPU_TYPE_CORE = 0x40, |
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| 216 | }; |
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| 217 | |
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| 218 | enum intel_native_id { |
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| 219 | INTEL_ATOM_CMT_NATIVE_ID = 0x2, /* Crestmont */ |
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| 220 | INTEL_ATOM_SKT_NATIVE_ID = 0x3, /* Skymont */ |
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| 221 | }; |
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| 222 | |
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| 223 | #endif /* _ASM_X86_INTEL_FAMILY_H */ |
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| 224 | |
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