1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_MSR_INDEX_H
3#define _ASM_X86_MSR_INDEX_H
4
5#include <linux/bits.h>
6
7/* CPU model specific register (MSR) numbers. */
8
9/* x86-64 specific MSRs */
10#define MSR_EFER 0xc0000080 /* extended feature register */
11#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
12#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
13#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
14#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
15#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
16#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
17#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
18#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
19
20/* EFER bits: */
21#define _EFER_SCE 0 /* SYSCALL/SYSRET */
22#define _EFER_LME 8 /* Long mode enable */
23#define _EFER_LMA 10 /* Long mode active (read-only) */
24#define _EFER_NX 11 /* No execute enable */
25#define _EFER_SVME 12 /* Enable virtualization */
26#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
27#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
28#define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */
29
30#define EFER_SCE (1<<_EFER_SCE)
31#define EFER_LME (1<<_EFER_LME)
32#define EFER_LMA (1<<_EFER_LMA)
33#define EFER_NX (1<<_EFER_NX)
34#define EFER_SVME (1<<_EFER_SVME)
35#define EFER_LMSLE (1<<_EFER_LMSLE)
36#define EFER_FFXSR (1<<_EFER_FFXSR)
37#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS)
38
39/* FRED MSRs */
40#define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */
41#define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */
42#define MSR_IA32_FRED_RSP2 0x1ce /* Level 2 stack pointer */
43#define MSR_IA32_FRED_RSP3 0x1cf /* Level 3 stack pointer */
44#define MSR_IA32_FRED_STKLVLS 0x1d0 /* Exception stack levels */
45#define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Level 0 shadow stack pointer */
46#define MSR_IA32_FRED_SSP1 0x1d1 /* Level 1 shadow stack pointer */
47#define MSR_IA32_FRED_SSP2 0x1d2 /* Level 2 shadow stack pointer */
48#define MSR_IA32_FRED_SSP3 0x1d3 /* Level 3 shadow stack pointer */
49#define MSR_IA32_FRED_CONFIG 0x1d4 /* Entrypoint and interrupt stack level */
50
51/* Intel MSRs. Some also available on other CPUs */
52#define MSR_TEST_CTRL 0x00000033
53#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29
54#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
55
56#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
57#define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */
58#define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */
59#define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */
60#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */
61#define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
62#define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */
63#define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)
64#define SPEC_CTRL_BHI_DIS_S_SHIFT 10 /* Disable Branch History Injection behavior */
65#define SPEC_CTRL_BHI_DIS_S BIT(SPEC_CTRL_BHI_DIS_S_SHIFT)
66
67/* A mask for bits which the kernel toggles when controlling mitigations */
68#define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \
69 | SPEC_CTRL_RRSBA_DIS_S \
70 | SPEC_CTRL_BHI_DIS_S)
71
72#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
73#define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
74#define PRED_CMD_SBPB BIT(7) /* Selective Branch Prediction Barrier */
75
76#define MSR_PPIN_CTL 0x0000004e
77#define MSR_PPIN 0x0000004f
78
79#define MSR_IA32_PERFCTR0 0x000000c1
80#define MSR_IA32_PERFCTR1 0x000000c2
81#define MSR_FSB_FREQ 0x000000cd
82#define MSR_PLATFORM_INFO 0x000000ce
83#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31
84#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
85
86#define MSR_IA32_UMWAIT_CONTROL 0xe1
87#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0)
88#define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1)
89/*
90 * The time field is bit[31:2], but representing a 32bit value with
91 * bit[1:0] zero.
92 */
93#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK (~0x03U)
94
95/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
96#define MSR_IA32_CORE_CAPS 0x000000cf
97#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT 2
98#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT)
99#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5
100#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
101
102#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
103#define NHM_C3_AUTO_DEMOTE (1UL << 25)
104#define NHM_C1_AUTO_DEMOTE (1UL << 26)
105#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
106#define SNB_C3_AUTO_UNDEMOTE (1UL << 27)
107#define SNB_C1_AUTO_UNDEMOTE (1UL << 28)
108
109#define MSR_MTRRcap 0x000000fe
110
111#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
112#define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */
113#define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */
114#define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */
115#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */
116#define ARCH_CAP_SSB_NO BIT(4) /*
117 * Not susceptible to Speculative Store Bypass
118 * attack, so no Speculative Store Bypass
119 * control required.
120 */
121#define ARCH_CAP_MDS_NO BIT(5) /*
122 * Not susceptible to
123 * Microarchitectural Data
124 * Sampling (MDS) vulnerabilities.
125 */
126#define ARCH_CAP_PSCHANGE_MC_NO BIT(6) /*
127 * The processor is not susceptible to a
128 * machine check error due to modifying the
129 * code page size along with either the
130 * physical address or cache type
131 * without TLB invalidation.
132 */
133#define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */
134#define ARCH_CAP_TAA_NO BIT(8) /*
135 * Not susceptible to
136 * TSX Async Abort (TAA) vulnerabilities.
137 */
138#define ARCH_CAP_SBDR_SSDP_NO BIT(13) /*
139 * Not susceptible to SBDR and SSDP
140 * variants of Processor MMIO stale data
141 * vulnerabilities.
142 */
143#define ARCH_CAP_FBSDP_NO BIT(14) /*
144 * Not susceptible to FBSDP variant of
145 * Processor MMIO stale data
146 * vulnerabilities.
147 */
148#define ARCH_CAP_PSDP_NO BIT(15) /*
149 * Not susceptible to PSDP variant of
150 * Processor MMIO stale data
151 * vulnerabilities.
152 */
153#define ARCH_CAP_FB_CLEAR BIT(17) /*
154 * VERW clears CPU fill buffer
155 * even on MDS_NO CPUs.
156 */
157#define ARCH_CAP_FB_CLEAR_CTRL BIT(18) /*
158 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
159 * bit available to control VERW
160 * behavior.
161 */
162#define ARCH_CAP_RRSBA BIT(19) /*
163 * Indicates RET may use predictors
164 * other than the RSB. With eIBRS
165 * enabled predictions in kernel mode
166 * are restricted to targets in
167 * kernel.
168 */
169#define ARCH_CAP_BHI_NO BIT(20) /*
170 * CPU is not affected by Branch
171 * History Injection.
172 */
173#define ARCH_CAP_PBRSB_NO BIT(24) /*
174 * Not susceptible to Post-Barrier
175 * Return Stack Buffer Predictions.
176 */
177#define ARCH_CAP_GDS_CTRL BIT(25) /*
178 * CPU is vulnerable to Gather
179 * Data Sampling (GDS) and
180 * has controls for mitigation.
181 */
182#define ARCH_CAP_GDS_NO BIT(26) /*
183 * CPU is not vulnerable to Gather
184 * Data Sampling (GDS).
185 */
186#define ARCH_CAP_RFDS_NO BIT(27) /*
187 * Not susceptible to Register
188 * File Data Sampling.
189 */
190#define ARCH_CAP_RFDS_CLEAR BIT(28) /*
191 * VERW clears CPU Register
192 * File.
193 */
194
195#define ARCH_CAP_XAPIC_DISABLE BIT(21) /*
196 * IA32_XAPIC_DISABLE_STATUS MSR
197 * supported
198 */
199
200#define MSR_IA32_FLUSH_CMD 0x0000010b
201#define L1D_FLUSH BIT(0) /*
202 * Writeback and invalidate the
203 * L1 data cache.
204 */
205
206#define MSR_IA32_BBL_CR_CTL 0x00000119
207#define MSR_IA32_BBL_CR_CTL3 0x0000011e
208
209#define MSR_IA32_TSX_CTRL 0x00000122
210#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
211#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
212
213#define MSR_IA32_MCU_OPT_CTRL 0x00000123
214#define RNGDS_MITG_DIS BIT(0) /* SRBDS support */
215#define RTM_ALLOW BIT(1) /* TSX development mode */
216#define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */
217#define GDS_MITG_DIS BIT(4) /* Disable GDS mitigation */
218#define GDS_MITG_LOCKED BIT(5) /* GDS mitigation locked */
219
220#define MSR_IA32_SYSENTER_CS 0x00000174
221#define MSR_IA32_SYSENTER_ESP 0x00000175
222#define MSR_IA32_SYSENTER_EIP 0x00000176
223
224#define MSR_IA32_MCG_CAP 0x00000179
225#define MSR_IA32_MCG_STATUS 0x0000017a
226#define MSR_IA32_MCG_CTL 0x0000017b
227#define MSR_ERROR_CONTROL 0x0000017f
228#define MSR_IA32_MCG_EXT_CTL 0x000004d0
229
230#define MSR_OFFCORE_RSP_0 0x000001a6
231#define MSR_OFFCORE_RSP_1 0x000001a7
232#define MSR_TURBO_RATIO_LIMIT 0x000001ad
233#define MSR_TURBO_RATIO_LIMIT1 0x000001ae
234#define MSR_TURBO_RATIO_LIMIT2 0x000001af
235
236#define MSR_SNOOP_RSP_0 0x00001328
237#define MSR_SNOOP_RSP_1 0x00001329
238
239#define MSR_LBR_SELECT 0x000001c8
240#define MSR_LBR_TOS 0x000001c9
241
242#define MSR_IA32_POWER_CTL 0x000001fc
243#define MSR_IA32_POWER_CTL_BIT_EE 19
244
245/* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */
246#define MSR_INTEGRITY_CAPS 0x000002d9
247#define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2
248#define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT)
249#define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4
250#define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)
251#define MSR_INTEGRITY_CAPS_SAF_GEN_MASK GENMASK_ULL(10, 9)
252
253#define MSR_LBR_NHM_FROM 0x00000680
254#define MSR_LBR_NHM_TO 0x000006c0
255#define MSR_LBR_CORE_FROM 0x00000040
256#define MSR_LBR_CORE_TO 0x00000060
257
258#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */
259#define LBR_INFO_MISPRED BIT_ULL(63)
260#define LBR_INFO_IN_TX BIT_ULL(62)
261#define LBR_INFO_ABORT BIT_ULL(61)
262#define LBR_INFO_CYC_CNT_VALID BIT_ULL(60)
263#define LBR_INFO_CYCLES 0xffff
264#define LBR_INFO_BR_TYPE_OFFSET 56
265#define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET)
266#define LBR_INFO_BR_CNTR_OFFSET 32
267#define LBR_INFO_BR_CNTR_NUM 4
268#define LBR_INFO_BR_CNTR_BITS 2
269#define LBR_INFO_BR_CNTR_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_BITS - 1, 0)
270#define LBR_INFO_BR_CNTR_FULL_MASK GENMASK_ULL(LBR_INFO_BR_CNTR_NUM * LBR_INFO_BR_CNTR_BITS - 1, 0)
271
272#define MSR_ARCH_LBR_CTL 0x000014ce
273#define ARCH_LBR_CTL_LBREN BIT(0)
274#define ARCH_LBR_CTL_CPL_OFFSET 1
275#define ARCH_LBR_CTL_CPL (0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
276#define ARCH_LBR_CTL_STACK_OFFSET 3
277#define ARCH_LBR_CTL_STACK (0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
278#define ARCH_LBR_CTL_FILTER_OFFSET 16
279#define ARCH_LBR_CTL_FILTER (0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
280#define MSR_ARCH_LBR_DEPTH 0x000014cf
281#define MSR_ARCH_LBR_FROM_0 0x00001500
282#define MSR_ARCH_LBR_TO_0 0x00001600
283#define MSR_ARCH_LBR_INFO_0 0x00001200
284
285#define MSR_IA32_PEBS_ENABLE 0x000003f1
286#define MSR_PEBS_DATA_CFG 0x000003f2
287#define MSR_IA32_DS_AREA 0x00000600
288#define MSR_IA32_PERF_CAPABILITIES 0x00000345
289#define PERF_CAP_METRICS_IDX 15
290#define PERF_CAP_PT_IDX 16
291
292#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
293#define PERF_CAP_PEBS_TRAP BIT_ULL(6)
294#define PERF_CAP_ARCH_REG BIT_ULL(7)
295#define PERF_CAP_PEBS_FORMAT 0xf00
296#define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
297#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
298 PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE)
299
300#define MSR_IA32_RTIT_CTL 0x00000570
301#define RTIT_CTL_TRACEEN BIT(0)
302#define RTIT_CTL_CYCLEACC BIT(1)
303#define RTIT_CTL_OS BIT(2)
304#define RTIT_CTL_USR BIT(3)
305#define RTIT_CTL_PWR_EVT_EN BIT(4)
306#define RTIT_CTL_FUP_ON_PTW BIT(5)
307#define RTIT_CTL_FABRIC_EN BIT(6)
308#define RTIT_CTL_CR3EN BIT(7)
309#define RTIT_CTL_TOPA BIT(8)
310#define RTIT_CTL_MTC_EN BIT(9)
311#define RTIT_CTL_TSC_EN BIT(10)
312#define RTIT_CTL_DISRETC BIT(11)
313#define RTIT_CTL_PTW_EN BIT(12)
314#define RTIT_CTL_BRANCH_EN BIT(13)
315#define RTIT_CTL_EVENT_EN BIT(31)
316#define RTIT_CTL_NOTNT BIT_ULL(55)
317#define RTIT_CTL_MTC_RANGE_OFFSET 14
318#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
319#define RTIT_CTL_CYC_THRESH_OFFSET 19
320#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
321#define RTIT_CTL_PSB_FREQ_OFFSET 24
322#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
323#define RTIT_CTL_ADDR0_OFFSET 32
324#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
325#define RTIT_CTL_ADDR1_OFFSET 36
326#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
327#define RTIT_CTL_ADDR2_OFFSET 40
328#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
329#define RTIT_CTL_ADDR3_OFFSET 44
330#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
331#define MSR_IA32_RTIT_STATUS 0x00000571
332#define RTIT_STATUS_FILTEREN BIT(0)
333#define RTIT_STATUS_CONTEXTEN BIT(1)
334#define RTIT_STATUS_TRIGGEREN BIT(2)
335#define RTIT_STATUS_BUFFOVF BIT(3)
336#define RTIT_STATUS_ERROR BIT(4)
337#define RTIT_STATUS_STOPPED BIT(5)
338#define RTIT_STATUS_BYTECNT_OFFSET 32
339#define RTIT_STATUS_BYTECNT (0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
340#define MSR_IA32_RTIT_ADDR0_A 0x00000580
341#define MSR_IA32_RTIT_ADDR0_B 0x00000581
342#define MSR_IA32_RTIT_ADDR1_A 0x00000582
343#define MSR_IA32_RTIT_ADDR1_B 0x00000583
344#define MSR_IA32_RTIT_ADDR2_A 0x00000584
345#define MSR_IA32_RTIT_ADDR2_B 0x00000585
346#define MSR_IA32_RTIT_ADDR3_A 0x00000586
347#define MSR_IA32_RTIT_ADDR3_B 0x00000587
348#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
349#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
350#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
351
352#define MSR_MTRRfix64K_00000 0x00000250
353#define MSR_MTRRfix16K_80000 0x00000258
354#define MSR_MTRRfix16K_A0000 0x00000259
355#define MSR_MTRRfix4K_C0000 0x00000268
356#define MSR_MTRRfix4K_C8000 0x00000269
357#define MSR_MTRRfix4K_D0000 0x0000026a
358#define MSR_MTRRfix4K_D8000 0x0000026b
359#define MSR_MTRRfix4K_E0000 0x0000026c
360#define MSR_MTRRfix4K_E8000 0x0000026d
361#define MSR_MTRRfix4K_F0000 0x0000026e
362#define MSR_MTRRfix4K_F8000 0x0000026f
363#define MSR_MTRRdefType 0x000002ff
364
365#define MSR_IA32_CR_PAT 0x00000277
366
367#define MSR_IA32_DEBUGCTLMSR 0x000001d9
368#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
369#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
370#define MSR_IA32_LASTINTFROMIP 0x000001dd
371#define MSR_IA32_LASTINTTOIP 0x000001de
372
373#define MSR_IA32_PASID 0x00000d93
374#define MSR_IA32_PASID_VALID BIT_ULL(31)
375
376/* DEBUGCTLMSR bits (others vary by model): */
377#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
378#define DEBUGCTLMSR_BTF_SHIFT 1
379#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
380#define DEBUGCTLMSR_BUS_LOCK_DETECT (1UL << 2)
381#define DEBUGCTLMSR_TR (1UL << 6)
382#define DEBUGCTLMSR_BTS (1UL << 7)
383#define DEBUGCTLMSR_BTINT (1UL << 8)
384#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
385#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
386#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
387#define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI (1UL << 12)
388#define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14
389#define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT)
390
391#define MSR_PEBS_FRONTEND 0x000003f7
392
393#define MSR_IA32_MC0_CTL 0x00000400
394#define MSR_IA32_MC0_STATUS 0x00000401
395#define MSR_IA32_MC0_ADDR 0x00000402
396#define MSR_IA32_MC0_MISC 0x00000403
397
398/* C-state Residency Counters */
399#define MSR_PKG_C3_RESIDENCY 0x000003f8
400#define MSR_PKG_C6_RESIDENCY 0x000003f9
401#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
402#define MSR_PKG_C7_RESIDENCY 0x000003fa
403#define MSR_CORE_C3_RESIDENCY 0x000003fc
404#define MSR_CORE_C6_RESIDENCY 0x000003fd
405#define MSR_CORE_C7_RESIDENCY 0x000003fe
406#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff
407#define MSR_PKG_C2_RESIDENCY 0x0000060d
408#define MSR_PKG_C8_RESIDENCY 0x00000630
409#define MSR_PKG_C9_RESIDENCY 0x00000631
410#define MSR_PKG_C10_RESIDENCY 0x00000632
411
412/* Interrupt Response Limit */
413#define MSR_PKGC3_IRTL 0x0000060a
414#define MSR_PKGC6_IRTL 0x0000060b
415#define MSR_PKGC7_IRTL 0x0000060c
416#define MSR_PKGC8_IRTL 0x00000633
417#define MSR_PKGC9_IRTL 0x00000634
418#define MSR_PKGC10_IRTL 0x00000635
419
420/* Run Time Average Power Limiting (RAPL) Interface */
421
422#define MSR_VR_CURRENT_CONFIG 0x00000601
423#define MSR_RAPL_POWER_UNIT 0x00000606
424
425#define MSR_PKG_POWER_LIMIT 0x00000610
426#define MSR_PKG_ENERGY_STATUS 0x00000611
427#define MSR_PKG_PERF_STATUS 0x00000613
428#define MSR_PKG_POWER_INFO 0x00000614
429
430#define MSR_DRAM_POWER_LIMIT 0x00000618
431#define MSR_DRAM_ENERGY_STATUS 0x00000619
432#define MSR_DRAM_PERF_STATUS 0x0000061b
433#define MSR_DRAM_POWER_INFO 0x0000061c
434
435#define MSR_PP0_POWER_LIMIT 0x00000638
436#define MSR_PP0_ENERGY_STATUS 0x00000639
437#define MSR_PP0_POLICY 0x0000063a
438#define MSR_PP0_PERF_STATUS 0x0000063b
439
440#define MSR_PP1_POWER_LIMIT 0x00000640
441#define MSR_PP1_ENERGY_STATUS 0x00000641
442#define MSR_PP1_POLICY 0x00000642
443
444#define MSR_AMD_RAPL_POWER_UNIT 0xc0010299
445#define MSR_AMD_CORE_ENERGY_STATUS 0xc001029a
446#define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b
447
448/* Config TDP MSRs */
449#define MSR_CONFIG_TDP_NOMINAL 0x00000648
450#define MSR_CONFIG_TDP_LEVEL_1 0x00000649
451#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
452#define MSR_CONFIG_TDP_CONTROL 0x0000064B
453#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
454
455#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D
456#define MSR_SECONDARY_TURBO_RATIO_LIMIT 0x00000650
457
458#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
459#define MSR_PKG_ANY_CORE_C0_RES 0x00000659
460#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
461#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
462
463#define MSR_CORE_C1_RES 0x00000660
464#define MSR_MODULE_C6_RES_MS 0x00000664
465
466#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
467#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
468
469#define MSR_ATOM_CORE_RATIOS 0x0000066a
470#define MSR_ATOM_CORE_VIDS 0x0000066b
471#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c
472#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d
473
474#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690
475#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
476#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
477
478/* Control-flow Enforcement Technology MSRs */
479#define MSR_IA32_U_CET 0x000006a0 /* user mode cet */
480#define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */
481#define CET_SHSTK_EN BIT_ULL(0)
482#define CET_WRSS_EN BIT_ULL(1)
483#define CET_ENDBR_EN BIT_ULL(2)
484#define CET_LEG_IW_EN BIT_ULL(3)
485#define CET_NO_TRACK_EN BIT_ULL(4)
486#define CET_SUPPRESS_DISABLE BIT_ULL(5)
487#define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))
488#define CET_SUPPRESS BIT_ULL(10)
489#define CET_WAIT_ENDBR BIT_ULL(11)
490
491#define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */
492#define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */
493#define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */
494#define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */
495#define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */
496
497/* Hardware P state interface */
498#define MSR_PPERF 0x0000064e
499#define MSR_PERF_LIMIT_REASONS 0x0000064f
500#define MSR_PM_ENABLE 0x00000770
501#define MSR_HWP_CAPABILITIES 0x00000771
502#define MSR_HWP_REQUEST_PKG 0x00000772
503#define MSR_HWP_INTERRUPT 0x00000773
504#define MSR_HWP_REQUEST 0x00000774
505#define MSR_HWP_STATUS 0x00000777
506
507/* CPUID.6.EAX */
508#define HWP_BASE_BIT (1<<7)
509#define HWP_NOTIFICATIONS_BIT (1<<8)
510#define HWP_ACTIVITY_WINDOW_BIT (1<<9)
511#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10)
512#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11)
513
514/* IA32_HWP_CAPABILITIES */
515#define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff)
516#define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff)
517#define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff)
518#define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff)
519
520/* IA32_HWP_REQUEST */
521#define HWP_MIN_PERF(x) (x & 0xff)
522#define HWP_MAX_PERF(x) ((x & 0xff) << 8)
523#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16)
524#define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24)
525#define HWP_EPP_PERFORMANCE 0x00
526#define HWP_EPP_BALANCE_PERFORMANCE 0x80
527#define HWP_EPP_BALANCE_POWERSAVE 0xC0
528#define HWP_EPP_POWERSAVE 0xFF
529#define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32)
530#define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42)
531
532/* IA32_HWP_STATUS */
533#define HWP_GUARANTEED_CHANGE(x) (x & 0x1)
534#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4)
535
536/* IA32_HWP_INTERRUPT */
537#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1)
538#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2)
539
540#define MSR_AMD64_MC0_MASK 0xc0010044
541
542#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
543#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
544#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
545#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
546
547#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
548
549/* These are consecutive and not in the normal 4er MCE bank block */
550#define MSR_IA32_MC0_CTL2 0x00000280
551#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
552
553#define MSR_P6_PERFCTR0 0x000000c1
554#define MSR_P6_PERFCTR1 0x000000c2
555#define MSR_P6_EVNTSEL0 0x00000186
556#define MSR_P6_EVNTSEL1 0x00000187
557
558#define MSR_KNC_PERFCTR0 0x00000020
559#define MSR_KNC_PERFCTR1 0x00000021
560#define MSR_KNC_EVNTSEL0 0x00000028
561#define MSR_KNC_EVNTSEL1 0x00000029
562
563/* Alternative perfctr range with full access. */
564#define MSR_IA32_PMC0 0x000004c1
565
566/* Auto-reload via MSR instead of DS area */
567#define MSR_RELOAD_PMC0 0x000014c1
568#define MSR_RELOAD_FIXED_CTR0 0x00001309
569
570/* KeyID partitioning between MKTME and TDX */
571#define MSR_IA32_MKTME_KEYID_PARTITIONING 0x00000087
572
573/*
574 * AMD64 MSRs. Not complete. See the architecture manual for a more
575 * complete list.
576 */
577#define MSR_AMD64_PATCH_LEVEL 0x0000008b
578#define MSR_AMD64_TSC_RATIO 0xc0000104
579#define MSR_AMD64_NB_CFG 0xc001001f
580#define MSR_AMD64_PATCH_LOADER 0xc0010020
581#define MSR_AMD_PERF_CTL 0xc0010062
582#define MSR_AMD_PERF_STATUS 0xc0010063
583#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
584#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
585#define MSR_AMD64_OSVW_STATUS 0xc0010141
586#define MSR_AMD_PPIN_CTL 0xc00102f0
587#define MSR_AMD_PPIN 0xc00102f1
588#define MSR_AMD64_CPUID_FN_1 0xc0011004
589#define MSR_AMD64_LS_CFG 0xc0011020
590#define MSR_AMD64_DC_CFG 0xc0011022
591#define MSR_AMD64_TW_CFG 0xc0011023
592
593#define MSR_AMD64_DE_CFG 0xc0011029
594#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
595#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
596#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9
597
598#define MSR_AMD64_BU_CFG2 0xc001102a
599#define MSR_AMD64_IBSFETCHCTL 0xc0011030
600#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
601#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
602#define MSR_AMD64_IBSFETCH_REG_COUNT 3
603#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
604#define MSR_AMD64_IBSOPCTL 0xc0011033
605#define MSR_AMD64_IBSOPRIP 0xc0011034
606#define MSR_AMD64_IBSOPDATA 0xc0011035
607#define MSR_AMD64_IBSOPDATA2 0xc0011036
608#define MSR_AMD64_IBSOPDATA3 0xc0011037
609#define MSR_AMD64_IBSDCLINAD 0xc0011038
610#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
611#define MSR_AMD64_IBSOP_REG_COUNT 7
612#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
613#define MSR_AMD64_IBSCTL 0xc001103a
614#define MSR_AMD64_IBSBRTARGET 0xc001103b
615#define MSR_AMD64_ICIBSEXTDCTL 0xc001103c
616#define MSR_AMD64_IBSOPDATA4 0xc001103d
617#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
618#define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b
619#define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e
620#define MSR_AMD64_SEV_ES_GHCB 0xc0010130
621#define MSR_AMD64_SEV 0xc0010131
622#define MSR_AMD64_SEV_ENABLED_BIT 0
623#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
624#define MSR_AMD64_SEV_ES_ENABLED_BIT 1
625#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
626#define MSR_AMD64_SEV_SNP_ENABLED_BIT 2
627#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)
628#define MSR_AMD64_SNP_VTOM_BIT 3
629#define MSR_AMD64_SNP_VTOM BIT_ULL(MSR_AMD64_SNP_VTOM_BIT)
630#define MSR_AMD64_SNP_REFLECT_VC_BIT 4
631#define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(MSR_AMD64_SNP_REFLECT_VC_BIT)
632#define MSR_AMD64_SNP_RESTRICTED_INJ_BIT 5
633#define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(MSR_AMD64_SNP_RESTRICTED_INJ_BIT)
634#define MSR_AMD64_SNP_ALT_INJ_BIT 6
635#define MSR_AMD64_SNP_ALT_INJ BIT_ULL(MSR_AMD64_SNP_ALT_INJ_BIT)
636#define MSR_AMD64_SNP_DEBUG_SWAP_BIT 7
637#define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(MSR_AMD64_SNP_DEBUG_SWAP_BIT)
638#define MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT 8
639#define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT)
640#define MSR_AMD64_SNP_BTB_ISOLATION_BIT 9
641#define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(MSR_AMD64_SNP_BTB_ISOLATION_BIT)
642#define MSR_AMD64_SNP_VMPL_SSS_BIT 10
643#define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(MSR_AMD64_SNP_VMPL_SSS_BIT)
644#define MSR_AMD64_SNP_SECURE_TSC_BIT 11
645#define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(MSR_AMD64_SNP_SECURE_TSC_BIT)
646#define MSR_AMD64_SNP_VMGEXIT_PARAM_BIT 12
647#define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(MSR_AMD64_SNP_VMGEXIT_PARAM_BIT)
648#define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13)
649#define MSR_AMD64_SNP_IBS_VIRT_BIT 14
650#define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(MSR_AMD64_SNP_IBS_VIRT_BIT)
651#define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15)
652#define MSR_AMD64_SNP_VMSA_REG_PROT_BIT 16
653#define MSR_AMD64_SNP_VMSA_REG_PROT BIT_ULL(MSR_AMD64_SNP_VMSA_REG_PROT_BIT)
654#define MSR_AMD64_SNP_SMT_PROT_BIT 17
655#define MSR_AMD64_SNP_SMT_PROT BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT)
656#define MSR_AMD64_SNP_RESV_BIT 18
657#define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT)
658
659#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
660
661#define MSR_AMD64_RMP_BASE 0xc0010132
662#define MSR_AMD64_RMP_END 0xc0010133
663
664/* AMD Collaborative Processor Performance Control MSRs */
665#define MSR_AMD_CPPC_CAP1 0xc00102b0
666#define MSR_AMD_CPPC_ENABLE 0xc00102b1
667#define MSR_AMD_CPPC_CAP2 0xc00102b2
668#define MSR_AMD_CPPC_REQ 0xc00102b3
669#define MSR_AMD_CPPC_STATUS 0xc00102b4
670
671#define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff)
672#define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff)
673#define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff)
674#define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff)
675
676#define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0)
677#define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8)
678#define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16)
679#define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24)
680
681/* AMD Performance Counter Global Status and Control MSRs */
682#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300
683#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301
684#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302
685
686/* AMD Last Branch Record MSRs */
687#define MSR_AMD64_LBR_SELECT 0xc000010e
688
689/* Zen4 */
690#define MSR_ZEN4_BP_CFG 0xc001102e
691#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
692
693/* Fam 19h MSRs */
694#define MSR_F19H_UMC_PERF_CTL 0xc0010800
695#define MSR_F19H_UMC_PERF_CTR 0xc0010801
696
697/* Zen 2 */
698#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
699#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1)
700
701/* Fam 17h MSRs */
702#define MSR_F17H_IRPERF 0xc00000e9
703
704/* Fam 16h MSRs */
705#define MSR_F16H_L2I_PERF_CTL 0xc0010230
706#define MSR_F16H_L2I_PERF_CTR 0xc0010231
707#define MSR_F16H_DR1_ADDR_MASK 0xc0011019
708#define MSR_F16H_DR2_ADDR_MASK 0xc001101a
709#define MSR_F16H_DR3_ADDR_MASK 0xc001101b
710#define MSR_F16H_DR0_ADDR_MASK 0xc0011027
711
712/* Fam 15h MSRs */
713#define MSR_F15H_CU_PWR_ACCUMULATOR 0xc001007a
714#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
715#define MSR_F15H_PERF_CTL 0xc0010200
716#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
717#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
718#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4)
719#define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6)
720#define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8)
721#define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10)
722
723#define MSR_F15H_PERF_CTR 0xc0010201
724#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR
725#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2)
726#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4)
727#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6)
728#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8)
729#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10)
730
731#define MSR_F15H_NB_PERF_CTL 0xc0010240
732#define MSR_F15H_NB_PERF_CTR 0xc0010241
733#define MSR_F15H_PTSC 0xc0010280
734#define MSR_F15H_IC_CFG 0xc0011021
735#define MSR_F15H_EX_CFG 0xc001102c
736
737/* Fam 10h MSRs */
738#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
739#define FAM10H_MMIO_CONF_ENABLE (1<<0)
740#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
741#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
742#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
743#define FAM10H_MMIO_CONF_BASE_SHIFT 20
744#define MSR_FAM10H_NODE_ID 0xc001100c
745
746/* K8 MSRs */
747#define MSR_K8_TOP_MEM1 0xc001001a
748#define MSR_K8_TOP_MEM2 0xc001001d
749#define MSR_AMD64_SYSCFG 0xc0010010
750#define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23
751#define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)
752#define MSR_AMD64_SYSCFG_SNP_EN_BIT 24
753#define MSR_AMD64_SYSCFG_SNP_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_EN_BIT)
754#define MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT 25
755#define MSR_AMD64_SYSCFG_SNP_VMPL_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT)
756#define MSR_AMD64_SYSCFG_MFDM_BIT 19
757#define MSR_AMD64_SYSCFG_MFDM BIT_ULL(MSR_AMD64_SYSCFG_MFDM_BIT)
758
759#define MSR_K8_INT_PENDING_MSG 0xc0010055
760/* C1E active bits in int pending message */
761#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
762#define MSR_K8_TSEG_ADDR 0xc0010112
763#define MSR_K8_TSEG_MASK 0xc0010113
764#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
765#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
766#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
767
768/* K7 MSRs */
769#define MSR_K7_EVNTSEL0 0xc0010000
770#define MSR_K7_PERFCTR0 0xc0010004
771#define MSR_K7_EVNTSEL1 0xc0010001
772#define MSR_K7_PERFCTR1 0xc0010005
773#define MSR_K7_EVNTSEL2 0xc0010002
774#define MSR_K7_PERFCTR2 0xc0010006
775#define MSR_K7_EVNTSEL3 0xc0010003
776#define MSR_K7_PERFCTR3 0xc0010007
777#define MSR_K7_CLK_CTL 0xc001001b
778#define MSR_K7_HWCR 0xc0010015
779#define MSR_K7_HWCR_SMMLOCK_BIT 0
780#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
781#define MSR_K7_HWCR_IRPERF_EN_BIT 30
782#define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
783#define MSR_K7_FID_VID_CTL 0xc0010041
784#define MSR_K7_FID_VID_STATUS 0xc0010042
785
786/* K6 MSRs */
787#define MSR_K6_WHCR 0xc0000082
788#define MSR_K6_UWCCR 0xc0000085
789#define MSR_K6_EPMR 0xc0000086
790#define MSR_K6_PSOR 0xc0000087
791#define MSR_K6_PFIR 0xc0000088
792
793/* Centaur-Hauls/IDT defined MSRs. */
794#define MSR_IDT_FCR1 0x00000107
795#define MSR_IDT_FCR2 0x00000108
796#define MSR_IDT_FCR3 0x00000109
797#define MSR_IDT_FCR4 0x0000010a
798
799#define MSR_IDT_MCR0 0x00000110
800#define MSR_IDT_MCR1 0x00000111
801#define MSR_IDT_MCR2 0x00000112
802#define MSR_IDT_MCR3 0x00000113
803#define MSR_IDT_MCR4 0x00000114
804#define MSR_IDT_MCR5 0x00000115
805#define MSR_IDT_MCR6 0x00000116
806#define MSR_IDT_MCR7 0x00000117
807#define MSR_IDT_MCR_CTRL 0x00000120
808
809/* VIA Cyrix defined MSRs*/
810#define MSR_VIA_FCR 0x00001107
811#define MSR_VIA_LONGHAUL 0x0000110a
812#define MSR_VIA_RNG 0x0000110b
813#define MSR_VIA_BCR2 0x00001147
814
815/* Transmeta defined MSRs */
816#define MSR_TMTA_LONGRUN_CTRL 0x80868010
817#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
818#define MSR_TMTA_LRTI_READOUT 0x80868018
819#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
820
821/* Intel defined MSRs. */
822#define MSR_IA32_P5_MC_ADDR 0x00000000
823#define MSR_IA32_P5_MC_TYPE 0x00000001
824#define MSR_IA32_TSC 0x00000010
825#define MSR_IA32_PLATFORM_ID 0x00000017
826#define MSR_IA32_EBL_CR_POWERON 0x0000002a
827#define MSR_EBC_FREQUENCY_ID 0x0000002c
828#define MSR_SMI_COUNT 0x00000034
829
830/* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */
831#define MSR_IA32_FEAT_CTL 0x0000003a
832#define FEAT_CTL_LOCKED BIT(0)
833#define FEAT_CTL_VMX_ENABLED_INSIDE_SMX BIT(1)
834#define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX BIT(2)
835#define FEAT_CTL_SGX_LC_ENABLED BIT(17)
836#define FEAT_CTL_SGX_ENABLED BIT(18)
837#define FEAT_CTL_LMCE_ENABLED BIT(20)
838
839#define MSR_IA32_TSC_ADJUST 0x0000003b
840#define MSR_IA32_BNDCFGS 0x00000d90
841
842#define MSR_IA32_BNDCFGS_RSVD 0x00000ffc
843
844#define MSR_IA32_XFD 0x000001c4
845#define MSR_IA32_XFD_ERR 0x000001c5
846#define MSR_IA32_XSS 0x00000da0
847
848#define MSR_IA32_APICBASE 0x0000001b
849#define MSR_IA32_APICBASE_BSP (1<<8)
850#define MSR_IA32_APICBASE_ENABLE (1<<11)
851#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
852
853#define MSR_IA32_UCODE_WRITE 0x00000079
854#define MSR_IA32_UCODE_REV 0x0000008b
855
856/* Intel SGX Launch Enclave Public Key Hash MSRs */
857#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
858#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
859#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
860#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
861
862#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b
863#define MSR_IA32_SMBASE 0x0000009e
864
865#define MSR_IA32_PERF_STATUS 0x00000198
866#define MSR_IA32_PERF_CTL 0x00000199
867#define INTEL_PERF_CTL_MASK 0xffff
868
869/* AMD Branch Sampling configuration */
870#define MSR_AMD_DBG_EXTN_CFG 0xc000010f
871#define MSR_AMD_SAMP_BR_FROM 0xc0010300
872
873#define DBG_EXTN_CFG_LBRV2EN BIT_ULL(6)
874
875#define MSR_IA32_MPERF 0x000000e7
876#define MSR_IA32_APERF 0x000000e8
877
878#define MSR_IA32_THERM_CONTROL 0x0000019a
879#define MSR_IA32_THERM_INTERRUPT 0x0000019b
880
881#define THERM_INT_HIGH_ENABLE (1 << 0)
882#define THERM_INT_LOW_ENABLE (1 << 1)
883#define THERM_INT_PLN_ENABLE (1 << 24)
884
885#define MSR_IA32_THERM_STATUS 0x0000019c
886
887#define THERM_STATUS_PROCHOT (1 << 0)
888#define THERM_STATUS_POWER_LIMIT (1 << 10)
889
890#define MSR_THERM2_CTL 0x0000019d
891
892#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
893
894#define MSR_IA32_MISC_ENABLE 0x000001a0
895
896#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
897
898#define MSR_MISC_FEATURE_CONTROL 0x000001a4
899#define MSR_MISC_PWR_MGMT 0x000001aa
900
901#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
902#define ENERGY_PERF_BIAS_PERFORMANCE 0
903#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4
904#define ENERGY_PERF_BIAS_NORMAL 6
905#define ENERGY_PERF_BIAS_NORMAL_POWERSAVE 7
906#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8
907#define ENERGY_PERF_BIAS_POWERSAVE 15
908
909#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
910
911#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
912#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
913#define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26)
914
915#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
916
917#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
918#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
919#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
920#define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25)
921
922/* Thermal Thresholds Support */
923#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
924#define THERM_SHIFT_THRESHOLD0 8
925#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
926#define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
927#define THERM_SHIFT_THRESHOLD1 16
928#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
929#define THERM_STATUS_THRESHOLD0 (1 << 6)
930#define THERM_LOG_THRESHOLD0 (1 << 7)
931#define THERM_STATUS_THRESHOLD1 (1 << 8)
932#define THERM_LOG_THRESHOLD1 (1 << 9)
933
934/* MISC_ENABLE bits: architectural */
935#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0
936#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
937#define MSR_IA32_MISC_ENABLE_TCC_BIT 1
938#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
939#define MSR_IA32_MISC_ENABLE_EMON_BIT 7
940#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
941#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11
942#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
943#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12
944#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
945#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16
946#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
947#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18
948#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
949#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22
950#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
951#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23
952#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
953#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34
954#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
955
956/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
957#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2
958#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
959#define MSR_IA32_MISC_ENABLE_TM1_BIT 3
960#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
961#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4
962#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
963#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6
964#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
965#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8
966#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
967#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9
968#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
969#define MSR_IA32_MISC_ENABLE_FERR_BIT 10
970#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
971#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10
972#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
973#define MSR_IA32_MISC_ENABLE_TM2_BIT 13
974#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
975#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19
976#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
977#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20
978#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
979#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24
980#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
981#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37
982#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
983#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38
984#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
985#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
986#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
987
988/* MISC_FEATURES_ENABLES non-architectural features */
989#define MSR_MISC_FEATURES_ENABLES 0x00000140
990
991#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0
992#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)
993#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1
994
995#define MSR_IA32_TSC_DEADLINE 0x000006E0
996
997
998#define MSR_TSX_FORCE_ABORT 0x0000010F
999
1000#define MSR_TFA_RTM_FORCE_ABORT_BIT 0
1001#define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
1002#define MSR_TFA_TSX_CPUID_CLEAR_BIT 1
1003#define MSR_TFA_TSX_CPUID_CLEAR BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT)
1004#define MSR_TFA_SDV_ENABLE_RTM_BIT 2
1005#define MSR_TFA_SDV_ENABLE_RTM BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT)
1006
1007/* P4/Xeon+ specific */
1008#define MSR_IA32_MCG_EAX 0x00000180
1009#define MSR_IA32_MCG_EBX 0x00000181
1010#define MSR_IA32_MCG_ECX 0x00000182
1011#define MSR_IA32_MCG_EDX 0x00000183
1012#define MSR_IA32_MCG_ESI 0x00000184
1013#define MSR_IA32_MCG_EDI 0x00000185
1014#define MSR_IA32_MCG_EBP 0x00000186
1015#define MSR_IA32_MCG_ESP 0x00000187
1016#define MSR_IA32_MCG_EFLAGS 0x00000188
1017#define MSR_IA32_MCG_EIP 0x00000189
1018#define MSR_IA32_MCG_RESERVED 0x0000018a
1019
1020/* Pentium IV performance counter MSRs */
1021#define MSR_P4_BPU_PERFCTR0 0x00000300
1022#define MSR_P4_BPU_PERFCTR1 0x00000301
1023#define MSR_P4_BPU_PERFCTR2 0x00000302
1024#define MSR_P4_BPU_PERFCTR3 0x00000303
1025#define MSR_P4_MS_PERFCTR0 0x00000304
1026#define MSR_P4_MS_PERFCTR1 0x00000305
1027#define MSR_P4_MS_PERFCTR2 0x00000306
1028#define MSR_P4_MS_PERFCTR3 0x00000307
1029#define MSR_P4_FLAME_PERFCTR0 0x00000308
1030#define MSR_P4_FLAME_PERFCTR1 0x00000309
1031#define MSR_P4_FLAME_PERFCTR2 0x0000030a
1032#define MSR_P4_FLAME_PERFCTR3 0x0000030b
1033#define MSR_P4_IQ_PERFCTR0 0x0000030c
1034#define MSR_P4_IQ_PERFCTR1 0x0000030d
1035#define MSR_P4_IQ_PERFCTR2 0x0000030e
1036#define MSR_P4_IQ_PERFCTR3 0x0000030f
1037#define MSR_P4_IQ_PERFCTR4 0x00000310
1038#define MSR_P4_IQ_PERFCTR5 0x00000311
1039#define MSR_P4_BPU_CCCR0 0x00000360
1040#define MSR_P4_BPU_CCCR1 0x00000361
1041#define MSR_P4_BPU_CCCR2 0x00000362
1042#define MSR_P4_BPU_CCCR3 0x00000363
1043#define MSR_P4_MS_CCCR0 0x00000364
1044#define MSR_P4_MS_CCCR1 0x00000365
1045#define MSR_P4_MS_CCCR2 0x00000366
1046#define MSR_P4_MS_CCCR3 0x00000367
1047#define MSR_P4_FLAME_CCCR0 0x00000368
1048#define MSR_P4_FLAME_CCCR1 0x00000369
1049#define MSR_P4_FLAME_CCCR2 0x0000036a
1050#define MSR_P4_FLAME_CCCR3 0x0000036b
1051#define MSR_P4_IQ_CCCR0 0x0000036c
1052#define MSR_P4_IQ_CCCR1 0x0000036d
1053#define MSR_P4_IQ_CCCR2 0x0000036e
1054#define MSR_P4_IQ_CCCR3 0x0000036f
1055#define MSR_P4_IQ_CCCR4 0x00000370
1056#define MSR_P4_IQ_CCCR5 0x00000371
1057#define MSR_P4_ALF_ESCR0 0x000003ca
1058#define MSR_P4_ALF_ESCR1 0x000003cb
1059#define MSR_P4_BPU_ESCR0 0x000003b2
1060#define MSR_P4_BPU_ESCR1 0x000003b3
1061#define MSR_P4_BSU_ESCR0 0x000003a0
1062#define MSR_P4_BSU_ESCR1 0x000003a1
1063#define MSR_P4_CRU_ESCR0 0x000003b8
1064#define MSR_P4_CRU_ESCR1 0x000003b9
1065#define MSR_P4_CRU_ESCR2 0x000003cc
1066#define MSR_P4_CRU_ESCR3 0x000003cd
1067#define MSR_P4_CRU_ESCR4 0x000003e0
1068#define MSR_P4_CRU_ESCR5 0x000003e1
1069#define MSR_P4_DAC_ESCR0 0x000003a8
1070#define MSR_P4_DAC_ESCR1 0x000003a9
1071#define MSR_P4_FIRM_ESCR0 0x000003a4
1072#define MSR_P4_FIRM_ESCR1 0x000003a5
1073#define MSR_P4_FLAME_ESCR0 0x000003a6
1074#define MSR_P4_FLAME_ESCR1 0x000003a7
1075#define MSR_P4_FSB_ESCR0 0x000003a2
1076#define MSR_P4_FSB_ESCR1 0x000003a3
1077#define MSR_P4_IQ_ESCR0 0x000003ba
1078#define MSR_P4_IQ_ESCR1 0x000003bb
1079#define MSR_P4_IS_ESCR0 0x000003b4
1080#define MSR_P4_IS_ESCR1 0x000003b5
1081#define MSR_P4_ITLB_ESCR0 0x000003b6
1082#define MSR_P4_ITLB_ESCR1 0x000003b7
1083#define MSR_P4_IX_ESCR0 0x000003c8
1084#define MSR_P4_IX_ESCR1 0x000003c9
1085#define MSR_P4_MOB_ESCR0 0x000003aa
1086#define MSR_P4_MOB_ESCR1 0x000003ab
1087#define MSR_P4_MS_ESCR0 0x000003c0
1088#define MSR_P4_MS_ESCR1 0x000003c1
1089#define MSR_P4_PMH_ESCR0 0x000003ac
1090#define MSR_P4_PMH_ESCR1 0x000003ad
1091#define MSR_P4_RAT_ESCR0 0x000003bc
1092#define MSR_P4_RAT_ESCR1 0x000003bd
1093#define MSR_P4_SAAT_ESCR0 0x000003ae
1094#define MSR_P4_SAAT_ESCR1 0x000003af
1095#define MSR_P4_SSU_ESCR0 0x000003be
1096#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
1097
1098#define MSR_P4_TBPU_ESCR0 0x000003c2
1099#define MSR_P4_TBPU_ESCR1 0x000003c3
1100#define MSR_P4_TC_ESCR0 0x000003c4
1101#define MSR_P4_TC_ESCR1 0x000003c5
1102#define MSR_P4_U2L_ESCR0 0x000003b0
1103#define MSR_P4_U2L_ESCR1 0x000003b1
1104
1105#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
1106
1107/* Intel Core-based CPU performance counters */
1108#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
1109#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
1110#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
1111#define MSR_CORE_PERF_FIXED_CTR3 0x0000030c
1112#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
1113#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
1114#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
1115#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
1116
1117#define MSR_PERF_METRICS 0x00000329
1118
1119/* PERF_GLOBAL_OVF_CTL bits */
1120#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT 55
1121#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
1122#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT 62
1123#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT)
1124#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT 63
1125#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD (1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT)
1126
1127/* Geode defined MSRs */
1128#define MSR_GEODE_BUSCONT_CONF0 0x00001900
1129
1130/* Intel VT MSRs */
1131#define MSR_IA32_VMX_BASIC 0x00000480
1132#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
1133#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
1134#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
1135#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
1136#define MSR_IA32_VMX_MISC 0x00000485
1137#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
1138#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
1139#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
1140#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
1141#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
1142#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
1143#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
1144#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
1145#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
1146#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
1147#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
1148#define MSR_IA32_VMX_VMFUNC 0x00000491
1149#define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492
1150
1151/* VMX_BASIC bits and bitmasks */
1152#define VMX_BASIC_VMCS_SIZE_SHIFT 32
1153#define VMX_BASIC_TRUE_CTLS (1ULL << 55)
1154#define VMX_BASIC_64 0x0001000000000000LLU
1155#define VMX_BASIC_MEM_TYPE_SHIFT 50
1156#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
1157#define VMX_BASIC_MEM_TYPE_WB 6LLU
1158#define VMX_BASIC_INOUT 0x0040000000000000LLU
1159
1160/* Resctrl MSRs: */
1161/* - Intel: */
1162#define MSR_IA32_L3_QOS_CFG 0xc81
1163#define MSR_IA32_L2_QOS_CFG 0xc82
1164#define MSR_IA32_QM_EVTSEL 0xc8d
1165#define MSR_IA32_QM_CTR 0xc8e
1166#define MSR_IA32_PQR_ASSOC 0xc8f
1167#define MSR_IA32_L3_CBM_BASE 0xc90
1168#define MSR_IA32_L2_CBM_BASE 0xd10
1169#define MSR_IA32_MBA_THRTL_BASE 0xd50
1170
1171/* - AMD: */
1172#define MSR_IA32_MBA_BW_BASE 0xc0000200
1173#define MSR_IA32_SMBA_BW_BASE 0xc0000280
1174#define MSR_IA32_EVT_CFG_BASE 0xc0000400
1175
1176/* MSR_IA32_VMX_MISC bits */
1177#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)
1178#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
1179#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
1180
1181/* AMD-V MSRs */
1182#define MSR_VM_CR 0xc0010114
1183#define MSR_VM_IGNNE 0xc0010115
1184#define MSR_VM_HSAVE_PA 0xc0010117
1185
1186#define SVM_VM_CR_VALID_MASK 0x001fULL
1187#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
1188#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
1189
1190/* Hardware Feedback Interface */
1191#define MSR_IA32_HW_FEEDBACK_PTR 0x17d0
1192#define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1
1193
1194/* x2APIC locked status */
1195#define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD
1196#define LEGACY_XAPIC_DISABLED BIT(0) /*
1197 * x2APIC mode is locked and
1198 * disabling x2APIC will cause
1199 * a #GP
1200 */
1201
1202#endif /* _ASM_X86_MSR_INDEX_H */
1203

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source code of linux/arch/x86/include/asm/msr-index.h