| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef _ASM_X86_PROCESSOR_FLAGS_H |
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| 3 | #define _ASM_X86_PROCESSOR_FLAGS_H |
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| 4 | |
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| 5 | #include <uapi/asm/processor-flags.h> |
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| 6 | #include <linux/mem_encrypt.h> |
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| 7 | |
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| 8 | #ifdef CONFIG_VM86 |
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| 9 | #define X86_VM_MASK X86_EFLAGS_VM |
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| 10 | #else |
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| 11 | #define X86_VM_MASK 0 /* No VM86 support */ |
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| 12 | #endif |
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| 13 | |
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| 14 | /* |
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| 15 | * CR3's layout varies depending on several things. |
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| 16 | * |
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| 17 | * If CR4.PCIDE is set (64-bit only), then CR3[11:0] is the address space ID. |
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| 18 | * If PAE is enabled, then CR3[11:5] is part of the PDPT address |
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| 19 | * (i.e. it's 32-byte aligned, not page-aligned) and CR3[4:0] is ignored. |
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| 20 | * Otherwise (non-PAE, non-PCID), CR3[3] is PWT, CR3[4] is PCD, and |
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| 21 | * CR3[2:0] and CR3[11:5] are ignored. |
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| 22 | * |
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| 23 | * In all cases, Linux puts zeros in the low ignored bits and in PWT and PCD. |
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| 24 | * |
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| 25 | * CR3[63] is always read as zero. If CR4.PCIDE is set, then CR3[63] may be |
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| 26 | * written as 1 to prevent the write to CR3 from flushing the TLB. |
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| 27 | * |
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| 28 | * On systems with SME, one bit (in a variable position!) is stolen to indicate |
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| 29 | * that the top-level paging structure is encrypted. |
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| 30 | * |
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| 31 | * On systemms with LAM, bits 61 and 62 are used to indicate LAM mode. |
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| 32 | * |
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| 33 | * All of the remaining bits indicate the physical address of the top-level |
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| 34 | * paging structure. |
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| 35 | * |
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| 36 | * CR3_ADDR_MASK is the mask used by read_cr3_pa(). |
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| 37 | */ |
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| 38 | #ifdef CONFIG_X86_64 |
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| 39 | /* Mask off the address space ID and SME encryption bits. */ |
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| 40 | #define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK) |
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| 41 | #define CR3_PCID_MASK 0xFFFull |
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| 42 | #define CR3_NOFLUSH BIT_ULL(63) |
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| 43 | |
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| 44 | #else |
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| 45 | /* |
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| 46 | * CR3_ADDR_MASK needs at least bits 31:5 set on PAE systems, and we save |
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| 47 | * a tiny bit of code size by setting all the bits. |
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| 48 | */ |
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| 49 | #define CR3_ADDR_MASK 0xFFFFFFFFull |
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| 50 | #define CR3_PCID_MASK 0ull |
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| 51 | #define CR3_NOFLUSH 0 |
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| 52 | #endif |
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| 53 | |
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| 54 | #ifdef CONFIG_PAGE_TABLE_ISOLATION |
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| 55 | # define X86_CR3_PTI_PCID_USER_BIT 11 |
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| 56 | #endif |
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| 57 | |
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| 58 | #endif /* _ASM_X86_PROCESSOR_FLAGS_H */ |
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| 59 | |
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