1// SPDX-License-Identifier: GPL-2.0
2#include <linux/sched.h>
3#include <linux/sched/clock.h>
4
5#include <asm/cpu.h>
6#include <asm/cpufeature.h>
7
8#include "cpu.h"
9
10#define MSR_ZHAOXIN_FCR57 0x00001257
11
12#define ACE_PRESENT (1 << 6)
13#define ACE_ENABLED (1 << 7)
14#define ACE_FCR (1 << 7) /* MSR_ZHAOXIN_FCR */
15
16#define RNG_PRESENT (1 << 2)
17#define RNG_ENABLED (1 << 3)
18#define RNG_ENABLE (1 << 8) /* MSR_ZHAOXIN_RNG */
19
20static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
21{
22 u32 lo, hi;
23
24 /* Test for Extended Feature Flags presence */
25 if (cpuid_eax(op: 0xC0000000) >= 0xC0000001) {
26 u32 tmp = cpuid_edx(op: 0xC0000001);
27
28 /* Enable ACE unit, if present and disabled */
29 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
30 rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
31 /* Enable ACE unit */
32 lo |= ACE_FCR;
33 wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
34 pr_info("CPU: Enabled ACE h/w crypto\n");
35 }
36
37 /* Enable RNG unit, if present and disabled */
38 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
39 rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
40 /* Enable RNG unit */
41 lo |= RNG_ENABLE;
42 wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
43 pr_info("CPU: Enabled h/w RNG\n");
44 }
45
46 /*
47 * Store Extended Feature Flags as word 5 of the CPU
48 * capability bit array
49 */
50 c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(op: 0xC0000001);
51 }
52
53 if (c->x86 >= 0x6)
54 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
55}
56
57static void early_init_zhaoxin(struct cpuinfo_x86 *c)
58{
59 if (c->x86 >= 0x6)
60 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
61#ifdef CONFIG_X86_64
62 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
63#endif
64 if (c->x86_power & (1 << 8)) {
65 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
66 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
67 }
68}
69
70static void init_zhaoxin(struct cpuinfo_x86 *c)
71{
72 early_init_zhaoxin(c);
73 init_intel_cacheinfo(c);
74
75 if (c->cpuid_level > 9) {
76 unsigned int eax = cpuid_eax(op: 10);
77
78 /*
79 * Check for version and the number of counters
80 * Version(eax[7:0]) can't be 0;
81 * Counters(eax[15:8]) should be greater than 1;
82 */
83 if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
84 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
85 }
86
87 if (c->x86 >= 0x6)
88 init_zhaoxin_cap(c);
89#ifdef CONFIG_X86_64
90 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
91#endif
92
93 init_ia32_feat_ctl(c);
94}
95
96#ifdef CONFIG_X86_32
97static unsigned int
98zhaoxin_size_cache(struct cpuinfo_x86 *c, unsigned int size)
99{
100 return size;
101}
102#endif
103
104static const struct cpu_dev zhaoxin_cpu_dev = {
105 .c_vendor = "zhaoxin",
106 .c_ident = { " Shanghai " },
107 .c_early_init = early_init_zhaoxin,
108 .c_init = init_zhaoxin,
109#ifdef CONFIG_X86_32
110 .legacy_cache_size = zhaoxin_size_cache,
111#endif
112 .c_x86_vendor = X86_VENDOR_ZHAOXIN,
113};
114
115cpu_dev_register(zhaoxin_cpu_dev);
116

source code of linux/arch/x86/kernel/cpu/zhaoxin.c