| 1 | /* SPDX-License-Identifier: GPL-2.0 |
| 2 | * |
| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | /************************************ |
| 9 | ** This is an auto-generated file ** |
| 10 | ** DO NOT EDIT BELOW ** |
| 11 | ************************************/ |
| 12 | |
| 13 | #ifndef ASIC_REG_ROT0_REGS_H_ |
| 14 | #define ASIC_REG_ROT0_REGS_H_ |
| 15 | |
| 16 | /* |
| 17 | ***************************************** |
| 18 | * ROT0 |
| 19 | * (Prototype: ROTATOR) |
| 20 | ***************************************** |
| 21 | */ |
| 22 | |
| 23 | #define mmROT0_KMD_MODE 0x4E0B000 |
| 24 | |
| 25 | #define mmROT0_CPL_QUEUE_EN 0x4E0B004 |
| 26 | |
| 27 | #define mmROT0_CPL_QUEUE_ADDR_L 0x4E0B008 |
| 28 | |
| 29 | #define mmROT0_CPL_QUEUE_ADDR_H 0x4E0B00C |
| 30 | |
| 31 | #define mmROT0_CPL_QUEUE_DATA 0x4E0B010 |
| 32 | |
| 33 | #define mmROT0_CPL_QUEUE_AWUSER 0x4E0B014 |
| 34 | |
| 35 | #define mmROT0_CPL_QUEUE_AXI 0x4E0B018 |
| 36 | |
| 37 | #define mmROT0_CPL_MSG_THRESHOLD 0x4E0B020 |
| 38 | |
| 39 | #define mmROT0_CPL_MSG_AXI 0x4E0B024 |
| 40 | |
| 41 | #define mmROT0_AXI_WB 0x4E0B028 |
| 42 | |
| 43 | #define mmROT0_ERR_CFG 0x4E0B02C |
| 44 | |
| 45 | #define mmROT0_ERR_STATUS 0x4E0B030 |
| 46 | |
| 47 | #define mmROT0_WBC_MAX_OUTSTANDING 0x4E0B038 |
| 48 | |
| 49 | #define mmROT0_WBC_RL 0x4E0B03C |
| 50 | |
| 51 | #define mmROT0_WBC_INFLIGHTS 0x4E0B040 |
| 52 | |
| 53 | #define mmROT0_WBC_INFO 0x4E0B044 |
| 54 | |
| 55 | #define mmROT0_WBC_MON 0x4E0B048 |
| 56 | |
| 57 | #define mmROT0_RSB_CAM_MAX_SIZE 0x4E0B04C |
| 58 | |
| 59 | #define mmROT0_RSB_CFG 0x4E0B050 |
| 60 | |
| 61 | #define mmROT0_RSB_MAX_OS 0x4E0B054 |
| 62 | |
| 63 | #define mmROT0_RSB_RL 0x4E0B058 |
| 64 | |
| 65 | #define mmROT0_RSB_INFLIGHTS 0x4E0B05C |
| 66 | |
| 67 | #define mmROT0_RSB_OCCUPANCY 0x4E0B060 |
| 68 | |
| 69 | #define mmROT0_RSB_INFO 0x4E0B064 |
| 70 | |
| 71 | #define mmROT0_RSB_MON 0x4E0B068 |
| 72 | |
| 73 | #define mmROT0_RSB_MON_CONTEXT_ID 0x4E0B06C |
| 74 | |
| 75 | #define mmROT0_MSS_HALT 0x4E0B070 |
| 76 | |
| 77 | #define mmROT0_MSS_SEI_STATUS 0x4E0B074 |
| 78 | |
| 79 | #define mmROT0_MSS_SEI_MASK 0x4E0B078 |
| 80 | |
| 81 | #define mmROT0_MSS_SPI_STATUS 0x4E0B07C |
| 82 | |
| 83 | #define mmROT0_MSS_SPI_MASK 0x4E0B080 |
| 84 | |
| 85 | #define mmROT0_DISABLE_PAD_CALC 0x4E0B084 |
| 86 | |
| 87 | #define mmROT0_QMAN_CFG 0x4E0B088 |
| 88 | |
| 89 | #define mmROT0_CLK_EN 0x4E0B08C |
| 90 | |
| 91 | #define mmROT0_MRSB_CAM_MAX_SIZE 0x4E0B090 |
| 92 | |
| 93 | #define mmROT0_MRSB_CFG 0x4E0B094 |
| 94 | |
| 95 | #define mmROT0_MRSB_MAX_OS 0x4E0B098 |
| 96 | |
| 97 | #define mmROT0_MRSB_RL 0x4E0B09C |
| 98 | |
| 99 | #define mmROT0_MRSB_INFLIGHTS 0x4E0B0A0 |
| 100 | |
| 101 | #define mmROT0_MRSB_OCCUPANCY 0x4E0B0A4 |
| 102 | |
| 103 | #define mmROT0_MRSB_INFO 0x4E0B0A8 |
| 104 | |
| 105 | #define mmROT0_MRSB_MON 0x4E0B0AC |
| 106 | |
| 107 | #define mmROT0_MRSB_MON_CONTEXT_ID 0x4E0B0B0 |
| 108 | |
| 109 | #define mmROT0_MSS_STS 0x4E0B0B4 |
| 110 | |
| 111 | #endif /* ASIC_REG_ROT0_REGS_H_ */ |
| 112 | |