1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2020-2025 Intel Corporation
4 */
5
6#ifndef __IVPU_DRV_H__
7#define __IVPU_DRV_H__
8
9#include <drm/drm_device.h>
10#include <drm/drm_drv.h>
11#include <drm/drm_managed.h>
12#include <drm/drm_mm.h>
13#include <drm/drm_print.h>
14
15#include <linux/pci.h>
16#include <linux/xarray.h>
17#include <uapi/drm/ivpu_accel.h>
18
19#include "ivpu_mmu_context.h"
20#include "ivpu_ipc.h"
21
22#define DRIVER_NAME "intel_vpu"
23#define DRIVER_DESC "Driver for Intel NPU (Neural Processing Unit)"
24
25#define PCI_DEVICE_ID_MTL 0x7d1d
26#define PCI_DEVICE_ID_ARL 0xad1d
27#define PCI_DEVICE_ID_LNL 0x643e
28#define PCI_DEVICE_ID_PTL_P 0xb03e
29#define PCI_DEVICE_ID_WCL 0xfd3e
30#define PCI_DEVICE_ID_NVL 0xd71d
31
32#define IVPU_HW_IP_37XX 37
33#define IVPU_HW_IP_40XX 40
34#define IVPU_HW_IP_50XX 50
35#define IVPU_HW_IP_60XX 60
36
37#define IVPU_HW_IP_REV_LNL_B0 4
38
39#define IVPU_HW_BTRS_MTL 1
40#define IVPU_HW_BTRS_LNL 2
41
42#define IVPU_GLOBAL_CONTEXT_MMU_SSID 0
43/* SSID 1 is used by the VPU to represent reserved context */
44#define IVPU_RESERVED_CONTEXT_MMU_SSID 1
45#define IVPU_USER_CONTEXT_MIN_SSID 2
46#define IVPU_USER_CONTEXT_MAX_SSID (IVPU_USER_CONTEXT_MIN_SSID + 63)
47
48#define IVPU_MIN_DB 1
49#define IVPU_MAX_DB 255
50
51#define IVPU_JOB_ID_JOB_MASK GENMASK(7, 0)
52#define IVPU_JOB_ID_CONTEXT_MASK GENMASK(31, 8)
53
54#define IVPU_NUM_PRIORITIES 4
55#define IVPU_NUM_CMDQS_PER_CTX (IVPU_NUM_PRIORITIES)
56
57#define IVPU_CMDQ_MIN_ID 1
58#define IVPU_CMDQ_MAX_ID 255
59
60#define IVPU_PLATFORM_SILICON 0
61#define IVPU_PLATFORM_SIMICS 2
62#define IVPU_PLATFORM_FPGA 3
63#define IVPU_PLATFORM_HSLE 4
64#define IVPU_PLATFORM_INVALID 8
65
66#define IVPU_SCHED_MODE_AUTO -1
67
68#define IVPU_DBG_REG BIT(0)
69#define IVPU_DBG_IRQ BIT(1)
70#define IVPU_DBG_MMU BIT(2)
71#define IVPU_DBG_FILE BIT(3)
72#define IVPU_DBG_MISC BIT(4)
73#define IVPU_DBG_FW_BOOT BIT(5)
74#define IVPU_DBG_PM BIT(6)
75#define IVPU_DBG_IPC BIT(7)
76#define IVPU_DBG_BO BIT(8)
77#define IVPU_DBG_JOB BIT(9)
78#define IVPU_DBG_JSM BIT(10)
79#define IVPU_DBG_KREF BIT(11)
80#define IVPU_DBG_RPM BIT(12)
81#define IVPU_DBG_MMU_MAP BIT(13)
82#define IVPU_DBG_IOCTL BIT(14)
83
84#define ivpu_err(vdev, fmt, ...) \
85 drm_err(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
86
87#define ivpu_err_ratelimited(vdev, fmt, ...) \
88 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
89
90#define ivpu_warn(vdev, fmt, ...) \
91 drm_warn(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
92
93#define ivpu_warn_ratelimited(vdev, fmt, ...) \
94 drm_err_ratelimited(&(vdev)->drm, "%s(): " fmt, __func__, ##__VA_ARGS__)
95
96#define ivpu_info(vdev, fmt, ...) drm_info(&(vdev)->drm, fmt, ##__VA_ARGS__)
97
98#define ivpu_dbg(vdev, type, fmt, args...) do { \
99 if (unlikely(IVPU_DBG_##type & ivpu_dbg_mask)) \
100 dev_dbg((vdev)->drm.dev, "[%s] " fmt, #type, ##args); \
101} while (0)
102
103#define IVPU_WA(wa_name) (vdev->wa.wa_name)
104
105#define IVPU_PRINT_WA(wa_name) do { \
106 if (IVPU_WA(wa_name)) \
107 ivpu_dbg(vdev, MISC, "Using WA: " #wa_name "\n"); \
108} while (0)
109
110struct ivpu_wa_table {
111 bool punit_disabled;
112 bool clear_runtime_mem;
113 bool interrupt_clear_with_0;
114 bool disable_clock_relinquish;
115 bool disable_d0i3_msg;
116 bool wp0_during_power_up;
117 bool disable_d0i2;
118};
119
120struct ivpu_hw_info;
121struct ivpu_mmu_info;
122struct ivpu_fw_info;
123struct ivpu_ipc_info;
124struct ivpu_pm_info;
125
126struct ivpu_device {
127 struct drm_device drm;
128 void __iomem *regb;
129 void __iomem *regv;
130 u32 platform;
131 u32 irq;
132
133 struct ivpu_wa_table wa;
134 struct ivpu_hw_info *hw;
135 struct ivpu_mmu_info *mmu;
136 struct ivpu_fw_info *fw;
137 struct ivpu_ipc_info *ipc;
138 struct ivpu_pm_info *pm;
139
140 struct ivpu_mmu_context gctx;
141 struct ivpu_mmu_context rctx;
142 struct mutex context_list_lock; /* Protects user context addition/removal */
143 struct xarray context_xa;
144 struct xa_limit context_xa_limit;
145
146 struct xarray db_xa;
147 struct xa_limit db_limit;
148 u32 db_next;
149
150 struct work_struct irq_ipc_work;
151 struct work_struct irq_dct_work;
152 struct work_struct context_abort_work;
153
154 struct mutex bo_list_lock; /* Protects bo_list */
155 struct list_head bo_list;
156
157 struct mutex submitted_jobs_lock; /* Protects submitted_jobs */
158 struct xarray submitted_jobs_xa;
159 struct ivpu_ipc_consumer job_done_consumer;
160 atomic_t job_timeout_counter;
161
162 atomic64_t unique_id_counter;
163
164 ktime_t busy_start_ts;
165 ktime_t busy_time;
166
167 struct {
168 int boot;
169 int jsm;
170 int tdr;
171 int inference;
172 int autosuspend;
173 int d0i3_entry_msg;
174 int state_dump_msg;
175 } timeout;
176};
177
178/*
179 * file_priv has its own refcount (ref) that allows user space to close the fd
180 * without blocking even if VPU is still processing some jobs.
181 */
182struct ivpu_file_priv {
183 struct kref ref;
184 struct ivpu_device *vdev;
185 struct mutex lock; /* Protects cmdq */
186 struct xarray cmdq_xa;
187 struct ivpu_mmu_context ctx;
188 struct mutex ms_lock; /* Protects ms_instance_list, ms_info_bo */
189 struct list_head ms_instance_list;
190 struct ivpu_bo *ms_info_bo;
191 struct xa_limit job_limit;
192 u32 job_id_next;
193 struct xa_limit cmdq_limit;
194 u32 cmdq_id_next;
195 bool has_mmu_faults;
196 bool bound;
197 bool aborted;
198};
199
200extern int ivpu_dbg_mask;
201extern u8 ivpu_pll_min_ratio;
202extern u8 ivpu_pll_max_ratio;
203extern int ivpu_sched_mode;
204extern bool ivpu_disable_mmu_cont_pages;
205extern bool ivpu_force_snoop;
206
207#define IVPU_TEST_MODE_FW_TEST BIT(0)
208#define IVPU_TEST_MODE_NULL_HW BIT(1)
209#define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2)
210#define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4)
211#define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5)
212#define IVPU_TEST_MODE_MIP_DISABLE BIT(6)
213#define IVPU_TEST_MODE_DISABLE_TIMEOUTS BIT(8)
214#define IVPU_TEST_MODE_TURBO_ENABLE BIT(9)
215#define IVPU_TEST_MODE_TURBO_DISABLE BIT(10)
216#define IVPU_TEST_MODE_CLK_RELINQ_DISABLE BIT(11)
217#define IVPU_TEST_MODE_CLK_RELINQ_ENABLE BIT(12)
218#define IVPU_TEST_MODE_D0I2_DISABLE BIT(13)
219extern int ivpu_test_mode;
220
221struct ivpu_file_priv *ivpu_file_priv_get(struct ivpu_file_priv *file_priv);
222void ivpu_file_priv_put(struct ivpu_file_priv **link);
223
224int ivpu_boot(struct ivpu_device *vdev);
225int ivpu_shutdown(struct ivpu_device *vdev);
226void ivpu_prepare_for_reset(struct ivpu_device *vdev);
227bool ivpu_is_capable(struct ivpu_device *vdev, u32 capability);
228
229static inline u8 ivpu_revision(struct ivpu_device *vdev)
230{
231 return to_pci_dev(vdev->drm.dev)->revision;
232}
233
234static inline u16 ivpu_device_id(struct ivpu_device *vdev)
235{
236 return to_pci_dev(vdev->drm.dev)->device;
237}
238
239static inline int ivpu_hw_ip_gen(struct ivpu_device *vdev)
240{
241 switch (ivpu_device_id(vdev)) {
242 case PCI_DEVICE_ID_MTL:
243 case PCI_DEVICE_ID_ARL:
244 return IVPU_HW_IP_37XX;
245 case PCI_DEVICE_ID_LNL:
246 return IVPU_HW_IP_40XX;
247 case PCI_DEVICE_ID_PTL_P:
248 case PCI_DEVICE_ID_WCL:
249 return IVPU_HW_IP_50XX;
250 case PCI_DEVICE_ID_NVL:
251 return IVPU_HW_IP_60XX;
252 default:
253 dump_stack();
254 ivpu_err(vdev, "Unknown NPU IP generation\n");
255 return 0;
256 }
257}
258
259static inline int ivpu_hw_btrs_gen(struct ivpu_device *vdev)
260{
261 switch (ivpu_device_id(vdev)) {
262 case PCI_DEVICE_ID_MTL:
263 case PCI_DEVICE_ID_ARL:
264 return IVPU_HW_BTRS_MTL;
265 case PCI_DEVICE_ID_LNL:
266 case PCI_DEVICE_ID_PTL_P:
267 case PCI_DEVICE_ID_WCL:
268 case PCI_DEVICE_ID_NVL:
269 return IVPU_HW_BTRS_LNL;
270 default:
271 dump_stack();
272 ivpu_err(vdev, "Unknown buttress generation\n");
273 return 0;
274 }
275}
276
277static inline struct ivpu_device *to_ivpu_device(struct drm_device *dev)
278{
279 return container_of(dev, struct ivpu_device, drm);
280}
281
282static inline u32 ivpu_get_context_count(struct ivpu_device *vdev)
283{
284 struct xa_limit ctx_limit = vdev->context_xa_limit;
285
286 return (ctx_limit.max - ctx_limit.min + 1);
287}
288
289static inline u32 ivpu_get_platform(struct ivpu_device *vdev)
290{
291 WARN_ON_ONCE(vdev->platform == IVPU_PLATFORM_INVALID);
292 return vdev->platform;
293}
294
295static inline bool ivpu_is_silicon(struct ivpu_device *vdev)
296{
297 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SILICON;
298}
299
300static inline bool ivpu_is_simics(struct ivpu_device *vdev)
301{
302 return ivpu_get_platform(vdev) == IVPU_PLATFORM_SIMICS;
303}
304
305static inline bool ivpu_is_fpga(struct ivpu_device *vdev)
306{
307 return ivpu_get_platform(vdev) == IVPU_PLATFORM_FPGA ||
308 ivpu_get_platform(vdev) == IVPU_PLATFORM_HSLE;
309}
310
311static inline bool ivpu_is_force_snoop_enabled(struct ivpu_device *vdev)
312{
313 return ivpu_force_snoop;
314}
315
316#endif /* __IVPU_DRV_H__ */
317

source code of linux/drivers/accel/ivpu/ivpu_drv.h