| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2020-2023 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __IVPU_HW_40XX_REG_H__ |
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| 7 | #define __IVPU_HW_40XX_REG_H__ |
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| 8 | |
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| 9 | #include <linux/bits.h> |
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| 10 | |
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| 11 | #define VPU_40XX_BUTTRESS_INTERRUPT_STAT 0x00000000u |
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| 12 | #define VPU_40XX_BUTTRESS_INTERRUPT_STAT_FREQ_CHANGE_MASK BIT_MASK(0) |
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| 13 | #define VPU_40XX_BUTTRESS_INTERRUPT_STAT_ATS_ERR_MASK BIT_MASK(1) |
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| 14 | #define VPU_40XX_BUTTRESS_INTERRUPT_STAT_CFI0_ERR_MASK BIT_MASK(2) |
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| 15 | #define VPU_40XX_BUTTRESS_INTERRUPT_STAT_CFI1_ERR_MASK BIT_MASK(3) |
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| 16 | #define VPU_40XX_BUTTRESS_INTERRUPT_STAT_IMR0_ERR_MASK BIT_MASK(4) |
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| 17 | #define VPU_40XX_BUTTRESS_INTERRUPT_STAT_IMR1_ERR_MASK BIT_MASK(5) |
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| 18 | #define VPU_40XX_BUTTRESS_INTERRUPT_STAT_SURV_ERR_MASK BIT_MASK(6) |
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| 19 | |
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| 20 | #define VPU_40XX_BUTTRESS_LOCAL_INT_MASK 0x00000004u |
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| 21 | #define VPU_40XX_BUTTRESS_GLOBAL_INT_MASK 0x00000008u |
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| 22 | |
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| 23 | #define VPU_40XX_BUTTRESS_HM_ATS 0x0000000cu |
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| 24 | |
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| 25 | #define VPU_40XX_BUTTRESS_ATS_ERR_LOG1 0x00000010u |
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| 26 | #define VPU_40XX_BUTTRESS_ATS_ERR_LOG2 0x00000014u |
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| 27 | #define VPU_40XX_BUTTRESS_ATS_ERR_CLEAR 0x00000018u |
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| 28 | |
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| 29 | #define VPU_40XX_BUTTRESS_CFI0_ERR_LOG 0x0000001cu |
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| 30 | #define VPU_40XX_BUTTRESS_CFI0_ERR_CLEAR 0x00000020u |
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| 31 | |
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| 32 | #define VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS_ATS 0x00000024u |
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| 33 | |
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| 34 | #define VPU_40XX_BUTTRESS_CFI1_ERR_LOG 0x00000040u |
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| 35 | #define VPU_40XX_BUTTRESS_CFI1_ERR_CLEAR 0x00000044u |
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| 36 | |
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| 37 | #define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_LOW 0x00000048u |
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| 38 | #define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_HIGH 0x0000004cu |
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| 39 | #define VPU_40XX_BUTTRESS_IMR_ERR_CFI0_CLEAR 0x00000050u |
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| 40 | |
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| 41 | #define VPU_40XX_BUTTRESS_PORT_ARBITRATION_WEIGHTS 0x00000054u |
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| 42 | |
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| 43 | #define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_LOW 0x00000058u |
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| 44 | #define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_HIGH 0x0000005cu |
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| 45 | #define VPU_40XX_BUTTRESS_IMR_ERR_CFI1_CLEAR 0x00000060u |
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| 46 | |
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| 47 | #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0 0x00000130u |
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| 48 | #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0_MIN_RATIO_MASK GENMASK(15, 0) |
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| 49 | #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0_MAX_RATIO_MASK GENMASK(31, 16) |
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| 50 | |
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| 51 | #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1 0x00000134u |
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| 52 | #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1_TARGET_RATIO_MASK GENMASK(15, 0) |
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| 53 | #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1_EPP_MASK GENMASK(31, 16) |
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| 54 | |
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| 55 | #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2 0x00000138u |
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| 56 | #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2_CONFIG_MASK GENMASK(15, 0) |
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| 57 | #define VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2_CDYN_MASK GENMASK(31, 16) |
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| 58 | |
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| 59 | #define VPU_40XX_BUTTRESS_WP_REQ_CMD 0x0000013cu |
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| 60 | #define VPU_40XX_BUTTRESS_WP_REQ_CMD_SEND_MASK BIT_MASK(0) |
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| 61 | |
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| 62 | #define VPU_40XX_BUTTRESS_PLL_FREQ 0x00000148u |
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| 63 | #define VPU_40XX_BUTTRESS_PLL_FREQ_RATIO_MASK GENMASK(15, 0) |
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| 64 | |
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| 65 | #define VPU_40XX_BUTTRESS_TILE_FUSE 0x00000150u |
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| 66 | #define VPU_40XX_BUTTRESS_TILE_FUSE_VALID_MASK BIT_MASK(0) |
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| 67 | #define VPU_40XX_BUTTRESS_TILE_FUSE_CONFIG_MASK GENMASK(6, 1) |
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| 68 | |
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| 69 | #define VPU_40XX_BUTTRESS_VPU_STATUS 0x00000154u |
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| 70 | #define VPU_40XX_BUTTRESS_VPU_STATUS_READY_MASK BIT_MASK(0) |
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| 71 | #define VPU_40XX_BUTTRESS_VPU_STATUS_IDLE_MASK BIT_MASK(1) |
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| 72 | #define VPU_40XX_BUTTRESS_VPU_STATUS_DUP_IDLE_MASK BIT_MASK(2) |
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| 73 | #define VPU_40XX_BUTTRESS_VPU_STATUS_CLOCK_RESOURCE_OWN_ACK_MASK BIT_MASK(6) |
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| 74 | #define VPU_40XX_BUTTRESS_VPU_STATUS_POWER_RESOURCE_OWN_ACK_MASK BIT_MASK(7) |
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| 75 | #define VPU_40XX_BUTTRESS_VPU_STATUS_PERF_CLK_MASK BIT_MASK(11) |
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| 76 | #define VPU_40XX_BUTTRESS_VPU_STATUS_DISABLE_CLK_RELINQUISH_MASK BIT_MASK(12) |
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| 77 | |
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| 78 | #define VPU_40XX_BUTTRESS_IP_RESET 0x00000160u |
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| 79 | #define VPU_40XX_BUTTRESS_IP_RESET_TRIGGER_MASK BIT_MASK(0) |
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| 80 | |
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| 81 | #define VPU_40XX_BUTTRESS_D0I3_CONTROL 0x00000164u |
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| 82 | #define VPU_40XX_BUTTRESS_D0I3_CONTROL_INPROGRESS_MASK BIT_MASK(0) |
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| 83 | #define VPU_40XX_BUTTRESS_D0I3_CONTROL_I3_MASK BIT_MASK(2) |
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| 84 | |
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| 85 | #define VPU_40XX_BUTTRESS_VPU_TELEMETRY_OFFSET 0x00000168u |
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| 86 | #define VPU_40XX_BUTTRESS_VPU_TELEMETRY_SIZE 0x0000016cu |
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| 87 | #define VPU_40XX_BUTTRESS_VPU_TELEMETRY_ENABLE 0x00000170u |
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| 88 | |
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| 89 | #define VPU_40XX_BUTTRESS_FMIN_FUSE 0x00000174u |
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| 90 | #define VPU_40XX_BUTTRESS_FMIN_FUSE_MIN_RATIO_MASK GENMASK(7, 0) |
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| 91 | #define VPU_40XX_BUTTRESS_FMIN_FUSE_PN_RATIO_MASK GENMASK(15, 8) |
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| 92 | |
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| 93 | #define VPU_40XX_BUTTRESS_FMAX_FUSE 0x00000178u |
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| 94 | #define VPU_40XX_BUTTRESS_FMAX_FUSE_MAX_RATIO_MASK GENMASK(7, 0) |
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| 95 | |
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| 96 | #define VPU_40XX_HOST_SS_CPR_CLK_EN 0x00000080u |
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| 97 | #define VPU_40XX_HOST_SS_CPR_CLK_EN_TOP_NOC_MASK BIT_MASK(1) |
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| 98 | #define VPU_40XX_HOST_SS_CPR_CLK_EN_DSS_MAS_MASK BIT_MASK(10) |
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| 99 | #define VPU_40XX_HOST_SS_CPR_CLK_EN_CSS_MAS_MASK BIT_MASK(11) |
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| 100 | |
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| 101 | #define VPU_40XX_HOST_SS_CPR_CLK_SET 0x00000084u |
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| 102 | #define VPU_40XX_HOST_SS_CPR_CLK_SET_TOP_NOC_MASK BIT_MASK(1) |
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| 103 | #define VPU_40XX_HOST_SS_CPR_CLK_SET_DSS_MAS_MASK BIT_MASK(10) |
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| 104 | #define VPU_40XX_HOST_SS_CPR_CLK_SET_MSS_MAS_MASK BIT_MASK(11) |
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| 105 | |
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| 106 | #define VPU_40XX_HOST_SS_CPR_RST_EN 0x00000090u |
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| 107 | #define VPU_40XX_HOST_SS_CPR_RST_EN_TOP_NOC_MASK BIT_MASK(1) |
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| 108 | #define VPU_40XX_HOST_SS_CPR_RST_EN_DSS_MAS_MASK BIT_MASK(10) |
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| 109 | #define VPU_40XX_HOST_SS_CPR_RST_EN_CSS_MAS_MASK BIT_MASK(11) |
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| 110 | |
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| 111 | #define VPU_40XX_HOST_SS_CPR_RST_SET 0x00000094u |
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| 112 | #define VPU_40XX_HOST_SS_CPR_RST_SET_TOP_NOC_MASK BIT_MASK(1) |
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| 113 | #define VPU_40XX_HOST_SS_CPR_RST_SET_DSS_MAS_MASK BIT_MASK(10) |
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| 114 | #define VPU_40XX_HOST_SS_CPR_RST_SET_MSS_MAS_MASK BIT_MASK(11) |
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| 115 | |
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| 116 | #define VPU_40XX_HOST_SS_CPR_RST_CLR 0x00000098u |
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| 117 | #define VPU_40XX_HOST_SS_CPR_RST_CLR_TOP_NOC_MASK BIT_MASK(1) |
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| 118 | #define VPU_40XX_HOST_SS_CPR_RST_CLR_DSS_MAS_MASK BIT_MASK(10) |
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| 119 | #define VPU_40XX_HOST_SS_CPR_RST_CLR_MSS_MAS_MASK BIT_MASK(11) |
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| 120 | |
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| 121 | #define VPU_40XX_HOST_SS_HW_VERSION 0x00000108u |
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| 122 | #define VPU_40XX_HOST_SS_HW_VERSION_SOC_REVISION_MASK GENMASK(7, 0) |
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| 123 | #define VPU_40XX_HOST_SS_HW_VERSION_SOC_NUMBER_MASK GENMASK(15, 8) |
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| 124 | #define VPU_40XX_HOST_SS_HW_VERSION_VPU_GENERATION_MASK GENMASK(23, 16) |
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| 125 | |
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| 126 | #define VPU_40XX_HOST_SS_SW_VERSION 0x0000010cu |
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| 127 | |
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| 128 | #define VPU_40XX_HOST_SS_GEN_CTRL 0x00000118u |
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| 129 | #define VPU_40XX_HOST_SS_GEN_CTRL_PS_MASK GENMASK(31, 29) |
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| 130 | |
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| 131 | #define VPU_40XX_HOST_SS_NOC_QREQN 0x00000154u |
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| 132 | #define VPU_40XX_HOST_SS_NOC_QREQN_TOP_SOCMMIO_MASK BIT_MASK(0) |
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| 133 | |
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| 134 | #define VPU_40XX_HOST_SS_NOC_QACCEPTN 0x00000158u |
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| 135 | #define VPU_40XX_HOST_SS_NOC_QACCEPTN_TOP_SOCMMIO_MASK BIT_MASK(0) |
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| 136 | |
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| 137 | #define VPU_40XX_HOST_SS_NOC_QDENY 0x0000015cu |
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| 138 | #define VPU_40XX_HOST_SS_NOC_QDENY_TOP_SOCMMIO_MASK BIT_MASK(0) |
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| 139 | |
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| 140 | #define VPU_40XX_TOP_NOC_QREQN 0x00000160u |
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| 141 | #define VPU_40XX_TOP_NOC_QREQN_CPU_CTRL_MASK BIT_MASK(0) |
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| 142 | #define VPU_40XX_TOP_NOC_QREQN_HOSTIF_L2CACHE_MASK BIT_MASK(2) |
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| 143 | |
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| 144 | #define VPU_40XX_TOP_NOC_QACCEPTN 0x00000164u |
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| 145 | #define VPU_40XX_TOP_NOC_QACCEPTN_CPU_CTRL_MASK BIT_MASK(0) |
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| 146 | #define VPU_40XX_TOP_NOC_QACCEPTN_HOSTIF_L2CACHE_MASK BIT_MASK(2) |
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| 147 | |
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| 148 | #define VPU_40XX_TOP_NOC_QDENY 0x00000168u |
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| 149 | #define VPU_40XX_TOP_NOC_QDENY_CPU_CTRL_MASK BIT_MASK(0) |
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| 150 | #define VPU_40XX_TOP_NOC_QDENY_HOSTIF_L2CACHE_MASK BIT_MASK(2) |
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| 151 | |
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| 152 | #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN 0x00000170u |
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| 153 | #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_ROM_CMX_MASK BIT_MASK(0) |
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| 154 | #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_DBG_MASK BIT_MASK(1) |
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| 155 | #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_CSS_CTRL_MASK BIT_MASK(2) |
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| 156 | #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_DEC400_MASK BIT_MASK(3) |
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| 157 | #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_NCE_MASK BIT_MASK(4) |
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| 158 | #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_MBI_MASK BIT_MASK(5) |
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| 159 | #define VPU_40XX_HOST_SS_FW_SOC_IRQ_EN_MSS_MBI_CMX_MASK BIT_MASK(6) |
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| 160 | |
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| 161 | #define VPU_40XX_HOST_SS_ICB_STATUS_0 0x00010210u |
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| 162 | #define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_0_INT_MASK BIT_MASK(0) |
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| 163 | #define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_1_INT_MASK BIT_MASK(1) |
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| 164 | #define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_2_INT_MASK BIT_MASK(2) |
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| 165 | #define VPU_40XX_HOST_SS_ICB_STATUS_0_TIMER_3_INT_MASK BIT_MASK(3) |
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| 166 | #define VPU_40XX_HOST_SS_ICB_STATUS_0_HOST_IPC_FIFO_INT_MASK BIT_MASK(4) |
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| 167 | #define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_0_INT_MASK BIT_MASK(5) |
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| 168 | #define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_1_INT_MASK BIT_MASK(6) |
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| 169 | #define VPU_40XX_HOST_SS_ICB_STATUS_0_MMU_IRQ_2_INT_MASK BIT_MASK(7) |
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| 170 | #define VPU_40XX_HOST_SS_ICB_STATUS_0_NOC_FIREWALL_INT_MASK BIT_MASK(8) |
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| 171 | #define VPU_40XX_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_0_INT_MASK BIT_MASK(30) |
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| 172 | #define VPU_40XX_HOST_SS_ICB_STATUS_0_CPU_INT_REDIRECT_1_INT_MASK BIT_MASK(31) |
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| 173 | |
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| 174 | #define VPU_40XX_HOST_SS_ICB_STATUS_1 0x00010214u |
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| 175 | #define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_2_INT_MASK BIT_MASK(0) |
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| 176 | #define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_3_INT_MASK BIT_MASK(1) |
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| 177 | #define VPU_40XX_HOST_SS_ICB_STATUS_1_CPU_INT_REDIRECT_4_INT_MASK BIT_MASK(2) |
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| 178 | |
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| 179 | #define VPU_40XX_HOST_SS_ICB_CLEAR_0 0x00010220u |
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| 180 | #define VPU_40XX_HOST_SS_ICB_CLEAR_1 0x00010224u |
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| 181 | #define VPU_40XX_HOST_SS_ICB_ENABLE_0 0x00010240u |
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| 182 | #define VPU_40XX_HOST_SS_ICB_ENABLE_1 0x00010244u |
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| 183 | |
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| 184 | #define VPU_40XX_HOST_SS_TIM_IPC_FIFO_ATM 0x000200f4u |
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| 185 | |
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| 186 | #define VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT 0x000200fcu |
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| 187 | #define VPU_40XX_HOST_SS_TIM_IPC_FIFO_STAT_FILL_LEVEL_MASK GENMASK(23, 16) |
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| 188 | |
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| 189 | #define VPU_40XX_HOST_SS_AON_PWR_ISO_EN0 0x00030020u |
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| 190 | #define VPU_40XX_HOST_SS_AON_PWR_ISO_EN0_CSS_CPU_MASK BIT_MASK(3) |
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| 191 | |
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| 192 | #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0 0x00030024u |
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| 193 | #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0_CSS_CPU_MASK BIT_MASK(3) |
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| 194 | |
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| 195 | #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0 0x00030028u |
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| 196 | #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0_CSS_CPU_MASK BIT_MASK(3) |
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| 197 | |
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| 198 | #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0 0x0003002cu |
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| 199 | #define VPU_40XX_HOST_SS_AON_PWR_ISLAND_STATUS0_CSS_CPU_MASK BIT_MASK(3) |
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| 200 | |
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| 201 | #define VPU_40XX_HOST_SS_AON_IDLE_GEN 0x00030200u |
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| 202 | #define VPU_40XX_HOST_SS_AON_IDLE_GEN_EN_MASK BIT_MASK(0) |
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| 203 | #define VPU_40XX_HOST_SS_AON_IDLE_GEN_HW_PG_EN_MASK BIT_MASK(1) |
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| 204 | |
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| 205 | #define VPU_40XX_HOST_SS_AON_DPU_ACTIVE 0x00030204u |
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| 206 | #define VPU_40XX_HOST_SS_AON_DPU_ACTIVE_DPU_ACTIVE_MASK BIT_MASK(0) |
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| 207 | |
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| 208 | #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO 0x00040040u |
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| 209 | #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_DONE_MASK BIT_MASK(0) |
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| 210 | #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IOSF_RS_ID_MASK GENMASK(2, 1) |
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| 211 | #define VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK GENMASK(31, 3) |
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| 212 | |
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| 213 | #define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR 0x00082020u |
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| 214 | #define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_FINAL_PLL_FREQ_MASK GENMASK(15, 0) |
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| 215 | #define VPU_40XX_HOST_SS_WORKPOINT_CONFIG_MIRROR_CONFIG_ID_MASK GENMASK(31, 16) |
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| 216 | |
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| 217 | #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES 0x00360000u |
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| 218 | #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_CACHE_OVERRIDE_EN_MASK BIT_MASK(0) |
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| 219 | #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AWCACHE_OVERRIDE_MASK BIT_MASK(1) |
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| 220 | #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_ARCACHE_OVERRIDE_MASK BIT_MASK(2) |
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| 221 | #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_SNOOP_OVERRIDE_EN_MASK BIT_MASK(3) |
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| 222 | #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AW_SNOOP_OVERRIDE_MASK BIT_MASK(4) |
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| 223 | #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_AR_SNOOP_OVERRIDE_MASK BIT_MASK(5) |
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| 224 | #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AW_CONTEXT_FLAG_MASK GENMASK(10, 6) |
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| 225 | #define VPU_40XX_HOST_IF_TCU_PTW_OVERRIDES_PTW_AR_CONTEXT_FLAG_MASK GENMASK(15, 11) |
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| 226 | |
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| 227 | #define VPU_40XX_HOST_IF_TBU_MMUSSIDV 0x00360004u |
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| 228 | #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU0_AWMMUSSIDV_MASK BIT_MASK(0) |
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| 229 | #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU0_ARMMUSSIDV_MASK BIT_MASK(1) |
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| 230 | #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU1_AWMMUSSIDV_MASK BIT_MASK(2) |
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| 231 | #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU1_ARMMUSSIDV_MASK BIT_MASK(3) |
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| 232 | #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU2_AWMMUSSIDV_MASK BIT_MASK(4) |
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| 233 | #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU2_ARMMUSSIDV_MASK BIT_MASK(5) |
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| 234 | #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU3_AWMMUSSIDV_MASK BIT_MASK(6) |
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| 235 | #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU3_ARMMUSSIDV_MASK BIT_MASK(7) |
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| 236 | #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU4_AWMMUSSIDV_MASK BIT_MASK(8) |
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| 237 | #define VPU_40XX_HOST_IF_TBU_MMUSSIDV_TBU4_ARMMUSSIDV_MASK BIT_MASK(9) |
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| 238 | |
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| 239 | #define VPU_40XX_CPU_SS_DSU_LEON_RT_BASE 0x04000000u |
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| 240 | #define VPU_40XX_CPU_SS_DSU_LEON_RT_DSU_CTRL 0x04000000u |
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| 241 | #define VPU_40XX_CPU_SS_DSU_LEON_RT_PC_REG 0x04400010u |
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| 242 | #define VPU_40XX_CPU_SS_DSU_LEON_RT_NPC_REG 0x04400014u |
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| 243 | #define VPU_40XX_CPU_SS_DSU_LEON_RT_DSU_TRAP_REG 0x04400020u |
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| 244 | |
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| 245 | #define VPU_40XX_CPU_SS_TIM_WATCHDOG 0x0102009cu |
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| 246 | #define VPU_40XX_CPU_SS_TIM_WDOG_EN 0x010200a4u |
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| 247 | #define VPU_40XX_CPU_SS_TIM_SAFE 0x010200a8u |
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| 248 | |
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| 249 | #define VPU_40XX_CPU_SS_TIM_GEN_CONFIG 0x01021008u |
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| 250 | #define VPU_40XX_CPU_SS_TIM_GEN_CONFIG_WDOG_TO_INT_CLR_MASK BIT_MASK(9) |
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| 251 | |
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| 252 | #define VPU_40XX_CPU_SS_CPR_NOC_QREQN 0x01010030u |
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| 253 | #define VPU_40XX_CPU_SS_CPR_NOC_QREQN_TOP_MMIO_MASK BIT_MASK(0) |
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| 254 | |
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| 255 | #define VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN 0x01010034u |
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| 256 | #define VPU_40XX_CPU_SS_CPR_NOC_QACCEPTN_TOP_MMIO_MASK BIT_MASK(0) |
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| 257 | |
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| 258 | #define VPU_40XX_CPU_SS_CPR_NOC_QDENY 0x01010038u |
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| 259 | #define VPU_40XX_CPU_SS_CPR_NOC_QDENY_TOP_MMIO_MASK BIT_MASK(0) |
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| 260 | |
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| 261 | #define VPU_40XX_CPU_SS_TIM_IPC_FIFO 0x010200f0u |
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| 262 | #define VPU_40XX_CPU_SS_TIM_PERF_EXT_FREE_CNT 0x01029008u |
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| 263 | |
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| 264 | #define VPU_40XX_CPU_SS_DOORBELL_0 0x01300000u |
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| 265 | #define VPU_40XX_CPU_SS_DOORBELL_0_SET_MASK BIT_MASK(0) |
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| 266 | |
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| 267 | #define VPU_40XX_CPU_SS_DOORBELL_1 0x01301000u |
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| 268 | |
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| 269 | #endif /* __IVPU_HW_40XX_REG_H__ */ |
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| 270 | |
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