1 | /* SPDX-License-Identifier: MIT */ |
2 | /* |
3 | * Copyright (C) 2020-2023 Intel Corporation |
4 | */ |
5 | |
6 | #ifndef VPU_BOOT_API_H |
7 | #define VPU_BOOT_API_H |
8 | |
9 | /* |
10 | * =========== FW API version information beginning ================ |
11 | * The bellow values will be used to construct the version info this way: |
12 | * fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) | |
13 | * VPU_BOOT_API_VER_MINOR; |
14 | * VPU_BOOT_API_VER_PATCH will be ignored. KMD and compatibility is not affected if this changes. |
15 | */ |
16 | |
17 | /* |
18 | * Major version changes that break backward compatibility. |
19 | * Major version must start from 1 and can only be incremented. |
20 | */ |
21 | #define VPU_BOOT_API_VER_MAJOR 3 |
22 | |
23 | /* |
24 | * Minor version changes when API backward compatibility is preserved. |
25 | * Resets to 0 if Major version is incremented. |
26 | */ |
27 | #define VPU_BOOT_API_VER_MINOR 12 |
28 | |
29 | /* |
30 | * API header changed (field names, documentation, formatting) but API itself has not been changed |
31 | */ |
32 | #define VPU_BOOT_API_VER_PATCH 2 |
33 | |
34 | /* |
35 | * Index in the API version table |
36 | * Must be unique for each API |
37 | */ |
38 | #define VPU_BOOT_API_VER_INDEX 0 |
39 | /* ------------ FW API version information end ---------------------*/ |
40 | |
41 | #pragma pack(push, 1) |
42 | |
43 | /* |
44 | * Firmware image header format |
45 | */ |
46 | #define 4096 |
47 | #define 0x1 |
48 | #define VPU_FW_VERSION_SIZE 32 |
49 | #define VPU_FW_API_VER_NUM 16 |
50 | |
51 | struct { |
52 | u32 ; |
53 | u32 ; |
54 | u64 ; |
55 | u32 ; |
56 | u64 ; |
57 | u8 [VPU_FW_VERSION_SIZE]; |
58 | u32 ; |
59 | u64 ; |
60 | u32 ; |
61 | u64 ; |
62 | u32 [VPU_FW_API_VER_NUM]; |
63 | /* Size of memory require for firmware execution */ |
64 | u32 ; |
65 | u32 ; |
66 | }; |
67 | |
68 | /* |
69 | * Firmware boot parameters format |
70 | */ |
71 | |
72 | #define VPU_BOOT_PLL_COUNT 3 |
73 | #define VPU_BOOT_PLL_OUT_COUNT 4 |
74 | |
75 | /** Values for boot_type field */ |
76 | #define VPU_BOOT_TYPE_COLDBOOT 0 |
77 | #define VPU_BOOT_TYPE_WARMBOOT 1 |
78 | |
79 | /** Value for magic filed */ |
80 | #define VPU_BOOT_PARAMS_MAGIC 0x10000 |
81 | |
82 | /** VPU scheduling mode. By default, OS scheduling is used. */ |
83 | #define VPU_SCHEDULING_MODE_OS 0 |
84 | #define VPU_SCHEDULING_MODE_HW 1 |
85 | |
86 | enum VPU_BOOT_L2_CACHE_CFG_TYPE { |
87 | VPU_BOOT_L2_CACHE_CFG_UPA = 0, |
88 | VPU_BOOT_L2_CACHE_CFG_NN = 1, |
89 | VPU_BOOT_L2_CACHE_CFG_NUM = 2 |
90 | }; |
91 | |
92 | /** |
93 | * Logging destinations. |
94 | * |
95 | * Logging output can be directed to different logging destinations. This enum |
96 | * defines the list of logging destinations supported by the VPU firmware (NOTE: |
97 | * a specific VPU FW binary may support only a subset of such output |
98 | * destinations, depending on the target platform and compile options). |
99 | */ |
100 | enum vpu_trace_destination { |
101 | VPU_TRACE_DESTINATION_PIPEPRINT = 0x1, |
102 | VPU_TRACE_DESTINATION_VERBOSE_TRACING = 0x2, |
103 | VPU_TRACE_DESTINATION_NORTH_PEAK = 0x4, |
104 | }; |
105 | |
106 | /* |
107 | * Processor bit shifts (for loggable HW components). |
108 | */ |
109 | #define VPU_TRACE_PROC_BIT_ARM 0 |
110 | #define VPU_TRACE_PROC_BIT_LRT 1 |
111 | #define VPU_TRACE_PROC_BIT_LNN 2 |
112 | #define VPU_TRACE_PROC_BIT_SHV_0 3 |
113 | #define VPU_TRACE_PROC_BIT_SHV_1 4 |
114 | #define VPU_TRACE_PROC_BIT_SHV_2 5 |
115 | #define VPU_TRACE_PROC_BIT_SHV_3 6 |
116 | #define VPU_TRACE_PROC_BIT_SHV_4 7 |
117 | #define VPU_TRACE_PROC_BIT_SHV_5 8 |
118 | #define VPU_TRACE_PROC_BIT_SHV_6 9 |
119 | #define VPU_TRACE_PROC_BIT_SHV_7 10 |
120 | #define VPU_TRACE_PROC_BIT_SHV_8 11 |
121 | #define VPU_TRACE_PROC_BIT_SHV_9 12 |
122 | #define VPU_TRACE_PROC_BIT_SHV_10 13 |
123 | #define VPU_TRACE_PROC_BIT_SHV_11 14 |
124 | #define VPU_TRACE_PROC_BIT_SHV_12 15 |
125 | #define VPU_TRACE_PROC_BIT_SHV_13 16 |
126 | #define VPU_TRACE_PROC_BIT_SHV_14 17 |
127 | #define VPU_TRACE_PROC_BIT_SHV_15 18 |
128 | #define VPU_TRACE_PROC_BIT_ACT_SHV_0 19 |
129 | #define VPU_TRACE_PROC_BIT_ACT_SHV_1 20 |
130 | #define VPU_TRACE_PROC_BIT_ACT_SHV_2 21 |
131 | #define VPU_TRACE_PROC_BIT_ACT_SHV_3 22 |
132 | #define VPU_TRACE_PROC_NO_OF_HW_DEVS 23 |
133 | |
134 | /* KMB HW component IDs are sequential, so define first and last IDs. */ |
135 | #define VPU_TRACE_PROC_BIT_KMB_FIRST VPU_TRACE_PROC_BIT_LRT |
136 | #define VPU_TRACE_PROC_BIT_KMB_LAST VPU_TRACE_PROC_BIT_SHV_15 |
137 | |
138 | struct vpu_boot_l2_cache_config { |
139 | u8 use; |
140 | u8 cfg; |
141 | }; |
142 | |
143 | struct vpu_warm_boot_section { |
144 | u32 src; |
145 | u32 dst; |
146 | u32 size; |
147 | u32 core_id; |
148 | u32 is_clear_op; |
149 | }; |
150 | |
151 | struct vpu_boot_params { |
152 | u32 magic; |
153 | u32 vpu_id; |
154 | u32 vpu_count; |
155 | u32 pad0[5]; |
156 | /* Clock frequencies: 0x20 - 0xFF */ |
157 | u32 frequency; |
158 | u32 pll[VPU_BOOT_PLL_COUNT][VPU_BOOT_PLL_OUT_COUNT]; |
159 | u32 perf_clk_frequency; |
160 | u32 pad1[42]; |
161 | /* Memory regions: 0x100 - 0x1FF */ |
162 | u64 ; |
163 | u32 ; |
164 | u64 shared_region_base; |
165 | u32 shared_region_size; |
166 | u64 ipc_payload_area_start; |
167 | u32 ipc_payload_area_size; |
168 | u64 global_aliased_pio_base; |
169 | u32 global_aliased_pio_size; |
170 | u32 autoconfig; |
171 | struct vpu_boot_l2_cache_config cache_defaults[VPU_BOOT_L2_CACHE_CFG_NUM]; |
172 | u64 global_memory_allocator_base; |
173 | u32 global_memory_allocator_size; |
174 | /** |
175 | * ShaveNN FW section VPU base address |
176 | * On VPU2.7 HW this address must be within 2GB range starting from L2C_PAGE_TABLE base |
177 | */ |
178 | u64 shave_nn_fw_base; |
179 | u64 save_restore_ret_address; /* stores the address of FW's restore entry point */ |
180 | u32 pad2[43]; |
181 | /* IRQ re-direct numbers: 0x200 - 0x2FF */ |
182 | s32 watchdog_irq_mss; |
183 | s32 watchdog_irq_nce; |
184 | /* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */ |
185 | u32 host_to_vpu_irq; |
186 | /* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */ |
187 | u32 job_done_irq; |
188 | /* VPU -> ARM IRQ line to use to request MMU update. */ |
189 | u32 mmu_update_request_irq; |
190 | /* ARM -> VPU IRQ line to use to notify of MMU update completion. */ |
191 | u32 mmu_update_done_irq; |
192 | /* ARM -> VPU IRQ line to use to request power level change. */ |
193 | u32 set_power_level_irq; |
194 | /* VPU -> ARM IRQ line to use to notify of power level change completion. */ |
195 | u32 set_power_level_done_irq; |
196 | /* VPU -> ARM IRQ line to use to notify of VPU idle state change */ |
197 | u32 set_vpu_idle_update_irq; |
198 | /* VPU -> ARM IRQ line to use to request counter reset. */ |
199 | u32 metric_query_event_irq; |
200 | /* ARM -> VPU IRQ line to use to notify of counter reset completion. */ |
201 | u32 metric_query_event_done_irq; |
202 | /* VPU -> ARM IRQ line to use to notify of preemption completion. */ |
203 | u32 preemption_done_irq; |
204 | /* Padding. */ |
205 | u32 pad3[52]; |
206 | /* Silicon information: 0x300 - 0x3FF */ |
207 | u32 host_version_id; |
208 | u32 si_stepping; |
209 | u64 device_id; |
210 | u64 feature_exclusion; |
211 | u64 sku; |
212 | /** PLL ratio for minimum clock frequency */ |
213 | u32 min_freq_pll_ratio; |
214 | /** PLL ratio for maximum clock frequency */ |
215 | u32 max_freq_pll_ratio; |
216 | /** |
217 | * Initial log level threshold (messages with log level severity less than |
218 | * the threshold will not be logged); applies to every enabled logging |
219 | * destination and loggable HW component. See 'mvLog_t' enum for acceptable |
220 | * values. |
221 | */ |
222 | u32 default_trace_level; |
223 | u32 boot_type; |
224 | u64 punit_telemetry_sram_base; |
225 | u64 punit_telemetry_sram_size; |
226 | u32 vpu_telemetry_enable; |
227 | u64 crit_tracing_buff_addr; |
228 | u32 crit_tracing_buff_size; |
229 | u64 verbose_tracing_buff_addr; |
230 | u32 verbose_tracing_buff_size; |
231 | u64 verbose_tracing_sw_component_mask; /* TO BE REMOVED */ |
232 | /** |
233 | * Mask of destinations to which logging messages are delivered; bitwise OR |
234 | * of values defined in vpu_trace_destination enum. |
235 | */ |
236 | u32 trace_destination_mask; |
237 | /** |
238 | * Mask of hardware components for which logging is enabled; bitwise OR of |
239 | * bits defined by the VPU_TRACE_PROC_BIT_* macros. |
240 | */ |
241 | u64 trace_hw_component_mask; |
242 | /** Mask of trace message formats supported by the driver */ |
243 | u64 tracing_buff_message_format_mask; |
244 | u64 trace_reserved_1[2]; |
245 | /** |
246 | * Period at which the VPU reads the temp sensor values into MMIO, on |
247 | * platforms where that is necessary (in ms). 0 to disable reads. |
248 | */ |
249 | u32 temp_sensor_period_ms; |
250 | /** PLL ratio for efficient clock frequency */ |
251 | u32 pn_freq_pll_ratio; |
252 | u32 pad4[28]; |
253 | /* Warm boot information: 0x400 - 0x43F */ |
254 | u32 warm_boot_sections_count; |
255 | u32 warm_boot_start_address_reference; |
256 | u32 warm_boot_section_info_address_offset; |
257 | u32 pad5[13]; |
258 | /* Power States transitions timestamps: 0x440 - 0x46F*/ |
259 | struct { |
260 | /* VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */ |
261 | u64 vpu_active_state_requested; |
262 | /* VPU_IDLE -> VPU_ACTIVE transition completed timestamp */ |
263 | u64 vpu_active_state_achieved; |
264 | /* VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */ |
265 | u64 vpu_idle_state_requested; |
266 | /* VPU_ACTIVE -> VPU_IDLE transition completed timestamp */ |
267 | u64 vpu_idle_state_achieved; |
268 | /* VPU_IDLE -> VPU_STANDBY transition initiated timestamp */ |
269 | u64 vpu_standby_state_requested; |
270 | /* VPU_IDLE -> VPU_STANDBY transition completed timestamp */ |
271 | u64 vpu_standby_state_achieved; |
272 | } power_states_timestamps; |
273 | /* VPU scheduling mode. Values defined by VPU_SCHEDULING_MODE_* macros. */ |
274 | u32 vpu_scheduling_mode; |
275 | /* Present call period in milliseconds. */ |
276 | u32 vpu_focus_present_timer_ms; |
277 | /* Unused/reserved: 0x478 - 0xFFF */ |
278 | u32 pad6[738]; |
279 | }; |
280 | |
281 | /* |
282 | * Magic numbers set between host and vpu to detect corruptio of tracing init |
283 | */ |
284 | |
285 | #define VPU_TRACING_BUFFER_CANARY (0xCAFECAFE) |
286 | |
287 | /* Tracing buffer message format definitions */ |
288 | #define VPU_TRACING_FORMAT_STRING 0 |
289 | #define VPU_TRACING_FORMAT_MIPI 2 |
290 | /* |
291 | * Header of the tracing buffer. |
292 | * The below defined header will be stored at the beginning of |
293 | * each allocated tracing buffer, followed by a series of 256b |
294 | * of ASCII trace message entries. |
295 | */ |
296 | struct { |
297 | /** |
298 | * Magic number set by host to detect corruption |
299 | * @see VPU_TRACING_BUFFER_CANARY |
300 | */ |
301 | u32 ; |
302 | /* offset from start of buffer for trace entries */ |
303 | u32 ; |
304 | u32 [14]; |
305 | /* End of first cache line */ |
306 | |
307 | /** |
308 | * Magic number set by host to detect corruption |
309 | * @see VPU_TRACING_BUFFER_CANARY |
310 | */ |
311 | u32 ; |
312 | /* offset from start of buffer from write start */ |
313 | u32 ; |
314 | /* counter for buffer wrapping */ |
315 | u32 ; |
316 | /* legacy field - do not use */ |
317 | u32 ; |
318 | /** |
319 | * Size of the log buffer include this header (@header_size) and space |
320 | * reserved for all messages. If @alignment` is greater that 0 the @Size |
321 | * must be multiple of @Alignment. |
322 | */ |
323 | u32 ; |
324 | /* Header version */ |
325 | u16 ; |
326 | /* Header size */ |
327 | u16 ; |
328 | /* |
329 | * Format of the messages in the trace buffer |
330 | * 0 - null terminated string |
331 | * 1 - size + null terminated string |
332 | * 2 - MIPI-SysT encoding |
333 | */ |
334 | u32 ; |
335 | /* |
336 | * Message alignment |
337 | * 0 - messages are place 1 after another |
338 | * n - every message starts and multiple on offset |
339 | */ |
340 | u32 ; /* 64, 128, 256 */ |
341 | /* Name of the logging entity, i.e "LRT", "LNN", "SHV0", etc */ |
342 | char [16]; |
343 | u32 [4]; |
344 | /* End of second cache line */ |
345 | }; |
346 | |
347 | #pragma pack(pop) |
348 | |
349 | #endif |
350 | |