| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* Copyright (C) 2019-2020 ARM Limited or its affiliates. */ |
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| 3 | |
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| 4 | #include <linux/bitops.h> |
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| 5 | |
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| 6 | #define POWER_DOWN_ENABLE 0x01 |
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| 7 | #define POWER_DOWN_DISABLE 0x00 |
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| 8 | |
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| 9 | /* hwrng quality: bits of true entropy per 1024 bits of input */ |
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| 10 | #define CC_TRNG_QUALITY 1024 |
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| 11 | |
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| 12 | /* CryptoCell TRNG HW definitions */ |
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| 13 | #define CC_TRNG_NUM_OF_ROSCS 4 |
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| 14 | /* The number of words generated in the entropy holding register (EHR) |
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| 15 | * 6 words (192 bit) according to HW implementation |
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| 16 | */ |
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| 17 | #define CC_TRNG_EHR_IN_WORDS 6 |
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| 18 | #define CC_TRNG_EHR_IN_BITS (CC_TRNG_EHR_IN_WORDS * BITS_PER_TYPE(u32)) |
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| 19 | |
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| 20 | #define CC_HOST_RNG_IRQ_MASK BIT(CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT) |
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| 21 | |
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| 22 | /* RNG interrupt mask */ |
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| 23 | #define CC_RNG_INT_MASK (BIT(CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT) | \ |
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| 24 | BIT(CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT) | \ |
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| 25 | BIT(CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT) | \ |
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| 26 | BIT(CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT) | \ |
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| 27 | BIT(CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT)) |
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| 28 | |
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| 29 | // -------------------------------------- |
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| 30 | // BLOCK: RNG |
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| 31 | // -------------------------------------- |
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| 32 | #define CC_RNG_IMR_REG_OFFSET 0x0100UL |
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| 33 | #define CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT 0x0UL |
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| 34 | #define CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT 0x1UL |
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| 35 | #define CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT 0x2UL |
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| 36 | #define CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT 0x3UL |
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| 37 | #define CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT 0x4UL |
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| 38 | #define CC_RNG_ISR_REG_OFFSET 0x0104UL |
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| 39 | #define CC_RNG_ISR_EHR_VALID_BIT_SHIFT 0x0UL |
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| 40 | #define CC_RNG_ISR_EHR_VALID_BIT_SIZE 0x1UL |
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| 41 | #define CC_RNG_ISR_AUTOCORR_ERR_BIT_SHIFT 0x1UL |
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| 42 | #define CC_RNG_ISR_AUTOCORR_ERR_BIT_SIZE 0x1UL |
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| 43 | #define CC_RNG_ISR_CRNGT_ERR_BIT_SHIFT 0x2UL |
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| 44 | #define CC_RNG_ISR_CRNGT_ERR_BIT_SIZE 0x1UL |
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| 45 | #define CC_RNG_ISR_WATCHDOG_BIT_SHIFT 0x4UL |
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| 46 | #define CC_RNG_ISR_WATCHDOG_BIT_SIZE 0x1UL |
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| 47 | #define CC_RNG_ICR_REG_OFFSET 0x0108UL |
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| 48 | #define CC_TRNG_CONFIG_REG_OFFSET 0x010CUL |
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| 49 | #define CC_EHR_DATA_0_REG_OFFSET 0x0114UL |
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| 50 | #define CC_RND_SOURCE_ENABLE_REG_OFFSET 0x012CUL |
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| 51 | #define CC_SAMPLE_CNT1_REG_OFFSET 0x0130UL |
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| 52 | #define CC_TRNG_DEBUG_CONTROL_REG_OFFSET 0x0138UL |
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| 53 | #define CC_RNG_SW_RESET_REG_OFFSET 0x0140UL |
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| 54 | #define CC_RNG_CLK_ENABLE_REG_OFFSET 0x01C4UL |
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| 55 | #define CC_RNG_DMA_ENABLE_REG_OFFSET 0x01C8UL |
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| 56 | #define CC_RNG_WATCHDOG_VAL_REG_OFFSET 0x01D8UL |
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| 57 | // -------------------------------------- |
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| 58 | // BLOCK: SEC_HOST_RGF |
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| 59 | // -------------------------------------- |
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| 60 | #define CC_HOST_RGF_IRR_REG_OFFSET 0x0A00UL |
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| 61 | #define CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT 0xAUL |
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| 62 | #define CC_HOST_RGF_IMR_REG_OFFSET 0x0A04UL |
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| 63 | #define CC_HOST_RGF_ICR_REG_OFFSET 0x0A08UL |
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| 64 | |
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| 65 | #define CC_HOST_POWER_DOWN_EN_REG_OFFSET 0x0A78UL |
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| 66 | |
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| 67 | // -------------------------------------- |
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| 68 | // BLOCK: NVM |
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| 69 | // -------------------------------------- |
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| 70 | #define CC_NVM_IS_IDLE_REG_OFFSET 0x0F10UL |
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| 71 | #define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT 0x0UL |
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| 72 | #define CC_NVM_IS_IDLE_VALUE_BIT_SIZE 0x1UL |
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| 73 | |
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