| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef _ADDI_TCW_H |
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| 3 | #define _ADDI_TCW_H |
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| 4 | |
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| 5 | /* |
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| 6 | * Following are the generic definitions for the ADDI-DATA timer/counter/ |
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| 7 | * watchdog (TCW) registers and bits. Some of the registers are not used |
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| 8 | * depending on the use of the TCW. |
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| 9 | */ |
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| 10 | |
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| 11 | #define ADDI_TCW_VAL_REG 0x00 |
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| 12 | |
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| 13 | #define ADDI_TCW_SYNC_REG 0x00 |
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| 14 | #define ADDI_TCW_SYNC_CTR_TRIG BIT(8) |
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| 15 | #define ADDI_TCW_SYNC_CTR_DIS BIT(7) |
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| 16 | #define ADDI_TCW_SYNC_CTR_ENA BIT(6) |
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| 17 | #define ADDI_TCW_SYNC_TIMER_TRIG BIT(5) |
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| 18 | #define ADDI_TCW_SYNC_TIMER_DIS BIT(4) |
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| 19 | #define ADDI_TCW_SYNC_TIMER_ENA BIT(3) |
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| 20 | #define ADDI_TCW_SYNC_WDOG_TRIG BIT(2) |
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| 21 | #define ADDI_TCW_SYNC_WDOG_DIS BIT(1) |
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| 22 | #define ADDI_TCW_SYNC_WDOG_ENA BIT(0) |
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| 23 | |
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| 24 | #define ADDI_TCW_RELOAD_REG 0x04 |
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| 25 | |
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| 26 | #define ADDI_TCW_TIMEBASE_REG 0x08 |
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| 27 | |
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| 28 | #define ADDI_TCW_CTRL_REG 0x0c |
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| 29 | #define ADDI_TCW_CTRL_EXT_CLK_STATUS BIT(21) |
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| 30 | #define ADDI_TCW_CTRL_CASCADE BIT(20) |
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| 31 | #define ADDI_TCW_CTRL_CNTR_ENA BIT(19) |
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| 32 | #define ADDI_TCW_CTRL_CNT_UP BIT(18) |
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| 33 | #define ADDI_TCW_CTRL_EXT_CLK(x) (((x) & 3) << 16) |
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| 34 | #define ADDI_TCW_CTRL_EXT_CLK_MASK ADDI_TCW_CTRL_EXT_CLK(3) |
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| 35 | #define ADDI_TCW_CTRL_MODE(x) (((x) & 7) << 13) |
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| 36 | #define ADDI_TCW_CTRL_MODE_MASK ADDI_TCW_CTRL_MODE(7) |
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| 37 | #define ADDI_TCW_CTRL_OUT(x) (((x) & 3) << 11) |
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| 38 | #define ADDI_TCW_CTRL_OUT_MASK ADDI_TCW_CTRL_OUT(3) |
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| 39 | #define ADDI_TCW_CTRL_GATE BIT(10) |
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| 40 | #define ADDI_TCW_CTRL_TRIG BIT(9) |
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| 41 | #define ADDI_TCW_CTRL_EXT_GATE(x) (((x) & 3) << 7) |
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| 42 | #define ADDI_TCW_CTRL_EXT_GATE_MASK ADDI_TCW_CTRL_EXT_GATE(3) |
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| 43 | #define ADDI_TCW_CTRL_EXT_TRIG(x) (((x) & 3) << 5) |
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| 44 | #define ADDI_TCW_CTRL_EXT_TRIG_MASK ADDI_TCW_CTRL_EXT_TRIG(3) |
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| 45 | #define ADDI_TCW_CTRL_TIMER_ENA BIT(4) |
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| 46 | #define ADDI_TCW_CTRL_RESET_ENA BIT(3) |
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| 47 | #define ADDI_TCW_CTRL_WARN_ENA BIT(2) |
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| 48 | #define ADDI_TCW_CTRL_IRQ_ENA BIT(1) |
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| 49 | #define ADDI_TCW_CTRL_ENA BIT(0) |
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| 50 | |
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| 51 | #define ADDI_TCW_STATUS_REG 0x10 |
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| 52 | #define ADDI_TCW_STATUS_SOFT_CLR BIT(3) |
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| 53 | #define ADDI_TCW_STATUS_HARDWARE_TRIG BIT(2) |
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| 54 | #define ADDI_TCW_STATUS_SOFT_TRIG BIT(1) |
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| 55 | #define ADDI_TCW_STATUS_OVERFLOW BIT(0) |
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| 56 | |
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| 57 | #define ADDI_TCW_IRQ_REG 0x14 |
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| 58 | #define ADDI_TCW_IRQ BIT(0) |
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| 59 | |
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| 60 | #define ADDI_TCW_WARN_TIMEVAL_REG 0x18 |
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| 61 | |
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| 62 | #define ADDI_TCW_WARN_TIMEBASE_REG 0x1c |
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| 63 | |
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| 64 | #endif |
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| 65 | |
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