| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Stuff for AMCC S5933 PCI Controller |
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| 4 | * |
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| 5 | * Author: Michal Dobes <dobes@tesnet.cz> |
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| 6 | * |
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| 7 | * Inspirated from general-purpose AMCC S5933 PCI Matchmaker driver |
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| 8 | * made by Andrea Cisternino <acister@pcape1.pi.infn.it> |
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| 9 | * and as result of espionage from MITE code made by David A. Schleef. |
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| 10 | * Thanks to AMCC for their on-line documentation and bus master DMA |
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| 11 | * example. |
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| 12 | */ |
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| 13 | |
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| 14 | #ifndef _AMCC_S5933_H_ |
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| 15 | #define _AMCC_S5933_H_ |
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| 16 | |
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| 17 | /****************************************************************************/ |
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| 18 | /* AMCC Operation Register Offsets - PCI */ |
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| 19 | /****************************************************************************/ |
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| 20 | |
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| 21 | #define AMCC_OP_REG_OMB1 0x00 |
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| 22 | #define AMCC_OP_REG_OMB2 0x04 |
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| 23 | #define AMCC_OP_REG_OMB3 0x08 |
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| 24 | #define AMCC_OP_REG_OMB4 0x0c |
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| 25 | #define AMCC_OP_REG_IMB1 0x10 |
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| 26 | #define AMCC_OP_REG_IMB2 0x14 |
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| 27 | #define AMCC_OP_REG_IMB3 0x18 |
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| 28 | #define AMCC_OP_REG_IMB4 0x1c |
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| 29 | #define AMCC_OP_REG_FIFO 0x20 |
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| 30 | #define AMCC_OP_REG_MWAR 0x24 |
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| 31 | #define AMCC_OP_REG_MWTC 0x28 |
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| 32 | #define AMCC_OP_REG_MRAR 0x2c |
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| 33 | #define AMCC_OP_REG_MRTC 0x30 |
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| 34 | #define AMCC_OP_REG_MBEF 0x34 |
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| 35 | #define AMCC_OP_REG_INTCSR 0x38 |
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| 36 | #define AMCC_OP_REG_INTCSR_SRC (AMCC_OP_REG_INTCSR + 2) /* INT source */ |
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| 37 | #define AMCC_OP_REG_INTCSR_FEC (AMCC_OP_REG_INTCSR + 3) /* FIFO ctrl */ |
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| 38 | #define AMCC_OP_REG_MCSR 0x3c |
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| 39 | #define AMCC_OP_REG_MCSR_NVDATA (AMCC_OP_REG_MCSR + 2) /* Data in byte 2 */ |
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| 40 | #define AMCC_OP_REG_MCSR_NVCMD (AMCC_OP_REG_MCSR + 3) /* Command in byte 3 */ |
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| 41 | |
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| 42 | #define AMCC_FIFO_DEPTH_DWORD 8 |
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| 43 | #define AMCC_FIFO_DEPTH_BYTES (8 * sizeof(u32)) |
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| 44 | |
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| 45 | /****************************************************************************/ |
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| 46 | /* AMCC - PCI Interrupt Control/Status Register */ |
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| 47 | /****************************************************************************/ |
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| 48 | #define INTCSR_OUTBOX_BYTE(x) ((x) & 0x3) |
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| 49 | #define INTCSR_OUTBOX_SELECT(x) (((x) & 0x3) << 2) |
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| 50 | #define INTCSR_OUTBOX_EMPTY_INT 0x10 /* enable outbox empty interrupt */ |
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| 51 | #define INTCSR_INBOX_BYTE(x) (((x) & 0x3) << 8) |
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| 52 | #define INTCSR_INBOX_SELECT(x) (((x) & 0x3) << 10) |
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| 53 | #define INTCSR_INBOX_FULL_INT 0x1000 /* enable inbox full interrupt */ |
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| 54 | /* read, or write clear inbox full interrupt */ |
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| 55 | #define INTCSR_INBOX_INTR_STATUS 0x20000 |
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| 56 | /* read only, interrupt asserted */ |
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| 57 | #define INTCSR_INTR_ASSERTED 0x800000 |
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| 58 | |
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| 59 | /****************************************************************************/ |
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| 60 | /* AMCC - PCI non-volatile ram command register (byte 3 of AMCC_OP_REG_MCSR) */ |
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| 61 | /****************************************************************************/ |
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| 62 | #define MCSR_NV_LOAD_LOW_ADDR 0x0 |
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| 63 | #define MCSR_NV_LOAD_HIGH_ADDR 0x20 |
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| 64 | #define MCSR_NV_WRITE 0x40 |
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| 65 | #define MCSR_NV_READ 0x60 |
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| 66 | #define MCSR_NV_MASK 0x60 |
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| 67 | #define MCSR_NV_ENABLE 0x80 |
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| 68 | #define MCSR_NV_BUSY MCSR_NV_ENABLE |
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| 69 | |
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| 70 | /****************************************************************************/ |
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| 71 | /* AMCC Operation Registers Size - PCI */ |
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| 72 | /****************************************************************************/ |
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| 73 | |
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| 74 | #define AMCC_OP_REG_SIZE 64 /* in bytes */ |
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| 75 | |
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| 76 | /****************************************************************************/ |
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| 77 | /* AMCC Operation Register Offsets - Add-on */ |
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| 78 | /****************************************************************************/ |
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| 79 | |
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| 80 | #define AMCC_OP_REG_AIMB1 0x00 |
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| 81 | #define AMCC_OP_REG_AIMB2 0x04 |
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| 82 | #define AMCC_OP_REG_AIMB3 0x08 |
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| 83 | #define AMCC_OP_REG_AIMB4 0x0c |
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| 84 | #define AMCC_OP_REG_AOMB1 0x10 |
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| 85 | #define AMCC_OP_REG_AOMB2 0x14 |
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| 86 | #define AMCC_OP_REG_AOMB3 0x18 |
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| 87 | #define AMCC_OP_REG_AOMB4 0x1c |
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| 88 | #define AMCC_OP_REG_AFIFO 0x20 |
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| 89 | #define AMCC_OP_REG_AMWAR 0x24 |
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| 90 | #define AMCC_OP_REG_APTA 0x28 |
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| 91 | #define AMCC_OP_REG_APTD 0x2c |
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| 92 | #define AMCC_OP_REG_AMRAR 0x30 |
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| 93 | #define AMCC_OP_REG_AMBEF 0x34 |
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| 94 | #define AMCC_OP_REG_AINT 0x38 |
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| 95 | #define AMCC_OP_REG_AGCSTS 0x3c |
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| 96 | #define AMCC_OP_REG_AMWTC 0x58 |
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| 97 | #define AMCC_OP_REG_AMRTC 0x5c |
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| 98 | |
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| 99 | /****************************************************************************/ |
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| 100 | /* AMCC - Add-on General Control/Status Register */ |
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| 101 | /****************************************************************************/ |
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| 102 | |
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| 103 | #define AGCSTS_CONTROL_MASK 0xfffff000 |
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| 104 | #define AGCSTS_NV_ACC_MASK 0xe0000000 |
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| 105 | #define AGCSTS_RESET_MASK 0x0e000000 |
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| 106 | #define AGCSTS_NV_DA_MASK 0x00ff0000 |
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| 107 | #define AGCSTS_BIST_MASK 0x0000f000 |
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| 108 | #define AGCSTS_STATUS_MASK 0x000000ff |
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| 109 | #define AGCSTS_TCZERO_MASK 0x000000c0 |
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| 110 | #define AGCSTS_FIFO_ST_MASK 0x0000003f |
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| 111 | |
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| 112 | #define AGCSTS_TC_ENABLE 0x10000000 |
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| 113 | |
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| 114 | #define AGCSTS_RESET_MBFLAGS 0x08000000 |
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| 115 | #define AGCSTS_RESET_P2A_FIFO 0x04000000 |
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| 116 | #define AGCSTS_RESET_A2P_FIFO 0x02000000 |
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| 117 | #define AGCSTS_RESET_FIFOS (AGCSTS_RESET_A2P_FIFO | AGCSTS_RESET_P2A_FIFO) |
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| 118 | |
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| 119 | #define AGCSTS_A2P_TCOUNT 0x00000080 |
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| 120 | #define AGCSTS_P2A_TCOUNT 0x00000040 |
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| 121 | |
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| 122 | #define AGCSTS_FS_P2A_EMPTY 0x00000020 |
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| 123 | #define AGCSTS_FS_P2A_HALF 0x00000010 |
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| 124 | #define AGCSTS_FS_P2A_FULL 0x00000008 |
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| 125 | |
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| 126 | #define AGCSTS_FS_A2P_EMPTY 0x00000004 |
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| 127 | #define AGCSTS_FS_A2P_HALF 0x00000002 |
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| 128 | #define AGCSTS_FS_A2P_FULL 0x00000001 |
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| 129 | |
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| 130 | /****************************************************************************/ |
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| 131 | /* AMCC - Add-on Interrupt Control/Status Register */ |
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| 132 | /****************************************************************************/ |
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| 133 | |
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| 134 | #define AINT_INT_MASK 0x00ff0000 |
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| 135 | #define AINT_SEL_MASK 0x0000ffff |
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| 136 | #define AINT_IS_ENSEL_MASK 0x00001f1f |
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| 137 | |
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| 138 | #define AINT_INT_ASSERTED 0x00800000 |
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| 139 | #define AINT_BM_ERROR 0x00200000 |
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| 140 | #define AINT_BIST_INT 0x00100000 |
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| 141 | |
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| 142 | #define AINT_RT_COMPLETE 0x00080000 |
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| 143 | #define AINT_WT_COMPLETE 0x00040000 |
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| 144 | |
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| 145 | #define AINT_OUT_MB_INT 0x00020000 |
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| 146 | #define AINT_IN_MB_INT 0x00010000 |
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| 147 | |
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| 148 | #define AINT_READ_COMPL 0x00008000 |
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| 149 | #define AINT_WRITE_COMPL 0x00004000 |
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| 150 | |
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| 151 | #define AINT_OMB_ENABLE 0x00001000 |
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| 152 | #define AINT_OMB_SELECT 0x00000c00 |
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| 153 | #define AINT_OMB_BYTE 0x00000300 |
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| 154 | |
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| 155 | #define AINT_IMB_ENABLE 0x00000010 |
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| 156 | #define AINT_IMB_SELECT 0x0000000c |
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| 157 | #define AINT_IMB_BYTE 0x00000003 |
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| 158 | |
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| 159 | /* these are bits from various different registers, needs cleanup XXX */ |
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| 160 | /* Enable Bus Mastering */ |
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| 161 | #define EN_A2P_TRANSFERS 0x00000400 |
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| 162 | /* FIFO Flag Reset */ |
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| 163 | #define RESET_A2P_FLAGS 0x04000000L |
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| 164 | /* FIFO Relative Priority */ |
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| 165 | #define A2P_HI_PRIORITY 0x00000100L |
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| 166 | /* Identify Interrupt Sources */ |
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| 167 | #define ANY_S593X_INT 0x00800000L |
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| 168 | #define READ_TC_INT 0x00080000L |
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| 169 | #define WRITE_TC_INT 0x00040000L |
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| 170 | #define IN_MB_INT 0x00020000L |
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| 171 | #define MASTER_ABORT_INT 0x00100000L |
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| 172 | #define TARGET_ABORT_INT 0x00200000L |
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| 173 | #define BUS_MASTER_INT 0x00200000L |
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| 174 | |
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| 175 | #endif |
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| 176 | |
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