1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * dmm32at.c |
4 | * Diamond Systems Diamond-MM-32-AT Comedi driver |
5 | * |
6 | * COMEDI - Linux Control and Measurement Device Interface |
7 | * Copyright (C) 2000 David A. Schleef <ds@schleef.org> |
8 | */ |
9 | |
10 | /* |
11 | * Driver: dmm32at |
12 | * Description: Diamond Systems Diamond-MM-32-AT |
13 | * Devices: [Diamond Systems] Diamond-MM-32-AT (dmm32at) |
14 | * Author: Perry J. Piplani <perry.j.piplani@nasa.gov> |
15 | * Updated: Fri Jun 4 09:13:24 CDT 2004 |
16 | * Status: experimental |
17 | * |
18 | * Configuration Options: |
19 | * comedi_config /dev/comedi0 dmm32at baseaddr,irq |
20 | * |
21 | * This driver is for the Diamond Systems MM-32-AT board |
22 | * http://www.diamondsystems.com/products/diamondmm32at |
23 | * |
24 | * It is being used on several projects inside NASA, without |
25 | * problems so far. For analog input commands, TRIG_EXT is not |
26 | * yet supported. |
27 | */ |
28 | |
29 | #include <linux/module.h> |
30 | #include <linux/delay.h> |
31 | #include <linux/interrupt.h> |
32 | #include <linux/comedi/comedidev.h> |
33 | #include <linux/comedi/comedi_8255.h> |
34 | |
35 | /* Board register addresses */ |
36 | #define DMM32AT_AI_START_CONV_REG 0x00 |
37 | #define DMM32AT_AI_LSB_REG 0x00 |
38 | #define DMM32AT_AUX_DOUT_REG 0x01 |
39 | #define DMM32AT_AUX_DOUT2 BIT(2) /* J3.42 - OUT2 (OUT2EN) */ |
40 | #define DMM32AT_AUX_DOUT1 BIT(1) /* J3.43 */ |
41 | #define DMM32AT_AUX_DOUT0 BIT(0) /* J3.44 - OUT0 (OUT0EN) */ |
42 | #define DMM32AT_AI_MSB_REG 0x01 |
43 | #define DMM32AT_AI_LO_CHAN_REG 0x02 |
44 | #define DMM32AT_AI_HI_CHAN_REG 0x03 |
45 | #define DMM32AT_AUX_DI_REG 0x04 |
46 | #define DMM32AT_AUX_DI_DACBUSY BIT(7) |
47 | #define DMM32AT_AUX_DI_CALBUSY BIT(6) |
48 | #define DMM32AT_AUX_DI3 BIT(3) /* J3.45 - ADCLK (CLKSEL) */ |
49 | #define DMM32AT_AUX_DI2 BIT(2) /* J3.46 - GATE12 (GT12EN) */ |
50 | #define DMM32AT_AUX_DI1 BIT(1) /* J3.47 - GATE0 (GT0EN) */ |
51 | #define DMM32AT_AUX_DI0 BIT(0) /* J3.48 - CLK0 (SRC0) */ |
52 | #define DMM32AT_AO_LSB_REG 0x04 |
53 | #define DMM32AT_AO_MSB_REG 0x05 |
54 | #define DMM32AT_AO_MSB_DACH(x) ((x) << 6) |
55 | #define DMM32AT_FIFO_DEPTH_REG 0x06 |
56 | #define DMM32AT_FIFO_CTRL_REG 0x07 |
57 | #define DMM32AT_FIFO_CTRL_FIFOEN BIT(3) |
58 | #define DMM32AT_FIFO_CTRL_SCANEN BIT(2) |
59 | #define DMM32AT_FIFO_CTRL_FIFORST BIT(1) |
60 | #define DMM32AT_FIFO_STATUS_REG 0x07 |
61 | #define DMM32AT_FIFO_STATUS_EF BIT(7) |
62 | #define DMM32AT_FIFO_STATUS_HF BIT(6) |
63 | #define DMM32AT_FIFO_STATUS_FF BIT(5) |
64 | #define DMM32AT_FIFO_STATUS_OVF BIT(4) |
65 | #define DMM32AT_FIFO_STATUS_FIFOEN BIT(3) |
66 | #define DMM32AT_FIFO_STATUS_SCANEN BIT(2) |
67 | #define DMM32AT_FIFO_STATUS_PAGE_MASK (3 << 0) |
68 | #define DMM32AT_CTRL_REG 0x08 |
69 | #define DMM32AT_CTRL_RESETA BIT(5) |
70 | #define DMM32AT_CTRL_RESETD BIT(4) |
71 | #define DMM32AT_CTRL_INTRST BIT(3) |
72 | #define DMM32AT_CTRL_PAGE(x) ((x) << 0) |
73 | #define DMM32AT_CTRL_PAGE_8254 DMM32AT_CTRL_PAGE(0) |
74 | #define DMM32AT_CTRL_PAGE_8255 DMM32AT_CTRL_PAGE(1) |
75 | #define DMM32AT_CTRL_PAGE_CALIB DMM32AT_CTRL_PAGE(3) |
76 | #define DMM32AT_AI_STATUS_REG 0x08 |
77 | #define DMM32AT_AI_STATUS_STS BIT(7) |
78 | #define DMM32AT_AI_STATUS_SD1 BIT(6) |
79 | #define DMM32AT_AI_STATUS_SD0 BIT(5) |
80 | #define DMM32AT_AI_STATUS_ADCH_MASK (0x1f << 0) |
81 | #define DMM32AT_INTCLK_REG 0x09 |
82 | #define DMM32AT_INTCLK_ADINT BIT(7) |
83 | #define DMM32AT_INTCLK_DINT BIT(6) |
84 | #define DMM32AT_INTCLK_TINT BIT(5) |
85 | #define DMM32AT_INTCLK_CLKEN BIT(1) /* 1=see below 0=software */ |
86 | #define DMM32AT_INTCLK_CLKSEL BIT(0) /* 1=OUT2 0=EXTCLK */ |
87 | #define DMM32AT_CTRDIO_CFG_REG 0x0a |
88 | #define DMM32AT_CTRDIO_CFG_FREQ12 BIT(7) /* CLK12 1=100KHz 0=10MHz */ |
89 | #define DMM32AT_CTRDIO_CFG_FREQ0 BIT(6) /* CLK0 1=10KHz 0=10MHz */ |
90 | #define DMM32AT_CTRDIO_CFG_OUT2EN BIT(5) /* J3.42 1=OUT2 is DOUT2 */ |
91 | #define DMM32AT_CTRDIO_CFG_OUT0EN BIT(4) /* J3,44 1=OUT0 is DOUT0 */ |
92 | #define DMM32AT_CTRDIO_CFG_GT0EN BIT(2) /* J3.47 1=DIN1 is GATE0 */ |
93 | #define DMM32AT_CTRDIO_CFG_SRC0 BIT(1) /* CLK0 is 0=FREQ0 1=J3.48 */ |
94 | #define DMM32AT_CTRDIO_CFG_GT12EN BIT(0) /* J3.46 1=DIN2 is GATE12 */ |
95 | #define DMM32AT_AI_CFG_REG 0x0b |
96 | #define DMM32AT_AI_CFG_SCINT(x) ((x) << 4) |
97 | #define DMM32AT_AI_CFG_SCINT_20US DMM32AT_AI_CFG_SCINT(0) |
98 | #define DMM32AT_AI_CFG_SCINT_15US DMM32AT_AI_CFG_SCINT(1) |
99 | #define DMM32AT_AI_CFG_SCINT_10US DMM32AT_AI_CFG_SCINT(2) |
100 | #define DMM32AT_AI_CFG_SCINT_5US DMM32AT_AI_CFG_SCINT(3) |
101 | #define DMM32AT_AI_CFG_RANGE BIT(3) /* 0=5V 1=10V */ |
102 | #define DMM32AT_AI_CFG_ADBU BIT(2) /* 0=bipolar 1=unipolar */ |
103 | #define DMM32AT_AI_CFG_GAIN(x) ((x) << 0) |
104 | #define DMM32AT_AI_READBACK_REG 0x0b |
105 | #define DMM32AT_AI_READBACK_WAIT BIT(7) /* DMM32AT_AI_STATUS_STS */ |
106 | #define DMM32AT_AI_READBACK_RANGE BIT(3) |
107 | #define DMM32AT_AI_READBACK_ADBU BIT(2) |
108 | #define DMM32AT_AI_READBACK_GAIN_MASK (3 << 0) |
109 | |
110 | #define DMM32AT_CLK1 0x0d |
111 | #define DMM32AT_CLK2 0x0e |
112 | #define DMM32AT_CLKCT 0x0f |
113 | |
114 | #define DMM32AT_8255_IOBASE 0x0c /* Page 1 registers */ |
115 | |
116 | /* Board register values. */ |
117 | |
118 | /* DMM32AT_AI_CFG_REG 0x0b */ |
119 | #define DMM32AT_RANGE_U10 0x0c |
120 | #define DMM32AT_RANGE_U5 0x0d |
121 | #define DMM32AT_RANGE_B10 0x08 |
122 | #define DMM32AT_RANGE_B5 0x00 |
123 | |
124 | /* DMM32AT_CLKCT 0x0f */ |
125 | #define DMM32AT_CLKCT1 0x56 /* mode3 counter 1 - write low byte only */ |
126 | #define DMM32AT_CLKCT2 0xb6 /* mode3 counter 2 - write high and low byte */ |
127 | |
128 | /* board AI ranges in comedi structure */ |
129 | static const struct comedi_lrange dmm32at_airanges = { |
130 | 4, { |
131 | UNI_RANGE(10), |
132 | UNI_RANGE(5), |
133 | BIP_RANGE(10), |
134 | BIP_RANGE(5) |
135 | } |
136 | }; |
137 | |
138 | /* register values for above ranges */ |
139 | static const unsigned char dmm32at_rangebits[] = { |
140 | DMM32AT_RANGE_U10, |
141 | DMM32AT_RANGE_U5, |
142 | DMM32AT_RANGE_B10, |
143 | DMM32AT_RANGE_B5, |
144 | }; |
145 | |
146 | /* only one of these ranges is valid, as set by a jumper on the |
147 | * board. The application should only use the range set by the jumper |
148 | */ |
149 | static const struct comedi_lrange dmm32at_aoranges = { |
150 | 4, { |
151 | UNI_RANGE(10), |
152 | UNI_RANGE(5), |
153 | BIP_RANGE(10), |
154 | BIP_RANGE(5) |
155 | } |
156 | }; |
157 | |
158 | static void dmm32at_ai_set_chanspec(struct comedi_device *dev, |
159 | struct comedi_subdevice *s, |
160 | unsigned int chanspec, int nchan) |
161 | { |
162 | unsigned int chan = CR_CHAN(chanspec); |
163 | unsigned int range = CR_RANGE(chanspec); |
164 | unsigned int last_chan = (chan + nchan - 1) % s->n_chan; |
165 | |
166 | outb(DMM32AT_FIFO_CTRL_FIFORST, port: dev->iobase + DMM32AT_FIFO_CTRL_REG); |
167 | |
168 | if (nchan > 1) |
169 | outb(DMM32AT_FIFO_CTRL_SCANEN, |
170 | port: dev->iobase + DMM32AT_FIFO_CTRL_REG); |
171 | |
172 | outb(value: chan, port: dev->iobase + DMM32AT_AI_LO_CHAN_REG); |
173 | outb(value: last_chan, port: dev->iobase + DMM32AT_AI_HI_CHAN_REG); |
174 | outb(value: dmm32at_rangebits[range], port: dev->iobase + DMM32AT_AI_CFG_REG); |
175 | } |
176 | |
177 | static unsigned int dmm32at_ai_get_sample(struct comedi_device *dev, |
178 | struct comedi_subdevice *s) |
179 | { |
180 | unsigned int val; |
181 | |
182 | val = inb(port: dev->iobase + DMM32AT_AI_LSB_REG); |
183 | val |= (inb(port: dev->iobase + DMM32AT_AI_MSB_REG) << 8); |
184 | |
185 | /* munge two's complement value to offset binary */ |
186 | return comedi_offset_munge(s, val); |
187 | } |
188 | |
189 | static int dmm32at_ai_status(struct comedi_device *dev, |
190 | struct comedi_subdevice *s, |
191 | struct comedi_insn *insn, |
192 | unsigned long context) |
193 | { |
194 | unsigned char status; |
195 | |
196 | status = inb(port: dev->iobase + context); |
197 | if ((status & DMM32AT_AI_STATUS_STS) == 0) |
198 | return 0; |
199 | return -EBUSY; |
200 | } |
201 | |
202 | static int dmm32at_ai_insn_read(struct comedi_device *dev, |
203 | struct comedi_subdevice *s, |
204 | struct comedi_insn *insn, |
205 | unsigned int *data) |
206 | { |
207 | int ret; |
208 | int i; |
209 | |
210 | dmm32at_ai_set_chanspec(dev, s, chanspec: insn->chanspec, nchan: 1); |
211 | |
212 | /* wait for circuit to settle */ |
213 | ret = comedi_timeout(dev, s, insn, cb: dmm32at_ai_status, |
214 | DMM32AT_AI_READBACK_REG); |
215 | if (ret) |
216 | return ret; |
217 | |
218 | for (i = 0; i < insn->n; i++) { |
219 | outb(value: 0xff, port: dev->iobase + DMM32AT_AI_START_CONV_REG); |
220 | |
221 | ret = comedi_timeout(dev, s, insn, cb: dmm32at_ai_status, |
222 | DMM32AT_AI_STATUS_REG); |
223 | if (ret) |
224 | return ret; |
225 | |
226 | data[i] = dmm32at_ai_get_sample(dev, s); |
227 | } |
228 | |
229 | return insn->n; |
230 | } |
231 | |
232 | static int dmm32at_ai_check_chanlist(struct comedi_device *dev, |
233 | struct comedi_subdevice *s, |
234 | struct comedi_cmd *cmd) |
235 | { |
236 | unsigned int chan0 = CR_CHAN(cmd->chanlist[0]); |
237 | unsigned int range0 = CR_RANGE(cmd->chanlist[0]); |
238 | int i; |
239 | |
240 | for (i = 1; i < cmd->chanlist_len; i++) { |
241 | unsigned int chan = CR_CHAN(cmd->chanlist[i]); |
242 | unsigned int range = CR_RANGE(cmd->chanlist[i]); |
243 | |
244 | if (chan != (chan0 + i) % s->n_chan) { |
245 | dev_dbg(dev->class_dev, |
246 | "entries in chanlist must be consecutive channels, counting upwards\n" ); |
247 | return -EINVAL; |
248 | } |
249 | if (range != range0) { |
250 | dev_dbg(dev->class_dev, |
251 | "entries in chanlist must all have the same gain\n" ); |
252 | return -EINVAL; |
253 | } |
254 | } |
255 | |
256 | return 0; |
257 | } |
258 | |
259 | static int dmm32at_ai_cmdtest(struct comedi_device *dev, |
260 | struct comedi_subdevice *s, |
261 | struct comedi_cmd *cmd) |
262 | { |
263 | int err = 0; |
264 | unsigned int arg; |
265 | |
266 | /* Step 1 : check if triggers are trivially valid */ |
267 | |
268 | err |= comedi_check_trigger_src(src: &cmd->start_src, TRIG_NOW); |
269 | err |= comedi_check_trigger_src(src: &cmd->scan_begin_src, TRIG_TIMER); |
270 | err |= comedi_check_trigger_src(src: &cmd->convert_src, TRIG_TIMER); |
271 | err |= comedi_check_trigger_src(src: &cmd->scan_end_src, TRIG_COUNT); |
272 | err |= comedi_check_trigger_src(src: &cmd->stop_src, TRIG_COUNT | TRIG_NONE); |
273 | |
274 | if (err) |
275 | return 1; |
276 | |
277 | /* Step 2a : make sure trigger sources are unique */ |
278 | |
279 | err |= comedi_check_trigger_is_unique(src: cmd->stop_src); |
280 | |
281 | /* Step 2b : and mutually compatible */ |
282 | |
283 | if (err) |
284 | return 2; |
285 | |
286 | /* Step 3: check if arguments are trivially valid */ |
287 | |
288 | err |= comedi_check_trigger_arg_is(arg: &cmd->start_arg, val: 0); |
289 | |
290 | err |= comedi_check_trigger_arg_min(arg: &cmd->scan_begin_arg, val: 1000000); |
291 | err |= comedi_check_trigger_arg_max(arg: &cmd->scan_begin_arg, val: 1000000000); |
292 | |
293 | if (cmd->convert_arg >= 17500) |
294 | cmd->convert_arg = 20000; |
295 | else if (cmd->convert_arg >= 12500) |
296 | cmd->convert_arg = 15000; |
297 | else if (cmd->convert_arg >= 7500) |
298 | cmd->convert_arg = 10000; |
299 | else |
300 | cmd->convert_arg = 5000; |
301 | |
302 | err |= comedi_check_trigger_arg_is(arg: &cmd->scan_end_arg, |
303 | val: cmd->chanlist_len); |
304 | |
305 | if (cmd->stop_src == TRIG_COUNT) |
306 | err |= comedi_check_trigger_arg_min(arg: &cmd->stop_arg, val: 1); |
307 | else /* TRIG_NONE */ |
308 | err |= comedi_check_trigger_arg_is(arg: &cmd->stop_arg, val: 0); |
309 | |
310 | if (err) |
311 | return 3; |
312 | |
313 | /* Step 4: fix up any arguments */ |
314 | |
315 | arg = cmd->convert_arg * cmd->scan_end_arg; |
316 | err |= comedi_check_trigger_arg_min(arg: &cmd->scan_begin_arg, val: arg); |
317 | |
318 | if (err) |
319 | return 4; |
320 | |
321 | /* Step 5: check channel list if it exists */ |
322 | if (cmd->chanlist && cmd->chanlist_len > 0) |
323 | err |= dmm32at_ai_check_chanlist(dev, s, cmd); |
324 | |
325 | if (err) |
326 | return 5; |
327 | |
328 | return 0; |
329 | } |
330 | |
331 | static void dmm32at_setaitimer(struct comedi_device *dev, unsigned int nansec) |
332 | { |
333 | unsigned char lo1, lo2, hi2; |
334 | unsigned short both2; |
335 | |
336 | /* based on 10mhz clock */ |
337 | lo1 = 200; |
338 | both2 = nansec / 20000; |
339 | hi2 = (both2 & 0xff00) >> 8; |
340 | lo2 = both2 & 0x00ff; |
341 | |
342 | /* set counter clocks to 10MHz, disable all aux dio */ |
343 | outb(value: 0, port: dev->iobase + DMM32AT_CTRDIO_CFG_REG); |
344 | |
345 | /* get access to the clock regs */ |
346 | outb(DMM32AT_CTRL_PAGE_8254, port: dev->iobase + DMM32AT_CTRL_REG); |
347 | |
348 | /* write the counter 1 control word and low byte to counter */ |
349 | outb(DMM32AT_CLKCT1, port: dev->iobase + DMM32AT_CLKCT); |
350 | outb(value: lo1, port: dev->iobase + DMM32AT_CLK1); |
351 | |
352 | /* write the counter 2 control word and low byte then to counter */ |
353 | outb(DMM32AT_CLKCT2, port: dev->iobase + DMM32AT_CLKCT); |
354 | outb(value: lo2, port: dev->iobase + DMM32AT_CLK2); |
355 | outb(value: hi2, port: dev->iobase + DMM32AT_CLK2); |
356 | |
357 | /* enable the ai conversion interrupt and the clock to start scans */ |
358 | outb(DMM32AT_INTCLK_ADINT | |
359 | DMM32AT_INTCLK_CLKEN | DMM32AT_INTCLK_CLKSEL, |
360 | port: dev->iobase + DMM32AT_INTCLK_REG); |
361 | } |
362 | |
363 | static int dmm32at_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
364 | { |
365 | struct comedi_cmd *cmd = &s->async->cmd; |
366 | int ret; |
367 | |
368 | dmm32at_ai_set_chanspec(dev, s, chanspec: cmd->chanlist[0], nchan: cmd->chanlist_len); |
369 | |
370 | /* reset the interrupt just in case */ |
371 | outb(DMM32AT_CTRL_INTRST, port: dev->iobase + DMM32AT_CTRL_REG); |
372 | |
373 | /* |
374 | * wait for circuit to settle |
375 | * we don't have the 'insn' here but it's not needed |
376 | */ |
377 | ret = comedi_timeout(dev, s, NULL, cb: dmm32at_ai_status, |
378 | DMM32AT_AI_READBACK_REG); |
379 | if (ret) |
380 | return ret; |
381 | |
382 | if (cmd->stop_src == TRIG_NONE || cmd->stop_arg > 1) { |
383 | /* start the clock and enable the interrupts */ |
384 | dmm32at_setaitimer(dev, nansec: cmd->scan_begin_arg); |
385 | } else { |
386 | /* start the interrupts and initiate a single scan */ |
387 | outb(DMM32AT_INTCLK_ADINT, port: dev->iobase + DMM32AT_INTCLK_REG); |
388 | outb(value: 0xff, port: dev->iobase + DMM32AT_AI_START_CONV_REG); |
389 | } |
390 | |
391 | return 0; |
392 | } |
393 | |
394 | static int dmm32at_ai_cancel(struct comedi_device *dev, |
395 | struct comedi_subdevice *s) |
396 | { |
397 | /* disable further interrupts and clocks */ |
398 | outb(value: 0x0, port: dev->iobase + DMM32AT_INTCLK_REG); |
399 | return 0; |
400 | } |
401 | |
402 | static irqreturn_t dmm32at_isr(int irq, void *d) |
403 | { |
404 | struct comedi_device *dev = d; |
405 | unsigned char intstat; |
406 | unsigned short val; |
407 | int i; |
408 | |
409 | if (!dev->attached) { |
410 | dev_err(dev->class_dev, "spurious interrupt\n" ); |
411 | return IRQ_HANDLED; |
412 | } |
413 | |
414 | intstat = inb(port: dev->iobase + DMM32AT_INTCLK_REG); |
415 | |
416 | if (intstat & DMM32AT_INTCLK_ADINT) { |
417 | struct comedi_subdevice *s = dev->read_subdev; |
418 | struct comedi_cmd *cmd = &s->async->cmd; |
419 | |
420 | for (i = 0; i < cmd->chanlist_len; i++) { |
421 | val = dmm32at_ai_get_sample(dev, s); |
422 | comedi_buf_write_samples(s, data: &val, nsamples: 1); |
423 | } |
424 | |
425 | if (cmd->stop_src == TRIG_COUNT && |
426 | s->async->scans_done >= cmd->stop_arg) |
427 | s->async->events |= COMEDI_CB_EOA; |
428 | |
429 | comedi_handle_events(dev, s); |
430 | } |
431 | |
432 | /* reset the interrupt */ |
433 | outb(DMM32AT_CTRL_INTRST, port: dev->iobase + DMM32AT_CTRL_REG); |
434 | return IRQ_HANDLED; |
435 | } |
436 | |
437 | static int dmm32at_ao_eoc(struct comedi_device *dev, |
438 | struct comedi_subdevice *s, |
439 | struct comedi_insn *insn, |
440 | unsigned long context) |
441 | { |
442 | unsigned char status; |
443 | |
444 | status = inb(port: dev->iobase + DMM32AT_AUX_DI_REG); |
445 | if ((status & DMM32AT_AUX_DI_DACBUSY) == 0) |
446 | return 0; |
447 | return -EBUSY; |
448 | } |
449 | |
450 | static int dmm32at_ao_insn_write(struct comedi_device *dev, |
451 | struct comedi_subdevice *s, |
452 | struct comedi_insn *insn, |
453 | unsigned int *data) |
454 | { |
455 | unsigned int chan = CR_CHAN(insn->chanspec); |
456 | int i; |
457 | |
458 | for (i = 0; i < insn->n; i++) { |
459 | unsigned int val = data[i]; |
460 | int ret; |
461 | |
462 | /* write LSB then MSB + chan to load DAC */ |
463 | outb(value: val & 0xff, port: dev->iobase + DMM32AT_AO_LSB_REG); |
464 | outb(value: (val >> 8) | DMM32AT_AO_MSB_DACH(chan), |
465 | port: dev->iobase + DMM32AT_AO_MSB_REG); |
466 | |
467 | /* wait for circuit to settle */ |
468 | ret = comedi_timeout(dev, s, insn, cb: dmm32at_ao_eoc, context: 0); |
469 | if (ret) |
470 | return ret; |
471 | |
472 | /* dummy read to update DAC */ |
473 | inb(port: dev->iobase + DMM32AT_AO_MSB_REG); |
474 | |
475 | s->readback[chan] = val; |
476 | } |
477 | |
478 | return insn->n; |
479 | } |
480 | |
481 | static int dmm32at_8255_io(struct comedi_device *dev, |
482 | int dir, int port, int data, unsigned long regbase) |
483 | { |
484 | /* get access to the DIO regs */ |
485 | outb(DMM32AT_CTRL_PAGE_8255, port: dev->iobase + DMM32AT_CTRL_REG); |
486 | |
487 | if (dir) { |
488 | outb(value: data, port: dev->iobase + regbase + port); |
489 | return 0; |
490 | } |
491 | return inb(port: dev->iobase + regbase + port); |
492 | } |
493 | |
494 | /* Make sure the board is there and put it to a known state */ |
495 | static int dmm32at_reset(struct comedi_device *dev) |
496 | { |
497 | unsigned char aihi, ailo, fifostat, aistat, intstat, airback; |
498 | |
499 | /* reset the board */ |
500 | outb(DMM32AT_CTRL_RESETA, port: dev->iobase + DMM32AT_CTRL_REG); |
501 | |
502 | /* allow a millisecond to reset */ |
503 | usleep_range(min: 1000, max: 3000); |
504 | |
505 | /* zero scan and fifo control */ |
506 | outb(value: 0x0, port: dev->iobase + DMM32AT_FIFO_CTRL_REG); |
507 | |
508 | /* zero interrupt and clock control */ |
509 | outb(value: 0x0, port: dev->iobase + DMM32AT_INTCLK_REG); |
510 | |
511 | /* write a test channel range, the high 3 bits should drop */ |
512 | outb(value: 0x80, port: dev->iobase + DMM32AT_AI_LO_CHAN_REG); |
513 | outb(value: 0xff, port: dev->iobase + DMM32AT_AI_HI_CHAN_REG); |
514 | |
515 | /* set the range at 10v unipolar */ |
516 | outb(DMM32AT_RANGE_U10, port: dev->iobase + DMM32AT_AI_CFG_REG); |
517 | |
518 | /* should take 10 us to settle, here's a hundred */ |
519 | usleep_range(min: 100, max: 200); |
520 | |
521 | /* read back the values */ |
522 | ailo = inb(port: dev->iobase + DMM32AT_AI_LO_CHAN_REG); |
523 | aihi = inb(port: dev->iobase + DMM32AT_AI_HI_CHAN_REG); |
524 | fifostat = inb(port: dev->iobase + DMM32AT_FIFO_STATUS_REG); |
525 | aistat = inb(port: dev->iobase + DMM32AT_AI_STATUS_REG); |
526 | intstat = inb(port: dev->iobase + DMM32AT_INTCLK_REG); |
527 | airback = inb(port: dev->iobase + DMM32AT_AI_READBACK_REG); |
528 | |
529 | /* |
530 | * NOTE: The (DMM32AT_AI_STATUS_SD1 | DMM32AT_AI_STATUS_SD0) |
531 | * test makes this driver only work if the board is configured |
532 | * with all A/D channels set for single-ended operation. |
533 | */ |
534 | if (ailo != 0x00 || aihi != 0x1f || |
535 | fifostat != DMM32AT_FIFO_STATUS_EF || |
536 | aistat != (DMM32AT_AI_STATUS_SD1 | DMM32AT_AI_STATUS_SD0) || |
537 | intstat != 0x00 || airback != 0x0c) |
538 | return -EIO; |
539 | |
540 | return 0; |
541 | } |
542 | |
543 | static int dmm32at_attach(struct comedi_device *dev, |
544 | struct comedi_devconfig *it) |
545 | { |
546 | struct comedi_subdevice *s; |
547 | int ret; |
548 | |
549 | ret = comedi_request_region(dev, start: it->options[0], len: 0x10); |
550 | if (ret) |
551 | return ret; |
552 | |
553 | ret = dmm32at_reset(dev); |
554 | if (ret) { |
555 | dev_err(dev->class_dev, "board detection failed\n" ); |
556 | return ret; |
557 | } |
558 | |
559 | if (it->options[1]) { |
560 | ret = request_irq(irq: it->options[1], handler: dmm32at_isr, flags: 0, |
561 | name: dev->board_name, dev); |
562 | if (ret == 0) |
563 | dev->irq = it->options[1]; |
564 | } |
565 | |
566 | ret = comedi_alloc_subdevices(dev, num_subdevices: 3); |
567 | if (ret) |
568 | return ret; |
569 | |
570 | /* Analog Input subdevice */ |
571 | s = &dev->subdevices[0]; |
572 | s->type = COMEDI_SUBD_AI; |
573 | s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF; |
574 | s->n_chan = 32; |
575 | s->maxdata = 0xffff; |
576 | s->range_table = &dmm32at_airanges; |
577 | s->insn_read = dmm32at_ai_insn_read; |
578 | if (dev->irq) { |
579 | dev->read_subdev = s; |
580 | s->subdev_flags |= SDF_CMD_READ; |
581 | s->len_chanlist = s->n_chan; |
582 | s->do_cmd = dmm32at_ai_cmd; |
583 | s->do_cmdtest = dmm32at_ai_cmdtest; |
584 | s->cancel = dmm32at_ai_cancel; |
585 | } |
586 | |
587 | /* Analog Output subdevice */ |
588 | s = &dev->subdevices[1]; |
589 | s->type = COMEDI_SUBD_AO; |
590 | s->subdev_flags = SDF_WRITABLE; |
591 | s->n_chan = 4; |
592 | s->maxdata = 0x0fff; |
593 | s->range_table = &dmm32at_aoranges; |
594 | s->insn_write = dmm32at_ao_insn_write; |
595 | |
596 | ret = comedi_alloc_subdev_readback(s); |
597 | if (ret) |
598 | return ret; |
599 | |
600 | /* Digital I/O subdevice */ |
601 | s = &dev->subdevices[2]; |
602 | return subdev_8255_cb_init(dev, s, io: dmm32at_8255_io, |
603 | DMM32AT_8255_IOBASE); |
604 | } |
605 | |
606 | static struct comedi_driver dmm32at_driver = { |
607 | .driver_name = "dmm32at" , |
608 | .module = THIS_MODULE, |
609 | .attach = dmm32at_attach, |
610 | .detach = comedi_legacy_detach, |
611 | }; |
612 | module_comedi_driver(dmm32at_driver); |
613 | |
614 | MODULE_AUTHOR("Comedi https://www.comedi.org" ); |
615 | MODULE_DESCRIPTION("Comedi: Diamond Systems Diamond-MM-32-AT" ); |
616 | MODULE_LICENSE("GPL" ); |
617 | |