1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Z8536 CIO Internal registers |
4 | */ |
5 | |
6 | #ifndef _Z8536_H |
7 | #define _Z8536_H |
8 | |
9 | /* Master Interrupt Control register */ |
10 | #define Z8536_INT_CTRL_REG 0x00 |
11 | #define Z8536_INT_CTRL_MIE BIT(7) /* Master Interrupt Enable */ |
12 | #define Z8536_INT_CTRL_DLC BIT(6) /* Disable Lower Chain */ |
13 | #define Z8536_INT_CTRL_NV BIT(5) /* No Vector */ |
14 | #define Z8536_INT_CTRL_PA_VIS BIT(4) /* Port A Vect Inc Status */ |
15 | #define Z8536_INT_CTRL_PB_VIS BIT(3) /* Port B Vect Inc Status */ |
16 | #define Z8536_INT_CTRL_VT_VIS BIT(2) /* C/T Vect Inc Status */ |
17 | #define Z8536_INT_CTRL_RJA BIT(1) /* Right Justified Addresses */ |
18 | #define Z8536_INT_CTRL_RESET BIT(0) /* Reset */ |
19 | |
20 | /* Master Configuration Control register */ |
21 | #define Z8536_CFG_CTRL_REG 0x01 |
22 | #define Z8536_CFG_CTRL_PBE BIT(7) /* Port B Enable */ |
23 | #define Z8536_CFG_CTRL_CT1E BIT(6) /* C/T 1 Enable */ |
24 | #define Z8536_CFG_CTRL_CT2E BIT(5) /* C/T 2 Enable */ |
25 | #define Z8536_CFG_CTRL_PCE_CT3E BIT(4) /* Port C & C/T 3 Enable */ |
26 | #define Z8536_CFG_CTRL_PLC BIT(3) /* Port A/B Link Control */ |
27 | #define Z8536_CFG_CTRL_PAE BIT(2) /* Port A Enable */ |
28 | #define Z8536_CFG_CTRL_LC(x) (((x) & 0x3) << 0) /* Link Control */ |
29 | #define Z8536_CFG_CTRL_LC_INDEP Z8536_CFG_CTRL_LC(0)/* Independent */ |
30 | #define Z8536_CFG_CTRL_LC_GATE Z8536_CFG_CTRL_LC(1)/* 1 Gates 2 */ |
31 | #define Z8536_CFG_CTRL_LC_TRIG Z8536_CFG_CTRL_LC(2)/* 1 Triggers 2 */ |
32 | #define Z8536_CFG_CTRL_LC_CLK Z8536_CFG_CTRL_LC(3)/* 1 Clocks 2 */ |
33 | #define Z8536_CFG_CTRL_LC_MASK Z8536_CFG_CTRL_LC(3) |
34 | |
35 | /* Interrupt Vector registers */ |
36 | #define Z8536_PA_INT_VECT_REG 0x02 |
37 | #define Z8536_PB_INT_VECT_REG 0x03 |
38 | #define Z8536_CT_INT_VECT_REG 0x04 |
39 | #define Z8536_CURR_INT_VECT_REG 0x1f |
40 | |
41 | /* Port A/B & Counter/Timer 1/2/3 Command and Status registers */ |
42 | #define Z8536_PA_CMDSTAT_REG 0x08 |
43 | #define Z8536_PB_CMDSTAT_REG 0x09 |
44 | #define Z8536_CT1_CMDSTAT_REG 0x0a |
45 | #define Z8536_CT2_CMDSTAT_REG 0x0b |
46 | #define Z8536_CT3_CMDSTAT_REG 0x0c |
47 | #define Z8536_CT_CMDSTAT_REG(x) (0x0a + (x)) |
48 | #define Z8536_CMD(x) (((x) & 0x7) << 5) |
49 | #define Z8536_CMD_NULL Z8536_CMD(0) /* Null Code */ |
50 | #define Z8536_CMD_CLR_IP_IUS Z8536_CMD(1) /* Clear IP & IUS */ |
51 | #define Z8536_CMD_SET_IUS Z8536_CMD(2) /* Set IUS */ |
52 | #define Z8536_CMD_CLR_IUS Z8536_CMD(3) /* Clear IUS */ |
53 | #define Z8536_CMD_SET_IP Z8536_CMD(4) /* Set IP */ |
54 | #define Z8536_CMD_CLR_IP Z8536_CMD(5) /* Clear IP */ |
55 | #define Z8536_CMD_SET_IE Z8536_CMD(6) /* Set IE */ |
56 | #define Z8536_CMD_CLR_IE Z8536_CMD(7) /* Clear IE */ |
57 | #define Z8536_CMD_MASK Z8536_CMD(7) |
58 | |
59 | #define Z8536_STAT_IUS BIT(7) /* Interrupt Under Service */ |
60 | #define Z8536_STAT_IE BIT(6) /* Interrupt Enable */ |
61 | #define Z8536_STAT_IP BIT(5) /* Interrupt Pending */ |
62 | #define Z8536_STAT_ERR BIT(4) /* Interrupt Error */ |
63 | #define Z8536_STAT_IE_IP (Z8536_STAT_IE | Z8536_STAT_IP) |
64 | |
65 | #define Z8536_PAB_STAT_ORE BIT(3) /* Output Register Empty */ |
66 | #define Z8536_PAB_STAT_IRF BIT(2) /* Input Register Full */ |
67 | #define Z8536_PAB_STAT_PMF BIT(1) /* Pattern Match Flag */ |
68 | #define Z8536_PAB_CMDSTAT_IOE BIT(0) /* Interrupt On Error */ |
69 | |
70 | #define Z8536_CT_CMD_RCC BIT(3) /* Read Counter Control */ |
71 | #define Z8536_CT_CMDSTAT_GCB BIT(2) /* Gate Command Bit */ |
72 | #define Z8536_CT_CMD_TCB BIT(1) /* Trigger Command Bit */ |
73 | #define Z8536_CT_STAT_CIP BIT(0) /* Count In Progress */ |
74 | |
75 | /* Port Data registers */ |
76 | #define Z8536_PA_DATA_REG 0x0d |
77 | #define Z8536_PB_DATA_REG 0x0e |
78 | #define Z8536_PC_DATA_REG 0x0f |
79 | |
80 | /* Counter/Timer 1/2/3 Current Count registers */ |
81 | #define Z8536_CT1_VAL_MSB_REG 0x10 |
82 | #define Z8536_CT1_VAL_LSB_REG 0x11 |
83 | #define Z8536_CT2_VAL_MSB_REG 0x12 |
84 | #define Z8536_CT2_VAL_LSB_REG 0x13 |
85 | #define Z8536_CT3_VAL_MSB_REG 0x14 |
86 | #define Z8536_CT3_VAL_LSB_REG 0x15 |
87 | #define Z8536_CT_VAL_MSB_REG(x) (0x10 + ((x) * 2)) |
88 | #define Z8536_CT_VAL_LSB_REG(x) (0x11 + ((x) * 2)) |
89 | |
90 | /* Counter/Timer 1/2/3 Time Constant registers */ |
91 | #define Z8536_CT1_RELOAD_MSB_REG 0x16 |
92 | #define Z8536_CT1_RELOAD_LSB_REG 0x17 |
93 | #define Z8536_CT2_RELOAD_MSB_REG 0x18 |
94 | #define Z8536_CT2_RELOAD_LSB_REG 0x19 |
95 | #define Z8536_CT3_RELOAD_MSB_REG 0x1a |
96 | #define Z8536_CT3_RELOAD_LSB_REG 0x1b |
97 | #define Z8536_CT_RELOAD_MSB_REG(x) (0x16 + ((x) * 2)) |
98 | #define Z8536_CT_RELOAD_LSB_REG(x) (0x17 + ((x) * 2)) |
99 | |
100 | /* Counter/Timer 1/2/3 Mode Specification registers */ |
101 | #define Z8536_CT1_MODE_REG 0x1c |
102 | #define Z8536_CT2_MODE_REG 0x1d |
103 | #define Z8536_CT3_MODE_REG 0x1e |
104 | #define Z8536_CT_MODE_REG(x) (0x1c + (x)) |
105 | #define Z8536_CT_MODE_CSC BIT(7) /* Continuous/Single Cycle */ |
106 | #define Z8536_CT_MODE_EOE BIT(6) /* External Output Enable */ |
107 | #define Z8536_CT_MODE_ECE BIT(5) /* External Count Enable */ |
108 | #define Z8536_CT_MODE_ETE BIT(4) /* External Trigger Enable */ |
109 | #define Z8536_CT_MODE_EGE BIT(3) /* External Gate Enable */ |
110 | #define Z8536_CT_MODE_REB BIT(2) /* Retrigger Enable Bit */ |
111 | #define Z8536_CT_MODE_DCS(x) (((x) & 0x3) << 0) /* Duty Cycle */ |
112 | #define Z8536_CT_MODE_DCS_PULSE Z8536_CT_MODE_DCS(0) /* Pulse */ |
113 | #define Z8536_CT_MODE_DCS_ONESHOT Z8536_CT_MODE_DCS(1) /* One-Shot */ |
114 | #define Z8536_CT_MODE_DCS_SQRWAVE Z8536_CT_MODE_DCS(2) /* Square Wave */ |
115 | #define Z8536_CT_MODE_DCS_DO_NOT_USE Z8536_CT_MODE_DCS(3) /* Do Not Use */ |
116 | #define Z8536_CT_MODE_DCS_MASK Z8536_CT_MODE_DCS(3) |
117 | |
118 | /* Port A/B Mode Specification registers */ |
119 | #define Z8536_PA_MODE_REG 0x20 |
120 | #define Z8536_PB_MODE_REG 0x28 |
121 | #define Z8536_PAB_MODE_PTS(x) (((x) & 0x3) << 6) /* Port type */ |
122 | #define Z8536_PAB_MODE_PTS_BIT Z8536_PAB_MODE_PTS(0 << 6)/* Bit */ |
123 | #define Z8536_PAB_MODE_PTS_INPUT Z8536_PAB_MODE_PTS(1 << 6)/* Input */ |
124 | #define Z8536_PAB_MODE_PTS_OUTPUT Z8536_PAB_MODE_PTS(2 << 6)/* Output */ |
125 | #define Z8536_PAB_MODE_PTS_BIDIR Z8536_PAB_MODE_PTS(3 << 6)/* Bidir */ |
126 | #define Z8536_PAB_MODE_PTS_MASK Z8536_PAB_MODE_PTS(3 << 6) |
127 | #define Z8536_PAB_MODE_ITB BIT(5) /* Interrupt on Two Bytes */ |
128 | #define Z8536_PAB_MODE_SB BIT(4) /* Single Buffered mode */ |
129 | #define Z8536_PAB_MODE_IMO BIT(3) /* Interrupt on Match Only */ |
130 | #define Z8536_PAB_MODE_PMS(x) (((x) & 0x3) << 1) /* Pattern Mode */ |
131 | #define Z8536_PAB_MODE_PMS_DISABLE Z8536_PAB_MODE_PMS(0)/* Disabled */ |
132 | #define Z8536_PAB_MODE_PMS_AND Z8536_PAB_MODE_PMS(1)/* "AND" */ |
133 | #define Z8536_PAB_MODE_PMS_OR Z8536_PAB_MODE_PMS(2)/* "OR" */ |
134 | #define Z8536_PAB_MODE_PMS_OR_PEV Z8536_PAB_MODE_PMS(3)/* "OR-Priority" */ |
135 | #define Z8536_PAB_MODE_PMS_MASK Z8536_PAB_MODE_PMS(3) |
136 | #define Z8536_PAB_MODE_LPM BIT(0) /* Latch on Pattern Match */ |
137 | #define Z8536_PAB_MODE_DTE BIT(0) /* Deskew Timer Enabled */ |
138 | |
139 | /* Port A/B Handshake Specification registers */ |
140 | #define Z8536_PA_HANDSHAKE_REG 0x21 |
141 | #define Z8536_PB_HANDSHAKE_REG 0x29 |
142 | #define Z8536_PAB_HANDSHAKE_HST(x) (((x) & 0x3) << 6) /* Handshake Type */ |
143 | #define Z8536_PAB_HANDSHAKE_HST_INTER Z8536_PAB_HANDSHAKE_HST(0)/*Interlock*/ |
144 | #define Z8536_PAB_HANDSHAKE_HST_STROBED Z8536_PAB_HANDSHAKE_HST(1)/* Strobed */ |
145 | #define Z8536_PAB_HANDSHAKE_HST_PULSED Z8536_PAB_HANDSHAKE_HST(2)/* Pulsed */ |
146 | #define Z8536_PAB_HANDSHAKE_HST_3WIRE Z8536_PAB_HANDSHAKE_HST(3)/* 3-Wire */ |
147 | #define Z8536_PAB_HANDSHAKE_HST_MASK Z8536_PAB_HANDSHAKE_HST(3) |
148 | #define Z8536_PAB_HANDSHAKE_RWS(x) (((x) & 0x7) << 3) /* Req/Wait */ |
149 | #define Z8536_PAB_HANDSHAKE_RWS_DISABLE Z8536_PAB_HANDSHAKE_RWS(0)/* Disabled */ |
150 | #define Z8536_PAB_HANDSHAKE_RWS_OUTWAIT Z8536_PAB_HANDSHAKE_RWS(1)/* Out Wait */ |
151 | #define Z8536_PAB_HANDSHAKE_RWS_INWAIT Z8536_PAB_HANDSHAKE_RWS(3)/* In Wait */ |
152 | #define Z8536_PAB_HANDSHAKE_RWS_SPREQ Z8536_PAB_HANDSHAKE_RWS(4)/* Special */ |
153 | #define Z8536_PAB_HANDSHAKE_RWS_OUTREQ Z8536_PAB_HANDSHAKE_RWS(5)/* Out Req */ |
154 | #define Z8536_PAB_HANDSHAKE_RWS_INREQ Z8536_PAB_HANDSHAKE_RWS(7)/* In Req */ |
155 | #define Z8536_PAB_HANDSHAKE_RWS_MASK Z8536_PAB_HANDSHAKE_RWS(7) |
156 | #define Z8536_PAB_HANDSHAKE_DESKEW(x) ((x) << 0)/* Deskew Time */ |
157 | #define Z8536_PAB_HANDSHAKE_DESKEW_MASK (3 << 0)/* Deskew Time mask */ |
158 | |
159 | /* |
160 | * Port A/B/C Data Path Polarity registers |
161 | * |
162 | * 0 = Non-Inverting |
163 | * 1 = Inverting |
164 | */ |
165 | #define Z8536_PA_DPP_REG 0x22 |
166 | #define Z8536_PB_DPP_REG 0x2a |
167 | #define Z8536_PC_DPP_REG 0x05 |
168 | |
169 | /* |
170 | * Port A/B/C Data Direction registers |
171 | * |
172 | * 0 = Output bit |
173 | * 1 = Input bit |
174 | */ |
175 | #define Z8536_PA_DD_REG 0x23 |
176 | #define Z8536_PB_DD_REG 0x2b |
177 | #define Z8536_PC_DD_REG 0x06 |
178 | |
179 | /* |
180 | * Port A/B/C Special I/O Control registers |
181 | * |
182 | * 0 = Normal Input or Output |
183 | * 1 = Output with open drain or Input with 1's catcher |
184 | */ |
185 | #define Z8536_PA_SIO_REG 0x24 |
186 | #define Z8536_PB_SIO_REG 0x2c |
187 | #define Z8536_PC_SIO_REG 0x07 |
188 | |
189 | /* |
190 | * Port A/B Pattern Polarity/Transition/Mask registers |
191 | * |
192 | * PM PT PP Pattern Specification |
193 | * -- -- -- ------------------------------------- |
194 | * 0 0 x Bit masked off |
195 | * 0 1 x Any transition |
196 | * 1 0 0 Zero (low-level) |
197 | * 1 0 1 One (high-level) |
198 | * 1 1 0 One-to-zero transition (falling-edge) |
199 | * 1 1 1 Zero-to-one transition (rising-edge) |
200 | */ |
201 | #define Z8536_PA_PP_REG 0x25 |
202 | #define Z8536_PB_PP_REG 0x2d |
203 | |
204 | #define Z8536_PA_PT_REG 0x26 |
205 | #define Z8536_PB_PT_REG 0x2e |
206 | |
207 | #define Z8536_PA_PM_REG 0x27 |
208 | #define Z8536_PB_PM_REG 0x2f |
209 | |
210 | #endif /* _Z8536_H */ |
211 | |