1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * CAAM Error Reporting |
4 | * |
5 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
6 | */ |
7 | |
8 | #include "compat.h" |
9 | #include "regs.h" |
10 | #include "desc.h" |
11 | #include "error.h" |
12 | |
13 | #ifdef DEBUG |
14 | #include <linux/highmem.h> |
15 | |
16 | void caam_dump_sg(const char *prefix_str, int prefix_type, |
17 | int rowsize, int groupsize, struct scatterlist *sg, |
18 | size_t tlen, bool ascii) |
19 | { |
20 | struct scatterlist *it; |
21 | void *it_page; |
22 | size_t len; |
23 | void *buf; |
24 | |
25 | for (it = sg; it && tlen > 0 ; it = sg_next(it)) { |
26 | /* |
27 | * make sure the scatterlist's page |
28 | * has a valid virtual memory mapping |
29 | */ |
30 | it_page = kmap_atomic(sg_page(it)); |
31 | if (unlikely(!it_page)) { |
32 | pr_err("caam_dump_sg: kmap failed\n" ); |
33 | return; |
34 | } |
35 | |
36 | buf = it_page + it->offset; |
37 | len = min_t(size_t, tlen, it->length); |
38 | print_hex_dump_debug(prefix_str, prefix_type, rowsize, |
39 | groupsize, buf, len, ascii); |
40 | tlen -= len; |
41 | |
42 | kunmap_atomic(it_page); |
43 | } |
44 | } |
45 | #else |
46 | void caam_dump_sg(const char *prefix_str, int prefix_type, |
47 | int rowsize, int groupsize, struct scatterlist *sg, |
48 | size_t tlen, bool ascii) |
49 | {} |
50 | #endif /* DEBUG */ |
51 | EXPORT_SYMBOL(caam_dump_sg); |
52 | |
53 | bool caam_little_end; |
54 | EXPORT_SYMBOL(caam_little_end); |
55 | |
56 | bool caam_imx; |
57 | EXPORT_SYMBOL(caam_imx); |
58 | |
59 | size_t caam_ptr_sz; |
60 | EXPORT_SYMBOL(caam_ptr_sz); |
61 | |
62 | static const struct { |
63 | u8 value; |
64 | const char *error_text; |
65 | } desc_error_list[] = { |
66 | { 0x00, "No error." }, |
67 | { 0x01, "SGT Length Error. The descriptor is trying to read more data than is contained in the SGT table." }, |
68 | { 0x02, "SGT Null Entry Error." }, |
69 | { 0x03, "Job Ring Control Error. There is a bad value in the Job Ring Control register." }, |
70 | { 0x04, "Invalid Descriptor Command. The Descriptor Command field is invalid." }, |
71 | { 0x05, "Reserved." }, |
72 | { 0x06, "Invalid KEY Command" }, |
73 | { 0x07, "Invalid LOAD Command" }, |
74 | { 0x08, "Invalid STORE Command" }, |
75 | { 0x09, "Invalid OPERATION Command" }, |
76 | { 0x0A, "Invalid FIFO LOAD Command" }, |
77 | { 0x0B, "Invalid FIFO STORE Command" }, |
78 | { 0x0C, "Invalid MOVE/MOVE_LEN Command" }, |
79 | { 0x0D, "Invalid JUMP Command. A nonlocal JUMP Command is invalid because the target is not a Job Header Command, or the jump is from a Trusted Descriptor to a Job Descriptor, or because the target Descriptor contains a Shared Descriptor." }, |
80 | { 0x0E, "Invalid MATH Command" }, |
81 | { 0x0F, "Invalid SIGNATURE Command" }, |
82 | { 0x10, "Invalid Sequence Command. A SEQ IN PTR OR SEQ OUT PTR Command is invalid or a SEQ KEY, SEQ LOAD, SEQ FIFO LOAD, or SEQ FIFO STORE decremented the input or output sequence length below 0. This error may result if a built-in PROTOCOL Command has encountered a malformed PDU." }, |
83 | { 0x11, "Skip data type invalid. The type must be 0xE or 0xF." }, |
84 | { 0x12, "Shared Descriptor Header Error" }, |
85 | { 0x13, "Header Error. Invalid length or parity, or certain other problems." }, |
86 | { 0x14, "Burster Error. Burster has gotten to an illegal state" }, |
87 | { 0x15, "Context Register Length Error. The descriptor is trying to read or write past the end of the Context Register. A SEQ LOAD or SEQ STORE with the VLF bit set was executed with too large a length in the variable length register (VSOL for SEQ STORE or VSIL for SEQ LOAD)." }, |
88 | { 0x16, "DMA Error" }, |
89 | { 0x17, "Reserved." }, |
90 | { 0x1A, "Job failed due to JR reset" }, |
91 | { 0x1B, "Job failed due to Fail Mode" }, |
92 | { 0x1C, "DECO Watchdog timer timeout error" }, |
93 | { 0x1D, "DECO tried to copy a key from another DECO but the other DECO's Key Registers were locked" }, |
94 | { 0x1E, "DECO attempted to copy data from a DECO that had an unmasked Descriptor error" }, |
95 | { 0x1F, "LIODN error. DECO was trying to share from itself or from another DECO but the two Non-SEQ LIODN values didn't match or the 'shared from' DECO's Descriptor required that the SEQ LIODNs be the same and they aren't." }, |
96 | { 0x20, "DECO has completed a reset initiated via the DRR register" }, |
97 | { 0x21, "Nonce error. When using EKT (CCM) key encryption option in the FIFO STORE Command, the Nonce counter reached its maximum value and this encryption mode can no longer be used." }, |
98 | { 0x22, "Meta data is too large (> 511 bytes) for TLS decap (input frame; block ciphers) and IPsec decap (output frame, when doing the next header byte update) and DCRC (output frame)." }, |
99 | { 0x23, "Read Input Frame error" }, |
100 | { 0x24, "JDKEK, TDKEK or TDSK not loaded error" }, |
101 | { 0x80, "DNR (do not run) error" }, |
102 | { 0x81, "undefined protocol command" }, |
103 | { 0x82, "invalid setting in PDB" }, |
104 | { 0x83, "Anti-replay LATE error" }, |
105 | { 0x84, "Anti-replay REPLAY error" }, |
106 | { 0x85, "Sequence number overflow" }, |
107 | { 0x86, "Sigver invalid signature" }, |
108 | { 0x87, "DSA Sign Illegal test descriptor" }, |
109 | { 0x88, "Protocol Format Error - A protocol has seen an error in the format of data received. When running RSA, this means that formatting with random padding was used, and did not follow the form: 0x00, 0x02, 8-to-N bytes of non-zero pad, 0x00, F data." }, |
110 | { 0x89, "Protocol Size Error - A protocol has seen an error in size. When running RSA, pdb size N < (size of F) when no formatting is used; or pdb size N < (F + 11) when formatting is used." }, |
111 | { 0xC1, "Blob Command error: Undefined mode" }, |
112 | { 0xC2, "Blob Command error: Secure Memory Blob mode error" }, |
113 | { 0xC4, "Blob Command error: Black Blob key or input size error" }, |
114 | { 0xC5, "Blob Command error: Invalid key destination" }, |
115 | { 0xC8, "Blob Command error: Trusted/Secure mode error" }, |
116 | { 0xF0, "IPsec TTL or hop limit field either came in as 0, or was decremented to 0" }, |
117 | { 0xF1, "3GPP HFN matches or exceeds the Threshold" }, |
118 | }; |
119 | |
120 | static const struct { |
121 | u8 value; |
122 | const char *error_text; |
123 | } qi_error_list[] = { |
124 | { 0x00, "No error" }, |
125 | { 0x1F, "Job terminated by FQ or ICID flush" }, |
126 | { 0x20, "FD format error" }, |
127 | { 0x21, "FD command format error" }, |
128 | { 0x23, "FL format error" }, |
129 | { 0x25, "CRJD specified in FD, but not enabled in FLC" }, |
130 | { 0x30, "Max. buffer size too small" }, |
131 | { 0x31, "DHR exceeds max. buffer size (allocate mode, S/G format)" }, |
132 | { 0x32, "SGT exceeds max. buffer size (allocate mode, S/G format" }, |
133 | { 0x33, "Size over/underflow (allocate mode)" }, |
134 | { 0x34, "Size over/underflow (reuse mode)" }, |
135 | { 0x35, "Length exceeds max. short length (allocate mode, S/G/ format)" }, |
136 | { 0x36, "Memory footprint exceeds max. value (allocate mode, S/G/ format)" }, |
137 | { 0x41, "SBC frame format not supported (allocate mode)" }, |
138 | { 0x42, "Pool 0 invalid / pool 1 size < pool 0 size (allocate mode)" }, |
139 | { 0x43, "Annotation output enabled but ASAR = 0 (allocate mode)" }, |
140 | { 0x44, "Unsupported or reserved frame format or SGHR = 1 (reuse mode)" }, |
141 | { 0x45, "DHR correction underflow (reuse mode, single buffer format)" }, |
142 | { 0x46, "Annotation length exceeds offset (reuse mode)" }, |
143 | { 0x48, "Annotation output enabled but ASA limited by ASAR (reuse mode)" }, |
144 | { 0x49, "Data offset correction exceeds input frame data length (reuse mode)" }, |
145 | { 0x4B, "Annotation output enabled but ASA cannot be expanded (frame list)" }, |
146 | { 0x51, "Unsupported IF reuse mode" }, |
147 | { 0x52, "Unsupported FL use mode" }, |
148 | { 0x53, "Unsupported RJD use mode" }, |
149 | { 0x54, "Unsupported inline descriptor use mode" }, |
150 | { 0xC0, "Table buffer pool 0 depletion" }, |
151 | { 0xC1, "Table buffer pool 1 depletion" }, |
152 | { 0xC2, "Data buffer pool 0 depletion, no OF allocated" }, |
153 | { 0xC3, "Data buffer pool 1 depletion, no OF allocated" }, |
154 | { 0xC4, "Data buffer pool 0 depletion, partial OF allocated" }, |
155 | { 0xC5, "Data buffer pool 1 depletion, partial OF allocated" }, |
156 | { 0xD0, "FLC read error" }, |
157 | { 0xD1, "FL read error" }, |
158 | { 0xD2, "FL write error" }, |
159 | { 0xD3, "OF SGT write error" }, |
160 | { 0xD4, "PTA read error" }, |
161 | { 0xD5, "PTA write error" }, |
162 | { 0xD6, "OF SGT F-bit write error" }, |
163 | { 0xD7, "ASA write error" }, |
164 | { 0xE1, "FLC[ICR]=0 ICID error" }, |
165 | { 0xE2, "FLC[ICR]=1 ICID error" }, |
166 | { 0xE4, "source of ICID flush not trusted (BDI = 0)" }, |
167 | }; |
168 | |
169 | static const char * const cha_id_list[] = { |
170 | "" , |
171 | "AES" , |
172 | "DES" , |
173 | "ARC4" , |
174 | "MDHA" , |
175 | "RNG" , |
176 | "SNOW f8" , |
177 | "Kasumi f8/9" , |
178 | "PKHA" , |
179 | "CRCA" , |
180 | "SNOW f9" , |
181 | "ZUCE" , |
182 | "ZUCA" , |
183 | }; |
184 | |
185 | static const char * const err_id_list[] = { |
186 | "No error." , |
187 | "Mode error." , |
188 | "Data size error." , |
189 | "Key size error." , |
190 | "PKHA A memory size error." , |
191 | "PKHA B memory size error." , |
192 | "Data arrived out of sequence error." , |
193 | "PKHA divide-by-zero error." , |
194 | "PKHA modulus even error." , |
195 | "DES key parity error." , |
196 | "ICV check failed." , |
197 | "Hardware error." , |
198 | "Unsupported CCM AAD size." , |
199 | "Class 1 CHA is not reset" , |
200 | "Invalid CHA combination was selected" , |
201 | "Invalid CHA selected." , |
202 | }; |
203 | |
204 | static const char * const rng_err_id_list[] = { |
205 | "" , |
206 | "" , |
207 | "" , |
208 | "Instantiate" , |
209 | "Not instantiated" , |
210 | "Test instantiate" , |
211 | "Prediction resistance" , |
212 | "Prediction resistance and test request" , |
213 | "Uninstantiate" , |
214 | "Secure key generation" , |
215 | "" , |
216 | "Hardware error" , |
217 | "Continuous check" |
218 | }; |
219 | |
220 | static int report_ccb_status(struct device *jrdev, const u32 status, |
221 | const char *error) |
222 | { |
223 | u8 cha_id = (status & JRSTA_CCBERR_CHAID_MASK) >> |
224 | JRSTA_CCBERR_CHAID_SHIFT; |
225 | u8 err_id = status & JRSTA_CCBERR_ERRID_MASK; |
226 | u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >> |
227 | JRSTA_DECOERR_INDEX_SHIFT; |
228 | char *idx_str; |
229 | const char *cha_str = "unidentified cha_id value 0x" ; |
230 | char cha_err_code[3] = { 0 }; |
231 | const char *err_str = "unidentified err_id value 0x" ; |
232 | char err_err_code[3] = { 0 }; |
233 | |
234 | if (status & JRSTA_DECOERR_JUMP) |
235 | idx_str = "jump tgt desc idx" ; |
236 | else |
237 | idx_str = "desc idx" ; |
238 | |
239 | if (cha_id < ARRAY_SIZE(cha_id_list)) |
240 | cha_str = cha_id_list[cha_id]; |
241 | else |
242 | snprintf(buf: cha_err_code, size: sizeof(cha_err_code), fmt: "%02x" , cha_id); |
243 | |
244 | if ((cha_id << JRSTA_CCBERR_CHAID_SHIFT) == JRSTA_CCBERR_CHAID_RNG && |
245 | err_id < ARRAY_SIZE(rng_err_id_list) && |
246 | strlen(rng_err_id_list[err_id])) { |
247 | /* RNG-only error */ |
248 | err_str = rng_err_id_list[err_id]; |
249 | } else { |
250 | err_str = err_id_list[err_id]; |
251 | } |
252 | |
253 | /* |
254 | * CCB ICV check failures are part of normal operation life; |
255 | * we leave the upper layers to do what they want with them. |
256 | */ |
257 | if (err_id == JRSTA_CCBERR_ERRID_ICVCHK) |
258 | return -EBADMSG; |
259 | |
260 | dev_err_ratelimited(jrdev, "%08x: %s: %s %d: %s%s: %s%s\n" , status, |
261 | error, idx_str, idx, cha_str, cha_err_code, |
262 | err_str, err_err_code); |
263 | |
264 | return -EINVAL; |
265 | } |
266 | |
267 | static int report_jump_status(struct device *jrdev, const u32 status, |
268 | const char *error) |
269 | { |
270 | dev_err(jrdev, "%08x: %s: %s() not implemented\n" , |
271 | status, error, __func__); |
272 | |
273 | return -EINVAL; |
274 | } |
275 | |
276 | static int report_deco_status(struct device *jrdev, const u32 status, |
277 | const char *error) |
278 | { |
279 | u8 err_id = status & JRSTA_DECOERR_ERROR_MASK; |
280 | u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >> |
281 | JRSTA_DECOERR_INDEX_SHIFT; |
282 | char *idx_str; |
283 | const char *err_str = "unidentified error value 0x" ; |
284 | char err_err_code[3] = { 0 }; |
285 | int i; |
286 | |
287 | if (status & JRSTA_DECOERR_JUMP) |
288 | idx_str = "jump tgt desc idx" ; |
289 | else |
290 | idx_str = "desc idx" ; |
291 | |
292 | for (i = 0; i < ARRAY_SIZE(desc_error_list); i++) |
293 | if (desc_error_list[i].value == err_id) |
294 | break; |
295 | |
296 | if (i != ARRAY_SIZE(desc_error_list) && desc_error_list[i].error_text) |
297 | err_str = desc_error_list[i].error_text; |
298 | else |
299 | snprintf(buf: err_err_code, size: sizeof(err_err_code), fmt: "%02x" , err_id); |
300 | |
301 | dev_err(jrdev, "%08x: %s: %s %d: %s%s\n" , |
302 | status, error, idx_str, idx, err_str, err_err_code); |
303 | |
304 | return -EINVAL; |
305 | } |
306 | |
307 | static int report_qi_status(struct device *qidev, const u32 status, |
308 | const char *error) |
309 | { |
310 | u8 err_id = status & JRSTA_QIERR_ERROR_MASK; |
311 | const char *err_str = "unidentified error value 0x" ; |
312 | char err_err_code[3] = { 0 }; |
313 | int i; |
314 | |
315 | for (i = 0; i < ARRAY_SIZE(qi_error_list); i++) |
316 | if (qi_error_list[i].value == err_id) |
317 | break; |
318 | |
319 | if (i != ARRAY_SIZE(qi_error_list) && qi_error_list[i].error_text) |
320 | err_str = qi_error_list[i].error_text; |
321 | else |
322 | snprintf(buf: err_err_code, size: sizeof(err_err_code), fmt: "%02x" , err_id); |
323 | |
324 | dev_err(qidev, "%08x: %s: %s%s\n" , |
325 | status, error, err_str, err_err_code); |
326 | |
327 | return -EINVAL; |
328 | } |
329 | |
330 | static int report_jr_status(struct device *jrdev, const u32 status, |
331 | const char *error) |
332 | { |
333 | dev_err(jrdev, "%08x: %s: %s() not implemented\n" , |
334 | status, error, __func__); |
335 | |
336 | return -EINVAL; |
337 | } |
338 | |
339 | static int report_cond_code_status(struct device *jrdev, const u32 status, |
340 | const char *error) |
341 | { |
342 | dev_err(jrdev, "%08x: %s: %s() not implemented\n" , |
343 | status, error, __func__); |
344 | |
345 | return -EINVAL; |
346 | } |
347 | |
348 | int caam_strstatus(struct device *jrdev, u32 status, bool qi_v2) |
349 | { |
350 | static const struct stat_src { |
351 | int (*report_ssed)(struct device *jrdev, const u32 status, |
352 | const char *error); |
353 | const char *error; |
354 | } status_src[16] = { |
355 | { NULL, "No error" }, |
356 | { NULL, NULL }, |
357 | { report_ccb_status, "CCB" }, |
358 | { report_jump_status, "Jump" }, |
359 | { report_deco_status, "DECO" }, |
360 | { report_qi_status, "Queue Manager Interface" }, |
361 | { report_jr_status, "Job Ring" }, |
362 | { report_cond_code_status, "Condition Code" }, |
363 | { NULL, NULL }, |
364 | { NULL, NULL }, |
365 | { NULL, NULL }, |
366 | { NULL, NULL }, |
367 | { NULL, NULL }, |
368 | { NULL, NULL }, |
369 | { NULL, NULL }, |
370 | { NULL, NULL }, |
371 | }; |
372 | u32 ssrc = status >> JRSTA_SSRC_SHIFT; |
373 | const char *error = status_src[ssrc].error; |
374 | |
375 | /* |
376 | * If there is an error handling function, call it to report the error. |
377 | * Otherwise print the error source name. |
378 | */ |
379 | if (status_src[ssrc].report_ssed) |
380 | return status_src[ssrc].report_ssed(jrdev, status, error); |
381 | |
382 | if (error) |
383 | dev_err(jrdev, "%d: %s\n" , ssrc, error); |
384 | else |
385 | dev_err(jrdev, "%d: unknown error source\n" , ssrc); |
386 | |
387 | return -EINVAL; |
388 | } |
389 | EXPORT_SYMBOL(caam_strstatus); |
390 | |
391 | MODULE_LICENSE("GPL" ); |
392 | MODULE_DESCRIPTION("FSL CAAM error reporting" ); |
393 | MODULE_AUTHOR("Freescale Semiconductor" ); |
394 | |