1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * CAAM/SEC 4.x driver backend |
4 | * Private/internal definitions between modules |
5 | * |
6 | * Copyright 2008-2011 Freescale Semiconductor, Inc. |
7 | * Copyright 2019, 2023 NXP |
8 | */ |
9 | |
10 | #ifndef INTERN_H |
11 | #define INTERN_H |
12 | |
13 | #include "ctrl.h" |
14 | #include <crypto/engine.h> |
15 | |
16 | /* Currently comes from Kconfig param as a ^2 (driver-required) */ |
17 | #define JOBR_DEPTH (1 << CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE) |
18 | |
19 | /* |
20 | * Maximum size for crypto-engine software queue based on Job Ring |
21 | * size (JOBR_DEPTH) and a THRESHOLD (reserved for the non-crypto-API |
22 | * requests that are not passed through crypto-engine) |
23 | */ |
24 | #define THRESHOLD 15 |
25 | #define CRYPTO_ENGINE_MAX_QLEN (JOBR_DEPTH - THRESHOLD) |
26 | |
27 | /* Kconfig params for interrupt coalescing if selected (else zero) */ |
28 | #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_INTC |
29 | #define JOBR_INTC JRCFG_ICEN |
30 | #define JOBR_INTC_TIME_THLD CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD |
31 | #define JOBR_INTC_COUNT_THLD CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD |
32 | #else |
33 | #define JOBR_INTC 0 |
34 | #define JOBR_INTC_TIME_THLD 0 |
35 | #define JOBR_INTC_COUNT_THLD 0 |
36 | #endif |
37 | |
38 | /* |
39 | * Storage for tracking each in-process entry moving across a ring |
40 | * Each entry on an output ring needs one of these |
41 | */ |
42 | struct caam_jrentry_info { |
43 | void (*callbk)(struct device *dev, u32 *desc, u32 status, void *arg); |
44 | void *cbkarg; /* Argument per ring entry */ |
45 | u32 *desc_addr_virt; /* Stored virt addr for postprocessing */ |
46 | dma_addr_t desc_addr_dma; /* Stored bus addr for done matching */ |
47 | u32 desc_size; /* Stored size for postprocessing, header derived */ |
48 | }; |
49 | |
50 | struct caam_jr_state { |
51 | dma_addr_t inpbusaddr; |
52 | dma_addr_t outbusaddr; |
53 | }; |
54 | |
55 | struct caam_jr_dequeue_params { |
56 | struct device *dev; |
57 | int enable_itr; |
58 | }; |
59 | |
60 | /* Private sub-storage for a single JobR */ |
61 | struct caam_drv_private_jr { |
62 | struct list_head list_node; /* Job Ring device list */ |
63 | struct device *dev; |
64 | int ridx; |
65 | struct caam_job_ring __iomem *rregs; /* JobR's register space */ |
66 | struct tasklet_struct irqtask; |
67 | struct caam_jr_dequeue_params tasklet_params; |
68 | int irq; /* One per queue */ |
69 | bool hwrng; |
70 | |
71 | /* Number of scatterlist crypt transforms active on the JobR */ |
72 | atomic_t tfm_count ____cacheline_aligned; |
73 | |
74 | /* Job ring info */ |
75 | struct caam_jrentry_info *entinfo; /* Alloc'ed 1 per ring entry */ |
76 | spinlock_t inplock ____cacheline_aligned; /* Input ring index lock */ |
77 | u32 inpring_avail; /* Number of free entries in input ring */ |
78 | int head; /* entinfo (s/w ring) head index */ |
79 | void *inpring; /* Base of input ring, alloc |
80 | * DMA-safe */ |
81 | int out_ring_read_index; /* Output index "tail" */ |
82 | int tail; /* entinfo (s/w ring) tail index */ |
83 | void *outring; /* Base of output ring, DMA-safe */ |
84 | struct crypto_engine *engine; |
85 | |
86 | struct caam_jr_state state; /* State of the JR during PM */ |
87 | }; |
88 | |
89 | struct caam_ctl_state { |
90 | struct masterid deco_mid[16]; |
91 | struct masterid jr_mid[4]; |
92 | u32 mcr; |
93 | u32 scfgr; |
94 | }; |
95 | |
96 | /* |
97 | * Driver-private storage for a single CAAM block instance |
98 | */ |
99 | struct caam_drv_private { |
100 | /* Physical-presence section */ |
101 | struct caam_ctrl __iomem *ctrl; /* controller region */ |
102 | struct caam_deco __iomem *deco; /* DECO/CCB views */ |
103 | struct caam_assurance __iomem *assure; |
104 | struct caam_queue_if __iomem *qi; /* QI control region */ |
105 | struct caam_job_ring __iomem *jr[4]; /* JobR's register space */ |
106 | |
107 | struct iommu_domain *domain; |
108 | |
109 | /* |
110 | * Detected geometry block. Filled in from device tree if powerpc, |
111 | * or from register-based version detection code |
112 | */ |
113 | u8 total_jobrs; /* Total Job Rings in device */ |
114 | u8 qi_present; /* Nonzero if QI present in device */ |
115 | u8 blob_present; /* Nonzero if BLOB support present in device */ |
116 | u8 mc_en; /* Nonzero if MC f/w is active */ |
117 | u8 optee_en; /* Nonzero if OP-TEE f/w is active */ |
118 | bool pr_support; /* RNG prediction resistance available */ |
119 | int secvio_irq; /* Security violation interrupt number */ |
120 | int virt_en; /* Virtualization enabled in CAAM */ |
121 | int era; /* CAAM Era (internal HW revision) */ |
122 | |
123 | #define RNG4_MAX_HANDLES 2 |
124 | /* RNG4 block */ |
125 | u32 rng4_sh_init; /* This bitmap shows which of the State |
126 | Handles of the RNG4 block are initialized |
127 | by this driver */ |
128 | |
129 | struct clk_bulk_data *clks; |
130 | int num_clks; |
131 | /* |
132 | * debugfs entries for developer view into driver/device |
133 | * variables at runtime. |
134 | */ |
135 | #ifdef CONFIG_DEBUG_FS |
136 | struct dentry *ctl; /* controller dir */ |
137 | struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap; |
138 | #endif |
139 | |
140 | int caam_off_during_pm; /* If the CAAM is reset after suspend */ |
141 | struct caam_ctl_state state; /* State of the CTL during PM */ |
142 | }; |
143 | |
144 | #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API |
145 | |
146 | int caam_algapi_init(struct device *dev); |
147 | void caam_algapi_exit(void); |
148 | |
149 | #else |
150 | |
151 | static inline int caam_algapi_init(struct device *dev) |
152 | { |
153 | return 0; |
154 | } |
155 | |
156 | static inline void caam_algapi_exit(void) |
157 | { |
158 | } |
159 | |
160 | #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API */ |
161 | |
162 | #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API |
163 | |
164 | int caam_algapi_hash_init(struct device *dev); |
165 | void caam_algapi_hash_exit(void); |
166 | |
167 | #else |
168 | |
169 | static inline int caam_algapi_hash_init(struct device *dev) |
170 | { |
171 | return 0; |
172 | } |
173 | |
174 | static inline void caam_algapi_hash_exit(void) |
175 | { |
176 | } |
177 | |
178 | #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API */ |
179 | |
180 | #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API |
181 | |
182 | int caam_pkc_init(struct device *dev); |
183 | void caam_pkc_exit(void); |
184 | |
185 | #else |
186 | |
187 | static inline int caam_pkc_init(struct device *dev) |
188 | { |
189 | return 0; |
190 | } |
191 | |
192 | static inline void caam_pkc_exit(void) |
193 | { |
194 | } |
195 | |
196 | #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API */ |
197 | |
198 | #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API |
199 | |
200 | int caam_rng_init(struct device *dev); |
201 | void caam_rng_exit(struct device *dev); |
202 | |
203 | #else |
204 | |
205 | static inline int caam_rng_init(struct device *dev) |
206 | { |
207 | return 0; |
208 | } |
209 | |
210 | static inline void caam_rng_exit(struct device *dev) {} |
211 | |
212 | #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API */ |
213 | |
214 | #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API |
215 | |
216 | int caam_prng_register(struct device *dev); |
217 | void caam_prng_unregister(void *data); |
218 | |
219 | #else |
220 | |
221 | static inline int caam_prng_register(struct device *dev) |
222 | { |
223 | return 0; |
224 | } |
225 | |
226 | static inline void caam_prng_unregister(void *data) {} |
227 | #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API */ |
228 | |
229 | #ifdef CONFIG_CAAM_QI |
230 | |
231 | int caam_qi_algapi_init(struct device *dev); |
232 | void caam_qi_algapi_exit(void); |
233 | |
234 | #else |
235 | |
236 | static inline int caam_qi_algapi_init(struct device *dev) |
237 | { |
238 | return 0; |
239 | } |
240 | |
241 | static inline void caam_qi_algapi_exit(void) |
242 | { |
243 | } |
244 | |
245 | #endif /* CONFIG_CAAM_QI */ |
246 | |
247 | static inline u64 caam_get_dma_mask(struct device *dev) |
248 | { |
249 | struct device_node *nprop = dev->of_node; |
250 | |
251 | if (caam_ptr_sz != sizeof(u64)) |
252 | return DMA_BIT_MASK(32); |
253 | |
254 | if (caam_dpaa2) |
255 | return DMA_BIT_MASK(49); |
256 | |
257 | if (of_device_is_compatible(device: nprop, "fsl,sec-v5.0-job-ring" ) || |
258 | of_device_is_compatible(device: nprop, "fsl,sec-v5.0" )) |
259 | return DMA_BIT_MASK(40); |
260 | |
261 | return DMA_BIT_MASK(36); |
262 | } |
263 | |
264 | |
265 | #endif /* INTERN_H */ |
266 | |