| 1 | /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ |
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| 2 | /* Copyright(c) 2014 - 2020 Intel Corporation */ |
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| 3 | #ifndef ADF_4XXX_HW_DATA_H_ |
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| 4 | #define ADF_4XXX_HW_DATA_H_ |
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| 5 | |
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| 6 | #include <linux/units.h> |
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| 7 | #include <adf_accel_devices.h> |
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| 8 | |
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| 9 | #define ADF_4XXX_MAX_ACCELENGINES 9 |
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| 10 | |
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| 11 | #define ADF_4XXX_ACCELENGINES_MASK (0x1FF) |
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| 12 | #define ADF_4XXX_ADMIN_AE_MASK (0x100) |
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| 13 | |
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| 14 | #define ADF_4XXX_HICPPAGENTCMDPARERRLOG_MASK 0x1F |
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| 15 | #define ADF_4XXX_PARITYERRORMASK_ATH_CPH_MASK 0xF000F |
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| 16 | #define ADF_4XXX_PARITYERRORMASK_CPR_XLT_MASK 0x10001 |
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| 17 | #define ADF_4XXX_PARITYERRORMASK_DCPR_UCS_MASK 0x30007 |
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| 18 | #define ADF_4XXX_PARITYERRORMASK_PKE_MASK 0x3F |
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| 19 | |
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| 20 | /* |
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| 21 | * SSMFEATREN bit mask |
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| 22 | * BIT(4) - enables parity detection on CPP |
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| 23 | * BIT(12) - enables the logging of push/pull data errors |
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| 24 | * in pperr register |
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| 25 | * BIT(16) - BIT(23) - enable parity detection on SPPs |
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| 26 | */ |
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| 27 | #define ADF_4XXX_SSMFEATREN_MASK \ |
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| 28 | (BIT(4) | BIT(12) | BIT(16) | BIT(17) | BIT(18) | \ |
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| 29 | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23)) |
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| 30 | |
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| 31 | /* Firmware Binaries */ |
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| 32 | #define ADF_4XXX_FW "qat_4xxx.bin" |
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| 33 | #define ADF_4XXX_MMP "qat_4xxx_mmp.bin" |
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| 34 | #define ADF_4XXX_SYM_OBJ "qat_4xxx_sym.bin" |
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| 35 | #define ADF_4XXX_DC_OBJ "qat_4xxx_dc.bin" |
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| 36 | #define ADF_4XXX_ASYM_OBJ "qat_4xxx_asym.bin" |
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| 37 | #define ADF_4XXX_ADMIN_OBJ "qat_4xxx_admin.bin" |
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| 38 | /* Firmware for 402XXX */ |
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| 39 | #define ADF_402XX_FW "qat_402xx.bin" |
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| 40 | #define ADF_402XX_MMP "qat_402xx_mmp.bin" |
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| 41 | #define ADF_402XX_SYM_OBJ "qat_402xx_sym.bin" |
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| 42 | #define ADF_402XX_DC_OBJ "qat_402xx_dc.bin" |
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| 43 | #define ADF_402XX_ASYM_OBJ "qat_402xx_asym.bin" |
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| 44 | #define ADF_402XX_ADMIN_OBJ "qat_402xx_admin.bin" |
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| 45 | |
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| 46 | /* RL constants */ |
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| 47 | #define ADF_4XXX_RL_PCIE_SCALE_FACTOR_DIV 100 |
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| 48 | #define ADF_4XXX_RL_PCIE_SCALE_FACTOR_MUL 102 |
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| 49 | #define ADF_4XXX_RL_DCPR_CORRECTION 1 |
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| 50 | #define ADF_4XXX_RL_SCANS_PER_SEC 954 |
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| 51 | #define ADF_4XXX_RL_MAX_TP_ASYM 173750UL |
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| 52 | #define ADF_4XXX_RL_MAX_TP_SYM 95000UL |
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| 53 | #define ADF_4XXX_RL_MAX_TP_DC 45000UL |
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| 54 | #define ADF_4XXX_RL_SLICE_REF 1000UL |
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| 55 | |
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| 56 | /* Clocks frequency */ |
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| 57 | #define ADF_4XXX_AE_FREQ (1000 * HZ_PER_MHZ) |
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| 58 | |
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| 59 | void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id); |
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| 60 | void adf_clean_hw_data_4xxx(struct adf_hw_device_data *hw_data); |
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| 61 | |
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| 62 | #endif |
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| 63 | |
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