1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright(c) 2025 Intel Corporation */
3#ifndef ADF_6XXX_HW_DATA_H_
4#define ADF_6XXX_HW_DATA_H_
5
6#include <linux/bits.h>
7#include <linux/time.h>
8#include <linux/units.h>
9
10#include "adf_accel_devices.h"
11#include "adf_cfg_common.h"
12#include "adf_dc.h"
13
14/* PCIe configuration space */
15#define ADF_GEN6_BAR_MASK (BIT(0) | BIT(2) | BIT(4))
16#define ADF_GEN6_SRAM_BAR 0
17#define ADF_GEN6_PMISC_BAR 1
18#define ADF_GEN6_ETR_BAR 2
19#define ADF_6XXX_MAX_ACCELENGINES 9
20
21/* Clocks frequency */
22#define ADF_GEN6_COUNTER_FREQ (100 * HZ_PER_MHZ)
23
24/* Physical function fuses */
25#define ADF_GEN6_FUSECTL0_OFFSET 0x2C8
26#define ADF_GEN6_FUSECTL1_OFFSET 0x2CC
27#define ADF_GEN6_FUSECTL4_OFFSET 0x2D8
28
29/* Accelerators */
30#define ADF_GEN6_ACCELERATORS_MASK 0x1
31#define ADF_GEN6_MAX_ACCELERATORS 1
32
33/* MSI-X interrupt */
34#define ADF_GEN6_SMIAPF_RP_X0_MASK_OFFSET 0x41A040
35#define ADF_GEN6_SMIAPF_RP_X1_MASK_OFFSET 0x41A044
36#define ADF_GEN6_SMIAPF_MASK_OFFSET 0x41A084
37#define ADF_GEN6_MSIX_RTTABLE_OFFSET(i) (0x409000 + ((i) * 4))
38
39/* Bank and ring configuration */
40#define ADF_GEN6_NUM_RINGS_PER_BANK 2
41#define ADF_GEN6_NUM_BANKS_PER_VF 4
42#define ADF_GEN6_ETR_MAX_BANKS 64
43#define ADF_GEN6_RX_RINGS_OFFSET 1
44#define ADF_GEN6_TX_RINGS_MASK 0x1
45
46/* Arbiter configuration */
47#define ADF_GEN6_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0))
48#define ADF_GEN6_ARB_OFFSET 0x000
49#define ADF_GEN6_ARB_WRK_2_SER_MAP_OFFSET 0x400
50
51/* Admin interface configuration */
52#define ADF_GEN6_ADMINMSGUR_OFFSET 0x500574
53#define ADF_GEN6_ADMINMSGLR_OFFSET 0x500578
54#define ADF_GEN6_MAILBOX_BASE_OFFSET 0x600970
55
56/*
57 * Watchdog timers
58 * Timeout is in cycles. Clock speed may vary across products but this
59 * value should be a few milli-seconds.
60 */
61#define ADF_SSM_WDT_DEFAULT_VALUE 0x7000000ULL
62#define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x8000000ULL
63#define ADF_SSMWDTATHL_OFFSET 0x5208
64#define ADF_SSMWDTATHH_OFFSET 0x520C
65#define ADF_SSMWDTCNVL_OFFSET 0x5408
66#define ADF_SSMWDTCNVH_OFFSET 0x540C
67#define ADF_SSMWDTUCSL_OFFSET 0x5808
68#define ADF_SSMWDTUCSH_OFFSET 0x580C
69#define ADF_SSMWDTDCPRL_OFFSET 0x5A08
70#define ADF_SSMWDTDCPRH_OFFSET 0x5A0C
71#define ADF_SSMWDTPKEL_OFFSET 0x5E08
72#define ADF_SSMWDTPKEH_OFFSET 0x5E0C
73
74/* Ring reset */
75#define ADF_RPRESET_POLL_TIMEOUT_US (5 * USEC_PER_SEC)
76#define ADF_RPRESET_POLL_DELAY_US 20
77#define ADF_WQM_CSR_RPRESETCTL_RESET BIT(0)
78#define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + (bank) * 8)
79#define ADF_WQM_CSR_RPRESETSTS_STATUS BIT(0)
80#define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4)
81
82/* Controls and sets up the corresponding ring mode of operation */
83#define ADF_GEN6_CSR_RINGMODECTL(bank) (0x9000 + (bank) * 4)
84
85/* Specifies the traffic class to use for the transactions to/from the ring */
86#define ADF_GEN6_RINGMODECTL_TC_MASK GENMASK(18, 16)
87#define ADF_GEN6_RINGMODECTL_TC_DEFAULT 0x7
88
89/* Specifies usage of tc for the transactions to/from this ring */
90#define ADF_GEN6_RINGMODECTL_TC_EN_MASK GENMASK(20, 19)
91
92/*
93 * Use the value programmed in the tc field for request descriptor
94 * and metadata read transactions
95 */
96#define ADF_GEN6_RINGMODECTL_TC_EN_OP1 0x1
97
98/* VC0 Resource Control Register */
99#define ADF_GEN6_PVC0CTL_OFFSET 0x204
100#define ADF_GEN6_PVC0CTL_TCVCMAP_OFFSET 1
101#define ADF_GEN6_PVC0CTL_TCVCMAP_MASK GENMASK(7, 1)
102#define ADF_GEN6_PVC0CTL_TCVCMAP_DEFAULT 0x7F
103
104/* VC1 Resource Control Register */
105#define ADF_GEN6_PVC1CTL_OFFSET 0x210
106#define ADF_GEN6_PVC1CTL_TCVCMAP_OFFSET 1
107#define ADF_GEN6_PVC1CTL_TCVCMAP_MASK GENMASK(7, 1)
108#define ADF_GEN6_PVC1CTL_TCVCMAP_DEFAULT 0x40
109#define ADF_GEN6_PVC1CTL_VCEN_OFFSET 31
110#define ADF_GEN6_PVC1CTL_VCEN_MASK BIT(31)
111/* RW bit: 0x1 - enables a Virtual Channel, 0x0 - disables */
112#define ADF_GEN6_PVC1CTL_VCEN_ON 0x1
113
114/* Error source mask registers */
115#define ADF_GEN6_ERRMSK0 0x41A210
116#define ADF_GEN6_ERRMSK1 0x41A214
117#define ADF_GEN6_ERRMSK2 0x41A218
118#define ADF_GEN6_ERRMSK3 0x41A21C
119
120#define ADF_GEN6_VFLNOTIFY BIT(7)
121
122/* Number of heartbeat counter pairs */
123#define ADF_NUM_HB_CNT_PER_AE ADF_NUM_THREADS_PER_AE
124
125/* Physical function fuses */
126#define ADF_6XXX_ACCELENGINES_MASK GENMASK(8, 0)
127#define ADF_6XXX_ADMIN_AE_MASK GENMASK(8, 8)
128
129/* Firmware binaries */
130#define ADF_6XXX_FW "qat_6xxx.bin"
131#define ADF_6XXX_MMP "qat_6xxx_mmp.bin"
132#define ADF_6XXX_CY_OBJ "qat_6xxx_cy.bin"
133#define ADF_6XXX_DC_OBJ "qat_6xxx_dc.bin"
134#define ADF_6XXX_ADMIN_OBJ "qat_6xxx_admin.bin"
135
136enum icp_qat_gen6_slice_mask {
137 ICP_ACCEL_GEN6_MASK_UCS_SLICE = BIT(0),
138 ICP_ACCEL_GEN6_MASK_AUTH_SLICE = BIT(1),
139 ICP_ACCEL_GEN6_MASK_PKE_SLICE = BIT(2),
140 ICP_ACCEL_GEN6_MASK_CPR_SLICE = BIT(3),
141 ICP_ACCEL_GEN6_MASK_DCPRZ_SLICE = BIT(4),
142 ICP_ACCEL_GEN6_MASK_WCP_WAT_SLICE = BIT(6),
143};
144
145void adf_init_hw_data_6xxx(struct adf_hw_device_data *hw_data);
146void adf_clean_hw_data_6xxx(struct adf_hw_device_data *hw_data);
147
148#endif /* ADF_6XXX_HW_DATA_H_ */
149

source code of linux/drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h