1 | /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ |
2 | /* Copyright(c) 2014 - 2020 Intel Corporation */ |
3 | #ifndef _ICP_QAT_FW_H_ |
4 | #define _ICP_QAT_FW_H_ |
5 | #include <linux/types.h> |
6 | #include "icp_qat_hw.h" |
7 | |
8 | #define QAT_FIELD_SET(flags, val, bitpos, mask) \ |
9 | { (flags) = (((flags) & (~((mask) << (bitpos)))) | \ |
10 | (((val) & (mask)) << (bitpos))) ; } |
11 | |
12 | #define QAT_FIELD_GET(flags, bitpos, mask) \ |
13 | (((flags) >> (bitpos)) & (mask)) |
14 | |
15 | #define ICP_QAT_FW_REQ_DEFAULT_SZ 128 |
16 | #define ICP_QAT_FW_RESP_DEFAULT_SZ 32 |
17 | #define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8 |
18 | #define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF |
19 | #define ICP_QAT_FW_NUM_LONGWORDS_1 1 |
20 | #define ICP_QAT_FW_NUM_LONGWORDS_2 2 |
21 | #define ICP_QAT_FW_NUM_LONGWORDS_3 3 |
22 | #define ICP_QAT_FW_NUM_LONGWORDS_4 4 |
23 | #define ICP_QAT_FW_NUM_LONGWORDS_5 5 |
24 | #define ICP_QAT_FW_NUM_LONGWORDS_6 6 |
25 | #define ICP_QAT_FW_NUM_LONGWORDS_7 7 |
26 | #define ICP_QAT_FW_NUM_LONGWORDS_10 10 |
27 | #define ICP_QAT_FW_NUM_LONGWORDS_13 13 |
28 | #define ICP_QAT_FW_NULL_REQ_SERV_ID 1 |
29 | |
30 | enum icp_qat_fw_comn_resp_serv_id { |
31 | ICP_QAT_FW_COMN_RESP_SERV_NULL, |
32 | ICP_QAT_FW_COMN_RESP_SERV_CPM_FW, |
33 | ICP_QAT_FW_COMN_RESP_SERV_DELIMITER |
34 | }; |
35 | |
36 | enum icp_qat_fw_comn_request_id { |
37 | ICP_QAT_FW_COMN_REQ_NULL = 0, |
38 | ICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3, |
39 | ICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4, |
40 | ICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7, |
41 | ICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9, |
42 | ICP_QAT_FW_COMN_REQ_DELIMITER |
43 | }; |
44 | |
45 | struct icp_qat_fw_comn_req_hdr_cd_pars { |
46 | union { |
47 | struct { |
48 | __u64 content_desc_addr; |
49 | __u16 content_desc_resrvd1; |
50 | __u8 content_desc_params_sz; |
51 | __u8 content_desc_hdr_resrvd2; |
52 | __u32 content_desc_resrvd3; |
53 | } s; |
54 | struct { |
55 | __u32 serv_specif_fields[4]; |
56 | } s1; |
57 | } u; |
58 | }; |
59 | |
60 | struct icp_qat_fw_comn_req_mid { |
61 | __u64 opaque_data; |
62 | __u64 src_data_addr; |
63 | __u64 dest_data_addr; |
64 | __u32 src_length; |
65 | __u32 dst_length; |
66 | }; |
67 | |
68 | struct icp_qat_fw_comn_req_cd_ctrl { |
69 | __u32 content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5]; |
70 | }; |
71 | |
72 | struct icp_qat_fw_comn_req_hdr { |
73 | __u8 resrvd1; |
74 | __u8 service_cmd_id; |
75 | __u8 service_type; |
76 | __u8 hdr_flags; |
77 | __u16 serv_specif_flags; |
78 | __u16 comn_req_flags; |
79 | }; |
80 | |
81 | struct icp_qat_fw_comn_req_rqpars { |
82 | __u32 serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13]; |
83 | }; |
84 | |
85 | struct icp_qat_fw_comn_req { |
86 | struct icp_qat_fw_comn_req_hdr comn_hdr; |
87 | struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars; |
88 | struct icp_qat_fw_comn_req_mid comn_mid; |
89 | struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars; |
90 | struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl; |
91 | }; |
92 | |
93 | struct icp_qat_fw_comn_error { |
94 | __u8 xlat_err_code; |
95 | __u8 cmp_err_code; |
96 | }; |
97 | |
98 | struct icp_qat_fw_comn_resp_hdr { |
99 | __u8 resrvd1; |
100 | __u8 service_id; |
101 | __u8 response_type; |
102 | __u8 hdr_flags; |
103 | struct icp_qat_fw_comn_error comn_error; |
104 | __u8 comn_status; |
105 | __u8 cmd_id; |
106 | }; |
107 | |
108 | struct icp_qat_fw_comn_resp { |
109 | struct icp_qat_fw_comn_resp_hdr comn_hdr; |
110 | __u64 opaque_data; |
111 | __u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_4]; |
112 | }; |
113 | |
114 | #define ICP_QAT_FW_COMN_REQ_FLAG_SET 1 |
115 | #define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0 |
116 | #define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7 |
117 | #define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1 |
118 | #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F |
119 | #define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6 |
120 | #define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1 |
121 | #define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5 |
122 | #define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1 |
123 | |
124 | #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \ |
125 | icp_qat_fw_comn_req_hdr_t.service_type |
126 | |
127 | #define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \ |
128 | icp_qat_fw_comn_req_hdr_t.service_type = val |
129 | |
130 | #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \ |
131 | icp_qat_fw_comn_req_hdr_t.service_cmd_id |
132 | |
133 | #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \ |
134 | icp_qat_fw_comn_req_hdr_t.service_cmd_id = val |
135 | |
136 | #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \ |
137 | ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags) |
138 | |
139 | #define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags) \ |
140 | QAT_FIELD_GET(hdr_flags, \ |
141 | ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \ |
142 | ICP_QAT_FW_COMN_CNVNR_FLAG_MASK) |
143 | |
144 | #define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_SET(hdr_t, val) \ |
145 | QAT_FIELD_SET((hdr_t.hdr_flags), (val), \ |
146 | ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \ |
147 | ICP_QAT_FW_COMN_CNVNR_FLAG_MASK) |
148 | |
149 | #define ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(hdr_flags) \ |
150 | QAT_FIELD_GET(hdr_flags, \ |
151 | ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \ |
152 | ICP_QAT_FW_COMN_CNV_FLAG_MASK) |
153 | |
154 | #define ICP_QAT_FW_COMN_HDR_CNV_FLAG_SET(hdr_t, val) \ |
155 | QAT_FIELD_SET((hdr_t.hdr_flags), (val), \ |
156 | ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \ |
157 | ICP_QAT_FW_COMN_CNV_FLAG_MASK) |
158 | |
159 | #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \ |
160 | ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) |
161 | |
162 | #define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \ |
163 | QAT_FIELD_GET(hdr_flags, \ |
164 | ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \ |
165 | ICP_QAT_FW_COMN_VALID_FLAG_MASK) |
166 | |
167 | #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \ |
168 | (hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK) |
169 | |
170 | #define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \ |
171 | QAT_FIELD_SET((hdr_t.hdr_flags), (val), \ |
172 | ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \ |
173 | ICP_QAT_FW_COMN_VALID_FLAG_MASK) |
174 | |
175 | #define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \ |
176 | (((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \ |
177 | ICP_QAT_FW_COMN_VALID_FLAG_BITPOS) |
178 | |
179 | #define QAT_COMN_PTR_TYPE_BITPOS 0 |
180 | #define QAT_COMN_PTR_TYPE_MASK 0x1 |
181 | #define QAT_COMN_CD_FLD_TYPE_BITPOS 1 |
182 | #define QAT_COMN_CD_FLD_TYPE_MASK 0x1 |
183 | #define QAT_COMN_PTR_TYPE_FLAT 0x0 |
184 | #define QAT_COMN_PTR_TYPE_SGL 0x1 |
185 | #define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0 |
186 | #define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1 |
187 | |
188 | #define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \ |
189 | ((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \ |
190 | | (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS)) |
191 | |
192 | #define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \ |
193 | QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK) |
194 | |
195 | #define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \ |
196 | QAT_FIELD_GET(flags, QAT_COMN_CD_FLD_TYPE_BITPOS, \ |
197 | QAT_COMN_CD_FLD_TYPE_MASK) |
198 | |
199 | #define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \ |
200 | QAT_FIELD_SET(flags, val, QAT_COMN_PTR_TYPE_BITPOS, \ |
201 | QAT_COMN_PTR_TYPE_MASK) |
202 | |
203 | #define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \ |
204 | QAT_FIELD_SET(flags, val, QAT_COMN_CD_FLD_TYPE_BITPOS, \ |
205 | QAT_COMN_CD_FLD_TYPE_MASK) |
206 | |
207 | #define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4 |
208 | #define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0 |
209 | #define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0 |
210 | #define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F |
211 | |
212 | #define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \ |
213 | ((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \ |
214 | >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS)) |
215 | |
216 | #define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \ |
217 | { ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \ |
218 | & ICP_QAT_FW_COMN_CURR_ID_MASK) | \ |
219 | ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \ |
220 | & ICP_QAT_FW_COMN_NEXT_ID_MASK)); } |
221 | |
222 | #define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \ |
223 | (((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) |
224 | |
225 | #define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \ |
226 | { ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \ |
227 | & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \ |
228 | ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); } |
229 | |
230 | #define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7 |
231 | #define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1 |
232 | #define QAT_COMN_RESP_PKE_STATUS_BITPOS 6 |
233 | #define QAT_COMN_RESP_PKE_STATUS_MASK 0x1 |
234 | #define QAT_COMN_RESP_CMP_STATUS_BITPOS 5 |
235 | #define QAT_COMN_RESP_CMP_STATUS_MASK 0x1 |
236 | #define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4 |
237 | #define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1 |
238 | #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3 |
239 | #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1 |
240 | |
241 | #define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \ |
242 | ((((crypto) & QAT_COMN_RESP_CRYPTO_STATUS_MASK) << \ |
243 | QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \ |
244 | (((comp) & QAT_COMN_RESP_CMP_STATUS_MASK) << \ |
245 | QAT_COMN_RESP_CMP_STATUS_BITPOS) | \ |
246 | (((xlat) & QAT_COMN_RESP_XLAT_STATUS_MASK) << \ |
247 | QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \ |
248 | (((eolb) & QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) << \ |
249 | QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS)) |
250 | |
251 | #define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \ |
252 | QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \ |
253 | QAT_COMN_RESP_CRYPTO_STATUS_MASK) |
254 | |
255 | #define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \ |
256 | QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \ |
257 | QAT_COMN_RESP_CMP_STATUS_MASK) |
258 | |
259 | #define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \ |
260 | QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \ |
261 | QAT_COMN_RESP_XLAT_STATUS_MASK) |
262 | |
263 | #define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \ |
264 | QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \ |
265 | QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) |
266 | |
267 | #define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0 |
268 | #define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1 |
269 | #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0 |
270 | #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1 |
271 | #define ERR_CODE_NO_ERROR 0 |
272 | #define ERR_CODE_INVALID_BLOCK_TYPE -1 |
273 | #define ERR_CODE_NO_MATCH_ONES_COMP -2 |
274 | #define ERR_CODE_TOO_MANY_LEN_OR_DIS -3 |
275 | #define ERR_CODE_INCOMPLETE_LEN -4 |
276 | #define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5 |
277 | #define ERR_CODE_RPT_GT_SPEC_LEN -6 |
278 | #define ERR_CODE_INV_LIT_LEN_CODE_LEN -7 |
279 | #define ERR_CODE_INV_DIS_CODE_LEN -8 |
280 | #define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9 |
281 | #define ERR_CODE_DIS_TOO_FAR_BACK -10 |
282 | #define ERR_CODE_OVERFLOW_ERROR -11 |
283 | #define ERR_CODE_SOFT_ERROR -12 |
284 | #define ERR_CODE_FATAL_ERROR -13 |
285 | #define ERR_CODE_SSM_ERROR -14 |
286 | #define ERR_CODE_ENDPOINT_ERROR -15 |
287 | |
288 | enum icp_qat_fw_slice { |
289 | ICP_QAT_FW_SLICE_NULL = 0, |
290 | ICP_QAT_FW_SLICE_CIPHER = 1, |
291 | ICP_QAT_FW_SLICE_AUTH = 2, |
292 | ICP_QAT_FW_SLICE_DRAM_RD = 3, |
293 | ICP_QAT_FW_SLICE_DRAM_WR = 4, |
294 | ICP_QAT_FW_SLICE_COMP = 5, |
295 | ICP_QAT_FW_SLICE_XLAT = 6, |
296 | ICP_QAT_FW_SLICE_DELIMITER |
297 | }; |
298 | #endif |
299 | |