| 1 | /* SPDX-License-Identifier: GPL-2.0-only |
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| 2 | * Copyright (C) 2020 Marvell. |
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| 3 | */ |
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| 4 | |
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| 5 | #ifndef __OTX2_CPTVF_H |
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| 6 | #define __OTX2_CPTVF_H |
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| 7 | |
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| 8 | #include "mbox.h" |
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| 9 | #include "otx2_cptlf.h" |
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| 10 | |
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| 11 | struct otx2_cptvf_dev { |
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| 12 | void __iomem *reg_base; /* Register start address */ |
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| 13 | void __iomem *pfvf_mbox_base; /* PF-VF mbox start address */ |
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| 14 | struct pci_dev *pdev; /* PCI device handle */ |
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| 15 | struct otx2_cptlfs_info lfs; /* CPT LFs attached to this VF */ |
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| 16 | u8 vf_id; /* Virtual function index */ |
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| 17 | |
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| 18 | /* PF <=> VF mbox */ |
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| 19 | struct otx2_mbox pfvf_mbox; |
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| 20 | struct work_struct pfvf_mbox_work; |
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| 21 | struct workqueue_struct *pfvf_mbox_wq; |
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| 22 | int blkaddr; |
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| 23 | void *bbuf_base; |
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| 24 | unsigned long cap_flag; |
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| 25 | u64 eng_caps[OTX2_CPT_MAX_ENG_TYPES]; |
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| 26 | }; |
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| 27 | |
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| 28 | irqreturn_t otx2_cptvf_pfvf_mbox_intr(int irq, void *arg); |
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| 29 | void otx2_cptvf_pfvf_mbox_handler(struct work_struct *work); |
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| 30 | int otx2_cptvf_send_eng_grp_num_msg(struct otx2_cptvf_dev *cptvf, int eng_type); |
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| 31 | int otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_dev *cptvf); |
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| 32 | int otx2_cpt_mbox_bbuf_init(struct otx2_cptvf_dev *cptvf, struct pci_dev *pdev); |
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| 33 | int otx2_cptvf_send_caps_msg(struct otx2_cptvf_dev *cptvf); |
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| 34 | |
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| 35 | #endif /* __OTX2_CPTVF_H */ |
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| 36 | |
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