1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright(c) 2020 Intel Corporation. */
3
4#ifndef __CXL_CORE_H__
5#define __CXL_CORE_H__
6
7#include <cxl/mailbox.h>
8
9extern const struct device_type cxl_nvdimm_bridge_type;
10extern const struct device_type cxl_nvdimm_type;
11extern const struct device_type cxl_pmu_type;
12
13extern struct attribute_group cxl_base_attribute_group;
14
15#ifdef CONFIG_CXL_REGION
16extern struct device_attribute dev_attr_create_pmem_region;
17extern struct device_attribute dev_attr_create_ram_region;
18extern struct device_attribute dev_attr_delete_region;
19extern struct device_attribute dev_attr_region;
20extern const struct device_type cxl_pmem_region_type;
21extern const struct device_type cxl_dax_region_type;
22extern const struct device_type cxl_region_type;
23void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled);
24#define CXL_REGION_ATTR(x) (&dev_attr_##x.attr)
25#define CXL_REGION_TYPE(x) (&cxl_region_type)
26#define SET_CXL_REGION_ATTR(x) (&dev_attr_##x.attr),
27#define CXL_PMEM_REGION_TYPE(x) (&cxl_pmem_region_type)
28#define CXL_DAX_REGION_TYPE(x) (&cxl_dax_region_type)
29int cxl_region_init(void);
30void cxl_region_exit(void);
31int cxl_get_poison_by_endpoint(struct cxl_port *port);
32struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa);
33u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd,
34 u64 dpa);
35
36#else
37static inline u64 cxl_dpa_to_hpa(struct cxl_region *cxlr,
38 const struct cxl_memdev *cxlmd, u64 dpa)
39{
40 return ULLONG_MAX;
41}
42static inline
43struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa)
44{
45 return NULL;
46}
47static inline int cxl_get_poison_by_endpoint(struct cxl_port *port)
48{
49 return 0;
50}
51static inline void cxl_decoder_kill_region(struct cxl_endpoint_decoder *cxled)
52{
53}
54static inline int cxl_region_init(void)
55{
56 return 0;
57}
58static inline void cxl_region_exit(void)
59{
60}
61#define CXL_REGION_ATTR(x) NULL
62#define CXL_REGION_TYPE(x) NULL
63#define SET_CXL_REGION_ATTR(x)
64#define CXL_PMEM_REGION_TYPE(x) NULL
65#define CXL_DAX_REGION_TYPE(x) NULL
66#endif
67
68struct cxl_send_command;
69struct cxl_mem_query_commands;
70int cxl_query_cmd(struct cxl_mailbox *cxl_mbox,
71 struct cxl_mem_query_commands __user *q);
72int cxl_send_cmd(struct cxl_mailbox *cxl_mbox, struct cxl_send_command __user *s);
73void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
74 resource_size_t length);
75
76struct dentry *cxl_debugfs_create_dir(const char *dir);
77int cxl_dpa_set_part(struct cxl_endpoint_decoder *cxled,
78 enum cxl_partition_mode mode);
79int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, u64 size);
80int cxl_dpa_free(struct cxl_endpoint_decoder *cxled);
81resource_size_t cxl_dpa_size(struct cxl_endpoint_decoder *cxled);
82resource_size_t cxl_dpa_resource_start(struct cxl_endpoint_decoder *cxled);
83
84enum cxl_rcrb {
85 CXL_RCRB_DOWNSTREAM,
86 CXL_RCRB_UPSTREAM,
87};
88struct cxl_rcrb_info;
89resource_size_t __rcrb_to_component(struct device *dev,
90 struct cxl_rcrb_info *ri,
91 enum cxl_rcrb which);
92u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb);
93
94#define PCI_RCRB_CAP_LIST_ID_MASK GENMASK(7, 0)
95#define PCI_RCRB_CAP_HDR_ID_MASK GENMASK(7, 0)
96#define PCI_RCRB_CAP_HDR_NEXT_MASK GENMASK(15, 8)
97#define PCI_CAP_EXP_SIZEOF 0x3c
98
99extern struct rw_semaphore cxl_dpa_rwsem;
100extern struct rw_semaphore cxl_region_rwsem;
101
102int cxl_memdev_init(void);
103void cxl_memdev_exit(void);
104void cxl_mbox_init(void);
105
106enum cxl_poison_trace_type {
107 CXL_POISON_TRACE_LIST,
108 CXL_POISON_TRACE_INJECT,
109 CXL_POISON_TRACE_CLEAR,
110};
111
112long cxl_pci_get_latency(struct pci_dev *pdev);
113int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c);
114int cxl_update_hmat_access_coordinates(int nid, struct cxl_region *cxlr,
115 enum access_coordinate_class access);
116bool cxl_need_node_perf_attrs_update(int nid);
117int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port,
118 struct access_coordinate *c);
119
120int cxl_ras_init(void);
121void cxl_ras_exit(void);
122int cxl_gpf_port_setup(struct cxl_dport *dport);
123int cxl_acpi_get_extended_linear_cache_size(struct resource *backing_res,
124 int nid, resource_size_t *size);
125
126#ifdef CONFIG_CXL_FEATURES
127struct cxl_feat_entry *
128cxl_feature_info(struct cxl_features_state *cxlfs, const uuid_t *uuid);
129size_t cxl_get_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid,
130 enum cxl_get_feat_selection selection,
131 void *feat_out, size_t feat_out_size, u16 offset,
132 u16 *return_code);
133int cxl_set_feature(struct cxl_mailbox *cxl_mbox, const uuid_t *feat_uuid,
134 u8 feat_version, const void *feat_data,
135 size_t feat_data_size, u32 feat_flag, u16 offset,
136 u16 *return_code);
137#endif
138
139#endif /* __CXL_CORE_H__ */
140

source code of linux/drivers/cxl/core/core.h