1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.
3 */
4#ifndef __QCOM_SCM_INT_H
5#define __QCOM_SCM_INT_H
6
7struct device;
8
9enum qcom_scm_convention {
10 SMC_CONVENTION_UNKNOWN,
11 SMC_CONVENTION_LEGACY,
12 SMC_CONVENTION_ARM_32,
13 SMC_CONVENTION_ARM_64,
14};
15
16extern enum qcom_scm_convention qcom_scm_convention;
17
18#define MAX_QCOM_SCM_ARGS 10
19#define MAX_QCOM_SCM_RETS 3
20
21enum qcom_scm_arg_types {
22 QCOM_SCM_VAL,
23 QCOM_SCM_RO,
24 QCOM_SCM_RW,
25 QCOM_SCM_BUFVAL,
26};
27
28#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
29 (((a) & 0x3) << 4) | \
30 (((b) & 0x3) << 6) | \
31 (((c) & 0x3) << 8) | \
32 (((d) & 0x3) << 10) | \
33 (((e) & 0x3) << 12) | \
34 (((f) & 0x3) << 14) | \
35 (((g) & 0x3) << 16) | \
36 (((h) & 0x3) << 18) | \
37 (((i) & 0x3) << 20) | \
38 (((j) & 0x3) << 22) | \
39 ((num) & 0xf))
40
41#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
42
43
44/**
45 * struct qcom_scm_desc
46 * @arginfo: Metadata describing the arguments in args[]
47 * @args: The array of arguments for the secure syscall
48 */
49struct qcom_scm_desc {
50 u32 svc;
51 u32 cmd;
52 u32 arginfo;
53 u64 args[MAX_QCOM_SCM_ARGS];
54 u32 owner;
55};
56
57/**
58 * struct qcom_scm_res
59 * @result: The values returned by the secure syscall
60 */
61struct qcom_scm_res {
62 u64 result[MAX_QCOM_SCM_RETS];
63};
64
65int qcom_scm_wait_for_wq_completion(u32 wq_ctx);
66int scm_get_wq_ctx(u32 *wq_ctx, u32 *flags, u32 *more_pending);
67
68#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))
69int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
70 enum qcom_scm_convention qcom_convention,
71 struct qcom_scm_res *res, bool atomic);
72#define scm_smc_call(dev, desc, res, atomic) \
73 __scm_smc_call((dev), (desc), qcom_scm_convention, (res), (atomic))
74
75#define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))
76int scm_legacy_call_atomic(struct device *dev, const struct qcom_scm_desc *desc,
77 struct qcom_scm_res *res);
78int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
79 struct qcom_scm_res *res);
80
81#define QCOM_SCM_SVC_BOOT 0x01
82#define QCOM_SCM_BOOT_SET_ADDR 0x01
83#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
84#define QCOM_SCM_BOOT_SDI_CONFIG 0x09
85#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
86#define QCOM_SCM_BOOT_SET_ADDR_MC 0x11
87#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
88#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
89#define QCOM_SCM_BOOT_MAX_CPUS 4
90#define QCOM_SCM_BOOT_MC_FLAG_AARCH64 BIT(0)
91#define QCOM_SCM_BOOT_MC_FLAG_COLDBOOT BIT(1)
92#define QCOM_SCM_BOOT_MC_FLAG_WARMBOOT BIT(2)
93
94#define QCOM_SCM_SVC_PIL 0x02
95#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
96#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
97#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
98#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
99#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
100#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
101
102#define QCOM_SCM_SVC_IO 0x05
103#define QCOM_SCM_IO_READ 0x01
104#define QCOM_SCM_IO_WRITE 0x02
105
106#define QCOM_SCM_SVC_INFO 0x06
107#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
108
109#define QCOM_SCM_SVC_MP 0x0c
110#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
111#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
112#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
113#define QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE 0x05
114#define QCOM_SCM_MP_VIDEO_VAR 0x08
115#define QCOM_SCM_MP_ASSIGN 0x16
116
117#define QCOM_SCM_SVC_OCMEM 0x0f
118#define QCOM_SCM_OCMEM_LOCK_CMD 0x01
119#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02
120
121#define QCOM_SCM_SVC_ES 0x10 /* Enterprise Security */
122#define QCOM_SCM_ES_INVALIDATE_ICE_KEY 0x03
123#define QCOM_SCM_ES_CONFIG_SET_ICE_KEY 0x04
124
125#define QCOM_SCM_SVC_HDCP 0x11
126#define QCOM_SCM_HDCP_INVOKE 0x01
127
128#define QCOM_SCM_SVC_LMH 0x13
129#define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE 0x01
130#define QCOM_SCM_LMH_LIMIT_DCVSH 0x10
131
132#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
133#define QCOM_SCM_SMMU_PT_FORMAT 0x01
134#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
135#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
136
137#define QCOM_SCM_SVC_WAITQ 0x24
138#define QCOM_SCM_WAITQ_RESUME 0x02
139#define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03
140
141/* common error codes */
142#define QCOM_SCM_V2_EBUSY -12
143#define QCOM_SCM_ENOMEM -5
144#define QCOM_SCM_EOPNOTSUPP -4
145#define QCOM_SCM_EINVAL_ADDR -3
146#define QCOM_SCM_EINVAL_ARG -2
147#define QCOM_SCM_ERROR -1
148#define QCOM_SCM_INTERRUPTED 1
149#define QCOM_SCM_WAITQ_SLEEP 2
150
151static inline int qcom_scm_remap_error(int err)
152{
153 switch (err) {
154 case QCOM_SCM_ERROR:
155 return -EIO;
156 case QCOM_SCM_EINVAL_ADDR:
157 case QCOM_SCM_EINVAL_ARG:
158 return -EINVAL;
159 case QCOM_SCM_EOPNOTSUPP:
160 return -EOPNOTSUPP;
161 case QCOM_SCM_ENOMEM:
162 return -ENOMEM;
163 case QCOM_SCM_V2_EBUSY:
164 return -EBUSY;
165 }
166 return -EINVAL;
167}
168
169#endif
170

source code of linux/drivers/firmware/qcom/qcom_scm.h