1 | /* |
2 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | * |
21 | */ |
22 | |
23 | #ifndef __ICELAND_SDMA_PKT_OPEN_H_ |
24 | #define __ICELAND_SDMA_PKT_OPEN_H_ |
25 | |
26 | #define SDMA_OP_NOP 0 |
27 | #define SDMA_OP_COPY 1 |
28 | #define SDMA_OP_WRITE 2 |
29 | #define SDMA_OP_INDIRECT 4 |
30 | #define SDMA_OP_FENCE 5 |
31 | #define SDMA_OP_TRAP 6 |
32 | #define SDMA_OP_SEM 7 |
33 | #define SDMA_OP_POLL_REGMEM 8 |
34 | #define SDMA_OP_COND_EXE 9 |
35 | #define SDMA_OP_ATOMIC 10 |
36 | #define SDMA_OP_CONST_FILL 11 |
37 | #define SDMA_OP_GEN_PTEPDE 12 |
38 | #define SDMA_OP_TIMESTAMP 13 |
39 | #define SDMA_OP_SRBM_WRITE 14 |
40 | #define SDMA_OP_PRE_EXE 15 |
41 | #define SDMA_SUBOP_TIMESTAMP_SET 0 |
42 | #define SDMA_SUBOP_TIMESTAMP_GET 1 |
43 | #define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 |
44 | #define SDMA_SUBOP_COPY_LINEAR 0 |
45 | #define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 |
46 | #define SDMA_SUBOP_COPY_TILED 1 |
47 | #define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 |
48 | #define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 |
49 | #define SDMA_SUBOP_COPY_SOA 3 |
50 | #define SDMA_SUBOP_WRITE_LINEAR 0 |
51 | #define SDMA_SUBOP_WRITE_TILED 1 |
52 | |
53 | /*define for op field*/ |
54 | #define 0 |
55 | #define 0x000000FF |
56 | #define 0 |
57 | #define (x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) |
58 | |
59 | /*define for sub_op field*/ |
60 | #define 0 |
61 | #define 0x000000FF |
62 | #define 8 |
63 | #define (x) (((x) & SDMA_PKT_HEADER_sub_op_mask) << SDMA_PKT_HEADER_sub_op_shift) |
64 | |
65 | /* |
66 | ** Definitions for SDMA_PKT_COPY_LINEAR packet |
67 | */ |
68 | |
69 | /*define for HEADER word*/ |
70 | /*define for op field*/ |
71 | #define 0 |
72 | #define 0x000000FF |
73 | #define 0 |
74 | #define (x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) |
75 | |
76 | /*define for sub_op field*/ |
77 | #define 0 |
78 | #define 0x000000FF |
79 | #define 8 |
80 | #define (x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) |
81 | |
82 | /*define for broadcast field*/ |
83 | #define 0 |
84 | #define 0x00000001 |
85 | #define 27 |
86 | #define (x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) |
87 | |
88 | /*define for COUNT word*/ |
89 | /*define for count field*/ |
90 | #define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 |
91 | #define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF |
92 | #define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 |
93 | #define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) |
94 | |
95 | /*define for PARAMETER word*/ |
96 | /*define for dst_sw field*/ |
97 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 |
98 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 |
99 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 |
100 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) |
101 | |
102 | /*define for dst_ha field*/ |
103 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_offset 2 |
104 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask 0x00000001 |
105 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_shift 22 |
106 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_ha_shift) |
107 | |
108 | /*define for src_sw field*/ |
109 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 |
110 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 |
111 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 |
112 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) |
113 | |
114 | /*define for src_ha field*/ |
115 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_offset 2 |
116 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask 0x00000001 |
117 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_shift 30 |
118 | #define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_ha_shift) |
119 | |
120 | /*define for SRC_ADDR_LO word*/ |
121 | /*define for src_addr_31_0 field*/ |
122 | #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 |
123 | #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF |
124 | #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 |
125 | #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) |
126 | |
127 | /*define for SRC_ADDR_HI word*/ |
128 | /*define for src_addr_63_32 field*/ |
129 | #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 |
130 | #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF |
131 | #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 |
132 | #define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) |
133 | |
134 | /*define for DST_ADDR_LO word*/ |
135 | /*define for dst_addr_31_0 field*/ |
136 | #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 |
137 | #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF |
138 | #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 |
139 | #define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) |
140 | |
141 | /*define for DST_ADDR_HI word*/ |
142 | /*define for dst_addr_63_32 field*/ |
143 | #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 |
144 | #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF |
145 | #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 |
146 | #define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) |
147 | |
148 | |
149 | /* |
150 | ** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet |
151 | */ |
152 | |
153 | /*define for HEADER word*/ |
154 | /*define for op field*/ |
155 | #define 0 |
156 | #define 0x000000FF |
157 | #define 0 |
158 | #define (x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) |
159 | |
160 | /*define for sub_op field*/ |
161 | #define 0 |
162 | #define 0x000000FF |
163 | #define 8 |
164 | #define (x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) |
165 | |
166 | /*define for broadcast field*/ |
167 | #define 0 |
168 | #define 0x00000001 |
169 | #define 27 |
170 | #define (x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) |
171 | |
172 | /*define for COUNT word*/ |
173 | /*define for count field*/ |
174 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 |
175 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x003FFFFF |
176 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 |
177 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) |
178 | |
179 | /*define for PARAMETER word*/ |
180 | /*define for dst2_sw field*/ |
181 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 |
182 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 |
183 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 |
184 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) |
185 | |
186 | /*define for dst2_ha field*/ |
187 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_offset 2 |
188 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask 0x00000001 |
189 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_shift 14 |
190 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_ha_shift) |
191 | |
192 | /*define for dst1_sw field*/ |
193 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 |
194 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 |
195 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 |
196 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) |
197 | |
198 | /*define for dst1_ha field*/ |
199 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_offset 2 |
200 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask 0x00000001 |
201 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_shift 22 |
202 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_ha_shift) |
203 | |
204 | /*define for src_sw field*/ |
205 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 |
206 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 |
207 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 |
208 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) |
209 | |
210 | /*define for src_ha field*/ |
211 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_offset 2 |
212 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask 0x00000001 |
213 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_shift 30 |
214 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_ha_shift) |
215 | |
216 | /*define for SRC_ADDR_LO word*/ |
217 | /*define for src_addr_31_0 field*/ |
218 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 |
219 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF |
220 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 |
221 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) |
222 | |
223 | /*define for SRC_ADDR_HI word*/ |
224 | /*define for src_addr_63_32 field*/ |
225 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 |
226 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF |
227 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 |
228 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) |
229 | |
230 | /*define for DST1_ADDR_LO word*/ |
231 | /*define for dst1_addr_31_0 field*/ |
232 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 |
233 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF |
234 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 |
235 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) |
236 | |
237 | /*define for DST1_ADDR_HI word*/ |
238 | /*define for dst1_addr_63_32 field*/ |
239 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 |
240 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF |
241 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 |
242 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) |
243 | |
244 | /*define for DST2_ADDR_LO word*/ |
245 | /*define for dst2_addr_31_0 field*/ |
246 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 |
247 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF |
248 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 |
249 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) |
250 | |
251 | /*define for DST2_ADDR_HI word*/ |
252 | /*define for dst2_addr_63_32 field*/ |
253 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 |
254 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF |
255 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 |
256 | #define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) |
257 | |
258 | |
259 | /* |
260 | ** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet |
261 | */ |
262 | |
263 | /*define for HEADER word*/ |
264 | /*define for op field*/ |
265 | #define 0 |
266 | #define 0x000000FF |
267 | #define 0 |
268 | #define (x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) |
269 | |
270 | /*define for sub_op field*/ |
271 | #define 0 |
272 | #define 0x000000FF |
273 | #define 8 |
274 | #define (x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) |
275 | |
276 | /*define for elementsize field*/ |
277 | #define 0 |
278 | #define 0x00000007 |
279 | #define 29 |
280 | #define (x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) |
281 | |
282 | /*define for SRC_ADDR_LO word*/ |
283 | /*define for src_addr_31_0 field*/ |
284 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 |
285 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF |
286 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 |
287 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) |
288 | |
289 | /*define for SRC_ADDR_HI word*/ |
290 | /*define for src_addr_63_32 field*/ |
291 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 |
292 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF |
293 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 |
294 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) |
295 | |
296 | /*define for DW_3 word*/ |
297 | /*define for src_x field*/ |
298 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 |
299 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF |
300 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 |
301 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) |
302 | |
303 | /*define for src_y field*/ |
304 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 |
305 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF |
306 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 |
307 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) |
308 | |
309 | /*define for DW_4 word*/ |
310 | /*define for src_z field*/ |
311 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 |
312 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x000007FF |
313 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 |
314 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) |
315 | |
316 | /*define for src_pitch field*/ |
317 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 |
318 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x00003FFF |
319 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 16 |
320 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) |
321 | |
322 | /*define for DW_5 word*/ |
323 | /*define for src_slice_pitch field*/ |
324 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 |
325 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF |
326 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 |
327 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) |
328 | |
329 | /*define for DST_ADDR_LO word*/ |
330 | /*define for dst_addr_31_0 field*/ |
331 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 |
332 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF |
333 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 |
334 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) |
335 | |
336 | /*define for DST_ADDR_HI word*/ |
337 | /*define for dst_addr_63_32 field*/ |
338 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 |
339 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF |
340 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 |
341 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) |
342 | |
343 | /*define for DW_8 word*/ |
344 | /*define for dst_x field*/ |
345 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 |
346 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF |
347 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 |
348 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) |
349 | |
350 | /*define for dst_y field*/ |
351 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 |
352 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF |
353 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 |
354 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) |
355 | |
356 | /*define for DW_9 word*/ |
357 | /*define for dst_z field*/ |
358 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 |
359 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x000007FF |
360 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 |
361 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) |
362 | |
363 | /*define for dst_pitch field*/ |
364 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 |
365 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x00003FFF |
366 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 16 |
367 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) |
368 | |
369 | /*define for DW_10 word*/ |
370 | /*define for dst_slice_pitch field*/ |
371 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 |
372 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF |
373 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 |
374 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) |
375 | |
376 | /*define for DW_11 word*/ |
377 | /*define for rect_x field*/ |
378 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 |
379 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF |
380 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 |
381 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) |
382 | |
383 | /*define for rect_y field*/ |
384 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 |
385 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF |
386 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 |
387 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) |
388 | |
389 | /*define for DW_12 word*/ |
390 | /*define for rect_z field*/ |
391 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 |
392 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x000007FF |
393 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 |
394 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) |
395 | |
396 | /*define for dst_sw field*/ |
397 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 |
398 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 |
399 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 |
400 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) |
401 | |
402 | /*define for dst_ha field*/ |
403 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_offset 12 |
404 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask 0x00000001 |
405 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_shift 22 |
406 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_ha_shift) |
407 | |
408 | /*define for src_sw field*/ |
409 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 |
410 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 |
411 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 |
412 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) |
413 | |
414 | /*define for src_ha field*/ |
415 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_offset 12 |
416 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask 0x00000001 |
417 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_shift 30 |
418 | #define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_ha_shift) |
419 | |
420 | |
421 | /* |
422 | ** Definitions for SDMA_PKT_COPY_TILED packet |
423 | */ |
424 | |
425 | /*define for HEADER word*/ |
426 | /*define for op field*/ |
427 | #define 0 |
428 | #define 0x000000FF |
429 | #define 0 |
430 | #define (x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) |
431 | |
432 | /*define for sub_op field*/ |
433 | #define 0 |
434 | #define 0x000000FF |
435 | #define 8 |
436 | #define (x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) |
437 | |
438 | /*define for detile field*/ |
439 | #define 0 |
440 | #define 0x00000001 |
441 | #define 31 |
442 | #define (x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) |
443 | |
444 | /*define for TILED_ADDR_LO word*/ |
445 | /*define for tiled_addr_31_0 field*/ |
446 | #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 |
447 | #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF |
448 | #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 |
449 | #define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) |
450 | |
451 | /*define for TILED_ADDR_HI word*/ |
452 | /*define for tiled_addr_63_32 field*/ |
453 | #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 |
454 | #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF |
455 | #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 |
456 | #define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) |
457 | |
458 | /*define for DW_3 word*/ |
459 | /*define for pitch_in_tile field*/ |
460 | #define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_offset 3 |
461 | #define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask 0x000007FF |
462 | #define SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift 0 |
463 | #define SDMA_PKT_COPY_TILED_DW_3_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_mask) << SDMA_PKT_COPY_TILED_DW_3_pitch_in_tile_shift) |
464 | |
465 | /*define for height field*/ |
466 | #define SDMA_PKT_COPY_TILED_DW_3_height_offset 3 |
467 | #define SDMA_PKT_COPY_TILED_DW_3_height_mask 0x00003FFF |
468 | #define SDMA_PKT_COPY_TILED_DW_3_height_shift 16 |
469 | #define SDMA_PKT_COPY_TILED_DW_3_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_height_mask) << SDMA_PKT_COPY_TILED_DW_3_height_shift) |
470 | |
471 | /*define for DW_4 word*/ |
472 | /*define for slice_pitch field*/ |
473 | #define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_offset 4 |
474 | #define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask 0x003FFFFF |
475 | #define SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift 0 |
476 | #define SDMA_PKT_COPY_TILED_DW_4_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_slice_pitch_mask) << SDMA_PKT_COPY_TILED_DW_4_slice_pitch_shift) |
477 | |
478 | /*define for DW_5 word*/ |
479 | /*define for element_size field*/ |
480 | #define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 |
481 | #define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 |
482 | #define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 |
483 | #define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) |
484 | |
485 | /*define for array_mode field*/ |
486 | #define SDMA_PKT_COPY_TILED_DW_5_array_mode_offset 5 |
487 | #define SDMA_PKT_COPY_TILED_DW_5_array_mode_mask 0x0000000F |
488 | #define SDMA_PKT_COPY_TILED_DW_5_array_mode_shift 3 |
489 | #define SDMA_PKT_COPY_TILED_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_array_mode_shift) |
490 | |
491 | /*define for mit_mode field*/ |
492 | #define SDMA_PKT_COPY_TILED_DW_5_mit_mode_offset 5 |
493 | #define SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask 0x00000007 |
494 | #define SDMA_PKT_COPY_TILED_DW_5_mit_mode_shift 8 |
495 | #define SDMA_PKT_COPY_TILED_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_mit_mode_shift) |
496 | |
497 | /*define for tilesplit_size field*/ |
498 | #define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_offset 5 |
499 | #define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask 0x00000007 |
500 | #define SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_shift 11 |
501 | #define SDMA_PKT_COPY_TILED_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_DW_5_tilesplit_size_shift) |
502 | |
503 | /*define for bank_w field*/ |
504 | #define SDMA_PKT_COPY_TILED_DW_5_bank_w_offset 5 |
505 | #define SDMA_PKT_COPY_TILED_DW_5_bank_w_mask 0x00000003 |
506 | #define SDMA_PKT_COPY_TILED_DW_5_bank_w_shift 15 |
507 | #define SDMA_PKT_COPY_TILED_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_DW_5_bank_w_shift) |
508 | |
509 | /*define for bank_h field*/ |
510 | #define SDMA_PKT_COPY_TILED_DW_5_bank_h_offset 5 |
511 | #define SDMA_PKT_COPY_TILED_DW_5_bank_h_mask 0x00000003 |
512 | #define SDMA_PKT_COPY_TILED_DW_5_bank_h_shift 18 |
513 | #define SDMA_PKT_COPY_TILED_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_DW_5_bank_h_shift) |
514 | |
515 | /*define for num_bank field*/ |
516 | #define SDMA_PKT_COPY_TILED_DW_5_num_bank_offset 5 |
517 | #define SDMA_PKT_COPY_TILED_DW_5_num_bank_mask 0x00000003 |
518 | #define SDMA_PKT_COPY_TILED_DW_5_num_bank_shift 21 |
519 | #define SDMA_PKT_COPY_TILED_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_DW_5_num_bank_shift) |
520 | |
521 | /*define for mat_aspt field*/ |
522 | #define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_offset 5 |
523 | #define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask 0x00000003 |
524 | #define SDMA_PKT_COPY_TILED_DW_5_mat_aspt_shift 24 |
525 | #define SDMA_PKT_COPY_TILED_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_DW_5_mat_aspt_shift) |
526 | |
527 | /*define for pipe_config field*/ |
528 | #define SDMA_PKT_COPY_TILED_DW_5_pipe_config_offset 5 |
529 | #define SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask 0x0000001F |
530 | #define SDMA_PKT_COPY_TILED_DW_5_pipe_config_shift 26 |
531 | #define SDMA_PKT_COPY_TILED_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_DW_5_pipe_config_shift) |
532 | |
533 | /*define for DW_6 word*/ |
534 | /*define for x field*/ |
535 | #define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 |
536 | #define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF |
537 | #define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 |
538 | #define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) |
539 | |
540 | /*define for y field*/ |
541 | #define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 |
542 | #define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF |
543 | #define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 |
544 | #define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) |
545 | |
546 | /*define for DW_7 word*/ |
547 | /*define for z field*/ |
548 | #define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 |
549 | #define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00000FFF |
550 | #define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 |
551 | #define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) |
552 | |
553 | /*define for linear_sw field*/ |
554 | #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 |
555 | #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 |
556 | #define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 |
557 | #define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) |
558 | |
559 | /*define for tile_sw field*/ |
560 | #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 |
561 | #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 |
562 | #define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 |
563 | #define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) |
564 | |
565 | /*define for LINEAR_ADDR_LO word*/ |
566 | /*define for linear_addr_31_0 field*/ |
567 | #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 |
568 | #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF |
569 | #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 |
570 | #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) |
571 | |
572 | /*define for LINEAR_ADDR_HI word*/ |
573 | /*define for linear_addr_63_32 field*/ |
574 | #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 |
575 | #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF |
576 | #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 |
577 | #define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) |
578 | |
579 | /*define for LINEAR_PITCH word*/ |
580 | /*define for linear_pitch field*/ |
581 | #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 |
582 | #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF |
583 | #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 |
584 | #define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) |
585 | |
586 | /*define for COUNT word*/ |
587 | /*define for count field*/ |
588 | #define SDMA_PKT_COPY_TILED_COUNT_count_offset 11 |
589 | #define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x000FFFFF |
590 | #define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 |
591 | #define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) |
592 | |
593 | |
594 | /* |
595 | ** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet |
596 | */ |
597 | |
598 | /*define for HEADER word*/ |
599 | /*define for op field*/ |
600 | #define 0 |
601 | #define 0x000000FF |
602 | #define 0 |
603 | #define (x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) |
604 | |
605 | /*define for sub_op field*/ |
606 | #define 0 |
607 | #define 0x000000FF |
608 | #define 8 |
609 | #define (x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) |
610 | |
611 | /*define for videocopy field*/ |
612 | #define 0 |
613 | #define 0x00000001 |
614 | #define 26 |
615 | #define (x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) |
616 | |
617 | /*define for broadcast field*/ |
618 | #define 0 |
619 | #define 0x00000001 |
620 | #define 27 |
621 | #define (x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) |
622 | |
623 | /*define for TILED_ADDR_LO_0 word*/ |
624 | /*define for tiled_addr0_31_0 field*/ |
625 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 |
626 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF |
627 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 |
628 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) |
629 | |
630 | /*define for TILED_ADDR_HI_0 word*/ |
631 | /*define for tiled_addr0_63_32 field*/ |
632 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 |
633 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF |
634 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 |
635 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) |
636 | |
637 | /*define for TILED_ADDR_LO_1 word*/ |
638 | /*define for tiled_addr1_31_0 field*/ |
639 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 |
640 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF |
641 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 |
642 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) |
643 | |
644 | /*define for TILED_ADDR_HI_1 word*/ |
645 | /*define for tiled_addr1_63_32 field*/ |
646 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 |
647 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF |
648 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 |
649 | #define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) |
650 | |
651 | /*define for DW_5 word*/ |
652 | /*define for pitch_in_tile field*/ |
653 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_offset 5 |
654 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask 0x000007FF |
655 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift 0 |
656 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_pitch_in_tile_shift) |
657 | |
658 | /*define for height field*/ |
659 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_offset 5 |
660 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask 0x00003FFF |
661 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_shift 16 |
662 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_height_shift) |
663 | |
664 | /*define for DW_6 word*/ |
665 | /*define for slice_pitch field*/ |
666 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_offset 6 |
667 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask 0x003FFFFF |
668 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift 0 |
669 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_slice_pitch_shift) |
670 | |
671 | /*define for DW_7 word*/ |
672 | /*define for element_size field*/ |
673 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 |
674 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 |
675 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 |
676 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) |
677 | |
678 | /*define for array_mode field*/ |
679 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_offset 7 |
680 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask 0x0000000F |
681 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_shift 3 |
682 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_array_mode_shift) |
683 | |
684 | /*define for mit_mode field*/ |
685 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_offset 7 |
686 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask 0x00000007 |
687 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_shift 8 |
688 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIT_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mit_mode_shift) |
689 | |
690 | /*define for tilesplit_size field*/ |
691 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_offset 7 |
692 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask 0x00000007 |
693 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_shift 11 |
694 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_tilesplit_size_shift) |
695 | |
696 | /*define for bank_w field*/ |
697 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_offset 7 |
698 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask 0x00000003 |
699 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_shift 15 |
700 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_BANK_W(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_w_shift) |
701 | |
702 | /*define for bank_h field*/ |
703 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_offset 7 |
704 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask 0x00000003 |
705 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_shift 18 |
706 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_BANK_H(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_bank_h_shift) |
707 | |
708 | /*define for num_bank field*/ |
709 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_offset 7 |
710 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask 0x00000003 |
711 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_shift 21 |
712 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_NUM_BANK(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_num_bank_shift) |
713 | |
714 | /*define for mat_aspt field*/ |
715 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_offset 7 |
716 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask 0x00000003 |
717 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_shift 24 |
718 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mat_aspt_shift) |
719 | |
720 | /*define for pipe_config field*/ |
721 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_offset 7 |
722 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask 0x0000001F |
723 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_shift 26 |
724 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_pipe_config_shift) |
725 | |
726 | /*define for DW_8 word*/ |
727 | /*define for x field*/ |
728 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 |
729 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF |
730 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 |
731 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) |
732 | |
733 | /*define for y field*/ |
734 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 |
735 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF |
736 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 |
737 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) |
738 | |
739 | /*define for DW_9 word*/ |
740 | /*define for z field*/ |
741 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 |
742 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00000FFF |
743 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 |
744 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) |
745 | |
746 | /*define for DW_10 word*/ |
747 | /*define for dst2_sw field*/ |
748 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 |
749 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 |
750 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 |
751 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) |
752 | |
753 | /*define for dst2_ha field*/ |
754 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_offset 10 |
755 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask 0x00000001 |
756 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_shift 14 |
757 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_HA(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_ha_shift) |
758 | |
759 | /*define for linear_sw field*/ |
760 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 |
761 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 |
762 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 |
763 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) |
764 | |
765 | /*define for tile_sw field*/ |
766 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 |
767 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 |
768 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 |
769 | #define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) |
770 | |
771 | /*define for LINEAR_ADDR_LO word*/ |
772 | /*define for linear_addr_31_0 field*/ |
773 | #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 |
774 | #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF |
775 | #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 |
776 | #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) |
777 | |
778 | /*define for LINEAR_ADDR_HI word*/ |
779 | /*define for linear_addr_63_32 field*/ |
780 | #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 |
781 | #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF |
782 | #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 |
783 | #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) |
784 | |
785 | /*define for LINEAR_PITCH word*/ |
786 | /*define for linear_pitch field*/ |
787 | #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 |
788 | #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF |
789 | #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 |
790 | #define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) |
791 | |
792 | /*define for COUNT word*/ |
793 | /*define for count field*/ |
794 | #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 14 |
795 | #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x000FFFFF |
796 | #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 |
797 | #define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) |
798 | |
799 | |
800 | /* |
801 | ** Definitions for SDMA_PKT_COPY_T2T packet |
802 | */ |
803 | |
804 | /*define for HEADER word*/ |
805 | /*define for op field*/ |
806 | #define 0 |
807 | #define 0x000000FF |
808 | #define 0 |
809 | #define (x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) |
810 | |
811 | /*define for sub_op field*/ |
812 | #define 0 |
813 | #define 0x000000FF |
814 | #define 8 |
815 | #define (x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) |
816 | |
817 | /*define for SRC_ADDR_LO word*/ |
818 | /*define for src_addr_31_0 field*/ |
819 | #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 |
820 | #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF |
821 | #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 |
822 | #define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) |
823 | |
824 | /*define for SRC_ADDR_HI word*/ |
825 | /*define for src_addr_63_32 field*/ |
826 | #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 |
827 | #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF |
828 | #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 |
829 | #define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) |
830 | |
831 | /*define for DW_3 word*/ |
832 | /*define for src_x field*/ |
833 | #define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 |
834 | #define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF |
835 | #define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 |
836 | #define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) |
837 | |
838 | /*define for src_y field*/ |
839 | #define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 |
840 | #define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF |
841 | #define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 |
842 | #define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) |
843 | |
844 | /*define for DW_4 word*/ |
845 | /*define for src_z field*/ |
846 | #define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 |
847 | #define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x000007FF |
848 | #define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 |
849 | #define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) |
850 | |
851 | /*define for src_pitch_in_tile field*/ |
852 | #define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_offset 4 |
853 | #define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask 0x00000FFF |
854 | #define SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_shift 16 |
855 | #define SDMA_PKT_COPY_T2T_DW_4_SRC_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_mask) << SDMA_PKT_COPY_T2T_DW_4_src_pitch_in_tile_shift) |
856 | |
857 | /*define for DW_5 word*/ |
858 | /*define for src_slice_pitch field*/ |
859 | #define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_offset 5 |
860 | #define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask 0x003FFFFF |
861 | #define SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift 0 |
862 | #define SDMA_PKT_COPY_T2T_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_T2T_DW_5_src_slice_pitch_shift) |
863 | |
864 | /*define for DW_6 word*/ |
865 | /*define for src_element_size field*/ |
866 | #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 |
867 | #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 |
868 | #define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 |
869 | #define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) |
870 | |
871 | /*define for src_array_mode field*/ |
872 | #define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_offset 6 |
873 | #define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask 0x0000000F |
874 | #define SDMA_PKT_COPY_T2T_DW_6_src_array_mode_shift 3 |
875 | #define SDMA_PKT_COPY_T2T_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_array_mode_shift) |
876 | |
877 | /*define for src_mit_mode field*/ |
878 | #define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_offset 6 |
879 | #define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask 0x00000007 |
880 | #define SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_shift 8 |
881 | #define SDMA_PKT_COPY_T2T_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mit_mode_shift) |
882 | |
883 | /*define for src_tilesplit_size field*/ |
884 | #define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_offset 6 |
885 | #define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask 0x00000007 |
886 | #define SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_shift 11 |
887 | #define SDMA_PKT_COPY_T2T_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_tilesplit_size_shift) |
888 | |
889 | /*define for src_bank_w field*/ |
890 | #define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_offset 6 |
891 | #define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask 0x00000003 |
892 | #define SDMA_PKT_COPY_T2T_DW_6_src_bank_w_shift 15 |
893 | #define SDMA_PKT_COPY_T2T_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_DW_6_src_bank_w_shift) |
894 | |
895 | /*define for src_bank_h field*/ |
896 | #define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_offset 6 |
897 | #define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask 0x00000003 |
898 | #define SDMA_PKT_COPY_T2T_DW_6_src_bank_h_shift 18 |
899 | #define SDMA_PKT_COPY_T2T_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_DW_6_src_bank_h_shift) |
900 | |
901 | /*define for src_num_bank field*/ |
902 | #define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_offset 6 |
903 | #define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask 0x00000003 |
904 | #define SDMA_PKT_COPY_T2T_DW_6_src_num_bank_shift 21 |
905 | #define SDMA_PKT_COPY_T2T_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_DW_6_src_num_bank_shift) |
906 | |
907 | /*define for src_mat_aspt field*/ |
908 | #define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_offset 6 |
909 | #define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask 0x00000003 |
910 | #define SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_shift 24 |
911 | #define SDMA_PKT_COPY_T2T_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mat_aspt_shift) |
912 | |
913 | /*define for src_pipe_config field*/ |
914 | #define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_offset 6 |
915 | #define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask 0x0000001F |
916 | #define SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_shift 26 |
917 | #define SDMA_PKT_COPY_T2T_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_DW_6_src_pipe_config_shift) |
918 | |
919 | /*define for DST_ADDR_LO word*/ |
920 | /*define for dst_addr_31_0 field*/ |
921 | #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 |
922 | #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF |
923 | #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 |
924 | #define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) |
925 | |
926 | /*define for DST_ADDR_HI word*/ |
927 | /*define for dst_addr_63_32 field*/ |
928 | #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 |
929 | #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF |
930 | #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 |
931 | #define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) |
932 | |
933 | /*define for DW_9 word*/ |
934 | /*define for dst_x field*/ |
935 | #define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 |
936 | #define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF |
937 | #define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 |
938 | #define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) |
939 | |
940 | /*define for dst_y field*/ |
941 | #define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 |
942 | #define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF |
943 | #define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 |
944 | #define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) |
945 | |
946 | /*define for DW_10 word*/ |
947 | /*define for dst_z field*/ |
948 | #define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 |
949 | #define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x000007FF |
950 | #define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 |
951 | #define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) |
952 | |
953 | /*define for dst_pitch_in_tile field*/ |
954 | #define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_offset 10 |
955 | #define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask 0x00000FFF |
956 | #define SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_shift 16 |
957 | #define SDMA_PKT_COPY_T2T_DW_10_DST_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_pitch_in_tile_shift) |
958 | |
959 | /*define for DW_11 word*/ |
960 | /*define for dst_slice_pitch field*/ |
961 | #define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_offset 11 |
962 | #define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask 0x003FFFFF |
963 | #define SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift 0 |
964 | #define SDMA_PKT_COPY_T2T_DW_11_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_slice_pitch_shift) |
965 | |
966 | /*define for DW_12 word*/ |
967 | /*define for dst_array_mode field*/ |
968 | #define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_offset 12 |
969 | #define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask 0x0000000F |
970 | #define SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_shift 3 |
971 | #define SDMA_PKT_COPY_T2T_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_array_mode_shift) |
972 | |
973 | /*define for dst_mit_mode field*/ |
974 | #define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_offset 12 |
975 | #define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask 0x00000007 |
976 | #define SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_shift 8 |
977 | #define SDMA_PKT_COPY_T2T_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mit_mode_shift) |
978 | |
979 | /*define for dst_tilesplit_size field*/ |
980 | #define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_offset 12 |
981 | #define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask 0x00000007 |
982 | #define SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_shift 11 |
983 | #define SDMA_PKT_COPY_T2T_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_tilesplit_size_shift) |
984 | |
985 | /*define for dst_bank_w field*/ |
986 | #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_offset 12 |
987 | #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask 0x00000003 |
988 | #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_shift 15 |
989 | #define SDMA_PKT_COPY_T2T_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_bank_w_shift) |
990 | |
991 | /*define for dst_bank_h field*/ |
992 | #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_offset 12 |
993 | #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask 0x00000003 |
994 | #define SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_shift 18 |
995 | #define SDMA_PKT_COPY_T2T_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_bank_h_shift) |
996 | |
997 | /*define for dst_num_bank field*/ |
998 | #define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_offset 12 |
999 | #define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask 0x00000003 |
1000 | #define SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_shift 21 |
1001 | #define SDMA_PKT_COPY_T2T_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_num_bank_shift) |
1002 | |
1003 | /*define for dst_mat_aspt field*/ |
1004 | #define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_offset 12 |
1005 | #define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask 0x00000003 |
1006 | #define SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_shift 24 |
1007 | #define SDMA_PKT_COPY_T2T_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mat_aspt_shift) |
1008 | |
1009 | /*define for dst_pipe_config field*/ |
1010 | #define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_offset 12 |
1011 | #define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask 0x0000001F |
1012 | #define SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_shift 26 |
1013 | #define SDMA_PKT_COPY_T2T_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_pipe_config_shift) |
1014 | |
1015 | /*define for DW_13 word*/ |
1016 | /*define for rect_x field*/ |
1017 | #define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 |
1018 | #define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF |
1019 | #define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 |
1020 | #define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) |
1021 | |
1022 | /*define for rect_y field*/ |
1023 | #define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 |
1024 | #define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF |
1025 | #define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 |
1026 | #define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) |
1027 | |
1028 | /*define for DW_14 word*/ |
1029 | /*define for rect_z field*/ |
1030 | #define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 |
1031 | #define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x000007FF |
1032 | #define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 |
1033 | #define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) |
1034 | |
1035 | /*define for dst_sw field*/ |
1036 | #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 |
1037 | #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 |
1038 | #define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 |
1039 | #define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) |
1040 | |
1041 | /*define for src_sw field*/ |
1042 | #define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 |
1043 | #define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 |
1044 | #define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 |
1045 | #define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) |
1046 | |
1047 | |
1048 | /* |
1049 | ** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet |
1050 | */ |
1051 | |
1052 | /*define for HEADER word*/ |
1053 | /*define for op field*/ |
1054 | #define 0 |
1055 | #define 0x000000FF |
1056 | #define 0 |
1057 | #define (x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) |
1058 | |
1059 | /*define for sub_op field*/ |
1060 | #define 0 |
1061 | #define 0x000000FF |
1062 | #define 8 |
1063 | #define (x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) |
1064 | |
1065 | /*define for detile field*/ |
1066 | #define 0 |
1067 | #define 0x00000001 |
1068 | #define 31 |
1069 | #define (x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) |
1070 | |
1071 | /*define for TILED_ADDR_LO word*/ |
1072 | /*define for tiled_addr_31_0 field*/ |
1073 | #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 |
1074 | #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF |
1075 | #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 |
1076 | #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) |
1077 | |
1078 | /*define for TILED_ADDR_HI word*/ |
1079 | /*define for tiled_addr_63_32 field*/ |
1080 | #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 |
1081 | #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF |
1082 | #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 |
1083 | #define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) |
1084 | |
1085 | /*define for DW_3 word*/ |
1086 | /*define for tiled_x field*/ |
1087 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 |
1088 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF |
1089 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 |
1090 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) |
1091 | |
1092 | /*define for tiled_y field*/ |
1093 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 |
1094 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF |
1095 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 |
1096 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) |
1097 | |
1098 | /*define for DW_4 word*/ |
1099 | /*define for tiled_z field*/ |
1100 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 |
1101 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x000007FF |
1102 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 |
1103 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) |
1104 | |
1105 | /*define for pitch_in_tile field*/ |
1106 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_offset 4 |
1107 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask 0x00000FFF |
1108 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_shift 16 |
1109 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_PITCH_IN_TILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_pitch_in_tile_shift) |
1110 | |
1111 | /*define for DW_5 word*/ |
1112 | /*define for slice_pitch field*/ |
1113 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_offset 5 |
1114 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask 0x003FFFFF |
1115 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift 0 |
1116 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_slice_pitch_shift) |
1117 | |
1118 | /*define for DW_6 word*/ |
1119 | /*define for element_size field*/ |
1120 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 |
1121 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 |
1122 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 |
1123 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) |
1124 | |
1125 | /*define for array_mode field*/ |
1126 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_offset 6 |
1127 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask 0x0000000F |
1128 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_shift 3 |
1129 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_array_mode_shift) |
1130 | |
1131 | /*define for mit_mode field*/ |
1132 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_offset 6 |
1133 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask 0x00000007 |
1134 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_shift 8 |
1135 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mit_mode_shift) |
1136 | |
1137 | /*define for tilesplit_size field*/ |
1138 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_offset 6 |
1139 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask 0x00000007 |
1140 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_shift 11 |
1141 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_tilesplit_size_shift) |
1142 | |
1143 | /*define for bank_w field*/ |
1144 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_offset 6 |
1145 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask 0x00000003 |
1146 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_shift 15 |
1147 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_w_shift) |
1148 | |
1149 | /*define for bank_h field*/ |
1150 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_offset 6 |
1151 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask 0x00000003 |
1152 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_shift 18 |
1153 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_bank_h_shift) |
1154 | |
1155 | /*define for num_bank field*/ |
1156 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_offset 6 |
1157 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask 0x00000003 |
1158 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_shift 21 |
1159 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_num_bank_shift) |
1160 | |
1161 | /*define for mat_aspt field*/ |
1162 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_offset 6 |
1163 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask 0x00000003 |
1164 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_shift 24 |
1165 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mat_aspt_shift) |
1166 | |
1167 | /*define for pipe_config field*/ |
1168 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_offset 6 |
1169 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask 0x0000001F |
1170 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_shift 26 |
1171 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_pipe_config_shift) |
1172 | |
1173 | /*define for LINEAR_ADDR_LO word*/ |
1174 | /*define for linear_addr_31_0 field*/ |
1175 | #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 |
1176 | #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF |
1177 | #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 |
1178 | #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) |
1179 | |
1180 | /*define for LINEAR_ADDR_HI word*/ |
1181 | /*define for linear_addr_63_32 field*/ |
1182 | #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 |
1183 | #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF |
1184 | #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 |
1185 | #define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) |
1186 | |
1187 | /*define for DW_9 word*/ |
1188 | /*define for linear_x field*/ |
1189 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 |
1190 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF |
1191 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 |
1192 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) |
1193 | |
1194 | /*define for linear_y field*/ |
1195 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 |
1196 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF |
1197 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 |
1198 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) |
1199 | |
1200 | /*define for DW_10 word*/ |
1201 | /*define for linear_z field*/ |
1202 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 |
1203 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x000007FF |
1204 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 |
1205 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) |
1206 | |
1207 | /*define for linear_pitch field*/ |
1208 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 |
1209 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF |
1210 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 |
1211 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) |
1212 | |
1213 | /*define for DW_11 word*/ |
1214 | /*define for linear_slice_pitch field*/ |
1215 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 |
1216 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF |
1217 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 |
1218 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) |
1219 | |
1220 | /*define for DW_12 word*/ |
1221 | /*define for rect_x field*/ |
1222 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 |
1223 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF |
1224 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 |
1225 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) |
1226 | |
1227 | /*define for rect_y field*/ |
1228 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 |
1229 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF |
1230 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 |
1231 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) |
1232 | |
1233 | /*define for DW_13 word*/ |
1234 | /*define for rect_z field*/ |
1235 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 |
1236 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x000007FF |
1237 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 |
1238 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) |
1239 | |
1240 | /*define for linear_sw field*/ |
1241 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 |
1242 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 |
1243 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 |
1244 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) |
1245 | |
1246 | /*define for tile_sw field*/ |
1247 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 |
1248 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 |
1249 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 |
1250 | #define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) |
1251 | |
1252 | |
1253 | /* |
1254 | ** Definitions for SDMA_PKT_COPY_STRUCT packet |
1255 | */ |
1256 | |
1257 | /*define for HEADER word*/ |
1258 | /*define for op field*/ |
1259 | #define 0 |
1260 | #define 0x000000FF |
1261 | #define 0 |
1262 | #define (x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) |
1263 | |
1264 | /*define for sub_op field*/ |
1265 | #define 0 |
1266 | #define 0x000000FF |
1267 | #define 8 |
1268 | #define (x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) |
1269 | |
1270 | /*define for detile field*/ |
1271 | #define 0 |
1272 | #define 0x00000001 |
1273 | #define 31 |
1274 | #define (x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) |
1275 | |
1276 | /*define for SB_ADDR_LO word*/ |
1277 | /*define for sb_addr_31_0 field*/ |
1278 | #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 |
1279 | #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF |
1280 | #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 |
1281 | #define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) |
1282 | |
1283 | /*define for SB_ADDR_HI word*/ |
1284 | /*define for sb_addr_63_32 field*/ |
1285 | #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 |
1286 | #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF |
1287 | #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 |
1288 | #define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) |
1289 | |
1290 | /*define for START_INDEX word*/ |
1291 | /*define for start_index field*/ |
1292 | #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 |
1293 | #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF |
1294 | #define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 |
1295 | #define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) |
1296 | |
1297 | /*define for COUNT word*/ |
1298 | /*define for count field*/ |
1299 | #define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 |
1300 | #define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF |
1301 | #define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 |
1302 | #define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) |
1303 | |
1304 | /*define for DW_5 word*/ |
1305 | /*define for stride field*/ |
1306 | #define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 |
1307 | #define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF |
1308 | #define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 |
1309 | #define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) |
1310 | |
1311 | /*define for struct_sw field*/ |
1312 | #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 |
1313 | #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 |
1314 | #define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 16 |
1315 | #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) |
1316 | |
1317 | /*define for struct_ha field*/ |
1318 | #define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_offset 5 |
1319 | #define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask 0x00000001 |
1320 | #define SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_shift 22 |
1321 | #define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_HA(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_ha_shift) |
1322 | |
1323 | /*define for linear_sw field*/ |
1324 | #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 |
1325 | #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 |
1326 | #define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 24 |
1327 | #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) |
1328 | |
1329 | /*define for linear_ha field*/ |
1330 | #define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_offset 5 |
1331 | #define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask 0x00000001 |
1332 | #define SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_shift 30 |
1333 | #define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_HA(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_ha_shift) |
1334 | |
1335 | /*define for LINEAR_ADDR_LO word*/ |
1336 | /*define for linear_addr_31_0 field*/ |
1337 | #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 |
1338 | #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF |
1339 | #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 |
1340 | #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) |
1341 | |
1342 | /*define for LINEAR_ADDR_HI word*/ |
1343 | /*define for linear_addr_63_32 field*/ |
1344 | #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 |
1345 | #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF |
1346 | #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 |
1347 | #define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) |
1348 | |
1349 | |
1350 | /* |
1351 | ** Definitions for SDMA_PKT_WRITE_UNTILED packet |
1352 | */ |
1353 | |
1354 | /*define for HEADER word*/ |
1355 | /*define for op field*/ |
1356 | #define 0 |
1357 | #define 0x000000FF |
1358 | #define 0 |
1359 | #define (x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) |
1360 | |
1361 | /*define for sub_op field*/ |
1362 | #define 0 |
1363 | #define 0x000000FF |
1364 | #define 8 |
1365 | #define (x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) |
1366 | |
1367 | /*define for DST_ADDR_LO word*/ |
1368 | /*define for dst_addr_31_0 field*/ |
1369 | #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 |
1370 | #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF |
1371 | #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 |
1372 | #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) |
1373 | |
1374 | /*define for DST_ADDR_HI word*/ |
1375 | /*define for dst_addr_63_32 field*/ |
1376 | #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 |
1377 | #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF |
1378 | #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 |
1379 | #define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) |
1380 | |
1381 | /*define for DW_3 word*/ |
1382 | /*define for count field*/ |
1383 | #define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 |
1384 | #define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x003FFFFF |
1385 | #define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 |
1386 | #define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) |
1387 | |
1388 | /*define for sw field*/ |
1389 | #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 |
1390 | #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 |
1391 | #define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 |
1392 | #define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) |
1393 | |
1394 | /*define for DATA0 word*/ |
1395 | /*define for data0 field*/ |
1396 | #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 |
1397 | #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF |
1398 | #define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 |
1399 | #define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) |
1400 | |
1401 | |
1402 | /* |
1403 | ** Definitions for SDMA_PKT_WRITE_TILED packet |
1404 | */ |
1405 | |
1406 | /*define for HEADER word*/ |
1407 | /*define for op field*/ |
1408 | #define 0 |
1409 | #define 0x000000FF |
1410 | #define 0 |
1411 | #define (x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) |
1412 | |
1413 | /*define for sub_op field*/ |
1414 | #define 0 |
1415 | #define 0x000000FF |
1416 | #define 8 |
1417 | #define (x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) |
1418 | |
1419 | /*define for DST_ADDR_LO word*/ |
1420 | /*define for dst_addr_31_0 field*/ |
1421 | #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 |
1422 | #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF |
1423 | #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 |
1424 | #define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) |
1425 | |
1426 | /*define for DST_ADDR_HI word*/ |
1427 | /*define for dst_addr_63_32 field*/ |
1428 | #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 |
1429 | #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF |
1430 | #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 |
1431 | #define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) |
1432 | |
1433 | /*define for DW_3 word*/ |
1434 | /*define for pitch_in_tile field*/ |
1435 | #define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_offset 3 |
1436 | #define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask 0x000007FF |
1437 | #define SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift 0 |
1438 | #define SDMA_PKT_WRITE_TILED_DW_3_PITCH_IN_TILE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_mask) << SDMA_PKT_WRITE_TILED_DW_3_pitch_in_tile_shift) |
1439 | |
1440 | /*define for height field*/ |
1441 | #define SDMA_PKT_WRITE_TILED_DW_3_height_offset 3 |
1442 | #define SDMA_PKT_WRITE_TILED_DW_3_height_mask 0x00003FFF |
1443 | #define SDMA_PKT_WRITE_TILED_DW_3_height_shift 16 |
1444 | #define SDMA_PKT_WRITE_TILED_DW_3_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_height_mask) << SDMA_PKT_WRITE_TILED_DW_3_height_shift) |
1445 | |
1446 | /*define for DW_4 word*/ |
1447 | /*define for slice_pitch field*/ |
1448 | #define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_offset 4 |
1449 | #define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask 0x003FFFFF |
1450 | #define SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift 0 |
1451 | #define SDMA_PKT_WRITE_TILED_DW_4_SLICE_PITCH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_mask) << SDMA_PKT_WRITE_TILED_DW_4_slice_pitch_shift) |
1452 | |
1453 | /*define for DW_5 word*/ |
1454 | /*define for element_size field*/ |
1455 | #define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 |
1456 | #define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 |
1457 | #define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 |
1458 | #define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) |
1459 | |
1460 | /*define for array_mode field*/ |
1461 | #define SDMA_PKT_WRITE_TILED_DW_5_array_mode_offset 5 |
1462 | #define SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask 0x0000000F |
1463 | #define SDMA_PKT_WRITE_TILED_DW_5_array_mode_shift 3 |
1464 | #define SDMA_PKT_WRITE_TILED_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_array_mode_shift) |
1465 | |
1466 | /*define for mit_mode field*/ |
1467 | #define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_offset 5 |
1468 | #define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask 0x00000007 |
1469 | #define SDMA_PKT_WRITE_TILED_DW_5_mit_mode_shift 8 |
1470 | #define SDMA_PKT_WRITE_TILED_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_mit_mode_shift) |
1471 | |
1472 | /*define for tilesplit_size field*/ |
1473 | #define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_offset 5 |
1474 | #define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask 0x00000007 |
1475 | #define SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_shift 11 |
1476 | #define SDMA_PKT_WRITE_TILED_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_tilesplit_size_shift) |
1477 | |
1478 | /*define for bank_w field*/ |
1479 | #define SDMA_PKT_WRITE_TILED_DW_5_bank_w_offset 5 |
1480 | #define SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask 0x00000003 |
1481 | #define SDMA_PKT_WRITE_TILED_DW_5_bank_w_shift 15 |
1482 | #define SDMA_PKT_WRITE_TILED_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_DW_5_bank_w_shift) |
1483 | |
1484 | /*define for bank_h field*/ |
1485 | #define SDMA_PKT_WRITE_TILED_DW_5_bank_h_offset 5 |
1486 | #define SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask 0x00000003 |
1487 | #define SDMA_PKT_WRITE_TILED_DW_5_bank_h_shift 18 |
1488 | #define SDMA_PKT_WRITE_TILED_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_DW_5_bank_h_shift) |
1489 | |
1490 | /*define for num_bank field*/ |
1491 | #define SDMA_PKT_WRITE_TILED_DW_5_num_bank_offset 5 |
1492 | #define SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask 0x00000003 |
1493 | #define SDMA_PKT_WRITE_TILED_DW_5_num_bank_shift 21 |
1494 | #define SDMA_PKT_WRITE_TILED_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_DW_5_num_bank_shift) |
1495 | |
1496 | /*define for mat_aspt field*/ |
1497 | #define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_offset 5 |
1498 | #define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask 0x00000003 |
1499 | #define SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_shift 24 |
1500 | #define SDMA_PKT_WRITE_TILED_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_DW_5_mat_aspt_shift) |
1501 | |
1502 | /*define for pipe_config field*/ |
1503 | #define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_offset 5 |
1504 | #define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask 0x0000001F |
1505 | #define SDMA_PKT_WRITE_TILED_DW_5_pipe_config_shift 26 |
1506 | #define SDMA_PKT_WRITE_TILED_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_DW_5_pipe_config_shift) |
1507 | |
1508 | /*define for DW_6 word*/ |
1509 | /*define for x field*/ |
1510 | #define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 |
1511 | #define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF |
1512 | #define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 |
1513 | #define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) |
1514 | |
1515 | /*define for y field*/ |
1516 | #define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 |
1517 | #define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF |
1518 | #define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 |
1519 | #define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) |
1520 | |
1521 | /*define for DW_7 word*/ |
1522 | /*define for z field*/ |
1523 | #define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 |
1524 | #define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00000FFF |
1525 | #define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 |
1526 | #define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) |
1527 | |
1528 | /*define for sw field*/ |
1529 | #define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 |
1530 | #define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 |
1531 | #define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 |
1532 | #define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) |
1533 | |
1534 | /*define for COUNT word*/ |
1535 | /*define for count field*/ |
1536 | #define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 |
1537 | #define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x003FFFFF |
1538 | #define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 |
1539 | #define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) |
1540 | |
1541 | /*define for DATA0 word*/ |
1542 | /*define for data0 field*/ |
1543 | #define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 |
1544 | #define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF |
1545 | #define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 |
1546 | #define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) |
1547 | |
1548 | |
1549 | /* |
1550 | ** Definitions for SDMA_PKT_WRITE_INCR packet |
1551 | */ |
1552 | |
1553 | /*define for HEADER word*/ |
1554 | /*define for op field*/ |
1555 | #define 0 |
1556 | #define 0x000000FF |
1557 | #define 0 |
1558 | #define (x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) |
1559 | |
1560 | /*define for sub_op field*/ |
1561 | #define 0 |
1562 | #define 0x000000FF |
1563 | #define 8 |
1564 | #define (x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) |
1565 | |
1566 | /*define for DST_ADDR_LO word*/ |
1567 | /*define for dst_addr_31_0 field*/ |
1568 | #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 |
1569 | #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF |
1570 | #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 |
1571 | #define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) |
1572 | |
1573 | /*define for DST_ADDR_HI word*/ |
1574 | /*define for dst_addr_63_32 field*/ |
1575 | #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 |
1576 | #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF |
1577 | #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 |
1578 | #define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) |
1579 | |
1580 | /*define for MASK_DW0 word*/ |
1581 | /*define for mask_dw0 field*/ |
1582 | #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 |
1583 | #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF |
1584 | #define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 |
1585 | #define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) |
1586 | |
1587 | /*define for MASK_DW1 word*/ |
1588 | /*define for mask_dw1 field*/ |
1589 | #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 |
1590 | #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF |
1591 | #define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 |
1592 | #define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) |
1593 | |
1594 | /*define for INIT_DW0 word*/ |
1595 | /*define for init_dw0 field*/ |
1596 | #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 |
1597 | #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF |
1598 | #define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 |
1599 | #define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) |
1600 | |
1601 | /*define for INIT_DW1 word*/ |
1602 | /*define for init_dw1 field*/ |
1603 | #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 |
1604 | #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF |
1605 | #define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 |
1606 | #define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) |
1607 | |
1608 | /*define for INCR_DW0 word*/ |
1609 | /*define for incr_dw0 field*/ |
1610 | #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 |
1611 | #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF |
1612 | #define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 |
1613 | #define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) |
1614 | |
1615 | /*define for INCR_DW1 word*/ |
1616 | /*define for incr_dw1 field*/ |
1617 | #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 |
1618 | #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF |
1619 | #define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 |
1620 | #define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) |
1621 | |
1622 | /*define for COUNT word*/ |
1623 | /*define for count field*/ |
1624 | #define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 |
1625 | #define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF |
1626 | #define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 |
1627 | #define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) |
1628 | |
1629 | |
1630 | /* |
1631 | ** Definitions for SDMA_PKT_INDIRECT packet |
1632 | */ |
1633 | |
1634 | /*define for HEADER word*/ |
1635 | /*define for op field*/ |
1636 | #define 0 |
1637 | #define 0x000000FF |
1638 | #define 0 |
1639 | #define (x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) |
1640 | |
1641 | /*define for sub_op field*/ |
1642 | #define 0 |
1643 | #define 0x000000FF |
1644 | #define 8 |
1645 | #define (x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) |
1646 | |
1647 | /*define for vmid field*/ |
1648 | #define 0 |
1649 | #define 0x0000000F |
1650 | #define 16 |
1651 | #define (x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) |
1652 | |
1653 | /*define for BASE_LO word*/ |
1654 | /*define for ib_base_31_0 field*/ |
1655 | #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 |
1656 | #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF |
1657 | #define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 |
1658 | #define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) |
1659 | |
1660 | /*define for BASE_HI word*/ |
1661 | /*define for ib_base_63_32 field*/ |
1662 | #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 |
1663 | #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF |
1664 | #define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 |
1665 | #define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) |
1666 | |
1667 | /*define for IB_SIZE word*/ |
1668 | /*define for ib_size field*/ |
1669 | #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 |
1670 | #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF |
1671 | #define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 |
1672 | #define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) |
1673 | |
1674 | /*define for CSA_ADDR_LO word*/ |
1675 | /*define for csa_addr_31_0 field*/ |
1676 | #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 |
1677 | #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF |
1678 | #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 |
1679 | #define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) |
1680 | |
1681 | /*define for CSA_ADDR_HI word*/ |
1682 | /*define for csa_addr_63_32 field*/ |
1683 | #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 |
1684 | #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF |
1685 | #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 |
1686 | #define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) |
1687 | |
1688 | |
1689 | /* |
1690 | ** Definitions for SDMA_PKT_SEMAPHORE packet |
1691 | */ |
1692 | |
1693 | /*define for HEADER word*/ |
1694 | /*define for op field*/ |
1695 | #define 0 |
1696 | #define 0x000000FF |
1697 | #define 0 |
1698 | #define (x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) |
1699 | |
1700 | /*define for sub_op field*/ |
1701 | #define 0 |
1702 | #define 0x000000FF |
1703 | #define 8 |
1704 | #define (x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) |
1705 | |
1706 | /*define for write_one field*/ |
1707 | #define 0 |
1708 | #define 0x00000001 |
1709 | #define 29 |
1710 | #define (x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) |
1711 | |
1712 | /*define for signal field*/ |
1713 | #define 0 |
1714 | #define 0x00000001 |
1715 | #define 30 |
1716 | #define (x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) |
1717 | |
1718 | /*define for mailbox field*/ |
1719 | #define 0 |
1720 | #define 0x00000001 |
1721 | #define 31 |
1722 | #define (x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) |
1723 | |
1724 | /*define for ADDR_LO word*/ |
1725 | /*define for addr_31_0 field*/ |
1726 | #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 |
1727 | #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF |
1728 | #define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 |
1729 | #define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) |
1730 | |
1731 | /*define for ADDR_HI word*/ |
1732 | /*define for addr_63_32 field*/ |
1733 | #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 |
1734 | #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF |
1735 | #define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 |
1736 | #define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) |
1737 | |
1738 | |
1739 | /* |
1740 | ** Definitions for SDMA_PKT_FENCE packet |
1741 | */ |
1742 | |
1743 | /*define for HEADER word*/ |
1744 | /*define for op field*/ |
1745 | #define 0 |
1746 | #define 0x000000FF |
1747 | #define 0 |
1748 | #define (x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) |
1749 | |
1750 | /*define for sub_op field*/ |
1751 | #define 0 |
1752 | #define 0x000000FF |
1753 | #define 8 |
1754 | #define (x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) |
1755 | |
1756 | /*define for ADDR_LO word*/ |
1757 | /*define for addr_31_0 field*/ |
1758 | #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 |
1759 | #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF |
1760 | #define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 |
1761 | #define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) |
1762 | |
1763 | /*define for ADDR_HI word*/ |
1764 | /*define for addr_63_32 field*/ |
1765 | #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 |
1766 | #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF |
1767 | #define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 |
1768 | #define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) |
1769 | |
1770 | /*define for DATA word*/ |
1771 | /*define for data field*/ |
1772 | #define SDMA_PKT_FENCE_DATA_data_offset 3 |
1773 | #define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF |
1774 | #define SDMA_PKT_FENCE_DATA_data_shift 0 |
1775 | #define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) |
1776 | |
1777 | |
1778 | /* |
1779 | ** Definitions for SDMA_PKT_SRBM_WRITE packet |
1780 | */ |
1781 | |
1782 | /*define for HEADER word*/ |
1783 | /*define for op field*/ |
1784 | #define 0 |
1785 | #define 0x000000FF |
1786 | #define 0 |
1787 | #define (x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) |
1788 | |
1789 | /*define for sub_op field*/ |
1790 | #define 0 |
1791 | #define 0x000000FF |
1792 | #define 8 |
1793 | #define (x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) |
1794 | |
1795 | /*define for byte_en field*/ |
1796 | #define 0 |
1797 | #define 0x0000000F |
1798 | #define 28 |
1799 | #define (x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) |
1800 | |
1801 | /*define for ADDR word*/ |
1802 | /*define for addr field*/ |
1803 | #define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 |
1804 | #define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0000FFFF |
1805 | #define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 |
1806 | #define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) |
1807 | |
1808 | /*define for DATA word*/ |
1809 | /*define for data field*/ |
1810 | #define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 |
1811 | #define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF |
1812 | #define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 |
1813 | #define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) |
1814 | |
1815 | |
1816 | /* |
1817 | ** Definitions for SDMA_PKT_PRE_EXE packet |
1818 | */ |
1819 | |
1820 | /*define for HEADER word*/ |
1821 | /*define for op field*/ |
1822 | #define 0 |
1823 | #define 0x000000FF |
1824 | #define 0 |
1825 | #define (x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) |
1826 | |
1827 | /*define for sub_op field*/ |
1828 | #define 0 |
1829 | #define 0x000000FF |
1830 | #define 8 |
1831 | #define (x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) |
1832 | |
1833 | /*define for dev_sel field*/ |
1834 | #define 0 |
1835 | #define 0x000000FF |
1836 | #define 16 |
1837 | #define (x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) |
1838 | |
1839 | /*define for EXEC_COUNT word*/ |
1840 | /*define for exec_count field*/ |
1841 | #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 |
1842 | #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF |
1843 | #define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 |
1844 | #define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) |
1845 | |
1846 | |
1847 | /* |
1848 | ** Definitions for SDMA_PKT_COND_EXE packet |
1849 | */ |
1850 | |
1851 | /*define for HEADER word*/ |
1852 | /*define for op field*/ |
1853 | #define 0 |
1854 | #define 0x000000FF |
1855 | #define 0 |
1856 | #define (x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) |
1857 | |
1858 | /*define for sub_op field*/ |
1859 | #define 0 |
1860 | #define 0x000000FF |
1861 | #define 8 |
1862 | #define (x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) |
1863 | |
1864 | /*define for ADDR_LO word*/ |
1865 | /*define for addr_31_0 field*/ |
1866 | #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 |
1867 | #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF |
1868 | #define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 |
1869 | #define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) |
1870 | |
1871 | /*define for ADDR_HI word*/ |
1872 | /*define for addr_63_32 field*/ |
1873 | #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 |
1874 | #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF |
1875 | #define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 |
1876 | #define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) |
1877 | |
1878 | /*define for REFERENCE word*/ |
1879 | /*define for reference field*/ |
1880 | #define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 |
1881 | #define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF |
1882 | #define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 |
1883 | #define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) |
1884 | |
1885 | /*define for EXEC_COUNT word*/ |
1886 | /*define for exec_count field*/ |
1887 | #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 |
1888 | #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF |
1889 | #define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 |
1890 | #define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) |
1891 | |
1892 | |
1893 | /* |
1894 | ** Definitions for SDMA_PKT_CONSTANT_FILL packet |
1895 | */ |
1896 | |
1897 | /*define for HEADER word*/ |
1898 | /*define for op field*/ |
1899 | #define 0 |
1900 | #define 0x000000FF |
1901 | #define 0 |
1902 | #define (x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) |
1903 | |
1904 | /*define for sub_op field*/ |
1905 | #define 0 |
1906 | #define 0x000000FF |
1907 | #define 8 |
1908 | #define (x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) |
1909 | |
1910 | /*define for sw field*/ |
1911 | #define 0 |
1912 | #define 0x00000003 |
1913 | #define 16 |
1914 | #define (x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) |
1915 | |
1916 | /*define for fillsize field*/ |
1917 | #define 0 |
1918 | #define 0x00000003 |
1919 | #define 30 |
1920 | #define (x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) |
1921 | |
1922 | /*define for DST_ADDR_LO word*/ |
1923 | /*define for dst_addr_31_0 field*/ |
1924 | #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 |
1925 | #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF |
1926 | #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 |
1927 | #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) |
1928 | |
1929 | /*define for DST_ADDR_HI word*/ |
1930 | /*define for dst_addr_63_32 field*/ |
1931 | #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 |
1932 | #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF |
1933 | #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 |
1934 | #define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) |
1935 | |
1936 | /*define for DATA word*/ |
1937 | /*define for src_data_31_0 field*/ |
1938 | #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 |
1939 | #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF |
1940 | #define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 |
1941 | #define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) |
1942 | |
1943 | /*define for COUNT word*/ |
1944 | /*define for count field*/ |
1945 | #define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 |
1946 | #define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x003FFFFF |
1947 | #define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 |
1948 | #define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) |
1949 | |
1950 | |
1951 | /* |
1952 | ** Definitions for SDMA_PKT_POLL_REGMEM packet |
1953 | */ |
1954 | |
1955 | /*define for HEADER word*/ |
1956 | /*define for op field*/ |
1957 | #define 0 |
1958 | #define 0x000000FF |
1959 | #define 0 |
1960 | #define (x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) |
1961 | |
1962 | /*define for sub_op field*/ |
1963 | #define 0 |
1964 | #define 0x000000FF |
1965 | #define 8 |
1966 | #define (x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) |
1967 | |
1968 | /*define for hdp_flush field*/ |
1969 | #define 0 |
1970 | #define 0x00000001 |
1971 | #define 26 |
1972 | #define (x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) |
1973 | |
1974 | /*define for func field*/ |
1975 | #define 0 |
1976 | #define 0x00000007 |
1977 | #define 28 |
1978 | #define (x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) |
1979 | |
1980 | /*define for mem_poll field*/ |
1981 | #define 0 |
1982 | #define 0x00000001 |
1983 | #define 31 |
1984 | #define (x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) |
1985 | |
1986 | /*define for ADDR_LO word*/ |
1987 | /*define for addr_31_0 field*/ |
1988 | #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 |
1989 | #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF |
1990 | #define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 |
1991 | #define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) |
1992 | |
1993 | /*define for ADDR_HI word*/ |
1994 | /*define for addr_63_32 field*/ |
1995 | #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 |
1996 | #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF |
1997 | #define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 |
1998 | #define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) |
1999 | |
2000 | /*define for VALUE word*/ |
2001 | /*define for value field*/ |
2002 | #define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 |
2003 | #define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF |
2004 | #define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 |
2005 | #define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) |
2006 | |
2007 | /*define for MASK word*/ |
2008 | /*define for mask field*/ |
2009 | #define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 |
2010 | #define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF |
2011 | #define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 |
2012 | #define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) |
2013 | |
2014 | /*define for DW5 word*/ |
2015 | /*define for interval field*/ |
2016 | #define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 |
2017 | #define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF |
2018 | #define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 |
2019 | #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) |
2020 | |
2021 | /*define for retry_count field*/ |
2022 | #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 |
2023 | #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF |
2024 | #define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 |
2025 | #define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) |
2026 | |
2027 | |
2028 | /* |
2029 | ** Definitions for SDMA_PKT_TIMESTAMP_SET packet |
2030 | */ |
2031 | |
2032 | /*define for HEADER word*/ |
2033 | /*define for op field*/ |
2034 | #define 0 |
2035 | #define 0x000000FF |
2036 | #define 0 |
2037 | #define (x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) |
2038 | |
2039 | /*define for sub_op field*/ |
2040 | #define 0 |
2041 | #define 0x000000FF |
2042 | #define 8 |
2043 | #define (x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) |
2044 | |
2045 | /*define for INIT_DATA_LO word*/ |
2046 | /*define for init_data_31_0 field*/ |
2047 | #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 |
2048 | #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF |
2049 | #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 |
2050 | #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) |
2051 | |
2052 | /*define for INIT_DATA_HI word*/ |
2053 | /*define for init_data_63_32 field*/ |
2054 | #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 |
2055 | #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF |
2056 | #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 |
2057 | #define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) |
2058 | |
2059 | |
2060 | /* |
2061 | ** Definitions for SDMA_PKT_TIMESTAMP_GET packet |
2062 | */ |
2063 | |
2064 | /*define for HEADER word*/ |
2065 | /*define for op field*/ |
2066 | #define 0 |
2067 | #define 0x000000FF |
2068 | #define 0 |
2069 | #define (x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) |
2070 | |
2071 | /*define for sub_op field*/ |
2072 | #define 0 |
2073 | #define 0x000000FF |
2074 | #define 8 |
2075 | #define (x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) |
2076 | |
2077 | /*define for WRITE_ADDR_LO word*/ |
2078 | /*define for write_addr_31_3 field*/ |
2079 | #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 |
2080 | #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF |
2081 | #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 |
2082 | #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) |
2083 | |
2084 | /*define for WRITE_ADDR_HI word*/ |
2085 | /*define for write_addr_63_32 field*/ |
2086 | #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 |
2087 | #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF |
2088 | #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 |
2089 | #define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) |
2090 | |
2091 | |
2092 | /* |
2093 | ** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet |
2094 | */ |
2095 | |
2096 | /*define for HEADER word*/ |
2097 | /*define for op field*/ |
2098 | #define 0 |
2099 | #define 0x000000FF |
2100 | #define 0 |
2101 | #define (x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) |
2102 | |
2103 | /*define for sub_op field*/ |
2104 | #define 0 |
2105 | #define 0x000000FF |
2106 | #define 8 |
2107 | #define (x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) |
2108 | |
2109 | /*define for WRITE_ADDR_LO word*/ |
2110 | /*define for write_addr_31_3 field*/ |
2111 | #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 |
2112 | #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF |
2113 | #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 |
2114 | #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) |
2115 | |
2116 | /*define for WRITE_ADDR_HI word*/ |
2117 | /*define for write_addr_63_32 field*/ |
2118 | #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 |
2119 | #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF |
2120 | #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 |
2121 | #define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) |
2122 | |
2123 | |
2124 | /* |
2125 | ** Definitions for SDMA_PKT_TRAP packet |
2126 | */ |
2127 | |
2128 | /*define for HEADER word*/ |
2129 | /*define for op field*/ |
2130 | #define 0 |
2131 | #define 0x000000FF |
2132 | #define 0 |
2133 | #define (x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) |
2134 | |
2135 | /*define for sub_op field*/ |
2136 | #define 0 |
2137 | #define 0x000000FF |
2138 | #define 8 |
2139 | #define (x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) |
2140 | |
2141 | /*define for INT_CONTEXT word*/ |
2142 | /*define for int_context field*/ |
2143 | #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 |
2144 | #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF |
2145 | #define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 |
2146 | #define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) |
2147 | |
2148 | |
2149 | /* |
2150 | ** Definitions for SDMA_PKT_NOP packet |
2151 | */ |
2152 | |
2153 | /*define for HEADER word*/ |
2154 | /*define for op field*/ |
2155 | #define 0 |
2156 | #define 0x000000FF |
2157 | #define 0 |
2158 | #define (x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) |
2159 | |
2160 | /*define for sub_op field*/ |
2161 | #define 0 |
2162 | #define 0x000000FF |
2163 | #define 8 |
2164 | #define (x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) |
2165 | |
2166 | /*define for count field*/ |
2167 | #define 0 |
2168 | #define 0x00003FFF |
2169 | #define 16 |
2170 | #define (x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) |
2171 | |
2172 | #endif /* __ICELAND_SDMA_PKT_OPEN_H_ */ |
2173 | |