| 1 | /* |
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| 2 | * Copyright 2014 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | #ifndef VI_H |
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| 24 | #define VI_H |
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| 25 | |
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| 26 | #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ |
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| 27 | #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ |
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| 28 | #define SDMA_MAX_INSTANCE 2 |
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| 29 | |
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| 30 | #define KFD_VI_SDMA_QUEUE_OFFSET 0x80 /* not a register */ |
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| 31 | |
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| 32 | /* crtc instance offsets */ |
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| 33 | #define CRTC0_REGISTER_OFFSET (0x1b9c - 0x1b9c) |
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| 34 | #define CRTC1_REGISTER_OFFSET (0x1d9c - 0x1b9c) |
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| 35 | #define CRTC2_REGISTER_OFFSET (0x1f9c - 0x1b9c) |
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| 36 | #define CRTC3_REGISTER_OFFSET (0x419c - 0x1b9c) |
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| 37 | #define CRTC4_REGISTER_OFFSET (0x439c - 0x1b9c) |
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| 38 | #define CRTC5_REGISTER_OFFSET (0x459c - 0x1b9c) |
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| 39 | #define CRTC6_REGISTER_OFFSET (0x479c - 0x1b9c) |
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| 40 | |
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| 41 | /* dig instance offsets */ |
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| 42 | #define DIG0_REGISTER_OFFSET (0x4a00 - 0x4a00) |
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| 43 | #define DIG1_REGISTER_OFFSET (0x4b00 - 0x4a00) |
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| 44 | #define DIG2_REGISTER_OFFSET (0x4c00 - 0x4a00) |
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| 45 | #define DIG3_REGISTER_OFFSET (0x4d00 - 0x4a00) |
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| 46 | #define DIG4_REGISTER_OFFSET (0x4e00 - 0x4a00) |
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| 47 | #define DIG5_REGISTER_OFFSET (0x4f00 - 0x4a00) |
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| 48 | #define DIG6_REGISTER_OFFSET (0x5400 - 0x4a00) |
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| 49 | #define DIG7_REGISTER_OFFSET (0x5600 - 0x4a00) |
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| 50 | #define DIG8_REGISTER_OFFSET (0x5700 - 0x4a00) |
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| 51 | |
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| 52 | /* audio endpt instance offsets */ |
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| 53 | #define AUD0_REGISTER_OFFSET (0x17a8 - 0x17a8) |
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| 54 | #define AUD1_REGISTER_OFFSET (0x17ac - 0x17a8) |
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| 55 | #define AUD2_REGISTER_OFFSET (0x17b0 - 0x17a8) |
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| 56 | #define AUD3_REGISTER_OFFSET (0x17b4 - 0x17a8) |
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| 57 | #define AUD4_REGISTER_OFFSET (0x17b8 - 0x17a8) |
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| 58 | #define AUD5_REGISTER_OFFSET (0x17bc - 0x17a8) |
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| 59 | #define AUD6_REGISTER_OFFSET (0x17c0 - 0x17a8) |
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| 60 | #define AUD7_REGISTER_OFFSET (0x17c4 - 0x17a8) |
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| 61 | |
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| 62 | /* hpd instance offsets */ |
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| 63 | #define HPD0_REGISTER_OFFSET (0x1898 - 0x1898) |
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| 64 | #define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898) |
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| 65 | #define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898) |
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| 66 | #define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898) |
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| 67 | #define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898) |
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| 68 | #define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898) |
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| 69 | |
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| 70 | #define PIPEID(x) ((x) << 0) |
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| 71 | #define MEID(x) ((x) << 2) |
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| 72 | #define VMID(x) ((x) << 4) |
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| 73 | #define QUEUEID(x) ((x) << 8) |
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| 74 | |
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| 75 | #define MC_SEQ_MISC0__MT__MASK 0xf0000000 |
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| 76 | #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 |
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| 77 | #define MC_SEQ_MISC0__MT__DDR2 0x20000000 |
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| 78 | #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 |
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| 79 | #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 |
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| 80 | #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 |
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| 81 | #define MC_SEQ_MISC0__MT__HBM 0x60000000 |
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| 82 | #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 |
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| 83 | |
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| 84 | /* |
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| 85 | * PM4 |
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| 86 | */ |
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| 87 | #define PACKET_TYPE0 0 |
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| 88 | #define PACKET_TYPE1 1 |
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| 89 | #define PACKET_TYPE2 2 |
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| 90 | #define PACKET_TYPE3 3 |
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| 91 | |
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| 92 | #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
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| 93 | #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
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| 94 | #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) |
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| 95 | #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
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| 96 | #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ |
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| 97 | ((reg) & 0xFFFF) | \ |
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| 98 | ((n) & 0x3FFF) << 16) |
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| 99 | #define CP_PACKET2 0x80000000 |
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| 100 | #define PACKET2_PAD_SHIFT 0 |
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| 101 | #define PACKET2_PAD_MASK (0x3fffffff << 0) |
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| 102 | |
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| 103 | #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
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| 104 | |
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| 105 | #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ |
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| 106 | (((op) & 0xFF) << 8) | \ |
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| 107 | ((n) & 0x3FFF) << 16) |
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| 108 | |
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| 109 | #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) |
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| 110 | |
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| 111 | /* Packet 3 types */ |
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| 112 | #define PACKET3_NOP 0x10 |
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| 113 | #define PACKET3_SET_BASE 0x11 |
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| 114 | #define PACKET3_BASE_INDEX(x) ((x) << 0) |
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| 115 | #define CE_PARTITION_BASE 3 |
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| 116 | #define PACKET3_CLEAR_STATE 0x12 |
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| 117 | #define PACKET3_INDEX_BUFFER_SIZE 0x13 |
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| 118 | #define PACKET3_DISPATCH_DIRECT 0x15 |
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| 119 | #define PACKET3_DISPATCH_INDIRECT 0x16 |
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| 120 | #define PACKET3_ATOMIC_GDS 0x1D |
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| 121 | #define PACKET3_ATOMIC_MEM 0x1E |
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| 122 | #define PACKET3_OCCLUSION_QUERY 0x1F |
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| 123 | #define PACKET3_SET_PREDICATION 0x20 |
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| 124 | #define PACKET3_REG_RMW 0x21 |
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| 125 | #define PACKET3_COND_EXEC 0x22 |
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| 126 | #define PACKET3_PRED_EXEC 0x23 |
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| 127 | #define PACKET3_DRAW_INDIRECT 0x24 |
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| 128 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25 |
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| 129 | #define PACKET3_INDEX_BASE 0x26 |
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| 130 | #define PACKET3_DRAW_INDEX_2 0x27 |
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| 131 | #define PACKET3_CONTEXT_CONTROL 0x28 |
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| 132 | #define PACKET3_INDEX_TYPE 0x2A |
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| 133 | #define PACKET3_DRAW_INDIRECT_MULTI 0x2C |
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| 134 | #define PACKET3_DRAW_INDEX_AUTO 0x2D |
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| 135 | #define PACKET3_NUM_INSTANCES 0x2F |
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| 136 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 |
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| 137 | #define PACKET3_INDIRECT_BUFFER_CONST 0x33 |
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| 138 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 |
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| 139 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 |
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| 140 | #define PACKET3_DRAW_PREAMBLE 0x36 |
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| 141 | #define PACKET3_WRITE_DATA 0x37 |
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| 142 | #define WRITE_DATA_DST_SEL(x) ((x) << 8) |
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| 143 | /* 0 - register |
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| 144 | * 1 - memory (sync - via GRBM) |
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| 145 | * 2 - gl2 |
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| 146 | * 3 - gds |
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| 147 | * 4 - reserved |
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| 148 | * 5 - memory (async - direct) |
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| 149 | */ |
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| 150 | #define WR_ONE_ADDR (1 << 16) |
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| 151 | #define WR_CONFIRM (1 << 20) |
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| 152 | #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) |
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| 153 | /* 0 - LRU |
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| 154 | * 1 - Stream |
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| 155 | */ |
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| 156 | #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) |
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| 157 | /* 0 - me |
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| 158 | * 1 - pfp |
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| 159 | * 2 - ce |
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| 160 | */ |
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| 161 | #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 |
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| 162 | #define PACKET3_MEM_SEMAPHORE 0x39 |
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| 163 | # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) |
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| 164 | # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ |
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| 165 | # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ |
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| 166 | # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) |
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| 167 | # define PACKET3_SEM_SEL_WAIT (0x7 << 29) |
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| 168 | #define PACKET3_WAIT_REG_MEM 0x3C |
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| 169 | #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) |
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| 170 | /* 0 - always |
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| 171 | * 1 - < |
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| 172 | * 2 - <= |
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| 173 | * 3 - == |
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| 174 | * 4 - != |
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| 175 | * 5 - >= |
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| 176 | * 6 - > |
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| 177 | */ |
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| 178 | #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) |
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| 179 | /* 0 - reg |
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| 180 | * 1 - mem |
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| 181 | */ |
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| 182 | #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) |
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| 183 | /* 0 - wait_reg_mem |
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| 184 | * 1 - wr_wait_wr_reg |
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| 185 | */ |
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| 186 | #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) |
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| 187 | /* 0 - me |
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| 188 | * 1 - pfp |
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| 189 | */ |
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| 190 | #define PACKET3_INDIRECT_BUFFER 0x3F |
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| 191 | #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) |
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| 192 | #define INDIRECT_BUFFER_VALID (1 << 23) |
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| 193 | #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) |
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| 194 | /* 0 - LRU |
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| 195 | * 1 - Stream |
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| 196 | * 2 - Bypass |
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| 197 | */ |
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| 198 | #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) |
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| 199 | #define PACKET3_COPY_DATA 0x40 |
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| 200 | #define PACKET3_PFP_SYNC_ME 0x42 |
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| 201 | #define PACKET3_SURFACE_SYNC 0x43 |
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| 202 | # define PACKET3_DEST_BASE_0_ENA (1 << 0) |
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| 203 | # define PACKET3_DEST_BASE_1_ENA (1 << 1) |
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| 204 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
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| 205 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) |
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| 206 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) |
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| 207 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) |
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| 208 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) |
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| 209 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) |
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| 210 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) |
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| 211 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) |
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| 212 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14) |
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| 213 | # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) |
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| 214 | # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ |
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| 215 | # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ |
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| 216 | # define PACKET3_DEST_BASE_2_ENA (1 << 19) |
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| 217 | # define PACKET3_DEST_BASE_3_ENA (1 << 21) |
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| 218 | # define PACKET3_TCL1_ACTION_ENA (1 << 22) |
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| 219 | # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ |
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| 220 | # define PACKET3_CB_ACTION_ENA (1 << 25) |
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| 221 | # define PACKET3_DB_ACTION_ENA (1 << 26) |
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| 222 | # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) |
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| 223 | # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) |
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| 224 | # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) |
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| 225 | #define PACKET3_COND_WRITE 0x45 |
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| 226 | #define PACKET3_EVENT_WRITE 0x46 |
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| 227 | #define EVENT_TYPE(x) ((x) << 0) |
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| 228 | #define EVENT_INDEX(x) ((x) << 8) |
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| 229 | /* 0 - any non-TS event |
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| 230 | * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* |
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| 231 | * 2 - SAMPLE_PIPELINESTAT |
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| 232 | * 3 - SAMPLE_STREAMOUTSTAT* |
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| 233 | * 4 - *S_PARTIAL_FLUSH |
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| 234 | * 5 - EOP events |
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| 235 | * 6 - EOS events |
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| 236 | */ |
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| 237 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
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| 238 | #define EOP_TCL1_VOL_ACTION_EN (1 << 12) |
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| 239 | #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ |
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| 240 | #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ |
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| 241 | #define EOP_TCL1_ACTION_EN (1 << 16) |
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| 242 | #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ |
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| 243 | #define EOP_TCL2_VOLATILE (1 << 24) |
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| 244 | #define EOP_CACHE_POLICY(x) ((x) << 25) |
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| 245 | /* 0 - LRU |
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| 246 | * 1 - Stream |
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| 247 | * 2 - Bypass |
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| 248 | */ |
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| 249 | #define DATA_SEL(x) ((x) << 29) |
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| 250 | /* 0 - discard |
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| 251 | * 1 - send low 32bit data |
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| 252 | * 2 - send 64bit data |
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| 253 | * 3 - send 64bit GPU counter value |
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| 254 | * 4 - send 64bit sys counter value |
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| 255 | */ |
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| 256 | #define INT_SEL(x) ((x) << 24) |
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| 257 | /* 0 - none |
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| 258 | * 1 - interrupt only (DATA_SEL = 0) |
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| 259 | * 2 - interrupt when data write is confirmed |
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| 260 | */ |
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| 261 | #define DST_SEL(x) ((x) << 16) |
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| 262 | /* 0 - MC |
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| 263 | * 1 - TC/L2 |
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| 264 | */ |
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| 265 | #define PACKET3_EVENT_WRITE_EOS 0x48 |
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| 266 | #define PACKET3_RELEASE_MEM 0x49 |
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| 267 | #define PACKET3_PREAMBLE_CNTL 0x4A |
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| 268 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) |
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| 269 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) |
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| 270 | #define PACKET3_DMA_DATA 0x50 |
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| 271 | /* 1. header |
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| 272 | * 2. CONTROL |
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| 273 | * 3. SRC_ADDR_LO or DATA [31:0] |
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| 274 | * 4. SRC_ADDR_HI [31:0] |
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| 275 | * 5. DST_ADDR_LO [31:0] |
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| 276 | * 6. DST_ADDR_HI [7:0] |
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| 277 | * 7. COMMAND [30:21] | BYTE_COUNT [20:0] |
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| 278 | */ |
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| 279 | /* CONTROL */ |
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| 280 | # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) |
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| 281 | /* 0 - ME |
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| 282 | * 1 - PFP |
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| 283 | */ |
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| 284 | # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) |
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| 285 | /* 0 - LRU |
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| 286 | * 1 - Stream |
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| 287 | * 2 - Bypass |
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| 288 | */ |
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| 289 | # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) |
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| 290 | # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) |
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| 291 | /* 0 - DST_ADDR using DAS |
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| 292 | * 1 - GDS |
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| 293 | * 3 - DST_ADDR using L2 |
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| 294 | */ |
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| 295 | # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) |
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| 296 | /* 0 - LRU |
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| 297 | * 1 - Stream |
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| 298 | * 2 - Bypass |
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| 299 | */ |
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| 300 | # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) |
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| 301 | # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) |
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| 302 | /* 0 - SRC_ADDR using SAS |
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| 303 | * 1 - GDS |
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| 304 | * 2 - DATA |
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| 305 | * 3 - SRC_ADDR using L2 |
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| 306 | */ |
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| 307 | # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) |
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| 308 | /* COMMAND */ |
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| 309 | # define PACKET3_DMA_DATA_DIS_WC (1 << 21) |
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| 310 | # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) |
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| 311 | /* 0 - none |
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| 312 | * 1 - 8 in 16 |
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| 313 | * 2 - 8 in 32 |
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| 314 | * 3 - 8 in 64 |
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| 315 | */ |
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| 316 | # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) |
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| 317 | /* 0 - none |
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| 318 | * 1 - 8 in 16 |
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| 319 | * 2 - 8 in 32 |
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| 320 | * 3 - 8 in 64 |
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| 321 | */ |
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| 322 | # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) |
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| 323 | /* 0 - memory |
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| 324 | * 1 - register |
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| 325 | */ |
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| 326 | # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) |
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| 327 | /* 0 - memory |
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| 328 | * 1 - register |
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| 329 | */ |
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| 330 | # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) |
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| 331 | # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) |
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| 332 | # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) |
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| 333 | #define PACKET3_ACQUIRE_MEM 0x58 |
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| 334 | #define PACKET3_REWIND 0x59 |
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| 335 | #define PACKET3_LOAD_UCONFIG_REG 0x5E |
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| 336 | #define PACKET3_LOAD_SH_REG 0x5F |
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| 337 | #define PACKET3_LOAD_CONFIG_REG 0x60 |
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| 338 | #define PACKET3_LOAD_CONTEXT_REG 0x61 |
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| 339 | #define PACKET3_SET_CONFIG_REG 0x68 |
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| 340 | #define PACKET3_SET_CONFIG_REG_START 0x00002000 |
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| 341 | #define PACKET3_SET_CONFIG_REG_END 0x00002c00 |
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| 342 | #define PACKET3_SET_CONTEXT_REG 0x69 |
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| 343 | #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 |
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| 344 | #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 |
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| 345 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 |
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| 346 | #define PACKET3_SET_SH_REG 0x76 |
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| 347 | #define PACKET3_SET_SH_REG_START 0x00002c00 |
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| 348 | #define PACKET3_SET_SH_REG_END 0x00003000 |
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| 349 | #define PACKET3_SET_SH_REG_OFFSET 0x77 |
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| 350 | #define PACKET3_SET_QUEUE_REG 0x78 |
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| 351 | #define PACKET3_SET_UCONFIG_REG 0x79 |
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| 352 | #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 |
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| 353 | #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 |
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| 354 | #define PACKET3_SCRATCH_RAM_WRITE 0x7D |
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| 355 | #define PACKET3_SCRATCH_RAM_READ 0x7E |
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| 356 | #define PACKET3_LOAD_CONST_RAM 0x80 |
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| 357 | #define PACKET3_WRITE_CONST_RAM 0x81 |
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| 358 | #define PACKET3_DUMP_CONST_RAM 0x83 |
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| 359 | #define PACKET3_INCREMENT_CE_COUNTER 0x84 |
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| 360 | #define PACKET3_INCREMENT_DE_COUNTER 0x85 |
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| 361 | #define PACKET3_WAIT_ON_CE_COUNTER 0x86 |
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| 362 | #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 |
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| 363 | #define PACKET3_SWITCH_BUFFER 0x8B |
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| 364 | #define PACKET3_FRAME_CONTROL 0x90 |
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| 365 | # define FRAME_CMD(x) ((x) << 28) |
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| 366 | /* |
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| 367 | * x=0: tmz_begin |
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| 368 | * x=1: tmz_end |
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| 369 | */ |
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| 370 | #define PACKET3_SET_RESOURCES 0xA0 |
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| 371 | /* 1. header |
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| 372 | * 2. CONTROL |
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| 373 | * 3. QUEUE_MASK_LO [31:0] |
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| 374 | * 4. QUEUE_MASK_HI [31:0] |
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| 375 | * 5. GWS_MASK_LO [31:0] |
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| 376 | * 6. GWS_MASK_HI [31:0] |
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| 377 | * 7. OAC_MASK [15:0] |
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| 378 | * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] |
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| 379 | */ |
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| 380 | # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) |
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| 381 | # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) |
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| 382 | # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) |
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| 383 | #define PACKET3_MAP_QUEUES 0xA2 |
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| 384 | /* 1. header |
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| 385 | * 2. CONTROL |
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| 386 | * 3. CONTROL2 |
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| 387 | * 4. MQD_ADDR_LO [31:0] |
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| 388 | * 5. MQD_ADDR_HI [31:0] |
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| 389 | * 6. WPTR_ADDR_LO [31:0] |
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| 390 | * 7. WPTR_ADDR_HI [31:0] |
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| 391 | */ |
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| 392 | /* CONTROL */ |
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| 393 | # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) |
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| 394 | # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) |
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| 395 | # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) |
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| 396 | # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) |
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| 397 | # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) |
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| 398 | # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) |
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| 399 | /* CONTROL2 */ |
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| 400 | # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) |
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| 401 | # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) |
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| 402 | # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 26) |
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| 403 | # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 29) |
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| 404 | # define PACKET3_MAP_QUEUES_ME(x) ((x) << 31) |
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| 405 | #define PACKET3_UNMAP_QUEUES 0xA3 |
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| 406 | /* 1. header |
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| 407 | * 2. CONTROL |
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| 408 | * 3. CONTROL2 |
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| 409 | * 4. CONTROL3 |
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| 410 | * 5. CONTROL4 |
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| 411 | * 6. CONTROL5 |
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| 412 | */ |
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| 413 | /* CONTROL */ |
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| 414 | # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) |
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| 415 | /* 0 - PREEMPT_QUEUES |
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| 416 | * 1 - RESET_QUEUES |
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| 417 | * 2 - DISABLE_PROCESS_QUEUES |
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| 418 | * 3 - PREEMPT_QUEUES_NO_UNMAP |
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| 419 | */ |
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| 420 | # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) |
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| 421 | # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) |
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| 422 | # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) |
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| 423 | /* CONTROL2a */ |
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| 424 | # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) |
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| 425 | /* CONTROL2b */ |
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| 426 | # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) |
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| 427 | /* CONTROL3a */ |
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| 428 | # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) |
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| 429 | /* CONTROL3b */ |
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| 430 | # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) |
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| 431 | /* CONTROL4 */ |
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| 432 | # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) |
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| 433 | /* CONTROL5 */ |
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| 434 | # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) |
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| 435 | #define PACKET3_QUERY_STATUS 0xA4 |
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| 436 | /* 1. header |
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| 437 | * 2. CONTROL |
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| 438 | * 3. CONTROL2 |
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| 439 | * 4. ADDR_LO [31:0] |
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| 440 | * 5. ADDR_HI [31:0] |
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| 441 | * 6. DATA_LO [31:0] |
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| 442 | * 7. DATA_HI [31:0] |
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| 443 | */ |
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| 444 | /* CONTROL */ |
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| 445 | # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) |
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| 446 | # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) |
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| 447 | # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) |
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| 448 | /* CONTROL2a */ |
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| 449 | # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) |
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| 450 | /* CONTROL2b */ |
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| 451 | # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) |
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| 452 | # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) |
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| 453 | |
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| 454 | |
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| 455 | #define VCE_CMD_NO_OP 0x00000000 |
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| 456 | #define VCE_CMD_END 0x00000001 |
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| 457 | #define VCE_CMD_IB 0x00000002 |
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| 458 | #define VCE_CMD_FENCE 0x00000003 |
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| 459 | #define VCE_CMD_TRAP 0x00000004 |
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| 460 | #define VCE_CMD_IB_AUTO 0x00000005 |
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| 461 | #define VCE_CMD_SEMAPHORE 0x00000006 |
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| 462 | |
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| 463 | #define VCE_CMD_IB_VM 0x00000102 |
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| 464 | #define VCE_CMD_WAIT_GE 0x00000106 |
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| 465 | #define VCE_CMD_UPDATE_PTB 0x00000107 |
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| 466 | #define VCE_CMD_FLUSH_TLB 0x00000108 |
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| 467 | |
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| 468 | /* HEVC ENC */ |
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| 469 | #define HEVC_ENC_CMD_NO_OP 0x00000000 |
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| 470 | #define HEVC_ENC_CMD_END 0x00000001 |
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| 471 | #define HEVC_ENC_CMD_FENCE 0x00000003 |
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| 472 | #define HEVC_ENC_CMD_TRAP 0x00000004 |
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| 473 | #define HEVC_ENC_CMD_IB_VM 0x00000102 |
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| 474 | #define HEVC_ENC_CMD_WAIT_GE 0x00000106 |
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| 475 | #define HEVC_ENC_CMD_UPDATE_PTB 0x00000107 |
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| 476 | #define HEVC_ENC_CMD_FLUSH_TLB 0x00000108 |
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| 477 | |
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| 478 | /* mmPA_SC_RASTER_CONFIG mask */ |
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| 479 | #define RB_MAP_PKR0(x) ((x) << 0) |
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| 480 | #define RB_MAP_PKR0_MASK (0x3 << 0) |
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| 481 | #define RB_MAP_PKR1(x) ((x) << 2) |
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| 482 | #define RB_MAP_PKR1_MASK (0x3 << 2) |
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| 483 | #define RB_XSEL2(x) ((x) << 4) |
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| 484 | #define RB_XSEL2_MASK (0x3 << 4) |
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| 485 | #define RB_XSEL (1 << 6) |
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| 486 | #define RB_YSEL (1 << 7) |
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| 487 | #define PKR_MAP(x) ((x) << 8) |
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| 488 | #define PKR_MAP_MASK (0x3 << 8) |
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| 489 | #define PKR_XSEL(x) ((x) << 10) |
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| 490 | #define PKR_XSEL_MASK (0x3 << 10) |
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| 491 | #define PKR_YSEL(x) ((x) << 12) |
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| 492 | #define PKR_YSEL_MASK (0x3 << 12) |
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| 493 | #define SC_MAP(x) ((x) << 16) |
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| 494 | #define SC_MAP_MASK (0x3 << 16) |
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| 495 | #define SC_XSEL(x) ((x) << 18) |
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| 496 | #define SC_XSEL_MASK (0x3 << 18) |
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| 497 | #define SC_YSEL(x) ((x) << 20) |
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| 498 | #define SC_YSEL_MASK (0x3 << 20) |
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| 499 | #define SE_MAP(x) ((x) << 24) |
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| 500 | #define SE_MAP_MASK (0x3 << 24) |
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| 501 | #define SE_XSEL(x) ((x) << 26) |
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| 502 | #define SE_XSEL_MASK (0x3 << 26) |
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| 503 | #define SE_YSEL(x) ((x) << 28) |
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| 504 | #define SE_YSEL_MASK (0x3 << 28) |
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| 505 | |
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| 506 | /* mmPA_SC_RASTER_CONFIG_1 mask */ |
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| 507 | #define SE_PAIR_MAP(x) ((x) << 0) |
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| 508 | #define SE_PAIR_MAP_MASK (0x3 << 0) |
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| 509 | #define SE_PAIR_XSEL(x) ((x) << 2) |
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| 510 | #define SE_PAIR_XSEL_MASK (0x3 << 2) |
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| 511 | #define SE_PAIR_YSEL(x) ((x) << 4) |
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| 512 | #define SE_PAIR_YSEL_MASK (0x3 << 4) |
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| 513 | |
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| 514 | #endif |
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| 515 | |
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