1 | /* SPDX-License-Identifier: GPL-2.0 OR MIT */ |
2 | /* |
3 | * Copyright 2014-2022 Advanced Micro Devices, Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | */ |
24 | |
25 | #ifndef F32_MES_PM4_PACKETS_H |
26 | #define F32_MES_PM4_PACKETS_H |
27 | |
28 | #ifndef PM4_MES_HEADER_DEFINED |
29 | #define |
30 | union { |
31 | struct { |
32 | uint32_t : 8; /* < reserved */ |
33 | uint32_t : 8; /* < IT opcode */ |
34 | uint32_t : 14;/* < Number of DWORDS - 1 in the |
35 | * information body |
36 | */ |
37 | uint32_t : 2; /* < packet identifier |
38 | * It should be 3 for type 3 packets |
39 | */ |
40 | }; |
41 | uint32_t ; |
42 | }; |
43 | #endif /* PM4_MES_HEADER_DEFINED */ |
44 | |
45 | /*--------------------MES_SET_RESOURCES--------------------*/ |
46 | |
47 | #ifndef PM4_MES_SET_RESOURCES_DEFINED |
48 | #define PM4_MES_SET_RESOURCES_DEFINED |
49 | enum mes_set_resources_queue_type_enum { |
50 | queue_type__mes_set_resources__kernel_interface_queue_kiq = 0, |
51 | queue_type__mes_set_resources__hsa_interface_queue_hiq = 1, |
52 | queue_type__mes_set_resources__hsa_debug_interface_queue = 4 |
53 | }; |
54 | |
55 | |
56 | struct pm4_mes_set_resources { |
57 | union { |
58 | union PM4_MES_TYPE_3_HEADER ; /* header */ |
59 | uint32_t ordinal1; |
60 | }; |
61 | |
62 | union { |
63 | struct { |
64 | uint32_t vmid_mask:16; |
65 | uint32_t unmap_latency:8; |
66 | uint32_t reserved1:5; |
67 | enum mes_set_resources_queue_type_enum queue_type:3; |
68 | } bitfields2; |
69 | uint32_t ordinal2; |
70 | }; |
71 | |
72 | uint32_t queue_mask_lo; |
73 | uint32_t queue_mask_hi; |
74 | uint32_t gws_mask_lo; |
75 | uint32_t gws_mask_hi; |
76 | |
77 | union { |
78 | struct { |
79 | uint32_t oac_mask:16; |
80 | uint32_t reserved2:16; |
81 | } bitfields7; |
82 | uint32_t ordinal7; |
83 | }; |
84 | |
85 | union { |
86 | struct { |
87 | uint32_t gds_heap_base:6; |
88 | uint32_t reserved3:5; |
89 | uint32_t gds_heap_size:6; |
90 | uint32_t reserved4:15; |
91 | } bitfields8; |
92 | uint32_t ordinal8; |
93 | }; |
94 | |
95 | }; |
96 | #endif |
97 | |
98 | /*--------------------MES_RUN_LIST--------------------*/ |
99 | |
100 | #ifndef PM4_MES_RUN_LIST_DEFINED |
101 | #define PM4_MES_RUN_LIST_DEFINED |
102 | |
103 | struct pm4_mes_runlist { |
104 | union { |
105 | union PM4_MES_TYPE_3_HEADER ; /* header */ |
106 | uint32_t ordinal1; |
107 | }; |
108 | |
109 | union { |
110 | struct { |
111 | uint32_t reserved1:2; |
112 | uint32_t ib_base_lo:30; |
113 | } bitfields2; |
114 | uint32_t ordinal2; |
115 | }; |
116 | |
117 | union { |
118 | struct { |
119 | uint32_t ib_base_hi:16; |
120 | uint32_t reserved2:16; |
121 | } bitfields3; |
122 | uint32_t ordinal3; |
123 | }; |
124 | |
125 | union { |
126 | struct { |
127 | uint32_t ib_size:20; |
128 | uint32_t chain:1; |
129 | uint32_t offload_polling:1; |
130 | uint32_t reserved2:1; |
131 | uint32_t valid:1; |
132 | uint32_t process_cnt:4; |
133 | uint32_t reserved3:4; |
134 | } bitfields4; |
135 | uint32_t ordinal4; |
136 | }; |
137 | |
138 | }; |
139 | #endif |
140 | |
141 | /*--------------------MES_MAP_PROCESS--------------------*/ |
142 | |
143 | #ifndef PM4_MES_MAP_PROCESS_DEFINED |
144 | #define PM4_MES_MAP_PROCESS_DEFINED |
145 | |
146 | struct pm4_mes_map_process { |
147 | union { |
148 | union PM4_MES_TYPE_3_HEADER ; /* header */ |
149 | uint32_t ordinal1; |
150 | }; |
151 | |
152 | union { |
153 | struct { |
154 | uint32_t pasid:16; |
155 | uint32_t reserved1:8; |
156 | uint32_t diq_enable:1; |
157 | uint32_t process_quantum:7; |
158 | } bitfields2; |
159 | uint32_t ordinal2; |
160 | }; |
161 | |
162 | union { |
163 | struct { |
164 | uint32_t page_table_base:28; |
165 | uint32_t reserved3:4; |
166 | } bitfields3; |
167 | uint32_t ordinal3; |
168 | }; |
169 | |
170 | uint32_t reserved; |
171 | |
172 | uint32_t sh_mem_bases; |
173 | uint32_t sh_mem_config; |
174 | uint32_t sh_mem_ape1_base; |
175 | uint32_t sh_mem_ape1_limit; |
176 | |
177 | uint32_t sh_hidden_private_base_vmid; |
178 | |
179 | uint32_t reserved2; |
180 | uint32_t reserved3; |
181 | |
182 | uint32_t gds_addr_lo; |
183 | uint32_t gds_addr_hi; |
184 | |
185 | union { |
186 | struct { |
187 | uint32_t num_gws:6; |
188 | uint32_t reserved4:2; |
189 | uint32_t num_oac:4; |
190 | uint32_t reserved5:4; |
191 | uint32_t gds_size:6; |
192 | uint32_t num_queues:10; |
193 | } bitfields10; |
194 | uint32_t ordinal10; |
195 | }; |
196 | |
197 | uint32_t completion_signal_lo; |
198 | uint32_t completion_signal_hi; |
199 | |
200 | }; |
201 | |
202 | #endif |
203 | |
204 | /*--------------------MES_MAP_QUEUES--------------------*/ |
205 | |
206 | #ifndef PM4_MES_MAP_QUEUES_VI_DEFINED |
207 | #define PM4_MES_MAP_QUEUES_VI_DEFINED |
208 | enum mes_map_queues_queue_sel_vi_enum { |
209 | queue_sel__mes_map_queues__map_to_specified_queue_slots_vi = 0, |
210 | queue_sel__mes_map_queues__map_to_hws_determined_queue_slots_vi = 1 |
211 | }; |
212 | |
213 | enum mes_map_queues_queue_type_vi_enum { |
214 | queue_type__mes_map_queues__normal_compute_vi = 0, |
215 | queue_type__mes_map_queues__debug_interface_queue_vi = 1, |
216 | queue_type__mes_map_queues__normal_latency_static_queue_vi = 2, |
217 | queue_type__mes_map_queues__low_latency_static_queue_vi = 3 |
218 | }; |
219 | |
220 | enum mes_map_queues_engine_sel_vi_enum { |
221 | engine_sel__mes_map_queues__compute_vi = 0, |
222 | engine_sel__mes_map_queues__sdma0_vi = 2, |
223 | engine_sel__mes_map_queues__sdma1_vi = 3 |
224 | }; |
225 | |
226 | |
227 | struct pm4_mes_map_queues { |
228 | union { |
229 | union PM4_MES_TYPE_3_HEADER ; /* header */ |
230 | uint32_t ordinal1; |
231 | }; |
232 | |
233 | union { |
234 | struct { |
235 | uint32_t reserved1:4; |
236 | enum mes_map_queues_queue_sel_vi_enum queue_sel:2; |
237 | uint32_t reserved2:15; |
238 | enum mes_map_queues_queue_type_vi_enum queue_type:3; |
239 | uint32_t reserved3:2; |
240 | enum mes_map_queues_engine_sel_vi_enum engine_sel:3; |
241 | uint32_t num_queues:3; |
242 | } bitfields2; |
243 | uint32_t ordinal2; |
244 | }; |
245 | |
246 | union { |
247 | struct { |
248 | uint32_t reserved3:1; |
249 | uint32_t check_disable:1; |
250 | uint32_t doorbell_offset:21; |
251 | uint32_t reserved4:3; |
252 | uint32_t queue:6; |
253 | } bitfields3; |
254 | uint32_t ordinal3; |
255 | }; |
256 | |
257 | uint32_t mqd_addr_lo; |
258 | uint32_t mqd_addr_hi; |
259 | uint32_t wptr_addr_lo; |
260 | uint32_t wptr_addr_hi; |
261 | }; |
262 | #endif |
263 | |
264 | /*--------------------MES_QUERY_STATUS--------------------*/ |
265 | |
266 | #ifndef PM4_MES_QUERY_STATUS_DEFINED |
267 | #define PM4_MES_QUERY_STATUS_DEFINED |
268 | enum mes_query_status_interrupt_sel_enum { |
269 | interrupt_sel__mes_query_status__completion_status = 0, |
270 | interrupt_sel__mes_query_status__process_status = 1, |
271 | interrupt_sel__mes_query_status__queue_status = 2 |
272 | }; |
273 | |
274 | enum mes_query_status_command_enum { |
275 | command__mes_query_status__interrupt_only = 0, |
276 | command__mes_query_status__fence_only_immediate = 1, |
277 | command__mes_query_status__fence_only_after_write_ack = 2, |
278 | command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3 |
279 | }; |
280 | |
281 | enum mes_query_status_engine_sel_enum { |
282 | engine_sel__mes_query_status__compute = 0, |
283 | engine_sel__mes_query_status__sdma0_queue = 2, |
284 | engine_sel__mes_query_status__sdma1_queue = 3 |
285 | }; |
286 | |
287 | struct pm4_mes_query_status { |
288 | union { |
289 | union PM4_MES_TYPE_3_HEADER ; /* header */ |
290 | uint32_t ordinal1; |
291 | }; |
292 | |
293 | union { |
294 | struct { |
295 | uint32_t context_id:28; |
296 | enum mes_query_status_interrupt_sel_enum |
297 | interrupt_sel:2; |
298 | enum mes_query_status_command_enum command:2; |
299 | } bitfields2; |
300 | uint32_t ordinal2; |
301 | }; |
302 | |
303 | union { |
304 | struct { |
305 | uint32_t pasid:16; |
306 | uint32_t reserved1:16; |
307 | } bitfields3a; |
308 | struct { |
309 | uint32_t reserved2:2; |
310 | uint32_t doorbell_offset:21; |
311 | uint32_t reserved3:2; |
312 | enum mes_query_status_engine_sel_enum engine_sel:3; |
313 | uint32_t reserved4:4; |
314 | } bitfields3b; |
315 | uint32_t ordinal3; |
316 | }; |
317 | |
318 | uint32_t addr_lo; |
319 | uint32_t addr_hi; |
320 | uint32_t data_lo; |
321 | uint32_t data_hi; |
322 | }; |
323 | #endif |
324 | |
325 | /*--------------------MES_UNMAP_QUEUES--------------------*/ |
326 | |
327 | #ifndef PM4_MES_UNMAP_QUEUES_DEFINED |
328 | #define PM4_MES_UNMAP_QUEUES_DEFINED |
329 | enum mes_unmap_queues_action_enum { |
330 | action__mes_unmap_queues__preempt_queues = 0, |
331 | action__mes_unmap_queues__reset_queues = 1, |
332 | action__mes_unmap_queues__disable_process_queues = 2, |
333 | action__mes_unmap_queues__reserved = 3 |
334 | }; |
335 | |
336 | enum mes_unmap_queues_queue_sel_enum { |
337 | queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0, |
338 | queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1, |
339 | queue_sel__mes_unmap_queues__unmap_all_queues = 2, |
340 | queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3 |
341 | }; |
342 | |
343 | enum mes_unmap_queues_engine_sel_enum { |
344 | engine_sel__mes_unmap_queues__compute = 0, |
345 | engine_sel__mes_unmap_queues__sdma0 = 2, |
346 | engine_sel__mes_unmap_queues__sdmal = 3 |
347 | }; |
348 | |
349 | struct pm4_mes_unmap_queues { |
350 | union { |
351 | union PM4_MES_TYPE_3_HEADER ; /* header */ |
352 | uint32_t ordinal1; |
353 | }; |
354 | |
355 | union { |
356 | struct { |
357 | enum mes_unmap_queues_action_enum action:2; |
358 | uint32_t reserved1:2; |
359 | enum mes_unmap_queues_queue_sel_enum queue_sel:2; |
360 | uint32_t reserved2:20; |
361 | enum mes_unmap_queues_engine_sel_enum engine_sel:3; |
362 | uint32_t num_queues:3; |
363 | } bitfields2; |
364 | uint32_t ordinal2; |
365 | }; |
366 | |
367 | union { |
368 | struct { |
369 | uint32_t pasid:16; |
370 | uint32_t reserved3:16; |
371 | } bitfields3a; |
372 | struct { |
373 | uint32_t reserved4:2; |
374 | uint32_t doorbell_offset0:21; |
375 | uint32_t reserved5:9; |
376 | } bitfields3b; |
377 | uint32_t ordinal3; |
378 | }; |
379 | |
380 | union { |
381 | struct { |
382 | uint32_t reserved6:2; |
383 | uint32_t doorbell_offset1:21; |
384 | uint32_t reserved7:9; |
385 | } bitfields4; |
386 | uint32_t ordinal4; |
387 | }; |
388 | |
389 | union { |
390 | struct { |
391 | uint32_t reserved8:2; |
392 | uint32_t doorbell_offset2:21; |
393 | uint32_t reserved9:9; |
394 | } bitfields5; |
395 | uint32_t ordinal5; |
396 | }; |
397 | |
398 | union { |
399 | struct { |
400 | uint32_t reserved10:2; |
401 | uint32_t doorbell_offset3:21; |
402 | uint32_t reserved11:9; |
403 | } bitfields6; |
404 | uint32_t ordinal6; |
405 | }; |
406 | }; |
407 | #endif |
408 | |
409 | #ifndef PM4_MEC_RELEASE_MEM_DEFINED |
410 | #define PM4_MEC_RELEASE_MEM_DEFINED |
411 | enum RELEASE_MEM_event_index_enum { |
412 | event_index___release_mem__end_of_pipe = 5, |
413 | event_index___release_mem__shader_done = 6 |
414 | }; |
415 | |
416 | enum RELEASE_MEM_cache_policy_enum { |
417 | cache_policy___release_mem__lru = 0, |
418 | cache_policy___release_mem__stream = 1, |
419 | cache_policy___release_mem__bypass = 2 |
420 | }; |
421 | |
422 | enum RELEASE_MEM_dst_sel_enum { |
423 | dst_sel___release_mem__memory_controller = 0, |
424 | dst_sel___release_mem__tc_l2 = 1, |
425 | dst_sel___release_mem__queue_write_pointer_register = 2, |
426 | dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3 |
427 | }; |
428 | |
429 | enum RELEASE_MEM_int_sel_enum { |
430 | int_sel___release_mem__none = 0, |
431 | int_sel___release_mem__send_interrupt_only = 1, |
432 | int_sel___release_mem__send_interrupt_after_write_confirm = 2, |
433 | int_sel___release_mem__send_data_after_write_confirm = 3 |
434 | }; |
435 | |
436 | enum RELEASE_MEM_data_sel_enum { |
437 | data_sel___release_mem__none = 0, |
438 | data_sel___release_mem__send_32_bit_low = 1, |
439 | data_sel___release_mem__send_64_bit_data = 2, |
440 | data_sel___release_mem__send_gpu_clock_counter = 3, |
441 | data_sel___release_mem__send_cp_perfcounter_hi_lo = 4, |
442 | data_sel___release_mem__store_gds_data_to_memory = 5 |
443 | }; |
444 | |
445 | struct pm4_mec_release_mem { |
446 | union { |
447 | union PM4_MES_TYPE_3_HEADER ; /*header */ |
448 | unsigned int ordinal1; |
449 | }; |
450 | |
451 | union { |
452 | struct { |
453 | unsigned int event_type:6; |
454 | unsigned int reserved1:2; |
455 | enum RELEASE_MEM_event_index_enum event_index:4; |
456 | unsigned int tcl1_vol_action_ena:1; |
457 | unsigned int tc_vol_action_ena:1; |
458 | unsigned int reserved2:1; |
459 | unsigned int tc_wb_action_ena:1; |
460 | unsigned int tcl1_action_ena:1; |
461 | unsigned int tc_action_ena:1; |
462 | unsigned int reserved3:6; |
463 | unsigned int atc:1; |
464 | enum RELEASE_MEM_cache_policy_enum cache_policy:2; |
465 | unsigned int reserved4:5; |
466 | } bitfields2; |
467 | unsigned int ordinal2; |
468 | }; |
469 | |
470 | union { |
471 | struct { |
472 | unsigned int reserved5:16; |
473 | enum RELEASE_MEM_dst_sel_enum dst_sel:2; |
474 | unsigned int reserved6:6; |
475 | enum RELEASE_MEM_int_sel_enum int_sel:3; |
476 | unsigned int reserved7:2; |
477 | enum RELEASE_MEM_data_sel_enum data_sel:3; |
478 | } bitfields3; |
479 | unsigned int ordinal3; |
480 | }; |
481 | |
482 | union { |
483 | struct { |
484 | unsigned int reserved8:2; |
485 | unsigned int address_lo_32b:30; |
486 | } bitfields4; |
487 | struct { |
488 | unsigned int reserved9:3; |
489 | unsigned int address_lo_64b:29; |
490 | } bitfields5; |
491 | unsigned int ordinal4; |
492 | }; |
493 | |
494 | unsigned int address_hi; |
495 | |
496 | unsigned int data_lo; |
497 | |
498 | unsigned int data_hi; |
499 | }; |
500 | #endif |
501 | |
502 | enum { |
503 | CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014 |
504 | }; |
505 | |
506 | #endif |
507 | |