| 1 | /* |
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| 2 | * Copyright 2017 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | * Authors: AMD |
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| 23 | * |
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| 24 | */ |
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| 25 | #ifndef __DC_FEATURES_H__ |
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| 26 | #define __DC_FEATURES_H__ |
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| 27 | |
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| 28 | // local features |
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| 29 | #define DC__PRESENT 1 |
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| 30 | #define DC__PRESENT__1 1 |
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| 31 | #define DC__NUM_DPP 4 |
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| 32 | |
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| 33 | /** |
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| 34 | * @DC__VOLTAGE_STATES: |
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| 35 | * |
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| 36 | * Define the maximum amount of states supported by the ASIC. Every ASIC has a |
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| 37 | * specific number of states; this macro defines the maximum number of states. |
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| 38 | */ |
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| 39 | #define DC__VOLTAGE_STATES 20 |
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| 40 | #define DC__NUM_DPP__4 1 |
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| 41 | #define DC__NUM_DPP__0_PRESENT 1 |
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| 42 | #define DC__NUM_DPP__1_PRESENT 1 |
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| 43 | #define DC__NUM_DPP__2_PRESENT 1 |
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| 44 | #define DC__NUM_DPP__3_PRESENT 1 |
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| 45 | #define DC__NUM_DPP__MAX 8 |
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| 46 | #define DC__NUM_DPP__MAX__8 1 |
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| 47 | #define DC__PIPE_10BIT 0 |
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| 48 | #define DC__PIPE_10BIT__0 1 |
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| 49 | #define DC__PIPE_10BIT__MAX 1 |
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| 50 | #define DC__PIPE_10BIT__MAX__1 1 |
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| 51 | #define DC__NUM_OPP 4 |
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| 52 | #define DC__NUM_OPP__4 1 |
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| 53 | #define DC__NUM_OPP__0_PRESENT 1 |
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| 54 | #define DC__NUM_OPP__1_PRESENT 1 |
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| 55 | #define DC__NUM_OPP__2_PRESENT 1 |
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| 56 | #define DC__NUM_OPP__3_PRESENT 1 |
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| 57 | #define DC__NUM_OPP__MAX 6 |
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| 58 | #define DC__NUM_OPP__MAX__6 1 |
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| 59 | #define DC__NUM_DSC 0 |
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| 60 | #define DC__NUM_DSC__0 1 |
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| 61 | #define DC__NUM_DSC__MAX 6 |
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| 62 | #define DC__NUM_DSC__MAX__6 1 |
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| 63 | #define DC__NUM_ABM 1 |
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| 64 | #define DC__NUM_ABM__1 1 |
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| 65 | #define DC__NUM_ABM__0_PRESENT 1 |
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| 66 | #define DC__NUM_ABM__MAX 2 |
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| 67 | #define DC__NUM_ABM__MAX__2 1 |
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| 68 | #define DC__ODM_PRESENT 0 |
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| 69 | #define DC__ODM_PRESENT__0 1 |
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| 70 | #define DC__NUM_OTG 4 |
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| 71 | #define DC__NUM_OTG__4 1 |
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| 72 | #define DC__NUM_OTG__0_PRESENT 1 |
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| 73 | #define DC__NUM_OTG__1_PRESENT 1 |
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| 74 | #define DC__NUM_OTG__2_PRESENT 1 |
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| 75 | #define DC__NUM_OTG__3_PRESENT 1 |
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| 76 | #define DC__NUM_OTG__MAX 6 |
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| 77 | #define DC__NUM_OTG__MAX__6 1 |
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| 78 | #define DC__NUM_DWB 2 |
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| 79 | #define DC__NUM_DWB__2 1 |
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| 80 | #define DC__NUM_DWB__0_PRESENT 1 |
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| 81 | #define DC__NUM_DWB__1_PRESENT 1 |
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| 82 | #define DC__NUM_DWB__MAX 2 |
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| 83 | #define DC__NUM_DWB__MAX__2 1 |
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| 84 | #define DC__NUM_DIG 4 |
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| 85 | #define DC__NUM_DIG__4 1 |
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| 86 | #define DC__NUM_DIG__0_PRESENT 1 |
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| 87 | #define DC__NUM_DIG__1_PRESENT 1 |
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| 88 | #define DC__NUM_DIG__2_PRESENT 1 |
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| 89 | #define DC__NUM_DIG__3_PRESENT 1 |
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| 90 | #define DC__NUM_DIG__MAX 6 |
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| 91 | #define DC__NUM_DIG__MAX__6 1 |
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| 92 | #define DC__NUM_AUX 4 |
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| 93 | #define DC__NUM_AUX__4 1 |
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| 94 | #define DC__NUM_AUX__0_PRESENT 1 |
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| 95 | #define DC__NUM_AUX__1_PRESENT 1 |
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| 96 | #define DC__NUM_AUX__2_PRESENT 1 |
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| 97 | #define DC__NUM_AUX__3_PRESENT 1 |
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| 98 | #define DC__NUM_AUX__MAX 6 |
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| 99 | #define DC__NUM_AUX__MAX__6 1 |
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| 100 | #define DC__NUM_AUDIO_STREAMS 4 |
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| 101 | #define DC__NUM_AUDIO_STREAMS__4 1 |
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| 102 | #define DC__NUM_AUDIO_STREAMS__0_PRESENT 1 |
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| 103 | #define DC__NUM_AUDIO_STREAMS__1_PRESENT 1 |
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| 104 | #define DC__NUM_AUDIO_STREAMS__2_PRESENT 1 |
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| 105 | #define DC__NUM_AUDIO_STREAMS__3_PRESENT 1 |
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| 106 | #define DC__NUM_AUDIO_STREAMS__MAX 8 |
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| 107 | #define DC__NUM_AUDIO_STREAMS__MAX__8 1 |
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| 108 | #define DC__NUM_AUDIO_ENDPOINTS 6 |
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| 109 | #define DC__NUM_AUDIO_ENDPOINTS__6 1 |
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| 110 | #define DC__NUM_AUDIO_ENDPOINTS__0_PRESENT 1 |
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| 111 | #define DC__NUM_AUDIO_ENDPOINTS__1_PRESENT 1 |
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| 112 | #define DC__NUM_AUDIO_ENDPOINTS__2_PRESENT 1 |
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| 113 | #define DC__NUM_AUDIO_ENDPOINTS__3_PRESENT 1 |
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| 114 | #define DC__NUM_AUDIO_ENDPOINTS__4_PRESENT 1 |
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| 115 | #define DC__NUM_AUDIO_ENDPOINTS__5_PRESENT 1 |
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| 116 | #define DC__NUM_AUDIO_ENDPOINTS__MAX 8 |
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| 117 | #define DC__NUM_AUDIO_ENDPOINTS__MAX__8 1 |
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| 118 | #define DC__NUM_AUDIO_INPUT_STREAMS 0 |
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| 119 | #define DC__NUM_AUDIO_INPUT_STREAMS__0 1 |
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| 120 | #define DC__NUM_AUDIO_INPUT_STREAMS__MAX 8 |
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| 121 | #define DC__NUM_AUDIO_INPUT_STREAMS__MAX__8 1 |
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| 122 | #define DC__NUM_AUDIO_INPUT_ENDPOINTS 0 |
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| 123 | #define DC__NUM_AUDIO_INPUT_ENDPOINTS__0 1 |
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| 124 | #define DC__NUM_AUDIO_INPUT_ENDPOINTS__MAX 8 |
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| 125 | #define DC__NUM_AUDIO_INPUT_ENDPOINTS__MAX__8 1 |
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| 126 | #define DC__NUM_CURSOR 1 |
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| 127 | #define DC__NUM_CURSOR__1 1 |
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| 128 | #define DC__NUM_CURSOR__0_PRESENT 1 |
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| 129 | #define DC__NUM_CURSOR__MAX 2 |
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| 130 | #define DC__NUM_CURSOR__MAX__2 1 |
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| 131 | #define DC__DIGITAL_BYPASS_PRESENT 0 |
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| 132 | #define DC__DIGITAL_BYPASS_PRESENT__0 1 |
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| 133 | #define DC__HCID_HWMAJVER 1 |
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| 134 | #define DC__HCID_HWMAJVER__1 1 |
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| 135 | #define DC__HCID_HWMINVER 0 |
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| 136 | #define DC__HCID_HWMINVER__0 1 |
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| 137 | #define DC__HCID_HWREV 0 |
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| 138 | #define DC__HCID_HWREV__0 1 |
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| 139 | #define DC__ROMSTRAP_PRESENT 0 |
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| 140 | #define DC__ROMSTRAP_PRESENT__0 1 |
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| 141 | #define DC__NUM_RBBMIF_DECODES 30 |
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| 142 | #define DC__NUM_RBBMIF_DECODES__30 1 |
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| 143 | #define DC__NUM_DBG_REGS 36 |
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| 144 | #define DC__NUM_DBG_REGS__36 1 |
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| 145 | #define DC__NUM_PIPES_UNDERLAY 0 |
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| 146 | #define DC__NUM_PIPES_UNDERLAY__0 1 |
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| 147 | #define DC__NUM_PIPES_UNDERLAY__MAX 2 |
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| 148 | #define DC__NUM_PIPES_UNDERLAY__MAX__2 1 |
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| 149 | #define DC__NUM_VCE_ENGINE 1 |
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| 150 | #define DC__NUM_VCE_ENGINE__1 1 |
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| 151 | #define DC__NUM_VCE_ENGINE__0_PRESENT 1 |
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| 152 | #define DC__NUM_VCE_ENGINE__MAX 2 |
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| 153 | #define DC__NUM_VCE_ENGINE__MAX__2 1 |
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| 154 | #define DC__OTG_EXTERNAL_SYNC_PRESENT 0 |
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| 155 | #define DC__OTG_EXTERNAL_SYNC_PRESENT__0 1 |
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| 156 | #define DC__OTG_CRC_PRESENT 1 |
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| 157 | #define DC__OTG_CRC_PRESENT__1 1 |
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| 158 | #define DC__VIP_PRESENT 0 |
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| 159 | #define DC__VIP_PRESENT__0 1 |
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| 160 | #define DC__DTMTEST_PRESENT 0 |
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| 161 | #define DC__DTMTEST_PRESENT__0 1 |
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| 162 | #define DC__POWER_GATE_PRESENT 1 |
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| 163 | #define DC__POWER_GATE_PRESENT__1 1 |
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| 164 | #define DC__MEM_PG 1 |
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| 165 | #define DC__MEM_PG__1 1 |
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| 166 | #define DC__FMT_SRC_SEL_PRESENT 0 |
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| 167 | #define DC__FMT_SRC_SEL_PRESENT__0 1 |
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| 168 | #define DC__DIG_FEATURES__HDMI_PRESENT 1 |
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| 169 | #define DC__DIG_FEATURES__HDMI_PRESENT__1 1 |
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| 170 | #define DC__DIG_FEATURES__DP_PRESENT 1 |
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| 171 | #define DC__DIG_FEATURES__DP_PRESENT__1 1 |
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| 172 | #define DC__DIG_FEATURES__DP_MST_PRESENT 1 |
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| 173 | #define DC__DIG_FEATURES__DP_MST_PRESENT__1 1 |
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| 174 | #define DC__DIG_LP_FEATURES__HDMI_PRESENT 0 |
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| 175 | #define DC__DIG_LP_FEATURES__HDMI_PRESENT__0 1 |
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| 176 | #define DC__DIG_LP_FEATURES__DP_PRESENT 1 |
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| 177 | #define DC__DIG_LP_FEATURES__DP_PRESENT__1 1 |
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| 178 | #define DC__DIG_LP_FEATURES__DP_MST_PRESENT 0 |
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| 179 | #define DC__DIG_LP_FEATURES__DP_MST_PRESENT__0 1 |
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| 180 | #define DC__DIG_RESYNC_FIFO_SIZE 14 |
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| 181 | #define DC__DIG_RESYNC_FIFO_SIZE__14 1 |
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| 182 | #define DC__DIG_RESYNC_FIFO_SIZE__0_PRESENT 1 |
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| 183 | #define DC__DIG_RESYNC_FIFO_SIZE__1_PRESENT 1 |
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| 184 | #define DC__DIG_RESYNC_FIFO_SIZE__2_PRESENT 1 |
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| 185 | #define DC__DIG_RESYNC_FIFO_SIZE__3_PRESENT 1 |
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| 186 | #define DC__DIG_RESYNC_FIFO_SIZE__4_PRESENT 1 |
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| 187 | #define DC__DIG_RESYNC_FIFO_SIZE__5_PRESENT 1 |
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| 188 | #define DC__DIG_RESYNC_FIFO_SIZE__6_PRESENT 1 |
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| 189 | #define DC__DIG_RESYNC_FIFO_SIZE__7_PRESENT 1 |
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| 190 | #define DC__DIG_RESYNC_FIFO_SIZE__8_PRESENT 1 |
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| 191 | #define DC__DIG_RESYNC_FIFO_SIZE__9_PRESENT 1 |
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| 192 | #define DC__DIG_RESYNC_FIFO_SIZE__10_PRESENT 1 |
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| 193 | #define DC__DIG_RESYNC_FIFO_SIZE__11_PRESENT 1 |
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| 194 | #define DC__DIG_RESYNC_FIFO_SIZE__12_PRESENT 1 |
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| 195 | #define DC__DIG_RESYNC_FIFO_SIZE__13_PRESENT 1 |
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| 196 | #define DC__DIG_RESYNC_FIFO_SIZE__MAX 16 |
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| 197 | #define DC__DIG_RESYNC_FIFO_SIZE__MAX__16 1 |
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| 198 | #define DC__DAC_RESYNC_FIFO_SIZE 12 |
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| 199 | #define DC__DAC_RESYNC_FIFO_SIZE__12 1 |
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| 200 | #define DC__DAC_RESYNC_FIFO_SIZE__0_PRESENT 1 |
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| 201 | #define DC__DAC_RESYNC_FIFO_SIZE__1_PRESENT 1 |
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| 202 | #define DC__DAC_RESYNC_FIFO_SIZE__2_PRESENT 1 |
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| 203 | #define DC__DAC_RESYNC_FIFO_SIZE__3_PRESENT 1 |
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| 204 | #define DC__DAC_RESYNC_FIFO_SIZE__4_PRESENT 1 |
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| 205 | #define DC__DAC_RESYNC_FIFO_SIZE__5_PRESENT 1 |
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| 206 | #define DC__DAC_RESYNC_FIFO_SIZE__6_PRESENT 1 |
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| 207 | #define DC__DAC_RESYNC_FIFO_SIZE__7_PRESENT 1 |
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| 208 | #define DC__DAC_RESYNC_FIFO_SIZE__8_PRESENT 1 |
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| 209 | #define DC__DAC_RESYNC_FIFO_SIZE__9_PRESENT 1 |
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| 210 | #define DC__DAC_RESYNC_FIFO_SIZE__10_PRESENT 1 |
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| 211 | #define DC__DAC_RESYNC_FIFO_SIZE__11_PRESENT 1 |
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| 212 | #define DC__DAC_RESYNC_FIFO_SIZE__MAX 16 |
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| 213 | #define DC__DAC_RESYNC_FIFO_SIZE__MAX__16 1 |
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| 214 | #define DC__DVO_RESYNC_FIFO_SIZE 12 |
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| 215 | #define DC__DVO_RESYNC_FIFO_SIZE__12 1 |
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| 216 | #define DC__DVO_RESYNC_FIFO_SIZE__0_PRESENT 1 |
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| 217 | #define DC__DVO_RESYNC_FIFO_SIZE__1_PRESENT 1 |
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| 218 | #define DC__DVO_RESYNC_FIFO_SIZE__2_PRESENT 1 |
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| 219 | #define DC__DVO_RESYNC_FIFO_SIZE__3_PRESENT 1 |
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| 220 | #define DC__DVO_RESYNC_FIFO_SIZE__4_PRESENT 1 |
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| 221 | #define DC__DVO_RESYNC_FIFO_SIZE__5_PRESENT 1 |
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| 222 | #define DC__DVO_RESYNC_FIFO_SIZE__6_PRESENT 1 |
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| 223 | #define DC__DVO_RESYNC_FIFO_SIZE__7_PRESENT 1 |
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| 224 | #define DC__DVO_RESYNC_FIFO_SIZE__8_PRESENT 1 |
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| 225 | #define DC__DVO_RESYNC_FIFO_SIZE__9_PRESENT 1 |
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| 226 | #define DC__DVO_RESYNC_FIFO_SIZE__10_PRESENT 1 |
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| 227 | #define DC__DVO_RESYNC_FIFO_SIZE__11_PRESENT 1 |
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| 228 | #define DC__DVO_RESYNC_FIFO_SIZE__MAX 16 |
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| 229 | #define DC__DVO_RESYNC_FIFO_SIZE__MAX__16 1 |
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| 230 | #define DC__MEM_CDC_PRESENT 1 |
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| 231 | #define DC__MEM_CDC_PRESENT__1 1 |
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| 232 | #define DC__NUM_HPD 4 |
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| 233 | #define DC__NUM_HPD__4 1 |
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| 234 | #define DC__NUM_HPD__0_PRESENT 1 |
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| 235 | #define DC__NUM_HPD__1_PRESENT 1 |
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| 236 | #define DC__NUM_HPD__2_PRESENT 1 |
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| 237 | #define DC__NUM_HPD__3_PRESENT 1 |
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| 238 | #define DC__NUM_HPD__MAX 6 |
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| 239 | #define DC__NUM_HPD__MAX__6 1 |
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| 240 | #define DC__NUM_DDC_PAIRS 4 |
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| 241 | #define DC__NUM_DDC_PAIRS__4 1 |
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| 242 | #define DC__NUM_DDC_PAIRS__0_PRESENT 1 |
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| 243 | #define DC__NUM_DDC_PAIRS__1_PRESENT 1 |
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| 244 | #define DC__NUM_DDC_PAIRS__2_PRESENT 1 |
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| 245 | #define DC__NUM_DDC_PAIRS__3_PRESENT 1 |
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| 246 | #define DC__NUM_DDC_PAIRS__MAX 6 |
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| 247 | #define DC__NUM_DDC_PAIRS__MAX__6 1 |
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| 248 | #define DC__NUM_AUDIO_PLL 0 |
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| 249 | #define DC__NUM_AUDIO_PLL__0 1 |
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| 250 | #define DC__NUM_AUDIO_PLL__MAX 2 |
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| 251 | #define DC__NUM_AUDIO_PLL__MAX__2 1 |
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| 252 | #define DC__NUM_PIXEL_PLL 1 |
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| 253 | #define DC__NUM_PIXEL_PLL__1 1 |
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| 254 | #define DC__NUM_PIXEL_PLL__0_PRESENT 1 |
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| 255 | #define DC__NUM_PIXEL_PLL__MAX 4 |
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| 256 | #define DC__NUM_PIXEL_PLL__MAX__4 1 |
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| 257 | #define DC__NUM_CASCADED_PLL 0 |
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| 258 | #define DC__NUM_CASCADED_PLL__0 1 |
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| 259 | #define DC__NUM_CASCADED_PLL__MAX 3 |
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| 260 | #define DC__NUM_CASCADED_PLL__MAX__3 1 |
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| 261 | #define DC__PIXCLK_FROM_PHYPLL 1 |
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| 262 | #define DC__PIXCLK_FROM_PHYPLL__1 1 |
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| 263 | #define DC__NB_STUTTER_MODE_PRESENT 0 |
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| 264 | #define DC__NB_STUTTER_MODE_PRESENT__0 1 |
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| 265 | #define DC__I2S0_AND_SPDIF0_PRESENT 0 |
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| 266 | #define DC__I2S0_AND_SPDIF0_PRESENT__0 1 |
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| 267 | #define DC__I2S1_PRESENT 0 |
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| 268 | #define DC__I2S1_PRESENT__0 1 |
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| 269 | #define DC__SPDIF1_PRESENT 0 |
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| 270 | #define DC__SPDIF1_PRESENT__0 1 |
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| 271 | #define DC__DSI_PRESENT 0 |
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| 272 | #define DC__DSI_PRESENT__0 1 |
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| 273 | #define DC__DACA_PRESENT 0 |
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| 274 | #define DC__DACA_PRESENT__0 1 |
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| 275 | #define DC__DACB_PRESENT 0 |
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| 276 | #define DC__DACB_PRESENT__0 1 |
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| 277 | #define DC__NUM_PIPES 4 |
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| 278 | #define DC__NUM_PIPES__4 1 |
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| 279 | #define DC__NUM_PIPES__0_PRESENT 1 |
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| 280 | #define DC__NUM_PIPES__1_PRESENT 1 |
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| 281 | #define DC__NUM_PIPES__2_PRESENT 1 |
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| 282 | #define DC__NUM_PIPES__3_PRESENT 1 |
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| 283 | #define DC__NUM_PIPES__MAX 6 |
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| 284 | #define DC__NUM_PIPES__MAX__6 1 |
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| 285 | #define DC__NUM_DIG_LP 0 |
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| 286 | #define DC__NUM_DIG_LP__0 1 |
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| 287 | #define DC__NUM_DIG_LP__MAX 2 |
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| 288 | #define DC__NUM_DIG_LP__MAX__2 1 |
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| 289 | #define DC__DPDEBUG_PRESENT 0 |
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| 290 | #define DC__DPDEBUG_PRESENT__0 1 |
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| 291 | #define DC__DISPLAY_WB_PRESENT 1 |
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| 292 | #define DC__DISPLAY_WB_PRESENT__1 1 |
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| 293 | #define DC__NUM_CWB 0 |
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| 294 | #define DC__NUM_CWB__0 1 |
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| 295 | #define DC__NUM_CWB__MAX 2 |
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| 296 | #define DC__NUM_CWB__MAX__2 1 |
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| 297 | #define DC__MVP_PRESENT 0 |
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| 298 | #define DC__MVP_PRESENT__0 1 |
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| 299 | #define DC__DVO_PRESENT 0 |
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| 300 | #define DC__DVO_PRESENT__0 1 |
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| 301 | #define DC__ABM_PRESENT 0 |
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| 302 | #define DC__ABM_PRESENT__0 1 |
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| 303 | #define DC__BPHYC_PLL_PRESENT 0 |
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| 304 | #define DC__BPHYC_PLL_PRESENT__0 1 |
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| 305 | #define DC__BPHYC_UNIPHY_PRESENT 0 |
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| 306 | #define DC__BPHYC_UNIPHY_PRESENT__0 1 |
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| 307 | #define DC__PHY_BROADCAST_PRESENT 0 |
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| 308 | #define DC__PHY_BROADCAST_PRESENT__0 1 |
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| 309 | #define DC__NUM_OF_DCRX_SD 0 |
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| 310 | #define DC__NUM_OF_DCRX_SD__0 1 |
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| 311 | #define DC__DVO_17BIT_MAPPING 0 |
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| 312 | #define DC__DVO_17BIT_MAPPING__0 1 |
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| 313 | #define DC__AVSYNC_PRESENT 0 |
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| 314 | #define DC__AVSYNC_PRESENT__0 1 |
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| 315 | #define DC__NUM_OF_DCRX_PORTS 0 |
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| 316 | #define DC__NUM_OF_DCRX_PORTS__0 1 |
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| 317 | #define DC__NUM_OF_DCRX_PORTS__MAX 1 |
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| 318 | #define DC__NUM_OF_DCRX_PORTS__MAX__1 1 |
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| 319 | #define DC__NUM_PHY 4 |
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| 320 | #define DC__NUM_PHY__4 1 |
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| 321 | #define DC__NUM_PHY__0_PRESENT 1 |
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| 322 | #define DC__NUM_PHY__1_PRESENT 1 |
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| 323 | #define DC__NUM_PHY__2_PRESENT 1 |
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| 324 | #define DC__NUM_PHY__3_PRESENT 1 |
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| 325 | #define DC__NUM_PHY__MAX 7 |
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| 326 | #define DC__NUM_PHY__MAX__7 1 |
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| 327 | #define DC__NUM_PHY_LP 0 |
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| 328 | #define DC__NUM_PHY_LP__0 1 |
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| 329 | #define DC__NUM_PHY_LP__MAX 2 |
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| 330 | #define DC__NUM_PHY_LP__MAX__2 1 |
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| 331 | #define DC__SYNC_CELL vid_sync_gf14lpp |
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| 332 | #define DC__SYNC_CELL__VID_SYNC_GF14LPP 1 |
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| 333 | #define DC__USE_NEW_VSS 1 |
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| 334 | #define DC__USE_NEW_VSS__1 1 |
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| 335 | #define DC__SYNC_CELL_DISPCLK_NUM_LATCHES 6 |
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| 336 | #define DC__SYNC_CELL_DISPCLK_NUM_LATCHES__6 1 |
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| 337 | #define DC__SYNC_CELL_DVOCLK_NUM_LATCHES 6 |
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| 338 | #define DC__SYNC_CELL_DVOCLK_NUM_LATCHES__6 1 |
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| 339 | #define DC__SYNC_CELL_PIXCLK_NUM_LATCHES 6 |
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| 340 | #define DC__SYNC_CELL_PIXCLK_NUM_LATCHES__6 1 |
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| 341 | #define DC__SYNC_CELL_SYMCLK_NUM_LATCHES 6 |
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| 342 | #define DC__SYNC_CELL_SYMCLK_NUM_LATCHES__6 1 |
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| 343 | #define DC__SYNC_CELL_DPPCLK_NUM_LATCHES 6 |
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| 344 | #define DC__SYNC_CELL_DPPCLK_NUM_LATCHES__6 1 |
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| 345 | #define DC__SYNC_CELL_DPREFCLK_NUM_LATCHES 6 |
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| 346 | #define DC__SYNC_CELL_DPREFCLK_NUM_LATCHES__6 1 |
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| 347 | #define DC__SYNC_CELL_REFCLK_NUM_LATCHES 6 |
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| 348 | #define DC__SYNC_CELL_REFCLK_NUM_LATCHES__6 1 |
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| 349 | #define DC__SYNC_CELL_PCIE_REFCLK_NUM_LATCHES 6 |
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| 350 | #define DC__SYNC_CELL_PCIE_REFCLK_NUM_LATCHES__6 1 |
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| 351 | #define DC__SYNC_CELL_MVPCLK_NUM_LATCHES 6 |
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| 352 | #define DC__SYNC_CELL_MVPCLK_NUM_LATCHES__6 1 |
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| 353 | #define DC__SYNC_CELL_SCLK_NUM_LATCHES 6 |
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| 354 | #define DC__SYNC_CELL_SCLK_NUM_LATCHES__6 1 |
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| 355 | #define DC__SYNC_CELL_DCEFCLK_NUM_LATCHES 6 |
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| 356 | #define DC__SYNC_CELL_DCEFCLK_NUM_LATCHES__6 1 |
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| 357 | #define DC__SYNC_CELL_AMCLK_NUM_LATCHES 6 |
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| 358 | #define DC__SYNC_CELL_AMCLK_NUM_LATCHES__6 1 |
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| 359 | #define DC__SYNC_CELL_DSICLK_NUM_LATCHES 6 |
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| 360 | #define DC__SYNC_CELL_DSICLK_NUM_LATCHES__6 1 |
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| 361 | #define DC__SYNC_CELL_BYTECLK_NUM_LATCHES 6 |
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| 362 | #define DC__SYNC_CELL_BYTECLK_NUM_LATCHES__6 1 |
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| 363 | #define DC__SYNC_CELL_ESCCLK_NUM_LATCHES 6 |
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| 364 | #define DC__SYNC_CELL_ESCCLK_NUM_LATCHES__6 1 |
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| 365 | #define DC__SYNC_CELL_DB_CLK_NUM_LATCHES 6 |
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| 366 | #define DC__SYNC_CELL_DB_CLK_NUM_LATCHES__6 1 |
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| 367 | #define UNIPHYA_PRESENT 1 |
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| 368 | #define UNIPHYA_PRESENT__1 1 |
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| 369 | #define DC__UNIPHYA_PRESENT 1 |
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| 370 | #define DC__UNIPHYA_PRESENT__1 1 |
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| 371 | #define UNIPHYB_PRESENT 1 |
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| 372 | #define UNIPHYB_PRESENT__1 1 |
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| 373 | #define DC__UNIPHYB_PRESENT 1 |
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| 374 | #define DC__UNIPHYB_PRESENT__1 1 |
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| 375 | #define UNIPHYC_PRESENT 1 |
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| 376 | #define UNIPHYC_PRESENT__1 1 |
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| 377 | #define DC__UNIPHYC_PRESENT 1 |
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| 378 | #define DC__UNIPHYC_PRESENT__1 1 |
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| 379 | #define UNIPHYD_PRESENT 1 |
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| 380 | #define UNIPHYD_PRESENT__1 1 |
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| 381 | #define DC__UNIPHYD_PRESENT 1 |
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| 382 | #define DC__UNIPHYD_PRESENT__1 1 |
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| 383 | #define UNIPHYE_PRESENT 0 |
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| 384 | #define UNIPHYE_PRESENT__0 1 |
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| 385 | #define DC__UNIPHYE_PRESENT 0 |
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| 386 | #define DC__UNIPHYE_PRESENT__0 1 |
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| 387 | #define UNIPHYF_PRESENT 0 |
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| 388 | #define UNIPHYF_PRESENT__0 1 |
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| 389 | #define DC__UNIPHYF_PRESENT 0 |
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| 390 | #define DC__UNIPHYF_PRESENT__0 1 |
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| 391 | #define UNIPHYG_PRESENT 0 |
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| 392 | #define UNIPHYG_PRESENT__0 1 |
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| 393 | #define DC__UNIPHYG_PRESENT 0 |
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| 394 | #define DC__UNIPHYG_PRESENT__0 1 |
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| 395 | #define DC__TMDS_LINK tmds_link_dual |
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| 396 | #define DC__TMDS_LINK__TMDS_LINK_DUAL 1 |
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| 397 | #define DC__WBSCL_PIXBW 8 |
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| 398 | #define DC__WBSCL_PIXBW__8 1 |
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| 399 | #define DC__DWB_CSC_PRESENT 0 |
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| 400 | #define DC__DWB_CSC_PRESENT__0 1 |
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| 401 | #define DC__DWB_LUMA_SCL_PRESENT 0 |
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| 402 | #define DC__DWB_LUMA_SCL_PRESENT__0 1 |
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| 403 | #define DC__DENTIST_INTERFACE_PRESENT 1 |
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| 404 | #define DC__DENTIST_INTERFACE_PRESENT__1 1 |
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| 405 | #define DC__GENERICA_PRESENT 1 |
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| 406 | #define DC__GENERICA_PRESENT__1 1 |
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| 407 | #define DC__GENERICB_PRESENT 1 |
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| 408 | #define DC__GENERICB_PRESENT__1 1 |
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| 409 | #define DC__GENERICC_PRESENT 0 |
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| 410 | #define DC__GENERICC_PRESENT__0 1 |
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| 411 | #define DC__GENERICD_PRESENT 0 |
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| 412 | #define DC__GENERICD_PRESENT__0 1 |
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| 413 | #define DC__GENERICE_PRESENT 0 |
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| 414 | #define DC__GENERICE_PRESENT__0 1 |
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| 415 | #define DC__GENERICF_PRESENT 0 |
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| 416 | #define DC__GENERICF_PRESENT__0 1 |
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| 417 | #define DC__GENERICG_PRESENT 0 |
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| 418 | #define DC__GENERICG_PRESENT__0 1 |
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| 419 | #define DC__UNIPHY_VOLTAGE_MODE 1 |
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| 420 | #define DC__UNIPHY_VOLTAGE_MODE__1 1 |
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| 421 | #define DC__BLON_TYPE dedicated |
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| 422 | #define DC__BLON_TYPE__DEDICATED 1 |
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| 423 | #define DC__UNIPHY_STAGGER_CH_PRESENT 1 |
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| 424 | #define DC__UNIPHY_STAGGER_CH_PRESENT__1 1 |
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| 425 | #define DC__XDMA_PRESENT 0 |
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| 426 | #define DC__XDMA_PRESENT__0 1 |
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| 427 | #define XDMA__PRESENT 0 |
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| 428 | #define XDMA__PRESENT__0 1 |
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| 429 | #define DC__DP_MEM_PG 0 |
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| 430 | #define DC__DP_MEM_PG__0 1 |
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| 431 | #define DP__MEM_PG 0 |
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| 432 | #define DP__MEM_PG__0 1 |
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| 433 | #define DC__AFMT_MEM_PG 0 |
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| 434 | #define DC__AFMT_MEM_PG__0 1 |
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| 435 | #define AFMT__MEM_PG 0 |
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| 436 | #define AFMT__MEM_PG__0 1 |
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| 437 | #define DC__HDMI_MEM_PG 0 |
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| 438 | #define DC__HDMI_MEM_PG__0 1 |
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| 439 | #define HDMI__MEM_PG 0 |
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| 440 | #define HDMI__MEM_PG__0 1 |
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| 441 | #define DC__I2C_MEM_PG 0 |
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| 442 | #define DC__I2C_MEM_PG__0 1 |
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| 443 | #define I2C__MEM_PG 0 |
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| 444 | #define I2C__MEM_PG__0 1 |
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| 445 | #define DC__DSCL_MEM_PG 0 |
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| 446 | #define DC__DSCL_MEM_PG__0 1 |
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| 447 | #define DSCL__MEM_PG 0 |
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| 448 | #define DSCL__MEM_PG__0 1 |
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| 449 | #define DC__CM_MEM_PG 0 |
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| 450 | #define DC__CM_MEM_PG__0 1 |
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| 451 | #define CM__MEM_PG 0 |
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| 452 | #define CM__MEM_PG__0 1 |
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| 453 | #define DC__OBUF_MEM_PG 0 |
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| 454 | #define DC__OBUF_MEM_PG__0 1 |
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| 455 | #define OBUF__MEM_PG 0 |
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| 456 | #define OBUF__MEM_PG__0 1 |
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| 457 | #define DC__WBIF_MEM_PG 1 |
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| 458 | #define DC__WBIF_MEM_PG__1 1 |
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| 459 | #define WBIF__MEM_PG 1 |
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| 460 | #define WBIF__MEM_PG__1 1 |
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| 461 | #define DC__VGA_MEM_PG 0 |
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| 462 | #define DC__VGA_MEM_PG__0 1 |
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| 463 | #define VGA__MEM_PG 0 |
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| 464 | #define VGA__MEM_PG__0 1 |
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| 465 | #define DC__FMT_MEM_PG 0 |
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| 466 | #define DC__FMT_MEM_PG__0 1 |
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| 467 | #define FMT__MEM_PG 0 |
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| 468 | #define FMT__MEM_PG__0 1 |
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| 469 | #define DC__ODM_MEM_PG 0 |
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| 470 | #define DC__ODM_MEM_PG__0 1 |
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| 471 | #define ODM__MEM_PG 0 |
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| 472 | #define ODM__MEM_PG__0 1 |
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| 473 | #define DC__DSI_MEM_PG 0 |
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| 474 | #define DC__DSI_MEM_PG__0 1 |
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| 475 | #define DSI__MEM_PG 0 |
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| 476 | #define DSI__MEM_PG__0 1 |
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| 477 | #define DC__AZ_MEM_PG 1 |
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| 478 | #define DC__AZ_MEM_PG__1 1 |
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| 479 | #define AZ__MEM_PG 1 |
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| 480 | #define AZ__MEM_PG__1 1 |
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| 481 | #define DC__WBSCL_MEM1P1024X64QS_MEM_PG 1 |
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| 482 | #define DC__WBSCL_MEM1P1024X64QS_MEM_PG__1 1 |
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| 483 | #define WBSCL_MEM1P1024X64QS__MEM_PG 1 |
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| 484 | #define WBSCL_MEM1P1024X64QS__MEM_PG__1 1 |
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| 485 | #define DC__WBSCL_MEM1P528X64QS_MEM_PG 1 |
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| 486 | #define DC__WBSCL_MEM1P528X64QS_MEM_PG__1 1 |
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| 487 | #define WBSCL_MEM1P528X64QS__MEM_PG 1 |
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| 488 | #define WBSCL_MEM1P528X64QS__MEM_PG__1 1 |
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| 489 | #define DC__DMCU_MEM1P1024X32BQS_MEM_PG 1 |
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| 490 | #define DC__DMCU_MEM1P1024X32BQS_MEM_PG__1 1 |
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| 491 | #define DMCU_MEM1P1024X32BQS__MEM_PG 1 |
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| 492 | #define DMCU_MEM1P1024X32BQS__MEM_PG__1 1 |
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| 493 | #define DC__HUBBUB_SDP_TAG_INT_MEM_PG 0 |
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| 494 | #define DC__HUBBUB_SDP_TAG_INT_MEM_PG__0 1 |
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| 495 | #define HUBBUB_SDP_TAG_INT__MEM_PG 0 |
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| 496 | #define HUBBUB_SDP_TAG_INT__MEM_PG__0 1 |
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| 497 | #define DC__HUBBUB_SDP_TAG_EXT_MEM_PG 0 |
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| 498 | #define DC__HUBBUB_SDP_TAG_EXT_MEM_PG__0 1 |
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| 499 | #define HUBBUB_SDP_TAG_EXT__MEM_PG 0 |
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| 500 | #define HUBBUB_SDP_TAG_EXT__MEM_PG__0 1 |
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| 501 | #define DC__HUBBUB_RET_ZERO_MEM_PG 0 |
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| 502 | #define DC__HUBBUB_RET_ZERO_MEM_PG__0 1 |
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| 503 | #define HUBBUB_RET_ZERO__MEM_PG 0 |
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| 504 | #define HUBBUB_RET_ZERO__MEM_PG__0 1 |
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| 505 | #define DC__HUBBUB_RET_ROB_MEM_PG 0 |
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| 506 | #define DC__HUBBUB_RET_ROB_MEM_PG__0 1 |
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| 507 | #define HUBBUB_RET_ROB__MEM_PG 0 |
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| 508 | #define HUBBUB_RET_ROB__MEM_PG__0 1 |
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| 509 | #define DC__HUBPRET_CUR_ROB_MEM_PG 0 |
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| 510 | #define DC__HUBPRET_CUR_ROB_MEM_PG__0 1 |
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| 511 | #define HUBPRET_CUR_ROB__MEM_PG 0 |
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| 512 | #define HUBPRET_CUR_ROB__MEM_PG__0 1 |
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| 513 | #define DC__HUBPRET_CUR_CDC_MEM_PG 0 |
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| 514 | #define DC__HUBPRET_CUR_CDC_MEM_PG__0 1 |
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| 515 | #define HUBPRET_CUR_CDC__MEM_PG 0 |
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| 516 | #define HUBPRET_CUR_CDC__MEM_PG__0 1 |
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| 517 | #define DC__HUBPREQ_MPTE_MEM_PG 0 |
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| 518 | #define DC__HUBPREQ_MPTE_MEM_PG__0 1 |
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| 519 | #define HUBPREQ_MPTE__MEM_PG 0 |
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| 520 | #define HUBPREQ_MPTE__MEM_PG__0 1 |
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| 521 | #define DC__HUBPREQ_META_MEM_PG 0 |
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| 522 | #define DC__HUBPREQ_META_MEM_PG__0 1 |
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| 523 | #define HUBPREQ_META__MEM_PG 0 |
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| 524 | #define HUBPREQ_META__MEM_PG__0 1 |
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| 525 | #define DC__HUBPREQ_DPTE_MEM_PG 0 |
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| 526 | #define DC__HUBPREQ_DPTE_MEM_PG__0 1 |
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| 527 | #define HUBPREQ_DPTE__MEM_PG 0 |
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| 528 | #define HUBPREQ_DPTE__MEM_PG__0 1 |
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| 529 | #define DC__HUBPRET_DET_MEM_PG 0 |
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| 530 | #define DC__HUBPRET_DET_MEM_PG__0 1 |
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| 531 | #define HUBPRET_DET__MEM_PG 0 |
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| 532 | #define HUBPRET_DET__MEM_PG__0 1 |
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| 533 | #define DC__HUBPRET_PIX_CDC_MEM_PG 0 |
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| 534 | #define DC__HUBPRET_PIX_CDC_MEM_PG__0 1 |
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| 535 | #define HUBPRET_PIX_CDC__MEM_PG 0 |
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| 536 | #define HUBPRET_PIX_CDC__MEM_PG__0 1 |
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| 537 | #define DC__TOP_BLKS__DCCG 1 |
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| 538 | #define DC__TOP_BLKS__DCHUBBUB 1 |
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| 539 | #define DC__TOP_BLKS__DCHUBP 1 |
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| 540 | #define DC__TOP_BLKS__HDA 1 |
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| 541 | #define DC__TOP_BLKS__DIO 1 |
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| 542 | #define DC__TOP_BLKS__DCIO 1 |
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| 543 | #define DC__TOP_BLKS__DMU 1 |
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| 544 | #define DC__TOP_BLKS__DPP 1 |
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| 545 | #define DC__TOP_BLKS__MPC 1 |
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| 546 | #define DC__TOP_BLKS__OPP 1 |
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| 547 | #define DC__TOP_BLKS__OPTC 1 |
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| 548 | #define DC__TOP_BLKS__MMHUBBUB 1 |
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| 549 | #define DC__TOP_BLKS__WB 1 |
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| 550 | #define DC__TOP_BLKS__MAX 13 |
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| 551 | #define DC__TOP_BLKS__MAX__13 1 |
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| 552 | #define DC__DCHUBP_DPP_SF_PIXEL_CREDITS 9 |
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| 553 | #define DC__DCHUBP_DPP_SF_PIXEL_CREDITS__9 1 |
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| 554 | #define DC__DPP_MPC_SF_PIXEL_CREDITS 9 |
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| 555 | #define DC__DPP_MPC_SF_PIXEL_CREDITS__9 1 |
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| 556 | #define DC__MPC_OPP_SF_PIXEL_CREDITS 8 |
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| 557 | #define DC__MPC_OPP_SF_PIXEL_CREDITS__8 1 |
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| 558 | #define DC__OPP_OPTC_SF_PIXEL_CREDITS 8 |
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| 559 | #define DC__OPP_OPTC_SF_PIXEL_CREDITS__8 1 |
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| 560 | #define DC__SFR_SFT_ROUND_TRIP_DELAY 5 |
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| 561 | #define DC__SFR_SFT_ROUND_TRIP_DELAY__5 1 |
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| 562 | #define DC__REPEATER_PROJECT_MAX 8 |
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| 563 | #define DC__REPEATER_PROJECT_MAX__8 1 |
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| 564 | #define DC__SURFACE_422_CAPABLE 0 |
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| 565 | #define DC__SURFACE_422_CAPABLE__0 1 |
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| 566 | #endif |
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| 567 | |
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