1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_HW_SHARED_H__
27#define __DAL_HW_SHARED_H__
28
29#include "os_types.h"
30#include "fixed31_32.h"
31#include "dc_hw_types.h"
32
33/******************************************************************************
34 * Data types shared between different Virtual HW blocks
35 ******************************************************************************/
36
37#define MAX_AUDIOS 7
38
39/**
40 * @MAX_PIPES:
41 *
42 * Every ASIC support a fixed number of pipes; MAX_PIPES defines a large number
43 * to be used inside loops and for determining array sizes.
44 */
45#define MAX_PIPES 6
46#define MAX_DIG_LINK_ENCODERS 7
47#define MAX_DWB_PIPES 1
48#define MAX_HPO_DP2_ENCODERS 4
49#define MAX_HPO_DP2_LINK_ENCODERS 2
50
51struct gamma_curve {
52 uint32_t offset;
53 uint32_t segments_num;
54};
55
56struct curve_points {
57 struct fixed31_32 x;
58 struct fixed31_32 y;
59 struct fixed31_32 offset;
60 struct fixed31_32 slope;
61
62 uint32_t custom_float_x;
63 uint32_t custom_float_y;
64 uint32_t custom_float_offset;
65 uint32_t custom_float_slope;
66};
67
68struct curve_points3 {
69 struct curve_points red;
70 struct curve_points green;
71 struct curve_points blue;
72};
73
74struct pwl_result_data {
75 struct fixed31_32 red;
76 struct fixed31_32 green;
77 struct fixed31_32 blue;
78
79 struct fixed31_32 delta_red;
80 struct fixed31_32 delta_green;
81 struct fixed31_32 delta_blue;
82
83 uint32_t red_reg;
84 uint32_t green_reg;
85 uint32_t blue_reg;
86
87 uint32_t delta_red_reg;
88 uint32_t delta_green_reg;
89 uint32_t delta_blue_reg;
90};
91
92struct dc_rgb {
93 uint32_t red;
94 uint32_t green;
95 uint32_t blue;
96};
97
98struct tetrahedral_17x17x17 {
99 struct dc_rgb lut0[1229];
100 struct dc_rgb lut1[1228];
101 struct dc_rgb lut2[1228];
102 struct dc_rgb lut3[1228];
103};
104struct tetrahedral_9x9x9 {
105 struct dc_rgb lut0[183];
106 struct dc_rgb lut1[182];
107 struct dc_rgb lut2[182];
108 struct dc_rgb lut3[182];
109};
110
111struct tetrahedral_params {
112 union {
113 struct tetrahedral_17x17x17 tetrahedral_17;
114 struct tetrahedral_9x9x9 tetrahedral_9;
115 };
116 bool use_tetrahedral_9;
117 bool use_12bits;
118
119};
120
121/* arr_curve_points - regamma regions/segments specification
122 * arr_points - beginning and end point specified separately (only one on DCE)
123 * corner_points - beginning and end point for all 3 colors (DCN)
124 * rgb_resulted - final curve
125 */
126struct pwl_params {
127 struct gamma_curve arr_curve_points[34];
128 union {
129 struct curve_points arr_points[2];
130 struct curve_points3 corner_points[2];
131 };
132 struct pwl_result_data rgb_resulted[256 + 3];
133 uint32_t hw_points_num;
134};
135
136/* move to dpp
137 * while we are moving functionality out of opp to dpp to align
138 * HW programming to HW IP, we define these struct in hw_shared
139 * so we can still compile while refactoring
140 */
141
142enum lb_pixel_depth {
143 /* do not change the values because it is used as bit vector */
144 LB_PIXEL_DEPTH_18BPP = 1,
145 LB_PIXEL_DEPTH_24BPP = 2,
146 LB_PIXEL_DEPTH_30BPP = 4,
147 LB_PIXEL_DEPTH_36BPP = 8
148};
149
150enum graphics_csc_adjust_type {
151 GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
152 GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
153 GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */
154};
155
156enum ipp_degamma_mode {
157 IPP_DEGAMMA_MODE_BYPASS,
158 IPP_DEGAMMA_MODE_HW_sRGB,
159 IPP_DEGAMMA_MODE_HW_xvYCC,
160 IPP_DEGAMMA_MODE_USER_PWL
161};
162
163enum gamcor_mode {
164 GAMCOR_MODE_BYPASS,
165 GAMCOR_MODE_RESERVED_1,
166 GAMCOR_MODE_USER_PWL,
167 GAMCOR_MODE_RESERVED_3
168};
169
170enum ipp_output_format {
171 IPP_OUTPUT_FORMAT_12_BIT_FIX,
172 IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
173 IPP_OUTPUT_FORMAT_FLOAT
174};
175
176enum expansion_mode {
177 EXPANSION_MODE_DYNAMIC,
178 EXPANSION_MODE_ZERO
179};
180
181struct default_adjustment {
182 enum lb_pixel_depth lb_color_depth;
183 enum dc_color_space out_color_space;
184 enum dc_color_space in_color_space;
185 enum dc_color_depth color_depth;
186 enum pixel_format surface_pixel_format;
187 enum graphics_csc_adjust_type csc_adjust_type;
188 bool force_hw_default;
189};
190
191
192struct out_csc_color_matrix {
193 enum dc_color_space color_space;
194 uint16_t regval[12];
195};
196
197enum gamut_remap_select {
198 GAMUT_REMAP_BYPASS = 0,
199 GAMUT_REMAP_COEFF,
200 GAMUT_REMAP_COMA_COEFF,
201 GAMUT_REMAP_COMB_COEFF
202};
203
204enum opp_regamma {
205 OPP_REGAMMA_BYPASS = 0,
206 OPP_REGAMMA_SRGB,
207 OPP_REGAMMA_XVYCC,
208 OPP_REGAMMA_USER
209};
210
211enum optc_dsc_mode {
212 OPTC_DSC_DISABLED = 0,
213 OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */
214 OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */
215};
216
217struct dc_bias_and_scale {
218 uint16_t scale_red;
219 uint16_t bias_red;
220 uint16_t scale_green;
221 uint16_t bias_green;
222 uint16_t scale_blue;
223 uint16_t bias_blue;
224};
225
226enum test_pattern_dyn_range {
227 TEST_PATTERN_DYN_RANGE_VESA = 0,
228 TEST_PATTERN_DYN_RANGE_CEA
229};
230
231enum test_pattern_mode {
232 TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
233 TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
234 TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
235 TEST_PATTERN_MODE_VERTICALBARS,
236 TEST_PATTERN_MODE_HORIZONTALBARS,
237 TEST_PATTERN_MODE_SINGLERAMP_RGB,
238 TEST_PATTERN_MODE_DUALRAMP_RGB,
239 TEST_PATTERN_MODE_XR_BIAS_RGB
240};
241
242enum test_pattern_color_format {
243 TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
244 TEST_PATTERN_COLOR_FORMAT_BPC_8,
245 TEST_PATTERN_COLOR_FORMAT_BPC_10,
246 TEST_PATTERN_COLOR_FORMAT_BPC_12
247};
248
249enum controller_dp_test_pattern {
250 CONTROLLER_DP_TEST_PATTERN_D102 = 0,
251 CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
252 CONTROLLER_DP_TEST_PATTERN_PRBS7,
253 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
254 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
255 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
256 CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
257 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
258 CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
259 CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
260 CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
261 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA,
262 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR
263};
264
265enum controller_dp_color_space {
266 CONTROLLER_DP_COLOR_SPACE_RGB,
267 CONTROLLER_DP_COLOR_SPACE_YCBCR601,
268 CONTROLLER_DP_COLOR_SPACE_YCBCR709,
269 CONTROLLER_DP_COLOR_SPACE_UDEFINED
270};
271
272enum dc_lut_mode {
273 LUT_BYPASS,
274 LUT_RAM_A,
275 LUT_RAM_B
276};
277
278/**
279 * speakersToChannels
280 *
281 * @brief
282 * translate speakers to channels
283 *
284 * FL - Front Left
285 * FR - Front Right
286 * RL - Rear Left
287 * RR - Rear Right
288 * RC - Rear Center
289 * FC - Front Center
290 * FLC - Front Left Center
291 * FRC - Front Right Center
292 * RLC - Rear Left Center
293 * RRC - Rear Right Center
294 * LFE - Low Freq Effect
295 *
296 * FC
297 * FLC FRC
298 * FL FR
299 *
300 * LFE
301 * ()
302 *
303 *
304 * RL RR
305 * RLC RRC
306 * RC
307 *
308 * ch 8 7 6 5 4 3 2 1
309 * 0b00000011 - - - - - - FR FL
310 * 0b00000111 - - - - - LFE FR FL
311 * 0b00001011 - - - - FC - FR FL
312 * 0b00001111 - - - - FC LFE FR FL
313 * 0b00010011 - - - RC - - FR FL
314 * 0b00010111 - - - RC - LFE FR FL
315 * 0b00011011 - - - RC FC - FR FL
316 * 0b00011111 - - - RC FC LFE FR FL
317 * 0b00110011 - - RR RL - - FR FL
318 * 0b00110111 - - RR RL - LFE FR FL
319 * 0b00111011 - - RR RL FC - FR FL
320 * 0b00111111 - - RR RL FC LFE FR FL
321 * 0b01110011 - RC RR RL - - FR FL
322 * 0b01110111 - RC RR RL - LFE FR FL
323 * 0b01111011 - RC RR RL FC - FR FL
324 * 0b01111111 - RC RR RL FC LFE FR FL
325 * 0b11110011 RRC RLC RR RL - - FR FL
326 * 0b11110111 RRC RLC RR RL - LFE FR FL
327 * 0b11111011 RRC RLC RR RL FC - FR FL
328 * 0b11111111 RRC RLC RR RL FC LFE FR FL
329 * 0b11000011 FRC FLC - - - - FR FL
330 * 0b11000111 FRC FLC - - - LFE FR FL
331 * 0b11001011 FRC FLC - - FC - FR FL
332 * 0b11001111 FRC FLC - - FC LFE FR FL
333 * 0b11010011 FRC FLC - RC - - FR FL
334 * 0b11010111 FRC FLC - RC - LFE FR FL
335 * 0b11011011 FRC FLC - RC FC - FR FL
336 * 0b11011111 FRC FLC - RC FC LFE FR FL
337 * 0b11110011 FRC FLC RR RL - - FR FL
338 * 0b11110111 FRC FLC RR RL - LFE FR FL
339 * 0b11111011 FRC FLC RR RL FC - FR FL
340 * 0b11111111 FRC FLC RR RL FC LFE FR FL
341 *
342 * @param
343 * speakers - speaker information as it comes from CEA audio block
344 */
345/* translate speakers to channels */
346
347union audio_cea_channels {
348 uint8_t all;
349 struct audio_cea_channels_bits {
350 uint32_t FL:1;
351 uint32_t FR:1;
352 uint32_t LFE:1;
353 uint32_t FC:1;
354 uint32_t RL_RC:1;
355 uint32_t RR:1;
356 uint32_t RC_RLC_FLC:1;
357 uint32_t RRC_FRC:1;
358 } channels;
359};
360
361#endif /* __DAL_HW_SHARED_H__ */
362

source code of linux/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h