1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef MOD_HDCP_H_
27#define MOD_HDCP_H_
28
29#include "os_types.h"
30#include "signal_types.h"
31
32/* Forward Declarations */
33struct mod_hdcp;
34
35#define MAX_NUM_OF_DISPLAYS 6
36#define MAX_NUM_OF_ATTEMPTS 4
37#define MAX_NUM_OF_ERROR_TRACE 10
38
39/* detailed return status */
40enum mod_hdcp_status {
41 MOD_HDCP_STATUS_SUCCESS = 0,
42 MOD_HDCP_STATUS_FAILURE,
43 MOD_HDCP_STATUS_RESET_NEEDED,
44 MOD_HDCP_STATUS_DISPLAY_OUT_OF_BOUND,
45 MOD_HDCP_STATUS_DISPLAY_NOT_FOUND,
46 MOD_HDCP_STATUS_INVALID_STATE,
47 MOD_HDCP_STATUS_NOT_IMPLEMENTED,
48 MOD_HDCP_STATUS_INTERNAL_POLICY_FAILURE,
49 MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE,
50 MOD_HDCP_STATUS_CREATE_PSP_SERVICE_FAILURE,
51 MOD_HDCP_STATUS_DESTROY_PSP_SERVICE_FAILURE,
52 MOD_HDCP_STATUS_HDCP1_CREATE_SESSION_FAILURE,
53 MOD_HDCP_STATUS_HDCP1_DESTROY_SESSION_FAILURE,
54 MOD_HDCP_STATUS_HDCP1_VALIDATE_ENCRYPTION_FAILURE,
55 MOD_HDCP_STATUS_HDCP1_NOT_HDCP_REPEATER,
56 MOD_HDCP_STATUS_HDCP1_NOT_CAPABLE,
57 MOD_HDCP_STATUS_HDCP1_R0_PRIME_PENDING,
58 MOD_HDCP_STATUS_HDCP1_VALIDATE_RX_FAILURE,
59 MOD_HDCP_STATUS_HDCP1_BKSV_REVOKED,
60 MOD_HDCP_STATUS_HDCP1_KSV_LIST_NOT_READY,
61 MOD_HDCP_STATUS_HDCP1_VALIDATE_KSV_LIST_FAILURE,
62 MOD_HDCP_STATUS_HDCP1_KSV_LIST_REVOKED,
63 MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION_FAILURE,
64 MOD_HDCP_STATUS_HDCP1_ENABLE_STREAM_ENCRYPTION_FAILURE,
65 MOD_HDCP_STATUS_HDCP1_MAX_CASCADE_EXCEEDED_FAILURE,
66 MOD_HDCP_STATUS_HDCP1_MAX_DEVS_EXCEEDED_FAILURE,
67 MOD_HDCP_STATUS_HDCP1_DEVICE_COUNT_MISMATCH_FAILURE,
68 MOD_HDCP_STATUS_HDCP1_LINK_INTEGRITY_FAILURE,
69 MOD_HDCP_STATUS_HDCP1_REAUTH_REQUEST_ISSUED,
70 MOD_HDCP_STATUS_HDCP1_LINK_MAINTENANCE_FAILURE,
71 MOD_HDCP_STATUS_HDCP1_INVALID_BKSV,
72 MOD_HDCP_STATUS_DDC_FAILURE, /* TODO: specific errors */
73 MOD_HDCP_STATUS_INVALID_OPERATION,
74 MOD_HDCP_STATUS_HDCP2_NOT_CAPABLE,
75 MOD_HDCP_STATUS_HDCP2_CREATE_SESSION_FAILURE,
76 MOD_HDCP_STATUS_HDCP2_DESTROY_SESSION_FAILURE,
77 MOD_HDCP_STATUS_HDCP2_PREP_AKE_INIT_FAILURE,
78 MOD_HDCP_STATUS_HDCP2_AKE_CERT_PENDING,
79 MOD_HDCP_STATUS_HDCP2_H_PRIME_PENDING,
80 MOD_HDCP_STATUS_HDCP2_PAIRING_INFO_PENDING,
81 MOD_HDCP_STATUS_HDCP2_VALIDATE_AKE_CERT_FAILURE,
82 MOD_HDCP_STATUS_HDCP2_AKE_CERT_REVOKED,
83 MOD_HDCP_STATUS_HDCP2_VALIDATE_H_PRIME_FAILURE,
84 MOD_HDCP_STATUS_HDCP2_VALIDATE_PAIRING_INFO_FAILURE,
85 MOD_HDCP_STATUS_HDCP2_PREP_LC_INIT_FAILURE,
86 MOD_HDCP_STATUS_HDCP2_L_PRIME_PENDING,
87 MOD_HDCP_STATUS_HDCP2_VALIDATE_L_PRIME_FAILURE,
88 MOD_HDCP_STATUS_HDCP2_PREP_EKS_FAILURE,
89 MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE,
90 MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_NOT_READY,
91 MOD_HDCP_STATUS_HDCP2_VALIDATE_RX_ID_LIST_FAILURE,
92 MOD_HDCP_STATUS_HDCP2_RX_ID_LIST_REVOKED,
93 MOD_HDCP_STATUS_HDCP2_ENABLE_STREAM_ENCRYPTION_FAILURE,
94 MOD_HDCP_STATUS_HDCP2_STREAM_READY_PENDING,
95 MOD_HDCP_STATUS_HDCP2_VALIDATE_STREAM_READY_FAILURE,
96 MOD_HDCP_STATUS_HDCP2_PREPARE_STREAM_MANAGEMENT_FAILURE,
97 MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST,
98 MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE,
99 MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE,
100 MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE,
101};
102
103struct mod_hdcp_displayport {
104 uint8_t rev;
105 uint8_t assr_enabled;
106 uint8_t mst_enabled;
107 uint8_t dp2_enabled;
108 uint8_t usb4_enabled;
109};
110
111struct mod_hdcp_hdmi {
112 uint8_t reserved;
113};
114enum mod_hdcp_operation_mode {
115 MOD_HDCP_MODE_OFF,
116 MOD_HDCP_MODE_DEFAULT,
117 MOD_HDCP_MODE_DP
118};
119
120enum mod_hdcp_display_state {
121 MOD_HDCP_DISPLAY_INACTIVE = 0,
122 MOD_HDCP_DISPLAY_ACTIVE,
123 MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED
124};
125
126struct mod_hdcp_psp_caps {
127 uint8_t dtm_v3_supported;
128};
129
130enum mod_hdcp_display_disable_option {
131 MOD_HDCP_DISPLAY_NOT_DISABLE = 0,
132 MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION,
133 MOD_HDCP_DISPLAY_DISABLE_ENCRYPTION,
134};
135
136struct mod_hdcp_atomic_op_i2c {
137 uint8_t address;
138 uint8_t offset;
139 uint8_t *data;
140 uint32_t size;
141};
142
143struct mod_hdcp_atomic_op_aux {
144 uint32_t address;
145 uint8_t *data;
146 uint32_t size;
147};
148
149struct mod_hdcp_ddc {
150 void *handle;
151 struct mod_hdcp_ddc_funcs {
152 bool (*read_i2c)(void *handle,
153 uint32_t address,
154 uint8_t offset,
155 uint8_t *data,
156 uint32_t size);
157 bool (*write_i2c)(void *handle,
158 uint32_t address,
159 const uint8_t *data,
160 uint32_t size);
161 bool (*read_dpcd)(void *handle,
162 uint32_t address,
163 uint8_t *data,
164 uint32_t size);
165 bool (*write_dpcd)(void *handle,
166 uint32_t address,
167 const uint8_t *data,
168 uint32_t size);
169 bool (*atomic_write_poll_read_i2c)(
170 void *handle,
171 const struct mod_hdcp_atomic_op_i2c *write,
172 const struct mod_hdcp_atomic_op_i2c *poll,
173 struct mod_hdcp_atomic_op_i2c *read,
174 uint32_t poll_timeout_us,
175 uint8_t poll_mask_msb
176 );
177 bool (*atomic_write_poll_read_aux)(
178 void *handle,
179 const struct mod_hdcp_atomic_op_aux *write,
180 const struct mod_hdcp_atomic_op_aux *poll,
181 struct mod_hdcp_atomic_op_aux *read,
182 uint32_t poll_timeout_us,
183 uint8_t poll_mask_msb
184 );
185 } funcs;
186};
187
188struct mod_hdcp_psp {
189 void *handle;
190 void *funcs;
191 struct mod_hdcp_psp_caps caps;
192};
193
194struct mod_hdcp_display_adjustment {
195 uint8_t disable : 2;
196 uint8_t reserved : 6;
197};
198
199struct mod_hdcp_link_adjustment_hdcp1 {
200 uint8_t disable : 1;
201 uint8_t postpone_encryption : 1;
202 uint8_t min_auth_retries_wa : 1;
203 uint8_t reserved : 5;
204};
205
206enum mod_hdcp_force_hdcp_type {
207 MOD_HDCP_FORCE_TYPE_MAX = 0,
208 MOD_HDCP_FORCE_TYPE_0,
209 MOD_HDCP_FORCE_TYPE_1
210};
211
212struct mod_hdcp_link_adjustment_hdcp2 {
213 uint8_t disable : 1;
214 uint8_t force_type : 2;
215 uint8_t force_no_stored_km : 1;
216 uint8_t increase_h_prime_timeout: 1;
217 uint8_t force_sw_locality_check : 1;
218 uint8_t reserved : 2;
219};
220
221struct mod_hdcp_link_adjustment {
222 uint8_t auth_delay;
223 struct mod_hdcp_link_adjustment_hdcp1 hdcp1;
224 struct mod_hdcp_link_adjustment_hdcp2 hdcp2;
225};
226
227struct mod_hdcp_error {
228 enum mod_hdcp_status status;
229 uint8_t state_id;
230};
231
232struct mod_hdcp_trace {
233 struct mod_hdcp_error errors[MAX_NUM_OF_ERROR_TRACE];
234 uint8_t error_count;
235};
236
237enum mod_hdcp_encryption_status {
238 MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF = 0,
239 MOD_HDCP_ENCRYPTION_STATUS_HDCP1_ON,
240 MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON,
241 MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON,
242 MOD_HDCP_ENCRYPTION_STATUS_HDCP2_ON
243};
244
245/* per link events dm has to notify to hdcp module */
246enum mod_hdcp_event {
247 MOD_HDCP_EVENT_CALLBACK = 0,
248 MOD_HDCP_EVENT_WATCHDOG_TIMEOUT,
249 MOD_HDCP_EVENT_CPIRQ
250};
251
252/* output flags from module requesting timer operations */
253struct mod_hdcp_output {
254 uint8_t callback_needed;
255 uint8_t callback_stop;
256 uint8_t watchdog_timer_needed;
257 uint8_t watchdog_timer_stop;
258 uint16_t callback_delay;
259 uint16_t watchdog_timer_delay;
260 uint8_t auth_complete;
261};
262
263/* used to represent per display info */
264struct mod_hdcp_display {
265 enum mod_hdcp_display_state state;
266 uint8_t index;
267 uint8_t controller;
268 uint8_t dig_fe;
269 uint8_t stream_enc_idx;
270 union {
271 uint8_t vc_id;
272 };
273 struct mod_hdcp_display_adjustment adjust;
274};
275
276/* used to represent per link info */
277/* in case a link has multiple displays, they share the same link info */
278struct mod_hdcp_link {
279 enum mod_hdcp_operation_mode mode;
280 uint8_t dig_be;
281 uint8_t ddc_line;
282 uint8_t link_enc_idx;
283 uint8_t phy_idx;
284 uint8_t dio_output_id;
285 uint8_t hdcp_supported_informational;
286 union {
287 struct mod_hdcp_displayport dp;
288 struct mod_hdcp_hdmi hdmi;
289 };
290 struct mod_hdcp_link_adjustment adjust;
291};
292
293/* a query structure for a display's hdcp information */
294struct mod_hdcp_display_query {
295 const struct mod_hdcp_display *display;
296 const struct mod_hdcp_link *link;
297 const struct mod_hdcp_trace *trace;
298 enum mod_hdcp_encryption_status encryption_status;
299};
300
301/* contains values per on external display configuration change */
302struct mod_hdcp_config {
303 struct mod_hdcp_psp psp;
304 struct mod_hdcp_ddc ddc;
305 struct {
306 uint8_t lc_enable_sw_fallback : 1;
307 uint8_t reserved : 7;
308 } debug;
309 uint8_t index;
310};
311
312/* dm allocates memory of mod_hdcp per dc_link on dm init based on memory size*/
313size_t mod_hdcp_get_memory_size(void);
314
315/* called per link on link creation */
316enum mod_hdcp_status mod_hdcp_setup(struct mod_hdcp *hdcp,
317 struct mod_hdcp_config *config);
318
319/* called per link on link destroy */
320enum mod_hdcp_status mod_hdcp_teardown(struct mod_hdcp *hdcp);
321
322/* called per display after stream is enabled */
323enum mod_hdcp_status mod_hdcp_add_display(struct mod_hdcp *hdcp,
324 struct mod_hdcp_link *link, struct mod_hdcp_display *display,
325 struct mod_hdcp_output *output);
326
327/* called per display before stream is disabled */
328enum mod_hdcp_status mod_hdcp_remove_display(struct mod_hdcp *hdcp,
329 uint8_t index, struct mod_hdcp_output *output);
330
331/* called per display to apply new authentication adjustment */
332enum mod_hdcp_status mod_hdcp_update_display(struct mod_hdcp *hdcp,
333 uint8_t index,
334 struct mod_hdcp_link_adjustment *link_adjust,
335 struct mod_hdcp_display_adjustment *display_adjust,
336 struct mod_hdcp_output *output);
337
338/* called to query hdcp information on a specific index */
339enum mod_hdcp_status mod_hdcp_query_display(struct mod_hdcp *hdcp,
340 uint8_t index, struct mod_hdcp_display_query *query);
341
342/* called per link on connectivity change */
343enum mod_hdcp_status mod_hdcp_reset_connection(struct mod_hdcp *hdcp,
344 struct mod_hdcp_output *output);
345
346/* called per link on events (i.e. callback, watchdog, CP_IRQ) */
347enum mod_hdcp_status mod_hdcp_process_event(struct mod_hdcp *hdcp,
348 enum mod_hdcp_event event, struct mod_hdcp_output *output);
349
350/* called to convert enum mod_hdcp_status to c string */
351char *mod_hdcp_status_to_str(int32_t status);
352
353/* called to convert state id to c string */
354char *mod_hdcp_state_id_to_str(int32_t id);
355
356/* called to convert signal type to operation mode */
357enum mod_hdcp_operation_mode mod_hdcp_signal_type_to_operation_mode(
358 enum signal_type signal);
359#endif /* MOD_HDCP_H_ */
360

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source code of linux/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h