1 | /* |
2 | * BIF_5_1 Register documentation |
3 | * |
4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included |
14 | * in all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
22 | */ |
23 | |
24 | #ifndef BIF_5_1_D_H |
25 | #define BIF_5_1_D_H |
26 | |
27 | #define mmMM_INDEX 0x0 |
28 | #define mmMM_INDEX_HI 0x6 |
29 | #define mmMM_DATA 0x1 |
30 | #define mmBIF_MM_INDACCESS_CNTL 0x1500 |
31 | #define mmBUS_CNTL 0x1508 |
32 | #define mmCONFIG_CNTL 0x1509 |
33 | #define mmCONFIG_MEMSIZE 0x150a |
34 | #define mmCONFIG_F0_BASE 0x150b |
35 | #define mmCONFIG_APER_SIZE 0x150c |
36 | #define mmCONFIG_REG_APER_SIZE 0x150d |
37 | #define mmBIF_SCRATCH0 0x150e |
38 | #define mmBIF_SCRATCH1 0x150f |
39 | #define mmBX_RESET_EN 0x1514 |
40 | #define mmMM_CFGREGS_CNTL 0x1513 |
41 | #define mmHW_DEBUG 0x1515 |
42 | #define mmMASTER_CREDIT_CNTL 0x1516 |
43 | #define mmSLAVE_REQ_CREDIT_CNTL 0x1517 |
44 | #define mmBX_RESET_CNTL 0x1518 |
45 | #define mmINTERRUPT_CNTL 0x151a |
46 | #define mmINTERRUPT_CNTL2 0x151b |
47 | #define mmBIF_DEBUG_CNTL 0x151c |
48 | #define mmBIF_DEBUG_MUX 0x151d |
49 | #define mmBIF_DEBUG_OUT 0x151e |
50 | #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 |
51 | #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 |
52 | #define mmCLKREQB_PAD_CNTL 0x1521 |
53 | #define mmSMBDAT_PAD_CNTL 0x1522 |
54 | #define mmSMBCLK_PAD_CNTL 0x1523 |
55 | #define mmBIF_XDMA_LO 0x14c0 |
56 | #define mmBIF_XDMA_HI 0x14c1 |
57 | #define mmBIF_FEATURES_CONTROL_MISC 0x14c2 |
58 | #define mmBIF_DOORBELL_CNTL 0x14c3 |
59 | #define mmBIF_SLVARB_MODE 0x14c4 |
60 | #define mmBIF_FB_EN 0x1524 |
61 | #define mmBIF_BUSNUM_CNTL1 0x1525 |
62 | #define mmBIF_BUSNUM_LIST0 0x1526 |
63 | #define mmBIF_BUSNUM_LIST1 0x1527 |
64 | #define mmBIF_BUSNUM_CNTL2 0x152b |
65 | #define mmBIF_BUSY_DELAY_CNTR 0x1529 |
66 | #define mmBIF_PERFMON_CNTL 0x152c |
67 | #define mmBIF_PERFCOUNTER0_RESULT 0x152d |
68 | #define mmBIF_PERFCOUNTER1_RESULT 0x152e |
69 | #define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 |
70 | #define mmGPU_HDP_FLUSH_REQ 0x1537 |
71 | #define mmGPU_HDP_FLUSH_DONE 0x1538 |
72 | #define mmSLAVE_HANG_ERROR 0x153b |
73 | #define mmCAPTURE_HOST_BUSNUM 0x153c |
74 | #define mmHOST_BUSNUM 0x153d |
75 | #define mmPEER_REG_RANGE0 0x153e |
76 | #define mmPEER_REG_RANGE1 0x153f |
77 | #define mmPEER0_FB_OFFSET_HI 0x14f3 |
78 | #define mmPEER0_FB_OFFSET_LO 0x14f2 |
79 | #define mmPEER1_FB_OFFSET_HI 0x14f1 |
80 | #define mmPEER1_FB_OFFSET_LO 0x14f0 |
81 | #define mmPEER2_FB_OFFSET_HI 0x14ef |
82 | #define mmPEER2_FB_OFFSET_LO 0x14ee |
83 | #define mmPEER3_FB_OFFSET_HI 0x14ed |
84 | #define mmPEER3_FB_OFFSET_LO 0x14ec |
85 | #define mmDBG_BYPASS_SRBM_ACCESS 0x14eb |
86 | #define mmSMBUS_BACO_DUMMY 0x14c6 |
87 | #define mmBIF_DEVFUNCNUM_LIST0 0x14e8 |
88 | #define mmBIF_DEVFUNCNUM_LIST1 0x14e7 |
89 | #define mmBACO_CNTL 0x14e5 |
90 | #define mmBF_ANA_ISO_CNTL 0x14c7 |
91 | #define mmMEM_TYPE_CNTL 0x14e4 |
92 | #define mmBIF_BACO_DEBUG 0x14df |
93 | #define mmBIF_BACO_DEBUG_LATCH 0x14dc |
94 | #define mmBACO_CNTL_MISC 0x14db |
95 | #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x14f8 |
96 | #define mmBIF_VDDGFX_GFX0_LOWER 0x1428 |
97 | #define mmBIF_VDDGFX_GFX0_UPPER 0x1429 |
98 | #define mmBIF_VDDGFX_GFX1_LOWER 0x142a |
99 | #define mmBIF_VDDGFX_GFX1_UPPER 0x142b |
100 | #define mmBIF_VDDGFX_GFX2_LOWER 0x142c |
101 | #define mmBIF_VDDGFX_GFX2_UPPER 0x142d |
102 | #define mmBIF_VDDGFX_GFX3_LOWER 0x142e |
103 | #define mmBIF_VDDGFX_GFX3_UPPER 0x142f |
104 | #define mmBIF_VDDGFX_GFX4_LOWER 0x1430 |
105 | #define mmBIF_VDDGFX_GFX4_UPPER 0x1431 |
106 | #define mmBIF_VDDGFX_GFX5_LOWER 0x1432 |
107 | #define mmBIF_VDDGFX_GFX5_UPPER 0x1433 |
108 | #define mmBIF_VDDGFX_RSV1_LOWER 0x1434 |
109 | #define mmBIF_VDDGFX_RSV1_UPPER 0x1435 |
110 | #define mmBIF_VDDGFX_RSV2_LOWER 0x1436 |
111 | #define mmBIF_VDDGFX_RSV2_UPPER 0x1437 |
112 | #define mmBIF_VDDGFX_RSV3_LOWER 0x1438 |
113 | #define mmBIF_VDDGFX_RSV3_UPPER 0x1439 |
114 | #define mmBIF_VDDGFX_RSV4_LOWER 0x143a |
115 | #define mmBIF_VDDGFX_RSV4_UPPER 0x143b |
116 | #define mmBIF_VDDGFX_FB_CMP 0x143c |
117 | #define mmBIF_DOORBELL_GBLAPER1_LOWER 0x14fc |
118 | #define mmBIF_DOORBELL_GBLAPER1_UPPER 0x14fd |
119 | #define mmBIF_DOORBELL_GBLAPER2_LOWER 0x14fe |
120 | #define mmBIF_DOORBELL_GBLAPER2_UPPER 0x14ff |
121 | #define mmBIF_SMU_INDEX 0x143d |
122 | #define mmBIF_SMU_DATA 0x143e |
123 | #define mmIMPCTL_RESET 0x14f5 |
124 | #define mmGARLIC_FLUSH_CNTL 0x1401 |
125 | #define mmGARLIC_FLUSH_ADDR_START_0 0x1402 |
126 | #define mmGARLIC_FLUSH_ADDR_START_1 0x1404 |
127 | #define mmGARLIC_FLUSH_ADDR_START_2 0x1406 |
128 | #define mmGARLIC_FLUSH_ADDR_START_3 0x1408 |
129 | #define mmGARLIC_FLUSH_ADDR_START_4 0x140a |
130 | #define mmGARLIC_FLUSH_ADDR_START_5 0x140c |
131 | #define mmGARLIC_FLUSH_ADDR_START_6 0x140e |
132 | #define mmGARLIC_FLUSH_ADDR_START_7 0x1410 |
133 | #define mmGARLIC_FLUSH_ADDR_END_0 0x1403 |
134 | #define mmGARLIC_FLUSH_ADDR_END_1 0x1405 |
135 | #define mmGARLIC_FLUSH_ADDR_END_2 0x1407 |
136 | #define mmGARLIC_FLUSH_ADDR_END_3 0x1409 |
137 | #define mmGARLIC_FLUSH_ADDR_END_4 0x140b |
138 | #define mmGARLIC_FLUSH_ADDR_END_5 0x140d |
139 | #define mmGARLIC_FLUSH_ADDR_END_6 0x140f |
140 | #define mmGARLIC_FLUSH_ADDR_END_7 0x1411 |
141 | #define mmGARLIC_FLUSH_REQ 0x1412 |
142 | #define mmGPU_GARLIC_FLUSH_REQ 0x1413 |
143 | #define mmGPU_GARLIC_FLUSH_DONE 0x1414 |
144 | #define mmGARLIC_COHE_CP_RB0_WPTR 0x1415 |
145 | #define mmGARLIC_COHE_CP_RB1_WPTR 0x1416 |
146 | #define mmGARLIC_COHE_CP_RB2_WPTR 0x1417 |
147 | #define mmGARLIC_COHE_UVD_RBC_RB_WPTR 0x1418 |
148 | #define mmGARLIC_COHE_SDMA0_GFX_RB_WPTR 0x1419 |
149 | #define mmGARLIC_COHE_SDMA1_GFX_RB_WPTR 0x141a |
150 | #define mmGARLIC_COHE_CP_DMA_ME_COMMAND 0x141b |
151 | #define mmGARLIC_COHE_CP_DMA_PFP_COMMAND 0x141c |
152 | #define mmGARLIC_COHE_SAM_SAB_RBI_WPTR 0x141d |
153 | #define mmGARLIC_COHE_SAM_SAB_RBO_WPTR 0x141e |
154 | #define mmGARLIC_COHE_VCE_OUT_RB_WPTR 0x141f |
155 | #define mmGARLIC_COHE_VCE_RB_WPTR2 0x1420 |
156 | #define mmGARLIC_COHE_VCE_RB_WPTR 0x1421 |
157 | #define mmGARLIC_COHE_SDMA2_GFX_RB_WPTR 0x1422 |
158 | #define mmGARLIC_COHE_SDMA3_GFX_RB_WPTR 0x1423 |
159 | #define mmGARLIC_COHE_CP_DMA_PIO_COMMAND 0x1424 |
160 | #define mmGARLIC_COHE_GARLIC_FLUSH_REQ 0x1425 |
161 | #define mmREMAP_HDP_MEM_FLUSH_CNTL 0x1426 |
162 | #define mmREMAP_HDP_REG_FLUSH_CNTL 0x1427 |
163 | #define mmBIOS_SCRATCH_0 0x5c9 |
164 | #define mmBIOS_SCRATCH_1 0x5ca |
165 | #define mmBIOS_SCRATCH_2 0x5cb |
166 | #define mmBIOS_SCRATCH_3 0x5cc |
167 | #define mmBIOS_SCRATCH_4 0x5cd |
168 | #define mmBIOS_SCRATCH_5 0x5ce |
169 | #define mmBIOS_SCRATCH_6 0x5cf |
170 | #define mmBIOS_SCRATCH_7 0x5d0 |
171 | #define mmBIOS_SCRATCH_8 0x5d1 |
172 | #define mmBIOS_SCRATCH_9 0x5d2 |
173 | #define mmBIOS_SCRATCH_10 0x5d3 |
174 | #define mmBIOS_SCRATCH_11 0x5d4 |
175 | #define mmBIOS_SCRATCH_12 0x5d5 |
176 | #define mmBIOS_SCRATCH_13 0x5d6 |
177 | #define mmBIOS_SCRATCH_14 0x5d7 |
178 | #define mmBIOS_SCRATCH_15 0x5d8 |
179 | #define mmBIF_RB_CNTL 0x1530 |
180 | #define mmBIF_RB_BASE 0x1531 |
181 | #define mmBIF_RB_RPTR 0x1532 |
182 | #define mmBIF_RB_WPTR 0x1533 |
183 | #define mmBIF_RB_WPTR_ADDR_HI 0x1534 |
184 | #define mmBIF_RB_WPTR_ADDR_LO 0x1535 |
185 | #define mmVENDOR_ID 0x0 |
186 | #define mmDEVICE_ID 0x0 |
187 | #define mmCOMMAND 0x1 |
188 | #define mmSTATUS 0x1 |
189 | #define mmREVISION_ID 0x2 |
190 | #define mmPROG_INTERFACE 0x2 |
191 | #define mmSUB_CLASS 0x2 |
192 | #define mmBASE_CLASS 0x2 |
193 | #define mmCACHE_LINE 0x3 |
194 | #define mmLATENCY 0x3 |
195 | #define 0x3 |
196 | #define mmBIST 0x3 |
197 | #define mmBASE_ADDR_1 0x4 |
198 | #define mmBASE_ADDR_2 0x5 |
199 | #define mmBASE_ADDR_3 0x6 |
200 | #define mmBASE_ADDR_4 0x7 |
201 | #define mmBASE_ADDR_5 0x8 |
202 | #define mmBASE_ADDR_6 0x9 |
203 | #define mmROM_BASE_ADDR 0xc |
204 | #define mmCAP_PTR 0xd |
205 | #define mmINTERRUPT_LINE 0xf |
206 | #define mmINTERRUPT_PIN 0xf |
207 | #define mmADAPTER_ID 0xb |
208 | #define mmMIN_GRANT 0xf |
209 | #define mmMAX_LATENCY 0xf |
210 | #define mmVENDOR_CAP_LIST 0x12 |
211 | #define mmADAPTER_ID_W 0x13 |
212 | #define mmPMI_CAP_LIST 0x14 |
213 | #define mmPMI_CAP 0x14 |
214 | #define mmPMI_STATUS_CNTL 0x15 |
215 | #define mmPCIE_CAP_LIST 0x16 |
216 | #define mmPCIE_CAP 0x16 |
217 | #define mmDEVICE_CAP 0x17 |
218 | #define mmDEVICE_CNTL 0x18 |
219 | #define mmDEVICE_STATUS 0x18 |
220 | #define mmLINK_CAP 0x19 |
221 | #define mmLINK_CNTL 0x1a |
222 | #define mmLINK_STATUS 0x1a |
223 | #define mmDEVICE_CAP2 0x1f |
224 | #define mmDEVICE_CNTL2 0x20 |
225 | #define mmDEVICE_STATUS2 0x20 |
226 | #define mmLINK_CAP2 0x21 |
227 | #define mmLINK_CNTL2 0x22 |
228 | #define mmLINK_STATUS2 0x22 |
229 | #define mmMSI_CAP_LIST 0x28 |
230 | #define mmMSI_MSG_CNTL 0x28 |
231 | #define mmMSI_MSG_ADDR_LO 0x29 |
232 | #define mmMSI_MSG_ADDR_HI 0x2a |
233 | #define mmMSI_MSG_DATA_64 0x2b |
234 | #define mmMSI_MSG_DATA 0x2a |
235 | #define mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x40 |
236 | #define mmPCIE_VENDOR_SPECIFIC_HDR 0x41 |
237 | #define mmPCIE_VENDOR_SPECIFIC1 0x42 |
238 | #define mmPCIE_VENDOR_SPECIFIC2 0x43 |
239 | #define mmPCIE_VC_ENH_CAP_LIST 0x44 |
240 | #define mmPCIE_PORT_VC_CAP_REG1 0x45 |
241 | #define mmPCIE_PORT_VC_CAP_REG2 0x46 |
242 | #define mmPCIE_PORT_VC_CNTL 0x47 |
243 | #define mmPCIE_PORT_VC_STATUS 0x47 |
244 | #define mmPCIE_VC0_RESOURCE_CAP 0x48 |
245 | #define mmPCIE_VC0_RESOURCE_CNTL 0x49 |
246 | #define mmPCIE_VC0_RESOURCE_STATUS 0x4a |
247 | #define mmPCIE_VC1_RESOURCE_CAP 0x4b |
248 | #define mmPCIE_VC1_RESOURCE_CNTL 0x4c |
249 | #define mmPCIE_VC1_RESOURCE_STATUS 0x4d |
250 | #define mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x50 |
251 | #define mmPCIE_DEV_SERIAL_NUM_DW1 0x51 |
252 | #define mmPCIE_DEV_SERIAL_NUM_DW2 0x52 |
253 | #define mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x54 |
254 | #define mmPCIE_UNCORR_ERR_STATUS 0x55 |
255 | #define mmPCIE_UNCORR_ERR_MASK 0x56 |
256 | #define mmPCIE_UNCORR_ERR_SEVERITY 0x57 |
257 | #define mmPCIE_CORR_ERR_STATUS 0x58 |
258 | #define mmPCIE_CORR_ERR_MASK 0x59 |
259 | #define mmPCIE_ADV_ERR_CAP_CNTL 0x5a |
260 | #define mmPCIE_HDR_LOG0 0x5b |
261 | #define mmPCIE_HDR_LOG1 0x5c |
262 | #define mmPCIE_HDR_LOG2 0x5d |
263 | #define mmPCIE_HDR_LOG3 0x5e |
264 | #define mmPCIE_TLP_PREFIX_LOG0 0x62 |
265 | #define mmPCIE_TLP_PREFIX_LOG1 0x63 |
266 | #define mmPCIE_TLP_PREFIX_LOG2 0x64 |
267 | #define mmPCIE_TLP_PREFIX_LOG3 0x65 |
268 | #define mmPCIE_BAR_ENH_CAP_LIST 0x80 |
269 | #define mmPCIE_BAR1_CAP 0x81 |
270 | #define mmPCIE_BAR1_CNTL 0x82 |
271 | #define mmPCIE_BAR2_CAP 0x83 |
272 | #define mmPCIE_BAR2_CNTL 0x84 |
273 | #define mmPCIE_BAR3_CAP 0x85 |
274 | #define mmPCIE_BAR3_CNTL 0x86 |
275 | #define mmPCIE_BAR4_CAP 0x87 |
276 | #define mmPCIE_BAR4_CNTL 0x88 |
277 | #define mmPCIE_BAR5_CAP 0x89 |
278 | #define mmPCIE_BAR5_CNTL 0x8a |
279 | #define mmPCIE_BAR6_CAP 0x8b |
280 | #define mmPCIE_BAR6_CNTL 0x8c |
281 | #define mmPCIE_PWR_BUDGET_ENH_CAP_LIST 0x90 |
282 | #define mmPCIE_PWR_BUDGET_DATA_SELECT 0x91 |
283 | #define mmPCIE_PWR_BUDGET_DATA 0x92 |
284 | #define mmPCIE_PWR_BUDGET_CAP 0x93 |
285 | #define mmPCIE_DPA_ENH_CAP_LIST 0x94 |
286 | #define mmPCIE_DPA_CAP 0x95 |
287 | #define mmPCIE_DPA_LATENCY_INDICATOR 0x96 |
288 | #define mmPCIE_DPA_STATUS 0x97 |
289 | #define mmPCIE_DPA_CNTL 0x97 |
290 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x98 |
291 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x98 |
292 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x98 |
293 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x98 |
294 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x99 |
295 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x99 |
296 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x99 |
297 | #define mmPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x99 |
298 | #define mmPCIE_SECONDARY_ENH_CAP_LIST 0x9c |
299 | #define mmPCIE_LINK_CNTL3 0x9d |
300 | #define mmPCIE_LANE_ERROR_STATUS 0x9e |
301 | #define mmPCIE_LANE_0_EQUALIZATION_CNTL 0x9f |
302 | #define mmPCIE_LANE_1_EQUALIZATION_CNTL 0x9f |
303 | #define mmPCIE_LANE_2_EQUALIZATION_CNTL 0xa0 |
304 | #define mmPCIE_LANE_3_EQUALIZATION_CNTL 0xa0 |
305 | #define mmPCIE_LANE_4_EQUALIZATION_CNTL 0xa1 |
306 | #define mmPCIE_LANE_5_EQUALIZATION_CNTL 0xa1 |
307 | #define mmPCIE_LANE_6_EQUALIZATION_CNTL 0xa2 |
308 | #define mmPCIE_LANE_7_EQUALIZATION_CNTL 0xa2 |
309 | #define mmPCIE_LANE_8_EQUALIZATION_CNTL 0xa3 |
310 | #define mmPCIE_LANE_9_EQUALIZATION_CNTL 0xa3 |
311 | #define mmPCIE_LANE_10_EQUALIZATION_CNTL 0xa4 |
312 | #define mmPCIE_LANE_11_EQUALIZATION_CNTL 0xa4 |
313 | #define mmPCIE_LANE_12_EQUALIZATION_CNTL 0xa5 |
314 | #define mmPCIE_LANE_13_EQUALIZATION_CNTL 0xa5 |
315 | #define mmPCIE_LANE_14_EQUALIZATION_CNTL 0xa6 |
316 | #define mmPCIE_LANE_15_EQUALIZATION_CNTL 0xa6 |
317 | #define mmPCIE_ACS_ENH_CAP_LIST 0xa8 |
318 | #define mmPCIE_ACS_CAP 0xa9 |
319 | #define mmPCIE_ACS_CNTL 0xa9 |
320 | #define mmPCIE_ATS_ENH_CAP_LIST 0xac |
321 | #define mmPCIE_ATS_CAP 0xad |
322 | #define mmPCIE_ATS_CNTL 0xad |
323 | #define mmPCIE_PAGE_REQ_ENH_CAP_LIST 0xb0 |
324 | #define mmPCIE_PAGE_REQ_CNTL 0xb1 |
325 | #define mmPCIE_PAGE_REQ_STATUS 0xb1 |
326 | #define mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xb2 |
327 | #define mmPCIE_OUTSTAND_PAGE_REQ_ALLOC 0xb3 |
328 | #define mmPCIE_PASID_ENH_CAP_LIST 0xb4 |
329 | #define mmPCIE_PASID_CAP 0xb5 |
330 | #define mmPCIE_PASID_CNTL 0xb5 |
331 | #define mmPCIE_TPH_REQR_ENH_CAP_LIST 0xb8 |
332 | #define mmPCIE_TPH_REQR_CAP 0xb9 |
333 | #define mmPCIE_TPH_REQR_CNTL 0xba |
334 | #define mmPCIE_MC_ENH_CAP_LIST 0xbc |
335 | #define mmPCIE_MC_CAP 0xbd |
336 | #define mmPCIE_MC_CNTL 0xbd |
337 | #define mmPCIE_MC_ADDR0 0xbe |
338 | #define mmPCIE_MC_ADDR1 0xbf |
339 | #define mmPCIE_MC_RCV0 0xc0 |
340 | #define mmPCIE_MC_RCV1 0xc1 |
341 | #define mmPCIE_MC_BLOCK_ALL0 0xc2 |
342 | #define mmPCIE_MC_BLOCK_ALL1 0xc3 |
343 | #define mmPCIE_MC_BLOCK_UNTRANSLATED_0 0xc4 |
344 | #define mmPCIE_MC_BLOCK_UNTRANSLATED_1 0xc5 |
345 | #define mmPCIE_LTR_ENH_CAP_LIST 0xc8 |
346 | #define mmPCIE_LTR_CAP 0xc9 |
347 | #define ixMM_INDEX_IND 0x1090000 |
348 | #define ixMM_INDEX_HI_IND 0x1090006 |
349 | #define ixMM_DATA_IND 0x1090001 |
350 | #define ixBIF_MM_INDACCESS_CNTL_IND 0x1091500 |
351 | #define ixBUS_CNTL_IND 0x1091508 |
352 | #define ixCONFIG_CNTL_IND 0x1091509 |
353 | #define ixCONFIG_MEMSIZE_IND 0x109150a |
354 | #define ixCONFIG_F0_BASE_IND 0x109150b |
355 | #define ixCONFIG_APER_SIZE_IND 0x109150c |
356 | #define ixCONFIG_REG_APER_SIZE_IND 0x109150d |
357 | #define ixBIF_SCRATCH0_IND 0x109150e |
358 | #define ixBIF_SCRATCH1_IND 0x109150f |
359 | #define ixBX_RESET_EN_IND 0x1091514 |
360 | #define ixMM_CFGREGS_CNTL_IND 0x1091513 |
361 | #define ixHW_DEBUG_IND 0x1091515 |
362 | #define ixMASTER_CREDIT_CNTL_IND 0x1091516 |
363 | #define ixSLAVE_REQ_CREDIT_CNTL_IND 0x1091517 |
364 | #define ixBX_RESET_CNTL_IND 0x1091518 |
365 | #define ixINTERRUPT_CNTL_IND 0x109151a |
366 | #define ixINTERRUPT_CNTL2_IND 0x109151b |
367 | #define ixBIF_DEBUG_CNTL_IND 0x109151c |
368 | #define ixBIF_DEBUG_MUX_IND 0x109151d |
369 | #define ixBIF_DEBUG_OUT_IND 0x109151e |
370 | #define ixHDP_REG_COHERENCY_FLUSH_CNTL_IND 0x1091528 |
371 | #define ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND 0x1091520 |
372 | #define ixCLKREQB_PAD_CNTL_IND 0x1091521 |
373 | #define ixSMBDAT_PAD_CNTL_IND 0x1091522 |
374 | #define ixSMBCLK_PAD_CNTL_IND 0x1091523 |
375 | #define ixBIF_XDMA_LO_IND 0x10914c0 |
376 | #define ixBIF_XDMA_HI_IND 0x10914c1 |
377 | #define ixBIF_FEATURES_CONTROL_MISC_IND 0x10914c2 |
378 | #define ixBIF_DOORBELL_CNTL_IND 0x10914c3 |
379 | #define ixBIF_SLVARB_MODE_IND 0x10914c4 |
380 | #define ixBIF_FB_EN_IND 0x1091524 |
381 | #define ixBIF_BUSNUM_CNTL1_IND 0x1091525 |
382 | #define ixBIF_BUSNUM_LIST0_IND 0x1091526 |
383 | #define ixBIF_BUSNUM_LIST1_IND 0x1091527 |
384 | #define ixBIF_BUSNUM_CNTL2_IND 0x109152b |
385 | #define ixBIF_BUSY_DELAY_CNTR_IND 0x1091529 |
386 | #define ixBIF_PERFMON_CNTL_IND 0x109152c |
387 | #define ixBIF_PERFCOUNTER0_RESULT_IND 0x109152d |
388 | #define ixBIF_PERFCOUNTER1_RESULT_IND 0x109152e |
389 | #define ixSLAVE_HANG_PROTECTION_CNTL_IND 0x1091536 |
390 | #define ixGPU_HDP_FLUSH_REQ_IND 0x1091537 |
391 | #define ixGPU_HDP_FLUSH_DONE_IND 0x1091538 |
392 | #define ixSLAVE_HANG_ERROR_IND 0x109153b |
393 | #define ixCAPTURE_HOST_BUSNUM_IND 0x109153c |
394 | #define ixHOST_BUSNUM_IND 0x109153d |
395 | #define ixPEER_REG_RANGE0_IND 0x109153e |
396 | #define ixPEER_REG_RANGE1_IND 0x109153f |
397 | #define ixPEER0_FB_OFFSET_HI_IND 0x10914f3 |
398 | #define ixPEER0_FB_OFFSET_LO_IND 0x10914f2 |
399 | #define ixPEER1_FB_OFFSET_HI_IND 0x10914f1 |
400 | #define ixPEER1_FB_OFFSET_LO_IND 0x10914f0 |
401 | #define ixPEER2_FB_OFFSET_HI_IND 0x10914ef |
402 | #define ixPEER2_FB_OFFSET_LO_IND 0x10914ee |
403 | #define ixPEER3_FB_OFFSET_HI_IND 0x10914ed |
404 | #define ixPEER3_FB_OFFSET_LO_IND 0x10914ec |
405 | #define ixDBG_BYPASS_SRBM_ACCESS_IND 0x10914eb |
406 | #define ixSMBUS_BACO_DUMMY_IND 0x10914c6 |
407 | #define ixBIF_DEVFUNCNUM_LIST0_IND 0x10914e8 |
408 | #define ixBIF_DEVFUNCNUM_LIST1_IND 0x10914e7 |
409 | #define ixBACO_CNTL_IND 0x10914e5 |
410 | #define ixBF_ANA_ISO_CNTL_IND 0x10914c7 |
411 | #define ixMEM_TYPE_CNTL_IND 0x10914e4 |
412 | #define ixBIF_BACO_DEBUG_IND 0x10914df |
413 | #define ixBIF_BACO_DEBUG_LATCH_IND 0x10914dc |
414 | #define ixBACO_CNTL_MISC_IND 0x10914db |
415 | #define ixSMU_BIF_VDDGFX_PWR_STATUS_IND 0x10914f8 |
416 | #define ixBIF_VDDGFX_GFX0_LOWER_IND 0x1091428 |
417 | #define ixBIF_VDDGFX_GFX0_UPPER_IND 0x1091429 |
418 | #define ixBIF_VDDGFX_GFX1_LOWER_IND 0x109142a |
419 | #define ixBIF_VDDGFX_GFX1_UPPER_IND 0x109142b |
420 | #define ixBIF_VDDGFX_GFX2_LOWER_IND 0x109142c |
421 | #define ixBIF_VDDGFX_GFX2_UPPER_IND 0x109142d |
422 | #define ixBIF_VDDGFX_GFX3_LOWER_IND 0x109142e |
423 | #define ixBIF_VDDGFX_GFX3_UPPER_IND 0x109142f |
424 | #define ixBIF_VDDGFX_GFX4_LOWER_IND 0x1091430 |
425 | #define ixBIF_VDDGFX_GFX4_UPPER_IND 0x1091431 |
426 | #define ixBIF_VDDGFX_GFX5_LOWER_IND 0x1091432 |
427 | #define ixBIF_VDDGFX_GFX5_UPPER_IND 0x1091433 |
428 | #define ixBIF_VDDGFX_RSV1_LOWER_IND 0x1091434 |
429 | #define ixBIF_VDDGFX_RSV1_UPPER_IND 0x1091435 |
430 | #define ixBIF_VDDGFX_RSV2_LOWER_IND 0x1091436 |
431 | #define ixBIF_VDDGFX_RSV2_UPPER_IND 0x1091437 |
432 | #define ixBIF_VDDGFX_RSV3_LOWER_IND 0x1091438 |
433 | #define ixBIF_VDDGFX_RSV3_UPPER_IND 0x1091439 |
434 | #define ixBIF_VDDGFX_RSV4_LOWER_IND 0x109143a |
435 | #define ixBIF_VDDGFX_RSV4_UPPER_IND 0x109143b |
436 | #define ixBIF_VDDGFX_FB_CMP_IND 0x109143c |
437 | #define ixBIF_DOORBELL_GBLAPER1_LOWER_IND 0x10914fc |
438 | #define ixBIF_DOORBELL_GBLAPER1_UPPER_IND 0x10914fd |
439 | #define ixBIF_DOORBELL_GBLAPER2_LOWER_IND 0x10914fe |
440 | #define ixBIF_DOORBELL_GBLAPER2_UPPER_IND 0x10914ff |
441 | #define ixBIF_SMU_INDEX_IND 0x109143d |
442 | #define ixBIF_SMU_DATA_IND 0x109143e |
443 | #define ixIMPCTL_RESET_IND 0x10914f5 |
444 | #define ixGARLIC_FLUSH_CNTL_IND 0x1091401 |
445 | #define ixGARLIC_FLUSH_REQ_IND 0x1091412 |
446 | #define ixGPU_GARLIC_FLUSH_REQ_IND 0x1091413 |
447 | #define ixGPU_GARLIC_FLUSH_DONE_IND 0x1091414 |
448 | #define ixGARLIC_COHE_CP_RB0_WPTR_IND 0x1091415 |
449 | #define ixGARLIC_COHE_CP_RB1_WPTR_IND 0x1091416 |
450 | #define ixGARLIC_COHE_CP_RB2_WPTR_IND 0x1091417 |
451 | #define ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND 0x1091418 |
452 | #define ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND 0x1091419 |
453 | #define ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND 0x109141a |
454 | #define ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND 0x109141b |
455 | #define ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND 0x109141c |
456 | #define ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND 0x109141d |
457 | #define ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND 0x109141e |
458 | #define ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND 0x109141f |
459 | #define ixGARLIC_COHE_VCE_RB_WPTR2_IND 0x1091420 |
460 | #define ixGARLIC_COHE_VCE_RB_WPTR_IND 0x1091421 |
461 | #define ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND 0x1091422 |
462 | #define ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND 0x1091423 |
463 | #define ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND 0x1091424 |
464 | #define ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND 0x1091425 |
465 | #define ixREMAP_HDP_MEM_FLUSH_CNTL_IND 0x1091426 |
466 | #define ixREMAP_HDP_REG_FLUSH_CNTL_IND 0x1091427 |
467 | #define ixBIOS_SCRATCH_0_IND 0x10905c9 |
468 | #define ixBIOS_SCRATCH_1_IND 0x10905ca |
469 | #define ixBIOS_SCRATCH_2_IND 0x10905cb |
470 | #define ixBIOS_SCRATCH_3_IND 0x10905cc |
471 | #define ixBIOS_SCRATCH_4_IND 0x10905cd |
472 | #define ixBIOS_SCRATCH_5_IND 0x10905ce |
473 | #define ixBIOS_SCRATCH_6_IND 0x10905cf |
474 | #define ixBIOS_SCRATCH_7_IND 0x10905d0 |
475 | #define ixBIOS_SCRATCH_8_IND 0x10905d1 |
476 | #define ixBIOS_SCRATCH_9_IND 0x10905d2 |
477 | #define ixBIOS_SCRATCH_10_IND 0x10905d3 |
478 | #define ixBIOS_SCRATCH_11_IND 0x10905d4 |
479 | #define ixBIOS_SCRATCH_12_IND 0x10905d5 |
480 | #define ixBIOS_SCRATCH_13_IND 0x10905d6 |
481 | #define ixBIOS_SCRATCH_14_IND 0x10905d7 |
482 | #define ixBIOS_SCRATCH_15_IND 0x10905d8 |
483 | #define ixBIF_RB_CNTL_IND 0x1091530 |
484 | #define ixBIF_RB_BASE_IND 0x1091531 |
485 | #define ixBIF_RB_RPTR_IND 0x1091532 |
486 | #define ixBIF_RB_WPTR_IND 0x1091533 |
487 | #define ixBIF_RB_WPTR_ADDR_HI_IND 0x1091534 |
488 | #define ixBIF_RB_WPTR_ADDR_LO_IND 0x1091535 |
489 | #define mmNB_GBIF_INDEX 0x34 |
490 | #define mmNB_GBIF_DATA 0x35 |
491 | #define mmPCIE_INDEX 0xe |
492 | #define mmPCIE_DATA 0xf |
493 | #define mmPCIE_INDEX_2 0xc |
494 | #define mmPCIE_DATA_2 0xd |
495 | #define ixPCIE_RESERVED 0x1400000 |
496 | #define ixPCIE_SCRATCH 0x1400001 |
497 | #define ixPCIE_HW_DEBUG 0x1400002 |
498 | #define ixPCIE_RX_NUM_NAK 0x140000e |
499 | #define ixPCIE_RX_NUM_NAK_GENERATED 0x140000f |
500 | #define ixPCIE_CNTL 0x1400010 |
501 | #define ixPCIE_CONFIG_CNTL 0x1400011 |
502 | #define ixPCIE_DEBUG_CNTL 0x1400012 |
503 | #define ixPCIE_INT_CNTL 0x140001a |
504 | #define ixPCIE_INT_STATUS 0x140001b |
505 | #define ixPCIE_CNTL2 0x140001c |
506 | #define ixPCIE_RX_CNTL2 0x140001d |
507 | #define ixPCIE_TX_F0_ATTR_CNTL 0x140001e |
508 | #define ixPCIE_TX_F1_F2_ATTR_CNTL 0x140001f |
509 | #define ixPCIE_CI_CNTL 0x1400020 |
510 | #define ixPCIE_BUS_CNTL 0x1400021 |
511 | #define ixPCIE_LC_STATE6 0x1400022 |
512 | #define ixPCIE_LC_STATE7 0x1400023 |
513 | #define ixPCIE_LC_STATE8 0x1400024 |
514 | #define ixPCIE_LC_STATE9 0x1400025 |
515 | #define ixPCIE_LC_STATE10 0x1400026 |
516 | #define ixPCIE_LC_STATE11 0x1400027 |
517 | #define ixPCIE_LC_STATUS1 0x1400028 |
518 | #define ixPCIE_LC_STATUS2 0x1400029 |
519 | #define ixPCIE_WPR_CNTL 0x1400030 |
520 | #define ixPCIE_RX_LAST_TLP0 0x1400031 |
521 | #define ixPCIE_RX_LAST_TLP1 0x1400032 |
522 | #define ixPCIE_RX_LAST_TLP2 0x1400033 |
523 | #define ixPCIE_RX_LAST_TLP3 0x1400034 |
524 | #define ixPCIE_TX_LAST_TLP0 0x1400035 |
525 | #define ixPCIE_TX_LAST_TLP1 0x1400036 |
526 | #define ixPCIE_TX_LAST_TLP2 0x1400037 |
527 | #define ixPCIE_TX_LAST_TLP3 0x1400038 |
528 | #define ixPCIE_I2C_REG_ADDR_EXPAND 0x140003a |
529 | #define ixPCIE_I2C_REG_DATA 0x140003b |
530 | #define ixPCIE_CFG_CNTL 0x140003c |
531 | #define ixPCIE_P_CNTL 0x1400040 |
532 | #define ixPCIE_P_BUF_STATUS 0x1400041 |
533 | #define ixPCIE_P_DECODER_STATUS 0x1400042 |
534 | #define ixPCIE_P_MISC_STATUS 0x1400043 |
535 | #define ixPCIE_P_RCV_L0S_FTS_DET 0x1400050 |
536 | #define ixPCIE_OBFF_CNTL 0x1400061 |
537 | #define ixPCIE_TX_LTR_CNTL 0x1400060 |
538 | #define ixPCIE_PERF_COUNT_CNTL 0x1400080 |
539 | #define ixPCIE_PERF_CNTL_TXCLK 0x1400081 |
540 | #define ixPCIE_PERF_COUNT0_TXCLK 0x1400082 |
541 | #define ixPCIE_PERF_COUNT1_TXCLK 0x1400083 |
542 | #define ixPCIE_PERF_CNTL_MST_R_CLK 0x1400084 |
543 | #define ixPCIE_PERF_COUNT0_MST_R_CLK 0x1400085 |
544 | #define ixPCIE_PERF_COUNT1_MST_R_CLK 0x1400086 |
545 | #define ixPCIE_PERF_CNTL_MST_C_CLK 0x1400087 |
546 | #define ixPCIE_PERF_COUNT0_MST_C_CLK 0x1400088 |
547 | #define ixPCIE_PERF_COUNT1_MST_C_CLK 0x1400089 |
548 | #define ixPCIE_PERF_CNTL_SLV_R_CLK 0x140008a |
549 | #define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x140008b |
550 | #define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x140008c |
551 | #define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d |
552 | #define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e |
553 | #define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f |
554 | #define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 |
555 | #define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 |
556 | #define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 |
557 | #define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 |
558 | #define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 |
559 | #define ixPCIE_PERF_CNTL_TXCLK2 0x1400095 |
560 | #define ixPCIE_PERF_COUNT0_TXCLK2 0x1400096 |
561 | #define ixPCIE_PERF_COUNT1_TXCLK2 0x1400097 |
562 | #define ixPCIE_STRAP_F0 0x14000b0 |
563 | #define ixPCIE_STRAP_F1 0x14000b1 |
564 | #define ixPCIE_STRAP_F2 0x14000b2 |
565 | #define ixPCIE_STRAP_F3 0x14000b3 |
566 | #define ixPCIE_STRAP_F4 0x14000b4 |
567 | #define ixPCIE_STRAP_F5 0x14000b5 |
568 | #define ixPCIE_STRAP_F6 0x14000b6 |
569 | #define ixPCIE_STRAP_F7 0x14000b7 |
570 | #define ixPCIE_STRAP_MISC 0x14000c0 |
571 | #define ixPCIE_STRAP_MISC2 0x14000c1 |
572 | #define ixPCIE_STRAP_PI 0x14000c2 |
573 | #define ixPCIE_STRAP_I2C_BD 0x14000c4 |
574 | #define ixPCIE_PRBS_CLR 0x14000c8 |
575 | #define ixPCIE_PRBS_STATUS1 0x14000c9 |
576 | #define ixPCIE_PRBS_STATUS2 0x14000ca |
577 | #define ixPCIE_PRBS_FREERUN 0x14000cb |
578 | #define ixPCIE_PRBS_MISC 0x14000cc |
579 | #define ixPCIE_PRBS_USER_PATTERN 0x14000cd |
580 | #define ixPCIE_PRBS_LO_BITCNT 0x14000ce |
581 | #define ixPCIE_PRBS_HI_BITCNT 0x14000cf |
582 | #define ixPCIE_PRBS_ERRCNT_0 0x14000d0 |
583 | #define ixPCIE_PRBS_ERRCNT_1 0x14000d1 |
584 | #define ixPCIE_PRBS_ERRCNT_2 0x14000d2 |
585 | #define ixPCIE_PRBS_ERRCNT_3 0x14000d3 |
586 | #define ixPCIE_PRBS_ERRCNT_4 0x14000d4 |
587 | #define ixPCIE_PRBS_ERRCNT_5 0x14000d5 |
588 | #define ixPCIE_PRBS_ERRCNT_6 0x14000d6 |
589 | #define ixPCIE_PRBS_ERRCNT_7 0x14000d7 |
590 | #define ixPCIE_PRBS_ERRCNT_8 0x14000d8 |
591 | #define ixPCIE_PRBS_ERRCNT_9 0x14000d9 |
592 | #define ixPCIE_PRBS_ERRCNT_10 0x14000da |
593 | #define ixPCIE_PRBS_ERRCNT_11 0x14000db |
594 | #define ixPCIE_PRBS_ERRCNT_12 0x14000dc |
595 | #define ixPCIE_PRBS_ERRCNT_13 0x14000dd |
596 | #define ixPCIE_PRBS_ERRCNT_14 0x14000de |
597 | #define ixPCIE_PRBS_ERRCNT_15 0x14000df |
598 | #define ixPCIE_F0_DPA_CAP 0x14000e0 |
599 | #define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x14000e4 |
600 | #define ixPCIE_F0_DPA_CNTL 0x14000e5 |
601 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x14000e7 |
602 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x14000e8 |
603 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x14000e9 |
604 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x14000ea |
605 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x14000eb |
606 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x14000ec |
607 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x14000ed |
608 | #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x14000ee |
609 | #define ixPCIEP_RESERVED 0x10010000 |
610 | #define ixPCIEP_SCRATCH 0x10010001 |
611 | #define ixPCIEP_HW_DEBUG 0x10010002 |
612 | #define ixPCIEP_PORT_CNTL 0x10010010 |
613 | #define ixPCIE_TX_CNTL 0x10010020 |
614 | #define ixPCIE_TX_REQUESTER_ID 0x10010021 |
615 | #define ixPCIE_TX_VENDOR_SPECIFIC 0x10010022 |
616 | #define ixPCIE_TX_REQUEST_NUM_CNTL 0x10010023 |
617 | #define ixPCIE_TX_SEQ 0x10010024 |
618 | #define ixPCIE_TX_REPLAY 0x10010025 |
619 | #define ixPCIE_TX_ACK_LATENCY_LIMIT 0x10010026 |
620 | #define ixPCIE_TX_CREDITS_ADVT_P 0x10010030 |
621 | #define ixPCIE_TX_CREDITS_ADVT_NP 0x10010031 |
622 | #define ixPCIE_TX_CREDITS_ADVT_CPL 0x10010032 |
623 | #define ixPCIE_TX_CREDITS_INIT_P 0x10010033 |
624 | #define ixPCIE_TX_CREDITS_INIT_NP 0x10010034 |
625 | #define ixPCIE_TX_CREDITS_INIT_CPL 0x10010035 |
626 | #define ixPCIE_TX_CREDITS_STATUS 0x10010036 |
627 | #define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x10010037 |
628 | #define ixPCIE_P_PORT_LANE_STATUS 0x10010050 |
629 | #define ixPCIE_FC_P 0x10010060 |
630 | #define ixPCIE_FC_NP 0x10010061 |
631 | #define ixPCIE_FC_CPL 0x10010062 |
632 | #define ixPCIE_ERR_CNTL 0x1001006a |
633 | #define ixPCIE_RX_CNTL 0x10010070 |
634 | #define ixPCIE_RX_EXPECTED_SEQNUM 0x10010071 |
635 | #define ixPCIE_RX_VENDOR_SPECIFIC 0x10010072 |
636 | #define ixPCIE_RX_CNTL3 0x10010074 |
637 | #define ixPCIE_RX_CREDITS_ALLOCATED_P 0x10010080 |
638 | #define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x10010081 |
639 | #define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x10010082 |
640 | #define ixPCIE_LC_CNTL 0x100100a0 |
641 | #define ixPCIE_LC_CNTL2 0x100100b1 |
642 | #define ixPCIE_LC_CNTL3 0x100100b5 |
643 | #define ixPCIE_LC_CNTL4 0x100100b6 |
644 | #define ixPCIE_LC_CNTL5 0x100100b7 |
645 | #define ixPCIE_LC_BW_CHANGE_CNTL 0x100100b2 |
646 | #define ixPCIE_LC_TRAINING_CNTL 0x100100a1 |
647 | #define ixPCIE_LC_LINK_WIDTH_CNTL 0x100100a2 |
648 | #define ixPCIE_LC_N_FTS_CNTL 0x100100a3 |
649 | #define ixPCIE_LC_SPEED_CNTL 0x100100a4 |
650 | #define ixPCIE_LC_CDR_CNTL 0x100100b3 |
651 | #define ixPCIE_LC_LANE_CNTL 0x100100b4 |
652 | #define ixPCIE_LC_FORCE_COEFF 0x100100b8 |
653 | #define ixPCIE_LC_BEST_EQ_SETTINGS 0x100100b9 |
654 | #define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x100100ba |
655 | #define ixPCIE_LC_STATE0 0x100100a5 |
656 | #define ixPCIE_LC_STATE1 0x100100a6 |
657 | #define ixPCIE_LC_STATE2 0x100100a7 |
658 | #define ixPCIE_LC_STATE3 0x100100a8 |
659 | #define ixPCIE_LC_STATE4 0x100100a9 |
660 | #define ixPCIE_LC_STATE5 0x100100aa |
661 | #define ixPCIEP_STRAP_LC 0x100100c0 |
662 | #define ixPCIEP_STRAP_MISC 0x100100c1 |
663 | #define ixPCIEP_BCH_ECC_CNTL 0x100100d0 |
664 | #define mmBIF_RFE_SNOOP_REG 0x27 |
665 | #define mmBIF_RFE_WARMRST_CNTL 0x1459 |
666 | #define mmBIF_RFE_SOFTRST_CNTL 0x1441 |
667 | #define mmBIF_RFE_CLIENT_SOFTRST_TRIGGER 0x1442 |
668 | #define mmBIF_RFE_MASTER_SOFTRST_TRIGGER 0x1443 |
669 | #define mmBIF_PWDN_COMMAND 0x1444 |
670 | #define mmBIF_PWDN_STATUS 0x1445 |
671 | #define mmBIF_RFE_MST_FBU_CMDSTATUS 0x1446 |
672 | #define mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS 0x1447 |
673 | #define mmBIF_RFE_MST_BX_CMDSTATUS 0x1448 |
674 | #define mmBIF_RFE_MST_TMOUT_STATUS 0x144b |
675 | #define mmBIF_RFE_MMCFG_CNTL 0x144c |
676 | #define ixBIF_CLOCKS_BITS_IND 0x1301489 |
677 | #define ixBIF_LNCNT_RESET_IND 0x1301488 |
678 | #define ixLNCNT_CONTROL_IND 0x1301487 |
679 | #define ixNEW_REFCLKB_TIMER_IND 0x1301485 |
680 | #define ixNEW_REFCLKB_TIMER_1_IND 0x1301484 |
681 | #define ixBIF_CLK_PDWN_DELAY_TIMER_IND 0x1301483 |
682 | #define ixBIF_RESET_EN_IND 0x1301482 |
683 | #define ixBIF_PIF_TXCLK_SWITCH_TIMER_IND 0x1301481 |
684 | #define ixBIF_BACO_MSIC_IND 0x1301480 |
685 | #define ixBIF_RESET_CNTL_IND 0x1301486 |
686 | #define ixBIF_RFE_CNTL_MISC_IND 0x130148c |
687 | #define ixBIF_MEM_PG_CNTL_IND 0x130148a |
688 | #define mmNB_GBIF_INDEX 0x34 |
689 | #define mmNB_GBIF_DATA 0x35 |
690 | #define mmBIF_CLOCKS_BITS 0x1489 |
691 | #define mmBIF_LNCNT_RESET 0x1488 |
692 | #define mmLNCNT_CONTROL 0x1487 |
693 | #define mmNEW_REFCLKB_TIMER 0x1485 |
694 | #define mmNEW_REFCLKB_TIMER_1 0x1484 |
695 | #define mmBIF_CLK_PDWN_DELAY_TIMER 0x1483 |
696 | #define mmBIF_RESET_EN 0x1482 |
697 | #define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x1481 |
698 | #define mmBIF_BACO_MSIC 0x1480 |
699 | #define mmBIF_RESET_CNTL 0x1486 |
700 | #define mmBIF_RFE_CNTL_MISC 0x148c |
701 | #define mmBIF_MEM_PG_CNTL 0x148a |
702 | #define mmC_PCIE_P_INDEX 0x38 |
703 | #define mmC_PCIE_P_DATA 0x39 |
704 | #define ixD2F1_PCIE_PORT_INDEX 0x2000038 |
705 | #define ixD2F1_PCIE_PORT_DATA 0x2000039 |
706 | #define ixD2F1_PCIEP_RESERVED 0x0 |
707 | #define ixD2F1_PCIEP_SCRATCH 0x1 |
708 | #define ixD2F1_PCIEP_HW_DEBUG 0x2 |
709 | #define ixD2F1_PCIEP_PORT_CNTL 0x10 |
710 | #define ixD2F1_PCIE_TX_CNTL 0x20 |
711 | #define ixD2F1_PCIE_TX_REQUESTER_ID 0x21 |
712 | #define ixD2F1_PCIE_TX_VENDOR_SPECIFIC 0x22 |
713 | #define ixD2F1_PCIE_TX_REQUEST_NUM_CNTL 0x23 |
714 | #define ixD2F1_PCIE_TX_SEQ 0x24 |
715 | #define ixD2F1_PCIE_TX_REPLAY 0x25 |
716 | #define ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT 0x26 |
717 | #define ixD2F1_PCIE_TX_CREDITS_ADVT_P 0x30 |
718 | #define ixD2F1_PCIE_TX_CREDITS_ADVT_NP 0x31 |
719 | #define ixD2F1_PCIE_TX_CREDITS_ADVT_CPL 0x32 |
720 | #define ixD2F1_PCIE_TX_CREDITS_INIT_P 0x33 |
721 | #define ixD2F1_PCIE_TX_CREDITS_INIT_NP 0x34 |
722 | #define ixD2F1_PCIE_TX_CREDITS_INIT_CPL 0x35 |
723 | #define ixD2F1_PCIE_TX_CREDITS_STATUS 0x36 |
724 | #define ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 |
725 | #define ixD2F1_PCIE_P_PORT_LANE_STATUS 0x50 |
726 | #define ixD2F1_PCIE_FC_P 0x60 |
727 | #define ixD2F1_PCIE_FC_NP 0x61 |
728 | #define ixD2F1_PCIE_FC_CPL 0x62 |
729 | #define ixD2F1_PCIE_ERR_CNTL 0x6a |
730 | #define ixD2F1_PCIE_RX_CNTL 0x70 |
731 | #define ixD2F1_PCIE_RX_EXPECTED_SEQNUM 0x71 |
732 | #define ixD2F1_PCIE_RX_VENDOR_SPECIFIC 0x72 |
733 | #define ixD2F1_PCIE_RX_CNTL3 0x74 |
734 | #define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P 0x80 |
735 | #define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 |
736 | #define ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 |
737 | #define ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL 0x83 |
738 | #define ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION 0x84 |
739 | #define ixD2F1_PCIE_LC_CNTL 0xa0 |
740 | #define ixD2F1_PCIE_LC_CNTL2 0xb1 |
741 | #define ixD2F1_PCIE_LC_CNTL3 0xb5 |
742 | #define ixD2F1_PCIE_LC_CNTL4 0xb6 |
743 | #define ixD2F1_PCIE_LC_CNTL5 0xb7 |
744 | #define ixD2F1_PCIE_LC_CNTL6 0xbb |
745 | #define ixD2F1_PCIE_LC_BW_CHANGE_CNTL 0xb2 |
746 | #define ixD2F1_PCIE_LC_TRAINING_CNTL 0xa1 |
747 | #define ixD2F1_PCIE_LC_LINK_WIDTH_CNTL 0xa2 |
748 | #define ixD2F1_PCIE_LC_N_FTS_CNTL 0xa3 |
749 | #define ixD2F1_PCIE_LC_SPEED_CNTL 0xa4 |
750 | #define ixD2F1_PCIE_LC_CDR_CNTL 0xb3 |
751 | #define ixD2F1_PCIE_LC_LANE_CNTL 0xb4 |
752 | #define ixD2F1_PCIE_LC_FORCE_COEFF 0xb8 |
753 | #define ixD2F1_PCIE_LC_BEST_EQ_SETTINGS 0xb9 |
754 | #define ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba |
755 | #define ixD2F1_PCIE_LC_STATE0 0xa5 |
756 | #define ixD2F1_PCIE_LC_STATE1 0xa6 |
757 | #define ixD2F1_PCIE_LC_STATE2 0xa7 |
758 | #define ixD2F1_PCIE_LC_STATE3 0xa8 |
759 | #define ixD2F1_PCIE_LC_STATE4 0xa9 |
760 | #define ixD2F1_PCIE_LC_STATE5 0xaa |
761 | #define ixD2F1_PCIEP_STRAP_LC 0xc0 |
762 | #define ixD2F1_PCIEP_STRAP_MISC 0xc1 |
763 | #define ixD2F1_PCIEP_BCH_ECC_CNTL 0xd0 |
764 | #define ixD2F1_PCIEP_HPGI_PRIVATE 0xd2 |
765 | #define ixD2F1_PCIEP_HPGI 0xda |
766 | #define ixD2F1_VENDOR_ID 0x2000000 |
767 | #define ixD2F1_DEVICE_ID 0x2000000 |
768 | #define ixD2F1_COMMAND 0x2000001 |
769 | #define ixD2F1_STATUS 0x2000001 |
770 | #define ixD2F1_REVISION_ID 0x2000002 |
771 | #define ixD2F1_PROG_INTERFACE 0x2000002 |
772 | #define ixD2F1_SUB_CLASS 0x2000002 |
773 | #define ixD2F1_BASE_CLASS 0x2000002 |
774 | #define ixD2F1_CACHE_LINE 0x2000003 |
775 | #define ixD2F1_LATENCY 0x2000003 |
776 | #define 0x2000003 |
777 | #define ixD2F1_BIST 0x2000003 |
778 | #define ixD2F1_SUB_BUS_NUMBER_LATENCY 0x2000006 |
779 | #define ixD2F1_IO_BASE_LIMIT 0x2000007 |
780 | #define ixD2F1_SECONDARY_STATUS 0x2000007 |
781 | #define ixD2F1_MEM_BASE_LIMIT 0x2000008 |
782 | #define ixD2F1_PREF_BASE_LIMIT 0x2000009 |
783 | #define ixD2F1_PREF_BASE_UPPER 0x200000a |
784 | #define ixD2F1_PREF_LIMIT_UPPER 0x200000b |
785 | #define ixD2F1_IO_BASE_LIMIT_HI 0x200000c |
786 | #define ixD2F1_IRQ_BRIDGE_CNTL 0x200000f |
787 | #define ixD2F1_CAP_PTR 0x200000d |
788 | #define ixD2F1_INTERRUPT_LINE 0x200000f |
789 | #define ixD2F1_INTERRUPT_PIN 0x200000f |
790 | #define ixD2F1_EXT_BRIDGE_CNTL 0x2000010 |
791 | #define ixD2F1_PMI_CAP_LIST 0x2000014 |
792 | #define ixD2F1_PMI_CAP 0x2000014 |
793 | #define ixD2F1_PMI_STATUS_CNTL 0x2000015 |
794 | #define ixD2F1_PCIE_CAP_LIST 0x2000016 |
795 | #define ixD2F1_PCIE_CAP 0x2000016 |
796 | #define ixD2F1_DEVICE_CAP 0x2000017 |
797 | #define ixD2F1_DEVICE_CNTL 0x2000018 |
798 | #define ixD2F1_DEVICE_STATUS 0x2000018 |
799 | #define ixD2F1_LINK_CAP 0x2000019 |
800 | #define ixD2F1_LINK_CNTL 0x200001a |
801 | #define ixD2F1_LINK_STATUS 0x200001a |
802 | #define ixD2F1_SLOT_CAP 0x200001b |
803 | #define ixD2F1_SLOT_CNTL 0x200001c |
804 | #define ixD2F1_SLOT_STATUS 0x200001c |
805 | #define ixD2F1_ROOT_CNTL 0x200001d |
806 | #define ixD2F1_ROOT_CAP 0x200001d |
807 | #define ixD2F1_ROOT_STATUS 0x200001e |
808 | #define ixD2F1_DEVICE_CAP2 0x200001f |
809 | #define ixD2F1_DEVICE_CNTL2 0x2000020 |
810 | #define ixD2F1_DEVICE_STATUS2 0x2000020 |
811 | #define ixD2F1_LINK_CAP2 0x2000021 |
812 | #define ixD2F1_LINK_CNTL2 0x2000022 |
813 | #define ixD2F1_LINK_STATUS2 0x2000022 |
814 | #define ixD2F1_SLOT_CAP2 0x2000023 |
815 | #define ixD2F1_SLOT_CNTL2 0x2000024 |
816 | #define ixD2F1_SLOT_STATUS2 0x2000024 |
817 | #define ixD2F1_MSI_CAP_LIST 0x2000028 |
818 | #define ixD2F1_MSI_MSG_CNTL 0x2000028 |
819 | #define ixD2F1_MSI_MSG_ADDR_LO 0x2000029 |
820 | #define ixD2F1_MSI_MSG_ADDR_HI 0x200002a |
821 | #define ixD2F1_MSI_MSG_DATA_64 0x200002b |
822 | #define ixD2F1_MSI_MSG_DATA 0x200002a |
823 | #define ixD2F1_SSID_CAP_LIST 0x2000030 |
824 | #define ixD2F1_SSID_CAP 0x2000031 |
825 | #define ixD2F1_MSI_MAP_CAP_LIST 0x2000032 |
826 | #define ixD2F1_MSI_MAP_CAP 0x2000032 |
827 | #define ixD2F1_MSI_MAP_ADDR_LO 0x2000033 |
828 | #define ixD2F1_MSI_MAP_ADDR_HI 0x2000034 |
829 | #define ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x2000040 |
830 | #define ixD2F1_PCIE_VENDOR_SPECIFIC_HDR 0x2000041 |
831 | #define ixD2F1_PCIE_VENDOR_SPECIFIC1 0x2000042 |
832 | #define ixD2F1_PCIE_VENDOR_SPECIFIC2 0x2000043 |
833 | #define ixD2F1_PCIE_VC_ENH_CAP_LIST 0x2000044 |
834 | #define ixD2F1_PCIE_PORT_VC_CAP_REG1 0x2000045 |
835 | #define ixD2F1_PCIE_PORT_VC_CAP_REG2 0x2000046 |
836 | #define ixD2F1_PCIE_PORT_VC_CNTL 0x2000047 |
837 | #define ixD2F1_PCIE_PORT_VC_STATUS 0x2000047 |
838 | #define ixD2F1_PCIE_VC0_RESOURCE_CAP 0x2000048 |
839 | #define ixD2F1_PCIE_VC0_RESOURCE_CNTL 0x2000049 |
840 | #define ixD2F1_PCIE_VC0_RESOURCE_STATUS 0x200004a |
841 | #define ixD2F1_PCIE_VC1_RESOURCE_CAP 0x200004b |
842 | #define ixD2F1_PCIE_VC1_RESOURCE_CNTL 0x200004c |
843 | #define ixD2F1_PCIE_VC1_RESOURCE_STATUS 0x200004d |
844 | #define ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x2000050 |
845 | #define ixD2F1_PCIE_DEV_SERIAL_NUM_DW1 0x2000051 |
846 | #define ixD2F1_PCIE_DEV_SERIAL_NUM_DW2 0x2000052 |
847 | #define ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x2000054 |
848 | #define ixD2F1_PCIE_UNCORR_ERR_STATUS 0x2000055 |
849 | #define ixD2F1_PCIE_UNCORR_ERR_MASK 0x2000056 |
850 | #define ixD2F1_PCIE_UNCORR_ERR_SEVERITY 0x2000057 |
851 | #define ixD2F1_PCIE_CORR_ERR_STATUS 0x2000058 |
852 | #define ixD2F1_PCIE_CORR_ERR_MASK 0x2000059 |
853 | #define ixD2F1_PCIE_ADV_ERR_CAP_CNTL 0x200005a |
854 | #define ixD2F1_PCIE_HDR_LOG0 0x200005b |
855 | #define ixD2F1_PCIE_HDR_LOG1 0x200005c |
856 | #define ixD2F1_PCIE_HDR_LOG2 0x200005d |
857 | #define ixD2F1_PCIE_HDR_LOG3 0x200005e |
858 | #define ixD2F1_PCIE_ROOT_ERR_CMD 0x200005f |
859 | #define ixD2F1_PCIE_ROOT_ERR_STATUS 0x2000060 |
860 | #define ixD2F1_PCIE_ERR_SRC_ID 0x2000061 |
861 | #define ixD2F1_PCIE_TLP_PREFIX_LOG0 0x2000062 |
862 | #define ixD2F1_PCIE_TLP_PREFIX_LOG1 0x2000063 |
863 | #define ixD2F1_PCIE_TLP_PREFIX_LOG2 0x2000064 |
864 | #define ixD2F1_PCIE_TLP_PREFIX_LOG3 0x2000065 |
865 | #define ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST 0x200009c |
866 | #define ixD2F1_PCIE_LINK_CNTL3 0x200009d |
867 | #define ixD2F1_PCIE_LANE_ERROR_STATUS 0x200009e |
868 | #define ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL 0x200009f |
869 | #define ixD2F1_PCIE_LANE_1_EQUALIZATION_CNTL 0x200009f |
870 | #define ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL 0x20000a0 |
871 | #define ixD2F1_PCIE_LANE_3_EQUALIZATION_CNTL 0x20000a0 |
872 | #define ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL 0x20000a1 |
873 | #define ixD2F1_PCIE_LANE_5_EQUALIZATION_CNTL 0x20000a1 |
874 | #define ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL 0x20000a2 |
875 | #define ixD2F1_PCIE_LANE_7_EQUALIZATION_CNTL 0x20000a2 |
876 | #define ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL 0x20000a3 |
877 | #define ixD2F1_PCIE_LANE_9_EQUALIZATION_CNTL 0x20000a3 |
878 | #define ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL 0x20000a4 |
879 | #define ixD2F1_PCIE_LANE_11_EQUALIZATION_CNTL 0x20000a4 |
880 | #define ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL 0x20000a5 |
881 | #define ixD2F1_PCIE_LANE_13_EQUALIZATION_CNTL 0x20000a5 |
882 | #define ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL 0x20000a6 |
883 | #define ixD2F1_PCIE_LANE_15_EQUALIZATION_CNTL 0x20000a6 |
884 | #define ixD2F1_PCIE_ACS_ENH_CAP_LIST 0x20000a8 |
885 | #define ixD2F1_PCIE_ACS_CAP 0x20000a9 |
886 | #define ixD2F1_PCIE_ACS_CNTL 0x20000a9 |
887 | #define ixD2F1_PCIE_MC_ENH_CAP_LIST 0x20000bc |
888 | #define ixD2F1_PCIE_MC_CAP 0x20000bd |
889 | #define ixD2F1_PCIE_MC_CNTL 0x20000bd |
890 | #define ixD2F1_PCIE_MC_ADDR0 0x20000be |
891 | #define ixD2F1_PCIE_MC_ADDR1 0x20000bf |
892 | #define ixD2F1_PCIE_MC_RCV0 0x20000c0 |
893 | #define ixD2F1_PCIE_MC_RCV1 0x20000c1 |
894 | #define ixD2F1_PCIE_MC_BLOCK_ALL0 0x20000c2 |
895 | #define ixD2F1_PCIE_MC_BLOCK_ALL1 0x20000c3 |
896 | #define ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x20000c4 |
897 | #define ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x20000c5 |
898 | #define ixD2F1_PCIE_MC_OVERLAY_BAR0 0x20000c6 |
899 | #define ixD2F1_PCIE_MC_OVERLAY_BAR1 0x20000c7 |
900 | #define ixD2F2_PCIE_PORT_INDEX 0x3000038 |
901 | #define ixD2F2_PCIE_PORT_DATA 0x3000039 |
902 | #define ixD2F2_PCIEP_RESERVED 0x0 |
903 | #define ixD2F2_PCIEP_SCRATCH 0x1 |
904 | #define ixD2F2_PCIEP_HW_DEBUG 0x2 |
905 | #define ixD2F2_PCIEP_PORT_CNTL 0x10 |
906 | #define ixD2F2_PCIE_TX_CNTL 0x20 |
907 | #define ixD2F2_PCIE_TX_REQUESTER_ID 0x21 |
908 | #define ixD2F2_PCIE_TX_VENDOR_SPECIFIC 0x22 |
909 | #define ixD2F2_PCIE_TX_REQUEST_NUM_CNTL 0x23 |
910 | #define ixD2F2_PCIE_TX_SEQ 0x24 |
911 | #define ixD2F2_PCIE_TX_REPLAY 0x25 |
912 | #define ixD2F2_PCIE_TX_ACK_LATENCY_LIMIT 0x26 |
913 | #define ixD2F2_PCIE_TX_CREDITS_ADVT_P 0x30 |
914 | #define ixD2F2_PCIE_TX_CREDITS_ADVT_NP 0x31 |
915 | #define ixD2F2_PCIE_TX_CREDITS_ADVT_CPL 0x32 |
916 | #define ixD2F2_PCIE_TX_CREDITS_INIT_P 0x33 |
917 | #define ixD2F2_PCIE_TX_CREDITS_INIT_NP 0x34 |
918 | #define ixD2F2_PCIE_TX_CREDITS_INIT_CPL 0x35 |
919 | #define ixD2F2_PCIE_TX_CREDITS_STATUS 0x36 |
920 | #define ixD2F2_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 |
921 | #define ixD2F2_PCIE_P_PORT_LANE_STATUS 0x50 |
922 | #define ixD2F2_PCIE_FC_P 0x60 |
923 | #define ixD2F2_PCIE_FC_NP 0x61 |
924 | #define ixD2F2_PCIE_FC_CPL 0x62 |
925 | #define ixD2F2_PCIE_ERR_CNTL 0x6a |
926 | #define ixD2F2_PCIE_RX_CNTL 0x70 |
927 | #define ixD2F2_PCIE_RX_EXPECTED_SEQNUM 0x71 |
928 | #define ixD2F2_PCIE_RX_VENDOR_SPECIFIC 0x72 |
929 | #define ixD2F2_PCIE_RX_CNTL3 0x74 |
930 | #define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_P 0x80 |
931 | #define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 |
932 | #define ixD2F2_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 |
933 | #define ixD2F2_PCIEP_ERROR_INJECT_PHYSICAL 0x83 |
934 | #define ixD2F2_PCIEP_ERROR_INJECT_TRANSACTION 0x84 |
935 | #define ixD2F2_PCIE_LC_CNTL 0xa0 |
936 | #define ixD2F2_PCIE_LC_CNTL2 0xb1 |
937 | #define ixD2F2_PCIE_LC_CNTL3 0xb5 |
938 | #define ixD2F2_PCIE_LC_CNTL4 0xb6 |
939 | #define ixD2F2_PCIE_LC_CNTL5 0xb7 |
940 | #define ixD2F2_PCIE_LC_CNTL6 0xbb |
941 | #define ixD2F2_PCIE_LC_BW_CHANGE_CNTL 0xb2 |
942 | #define ixD2F2_PCIE_LC_TRAINING_CNTL 0xa1 |
943 | #define ixD2F2_PCIE_LC_LINK_WIDTH_CNTL 0xa2 |
944 | #define ixD2F2_PCIE_LC_N_FTS_CNTL 0xa3 |
945 | #define ixD2F2_PCIE_LC_SPEED_CNTL 0xa4 |
946 | #define ixD2F2_PCIE_LC_CDR_CNTL 0xb3 |
947 | #define ixD2F2_PCIE_LC_LANE_CNTL 0xb4 |
948 | #define ixD2F2_PCIE_LC_FORCE_COEFF 0xb8 |
949 | #define ixD2F2_PCIE_LC_BEST_EQ_SETTINGS 0xb9 |
950 | #define ixD2F2_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba |
951 | #define ixD2F2_PCIE_LC_STATE0 0xa5 |
952 | #define ixD2F2_PCIE_LC_STATE1 0xa6 |
953 | #define ixD2F2_PCIE_LC_STATE2 0xa7 |
954 | #define ixD2F2_PCIE_LC_STATE3 0xa8 |
955 | #define ixD2F2_PCIE_LC_STATE4 0xa9 |
956 | #define ixD2F2_PCIE_LC_STATE5 0xaa |
957 | #define ixD2F2_PCIEP_STRAP_LC 0xc0 |
958 | #define ixD2F2_PCIEP_STRAP_MISC 0xc1 |
959 | #define ixD2F2_PCIEP_BCH_ECC_CNTL 0xd0 |
960 | #define ixD2F2_PCIEP_HPGI_PRIVATE 0xd2 |
961 | #define ixD2F2_PCIEP_HPGI 0xda |
962 | #define ixD2F2_VENDOR_ID 0x3000000 |
963 | #define ixD2F2_DEVICE_ID 0x3000000 |
964 | #define ixD2F2_COMMAND 0x3000001 |
965 | #define ixD2F2_STATUS 0x3000001 |
966 | #define ixD2F2_REVISION_ID 0x3000002 |
967 | #define ixD2F2_PROG_INTERFACE 0x3000002 |
968 | #define ixD2F2_SUB_CLASS 0x3000002 |
969 | #define ixD2F2_BASE_CLASS 0x3000002 |
970 | #define ixD2F2_CACHE_LINE 0x3000003 |
971 | #define ixD2F2_LATENCY 0x3000003 |
972 | #define 0x3000003 |
973 | #define ixD2F2_BIST 0x3000003 |
974 | #define ixD2F2_SUB_BUS_NUMBER_LATENCY 0x3000006 |
975 | #define ixD2F2_IO_BASE_LIMIT 0x3000007 |
976 | #define ixD2F2_SECONDARY_STATUS 0x3000007 |
977 | #define ixD2F2_MEM_BASE_LIMIT 0x3000008 |
978 | #define ixD2F2_PREF_BASE_LIMIT 0x3000009 |
979 | #define ixD2F2_PREF_BASE_UPPER 0x300000a |
980 | #define ixD2F2_PREF_LIMIT_UPPER 0x300000b |
981 | #define ixD2F2_IO_BASE_LIMIT_HI 0x300000c |
982 | #define ixD2F2_IRQ_BRIDGE_CNTL 0x300000f |
983 | #define ixD2F2_CAP_PTR 0x300000d |
984 | #define ixD2F2_INTERRUPT_LINE 0x300000f |
985 | #define ixD2F2_INTERRUPT_PIN 0x300000f |
986 | #define ixD2F2_EXT_BRIDGE_CNTL 0x3000010 |
987 | #define ixD2F2_PMI_CAP_LIST 0x3000014 |
988 | #define ixD2F2_PMI_CAP 0x3000014 |
989 | #define ixD2F2_PMI_STATUS_CNTL 0x3000015 |
990 | #define ixD2F2_PCIE_CAP_LIST 0x3000016 |
991 | #define ixD2F2_PCIE_CAP 0x3000016 |
992 | #define ixD2F2_DEVICE_CAP 0x3000017 |
993 | #define ixD2F2_DEVICE_CNTL 0x3000018 |
994 | #define ixD2F2_DEVICE_STATUS 0x3000018 |
995 | #define ixD2F2_LINK_CAP 0x3000019 |
996 | #define ixD2F2_LINK_CNTL 0x300001a |
997 | #define ixD2F2_LINK_STATUS 0x300001a |
998 | #define ixD2F2_SLOT_CAP 0x300001b |
999 | #define ixD2F2_SLOT_CNTL 0x300001c |
1000 | #define ixD2F2_SLOT_STATUS 0x300001c |
1001 | #define ixD2F2_ROOT_CNTL 0x300001d |
1002 | #define ixD2F2_ROOT_CAP 0x300001d |
1003 | #define ixD2F2_ROOT_STATUS 0x300001e |
1004 | #define ixD2F2_DEVICE_CAP2 0x300001f |
1005 | #define ixD2F2_DEVICE_CNTL2 0x3000020 |
1006 | #define ixD2F2_DEVICE_STATUS2 0x3000020 |
1007 | #define ixD2F2_LINK_CAP2 0x3000021 |
1008 | #define ixD2F2_LINK_CNTL2 0x3000022 |
1009 | #define ixD2F2_LINK_STATUS2 0x3000022 |
1010 | #define ixD2F2_SLOT_CAP2 0x3000023 |
1011 | #define ixD2F2_SLOT_CNTL2 0x3000024 |
1012 | #define ixD2F2_SLOT_STATUS2 0x3000024 |
1013 | #define ixD2F2_MSI_CAP_LIST 0x3000028 |
1014 | #define ixD2F2_MSI_MSG_CNTL 0x3000028 |
1015 | #define ixD2F2_MSI_MSG_ADDR_LO 0x3000029 |
1016 | #define ixD2F2_MSI_MSG_ADDR_HI 0x300002a |
1017 | #define ixD2F2_MSI_MSG_DATA_64 0x300002b |
1018 | #define ixD2F2_MSI_MSG_DATA 0x300002a |
1019 | #define ixD2F2_SSID_CAP_LIST 0x3000030 |
1020 | #define ixD2F2_SSID_CAP 0x3000031 |
1021 | #define ixD2F2_MSI_MAP_CAP_LIST 0x3000032 |
1022 | #define ixD2F2_MSI_MAP_CAP 0x3000032 |
1023 | #define ixD2F2_MSI_MAP_ADDR_LO 0x3000033 |
1024 | #define ixD2F2_MSI_MAP_ADDR_HI 0x3000034 |
1025 | #define ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x3000040 |
1026 | #define ixD2F2_PCIE_VENDOR_SPECIFIC_HDR 0x3000041 |
1027 | #define ixD2F2_PCIE_VENDOR_SPECIFIC1 0x3000042 |
1028 | #define ixD2F2_PCIE_VENDOR_SPECIFIC2 0x3000043 |
1029 | #define ixD2F2_PCIE_VC_ENH_CAP_LIST 0x3000044 |
1030 | #define ixD2F2_PCIE_PORT_VC_CAP_REG1 0x3000045 |
1031 | #define ixD2F2_PCIE_PORT_VC_CAP_REG2 0x3000046 |
1032 | #define ixD2F2_PCIE_PORT_VC_CNTL 0x3000047 |
1033 | #define ixD2F2_PCIE_PORT_VC_STATUS 0x3000047 |
1034 | #define ixD2F2_PCIE_VC0_RESOURCE_CAP 0x3000048 |
1035 | #define ixD2F2_PCIE_VC0_RESOURCE_CNTL 0x3000049 |
1036 | #define ixD2F2_PCIE_VC0_RESOURCE_STATUS 0x300004a |
1037 | #define ixD2F2_PCIE_VC1_RESOURCE_CAP 0x300004b |
1038 | #define ixD2F2_PCIE_VC1_RESOURCE_CNTL 0x300004c |
1039 | #define ixD2F2_PCIE_VC1_RESOURCE_STATUS 0x300004d |
1040 | #define ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x3000050 |
1041 | #define ixD2F2_PCIE_DEV_SERIAL_NUM_DW1 0x3000051 |
1042 | #define ixD2F2_PCIE_DEV_SERIAL_NUM_DW2 0x3000052 |
1043 | #define ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x3000054 |
1044 | #define ixD2F2_PCIE_UNCORR_ERR_STATUS 0x3000055 |
1045 | #define ixD2F2_PCIE_UNCORR_ERR_MASK 0x3000056 |
1046 | #define ixD2F2_PCIE_UNCORR_ERR_SEVERITY 0x3000057 |
1047 | #define ixD2F2_PCIE_CORR_ERR_STATUS 0x3000058 |
1048 | #define ixD2F2_PCIE_CORR_ERR_MASK 0x3000059 |
1049 | #define ixD2F2_PCIE_ADV_ERR_CAP_CNTL 0x300005a |
1050 | #define ixD2F2_PCIE_HDR_LOG0 0x300005b |
1051 | #define ixD2F2_PCIE_HDR_LOG1 0x300005c |
1052 | #define ixD2F2_PCIE_HDR_LOG2 0x300005d |
1053 | #define ixD2F2_PCIE_HDR_LOG3 0x300005e |
1054 | #define ixD2F2_PCIE_ROOT_ERR_CMD 0x300005f |
1055 | #define ixD2F2_PCIE_ROOT_ERR_STATUS 0x3000060 |
1056 | #define ixD2F2_PCIE_ERR_SRC_ID 0x3000061 |
1057 | #define ixD2F2_PCIE_TLP_PREFIX_LOG0 0x3000062 |
1058 | #define ixD2F2_PCIE_TLP_PREFIX_LOG1 0x3000063 |
1059 | #define ixD2F2_PCIE_TLP_PREFIX_LOG2 0x3000064 |
1060 | #define ixD2F2_PCIE_TLP_PREFIX_LOG3 0x3000065 |
1061 | #define ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST 0x300009c |
1062 | #define ixD2F2_PCIE_LINK_CNTL3 0x300009d |
1063 | #define ixD2F2_PCIE_LANE_ERROR_STATUS 0x300009e |
1064 | #define ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL 0x300009f |
1065 | #define ixD2F2_PCIE_LANE_1_EQUALIZATION_CNTL 0x300009f |
1066 | #define ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL 0x30000a0 |
1067 | #define ixD2F2_PCIE_LANE_3_EQUALIZATION_CNTL 0x30000a0 |
1068 | #define ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL 0x30000a1 |
1069 | #define ixD2F2_PCIE_LANE_5_EQUALIZATION_CNTL 0x30000a1 |
1070 | #define ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL 0x30000a2 |
1071 | #define ixD2F2_PCIE_LANE_7_EQUALIZATION_CNTL 0x30000a2 |
1072 | #define ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL 0x30000a3 |
1073 | #define ixD2F2_PCIE_LANE_9_EQUALIZATION_CNTL 0x30000a3 |
1074 | #define ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL 0x30000a4 |
1075 | #define ixD2F2_PCIE_LANE_11_EQUALIZATION_CNTL 0x30000a4 |
1076 | #define ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL 0x30000a5 |
1077 | #define ixD2F2_PCIE_LANE_13_EQUALIZATION_CNTL 0x30000a5 |
1078 | #define ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL 0x30000a6 |
1079 | #define ixD2F2_PCIE_LANE_15_EQUALIZATION_CNTL 0x30000a6 |
1080 | #define ixD2F2_PCIE_ACS_ENH_CAP_LIST 0x30000a8 |
1081 | #define ixD2F2_PCIE_ACS_CAP 0x30000a9 |
1082 | #define ixD2F2_PCIE_ACS_CNTL 0x30000a9 |
1083 | #define ixD2F2_PCIE_MC_ENH_CAP_LIST 0x30000bc |
1084 | #define ixD2F2_PCIE_MC_CAP 0x30000bd |
1085 | #define ixD2F2_PCIE_MC_CNTL 0x30000bd |
1086 | #define ixD2F2_PCIE_MC_ADDR0 0x30000be |
1087 | #define ixD2F2_PCIE_MC_ADDR1 0x30000bf |
1088 | #define ixD2F2_PCIE_MC_RCV0 0x30000c0 |
1089 | #define ixD2F2_PCIE_MC_RCV1 0x30000c1 |
1090 | #define ixD2F2_PCIE_MC_BLOCK_ALL0 0x30000c2 |
1091 | #define ixD2F2_PCIE_MC_BLOCK_ALL1 0x30000c3 |
1092 | #define ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x30000c4 |
1093 | #define ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x30000c5 |
1094 | #define ixD2F2_PCIE_MC_OVERLAY_BAR0 0x30000c6 |
1095 | #define ixD2F2_PCIE_MC_OVERLAY_BAR1 0x30000c7 |
1096 | #define ixD2F3_PCIE_PORT_INDEX 0x4000038 |
1097 | #define ixD2F3_PCIE_PORT_DATA 0x4000039 |
1098 | #define ixD2F3_PCIEP_RESERVED 0x0 |
1099 | #define ixD2F3_PCIEP_SCRATCH 0x1 |
1100 | #define ixD2F3_PCIEP_HW_DEBUG 0x2 |
1101 | #define ixD2F3_PCIEP_PORT_CNTL 0x10 |
1102 | #define ixD2F3_PCIE_TX_CNTL 0x20 |
1103 | #define ixD2F3_PCIE_TX_REQUESTER_ID 0x21 |
1104 | #define ixD2F3_PCIE_TX_VENDOR_SPECIFIC 0x22 |
1105 | #define ixD2F3_PCIE_TX_REQUEST_NUM_CNTL 0x23 |
1106 | #define ixD2F3_PCIE_TX_SEQ 0x24 |
1107 | #define ixD2F3_PCIE_TX_REPLAY 0x25 |
1108 | #define ixD2F3_PCIE_TX_ACK_LATENCY_LIMIT 0x26 |
1109 | #define ixD2F3_PCIE_TX_CREDITS_ADVT_P 0x30 |
1110 | #define ixD2F3_PCIE_TX_CREDITS_ADVT_NP 0x31 |
1111 | #define ixD2F3_PCIE_TX_CREDITS_ADVT_CPL 0x32 |
1112 | #define ixD2F3_PCIE_TX_CREDITS_INIT_P 0x33 |
1113 | #define ixD2F3_PCIE_TX_CREDITS_INIT_NP 0x34 |
1114 | #define ixD2F3_PCIE_TX_CREDITS_INIT_CPL 0x35 |
1115 | #define ixD2F3_PCIE_TX_CREDITS_STATUS 0x36 |
1116 | #define ixD2F3_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 |
1117 | #define ixD2F3_PCIE_P_PORT_LANE_STATUS 0x50 |
1118 | #define ixD2F3_PCIE_FC_P 0x60 |
1119 | #define ixD2F3_PCIE_FC_NP 0x61 |
1120 | #define ixD2F3_PCIE_FC_CPL 0x62 |
1121 | #define ixD2F3_PCIE_ERR_CNTL 0x6a |
1122 | #define ixD2F3_PCIE_RX_CNTL 0x70 |
1123 | #define ixD2F3_PCIE_RX_EXPECTED_SEQNUM 0x71 |
1124 | #define ixD2F3_PCIE_RX_VENDOR_SPECIFIC 0x72 |
1125 | #define ixD2F3_PCIE_RX_CNTL3 0x74 |
1126 | #define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_P 0x80 |
1127 | #define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 |
1128 | #define ixD2F3_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 |
1129 | #define ixD2F3_PCIEP_ERROR_INJECT_PHYSICAL 0x83 |
1130 | #define ixD2F3_PCIEP_ERROR_INJECT_TRANSACTION 0x84 |
1131 | #define ixD2F3_PCIE_LC_CNTL 0xa0 |
1132 | #define ixD2F3_PCIE_LC_CNTL2 0xb1 |
1133 | #define ixD2F3_PCIE_LC_CNTL3 0xb5 |
1134 | #define ixD2F3_PCIE_LC_CNTL4 0xb6 |
1135 | #define ixD2F3_PCIE_LC_CNTL5 0xb7 |
1136 | #define ixD2F3_PCIE_LC_CNTL6 0xbb |
1137 | #define ixD2F3_PCIE_LC_BW_CHANGE_CNTL 0xb2 |
1138 | #define ixD2F3_PCIE_LC_TRAINING_CNTL 0xa1 |
1139 | #define ixD2F3_PCIE_LC_LINK_WIDTH_CNTL 0xa2 |
1140 | #define ixD2F3_PCIE_LC_N_FTS_CNTL 0xa3 |
1141 | #define ixD2F3_PCIE_LC_SPEED_CNTL 0xa4 |
1142 | #define ixD2F3_PCIE_LC_CDR_CNTL 0xb3 |
1143 | #define ixD2F3_PCIE_LC_LANE_CNTL 0xb4 |
1144 | #define ixD2F3_PCIE_LC_FORCE_COEFF 0xb8 |
1145 | #define ixD2F3_PCIE_LC_BEST_EQ_SETTINGS 0xb9 |
1146 | #define ixD2F3_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba |
1147 | #define ixD2F3_PCIE_LC_STATE0 0xa5 |
1148 | #define ixD2F3_PCIE_LC_STATE1 0xa6 |
1149 | #define ixD2F3_PCIE_LC_STATE2 0xa7 |
1150 | #define ixD2F3_PCIE_LC_STATE3 0xa8 |
1151 | #define ixD2F3_PCIE_LC_STATE4 0xa9 |
1152 | #define ixD2F3_PCIE_LC_STATE5 0xaa |
1153 | #define ixD2F3_PCIEP_STRAP_LC 0xc0 |
1154 | #define ixD2F3_PCIEP_STRAP_MISC 0xc1 |
1155 | #define ixD2F3_PCIEP_BCH_ECC_CNTL 0xd0 |
1156 | #define ixD2F3_PCIEP_HPGI_PRIVATE 0xd2 |
1157 | #define ixD2F3_PCIEP_HPGI 0xda |
1158 | #define ixD2F3_VENDOR_ID 0x4000000 |
1159 | #define ixD2F3_DEVICE_ID 0x4000000 |
1160 | #define ixD2F3_COMMAND 0x4000001 |
1161 | #define ixD2F3_STATUS 0x4000001 |
1162 | #define ixD2F3_REVISION_ID 0x4000002 |
1163 | #define ixD2F3_PROG_INTERFACE 0x4000002 |
1164 | #define ixD2F3_SUB_CLASS 0x4000002 |
1165 | #define ixD2F3_BASE_CLASS 0x4000002 |
1166 | #define ixD2F3_CACHE_LINE 0x4000003 |
1167 | #define ixD2F3_LATENCY 0x4000003 |
1168 | #define 0x4000003 |
1169 | #define ixD2F3_BIST 0x4000003 |
1170 | #define ixD2F3_SUB_BUS_NUMBER_LATENCY 0x4000006 |
1171 | #define ixD2F3_IO_BASE_LIMIT 0x4000007 |
1172 | #define ixD2F3_SECONDARY_STATUS 0x4000007 |
1173 | #define ixD2F3_MEM_BASE_LIMIT 0x4000008 |
1174 | #define ixD2F3_PREF_BASE_LIMIT 0x4000009 |
1175 | #define ixD2F3_PREF_BASE_UPPER 0x400000a |
1176 | #define ixD2F3_PREF_LIMIT_UPPER 0x400000b |
1177 | #define ixD2F3_IO_BASE_LIMIT_HI 0x400000c |
1178 | #define ixD2F3_IRQ_BRIDGE_CNTL 0x400000f |
1179 | #define ixD2F3_CAP_PTR 0x400000d |
1180 | #define ixD2F3_INTERRUPT_LINE 0x400000f |
1181 | #define ixD2F3_INTERRUPT_PIN 0x400000f |
1182 | #define ixD2F3_EXT_BRIDGE_CNTL 0x4000010 |
1183 | #define ixD2F3_PMI_CAP_LIST 0x4000014 |
1184 | #define ixD2F3_PMI_CAP 0x4000014 |
1185 | #define ixD2F3_PMI_STATUS_CNTL 0x4000015 |
1186 | #define ixD2F3_PCIE_CAP_LIST 0x4000016 |
1187 | #define ixD2F3_PCIE_CAP 0x4000016 |
1188 | #define ixD2F3_DEVICE_CAP 0x4000017 |
1189 | #define ixD2F3_DEVICE_CNTL 0x4000018 |
1190 | #define ixD2F3_DEVICE_STATUS 0x4000018 |
1191 | #define ixD2F3_LINK_CAP 0x4000019 |
1192 | #define ixD2F3_LINK_CNTL 0x400001a |
1193 | #define ixD2F3_LINK_STATUS 0x400001a |
1194 | #define ixD2F3_SLOT_CAP 0x400001b |
1195 | #define ixD2F3_SLOT_CNTL 0x400001c |
1196 | #define ixD2F3_SLOT_STATUS 0x400001c |
1197 | #define ixD2F3_ROOT_CNTL 0x400001d |
1198 | #define ixD2F3_ROOT_CAP 0x400001d |
1199 | #define ixD2F3_ROOT_STATUS 0x400001e |
1200 | #define ixD2F3_DEVICE_CAP2 0x400001f |
1201 | #define ixD2F3_DEVICE_CNTL2 0x4000020 |
1202 | #define ixD2F3_DEVICE_STATUS2 0x4000020 |
1203 | #define ixD2F3_LINK_CAP2 0x4000021 |
1204 | #define ixD2F3_LINK_CNTL2 0x4000022 |
1205 | #define ixD2F3_LINK_STATUS2 0x4000022 |
1206 | #define ixD2F3_SLOT_CAP2 0x4000023 |
1207 | #define ixD2F3_SLOT_CNTL2 0x4000024 |
1208 | #define ixD2F3_SLOT_STATUS2 0x4000024 |
1209 | #define ixD2F3_MSI_CAP_LIST 0x4000028 |
1210 | #define ixD2F3_MSI_MSG_CNTL 0x4000028 |
1211 | #define ixD2F3_MSI_MSG_ADDR_LO 0x4000029 |
1212 | #define ixD2F3_MSI_MSG_ADDR_HI 0x400002a |
1213 | #define ixD2F3_MSI_MSG_DATA_64 0x400002b |
1214 | #define ixD2F3_MSI_MSG_DATA 0x400002a |
1215 | #define ixD2F3_SSID_CAP_LIST 0x4000030 |
1216 | #define ixD2F3_SSID_CAP 0x4000031 |
1217 | #define ixD2F3_MSI_MAP_CAP_LIST 0x4000032 |
1218 | #define ixD2F3_MSI_MAP_CAP 0x4000032 |
1219 | #define ixD2F3_MSI_MAP_ADDR_LO 0x4000033 |
1220 | #define ixD2F3_MSI_MAP_ADDR_HI 0x4000034 |
1221 | #define ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x4000040 |
1222 | #define ixD2F3_PCIE_VENDOR_SPECIFIC_HDR 0x4000041 |
1223 | #define ixD2F3_PCIE_VENDOR_SPECIFIC1 0x4000042 |
1224 | #define ixD2F3_PCIE_VENDOR_SPECIFIC2 0x4000043 |
1225 | #define ixD2F3_PCIE_VC_ENH_CAP_LIST 0x4000044 |
1226 | #define ixD2F3_PCIE_PORT_VC_CAP_REG1 0x4000045 |
1227 | #define ixD2F3_PCIE_PORT_VC_CAP_REG2 0x4000046 |
1228 | #define ixD2F3_PCIE_PORT_VC_CNTL 0x4000047 |
1229 | #define ixD2F3_PCIE_PORT_VC_STATUS 0x4000047 |
1230 | #define ixD2F3_PCIE_VC0_RESOURCE_CAP 0x4000048 |
1231 | #define ixD2F3_PCIE_VC0_RESOURCE_CNTL 0x4000049 |
1232 | #define ixD2F3_PCIE_VC0_RESOURCE_STATUS 0x400004a |
1233 | #define ixD2F3_PCIE_VC1_RESOURCE_CAP 0x400004b |
1234 | #define ixD2F3_PCIE_VC1_RESOURCE_CNTL 0x400004c |
1235 | #define ixD2F3_PCIE_VC1_RESOURCE_STATUS 0x400004d |
1236 | #define ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x4000050 |
1237 | #define ixD2F3_PCIE_DEV_SERIAL_NUM_DW1 0x4000051 |
1238 | #define ixD2F3_PCIE_DEV_SERIAL_NUM_DW2 0x4000052 |
1239 | #define ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x4000054 |
1240 | #define ixD2F3_PCIE_UNCORR_ERR_STATUS 0x4000055 |
1241 | #define ixD2F3_PCIE_UNCORR_ERR_MASK 0x4000056 |
1242 | #define ixD2F3_PCIE_UNCORR_ERR_SEVERITY 0x4000057 |
1243 | #define ixD2F3_PCIE_CORR_ERR_STATUS 0x4000058 |
1244 | #define ixD2F3_PCIE_CORR_ERR_MASK 0x4000059 |
1245 | #define ixD2F3_PCIE_ADV_ERR_CAP_CNTL 0x400005a |
1246 | #define ixD2F3_PCIE_HDR_LOG0 0x400005b |
1247 | #define ixD2F3_PCIE_HDR_LOG1 0x400005c |
1248 | #define ixD2F3_PCIE_HDR_LOG2 0x400005d |
1249 | #define ixD2F3_PCIE_HDR_LOG3 0x400005e |
1250 | #define ixD2F3_PCIE_ROOT_ERR_CMD 0x400005f |
1251 | #define ixD2F3_PCIE_ROOT_ERR_STATUS 0x4000060 |
1252 | #define ixD2F3_PCIE_ERR_SRC_ID 0x4000061 |
1253 | #define ixD2F3_PCIE_TLP_PREFIX_LOG0 0x4000062 |
1254 | #define ixD2F3_PCIE_TLP_PREFIX_LOG1 0x4000063 |
1255 | #define ixD2F3_PCIE_TLP_PREFIX_LOG2 0x4000064 |
1256 | #define ixD2F3_PCIE_TLP_PREFIX_LOG3 0x4000065 |
1257 | #define ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST 0x400009c |
1258 | #define ixD2F3_PCIE_LINK_CNTL3 0x400009d |
1259 | #define ixD2F3_PCIE_LANE_ERROR_STATUS 0x400009e |
1260 | #define ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL 0x400009f |
1261 | #define ixD2F3_PCIE_LANE_1_EQUALIZATION_CNTL 0x400009f |
1262 | #define ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL 0x40000a0 |
1263 | #define ixD2F3_PCIE_LANE_3_EQUALIZATION_CNTL 0x40000a0 |
1264 | #define ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL 0x40000a1 |
1265 | #define ixD2F3_PCIE_LANE_5_EQUALIZATION_CNTL 0x40000a1 |
1266 | #define ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL 0x40000a2 |
1267 | #define ixD2F3_PCIE_LANE_7_EQUALIZATION_CNTL 0x40000a2 |
1268 | #define ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL 0x40000a3 |
1269 | #define ixD2F3_PCIE_LANE_9_EQUALIZATION_CNTL 0x40000a3 |
1270 | #define ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL 0x40000a4 |
1271 | #define ixD2F3_PCIE_LANE_11_EQUALIZATION_CNTL 0x40000a4 |
1272 | #define ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL 0x40000a5 |
1273 | #define ixD2F3_PCIE_LANE_13_EQUALIZATION_CNTL 0x40000a5 |
1274 | #define ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL 0x40000a6 |
1275 | #define ixD2F3_PCIE_LANE_15_EQUALIZATION_CNTL 0x40000a6 |
1276 | #define ixD2F3_PCIE_ACS_ENH_CAP_LIST 0x40000a8 |
1277 | #define ixD2F3_PCIE_ACS_CAP 0x40000a9 |
1278 | #define ixD2F3_PCIE_ACS_CNTL 0x40000a9 |
1279 | #define ixD2F3_PCIE_MC_ENH_CAP_LIST 0x40000bc |
1280 | #define ixD2F3_PCIE_MC_CAP 0x40000bd |
1281 | #define ixD2F3_PCIE_MC_CNTL 0x40000bd |
1282 | #define ixD2F3_PCIE_MC_ADDR0 0x40000be |
1283 | #define ixD2F3_PCIE_MC_ADDR1 0x40000bf |
1284 | #define ixD2F3_PCIE_MC_RCV0 0x40000c0 |
1285 | #define ixD2F3_PCIE_MC_RCV1 0x40000c1 |
1286 | #define ixD2F3_PCIE_MC_BLOCK_ALL0 0x40000c2 |
1287 | #define ixD2F3_PCIE_MC_BLOCK_ALL1 0x40000c3 |
1288 | #define ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0 0x40000c4 |
1289 | #define ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1 0x40000c5 |
1290 | #define ixD2F3_PCIE_MC_OVERLAY_BAR0 0x40000c6 |
1291 | #define ixD2F3_PCIE_MC_OVERLAY_BAR1 0x40000c7 |
1292 | #define ixD2F4_PCIE_PORT_INDEX 0x5000038 |
1293 | #define ixD2F4_PCIE_PORT_DATA 0x5000039 |
1294 | #define ixD2F4_PCIEP_RESERVED 0x0 |
1295 | #define ixD2F4_PCIEP_SCRATCH 0x1 |
1296 | #define ixD2F4_PCIEP_HW_DEBUG 0x2 |
1297 | #define ixD2F4_PCIEP_PORT_CNTL 0x10 |
1298 | #define ixD2F4_PCIE_TX_CNTL 0x20 |
1299 | #define ixD2F4_PCIE_TX_REQUESTER_ID 0x21 |
1300 | #define ixD2F4_PCIE_TX_VENDOR_SPECIFIC 0x22 |
1301 | #define ixD2F4_PCIE_TX_REQUEST_NUM_CNTL 0x23 |
1302 | #define ixD2F4_PCIE_TX_SEQ 0x24 |
1303 | #define ixD2F4_PCIE_TX_REPLAY 0x25 |
1304 | #define ixD2F4_PCIE_TX_ACK_LATENCY_LIMIT 0x26 |
1305 | #define ixD2F4_PCIE_TX_CREDITS_ADVT_P 0x30 |
1306 | #define ixD2F4_PCIE_TX_CREDITS_ADVT_NP 0x31 |
1307 | #define ixD2F4_PCIE_TX_CREDITS_ADVT_CPL 0x32 |
1308 | #define ixD2F4_PCIE_TX_CREDITS_INIT_P 0x33 |
1309 | #define ixD2F4_PCIE_TX_CREDITS_INIT_NP 0x34 |
1310 | #define ixD2F4_PCIE_TX_CREDITS_INIT_CPL 0x35 |
1311 | #define ixD2F4_PCIE_TX_CREDITS_STATUS 0x36 |
1312 | #define ixD2F4_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 |
1313 | #define ixD2F4_PCIE_P_PORT_LANE_STATUS 0x50 |
1314 | #define ixD2F4_PCIE_FC_P 0x60 |
1315 | #define ixD2F4_PCIE_FC_NP 0x61 |
1316 | #define ixD2F4_PCIE_FC_CPL 0x62 |
1317 | #define ixD2F4_PCIE_ERR_CNTL 0x6a |
1318 | #define ixD2F4_PCIE_RX_CNTL 0x70 |
1319 | #define ixD2F4_PCIE_RX_EXPECTED_SEQNUM 0x71 |
1320 | #define ixD2F4_PCIE_RX_VENDOR_SPECIFIC 0x72 |
1321 | #define ixD2F4_PCIE_RX_CNTL3 0x74 |
1322 | #define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_P 0x80 |
1323 | #define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 |
1324 | #define ixD2F4_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 |
1325 | #define ixD2F4_PCIEP_ERROR_INJECT_PHYSICAL 0x83 |
1326 | #define ixD2F4_PCIEP_ERROR_INJECT_TRANSACTION 0x84 |
1327 | #define ixD2F4_PCIE_LC_CNTL 0xa0 |
1328 | #define ixD2F4_PCIE_LC_CNTL2 0xb1 |
1329 | #define ixD2F4_PCIE_LC_CNTL3 0xb5 |
1330 | #define ixD2F4_PCIE_LC_CNTL4 0xb6 |
1331 | #define ixD2F4_PCIE_LC_CNTL5 0xb7 |
1332 | #define ixD2F4_PCIE_LC_CNTL6 0xbb |
1333 | #define ixD2F4_PCIE_LC_BW_CHANGE_CNTL 0xb2 |
1334 | #define ixD2F4_PCIE_LC_TRAINING_CNTL 0xa1 |
1335 | #define ixD2F4_PCIE_LC_LINK_WIDTH_CNTL 0xa2 |
1336 | #define ixD2F4_PCIE_LC_N_FTS_CNTL 0xa3 |
1337 | #define ixD2F4_PCIE_LC_SPEED_CNTL 0xa4 |
1338 | #define ixD2F4_PCIE_LC_CDR_CNTL 0xb3 |
1339 | #define ixD2F4_PCIE_LC_LANE_CNTL 0xb4 |
1340 | #define ixD2F4_PCIE_LC_FORCE_COEFF 0xb8 |
1341 | #define ixD2F4_PCIE_LC_BEST_EQ_SETTINGS 0xb9 |
1342 | #define ixD2F4_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba |
1343 | #define ixD2F4_PCIE_LC_STATE0 0xa5 |
1344 | #define ixD2F4_PCIE_LC_STATE1 0xa6 |
1345 | #define ixD2F4_PCIE_LC_STATE2 0xa7 |
1346 | #define ixD2F4_PCIE_LC_STATE3 0xa8 |
1347 | #define ixD2F4_PCIE_LC_STATE4 0xa9 |
1348 | #define ixD2F4_PCIE_LC_STATE5 0xaa |
1349 | #define ixD2F4_PCIEP_STRAP_LC 0xc0 |
1350 | #define ixD2F4_PCIEP_STRAP_MISC 0xc1 |
1351 | #define ixD2F4_PCIEP_BCH_ECC_CNTL 0xd0 |
1352 | #define ixD2F4_PCIEP_HPGI_PRIVATE 0xd2 |
1353 | #define ixD2F4_PCIEP_HPGI 0xda |
1354 | #define ixD2F4_VENDOR_ID 0x5000000 |
1355 | #define ixD2F4_DEVICE_ID 0x5000000 |
1356 | #define ixD2F4_COMMAND 0x5000001 |
1357 | #define ixD2F4_STATUS 0x5000001 |
1358 | #define ixD2F4_REVISION_ID 0x5000002 |
1359 | #define ixD2F4_PROG_INTERFACE 0x5000002 |
1360 | #define ixD2F4_SUB_CLASS 0x5000002 |
1361 | #define ixD2F4_BASE_CLASS 0x5000002 |
1362 | #define ixD2F4_CACHE_LINE 0x5000003 |
1363 | #define ixD2F4_LATENCY 0x5000003 |
1364 | #define 0x5000003 |
1365 | #define ixD2F4_BIST 0x5000003 |
1366 | #define ixD2F4_SUB_BUS_NUMBER_LATENCY 0x5000006 |
1367 | #define ixD2F4_IO_BASE_LIMIT 0x5000007 |
1368 | #define ixD2F4_SECONDARY_STATUS 0x5000007 |
1369 | #define ixD2F4_MEM_BASE_LIMIT 0x5000008 |
1370 | #define ixD2F4_PREF_BASE_LIMIT 0x5000009 |
1371 | #define ixD2F4_PREF_BASE_UPPER 0x500000a |
1372 | #define ixD2F4_PREF_LIMIT_UPPER 0x500000b |
1373 | #define ixD2F4_IO_BASE_LIMIT_HI 0x500000c |
1374 | #define ixD2F4_IRQ_BRIDGE_CNTL 0x500000f |
1375 | #define ixD2F4_CAP_PTR 0x500000d |
1376 | #define ixD2F4_INTERRUPT_LINE 0x500000f |
1377 | #define ixD2F4_INTERRUPT_PIN 0x500000f |
1378 | #define ixD2F4_EXT_BRIDGE_CNTL 0x5000010 |
1379 | #define ixD2F4_PMI_CAP_LIST 0x5000014 |
1380 | #define ixD2F4_PMI_CAP 0x5000014 |
1381 | #define ixD2F4_PMI_STATUS_CNTL 0x5000015 |
1382 | #define ixD2F4_PCIE_CAP_LIST 0x5000016 |
1383 | #define ixD2F4_PCIE_CAP 0x5000016 |
1384 | #define ixD2F4_DEVICE_CAP 0x5000017 |
1385 | #define ixD2F4_DEVICE_CNTL 0x5000018 |
1386 | #define ixD2F4_DEVICE_STATUS 0x5000018 |
1387 | #define ixD2F4_LINK_CAP 0x5000019 |
1388 | #define ixD2F4_LINK_CNTL 0x500001a |
1389 | #define ixD2F4_LINK_STATUS 0x500001a |
1390 | #define ixD2F4_SLOT_CAP 0x500001b |
1391 | #define ixD2F4_SLOT_CNTL 0x500001c |
1392 | #define ixD2F4_SLOT_STATUS 0x500001c |
1393 | #define ixD2F4_ROOT_CNTL 0x500001d |
1394 | #define ixD2F4_ROOT_CAP 0x500001d |
1395 | #define ixD2F4_ROOT_STATUS 0x500001e |
1396 | #define ixD2F4_DEVICE_CAP2 0x500001f |
1397 | #define ixD2F4_DEVICE_CNTL2 0x5000020 |
1398 | #define ixD2F4_DEVICE_STATUS2 0x5000020 |
1399 | #define ixD2F4_LINK_CAP2 0x5000021 |
1400 | #define ixD2F4_LINK_CNTL2 0x5000022 |
1401 | #define ixD2F4_LINK_STATUS2 0x5000022 |
1402 | #define ixD2F4_SLOT_CAP2 0x5000023 |
1403 | #define ixD2F4_SLOT_CNTL2 0x5000024 |
1404 | #define ixD2F4_SLOT_STATUS2 0x5000024 |
1405 | #define ixD2F4_MSI_CAP_LIST 0x5000028 |
1406 | #define ixD2F4_MSI_MSG_CNTL 0x5000028 |
1407 | #define ixD2F4_MSI_MSG_ADDR_LO 0x5000029 |
1408 | #define ixD2F4_MSI_MSG_ADDR_HI 0x500002a |
1409 | #define ixD2F4_MSI_MSG_DATA_64 0x500002b |
1410 | #define ixD2F4_MSI_MSG_DATA 0x500002a |
1411 | #define ixD2F4_SSID_CAP_LIST 0x5000030 |
1412 | #define ixD2F4_SSID_CAP 0x5000031 |
1413 | #define ixD2F4_MSI_MAP_CAP_LIST 0x5000032 |
1414 | #define ixD2F4_MSI_MAP_CAP 0x5000032 |
1415 | #define ixD2F4_MSI_MAP_ADDR_LO 0x5000033 |
1416 | #define ixD2F4_MSI_MAP_ADDR_HI 0x5000034 |
1417 | #define ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x5000040 |
1418 | #define ixD2F4_PCIE_VENDOR_SPECIFIC_HDR 0x5000041 |
1419 | #define ixD2F4_PCIE_VENDOR_SPECIFIC1 0x5000042 |
1420 | #define ixD2F4_PCIE_VENDOR_SPECIFIC2 0x5000043 |
1421 | #define ixD2F4_PCIE_VC_ENH_CAP_LIST 0x5000044 |
1422 | #define ixD2F4_PCIE_PORT_VC_CAP_REG1 0x5000045 |
1423 | #define ixD2F4_PCIE_PORT_VC_CAP_REG2 0x5000046 |
1424 | #define ixD2F4_PCIE_PORT_VC_CNTL 0x5000047 |
1425 | #define ixD2F4_PCIE_PORT_VC_STATUS 0x5000047 |
1426 | #define ixD2F4_PCIE_VC0_RESOURCE_CAP 0x5000048 |
1427 | #define ixD2F4_PCIE_VC0_RESOURCE_CNTL 0x5000049 |
1428 | #define ixD2F4_PCIE_VC0_RESOURCE_STATUS 0x500004a |
1429 | #define ixD2F4_PCIE_VC1_RESOURCE_CAP 0x500004b |
1430 | #define ixD2F4_PCIE_VC1_RESOURCE_CNTL 0x500004c |
1431 | #define ixD2F4_PCIE_VC1_RESOURCE_STATUS 0x500004d |
1432 | #define ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x5000050 |
1433 | #define ixD2F4_PCIE_DEV_SERIAL_NUM_DW1 0x5000051 |
1434 | #define ixD2F4_PCIE_DEV_SERIAL_NUM_DW2 0x5000052 |
1435 | #define ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x5000054 |
1436 | #define ixD2F4_PCIE_UNCORR_ERR_STATUS 0x5000055 |
1437 | #define ixD2F4_PCIE_UNCORR_ERR_MASK 0x5000056 |
1438 | #define ixD2F4_PCIE_UNCORR_ERR_SEVERITY 0x5000057 |
1439 | #define ixD2F4_PCIE_CORR_ERR_STATUS 0x5000058 |
1440 | #define ixD2F4_PCIE_CORR_ERR_MASK 0x5000059 |
1441 | #define ixD2F4_PCIE_ADV_ERR_CAP_CNTL 0x500005a |
1442 | #define ixD2F4_PCIE_HDR_LOG0 0x500005b |
1443 | #define ixD2F4_PCIE_HDR_LOG1 0x500005c |
1444 | #define ixD2F4_PCIE_HDR_LOG2 0x500005d |
1445 | #define ixD2F4_PCIE_HDR_LOG3 0x500005e |
1446 | #define ixD2F4_PCIE_ROOT_ERR_CMD 0x500005f |
1447 | #define ixD2F4_PCIE_ROOT_ERR_STATUS 0x5000060 |
1448 | #define ixD2F4_PCIE_ERR_SRC_ID 0x5000061 |
1449 | #define ixD2F4_PCIE_TLP_PREFIX_LOG0 0x5000062 |
1450 | #define ixD2F4_PCIE_TLP_PREFIX_LOG1 0x5000063 |
1451 | #define ixD2F4_PCIE_TLP_PREFIX_LOG2 0x5000064 |
1452 | #define ixD2F4_PCIE_TLP_PREFIX_LOG3 0x5000065 |
1453 | #define ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST 0x500009c |
1454 | #define ixD2F4_PCIE_LINK_CNTL3 0x500009d |
1455 | #define ixD2F4_PCIE_LANE_ERROR_STATUS 0x500009e |
1456 | #define ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL 0x500009f |
1457 | #define ixD2F4_PCIE_LANE_1_EQUALIZATION_CNTL 0x500009f |
1458 | #define ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL 0x50000a0 |
1459 | #define ixD2F4_PCIE_LANE_3_EQUALIZATION_CNTL 0x50000a0 |
1460 | #define ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL 0x50000a1 |
1461 | #define ixD2F4_PCIE_LANE_5_EQUALIZATION_CNTL 0x50000a1 |
1462 | #define ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL 0x50000a2 |
1463 | #define ixD2F4_PCIE_LANE_7_EQUALIZATION_CNTL 0x50000a2 |
1464 | #define ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL 0x50000a3 |
1465 | #define ixD2F4_PCIE_LANE_9_EQUALIZATION_CNTL 0x50000a3 |
1466 | #define ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL 0x50000a4 |
1467 | #define ixD2F4_PCIE_LANE_11_EQUALIZATION_CNTL 0x50000a4 |
1468 | #define ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL 0x50000a5 |
1469 | #define ixD2F4_PCIE_LANE_13_EQUALIZATION_CNTL 0x50000a5 |
1470 | #define ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL 0x50000a6 |
1471 | #define ixD2F4_PCIE_LANE_15_EQUALIZATION_CNTL 0x50000a6 |
1472 | #define ixD2F4_PCIE_ACS_ENH_CAP_LIST 0x50000a8 |
1473 | #define ixD2F4_PCIE_ACS_CAP 0x50000a9 |
1474 | #define ixD2F4_PCIE_ACS_CNTL 0x50000a9 |
1475 | #define ixD2F4_PCIE_MC_ENH_CAP_LIST 0x50000bc |
1476 | #define ixD2F4_PCIE_MC_CAP 0x50000bd |
1477 | #define ixD2F4_PCIE_MC_CNTL 0x50000bd |
1478 | #define ixD2F4_PCIE_MC_ADDR0 0x50000be |
1479 | #define ixD2F4_PCIE_MC_ADDR1 0x50000bf |
1480 | #define ixD2F4_PCIE_MC_RCV0 0x50000c0 |
1481 | #define ixD2F4_PCIE_MC_RCV1 0x50000c1 |
1482 | #define ixD2F4_PCIE_MC_BLOCK_ALL0 0x50000c2 |
1483 | #define ixD2F4_PCIE_MC_BLOCK_ALL1 0x50000c3 |
1484 | #define ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0 0x50000c4 |
1485 | #define ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1 0x50000c5 |
1486 | #define ixD2F4_PCIE_MC_OVERLAY_BAR0 0x50000c6 |
1487 | #define ixD2F4_PCIE_MC_OVERLAY_BAR1 0x50000c7 |
1488 | #define ixD2F5_PCIE_PORT_INDEX 0x6000038 |
1489 | #define ixD2F5_PCIE_PORT_DATA 0x6000039 |
1490 | #define ixD2F5_PCIEP_RESERVED 0x0 |
1491 | #define ixD2F5_PCIEP_SCRATCH 0x1 |
1492 | #define ixD2F5_PCIEP_HW_DEBUG 0x2 |
1493 | #define ixD2F5_PCIEP_PORT_CNTL 0x10 |
1494 | #define ixD2F5_PCIE_TX_CNTL 0x20 |
1495 | #define ixD2F5_PCIE_TX_REQUESTER_ID 0x21 |
1496 | #define ixD2F5_PCIE_TX_VENDOR_SPECIFIC 0x22 |
1497 | #define ixD2F5_PCIE_TX_REQUEST_NUM_CNTL 0x23 |
1498 | #define ixD2F5_PCIE_TX_SEQ 0x24 |
1499 | #define ixD2F5_PCIE_TX_REPLAY 0x25 |
1500 | #define ixD2F5_PCIE_TX_ACK_LATENCY_LIMIT 0x26 |
1501 | #define ixD2F5_PCIE_TX_CREDITS_ADVT_P 0x30 |
1502 | #define ixD2F5_PCIE_TX_CREDITS_ADVT_NP 0x31 |
1503 | #define ixD2F5_PCIE_TX_CREDITS_ADVT_CPL 0x32 |
1504 | #define ixD2F5_PCIE_TX_CREDITS_INIT_P 0x33 |
1505 | #define ixD2F5_PCIE_TX_CREDITS_INIT_NP 0x34 |
1506 | #define ixD2F5_PCIE_TX_CREDITS_INIT_CPL 0x35 |
1507 | #define ixD2F5_PCIE_TX_CREDITS_STATUS 0x36 |
1508 | #define ixD2F5_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 |
1509 | #define ixD2F5_PCIE_P_PORT_LANE_STATUS 0x50 |
1510 | #define ixD2F5_PCIE_FC_P 0x60 |
1511 | #define ixD2F5_PCIE_FC_NP 0x61 |
1512 | #define ixD2F5_PCIE_FC_CPL 0x62 |
1513 | #define ixD2F5_PCIE_ERR_CNTL 0x6a |
1514 | #define ixD2F5_PCIE_RX_CNTL 0x70 |
1515 | #define ixD2F5_PCIE_RX_EXPECTED_SEQNUM 0x71 |
1516 | #define ixD2F5_PCIE_RX_VENDOR_SPECIFIC 0x72 |
1517 | #define ixD2F5_PCIE_RX_CNTL3 0x74 |
1518 | #define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_P 0x80 |
1519 | #define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 |
1520 | #define ixD2F5_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 |
1521 | #define ixD2F5_PCIEP_ERROR_INJECT_PHYSICAL 0x83 |
1522 | #define ixD2F5_PCIEP_ERROR_INJECT_TRANSACTION 0x84 |
1523 | #define ixD2F5_PCIE_LC_CNTL 0xa0 |
1524 | #define ixD2F5_PCIE_LC_CNTL2 0xb1 |
1525 | #define ixD2F5_PCIE_LC_CNTL3 0xb5 |
1526 | #define ixD2F5_PCIE_LC_CNTL4 0xb6 |
1527 | #define ixD2F5_PCIE_LC_CNTL5 0xb7 |
1528 | #define ixD2F5_PCIE_LC_CNTL6 0xbb |
1529 | #define ixD2F5_PCIE_LC_BW_CHANGE_CNTL 0xb2 |
1530 | #define ixD2F5_PCIE_LC_TRAINING_CNTL 0xa1 |
1531 | #define ixD2F5_PCIE_LC_LINK_WIDTH_CNTL 0xa2 |
1532 | #define ixD2F5_PCIE_LC_N_FTS_CNTL 0xa3 |
1533 | #define ixD2F5_PCIE_LC_SPEED_CNTL 0xa4 |
1534 | #define ixD2F5_PCIE_LC_CDR_CNTL 0xb3 |
1535 | #define ixD2F5_PCIE_LC_LANE_CNTL 0xb4 |
1536 | #define ixD2F5_PCIE_LC_FORCE_COEFF 0xb8 |
1537 | #define ixD2F5_PCIE_LC_BEST_EQ_SETTINGS 0xb9 |
1538 | #define ixD2F5_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba |
1539 | #define ixD2F5_PCIE_LC_STATE0 0xa5 |
1540 | #define ixD2F5_PCIE_LC_STATE1 0xa6 |
1541 | #define ixD2F5_PCIE_LC_STATE2 0xa7 |
1542 | #define ixD2F5_PCIE_LC_STATE3 0xa8 |
1543 | #define ixD2F5_PCIE_LC_STATE4 0xa9 |
1544 | #define ixD2F5_PCIE_LC_STATE5 0xaa |
1545 | #define ixD2F5_PCIEP_STRAP_LC 0xc0 |
1546 | #define ixD2F5_PCIEP_STRAP_MISC 0xc1 |
1547 | #define ixD2F5_PCIEP_BCH_ECC_CNTL 0xd0 |
1548 | #define ixD2F5_PCIEP_HPGI_PRIVATE 0xd2 |
1549 | #define ixD2F5_PCIEP_HPGI 0xda |
1550 | #define ixD2F5_VENDOR_ID 0x6000000 |
1551 | #define ixD2F5_DEVICE_ID 0x6000000 |
1552 | #define ixD2F5_COMMAND 0x6000001 |
1553 | #define ixD2F5_STATUS 0x6000001 |
1554 | #define ixD2F5_REVISION_ID 0x6000002 |
1555 | #define ixD2F5_PROG_INTERFACE 0x6000002 |
1556 | #define ixD2F5_SUB_CLASS 0x6000002 |
1557 | #define ixD2F5_BASE_CLASS 0x6000002 |
1558 | #define ixD2F5_CACHE_LINE 0x6000003 |
1559 | #define ixD2F5_LATENCY 0x6000003 |
1560 | #define 0x6000003 |
1561 | #define ixD2F5_BIST 0x6000003 |
1562 | #define ixD2F5_SUB_BUS_NUMBER_LATENCY 0x6000006 |
1563 | #define ixD2F5_IO_BASE_LIMIT 0x6000007 |
1564 | #define ixD2F5_SECONDARY_STATUS 0x6000007 |
1565 | #define ixD2F5_MEM_BASE_LIMIT 0x6000008 |
1566 | #define ixD2F5_PREF_BASE_LIMIT 0x6000009 |
1567 | #define ixD2F5_PREF_BASE_UPPER 0x600000a |
1568 | #define ixD2F5_PREF_LIMIT_UPPER 0x600000b |
1569 | #define ixD2F5_IO_BASE_LIMIT_HI 0x600000c |
1570 | #define ixD2F5_IRQ_BRIDGE_CNTL 0x600000f |
1571 | #define ixD2F5_CAP_PTR 0x600000d |
1572 | #define ixD2F5_INTERRUPT_LINE 0x600000f |
1573 | #define ixD2F5_INTERRUPT_PIN 0x600000f |
1574 | #define ixD2F5_EXT_BRIDGE_CNTL 0x6000010 |
1575 | #define ixD2F5_PMI_CAP_LIST 0x6000014 |
1576 | #define ixD2F5_PMI_CAP 0x6000014 |
1577 | #define ixD2F5_PMI_STATUS_CNTL 0x6000015 |
1578 | #define ixD2F5_PCIE_CAP_LIST 0x6000016 |
1579 | #define ixD2F5_PCIE_CAP 0x6000016 |
1580 | #define ixD2F5_DEVICE_CAP 0x6000017 |
1581 | #define ixD2F5_DEVICE_CNTL 0x6000018 |
1582 | #define ixD2F5_DEVICE_STATUS 0x6000018 |
1583 | #define ixD2F5_LINK_CAP 0x6000019 |
1584 | #define ixD2F5_LINK_CNTL 0x600001a |
1585 | #define ixD2F5_LINK_STATUS 0x600001a |
1586 | #define ixD2F5_SLOT_CAP 0x600001b |
1587 | #define ixD2F5_SLOT_CNTL 0x600001c |
1588 | #define ixD2F5_SLOT_STATUS 0x600001c |
1589 | #define ixD2F5_ROOT_CNTL 0x600001d |
1590 | #define ixD2F5_ROOT_CAP 0x600001d |
1591 | #define ixD2F5_ROOT_STATUS 0x600001e |
1592 | #define ixD2F5_DEVICE_CAP2 0x600001f |
1593 | #define ixD2F5_DEVICE_CNTL2 0x6000020 |
1594 | #define ixD2F5_DEVICE_STATUS2 0x6000020 |
1595 | #define ixD2F5_LINK_CAP2 0x6000021 |
1596 | #define ixD2F5_LINK_CNTL2 0x6000022 |
1597 | #define ixD2F5_LINK_STATUS2 0x6000022 |
1598 | #define ixD2F5_SLOT_CAP2 0x6000023 |
1599 | #define ixD2F5_SLOT_CNTL2 0x6000024 |
1600 | #define ixD2F5_SLOT_STATUS2 0x6000024 |
1601 | #define ixD2F5_MSI_CAP_LIST 0x6000028 |
1602 | #define ixD2F5_MSI_MSG_CNTL 0x6000028 |
1603 | #define ixD2F5_MSI_MSG_ADDR_LO 0x6000029 |
1604 | #define ixD2F5_MSI_MSG_ADDR_HI 0x600002a |
1605 | #define ixD2F5_MSI_MSG_DATA_64 0x600002b |
1606 | #define ixD2F5_MSI_MSG_DATA 0x600002a |
1607 | #define ixD2F5_SSID_CAP_LIST 0x6000030 |
1608 | #define ixD2F5_SSID_CAP 0x6000031 |
1609 | #define ixD2F5_MSI_MAP_CAP_LIST 0x6000032 |
1610 | #define ixD2F5_MSI_MAP_CAP 0x6000032 |
1611 | #define ixD2F5_MSI_MAP_ADDR_LO 0x6000033 |
1612 | #define ixD2F5_MSI_MAP_ADDR_HI 0x6000034 |
1613 | #define ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x6000040 |
1614 | #define ixD2F5_PCIE_VENDOR_SPECIFIC_HDR 0x6000041 |
1615 | #define ixD2F5_PCIE_VENDOR_SPECIFIC1 0x6000042 |
1616 | #define ixD2F5_PCIE_VENDOR_SPECIFIC2 0x6000043 |
1617 | #define ixD2F5_PCIE_VC_ENH_CAP_LIST 0x6000044 |
1618 | #define ixD2F5_PCIE_PORT_VC_CAP_REG1 0x6000045 |
1619 | #define ixD2F5_PCIE_PORT_VC_CAP_REG2 0x6000046 |
1620 | #define ixD2F5_PCIE_PORT_VC_CNTL 0x6000047 |
1621 | #define ixD2F5_PCIE_PORT_VC_STATUS 0x6000047 |
1622 | #define ixD2F5_PCIE_VC0_RESOURCE_CAP 0x6000048 |
1623 | #define ixD2F5_PCIE_VC0_RESOURCE_CNTL 0x6000049 |
1624 | #define ixD2F5_PCIE_VC0_RESOURCE_STATUS 0x600004a |
1625 | #define ixD2F5_PCIE_VC1_RESOURCE_CAP 0x600004b |
1626 | #define ixD2F5_PCIE_VC1_RESOURCE_CNTL 0x600004c |
1627 | #define ixD2F5_PCIE_VC1_RESOURCE_STATUS 0x600004d |
1628 | #define ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x6000050 |
1629 | #define ixD2F5_PCIE_DEV_SERIAL_NUM_DW1 0x6000051 |
1630 | #define ixD2F5_PCIE_DEV_SERIAL_NUM_DW2 0x6000052 |
1631 | #define ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x6000054 |
1632 | #define ixD2F5_PCIE_UNCORR_ERR_STATUS 0x6000055 |
1633 | #define ixD2F5_PCIE_UNCORR_ERR_MASK 0x6000056 |
1634 | #define ixD2F5_PCIE_UNCORR_ERR_SEVERITY 0x6000057 |
1635 | #define ixD2F5_PCIE_CORR_ERR_STATUS 0x6000058 |
1636 | #define ixD2F5_PCIE_CORR_ERR_MASK 0x6000059 |
1637 | #define ixD2F5_PCIE_ADV_ERR_CAP_CNTL 0x600005a |
1638 | #define ixD2F5_PCIE_HDR_LOG0 0x600005b |
1639 | #define ixD2F5_PCIE_HDR_LOG1 0x600005c |
1640 | #define ixD2F5_PCIE_HDR_LOG2 0x600005d |
1641 | #define ixD2F5_PCIE_HDR_LOG3 0x600005e |
1642 | #define ixD2F5_PCIE_ROOT_ERR_CMD 0x600005f |
1643 | #define ixD2F5_PCIE_ROOT_ERR_STATUS 0x6000060 |
1644 | #define ixD2F5_PCIE_ERR_SRC_ID 0x6000061 |
1645 | #define ixD2F5_PCIE_TLP_PREFIX_LOG0 0x6000062 |
1646 | #define ixD2F5_PCIE_TLP_PREFIX_LOG1 0x6000063 |
1647 | #define ixD2F5_PCIE_TLP_PREFIX_LOG2 0x6000064 |
1648 | #define ixD2F5_PCIE_TLP_PREFIX_LOG3 0x6000065 |
1649 | #define ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST 0x600009c |
1650 | #define ixD2F5_PCIE_LINK_CNTL3 0x600009d |
1651 | #define ixD2F5_PCIE_LANE_ERROR_STATUS 0x600009e |
1652 | #define ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL 0x600009f |
1653 | #define ixD2F5_PCIE_LANE_1_EQUALIZATION_CNTL 0x600009f |
1654 | #define ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL 0x60000a0 |
1655 | #define ixD2F5_PCIE_LANE_3_EQUALIZATION_CNTL 0x60000a0 |
1656 | #define ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL 0x60000a1 |
1657 | #define ixD2F5_PCIE_LANE_5_EQUALIZATION_CNTL 0x60000a1 |
1658 | #define ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL 0x60000a2 |
1659 | #define ixD2F5_PCIE_LANE_7_EQUALIZATION_CNTL 0x60000a2 |
1660 | #define ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL 0x60000a3 |
1661 | #define ixD2F5_PCIE_LANE_9_EQUALIZATION_CNTL 0x60000a3 |
1662 | #define ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL 0x60000a4 |
1663 | #define ixD2F5_PCIE_LANE_11_EQUALIZATION_CNTL 0x60000a4 |
1664 | #define ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL 0x60000a5 |
1665 | #define ixD2F5_PCIE_LANE_13_EQUALIZATION_CNTL 0x60000a5 |
1666 | #define ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL 0x60000a6 |
1667 | #define ixD2F5_PCIE_LANE_15_EQUALIZATION_CNTL 0x60000a6 |
1668 | #define ixD2F5_PCIE_ACS_ENH_CAP_LIST 0x60000a8 |
1669 | #define ixD2F5_PCIE_ACS_CAP 0x60000a9 |
1670 | #define ixD2F5_PCIE_ACS_CNTL 0x60000a9 |
1671 | #define ixD2F5_PCIE_MC_ENH_CAP_LIST 0x60000bc |
1672 | #define ixD2F5_PCIE_MC_CAP 0x60000bd |
1673 | #define ixD2F5_PCIE_MC_CNTL 0x60000bd |
1674 | #define ixD2F5_PCIE_MC_ADDR0 0x60000be |
1675 | #define ixD2F5_PCIE_MC_ADDR1 0x60000bf |
1676 | #define ixD2F5_PCIE_MC_RCV0 0x60000c0 |
1677 | #define ixD2F5_PCIE_MC_RCV1 0x60000c1 |
1678 | #define ixD2F5_PCIE_MC_BLOCK_ALL0 0x60000c2 |
1679 | #define ixD2F5_PCIE_MC_BLOCK_ALL1 0x60000c3 |
1680 | #define ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0 0x60000c4 |
1681 | #define ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1 0x60000c5 |
1682 | #define ixD2F5_PCIE_MC_OVERLAY_BAR0 0x60000c6 |
1683 | #define ixD2F5_PCIE_MC_OVERLAY_BAR1 0x60000c7 |
1684 | #define ixD3F1_PCIE_PORT_INDEX 0x7000038 |
1685 | #define ixD3F1_PCIE_PORT_DATA 0x7000039 |
1686 | #define ixD3F1_PCIEP_RESERVED 0x0 |
1687 | #define ixD3F1_PCIEP_SCRATCH 0x1 |
1688 | #define ixD3F1_PCIEP_HW_DEBUG 0x2 |
1689 | #define ixD3F1_PCIEP_PORT_CNTL 0x10 |
1690 | #define ixD3F1_PCIE_TX_CNTL 0x20 |
1691 | #define ixD3F1_PCIE_TX_REQUESTER_ID 0x21 |
1692 | #define ixD3F1_PCIE_TX_VENDOR_SPECIFIC 0x22 |
1693 | #define ixD3F1_PCIE_TX_REQUEST_NUM_CNTL 0x23 |
1694 | #define ixD3F1_PCIE_TX_SEQ 0x24 |
1695 | #define ixD3F1_PCIE_TX_REPLAY 0x25 |
1696 | #define ixD3F1_PCIE_TX_ACK_LATENCY_LIMIT 0x26 |
1697 | #define ixD3F1_PCIE_TX_CREDITS_ADVT_P 0x30 |
1698 | #define ixD3F1_PCIE_TX_CREDITS_ADVT_NP 0x31 |
1699 | #define ixD3F1_PCIE_TX_CREDITS_ADVT_CPL 0x32 |
1700 | #define ixD3F1_PCIE_TX_CREDITS_INIT_P 0x33 |
1701 | #define ixD3F1_PCIE_TX_CREDITS_INIT_NP 0x34 |
1702 | #define ixD3F1_PCIE_TX_CREDITS_INIT_CPL 0x35 |
1703 | #define ixD3F1_PCIE_TX_CREDITS_STATUS 0x36 |
1704 | #define ixD3F1_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 |
1705 | #define ixD3F1_PCIE_P_PORT_LANE_STATUS 0x50 |
1706 | #define ixD3F1_PCIE_FC_P 0x60 |
1707 | #define ixD3F1_PCIE_FC_NP 0x61 |
1708 | #define ixD3F1_PCIE_FC_CPL 0x62 |
1709 | #define ixD3F1_PCIE_ERR_CNTL 0x6a |
1710 | #define ixD3F1_PCIE_RX_CNTL 0x70 |
1711 | #define ixD3F1_PCIE_RX_EXPECTED_SEQNUM 0x71 |
1712 | #define ixD3F1_PCIE_RX_VENDOR_SPECIFIC 0x72 |
1713 | #define ixD3F1_PCIE_RX_CNTL3 0x74 |
1714 | #define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_P 0x80 |
1715 | #define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 |
1716 | #define ixD3F1_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 |
1717 | #define ixD3F1_PCIEP_ERROR_INJECT_PHYSICAL 0x83 |
1718 | #define ixD3F1_PCIEP_ERROR_INJECT_TRANSACTION 0x84 |
1719 | #define ixD3F1_PCIE_LC_CNTL 0xa0 |
1720 | #define ixD3F1_PCIE_LC_CNTL2 0xb1 |
1721 | #define ixD3F1_PCIE_LC_CNTL3 0xb5 |
1722 | #define ixD3F1_PCIE_LC_CNTL4 0xb6 |
1723 | #define ixD3F1_PCIE_LC_CNTL5 0xb7 |
1724 | #define ixD3F1_PCIE_LC_CNTL6 0xbb |
1725 | #define ixD3F1_PCIE_LC_BW_CHANGE_CNTL 0xb2 |
1726 | #define ixD3F1_PCIE_LC_TRAINING_CNTL 0xa1 |
1727 | #define ixD3F1_PCIE_LC_LINK_WIDTH_CNTL 0xa2 |
1728 | #define ixD3F1_PCIE_LC_N_FTS_CNTL 0xa3 |
1729 | #define ixD3F1_PCIE_LC_SPEED_CNTL 0xa4 |
1730 | #define ixD3F1_PCIE_LC_CDR_CNTL 0xb3 |
1731 | #define ixD3F1_PCIE_LC_LANE_CNTL 0xb4 |
1732 | #define ixD3F1_PCIE_LC_FORCE_COEFF 0xb8 |
1733 | #define ixD3F1_PCIE_LC_BEST_EQ_SETTINGS 0xb9 |
1734 | #define ixD3F1_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba |
1735 | #define ixD3F1_PCIE_LC_STATE0 0xa5 |
1736 | #define ixD3F1_PCIE_LC_STATE1 0xa6 |
1737 | #define ixD3F1_PCIE_LC_STATE2 0xa7 |
1738 | #define ixD3F1_PCIE_LC_STATE3 0xa8 |
1739 | #define ixD3F1_PCIE_LC_STATE4 0xa9 |
1740 | #define ixD3F1_PCIE_LC_STATE5 0xaa |
1741 | #define ixD3F1_PCIEP_STRAP_LC 0xc0 |
1742 | #define ixD3F1_PCIEP_STRAP_MISC 0xc1 |
1743 | #define ixD3F1_PCIEP_BCH_ECC_CNTL 0xd0 |
1744 | #define ixD3F1_PCIEP_HPGI_PRIVATE 0xd2 |
1745 | #define ixD3F1_PCIEP_HPGI 0xda |
1746 | #define ixD3F1_VENDOR_ID 0x7000000 |
1747 | #define ixD3F1_DEVICE_ID 0x7000000 |
1748 | #define ixD3F1_COMMAND 0x7000001 |
1749 | #define ixD3F1_STATUS 0x7000001 |
1750 | #define ixD3F1_REVISION_ID 0x7000002 |
1751 | #define ixD3F1_PROG_INTERFACE 0x7000002 |
1752 | #define ixD3F1_SUB_CLASS 0x7000002 |
1753 | #define ixD3F1_BASE_CLASS 0x7000002 |
1754 | #define ixD3F1_CACHE_LINE 0x7000003 |
1755 | #define ixD3F1_LATENCY 0x7000003 |
1756 | #define 0x7000003 |
1757 | #define ixD3F1_BIST 0x7000003 |
1758 | #define ixD3F1_SUB_BUS_NUMBER_LATENCY 0x7000006 |
1759 | #define ixD3F1_IO_BASE_LIMIT 0x7000007 |
1760 | #define ixD3F1_SECONDARY_STATUS 0x7000007 |
1761 | #define ixD3F1_MEM_BASE_LIMIT 0x7000008 |
1762 | #define ixD3F1_PREF_BASE_LIMIT 0x7000009 |
1763 | #define ixD3F1_PREF_BASE_UPPER 0x700000a |
1764 | #define ixD3F1_PREF_LIMIT_UPPER 0x700000b |
1765 | #define ixD3F1_IO_BASE_LIMIT_HI 0x700000c |
1766 | #define ixD3F1_IRQ_BRIDGE_CNTL 0x700000f |
1767 | #define ixD3F1_CAP_PTR 0x700000d |
1768 | #define ixD3F1_INTERRUPT_LINE 0x700000f |
1769 | #define ixD3F1_INTERRUPT_PIN 0x700000f |
1770 | #define ixD3F1_EXT_BRIDGE_CNTL 0x7000010 |
1771 | #define ixD3F1_PMI_CAP_LIST 0x7000014 |
1772 | #define ixD3F1_PMI_CAP 0x7000014 |
1773 | #define ixD3F1_PMI_STATUS_CNTL 0x7000015 |
1774 | #define ixD3F1_PCIE_CAP_LIST 0x7000016 |
1775 | #define ixD3F1_PCIE_CAP 0x7000016 |
1776 | #define ixD3F1_DEVICE_CAP 0x7000017 |
1777 | #define ixD3F1_DEVICE_CNTL 0x7000018 |
1778 | #define ixD3F1_DEVICE_STATUS 0x7000018 |
1779 | #define ixD3F1_LINK_CAP 0x7000019 |
1780 | #define ixD3F1_LINK_CNTL 0x700001a |
1781 | #define ixD3F1_LINK_STATUS 0x700001a |
1782 | #define ixD3F1_SLOT_CAP 0x700001b |
1783 | #define ixD3F1_SLOT_CNTL 0x700001c |
1784 | #define ixD3F1_SLOT_STATUS 0x700001c |
1785 | #define ixD3F1_ROOT_CNTL 0x700001d |
1786 | #define ixD3F1_ROOT_CAP 0x700001d |
1787 | #define ixD3F1_ROOT_STATUS 0x700001e |
1788 | #define ixD3F1_DEVICE_CAP2 0x700001f |
1789 | #define ixD3F1_DEVICE_CNTL2 0x7000020 |
1790 | #define ixD3F1_DEVICE_STATUS2 0x7000020 |
1791 | #define ixD3F1_LINK_CAP2 0x7000021 |
1792 | #define ixD3F1_LINK_CNTL2 0x7000022 |
1793 | #define ixD3F1_LINK_STATUS2 0x7000022 |
1794 | #define ixD3F1_SLOT_CAP2 0x7000023 |
1795 | #define ixD3F1_SLOT_CNTL2 0x7000024 |
1796 | #define ixD3F1_SLOT_STATUS2 0x7000024 |
1797 | #define ixD3F1_MSI_CAP_LIST 0x7000028 |
1798 | #define ixD3F1_MSI_MSG_CNTL 0x7000028 |
1799 | #define ixD3F1_MSI_MSG_ADDR_LO 0x7000029 |
1800 | #define ixD3F1_MSI_MSG_ADDR_HI 0x700002a |
1801 | #define ixD3F1_MSI_MSG_DATA_64 0x700002b |
1802 | #define ixD3F1_MSI_MSG_DATA 0x700002a |
1803 | #define ixD3F1_SSID_CAP_LIST 0x7000030 |
1804 | #define ixD3F1_SSID_CAP 0x7000031 |
1805 | #define ixD3F1_MSI_MAP_CAP_LIST 0x7000032 |
1806 | #define ixD3F1_MSI_MAP_CAP 0x7000032 |
1807 | #define ixD3F1_MSI_MAP_ADDR_LO 0x7000033 |
1808 | #define ixD3F1_MSI_MAP_ADDR_HI 0x7000034 |
1809 | #define ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x7000040 |
1810 | #define ixD3F1_PCIE_VENDOR_SPECIFIC_HDR 0x7000041 |
1811 | #define ixD3F1_PCIE_VENDOR_SPECIFIC1 0x7000042 |
1812 | #define ixD3F1_PCIE_VENDOR_SPECIFIC2 0x7000043 |
1813 | #define ixD3F1_PCIE_VC_ENH_CAP_LIST 0x7000044 |
1814 | #define ixD3F1_PCIE_PORT_VC_CAP_REG1 0x7000045 |
1815 | #define ixD3F1_PCIE_PORT_VC_CAP_REG2 0x7000046 |
1816 | #define ixD3F1_PCIE_PORT_VC_CNTL 0x7000047 |
1817 | #define ixD3F1_PCIE_PORT_VC_STATUS 0x7000047 |
1818 | #define ixD3F1_PCIE_VC0_RESOURCE_CAP 0x7000048 |
1819 | #define ixD3F1_PCIE_VC0_RESOURCE_CNTL 0x7000049 |
1820 | #define ixD3F1_PCIE_VC0_RESOURCE_STATUS 0x700004a |
1821 | #define ixD3F1_PCIE_VC1_RESOURCE_CAP 0x700004b |
1822 | #define ixD3F1_PCIE_VC1_RESOURCE_CNTL 0x700004c |
1823 | #define ixD3F1_PCIE_VC1_RESOURCE_STATUS 0x700004d |
1824 | #define ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x7000050 |
1825 | #define ixD3F1_PCIE_DEV_SERIAL_NUM_DW1 0x7000051 |
1826 | #define ixD3F1_PCIE_DEV_SERIAL_NUM_DW2 0x7000052 |
1827 | #define ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x7000054 |
1828 | #define ixD3F1_PCIE_UNCORR_ERR_STATUS 0x7000055 |
1829 | #define ixD3F1_PCIE_UNCORR_ERR_MASK 0x7000056 |
1830 | #define ixD3F1_PCIE_UNCORR_ERR_SEVERITY 0x7000057 |
1831 | #define ixD3F1_PCIE_CORR_ERR_STATUS 0x7000058 |
1832 | #define ixD3F1_PCIE_CORR_ERR_MASK 0x7000059 |
1833 | #define ixD3F1_PCIE_ADV_ERR_CAP_CNTL 0x700005a |
1834 | #define ixD3F1_PCIE_HDR_LOG0 0x700005b |
1835 | #define ixD3F1_PCIE_HDR_LOG1 0x700005c |
1836 | #define ixD3F1_PCIE_HDR_LOG2 0x700005d |
1837 | #define ixD3F1_PCIE_HDR_LOG3 0x700005e |
1838 | #define ixD3F1_PCIE_ROOT_ERR_CMD 0x700005f |
1839 | #define ixD3F1_PCIE_ROOT_ERR_STATUS 0x7000060 |
1840 | #define ixD3F1_PCIE_ERR_SRC_ID 0x7000061 |
1841 | #define ixD3F1_PCIE_TLP_PREFIX_LOG0 0x7000062 |
1842 | #define ixD3F1_PCIE_TLP_PREFIX_LOG1 0x7000063 |
1843 | #define ixD3F1_PCIE_TLP_PREFIX_LOG2 0x7000064 |
1844 | #define ixD3F1_PCIE_TLP_PREFIX_LOG3 0x7000065 |
1845 | #define ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST 0x700009c |
1846 | #define ixD3F1_PCIE_LINK_CNTL3 0x700009d |
1847 | #define ixD3F1_PCIE_LANE_ERROR_STATUS 0x700009e |
1848 | #define ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL 0x700009f |
1849 | #define ixD3F1_PCIE_LANE_1_EQUALIZATION_CNTL 0x700009f |
1850 | #define ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL 0x70000a0 |
1851 | #define ixD3F1_PCIE_LANE_3_EQUALIZATION_CNTL 0x70000a0 |
1852 | #define ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL 0x70000a1 |
1853 | #define ixD3F1_PCIE_LANE_5_EQUALIZATION_CNTL 0x70000a1 |
1854 | #define ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL 0x70000a2 |
1855 | #define ixD3F1_PCIE_LANE_7_EQUALIZATION_CNTL 0x70000a2 |
1856 | #define ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL 0x70000a3 |
1857 | #define ixD3F1_PCIE_LANE_9_EQUALIZATION_CNTL 0x70000a3 |
1858 | #define ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL 0x70000a4 |
1859 | #define ixD3F1_PCIE_LANE_11_EQUALIZATION_CNTL 0x70000a4 |
1860 | #define ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL 0x70000a5 |
1861 | #define ixD3F1_PCIE_LANE_13_EQUALIZATION_CNTL 0x70000a5 |
1862 | #define ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL 0x70000a6 |
1863 | #define ixD3F1_PCIE_LANE_15_EQUALIZATION_CNTL 0x70000a6 |
1864 | #define ixD3F1_PCIE_ACS_ENH_CAP_LIST 0x70000a8 |
1865 | #define ixD3F1_PCIE_ACS_CAP 0x70000a9 |
1866 | #define ixD3F1_PCIE_ACS_CNTL 0x70000a9 |
1867 | #define ixD3F1_PCIE_MC_ENH_CAP_LIST 0x70000bc |
1868 | #define ixD3F1_PCIE_MC_CAP 0x70000bd |
1869 | #define ixD3F1_PCIE_MC_CNTL 0x70000bd |
1870 | #define ixD3F1_PCIE_MC_ADDR0 0x70000be |
1871 | #define ixD3F1_PCIE_MC_ADDR1 0x70000bf |
1872 | #define ixD3F1_PCIE_MC_RCV0 0x70000c0 |
1873 | #define ixD3F1_PCIE_MC_RCV1 0x70000c1 |
1874 | #define ixD3F1_PCIE_MC_BLOCK_ALL0 0x70000c2 |
1875 | #define ixD3F1_PCIE_MC_BLOCK_ALL1 0x70000c3 |
1876 | #define ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0 0x70000c4 |
1877 | #define ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1 0x70000c5 |
1878 | #define ixD3F1_PCIE_MC_OVERLAY_BAR0 0x70000c6 |
1879 | #define ixD3F1_PCIE_MC_OVERLAY_BAR1 0x70000c7 |
1880 | #define ixD3F2_PCIE_PORT_INDEX 0x8000038 |
1881 | #define ixD3F2_PCIE_PORT_DATA 0x8000039 |
1882 | #define ixD3F2_PCIEP_RESERVED 0x0 |
1883 | #define ixD3F2_PCIEP_SCRATCH 0x1 |
1884 | #define ixD3F2_PCIEP_HW_DEBUG 0x2 |
1885 | #define ixD3F2_PCIEP_PORT_CNTL 0x10 |
1886 | #define ixD3F2_PCIE_TX_CNTL 0x20 |
1887 | #define ixD3F2_PCIE_TX_REQUESTER_ID 0x21 |
1888 | #define ixD3F2_PCIE_TX_VENDOR_SPECIFIC 0x22 |
1889 | #define ixD3F2_PCIE_TX_REQUEST_NUM_CNTL 0x23 |
1890 | #define ixD3F2_PCIE_TX_SEQ 0x24 |
1891 | #define ixD3F2_PCIE_TX_REPLAY 0x25 |
1892 | #define ixD3F2_PCIE_TX_ACK_LATENCY_LIMIT 0x26 |
1893 | #define ixD3F2_PCIE_TX_CREDITS_ADVT_P 0x30 |
1894 | #define ixD3F2_PCIE_TX_CREDITS_ADVT_NP 0x31 |
1895 | #define ixD3F2_PCIE_TX_CREDITS_ADVT_CPL 0x32 |
1896 | #define ixD3F2_PCIE_TX_CREDITS_INIT_P 0x33 |
1897 | #define ixD3F2_PCIE_TX_CREDITS_INIT_NP 0x34 |
1898 | #define ixD3F2_PCIE_TX_CREDITS_INIT_CPL 0x35 |
1899 | #define ixD3F2_PCIE_TX_CREDITS_STATUS 0x36 |
1900 | #define ixD3F2_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 |
1901 | #define ixD3F2_PCIE_P_PORT_LANE_STATUS 0x50 |
1902 | #define ixD3F2_PCIE_FC_P 0x60 |
1903 | #define ixD3F2_PCIE_FC_NP 0x61 |
1904 | #define ixD3F2_PCIE_FC_CPL 0x62 |
1905 | #define ixD3F2_PCIE_ERR_CNTL 0x6a |
1906 | #define ixD3F2_PCIE_RX_CNTL 0x70 |
1907 | #define ixD3F2_PCIE_RX_EXPECTED_SEQNUM 0x71 |
1908 | #define ixD3F2_PCIE_RX_VENDOR_SPECIFIC 0x72 |
1909 | #define ixD3F2_PCIE_RX_CNTL3 0x74 |
1910 | #define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_P 0x80 |
1911 | #define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 |
1912 | #define ixD3F2_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 |
1913 | #define ixD3F2_PCIEP_ERROR_INJECT_PHYSICAL 0x83 |
1914 | #define ixD3F2_PCIEP_ERROR_INJECT_TRANSACTION 0x84 |
1915 | #define ixD3F2_PCIE_LC_CNTL 0xa0 |
1916 | #define ixD3F2_PCIE_LC_CNTL2 0xb1 |
1917 | #define ixD3F2_PCIE_LC_CNTL3 0xb5 |
1918 | #define ixD3F2_PCIE_LC_CNTL4 0xb6 |
1919 | #define ixD3F2_PCIE_LC_CNTL5 0xb7 |
1920 | #define ixD3F2_PCIE_LC_CNTL6 0xbb |
1921 | #define ixD3F2_PCIE_LC_BW_CHANGE_CNTL 0xb2 |
1922 | #define ixD3F2_PCIE_LC_TRAINING_CNTL 0xa1 |
1923 | #define ixD3F2_PCIE_LC_LINK_WIDTH_CNTL 0xa2 |
1924 | #define ixD3F2_PCIE_LC_N_FTS_CNTL 0xa3 |
1925 | #define ixD3F2_PCIE_LC_SPEED_CNTL 0xa4 |
1926 | #define ixD3F2_PCIE_LC_CDR_CNTL 0xb3 |
1927 | #define ixD3F2_PCIE_LC_LANE_CNTL 0xb4 |
1928 | #define ixD3F2_PCIE_LC_FORCE_COEFF 0xb8 |
1929 | #define ixD3F2_PCIE_LC_BEST_EQ_SETTINGS 0xb9 |
1930 | #define ixD3F2_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba |
1931 | #define ixD3F2_PCIE_LC_STATE0 0xa5 |
1932 | #define ixD3F2_PCIE_LC_STATE1 0xa6 |
1933 | #define ixD3F2_PCIE_LC_STATE2 0xa7 |
1934 | #define ixD3F2_PCIE_LC_STATE3 0xa8 |
1935 | #define ixD3F2_PCIE_LC_STATE4 0xa9 |
1936 | #define ixD3F2_PCIE_LC_STATE5 0xaa |
1937 | #define ixD3F2_PCIEP_STRAP_LC 0xc0 |
1938 | #define ixD3F2_PCIEP_STRAP_MISC 0xc1 |
1939 | #define ixD3F2_PCIEP_BCH_ECC_CNTL 0xd0 |
1940 | #define ixD3F2_PCIEP_HPGI_PRIVATE 0xd2 |
1941 | #define ixD3F2_PCIEP_HPGI 0xda |
1942 | #define ixD3F2_VENDOR_ID 0x8000000 |
1943 | #define ixD3F2_DEVICE_ID 0x8000000 |
1944 | #define ixD3F2_COMMAND 0x8000001 |
1945 | #define ixD3F2_STATUS 0x8000001 |
1946 | #define ixD3F2_REVISION_ID 0x8000002 |
1947 | #define ixD3F2_PROG_INTERFACE 0x8000002 |
1948 | #define ixD3F2_SUB_CLASS 0x8000002 |
1949 | #define ixD3F2_BASE_CLASS 0x8000002 |
1950 | #define ixD3F2_CACHE_LINE 0x8000003 |
1951 | #define ixD3F2_LATENCY 0x8000003 |
1952 | #define 0x8000003 |
1953 | #define ixD3F2_BIST 0x8000003 |
1954 | #define ixD3F2_SUB_BUS_NUMBER_LATENCY 0x8000006 |
1955 | #define ixD3F2_IO_BASE_LIMIT 0x8000007 |
1956 | #define ixD3F2_SECONDARY_STATUS 0x8000007 |
1957 | #define ixD3F2_MEM_BASE_LIMIT 0x8000008 |
1958 | #define ixD3F2_PREF_BASE_LIMIT 0x8000009 |
1959 | #define ixD3F2_PREF_BASE_UPPER 0x800000a |
1960 | #define ixD3F2_PREF_LIMIT_UPPER 0x800000b |
1961 | #define ixD3F2_IO_BASE_LIMIT_HI 0x800000c |
1962 | #define ixD3F2_IRQ_BRIDGE_CNTL 0x800000f |
1963 | #define ixD3F2_CAP_PTR 0x800000d |
1964 | #define ixD3F2_INTERRUPT_LINE 0x800000f |
1965 | #define ixD3F2_INTERRUPT_PIN 0x800000f |
1966 | #define ixD3F2_EXT_BRIDGE_CNTL 0x8000010 |
1967 | #define ixD3F2_PMI_CAP_LIST 0x8000014 |
1968 | #define ixD3F2_PMI_CAP 0x8000014 |
1969 | #define ixD3F2_PMI_STATUS_CNTL 0x8000015 |
1970 | #define ixD3F2_PCIE_CAP_LIST 0x8000016 |
1971 | #define ixD3F2_PCIE_CAP 0x8000016 |
1972 | #define ixD3F2_DEVICE_CAP 0x8000017 |
1973 | #define ixD3F2_DEVICE_CNTL 0x8000018 |
1974 | #define ixD3F2_DEVICE_STATUS 0x8000018 |
1975 | #define ixD3F2_LINK_CAP 0x8000019 |
1976 | #define ixD3F2_LINK_CNTL 0x800001a |
1977 | #define ixD3F2_LINK_STATUS 0x800001a |
1978 | #define ixD3F2_SLOT_CAP 0x800001b |
1979 | #define ixD3F2_SLOT_CNTL 0x800001c |
1980 | #define ixD3F2_SLOT_STATUS 0x800001c |
1981 | #define ixD3F2_ROOT_CNTL 0x800001d |
1982 | #define ixD3F2_ROOT_CAP 0x800001d |
1983 | #define ixD3F2_ROOT_STATUS 0x800001e |
1984 | #define ixD3F2_DEVICE_CAP2 0x800001f |
1985 | #define ixD3F2_DEVICE_CNTL2 0x8000020 |
1986 | #define ixD3F2_DEVICE_STATUS2 0x8000020 |
1987 | #define ixD3F2_LINK_CAP2 0x8000021 |
1988 | #define ixD3F2_LINK_CNTL2 0x8000022 |
1989 | #define ixD3F2_LINK_STATUS2 0x8000022 |
1990 | #define ixD3F2_SLOT_CAP2 0x8000023 |
1991 | #define ixD3F2_SLOT_CNTL2 0x8000024 |
1992 | #define ixD3F2_SLOT_STATUS2 0x8000024 |
1993 | #define ixD3F2_MSI_CAP_LIST 0x8000028 |
1994 | #define ixD3F2_MSI_MSG_CNTL 0x8000028 |
1995 | #define ixD3F2_MSI_MSG_ADDR_LO 0x8000029 |
1996 | #define ixD3F2_MSI_MSG_ADDR_HI 0x800002a |
1997 | #define ixD3F2_MSI_MSG_DATA_64 0x800002b |
1998 | #define ixD3F2_MSI_MSG_DATA 0x800002a |
1999 | #define ixD3F2_SSID_CAP_LIST 0x8000030 |
2000 | #define ixD3F2_SSID_CAP 0x8000031 |
2001 | #define ixD3F2_MSI_MAP_CAP_LIST 0x8000032 |
2002 | #define ixD3F2_MSI_MAP_CAP 0x8000032 |
2003 | #define ixD3F2_MSI_MAP_ADDR_LO 0x8000033 |
2004 | #define ixD3F2_MSI_MAP_ADDR_HI 0x8000034 |
2005 | #define ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x8000040 |
2006 | #define ixD3F2_PCIE_VENDOR_SPECIFIC_HDR 0x8000041 |
2007 | #define ixD3F2_PCIE_VENDOR_SPECIFIC1 0x8000042 |
2008 | #define ixD3F2_PCIE_VENDOR_SPECIFIC2 0x8000043 |
2009 | #define ixD3F2_PCIE_VC_ENH_CAP_LIST 0x8000044 |
2010 | #define ixD3F2_PCIE_PORT_VC_CAP_REG1 0x8000045 |
2011 | #define ixD3F2_PCIE_PORT_VC_CAP_REG2 0x8000046 |
2012 | #define ixD3F2_PCIE_PORT_VC_CNTL 0x8000047 |
2013 | #define ixD3F2_PCIE_PORT_VC_STATUS 0x8000047 |
2014 | #define ixD3F2_PCIE_VC0_RESOURCE_CAP 0x8000048 |
2015 | #define ixD3F2_PCIE_VC0_RESOURCE_CNTL 0x8000049 |
2016 | #define ixD3F2_PCIE_VC0_RESOURCE_STATUS 0x800004a |
2017 | #define ixD3F2_PCIE_VC1_RESOURCE_CAP 0x800004b |
2018 | #define ixD3F2_PCIE_VC1_RESOURCE_CNTL 0x800004c |
2019 | #define ixD3F2_PCIE_VC1_RESOURCE_STATUS 0x800004d |
2020 | #define ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x8000050 |
2021 | #define ixD3F2_PCIE_DEV_SERIAL_NUM_DW1 0x8000051 |
2022 | #define ixD3F2_PCIE_DEV_SERIAL_NUM_DW2 0x8000052 |
2023 | #define ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x8000054 |
2024 | #define ixD3F2_PCIE_UNCORR_ERR_STATUS 0x8000055 |
2025 | #define ixD3F2_PCIE_UNCORR_ERR_MASK 0x8000056 |
2026 | #define ixD3F2_PCIE_UNCORR_ERR_SEVERITY 0x8000057 |
2027 | #define ixD3F2_PCIE_CORR_ERR_STATUS 0x8000058 |
2028 | #define ixD3F2_PCIE_CORR_ERR_MASK 0x8000059 |
2029 | #define ixD3F2_PCIE_ADV_ERR_CAP_CNTL 0x800005a |
2030 | #define ixD3F2_PCIE_HDR_LOG0 0x800005b |
2031 | #define ixD3F2_PCIE_HDR_LOG1 0x800005c |
2032 | #define ixD3F2_PCIE_HDR_LOG2 0x800005d |
2033 | #define ixD3F2_PCIE_HDR_LOG3 0x800005e |
2034 | #define ixD3F2_PCIE_ROOT_ERR_CMD 0x800005f |
2035 | #define ixD3F2_PCIE_ROOT_ERR_STATUS 0x8000060 |
2036 | #define ixD3F2_PCIE_ERR_SRC_ID 0x8000061 |
2037 | #define ixD3F2_PCIE_TLP_PREFIX_LOG0 0x8000062 |
2038 | #define ixD3F2_PCIE_TLP_PREFIX_LOG1 0x8000063 |
2039 | #define ixD3F2_PCIE_TLP_PREFIX_LOG2 0x8000064 |
2040 | #define ixD3F2_PCIE_TLP_PREFIX_LOG3 0x8000065 |
2041 | #define ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST 0x800009c |
2042 | #define ixD3F2_PCIE_LINK_CNTL3 0x800009d |
2043 | #define ixD3F2_PCIE_LANE_ERROR_STATUS 0x800009e |
2044 | #define ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL 0x800009f |
2045 | #define ixD3F2_PCIE_LANE_1_EQUALIZATION_CNTL 0x800009f |
2046 | #define ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL 0x80000a0 |
2047 | #define ixD3F2_PCIE_LANE_3_EQUALIZATION_CNTL 0x80000a0 |
2048 | #define ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL 0x80000a1 |
2049 | #define ixD3F2_PCIE_LANE_5_EQUALIZATION_CNTL 0x80000a1 |
2050 | #define ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL 0x80000a2 |
2051 | #define ixD3F2_PCIE_LANE_7_EQUALIZATION_CNTL 0x80000a2 |
2052 | #define ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL 0x80000a3 |
2053 | #define ixD3F2_PCIE_LANE_9_EQUALIZATION_CNTL 0x80000a3 |
2054 | #define ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL 0x80000a4 |
2055 | #define ixD3F2_PCIE_LANE_11_EQUALIZATION_CNTL 0x80000a4 |
2056 | #define ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL 0x80000a5 |
2057 | #define ixD3F2_PCIE_LANE_13_EQUALIZATION_CNTL 0x80000a5 |
2058 | #define ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL 0x80000a6 |
2059 | #define ixD3F2_PCIE_LANE_15_EQUALIZATION_CNTL 0x80000a6 |
2060 | #define ixD3F2_PCIE_ACS_ENH_CAP_LIST 0x80000a8 |
2061 | #define ixD3F2_PCIE_ACS_CAP 0x80000a9 |
2062 | #define ixD3F2_PCIE_ACS_CNTL 0x80000a9 |
2063 | #define ixD3F2_PCIE_MC_ENH_CAP_LIST 0x80000bc |
2064 | #define ixD3F2_PCIE_MC_CAP 0x80000bd |
2065 | #define ixD3F2_PCIE_MC_CNTL 0x80000bd |
2066 | #define ixD3F2_PCIE_MC_ADDR0 0x80000be |
2067 | #define ixD3F2_PCIE_MC_ADDR1 0x80000bf |
2068 | #define ixD3F2_PCIE_MC_RCV0 0x80000c0 |
2069 | #define ixD3F2_PCIE_MC_RCV1 0x80000c1 |
2070 | #define ixD3F2_PCIE_MC_BLOCK_ALL0 0x80000c2 |
2071 | #define ixD3F2_PCIE_MC_BLOCK_ALL1 0x80000c3 |
2072 | #define ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0 0x80000c4 |
2073 | #define ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1 0x80000c5 |
2074 | #define ixD3F2_PCIE_MC_OVERLAY_BAR0 0x80000c6 |
2075 | #define ixD3F2_PCIE_MC_OVERLAY_BAR1 0x80000c7 |
2076 | #define ixD3F3_PCIE_PORT_INDEX 0x9000038 |
2077 | #define ixD3F3_PCIE_PORT_DATA 0x9000039 |
2078 | #define ixD3F3_PCIEP_RESERVED 0x0 |
2079 | #define ixD3F3_PCIEP_SCRATCH 0x1 |
2080 | #define ixD3F3_PCIEP_HW_DEBUG 0x2 |
2081 | #define ixD3F3_PCIEP_PORT_CNTL 0x10 |
2082 | #define ixD3F3_PCIE_TX_CNTL 0x20 |
2083 | #define ixD3F3_PCIE_TX_REQUESTER_ID 0x21 |
2084 | #define ixD3F3_PCIE_TX_VENDOR_SPECIFIC 0x22 |
2085 | #define ixD3F3_PCIE_TX_REQUEST_NUM_CNTL 0x23 |
2086 | #define ixD3F3_PCIE_TX_SEQ 0x24 |
2087 | #define ixD3F3_PCIE_TX_REPLAY 0x25 |
2088 | #define ixD3F3_PCIE_TX_ACK_LATENCY_LIMIT 0x26 |
2089 | #define ixD3F3_PCIE_TX_CREDITS_ADVT_P 0x30 |
2090 | #define ixD3F3_PCIE_TX_CREDITS_ADVT_NP 0x31 |
2091 | #define ixD3F3_PCIE_TX_CREDITS_ADVT_CPL 0x32 |
2092 | #define ixD3F3_PCIE_TX_CREDITS_INIT_P 0x33 |
2093 | #define ixD3F3_PCIE_TX_CREDITS_INIT_NP 0x34 |
2094 | #define ixD3F3_PCIE_TX_CREDITS_INIT_CPL 0x35 |
2095 | #define ixD3F3_PCIE_TX_CREDITS_STATUS 0x36 |
2096 | #define ixD3F3_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 |
2097 | #define ixD3F3_PCIE_P_PORT_LANE_STATUS 0x50 |
2098 | #define ixD3F3_PCIE_FC_P 0x60 |
2099 | #define ixD3F3_PCIE_FC_NP 0x61 |
2100 | #define ixD3F3_PCIE_FC_CPL 0x62 |
2101 | #define ixD3F3_PCIE_ERR_CNTL 0x6a |
2102 | #define ixD3F3_PCIE_RX_CNTL 0x70 |
2103 | #define ixD3F3_PCIE_RX_EXPECTED_SEQNUM 0x71 |
2104 | #define ixD3F3_PCIE_RX_VENDOR_SPECIFIC 0x72 |
2105 | #define ixD3F3_PCIE_RX_CNTL3 0x74 |
2106 | #define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_P 0x80 |
2107 | #define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 |
2108 | #define ixD3F3_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 |
2109 | #define ixD3F3_PCIEP_ERROR_INJECT_PHYSICAL 0x83 |
2110 | #define ixD3F3_PCIEP_ERROR_INJECT_TRANSACTION 0x84 |
2111 | #define ixD3F3_PCIE_LC_CNTL 0xa0 |
2112 | #define ixD3F3_PCIE_LC_CNTL2 0xb1 |
2113 | #define ixD3F3_PCIE_LC_CNTL3 0xb5 |
2114 | #define ixD3F3_PCIE_LC_CNTL4 0xb6 |
2115 | #define ixD3F3_PCIE_LC_CNTL5 0xb7 |
2116 | #define ixD3F3_PCIE_LC_CNTL6 0xbb |
2117 | #define ixD3F3_PCIE_LC_BW_CHANGE_CNTL 0xb2 |
2118 | #define ixD3F3_PCIE_LC_TRAINING_CNTL 0xa1 |
2119 | #define ixD3F3_PCIE_LC_LINK_WIDTH_CNTL 0xa2 |
2120 | #define ixD3F3_PCIE_LC_N_FTS_CNTL 0xa3 |
2121 | #define ixD3F3_PCIE_LC_SPEED_CNTL 0xa4 |
2122 | #define ixD3F3_PCIE_LC_CDR_CNTL 0xb3 |
2123 | #define ixD3F3_PCIE_LC_LANE_CNTL 0xb4 |
2124 | #define ixD3F3_PCIE_LC_FORCE_COEFF 0xb8 |
2125 | #define ixD3F3_PCIE_LC_BEST_EQ_SETTINGS 0xb9 |
2126 | #define ixD3F3_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba |
2127 | #define ixD3F3_PCIE_LC_STATE0 0xa5 |
2128 | #define ixD3F3_PCIE_LC_STATE1 0xa6 |
2129 | #define ixD3F3_PCIE_LC_STATE2 0xa7 |
2130 | #define ixD3F3_PCIE_LC_STATE3 0xa8 |
2131 | #define ixD3F3_PCIE_LC_STATE4 0xa9 |
2132 | #define ixD3F3_PCIE_LC_STATE5 0xaa |
2133 | #define ixD3F3_PCIEP_STRAP_LC 0xc0 |
2134 | #define ixD3F3_PCIEP_STRAP_MISC 0xc1 |
2135 | #define ixD3F3_PCIEP_BCH_ECC_CNTL 0xd0 |
2136 | #define ixD3F3_PCIEP_HPGI_PRIVATE 0xd2 |
2137 | #define ixD3F3_PCIEP_HPGI 0xda |
2138 | #define ixD3F3_VENDOR_ID 0x9000000 |
2139 | #define ixD3F3_DEVICE_ID 0x9000000 |
2140 | #define ixD3F3_COMMAND 0x9000001 |
2141 | #define ixD3F3_STATUS 0x9000001 |
2142 | #define ixD3F3_REVISION_ID 0x9000002 |
2143 | #define ixD3F3_PROG_INTERFACE 0x9000002 |
2144 | #define ixD3F3_SUB_CLASS 0x9000002 |
2145 | #define ixD3F3_BASE_CLASS 0x9000002 |
2146 | #define ixD3F3_CACHE_LINE 0x9000003 |
2147 | #define ixD3F3_LATENCY 0x9000003 |
2148 | #define 0x9000003 |
2149 | #define ixD3F3_BIST 0x9000003 |
2150 | #define ixD3F3_SUB_BUS_NUMBER_LATENCY 0x9000006 |
2151 | #define ixD3F3_IO_BASE_LIMIT 0x9000007 |
2152 | #define ixD3F3_SECONDARY_STATUS 0x9000007 |
2153 | #define ixD3F3_MEM_BASE_LIMIT 0x9000008 |
2154 | #define ixD3F3_PREF_BASE_LIMIT 0x9000009 |
2155 | #define ixD3F3_PREF_BASE_UPPER 0x900000a |
2156 | #define ixD3F3_PREF_LIMIT_UPPER 0x900000b |
2157 | #define ixD3F3_IO_BASE_LIMIT_HI 0x900000c |
2158 | #define ixD3F3_IRQ_BRIDGE_CNTL 0x900000f |
2159 | #define ixD3F3_CAP_PTR 0x900000d |
2160 | #define ixD3F3_INTERRUPT_LINE 0x900000f |
2161 | #define ixD3F3_INTERRUPT_PIN 0x900000f |
2162 | #define ixD3F3_EXT_BRIDGE_CNTL 0x9000010 |
2163 | #define ixD3F3_PMI_CAP_LIST 0x9000014 |
2164 | #define ixD3F3_PMI_CAP 0x9000014 |
2165 | #define ixD3F3_PMI_STATUS_CNTL 0x9000015 |
2166 | #define ixD3F3_PCIE_CAP_LIST 0x9000016 |
2167 | #define ixD3F3_PCIE_CAP 0x9000016 |
2168 | #define ixD3F3_DEVICE_CAP 0x9000017 |
2169 | #define ixD3F3_DEVICE_CNTL 0x9000018 |
2170 | #define ixD3F3_DEVICE_STATUS 0x9000018 |
2171 | #define ixD3F3_LINK_CAP 0x9000019 |
2172 | #define ixD3F3_LINK_CNTL 0x900001a |
2173 | #define ixD3F3_LINK_STATUS 0x900001a |
2174 | #define ixD3F3_SLOT_CAP 0x900001b |
2175 | #define ixD3F3_SLOT_CNTL 0x900001c |
2176 | #define ixD3F3_SLOT_STATUS 0x900001c |
2177 | #define ixD3F3_ROOT_CNTL 0x900001d |
2178 | #define ixD3F3_ROOT_CAP 0x900001d |
2179 | #define ixD3F3_ROOT_STATUS 0x900001e |
2180 | #define ixD3F3_DEVICE_CAP2 0x900001f |
2181 | #define ixD3F3_DEVICE_CNTL2 0x9000020 |
2182 | #define ixD3F3_DEVICE_STATUS2 0x9000020 |
2183 | #define ixD3F3_LINK_CAP2 0x9000021 |
2184 | #define ixD3F3_LINK_CNTL2 0x9000022 |
2185 | #define ixD3F3_LINK_STATUS2 0x9000022 |
2186 | #define ixD3F3_SLOT_CAP2 0x9000023 |
2187 | #define ixD3F3_SLOT_CNTL2 0x9000024 |
2188 | #define ixD3F3_SLOT_STATUS2 0x9000024 |
2189 | #define ixD3F3_MSI_CAP_LIST 0x9000028 |
2190 | #define ixD3F3_MSI_MSG_CNTL 0x9000028 |
2191 | #define ixD3F3_MSI_MSG_ADDR_LO 0x9000029 |
2192 | #define ixD3F3_MSI_MSG_ADDR_HI 0x900002a |
2193 | #define ixD3F3_MSI_MSG_DATA_64 0x900002b |
2194 | #define ixD3F3_MSI_MSG_DATA 0x900002a |
2195 | #define ixD3F3_SSID_CAP_LIST 0x9000030 |
2196 | #define ixD3F3_SSID_CAP 0x9000031 |
2197 | #define ixD3F3_MSI_MAP_CAP_LIST 0x9000032 |
2198 | #define ixD3F3_MSI_MAP_CAP 0x9000032 |
2199 | #define ixD3F3_MSI_MAP_ADDR_LO 0x9000033 |
2200 | #define ixD3F3_MSI_MAP_ADDR_HI 0x9000034 |
2201 | #define ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x9000040 |
2202 | #define ixD3F3_PCIE_VENDOR_SPECIFIC_HDR 0x9000041 |
2203 | #define ixD3F3_PCIE_VENDOR_SPECIFIC1 0x9000042 |
2204 | #define ixD3F3_PCIE_VENDOR_SPECIFIC2 0x9000043 |
2205 | #define ixD3F3_PCIE_VC_ENH_CAP_LIST 0x9000044 |
2206 | #define ixD3F3_PCIE_PORT_VC_CAP_REG1 0x9000045 |
2207 | #define ixD3F3_PCIE_PORT_VC_CAP_REG2 0x9000046 |
2208 | #define ixD3F3_PCIE_PORT_VC_CNTL 0x9000047 |
2209 | #define ixD3F3_PCIE_PORT_VC_STATUS 0x9000047 |
2210 | #define ixD3F3_PCIE_VC0_RESOURCE_CAP 0x9000048 |
2211 | #define ixD3F3_PCIE_VC0_RESOURCE_CNTL 0x9000049 |
2212 | #define ixD3F3_PCIE_VC0_RESOURCE_STATUS 0x900004a |
2213 | #define ixD3F3_PCIE_VC1_RESOURCE_CAP 0x900004b |
2214 | #define ixD3F3_PCIE_VC1_RESOURCE_CNTL 0x900004c |
2215 | #define ixD3F3_PCIE_VC1_RESOURCE_STATUS 0x900004d |
2216 | #define ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x9000050 |
2217 | #define ixD3F3_PCIE_DEV_SERIAL_NUM_DW1 0x9000051 |
2218 | #define ixD3F3_PCIE_DEV_SERIAL_NUM_DW2 0x9000052 |
2219 | #define ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x9000054 |
2220 | #define ixD3F3_PCIE_UNCORR_ERR_STATUS 0x9000055 |
2221 | #define ixD3F3_PCIE_UNCORR_ERR_MASK 0x9000056 |
2222 | #define ixD3F3_PCIE_UNCORR_ERR_SEVERITY 0x9000057 |
2223 | #define ixD3F3_PCIE_CORR_ERR_STATUS 0x9000058 |
2224 | #define ixD3F3_PCIE_CORR_ERR_MASK 0x9000059 |
2225 | #define ixD3F3_PCIE_ADV_ERR_CAP_CNTL 0x900005a |
2226 | #define ixD3F3_PCIE_HDR_LOG0 0x900005b |
2227 | #define ixD3F3_PCIE_HDR_LOG1 0x900005c |
2228 | #define ixD3F3_PCIE_HDR_LOG2 0x900005d |
2229 | #define ixD3F3_PCIE_HDR_LOG3 0x900005e |
2230 | #define ixD3F3_PCIE_ROOT_ERR_CMD 0x900005f |
2231 | #define ixD3F3_PCIE_ROOT_ERR_STATUS 0x9000060 |
2232 | #define ixD3F3_PCIE_ERR_SRC_ID 0x9000061 |
2233 | #define ixD3F3_PCIE_TLP_PREFIX_LOG0 0x9000062 |
2234 | #define ixD3F3_PCIE_TLP_PREFIX_LOG1 0x9000063 |
2235 | #define ixD3F3_PCIE_TLP_PREFIX_LOG2 0x9000064 |
2236 | #define ixD3F3_PCIE_TLP_PREFIX_LOG3 0x9000065 |
2237 | #define ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST 0x900009c |
2238 | #define ixD3F3_PCIE_LINK_CNTL3 0x900009d |
2239 | #define ixD3F3_PCIE_LANE_ERROR_STATUS 0x900009e |
2240 | #define ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL 0x900009f |
2241 | #define ixD3F3_PCIE_LANE_1_EQUALIZATION_CNTL 0x900009f |
2242 | #define ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL 0x90000a0 |
2243 | #define ixD3F3_PCIE_LANE_3_EQUALIZATION_CNTL 0x90000a0 |
2244 | #define ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL 0x90000a1 |
2245 | #define ixD3F3_PCIE_LANE_5_EQUALIZATION_CNTL 0x90000a1 |
2246 | #define ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL 0x90000a2 |
2247 | #define ixD3F3_PCIE_LANE_7_EQUALIZATION_CNTL 0x90000a2 |
2248 | #define ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL 0x90000a3 |
2249 | #define ixD3F3_PCIE_LANE_9_EQUALIZATION_CNTL 0x90000a3 |
2250 | #define ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL 0x90000a4 |
2251 | #define ixD3F3_PCIE_LANE_11_EQUALIZATION_CNTL 0x90000a4 |
2252 | #define ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL 0x90000a5 |
2253 | #define ixD3F3_PCIE_LANE_13_EQUALIZATION_CNTL 0x90000a5 |
2254 | #define ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL 0x90000a6 |
2255 | #define ixD3F3_PCIE_LANE_15_EQUALIZATION_CNTL 0x90000a6 |
2256 | #define ixD3F3_PCIE_ACS_ENH_CAP_LIST 0x90000a8 |
2257 | #define ixD3F3_PCIE_ACS_CAP 0x90000a9 |
2258 | #define ixD3F3_PCIE_ACS_CNTL 0x90000a9 |
2259 | #define ixD3F3_PCIE_MC_ENH_CAP_LIST 0x90000bc |
2260 | #define ixD3F3_PCIE_MC_CAP 0x90000bd |
2261 | #define ixD3F3_PCIE_MC_CNTL 0x90000bd |
2262 | #define ixD3F3_PCIE_MC_ADDR0 0x90000be |
2263 | #define ixD3F3_PCIE_MC_ADDR1 0x90000bf |
2264 | #define ixD3F3_PCIE_MC_RCV0 0x90000c0 |
2265 | #define ixD3F3_PCIE_MC_RCV1 0x90000c1 |
2266 | #define ixD3F3_PCIE_MC_BLOCK_ALL0 0x90000c2 |
2267 | #define ixD3F3_PCIE_MC_BLOCK_ALL1 0x90000c3 |
2268 | #define ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0 0x90000c4 |
2269 | #define ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1 0x90000c5 |
2270 | #define ixD3F3_PCIE_MC_OVERLAY_BAR0 0x90000c6 |
2271 | #define ixD3F3_PCIE_MC_OVERLAY_BAR1 0x90000c7 |
2272 | #define ixD3F4_PCIE_PORT_INDEX 0xa000038 |
2273 | #define ixD3F4_PCIE_PORT_DATA 0xa000039 |
2274 | #define ixD3F4_PCIEP_RESERVED 0x0 |
2275 | #define ixD3F4_PCIEP_SCRATCH 0x1 |
2276 | #define ixD3F4_PCIEP_HW_DEBUG 0x2 |
2277 | #define ixD3F4_PCIEP_PORT_CNTL 0x10 |
2278 | #define ixD3F4_PCIE_TX_CNTL 0x20 |
2279 | #define ixD3F4_PCIE_TX_REQUESTER_ID 0x21 |
2280 | #define ixD3F4_PCIE_TX_VENDOR_SPECIFIC 0x22 |
2281 | #define ixD3F4_PCIE_TX_REQUEST_NUM_CNTL 0x23 |
2282 | #define ixD3F4_PCIE_TX_SEQ 0x24 |
2283 | #define ixD3F4_PCIE_TX_REPLAY 0x25 |
2284 | #define ixD3F4_PCIE_TX_ACK_LATENCY_LIMIT 0x26 |
2285 | #define ixD3F4_PCIE_TX_CREDITS_ADVT_P 0x30 |
2286 | #define ixD3F4_PCIE_TX_CREDITS_ADVT_NP 0x31 |
2287 | #define ixD3F4_PCIE_TX_CREDITS_ADVT_CPL 0x32 |
2288 | #define ixD3F4_PCIE_TX_CREDITS_INIT_P 0x33 |
2289 | #define ixD3F4_PCIE_TX_CREDITS_INIT_NP 0x34 |
2290 | #define ixD3F4_PCIE_TX_CREDITS_INIT_CPL 0x35 |
2291 | #define ixD3F4_PCIE_TX_CREDITS_STATUS 0x36 |
2292 | #define ixD3F4_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 |
2293 | #define ixD3F4_PCIE_P_PORT_LANE_STATUS 0x50 |
2294 | #define ixD3F4_PCIE_FC_P 0x60 |
2295 | #define ixD3F4_PCIE_FC_NP 0x61 |
2296 | #define ixD3F4_PCIE_FC_CPL 0x62 |
2297 | #define ixD3F4_PCIE_ERR_CNTL 0x6a |
2298 | #define ixD3F4_PCIE_RX_CNTL 0x70 |
2299 | #define ixD3F4_PCIE_RX_EXPECTED_SEQNUM 0x71 |
2300 | #define ixD3F4_PCIE_RX_VENDOR_SPECIFIC 0x72 |
2301 | #define ixD3F4_PCIE_RX_CNTL3 0x74 |
2302 | #define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_P 0x80 |
2303 | #define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 |
2304 | #define ixD3F4_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 |
2305 | #define ixD3F4_PCIEP_ERROR_INJECT_PHYSICAL 0x83 |
2306 | #define ixD3F4_PCIEP_ERROR_INJECT_TRANSACTION 0x84 |
2307 | #define ixD3F4_PCIE_LC_CNTL 0xa0 |
2308 | #define ixD3F4_PCIE_LC_CNTL2 0xb1 |
2309 | #define ixD3F4_PCIE_LC_CNTL3 0xb5 |
2310 | #define ixD3F4_PCIE_LC_CNTL4 0xb6 |
2311 | #define ixD3F4_PCIE_LC_CNTL5 0xb7 |
2312 | #define ixD3F4_PCIE_LC_CNTL6 0xbb |
2313 | #define ixD3F4_PCIE_LC_BW_CHANGE_CNTL 0xb2 |
2314 | #define ixD3F4_PCIE_LC_TRAINING_CNTL 0xa1 |
2315 | #define ixD3F4_PCIE_LC_LINK_WIDTH_CNTL 0xa2 |
2316 | #define ixD3F4_PCIE_LC_N_FTS_CNTL 0xa3 |
2317 | #define ixD3F4_PCIE_LC_SPEED_CNTL 0xa4 |
2318 | #define ixD3F4_PCIE_LC_CDR_CNTL 0xb3 |
2319 | #define ixD3F4_PCIE_LC_LANE_CNTL 0xb4 |
2320 | #define ixD3F4_PCIE_LC_FORCE_COEFF 0xb8 |
2321 | #define ixD3F4_PCIE_LC_BEST_EQ_SETTINGS 0xb9 |
2322 | #define ixD3F4_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba |
2323 | #define ixD3F4_PCIE_LC_STATE0 0xa5 |
2324 | #define ixD3F4_PCIE_LC_STATE1 0xa6 |
2325 | #define ixD3F4_PCIE_LC_STATE2 0xa7 |
2326 | #define ixD3F4_PCIE_LC_STATE3 0xa8 |
2327 | #define ixD3F4_PCIE_LC_STATE4 0xa9 |
2328 | #define ixD3F4_PCIE_LC_STATE5 0xaa |
2329 | #define ixD3F4_PCIEP_STRAP_LC 0xc0 |
2330 | #define ixD3F4_PCIEP_STRAP_MISC 0xc1 |
2331 | #define ixD3F4_PCIEP_BCH_ECC_CNTL 0xd0 |
2332 | #define ixD3F4_PCIEP_HPGI_PRIVATE 0xd2 |
2333 | #define ixD3F4_PCIEP_HPGI 0xda |
2334 | #define ixD3F4_VENDOR_ID 0xa000000 |
2335 | #define ixD3F4_DEVICE_ID 0xa000000 |
2336 | #define ixD3F4_COMMAND 0xa000001 |
2337 | #define ixD3F4_STATUS 0xa000001 |
2338 | #define ixD3F4_REVISION_ID 0xa000002 |
2339 | #define ixD3F4_PROG_INTERFACE 0xa000002 |
2340 | #define ixD3F4_SUB_CLASS 0xa000002 |
2341 | #define ixD3F4_BASE_CLASS 0xa000002 |
2342 | #define ixD3F4_CACHE_LINE 0xa000003 |
2343 | #define ixD3F4_LATENCY 0xa000003 |
2344 | #define 0xa000003 |
2345 | #define ixD3F4_BIST 0xa000003 |
2346 | #define ixD3F4_SUB_BUS_NUMBER_LATENCY 0xa000006 |
2347 | #define ixD3F4_IO_BASE_LIMIT 0xa000007 |
2348 | #define ixD3F4_SECONDARY_STATUS 0xa000007 |
2349 | #define ixD3F4_MEM_BASE_LIMIT 0xa000008 |
2350 | #define ixD3F4_PREF_BASE_LIMIT 0xa000009 |
2351 | #define ixD3F4_PREF_BASE_UPPER 0xa00000a |
2352 | #define ixD3F4_PREF_LIMIT_UPPER 0xa00000b |
2353 | #define ixD3F4_IO_BASE_LIMIT_HI 0xa00000c |
2354 | #define ixD3F4_IRQ_BRIDGE_CNTL 0xa00000f |
2355 | #define ixD3F4_CAP_PTR 0xa00000d |
2356 | #define ixD3F4_INTERRUPT_LINE 0xa00000f |
2357 | #define ixD3F4_INTERRUPT_PIN 0xa00000f |
2358 | #define ixD3F4_EXT_BRIDGE_CNTL 0xa000010 |
2359 | #define ixD3F4_PMI_CAP_LIST 0xa000014 |
2360 | #define ixD3F4_PMI_CAP 0xa000014 |
2361 | #define ixD3F4_PMI_STATUS_CNTL 0xa000015 |
2362 | #define ixD3F4_PCIE_CAP_LIST 0xa000016 |
2363 | #define ixD3F4_PCIE_CAP 0xa000016 |
2364 | #define ixD3F4_DEVICE_CAP 0xa000017 |
2365 | #define ixD3F4_DEVICE_CNTL 0xa000018 |
2366 | #define ixD3F4_DEVICE_STATUS 0xa000018 |
2367 | #define ixD3F4_LINK_CAP 0xa000019 |
2368 | #define ixD3F4_LINK_CNTL 0xa00001a |
2369 | #define ixD3F4_LINK_STATUS 0xa00001a |
2370 | #define ixD3F4_SLOT_CAP 0xa00001b |
2371 | #define ixD3F4_SLOT_CNTL 0xa00001c |
2372 | #define ixD3F4_SLOT_STATUS 0xa00001c |
2373 | #define ixD3F4_ROOT_CNTL 0xa00001d |
2374 | #define ixD3F4_ROOT_CAP 0xa00001d |
2375 | #define ixD3F4_ROOT_STATUS 0xa00001e |
2376 | #define ixD3F4_DEVICE_CAP2 0xa00001f |
2377 | #define ixD3F4_DEVICE_CNTL2 0xa000020 |
2378 | #define ixD3F4_DEVICE_STATUS2 0xa000020 |
2379 | #define ixD3F4_LINK_CAP2 0xa000021 |
2380 | #define ixD3F4_LINK_CNTL2 0xa000022 |
2381 | #define ixD3F4_LINK_STATUS2 0xa000022 |
2382 | #define ixD3F4_SLOT_CAP2 0xa000023 |
2383 | #define ixD3F4_SLOT_CNTL2 0xa000024 |
2384 | #define ixD3F4_SLOT_STATUS2 0xa000024 |
2385 | #define ixD3F4_MSI_CAP_LIST 0xa000028 |
2386 | #define ixD3F4_MSI_MSG_CNTL 0xa000028 |
2387 | #define ixD3F4_MSI_MSG_ADDR_LO 0xa000029 |
2388 | #define ixD3F4_MSI_MSG_ADDR_HI 0xa00002a |
2389 | #define ixD3F4_MSI_MSG_DATA_64 0xa00002b |
2390 | #define ixD3F4_MSI_MSG_DATA 0xa00002a |
2391 | #define ixD3F4_SSID_CAP_LIST 0xa000030 |
2392 | #define ixD3F4_SSID_CAP 0xa000031 |
2393 | #define ixD3F4_MSI_MAP_CAP_LIST 0xa000032 |
2394 | #define ixD3F4_MSI_MAP_CAP 0xa000032 |
2395 | #define ixD3F4_MSI_MAP_ADDR_LO 0xa000033 |
2396 | #define ixD3F4_MSI_MAP_ADDR_HI 0xa000034 |
2397 | #define ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xa000040 |
2398 | #define ixD3F4_PCIE_VENDOR_SPECIFIC_HDR 0xa000041 |
2399 | #define ixD3F4_PCIE_VENDOR_SPECIFIC1 0xa000042 |
2400 | #define ixD3F4_PCIE_VENDOR_SPECIFIC2 0xa000043 |
2401 | #define ixD3F4_PCIE_VC_ENH_CAP_LIST 0xa000044 |
2402 | #define ixD3F4_PCIE_PORT_VC_CAP_REG1 0xa000045 |
2403 | #define ixD3F4_PCIE_PORT_VC_CAP_REG2 0xa000046 |
2404 | #define ixD3F4_PCIE_PORT_VC_CNTL 0xa000047 |
2405 | #define ixD3F4_PCIE_PORT_VC_STATUS 0xa000047 |
2406 | #define ixD3F4_PCIE_VC0_RESOURCE_CAP 0xa000048 |
2407 | #define ixD3F4_PCIE_VC0_RESOURCE_CNTL 0xa000049 |
2408 | #define ixD3F4_PCIE_VC0_RESOURCE_STATUS 0xa00004a |
2409 | #define ixD3F4_PCIE_VC1_RESOURCE_CAP 0xa00004b |
2410 | #define ixD3F4_PCIE_VC1_RESOURCE_CNTL 0xa00004c |
2411 | #define ixD3F4_PCIE_VC1_RESOURCE_STATUS 0xa00004d |
2412 | #define ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xa000050 |
2413 | #define ixD3F4_PCIE_DEV_SERIAL_NUM_DW1 0xa000051 |
2414 | #define ixD3F4_PCIE_DEV_SERIAL_NUM_DW2 0xa000052 |
2415 | #define ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xa000054 |
2416 | #define ixD3F4_PCIE_UNCORR_ERR_STATUS 0xa000055 |
2417 | #define ixD3F4_PCIE_UNCORR_ERR_MASK 0xa000056 |
2418 | #define ixD3F4_PCIE_UNCORR_ERR_SEVERITY 0xa000057 |
2419 | #define ixD3F4_PCIE_CORR_ERR_STATUS 0xa000058 |
2420 | #define ixD3F4_PCIE_CORR_ERR_MASK 0xa000059 |
2421 | #define ixD3F4_PCIE_ADV_ERR_CAP_CNTL 0xa00005a |
2422 | #define ixD3F4_PCIE_HDR_LOG0 0xa00005b |
2423 | #define ixD3F4_PCIE_HDR_LOG1 0xa00005c |
2424 | #define ixD3F4_PCIE_HDR_LOG2 0xa00005d |
2425 | #define ixD3F4_PCIE_HDR_LOG3 0xa00005e |
2426 | #define ixD3F4_PCIE_ROOT_ERR_CMD 0xa00005f |
2427 | #define ixD3F4_PCIE_ROOT_ERR_STATUS 0xa000060 |
2428 | #define ixD3F4_PCIE_ERR_SRC_ID 0xa000061 |
2429 | #define ixD3F4_PCIE_TLP_PREFIX_LOG0 0xa000062 |
2430 | #define ixD3F4_PCIE_TLP_PREFIX_LOG1 0xa000063 |
2431 | #define ixD3F4_PCIE_TLP_PREFIX_LOG2 0xa000064 |
2432 | #define ixD3F4_PCIE_TLP_PREFIX_LOG3 0xa000065 |
2433 | #define ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST 0xa00009c |
2434 | #define ixD3F4_PCIE_LINK_CNTL3 0xa00009d |
2435 | #define ixD3F4_PCIE_LANE_ERROR_STATUS 0xa00009e |
2436 | #define ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL 0xa00009f |
2437 | #define ixD3F4_PCIE_LANE_1_EQUALIZATION_CNTL 0xa00009f |
2438 | #define ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL 0xa0000a0 |
2439 | #define ixD3F4_PCIE_LANE_3_EQUALIZATION_CNTL 0xa0000a0 |
2440 | #define ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL 0xa0000a1 |
2441 | #define ixD3F4_PCIE_LANE_5_EQUALIZATION_CNTL 0xa0000a1 |
2442 | #define ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL 0xa0000a2 |
2443 | #define ixD3F4_PCIE_LANE_7_EQUALIZATION_CNTL 0xa0000a2 |
2444 | #define ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL 0xa0000a3 |
2445 | #define ixD3F4_PCIE_LANE_9_EQUALIZATION_CNTL 0xa0000a3 |
2446 | #define ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL 0xa0000a4 |
2447 | #define ixD3F4_PCIE_LANE_11_EQUALIZATION_CNTL 0xa0000a4 |
2448 | #define ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL 0xa0000a5 |
2449 | #define ixD3F4_PCIE_LANE_13_EQUALIZATION_CNTL 0xa0000a5 |
2450 | #define ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL 0xa0000a6 |
2451 | #define ixD3F4_PCIE_LANE_15_EQUALIZATION_CNTL 0xa0000a6 |
2452 | #define ixD3F4_PCIE_ACS_ENH_CAP_LIST 0xa0000a8 |
2453 | #define ixD3F4_PCIE_ACS_CAP 0xa0000a9 |
2454 | #define ixD3F4_PCIE_ACS_CNTL 0xa0000a9 |
2455 | #define ixD3F4_PCIE_MC_ENH_CAP_LIST 0xa0000bc |
2456 | #define ixD3F4_PCIE_MC_CAP 0xa0000bd |
2457 | #define ixD3F4_PCIE_MC_CNTL 0xa0000bd |
2458 | #define ixD3F4_PCIE_MC_ADDR0 0xa0000be |
2459 | #define ixD3F4_PCIE_MC_ADDR1 0xa0000bf |
2460 | #define ixD3F4_PCIE_MC_RCV0 0xa0000c0 |
2461 | #define ixD3F4_PCIE_MC_RCV1 0xa0000c1 |
2462 | #define ixD3F4_PCIE_MC_BLOCK_ALL0 0xa0000c2 |
2463 | #define ixD3F4_PCIE_MC_BLOCK_ALL1 0xa0000c3 |
2464 | #define ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0 0xa0000c4 |
2465 | #define ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1 0xa0000c5 |
2466 | #define ixD3F4_PCIE_MC_OVERLAY_BAR0 0xa0000c6 |
2467 | #define ixD3F4_PCIE_MC_OVERLAY_BAR1 0xa0000c7 |
2468 | #define ixD3F5_PCIE_PORT_INDEX 0xb000038 |
2469 | #define ixD3F5_PCIE_PORT_DATA 0xb000039 |
2470 | #define ixD3F5_PCIEP_RESERVED 0x0 |
2471 | #define ixD3F5_PCIEP_SCRATCH 0x1 |
2472 | #define ixD3F5_PCIEP_HW_DEBUG 0x2 |
2473 | #define ixD3F5_PCIEP_PORT_CNTL 0x10 |
2474 | #define ixD3F5_PCIE_TX_CNTL 0x20 |
2475 | #define ixD3F5_PCIE_TX_REQUESTER_ID 0x21 |
2476 | #define ixD3F5_PCIE_TX_VENDOR_SPECIFIC 0x22 |
2477 | #define ixD3F5_PCIE_TX_REQUEST_NUM_CNTL 0x23 |
2478 | #define ixD3F5_PCIE_TX_SEQ 0x24 |
2479 | #define ixD3F5_PCIE_TX_REPLAY 0x25 |
2480 | #define ixD3F5_PCIE_TX_ACK_LATENCY_LIMIT 0x26 |
2481 | #define ixD3F5_PCIE_TX_CREDITS_ADVT_P 0x30 |
2482 | #define ixD3F5_PCIE_TX_CREDITS_ADVT_NP 0x31 |
2483 | #define ixD3F5_PCIE_TX_CREDITS_ADVT_CPL 0x32 |
2484 | #define ixD3F5_PCIE_TX_CREDITS_INIT_P 0x33 |
2485 | #define ixD3F5_PCIE_TX_CREDITS_INIT_NP 0x34 |
2486 | #define ixD3F5_PCIE_TX_CREDITS_INIT_CPL 0x35 |
2487 | #define ixD3F5_PCIE_TX_CREDITS_STATUS 0x36 |
2488 | #define ixD3F5_PCIE_TX_CREDITS_FCU_THRESHOLD 0x37 |
2489 | #define ixD3F5_PCIE_P_PORT_LANE_STATUS 0x50 |
2490 | #define ixD3F5_PCIE_FC_P 0x60 |
2491 | #define ixD3F5_PCIE_FC_NP 0x61 |
2492 | #define ixD3F5_PCIE_FC_CPL 0x62 |
2493 | #define ixD3F5_PCIE_ERR_CNTL 0x6a |
2494 | #define ixD3F5_PCIE_RX_CNTL 0x70 |
2495 | #define ixD3F5_PCIE_RX_EXPECTED_SEQNUM 0x71 |
2496 | #define ixD3F5_PCIE_RX_VENDOR_SPECIFIC 0x72 |
2497 | #define ixD3F5_PCIE_RX_CNTL3 0x74 |
2498 | #define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_P 0x80 |
2499 | #define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_NP 0x81 |
2500 | #define ixD3F5_PCIE_RX_CREDITS_ALLOCATED_CPL 0x82 |
2501 | #define ixD3F5_PCIEP_ERROR_INJECT_PHYSICAL 0x83 |
2502 | #define ixD3F5_PCIEP_ERROR_INJECT_TRANSACTION 0x84 |
2503 | #define ixD3F5_PCIE_LC_CNTL 0xa0 |
2504 | #define ixD3F5_PCIE_LC_CNTL2 0xb1 |
2505 | #define ixD3F5_PCIE_LC_CNTL3 0xb5 |
2506 | #define ixD3F5_PCIE_LC_CNTL4 0xb6 |
2507 | #define ixD3F5_PCIE_LC_CNTL5 0xb7 |
2508 | #define ixD3F5_PCIE_LC_CNTL6 0xbb |
2509 | #define ixD3F5_PCIE_LC_BW_CHANGE_CNTL 0xb2 |
2510 | #define ixD3F5_PCIE_LC_TRAINING_CNTL 0xa1 |
2511 | #define ixD3F5_PCIE_LC_LINK_WIDTH_CNTL 0xa2 |
2512 | #define ixD3F5_PCIE_LC_N_FTS_CNTL 0xa3 |
2513 | #define ixD3F5_PCIE_LC_SPEED_CNTL 0xa4 |
2514 | #define ixD3F5_PCIE_LC_CDR_CNTL 0xb3 |
2515 | #define ixD3F5_PCIE_LC_LANE_CNTL 0xb4 |
2516 | #define ixD3F5_PCIE_LC_FORCE_COEFF 0xb8 |
2517 | #define ixD3F5_PCIE_LC_BEST_EQ_SETTINGS 0xb9 |
2518 | #define ixD3F5_PCIE_LC_FORCE_EQ_REQ_COEFF 0xba |
2519 | #define ixD3F5_PCIE_LC_STATE0 0xa5 |
2520 | #define ixD3F5_PCIE_LC_STATE1 0xa6 |
2521 | #define ixD3F5_PCIE_LC_STATE2 0xa7 |
2522 | #define ixD3F5_PCIE_LC_STATE3 0xa8 |
2523 | #define ixD3F5_PCIE_LC_STATE4 0xa9 |
2524 | #define ixD3F5_PCIE_LC_STATE5 0xaa |
2525 | #define ixD3F5_PCIEP_STRAP_LC 0xc0 |
2526 | #define ixD3F5_PCIEP_STRAP_MISC 0xc1 |
2527 | #define ixD3F5_PCIEP_BCH_ECC_CNTL 0xd0 |
2528 | #define ixD3F5_PCIEP_HPGI_PRIVATE 0xd2 |
2529 | #define ixD3F5_PCIEP_HPGI 0xda |
2530 | #define ixD3F5_VENDOR_ID 0xb000000 |
2531 | #define ixD3F5_DEVICE_ID 0xb000000 |
2532 | #define ixD3F5_COMMAND 0xb000001 |
2533 | #define ixD3F5_STATUS 0xb000001 |
2534 | #define ixD3F5_REVISION_ID 0xb000002 |
2535 | #define ixD3F5_PROG_INTERFACE 0xb000002 |
2536 | #define ixD3F5_SUB_CLASS 0xb000002 |
2537 | #define ixD3F5_BASE_CLASS 0xb000002 |
2538 | #define ixD3F5_CACHE_LINE 0xb000003 |
2539 | #define ixD3F5_LATENCY 0xb000003 |
2540 | #define 0xb000003 |
2541 | #define ixD3F5_BIST 0xb000003 |
2542 | #define ixD3F5_SUB_BUS_NUMBER_LATENCY 0xb000006 |
2543 | #define ixD3F5_IO_BASE_LIMIT 0xb000007 |
2544 | #define ixD3F5_SECONDARY_STATUS 0xb000007 |
2545 | #define ixD3F5_MEM_BASE_LIMIT 0xb000008 |
2546 | #define ixD3F5_PREF_BASE_LIMIT 0xb000009 |
2547 | #define ixD3F5_PREF_BASE_UPPER 0xb00000a |
2548 | #define ixD3F5_PREF_LIMIT_UPPER 0xb00000b |
2549 | #define ixD3F5_IO_BASE_LIMIT_HI 0xb00000c |
2550 | #define ixD3F5_IRQ_BRIDGE_CNTL 0xb00000f |
2551 | #define ixD3F5_CAP_PTR 0xb00000d |
2552 | #define ixD3F5_INTERRUPT_LINE 0xb00000f |
2553 | #define ixD3F5_INTERRUPT_PIN 0xb00000f |
2554 | #define ixD3F5_EXT_BRIDGE_CNTL 0xb000010 |
2555 | #define ixD3F5_PMI_CAP_LIST 0xb000014 |
2556 | #define ixD3F5_PMI_CAP 0xb000014 |
2557 | #define ixD3F5_PMI_STATUS_CNTL 0xb000015 |
2558 | #define ixD3F5_PCIE_CAP_LIST 0xb000016 |
2559 | #define ixD3F5_PCIE_CAP 0xb000016 |
2560 | #define ixD3F5_DEVICE_CAP 0xb000017 |
2561 | #define ixD3F5_DEVICE_CNTL 0xb000018 |
2562 | #define ixD3F5_DEVICE_STATUS 0xb000018 |
2563 | #define ixD3F5_LINK_CAP 0xb000019 |
2564 | #define ixD3F5_LINK_CNTL 0xb00001a |
2565 | #define ixD3F5_LINK_STATUS 0xb00001a |
2566 | #define ixD3F5_SLOT_CAP 0xb00001b |
2567 | #define ixD3F5_SLOT_CNTL 0xb00001c |
2568 | #define ixD3F5_SLOT_STATUS 0xb00001c |
2569 | #define ixD3F5_ROOT_CNTL 0xb00001d |
2570 | #define ixD3F5_ROOT_CAP 0xb00001d |
2571 | #define ixD3F5_ROOT_STATUS 0xb00001e |
2572 | #define ixD3F5_DEVICE_CAP2 0xb00001f |
2573 | #define ixD3F5_DEVICE_CNTL2 0xb000020 |
2574 | #define ixD3F5_DEVICE_STATUS2 0xb000020 |
2575 | #define ixD3F5_LINK_CAP2 0xb000021 |
2576 | #define ixD3F5_LINK_CNTL2 0xb000022 |
2577 | #define ixD3F5_LINK_STATUS2 0xb000022 |
2578 | #define ixD3F5_SLOT_CAP2 0xb000023 |
2579 | #define ixD3F5_SLOT_CNTL2 0xb000024 |
2580 | #define ixD3F5_SLOT_STATUS2 0xb000024 |
2581 | #define ixD3F5_MSI_CAP_LIST 0xb000028 |
2582 | #define ixD3F5_MSI_MSG_CNTL 0xb000028 |
2583 | #define ixD3F5_MSI_MSG_ADDR_LO 0xb000029 |
2584 | #define ixD3F5_MSI_MSG_ADDR_HI 0xb00002a |
2585 | #define ixD3F5_MSI_MSG_DATA_64 0xb00002b |
2586 | #define ixD3F5_MSI_MSG_DATA 0xb00002a |
2587 | #define ixD3F5_SSID_CAP_LIST 0xb000030 |
2588 | #define ixD3F5_SSID_CAP 0xb000031 |
2589 | #define ixD3F5_MSI_MAP_CAP_LIST 0xb000032 |
2590 | #define ixD3F5_MSI_MAP_CAP 0xb000032 |
2591 | #define ixD3F5_MSI_MAP_ADDR_LO 0xb000033 |
2592 | #define ixD3F5_MSI_MAP_ADDR_HI 0xb000034 |
2593 | #define ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xb000040 |
2594 | #define ixD3F5_PCIE_VENDOR_SPECIFIC_HDR 0xb000041 |
2595 | #define ixD3F5_PCIE_VENDOR_SPECIFIC1 0xb000042 |
2596 | #define ixD3F5_PCIE_VENDOR_SPECIFIC2 0xb000043 |
2597 | #define ixD3F5_PCIE_VC_ENH_CAP_LIST 0xb000044 |
2598 | #define ixD3F5_PCIE_PORT_VC_CAP_REG1 0xb000045 |
2599 | #define ixD3F5_PCIE_PORT_VC_CAP_REG2 0xb000046 |
2600 | #define ixD3F5_PCIE_PORT_VC_CNTL 0xb000047 |
2601 | #define ixD3F5_PCIE_PORT_VC_STATUS 0xb000047 |
2602 | #define ixD3F5_PCIE_VC0_RESOURCE_CAP 0xb000048 |
2603 | #define ixD3F5_PCIE_VC0_RESOURCE_CNTL 0xb000049 |
2604 | #define ixD3F5_PCIE_VC0_RESOURCE_STATUS 0xb00004a |
2605 | #define ixD3F5_PCIE_VC1_RESOURCE_CAP 0xb00004b |
2606 | #define ixD3F5_PCIE_VC1_RESOURCE_CNTL 0xb00004c |
2607 | #define ixD3F5_PCIE_VC1_RESOURCE_STATUS 0xb00004d |
2608 | #define ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xb000050 |
2609 | #define ixD3F5_PCIE_DEV_SERIAL_NUM_DW1 0xb000051 |
2610 | #define ixD3F5_PCIE_DEV_SERIAL_NUM_DW2 0xb000052 |
2611 | #define ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xb000054 |
2612 | #define ixD3F5_PCIE_UNCORR_ERR_STATUS 0xb000055 |
2613 | #define ixD3F5_PCIE_UNCORR_ERR_MASK 0xb000056 |
2614 | #define ixD3F5_PCIE_UNCORR_ERR_SEVERITY 0xb000057 |
2615 | #define ixD3F5_PCIE_CORR_ERR_STATUS 0xb000058 |
2616 | #define ixD3F5_PCIE_CORR_ERR_MASK 0xb000059 |
2617 | #define ixD3F5_PCIE_ADV_ERR_CAP_CNTL 0xb00005a |
2618 | #define ixD3F5_PCIE_HDR_LOG0 0xb00005b |
2619 | #define ixD3F5_PCIE_HDR_LOG1 0xb00005c |
2620 | #define ixD3F5_PCIE_HDR_LOG2 0xb00005d |
2621 | #define ixD3F5_PCIE_HDR_LOG3 0xb00005e |
2622 | #define ixD3F5_PCIE_ROOT_ERR_CMD 0xb00005f |
2623 | #define ixD3F5_PCIE_ROOT_ERR_STATUS 0xb000060 |
2624 | #define ixD3F5_PCIE_ERR_SRC_ID 0xb000061 |
2625 | #define ixD3F5_PCIE_TLP_PREFIX_LOG0 0xb000062 |
2626 | #define ixD3F5_PCIE_TLP_PREFIX_LOG1 0xb000063 |
2627 | #define ixD3F5_PCIE_TLP_PREFIX_LOG2 0xb000064 |
2628 | #define ixD3F5_PCIE_TLP_PREFIX_LOG3 0xb000065 |
2629 | #define ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST 0xb00009c |
2630 | #define ixD3F5_PCIE_LINK_CNTL3 0xb00009d |
2631 | #define ixD3F5_PCIE_LANE_ERROR_STATUS 0xb00009e |
2632 | #define ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL 0xb00009f |
2633 | #define ixD3F5_PCIE_LANE_1_EQUALIZATION_CNTL 0xb00009f |
2634 | #define ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL 0xb0000a0 |
2635 | #define ixD3F5_PCIE_LANE_3_EQUALIZATION_CNTL 0xb0000a0 |
2636 | #define ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL 0xb0000a1 |
2637 | #define ixD3F5_PCIE_LANE_5_EQUALIZATION_CNTL 0xb0000a1 |
2638 | #define ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL 0xb0000a2 |
2639 | #define ixD3F5_PCIE_LANE_7_EQUALIZATION_CNTL 0xb0000a2 |
2640 | #define ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL 0xb0000a3 |
2641 | #define ixD3F5_PCIE_LANE_9_EQUALIZATION_CNTL 0xb0000a3 |
2642 | #define ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL 0xb0000a4 |
2643 | #define ixD3F5_PCIE_LANE_11_EQUALIZATION_CNTL 0xb0000a4 |
2644 | #define ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL 0xb0000a5 |
2645 | #define ixD3F5_PCIE_LANE_13_EQUALIZATION_CNTL 0xb0000a5 |
2646 | #define ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL 0xb0000a6 |
2647 | #define ixD3F5_PCIE_LANE_15_EQUALIZATION_CNTL 0xb0000a6 |
2648 | #define ixD3F5_PCIE_ACS_ENH_CAP_LIST 0xb0000a8 |
2649 | #define ixD3F5_PCIE_ACS_CAP 0xb0000a9 |
2650 | #define ixD3F5_PCIE_ACS_CNTL 0xb0000a9 |
2651 | #define ixD3F5_PCIE_MC_ENH_CAP_LIST 0xb0000bc |
2652 | #define ixD3F5_PCIE_MC_CAP 0xb0000bd |
2653 | #define ixD3F5_PCIE_MC_CNTL 0xb0000bd |
2654 | #define ixD3F5_PCIE_MC_ADDR0 0xb0000be |
2655 | #define ixD3F5_PCIE_MC_ADDR1 0xb0000bf |
2656 | #define ixD3F5_PCIE_MC_RCV0 0xb0000c0 |
2657 | #define ixD3F5_PCIE_MC_RCV1 0xb0000c1 |
2658 | #define ixD3F5_PCIE_MC_BLOCK_ALL0 0xb0000c2 |
2659 | #define ixD3F5_PCIE_MC_BLOCK_ALL1 0xb0000c3 |
2660 | #define ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0 0xb0000c4 |
2661 | #define ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1 0xb0000c5 |
2662 | #define ixD3F5_PCIE_MC_OVERLAY_BAR0 0xb0000c6 |
2663 | #define ixD3F5_PCIE_MC_OVERLAY_BAR1 0xb0000c7 |
2664 | #define mmC_PCIE_INDEX 0x28 |
2665 | #define mmPCIE_WRAPPER0_C_PCIE_INDEX 0x28 |
2666 | #define mmPCIE_WRAPPER1_C_PCIE_INDEX 0x38 |
2667 | #define mmC_PCIE_DATA 0x29 |
2668 | #define mmPCIE_WRAPPER0_C_PCIE_DATA 0x29 |
2669 | #define mmPCIE_WRAPPER1_C_PCIE_DATA 0x39 |
2670 | #define mmRFE_SNOOP_RST 0x3c |
2671 | #define ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1 0x1500000 |
2672 | #define ixPSX80_WRP_BIF_STRAP_PI_CNTL 0x1500001 |
2673 | #define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE 0x1500002 |
2674 | #define ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE 0x1500003 |
2675 | #define ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE 0x1500004 |
2676 | #define ixPSX80_WRP_BIF_STRAP_TEST_DFT 0x1500005 |
2677 | #define ixPSX80_WRP_BIF_STRAP_ID 0x1500006 |
2678 | #define ixPSX80_WRP_BIF_STRAP_REV_ID 0x1500007 |
2679 | #define ixPSX80_WRP_BIF_STRAP_I2C_CNTL 0x1500008 |
2680 | #define ixPSX80_WRP_BIF_INT_CNTL 0x1500009 |
2681 | #define ixPSX80_WRP_BIF_STRAP_ACS 0x150000a |
2682 | #define ixPSX80_WRP_BIF_STRAP_PM 0x150000b |
2683 | #define ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2 0x150000c |
2684 | #define ixPSX80_WRP_BIF_SERIAL_NUM 0x1500045 |
2685 | #define ixPSX80_WRP_BIF_SSID 0x1500046 |
2686 | #define ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL 0x1500050 |
2687 | #define ixPSX80_WRP_PCIE_LINK_CONFIG 0x1500080 |
2688 | #define ixPSX80_WRP_PCIE_HOLD_TRAINING_A 0x1500800 |
2689 | #define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A 0x1500801 |
2690 | #define ixPSX80_WRP_BIF_STRAP_ASPM_A 0x1500802 |
2691 | #define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A 0x1500803 |
2692 | #define ixPSX80_WRP_BIF_STRAP_MISC_PORT_A 0x1500804 |
2693 | #define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A 0x1500805 |
2694 | #define ixPSX80_WRP_PCIE_PORT_IS_SB_A 0x1500813 |
2695 | #define ixPSX80_WRP_PCIE_HOLD_TRAINING_B 0x1500900 |
2696 | #define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B 0x1500901 |
2697 | #define ixPSX80_WRP_BIF_STRAP_ASPM_B 0x1500902 |
2698 | #define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B 0x1500903 |
2699 | #define ixPSX80_WRP_BIF_STRAP_MISC_PORT_B 0x1500904 |
2700 | #define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B 0x1500905 |
2701 | #define ixPSX80_WRP_PCIE_PORT_IS_SB_B 0x1500913 |
2702 | #define ixPSX80_WRP_PCIE_HOLD_TRAINING_C 0x1500a00 |
2703 | #define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C 0x1500a01 |
2704 | #define ixPSX80_WRP_BIF_STRAP_ASPM_C 0x1500a02 |
2705 | #define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C 0x1500a03 |
2706 | #define ixPSX80_WRP_BIF_STRAP_MISC_PORT_C 0x1500a04 |
2707 | #define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C 0x1500a05 |
2708 | #define ixPSX80_WRP_PCIE_PORT_IS_SB_C 0x1500a13 |
2709 | #define ixPSX80_WRP_PCIE_HOLD_TRAINING_D 0x1500b00 |
2710 | #define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D 0x1500b01 |
2711 | #define ixPSX80_WRP_BIF_STRAP_ASPM_D 0x1500b02 |
2712 | #define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D 0x1500b03 |
2713 | #define ixPSX80_WRP_BIF_STRAP_MISC_PORT_D 0x1500b04 |
2714 | #define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D 0x1500b05 |
2715 | #define ixPSX80_WRP_PCIE_PORT_IS_SB_D 0x1500b13 |
2716 | #define ixPSX80_WRP_PCIE_HOLD_TRAINING_E 0x1500c00 |
2717 | #define ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E 0x1500c01 |
2718 | #define ixPSX80_WRP_BIF_STRAP_ASPM_E 0x1500c02 |
2719 | #define ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E 0x1500c03 |
2720 | #define ixPSX80_WRP_BIF_STRAP_MISC_PORT_E 0x1500c04 |
2721 | #define ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E 0x1500c05 |
2722 | #define ixPSX80_WRP_PCIE_PORT_IS_SB_E 0x1500c13 |
2723 | #define ixPSX80_WRP_LNCNT_CONTROL 0x1508030 |
2724 | #define ixPSX80_WRP_CFG_LNC_WINDOW 0x1508031 |
2725 | #define ixPSX80_WRP_LNCNT_QUAN_THRD 0x1508032 |
2726 | #define ixPSX80_WRP_LNCNT_WEIGHT 0x1508033 |
2727 | #define ixPSX80_WRP_LNC_TOTAL_WACC 0x1508034 |
2728 | #define ixPSX80_WRP_LNC_BW_WACC 0x1508035 |
2729 | #define ixPSX80_WRP_LNC_CMN_WACC 0x1508036 |
2730 | #define ixPSX80_WRP_PCIE_EFUSE 0x150fff0 |
2731 | #define ixPSX80_WRP_PCIE_EFUSE2 0x150fff1 |
2732 | #define ixPSX80_WRP_PCIE_EFUSE3 0x150fff2 |
2733 | #define ixPSX80_WRP_PCIE_EFUSE4 0x150fff3 |
2734 | #define ixPSX80_WRP_PCIE_EFUSE5 0x150fff4 |
2735 | #define ixPSX80_WRP_PCIE_EFUSE6 0x150fff5 |
2736 | #define ixPSX80_WRP_PCIE_EFUSE7 0x150fff6 |
2737 | #define ixPSX80_WRP_PCIE_WRAP_SCRATCH1 0x1308001 |
2738 | #define ixPSX80_WRP_PCIE_WRAP_SCRATCH2 0x1308002 |
2739 | #define ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC 0x1308005 |
2740 | #define ixPSX80_WRP_PCIE_WRAP_DTM_MISC 0x1308006 |
2741 | #define ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1308007 |
2742 | #define ixPSX80_WRP_PCIE_WRAP_MISC 0x1308008 |
2743 | #define ixPSX80_WRP_PCIE_WRAP_PIF_MISC 0x1308009 |
2744 | #define ixPSX80_WRP_PCIE_RXDET_OVERRIDE 0x130800a |
2745 | #define ixPSX80_WRP_IMPCTL_CNTL_PIF0 0x1308070 |
2746 | #define ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL 0x1308090 |
2747 | #define ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL 0x1308096 |
2748 | #define ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL 0x1308097 |
2749 | #define ixPSX80_WRP_REG_ADAPT_pif0_CONTROL 0x1308098 |
2750 | #define ixPSX80_WRP_BIOSTIMER_CMD 0x13080f0 |
2751 | #define ixPSX80_WRP_BIOSTIMER_CNTL 0x13080f1 |
2752 | #define ixPSX80_WRP_BIOSTIMER_DEBUG 0x13080f2 |
2753 | #define ixPSX80_WRP_DTM_RX_BP_CNTL 0x130ffe0 |
2754 | #define ixPSX80_WRP_DTM_CNTL 0x130ffe1 |
2755 | #define ixPSX80_WRP_DTM_CNTL_LEGACY 0x130ffe2 |
2756 | #define ixPSX80_WRP_DTM_STI_LCLK_CTRL 0x130ffe3 |
2757 | #define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x 0x130ffe4 |
2758 | #define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt 0x130ffe5 |
2759 | #define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x 0x130ffe6 |
2760 | #define ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt 0x130ffe7 |
2761 | #define ixPSX80_WRP_DELAYLINE_COMMAND 0x130ffd0 |
2762 | #define ixPSX80_WRP_DELAYLINE_STATUS 0x130ffd1 |
2763 | #define ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1 0x1510000 |
2764 | #define ixPSX81_WRP_BIF_STRAP_PI_CNTL 0x1510001 |
2765 | #define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE 0x1510002 |
2766 | #define ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE 0x1510003 |
2767 | #define ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE 0x1510004 |
2768 | #define ixPSX81_WRP_BIF_STRAP_TEST_DFT 0x1510005 |
2769 | #define ixPSX81_WRP_BIF_STRAP_ID 0x1510006 |
2770 | #define ixPSX81_WRP_BIF_STRAP_REV_ID 0x1510007 |
2771 | #define ixPSX81_WRP_BIF_STRAP_I2C_CNTL 0x1510008 |
2772 | #define ixPSX81_WRP_BIF_INT_CNTL 0x1510009 |
2773 | #define ixPSX81_WRP_BIF_STRAP_ACS 0x151000a |
2774 | #define ixPSX81_WRP_BIF_STRAP_PM 0x151000b |
2775 | #define ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2 0x151000c |
2776 | #define ixPSX81_WRP_BIF_SERIAL_NUM 0x1510045 |
2777 | #define ixPSX81_WRP_BIF_SSID 0x1510046 |
2778 | #define ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL 0x1510050 |
2779 | #define ixPSX81_WRP_PCIE_LINK_CONFIG 0x1510080 |
2780 | #define ixPSX81_WRP_PCIE_HOLD_TRAINING_A 0x1510800 |
2781 | #define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A 0x1510801 |
2782 | #define ixPSX81_WRP_BIF_STRAP_ASPM_A 0x1510802 |
2783 | #define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A 0x1510803 |
2784 | #define ixPSX81_WRP_BIF_STRAP_MISC_PORT_A 0x1510804 |
2785 | #define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A 0x1510805 |
2786 | #define ixPSX81_WRP_PCIE_PORT_IS_SB_A 0x1510813 |
2787 | #define ixPSX81_WRP_PCIE_HOLD_TRAINING_B 0x1510900 |
2788 | #define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B 0x1510901 |
2789 | #define ixPSX81_WRP_BIF_STRAP_ASPM_B 0x1510902 |
2790 | #define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B 0x1510903 |
2791 | #define ixPSX81_WRP_BIF_STRAP_MISC_PORT_B 0x1510904 |
2792 | #define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B 0x1510905 |
2793 | #define ixPSX81_WRP_PCIE_PORT_IS_SB_B 0x1510913 |
2794 | #define ixPSX81_WRP_PCIE_HOLD_TRAINING_C 0x1510a00 |
2795 | #define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C 0x1510a01 |
2796 | #define ixPSX81_WRP_BIF_STRAP_ASPM_C 0x1510a02 |
2797 | #define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C 0x1510a03 |
2798 | #define ixPSX81_WRP_BIF_STRAP_MISC_PORT_C 0x1510a04 |
2799 | #define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C 0x1510a05 |
2800 | #define ixPSX81_WRP_PCIE_PORT_IS_SB_C 0x1510a13 |
2801 | #define ixPSX81_WRP_PCIE_HOLD_TRAINING_D 0x1510b00 |
2802 | #define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D 0x1510b01 |
2803 | #define ixPSX81_WRP_BIF_STRAP_ASPM_D 0x1510b02 |
2804 | #define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D 0x1510b03 |
2805 | #define ixPSX81_WRP_BIF_STRAP_MISC_PORT_D 0x1510b04 |
2806 | #define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D 0x1510b05 |
2807 | #define ixPSX81_WRP_PCIE_PORT_IS_SB_D 0x1510b13 |
2808 | #define ixPSX81_WRP_PCIE_HOLD_TRAINING_E 0x1510c00 |
2809 | #define ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E 0x1510c01 |
2810 | #define ixPSX81_WRP_BIF_STRAP_ASPM_E 0x1510c02 |
2811 | #define ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E 0x1510c03 |
2812 | #define ixPSX81_WRP_BIF_STRAP_MISC_PORT_E 0x1510c04 |
2813 | #define ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E 0x1510c05 |
2814 | #define ixPSX81_WRP_PCIE_PORT_IS_SB_E 0x1510c13 |
2815 | #define ixPSX81_WRP_LNCNT_CONTROL 0x1518030 |
2816 | #define ixPSX81_WRP_CFG_LNC_WINDOW 0x1518031 |
2817 | #define ixPSX81_WRP_LNCNT_QUAN_THRD 0x1518032 |
2818 | #define ixPSX81_WRP_LNCNT_WEIGHT 0x1518033 |
2819 | #define ixPSX81_WRP_LNC_TOTAL_WACC 0x1518034 |
2820 | #define ixPSX81_WRP_LNC_BW_WACC 0x1518035 |
2821 | #define ixPSX81_WRP_LNC_CMN_WACC 0x1518036 |
2822 | #define ixPSX81_WRP_PCIE_EFUSE 0x151fff0 |
2823 | #define ixPSX81_WRP_PCIE_EFUSE2 0x151fff1 |
2824 | #define ixPSX81_WRP_PCIE_EFUSE3 0x151fff2 |
2825 | #define ixPSX81_WRP_PCIE_EFUSE4 0x151fff3 |
2826 | #define ixPSX81_WRP_PCIE_EFUSE5 0x151fff4 |
2827 | #define ixPSX81_WRP_PCIE_EFUSE6 0x151fff5 |
2828 | #define ixPSX81_WRP_PCIE_EFUSE7 0x151fff6 |
2829 | #define ixPSX81_WRP_PCIE_WRAP_SCRATCH1 0x1318001 |
2830 | #define ixPSX81_WRP_PCIE_WRAP_SCRATCH2 0x1318002 |
2831 | #define ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC 0x1318005 |
2832 | #define ixPSX81_WRP_PCIE_WRAP_DTM_MISC 0x1318006 |
2833 | #define ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN 0x1318007 |
2834 | #define ixPSX81_WRP_PCIE_WRAP_MISC 0x1318008 |
2835 | #define ixPSX81_WRP_PCIE_WRAP_PIF_MISC 0x1318009 |
2836 | #define ixPSX81_WRP_PCIE_RXDET_OVERRIDE 0x131800a |
2837 | #define ixPSX81_WRP_IMPCTL_CNTL_PIF0 0x1318070 |
2838 | #define ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL 0x1318090 |
2839 | #define ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL 0x1318096 |
2840 | #define ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL 0x1318097 |
2841 | #define ixPSX81_WRP_REG_ADAPT_pif0_CONTROL 0x1318098 |
2842 | #define ixPSX81_WRP_BIOSTIMER_CMD 0x13180f0 |
2843 | #define ixPSX81_WRP_BIOSTIMER_CNTL 0x13180f1 |
2844 | #define ixPSX81_WRP_BIOSTIMER_DEBUG 0x13180f2 |
2845 | #define ixPSX81_WRP_DTM_RX_BP_CNTL 0x131ffe0 |
2846 | #define ixPSX81_WRP_DTM_CNTL 0x131ffe1 |
2847 | #define ixPSX81_WRP_DTM_CNTL_LEGACY 0x131ffe2 |
2848 | #define ixPSX81_WRP_DTM_STI_LCLK_CTRL 0x131ffe3 |
2849 | #define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x 0x131ffe4 |
2850 | #define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt 0x131ffe5 |
2851 | #define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x 0x131ffe6 |
2852 | #define ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt 0x131ffe7 |
2853 | #define ixPSX81_WRP_DELAYLINE_COMMAND 0x131ffd0 |
2854 | #define ixPSX81_WRP_DELAYLINE_STATUS 0x131ffd1 |
2855 | #define ixRFE_WARMRST_CNTL 0x1085164 |
2856 | #define ixRFE_SOFTRST_CNTL 0x1080001 |
2857 | #define ixRFE_IMPRST_CNTL 0x1085160 |
2858 | #define ixRFE_CLIENT_SOFTRST_TRIGGER 0x1080004 |
2859 | #define ixRFE_MASTER_SOFTRST_TRIGGER 0x1080005 |
2860 | #define ixRFE_PWDN_COMMAND 0x1080010 |
2861 | #define ixRFE_PWDN_STATUS 0x1080011 |
2862 | #define ixRFE_MST_PCIEW0_CMDSTATUS 0x1080020 |
2863 | #define ixRFE_MST_PCIEW1_CMDSTATUS 0x1080021 |
2864 | #define ixRFE_MST_RWREG_RFEWRC_CMDSTATUS 0x1080022 |
2865 | #define ixRFE_MST_TMOUT_STATUS 0x108003f |
2866 | #define ixRFE_IMPARBH_STATUS 0x1085140 |
2867 | #define ixRFE_IMPARBH_CONTROL 0x1080083 |
2868 | #define ixPSX80_BIF_PCIE_RESERVED 0x1400000 |
2869 | #define ixPSX80_BIF_PCIE_SCRATCH 0x1400001 |
2870 | #define ixPSX80_BIF_PCIE_HW_DEBUG 0x1400002 |
2871 | #define ixPSX80_BIF_PCIE_RX_NUM_NAK 0x140000e |
2872 | #define ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED 0x140000f |
2873 | #define ixPSX80_BIF_PCIE_CNTL 0x1400010 |
2874 | #define ixPSX80_BIF_PCIE_CONFIG_CNTL 0x1400011 |
2875 | #define ixPSX80_BIF_PCIE_DEBUG_CNTL 0x1400012 |
2876 | #define ixPSX80_BIF_PCIE_CNTL2 0x140001c |
2877 | #define ixPSX80_BIF_PCIE_RX_CNTL2 0x140001d |
2878 | #define ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL 0x140001e |
2879 | #define ixPSX80_BIF_PCIE_CI_CNTL 0x1400020 |
2880 | #define ixPSX80_BIF_PCIE_BUS_CNTL 0x1400021 |
2881 | #define ixPSX80_BIF_PCIE_LC_STATE6 0x1400022 |
2882 | #define ixPSX80_BIF_PCIE_LC_STATE7 0x1400023 |
2883 | #define ixPSX80_BIF_PCIE_LC_STATE8 0x1400024 |
2884 | #define ixPSX80_BIF_PCIE_LC_STATE9 0x1400025 |
2885 | #define ixPSX80_BIF_PCIE_LC_STATE10 0x1400026 |
2886 | #define ixPSX80_BIF_PCIE_LC_STATE11 0x1400027 |
2887 | #define ixPSX80_BIF_PCIE_LC_STATUS1 0x1400028 |
2888 | #define ixPSX80_BIF_PCIE_LC_STATUS2 0x1400029 |
2889 | #define ixPSX80_BIF_PCIE_WPR_CNTL 0x1400030 |
2890 | #define ixPSX80_BIF_PCIE_RX_LAST_TLP0 0x1400031 |
2891 | #define ixPSX80_BIF_PCIE_RX_LAST_TLP1 0x1400032 |
2892 | #define ixPSX80_BIF_PCIE_RX_LAST_TLP2 0x1400033 |
2893 | #define ixPSX80_BIF_PCIE_RX_LAST_TLP3 0x1400034 |
2894 | #define ixPSX80_BIF_PCIE_TX_LAST_TLP0 0x1400035 |
2895 | #define ixPSX80_BIF_PCIE_TX_LAST_TLP1 0x1400036 |
2896 | #define ixPSX80_BIF_PCIE_TX_LAST_TLP2 0x1400037 |
2897 | #define ixPSX80_BIF_PCIE_TX_LAST_TLP3 0x1400038 |
2898 | #define ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND 0x140003a |
2899 | #define ixPSX80_BIF_PCIE_I2C_REG_DATA 0x140003b |
2900 | #define ixPSX80_BIF_PCIE_CFG_CNTL 0x140003c |
2901 | #define ixPSX80_BIF_PCIE_LC_PM_CNTL 0x140003d |
2902 | #define ixPSX80_BIF_PCIE_P_CNTL 0x1400040 |
2903 | #define ixPSX80_BIF_PCIE_P_BUF_STATUS 0x1400041 |
2904 | #define ixPSX80_BIF_PCIE_P_DECODER_STATUS 0x1400042 |
2905 | #define ixPSX80_BIF_PCIE_P_MISC_STATUS 0x1400043 |
2906 | #define ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET 0x1400050 |
2907 | #define ixPSX80_BIF_PCIE_PERF_COUNT_CNTL 0x1400080 |
2908 | #define ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK 0x1400081 |
2909 | #define ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK 0x1400082 |
2910 | #define ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK 0x1400083 |
2911 | #define ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK 0x1400084 |
2912 | #define ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK 0x1400085 |
2913 | #define ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK 0x1400086 |
2914 | #define ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK 0x1400087 |
2915 | #define ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK 0x1400088 |
2916 | #define ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK 0x1400089 |
2917 | #define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK 0x140008a |
2918 | #define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK 0x140008b |
2919 | #define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK 0x140008c |
2920 | #define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK 0x140008d |
2921 | #define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK 0x140008e |
2922 | #define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK 0x140008f |
2923 | #define ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK 0x1400090 |
2924 | #define ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1400091 |
2925 | #define ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1400092 |
2926 | #define ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1400093 |
2927 | #define ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1400094 |
2928 | #define ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2 0x1400095 |
2929 | #define ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2 0x1400096 |
2930 | #define ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2 0x1400097 |
2931 | #define ixPSX80_BIF_PCIE_STRAP_F0 0x14000b0 |
2932 | #define ixPSX80_BIF_PCIE_STRAP_MISC 0x14000c0 |
2933 | #define ixPSX80_BIF_PCIE_STRAP_MISC2 0x14000c1 |
2934 | #define ixPSX80_BIF_PCIE_STRAP_PI 0x14000c2 |
2935 | #define ixPSX80_BIF_PCIE_STRAP_I2C_BD 0x14000c4 |
2936 | #define ixPSX80_BIF_PCIE_PRBS_CLR 0x14000c8 |
2937 | #define ixPSX80_BIF_PCIE_PRBS_STATUS1 0x14000c9 |
2938 | #define ixPSX80_BIF_PCIE_PRBS_STATUS2 0x14000ca |
2939 | #define ixPSX80_BIF_PCIE_PRBS_FREERUN 0x14000cb |
2940 | #define ixPSX80_BIF_PCIE_PRBS_MISC 0x14000cc |
2941 | #define ixPSX80_BIF_PCIE_PRBS_USER_PATTERN 0x14000cd |
2942 | #define ixPSX80_BIF_PCIE_PRBS_LO_BITCNT 0x14000ce |
2943 | #define ixPSX80_BIF_PCIE_PRBS_HI_BITCNT 0x14000cf |
2944 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_0 0x14000d0 |
2945 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_1 0x14000d1 |
2946 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_2 0x14000d2 |
2947 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_3 0x14000d3 |
2948 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_4 0x14000d4 |
2949 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_5 0x14000d5 |
2950 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_6 0x14000d6 |
2951 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_7 0x14000d7 |
2952 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_8 0x14000d8 |
2953 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_9 0x14000d9 |
2954 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_10 0x14000da |
2955 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_11 0x14000db |
2956 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_12 0x14000dc |
2957 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_13 0x14000dd |
2958 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_14 0x14000de |
2959 | #define ixPSX80_BIF_PCIE_PRBS_ERRCNT_15 0x14000df |
2960 | #define ixPSX80_BIF_SWRST_COMMAND_STATUS 0x1400100 |
2961 | #define ixPSX80_BIF_SWRST_GENERAL_CONTROL 0x1400101 |
2962 | #define ixPSX80_BIF_SWRST_COMMAND_0 0x1400102 |
2963 | #define ixPSX80_BIF_SWRST_COMMAND_1 0x1400103 |
2964 | #define ixPSX80_BIF_SWRST_CONTROL_0 0x1400104 |
2965 | #define ixPSX80_BIF_SWRST_CONTROL_1 0x1400105 |
2966 | #define ixPSX80_BIF_SWRST_CONTROL_2 0x1400106 |
2967 | #define ixPSX80_BIF_SWRST_CONTROL_3 0x1400107 |
2968 | #define ixPSX80_BIF_SWRST_CONTROL_4 0x1400108 |
2969 | #define ixPSX80_BIF_SWRST_CONTROL_5 0x1400109 |
2970 | #define ixPSX80_BIF_SWRST_CONTROL_6 0x140010a |
2971 | #define ixPSX80_BIF_CPM_CONTROL 0x1400118 |
2972 | #define ixPSX80_BIF_LM_CONTROL 0x1400120 |
2973 | #define ixPSX80_BIF_LM_PCIETXMUX0 0x1400121 |
2974 | #define ixPSX80_BIF_LM_PCIETXMUX1 0x1400122 |
2975 | #define ixPSX80_BIF_LM_PCIETXMUX2 0x1400123 |
2976 | #define ixPSX80_BIF_LM_PCIETXMUX3 0x1400124 |
2977 | #define ixPSX80_BIF_LM_PCIERXMUX0 0x1400125 |
2978 | #define ixPSX80_BIF_LM_PCIERXMUX1 0x1400126 |
2979 | #define ixPSX80_BIF_LM_PCIERXMUX2 0x1400127 |
2980 | #define ixPSX80_BIF_LM_PCIERXMUX3 0x1400128 |
2981 | #define ixPSX80_BIF_LM_LANEENABLE 0x1400129 |
2982 | #define ixPSX80_BIF_LM_PRBSCONTROL 0x140012a |
2983 | #define ixPSX80_BIF_LM_POWERCONTROL 0x140012b |
2984 | #define ixPSX80_BIF_LM_POWERCONTROL1 0x140012c |
2985 | #define ixPSX80_BIF_LM_POWERCONTROL2 0x140012d |
2986 | #define ixPSX80_BIF_LM_POWERCONTROL3 0x140012e |
2987 | #define ixPSX80_BIF_LM_POWERCONTROL4 0x140012f |
2988 | #define ixPSX81_BIF_PCIE_RESERVED 0x1410000 |
2989 | #define ixPSX81_BIF_PCIE_SCRATCH 0x1410001 |
2990 | #define ixPSX81_BIF_PCIE_HW_DEBUG 0x1410002 |
2991 | #define ixPSX81_BIF_PCIE_RX_NUM_NAK 0x141000e |
2992 | #define ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED 0x141000f |
2993 | #define ixPSX81_BIF_PCIE_CNTL 0x1410010 |
2994 | #define ixPSX81_BIF_PCIE_CONFIG_CNTL 0x1410011 |
2995 | #define ixPSX81_BIF_PCIE_DEBUG_CNTL 0x1410012 |
2996 | #define ixPSX81_BIF_PCIE_CNTL2 0x141001c |
2997 | #define ixPSX81_BIF_PCIE_RX_CNTL2 0x141001d |
2998 | #define ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL 0x141001e |
2999 | #define ixPSX81_BIF_PCIE_CI_CNTL 0x1410020 |
3000 | #define ixPSX81_BIF_PCIE_BUS_CNTL 0x1410021 |
3001 | #define ixPSX81_BIF_PCIE_LC_STATE6 0x1410022 |
3002 | #define ixPSX81_BIF_PCIE_LC_STATE7 0x1410023 |
3003 | #define ixPSX81_BIF_PCIE_LC_STATE8 0x1410024 |
3004 | #define ixPSX81_BIF_PCIE_LC_STATE9 0x1410025 |
3005 | #define ixPSX81_BIF_PCIE_LC_STATE10 0x1410026 |
3006 | #define ixPSX81_BIF_PCIE_LC_STATE11 0x1410027 |
3007 | #define ixPSX81_BIF_PCIE_LC_STATUS1 0x1410028 |
3008 | #define ixPSX81_BIF_PCIE_LC_STATUS2 0x1410029 |
3009 | #define ixPSX81_BIF_PCIE_WPR_CNTL 0x1410030 |
3010 | #define ixPSX81_BIF_PCIE_RX_LAST_TLP0 0x1410031 |
3011 | #define ixPSX81_BIF_PCIE_RX_LAST_TLP1 0x1410032 |
3012 | #define ixPSX81_BIF_PCIE_RX_LAST_TLP2 0x1410033 |
3013 | #define ixPSX81_BIF_PCIE_RX_LAST_TLP3 0x1410034 |
3014 | #define ixPSX81_BIF_PCIE_TX_LAST_TLP0 0x1410035 |
3015 | #define ixPSX81_BIF_PCIE_TX_LAST_TLP1 0x1410036 |
3016 | #define ixPSX81_BIF_PCIE_TX_LAST_TLP2 0x1410037 |
3017 | #define ixPSX81_BIF_PCIE_TX_LAST_TLP3 0x1410038 |
3018 | #define ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND 0x141003a |
3019 | #define ixPSX81_BIF_PCIE_I2C_REG_DATA 0x141003b |
3020 | #define ixPSX81_BIF_PCIE_CFG_CNTL 0x141003c |
3021 | #define ixPSX81_BIF_PCIE_LC_PM_CNTL 0x141003d |
3022 | #define ixPSX81_BIF_PCIE_P_CNTL 0x1410040 |
3023 | #define ixPSX81_BIF_PCIE_P_BUF_STATUS 0x1410041 |
3024 | #define ixPSX81_BIF_PCIE_P_DECODER_STATUS 0x1410042 |
3025 | #define ixPSX81_BIF_PCIE_P_MISC_STATUS 0x1410043 |
3026 | #define ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET 0x1410050 |
3027 | #define ixPSX81_BIF_PCIE_PERF_COUNT_CNTL 0x1410080 |
3028 | #define ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK 0x1410081 |
3029 | #define ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK 0x1410082 |
3030 | #define ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK 0x1410083 |
3031 | #define ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK 0x1410084 |
3032 | #define ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK 0x1410085 |
3033 | #define ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK 0x1410086 |
3034 | #define ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK 0x1410087 |
3035 | #define ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK 0x1410088 |
3036 | #define ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK 0x1410089 |
3037 | #define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK 0x141008a |
3038 | #define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK 0x141008b |
3039 | #define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK 0x141008c |
3040 | #define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK 0x141008d |
3041 | #define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK 0x141008e |
3042 | #define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK 0x141008f |
3043 | #define ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK 0x1410090 |
3044 | #define ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK 0x1410091 |
3045 | #define ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK 0x1410092 |
3046 | #define ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1410093 |
3047 | #define ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL 0x1410094 |
3048 | #define ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2 0x1410095 |
3049 | #define ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2 0x1410096 |
3050 | #define ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2 0x1410097 |
3051 | #define ixPSX81_BIF_PCIE_STRAP_F0 0x14100b0 |
3052 | #define ixPSX81_BIF_PCIE_STRAP_MISC 0x14100c0 |
3053 | #define ixPSX81_BIF_PCIE_STRAP_MISC2 0x14100c1 |
3054 | #define ixPSX81_BIF_PCIE_STRAP_PI 0x14100c2 |
3055 | #define ixPSX81_BIF_PCIE_STRAP_I2C_BD 0x14100c4 |
3056 | #define ixPSX81_BIF_PCIE_PRBS_CLR 0x14100c8 |
3057 | #define ixPSX81_BIF_PCIE_PRBS_STATUS1 0x14100c9 |
3058 | #define ixPSX81_BIF_PCIE_PRBS_STATUS2 0x14100ca |
3059 | #define ixPSX81_BIF_PCIE_PRBS_FREERUN 0x14100cb |
3060 | #define ixPSX81_BIF_PCIE_PRBS_MISC 0x14100cc |
3061 | #define ixPSX81_BIF_PCIE_PRBS_USER_PATTERN 0x14100cd |
3062 | #define ixPSX81_BIF_PCIE_PRBS_LO_BITCNT 0x14100ce |
3063 | #define ixPSX81_BIF_PCIE_PRBS_HI_BITCNT 0x14100cf |
3064 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_0 0x14100d0 |
3065 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_1 0x14100d1 |
3066 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_2 0x14100d2 |
3067 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_3 0x14100d3 |
3068 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_4 0x14100d4 |
3069 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_5 0x14100d5 |
3070 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_6 0x14100d6 |
3071 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_7 0x14100d7 |
3072 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_8 0x14100d8 |
3073 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_9 0x14100d9 |
3074 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_10 0x14100da |
3075 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_11 0x14100db |
3076 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_12 0x14100dc |
3077 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_13 0x14100dd |
3078 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_14 0x14100de |
3079 | #define ixPSX81_BIF_PCIE_PRBS_ERRCNT_15 0x14100df |
3080 | #define ixPSX81_BIF_SWRST_COMMAND_STATUS 0x1410100 |
3081 | #define ixPSX81_BIF_SWRST_GENERAL_CONTROL 0x1410101 |
3082 | #define ixPSX81_BIF_SWRST_COMMAND_0 0x1410102 |
3083 | #define ixPSX81_BIF_SWRST_COMMAND_1 0x1410103 |
3084 | #define ixPSX81_BIF_SWRST_CONTROL_0 0x1410104 |
3085 | #define ixPSX81_BIF_SWRST_CONTROL_1 0x1410105 |
3086 | #define ixPSX81_BIF_SWRST_CONTROL_2 0x1410106 |
3087 | #define ixPSX81_BIF_SWRST_CONTROL_3 0x1410107 |
3088 | #define ixPSX81_BIF_SWRST_CONTROL_4 0x1410108 |
3089 | #define ixPSX81_BIF_SWRST_CONTROL_5 0x1410109 |
3090 | #define ixPSX81_BIF_SWRST_CONTROL_6 0x141010a |
3091 | #define ixPSX81_BIF_CPM_CONTROL 0x1410118 |
3092 | #define ixPSX81_BIF_LM_CONTROL 0x1410120 |
3093 | #define ixPSX81_BIF_LM_PCIETXMUX0 0x1410121 |
3094 | #define ixPSX81_BIF_LM_PCIETXMUX1 0x1410122 |
3095 | #define ixPSX81_BIF_LM_PCIETXMUX2 0x1410123 |
3096 | #define ixPSX81_BIF_LM_PCIETXMUX3 0x1410124 |
3097 | #define ixPSX81_BIF_LM_PCIERXMUX0 0x1410125 |
3098 | #define ixPSX81_BIF_LM_PCIERXMUX1 0x1410126 |
3099 | #define ixPSX81_BIF_LM_PCIERXMUX2 0x1410127 |
3100 | #define ixPSX81_BIF_LM_PCIERXMUX3 0x1410128 |
3101 | #define ixPSX81_BIF_LM_LANEENABLE 0x1410129 |
3102 | #define ixPSX81_BIF_LM_PRBSCONTROL 0x141012a |
3103 | #define ixPSX81_BIF_LM_POWERCONTROL 0x141012b |
3104 | #define ixPSX81_BIF_LM_POWERCONTROL1 0x141012c |
3105 | #define ixPSX81_BIF_LM_POWERCONTROL2 0x141012d |
3106 | #define ixPSX81_BIF_LM_POWERCONTROL3 0x141012e |
3107 | #define ixPSX81_BIF_LM_POWERCONTROL4 0x141012f |
3108 | #define ixPSX80_PHY0_COM_COMMON_FUSE1 0x1206200 |
3109 | #define ixPSX80_PHY0_COM_COMMON_FUSE2 0x1206201 |
3110 | #define ixPSX80_PHY0_COM_COMMON_FUSE3 0x1206202 |
3111 | #define ixPSX80_PHY0_COM_COMMON_ELECIDLE 0x1206204 |
3112 | #define ixPSX80_PHY0_COM_COMMON_DFX 0x1206205 |
3113 | #define ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM 0x1206206 |
3114 | #define ixPSX80_PHY0_COM_COMMON_SELDEEMPH35 0x1206207 |
3115 | #define ixPSX80_PHY0_COM_COMMON_SELDEEMPH60 0x1206208 |
3116 | #define ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT 0x1206209 |
3117 | #define ixPSX80_PHY0_COM_COMMON_ADAPTCTL1 0x120620a |
3118 | #define ixPSX80_PHY0_COM_COMMON_ADAPTCTL2 0x120620b |
3119 | #define ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL 0x120620c |
3120 | #define ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1 0x120620d |
3121 | #define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL 0x120620e |
3122 | #define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1 0x120620f |
3123 | #define ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1 0x1206210 |
3124 | #define ixPSX80_PHY0_COM_COMMON_LNCNTRL 0x1206211 |
3125 | #define ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG 0x1206212 |
3126 | #define ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG 0x1206213 |
3127 | #define ixPSX80_PHY0_COM_COMMON_CDR_PHCTL 0x1206214 |
3128 | #define ixPSX80_PHY0_COM_COMMON_CDR_FRCTL 0x1206215 |
3129 | #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST 0x120fe00 |
3130 | #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0 0x1200000 |
3131 | #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1 0x1200100 |
3132 | #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2 0x1200200 |
3133 | #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3 0x1200300 |
3134 | #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4 0x1200400 |
3135 | #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5 0x1200500 |
3136 | #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6 0x1200600 |
3137 | #define ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7 0x1200700 |
3138 | #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST 0x120fe01 |
3139 | #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0 0x1200001 |
3140 | #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1 0x1200101 |
3141 | #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2 0x1200201 |
3142 | #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3 0x1200301 |
3143 | #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4 0x1200401 |
3144 | #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5 0x1200501 |
3145 | #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6 0x1200601 |
3146 | #define ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7 0x1200701 |
3147 | #define ixPSX80_PHY0_RX_RX_CTL_BROADCAST 0x120fe02 |
3148 | #define ixPSX80_PHY0_RX_RX_CTL_LANE0 0x1200002 |
3149 | #define ixPSX80_PHY0_RX_RX_CTL_LANE1 0x1200102 |
3150 | #define ixPSX80_PHY0_RX_RX_CTL_LANE2 0x1200202 |
3151 | #define ixPSX80_PHY0_RX_RX_CTL_LANE3 0x1200302 |
3152 | #define ixPSX80_PHY0_RX_RX_CTL_LANE4 0x1200402 |
3153 | #define ixPSX80_PHY0_RX_RX_CTL_LANE5 0x1200502 |
3154 | #define ixPSX80_PHY0_RX_RX_CTL_LANE6 0x1200602 |
3155 | #define ixPSX80_PHY0_RX_RX_CTL_LANE7 0x1200702 |
3156 | #define ixPSX80_PHY0_RX_DLL_CTL_BROADCAST 0x120fe03 |
3157 | #define ixPSX80_PHY0_RX_DLL_CTL_LANE0 0x1200003 |
3158 | #define ixPSX80_PHY0_RX_DLL_CTL_LANE1 0x1200103 |
3159 | #define ixPSX80_PHY0_RX_DLL_CTL_LANE2 0x1200203 |
3160 | #define ixPSX80_PHY0_RX_DLL_CTL_LANE3 0x1200303 |
3161 | #define ixPSX80_PHY0_RX_DLL_CTL_LANE4 0x1200403 |
3162 | #define ixPSX80_PHY0_RX_DLL_CTL_LANE5 0x1200503 |
3163 | #define ixPSX80_PHY0_RX_DLL_CTL_LANE6 0x1200603 |
3164 | #define ixPSX80_PHY0_RX_DLL_CTL_LANE7 0x1200703 |
3165 | #define ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST 0x120fe04 |
3166 | #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE0 0x1200004 |
3167 | #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE1 0x1200104 |
3168 | #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE2 0x1200204 |
3169 | #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE3 0x1200304 |
3170 | #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE4 0x1200404 |
3171 | #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE5 0x1200504 |
3172 | #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE6 0x1200604 |
3173 | #define ixPSX80_PHY0_RX_RXTEST_REGS_LANE7 0x1200704 |
3174 | #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST 0x120fe05 |
3175 | #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0 0x1200005 |
3176 | #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1 0x1200105 |
3177 | #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2 0x1200205 |
3178 | #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3 0x1200305 |
3179 | #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4 0x1200405 |
3180 | #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5 0x1200505 |
3181 | #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6 0x1200605 |
3182 | #define ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7 0x1200705 |
3183 | #define ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST 0x120fe0a |
3184 | #define ixPSX80_PHY0_RX_ADAPTCTL_LANE0 0x120000a |
3185 | #define ixPSX80_PHY0_RX_ADAPTCTL_LANE1 0x120010a |
3186 | #define ixPSX80_PHY0_RX_ADAPTCTL_LANE2 0x120020a |
3187 | #define ixPSX80_PHY0_RX_ADAPTCTL_LANE3 0x120030a |
3188 | #define ixPSX80_PHY0_RX_ADAPTCTL_LANE4 0x120040a |
3189 | #define ixPSX80_PHY0_RX_ADAPTCTL_LANE5 0x120050a |
3190 | #define ixPSX80_PHY0_RX_ADAPTCTL_LANE6 0x120060a |
3191 | #define ixPSX80_PHY0_RX_ADAPTCTL_LANE7 0x120070a |
3192 | #define ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST 0x120fe0b |
3193 | #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE0 0x120000b |
3194 | #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE1 0x120010b |
3195 | #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE2 0x120020b |
3196 | #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE3 0x120030b |
3197 | #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE4 0x120040b |
3198 | #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE5 0x120050b |
3199 | #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE6 0x120060b |
3200 | #define ixPSX80_PHY0_RX_FOMCALCCTL_LANE7 0x120070b |
3201 | #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST 0x120fe0c |
3202 | #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0 0x120000c |
3203 | #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1 0x120010c |
3204 | #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2 0x120020c |
3205 | #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3 0x120030c |
3206 | #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4 0x120040c |
3207 | #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5 0x120050c |
3208 | #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6 0x120060c |
3209 | #define ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7 0x120070c |
3210 | #define ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST 0x120fe0d |
3211 | #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0 0x120000d |
3212 | #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1 0x120010d |
3213 | #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2 0x120020d |
3214 | #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3 0x120030d |
3215 | #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4 0x120040d |
3216 | #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5 0x120050d |
3217 | #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6 0x120060d |
3218 | #define ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7 0x120070d |
3219 | #define ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST 0x120fe0e |
3220 | #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE0 0x120000e |
3221 | #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE1 0x120010e |
3222 | #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE2 0x120020e |
3223 | #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE3 0x120030e |
3224 | #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE4 0x120040e |
3225 | #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE5 0x120050e |
3226 | #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE6 0x120060e |
3227 | #define ixPSX80_PHY0_RX_ADAPTDBG1_LANE7 0x120070e |
3228 | #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST 0x120ff00 |
3229 | #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0 0x1202000 |
3230 | #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1 0x1202100 |
3231 | #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2 0x1202200 |
3232 | #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3 0x1202300 |
3233 | #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4 0x1202400 |
3234 | #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5 0x1202500 |
3235 | #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6 0x1202600 |
3236 | #define ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7 0x1202700 |
3237 | #define ixPSX80_PHY0_TX_DFX_BROADCAST 0x120ff01 |
3238 | #define ixPSX80_PHY0_TX_DFX_LANE0 0x1202001 |
3239 | #define ixPSX80_PHY0_TX_DFX_LANE1 0x1202101 |
3240 | #define ixPSX80_PHY0_TX_DFX_LANE2 0x1202201 |
3241 | #define ixPSX80_PHY0_TX_DFX_LANE3 0x1202301 |
3242 | #define ixPSX80_PHY0_TX_DFX_LANE4 0x1202401 |
3243 | #define ixPSX80_PHY0_TX_DFX_LANE5 0x1202501 |
3244 | #define ixPSX80_PHY0_TX_DFX_LANE6 0x1202601 |
3245 | #define ixPSX80_PHY0_TX_DFX_LANE7 0x1202701 |
3246 | #define ixPSX80_PHY0_TX_DEEMPH_BROADCAST 0x120ff02 |
3247 | #define ixPSX80_PHY0_TX_DEEMPH_LANE0 0x1202002 |
3248 | #define ixPSX80_PHY0_TX_DEEMPH_LANE1 0x1202102 |
3249 | #define ixPSX80_PHY0_TX_DEEMPH_LANE2 0x1202202 |
3250 | #define ixPSX80_PHY0_TX_DEEMPH_LANE3 0x1202302 |
3251 | #define ixPSX80_PHY0_TX_DEEMPH_LANE4 0x1202402 |
3252 | #define ixPSX80_PHY0_TX_DEEMPH_LANE5 0x1202502 |
3253 | #define ixPSX80_PHY0_TX_DEEMPH_LANE6 0x1202602 |
3254 | #define ixPSX80_PHY0_TX_DEEMPH_LANE7 0x1202702 |
3255 | #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST 0x120ff03 |
3256 | #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0 0x1202003 |
3257 | #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1 0x1202103 |
3258 | #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2 0x1202203 |
3259 | #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3 0x1202303 |
3260 | #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4 0x1202403 |
3261 | #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5 0x1202503 |
3262 | #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6 0x1202603 |
3263 | #define ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7 0x1202703 |
3264 | #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST 0x120ff04 |
3265 | #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0 0x1202004 |
3266 | #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1 0x1202104 |
3267 | #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2 0x1202204 |
3268 | #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3 0x1202304 |
3269 | #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4 0x1202404 |
3270 | #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5 0x1202504 |
3271 | #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6 0x1202604 |
3272 | #define ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7 0x1202704 |
3273 | #define ixPSX80_PHY0_TX_TXCNTRL_BROADCAST 0x120ff06 |
3274 | #define ixPSX80_PHY0_TX_TXCNTRL_LANE0 0x1202006 |
3275 | #define ixPSX80_PHY0_TX_TXCNTRL_LANE1 0x1202106 |
3276 | #define ixPSX80_PHY0_TX_TXCNTRL_LANE2 0x1202206 |
3277 | #define ixPSX80_PHY0_TX_TXCNTRL_LANE3 0x1202306 |
3278 | #define ixPSX80_PHY0_TX_TXCNTRL_LANE4 0x1202406 |
3279 | #define ixPSX80_PHY0_TX_TXCNTRL_LANE5 0x1202506 |
3280 | #define ixPSX80_PHY0_TX_TXCNTRL_LANE6 0x1202606 |
3281 | #define ixPSX80_PHY0_TX_TXCNTRL_LANE7 0x1202706 |
3282 | #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST 0x120ff07 |
3283 | #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x1202007 |
3284 | #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x1202107 |
3285 | #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x1202207 |
3286 | #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x1202307 |
3287 | #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4 0x1202407 |
3288 | #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5 0x1202507 |
3289 | #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6 0x1202607 |
3290 | #define ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7 0x1202707 |
3291 | #define ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn 0x1204180 |
3292 | #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt 0x1204101 |
3293 | #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl 0x1204102 |
3294 | #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1 0x1204103 |
3295 | #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2 0x1204104 |
3296 | #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode 0x1204105 |
3297 | #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl 0x1204108 |
3298 | #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3 0x1204109 |
3299 | #define ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess 0x120410a |
3300 | #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4 0x120410b |
3301 | #define ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5 0x120410c |
3302 | #define ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn 0x1204080 |
3303 | #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt 0x1204001 |
3304 | #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl 0x1204002 |
3305 | #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1 0x1204003 |
3306 | #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2 0x1204004 |
3307 | #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode 0x1204005 |
3308 | #define ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl 0x1204007 |
3309 | #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl 0x1204008 |
3310 | #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3 0x1204009 |
3311 | #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4 0x120400b |
3312 | #define ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5 0x120400c |
3313 | #define ixPSX81_PHY0_COM_COMMON_FUSE1 0x1216200 |
3314 | #define ixPSX81_PHY0_COM_COMMON_FUSE2 0x1216201 |
3315 | #define ixPSX81_PHY0_COM_COMMON_FUSE3 0x1216202 |
3316 | #define ixPSX81_PHY0_COM_COMMON_ELECIDLE 0x1216204 |
3317 | #define ixPSX81_PHY0_COM_COMMON_DFX 0x1216205 |
3318 | #define ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM 0x1216206 |
3319 | #define ixPSX81_PHY0_COM_COMMON_SELDEEMPH35 0x1216207 |
3320 | #define ixPSX81_PHY0_COM_COMMON_SELDEEMPH60 0x1216208 |
3321 | #define ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT 0x1216209 |
3322 | #define ixPSX81_PHY0_COM_COMMON_ADAPTCTL1 0x121620a |
3323 | #define ixPSX81_PHY0_COM_COMMON_ADAPTCTL2 0x121620b |
3324 | #define ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL 0x121620c |
3325 | #define ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1 0x121620d |
3326 | #define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL 0x121620e |
3327 | #define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1 0x121620f |
3328 | #define ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1 0x1216210 |
3329 | #define ixPSX81_PHY0_COM_COMMON_LNCNTRL 0x1216211 |
3330 | #define ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG 0x1216212 |
3331 | #define ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG 0x1216213 |
3332 | #define ixPSX81_PHY0_COM_COMMON_CDR_PHCTL 0x1216214 |
3333 | #define ixPSX81_PHY0_COM_COMMON_CDR_FRCTL 0x1216215 |
3334 | #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST 0x121fe00 |
3335 | #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0 0x1210000 |
3336 | #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1 0x1210100 |
3337 | #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2 0x1210200 |
3338 | #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3 0x1210300 |
3339 | #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4 0x1210400 |
3340 | #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5 0x1210500 |
3341 | #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6 0x1210600 |
3342 | #define ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7 0x1210700 |
3343 | #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST 0x121fe01 |
3344 | #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0 0x1210001 |
3345 | #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1 0x1210101 |
3346 | #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2 0x1210201 |
3347 | #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3 0x1210301 |
3348 | #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4 0x1210401 |
3349 | #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5 0x1210501 |
3350 | #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6 0x1210601 |
3351 | #define ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7 0x1210701 |
3352 | #define ixPSX81_PHY0_RX_RX_CTL_BROADCAST 0x121fe02 |
3353 | #define ixPSX81_PHY0_RX_RX_CTL_LANE0 0x1210002 |
3354 | #define ixPSX81_PHY0_RX_RX_CTL_LANE1 0x1210102 |
3355 | #define ixPSX81_PHY0_RX_RX_CTL_LANE2 0x1210202 |
3356 | #define ixPSX81_PHY0_RX_RX_CTL_LANE3 0x1210302 |
3357 | #define ixPSX81_PHY0_RX_RX_CTL_LANE4 0x1210402 |
3358 | #define ixPSX81_PHY0_RX_RX_CTL_LANE5 0x1210502 |
3359 | #define ixPSX81_PHY0_RX_RX_CTL_LANE6 0x1210602 |
3360 | #define ixPSX81_PHY0_RX_RX_CTL_LANE7 0x1210702 |
3361 | #define ixPSX81_PHY0_RX_DLL_CTL_BROADCAST 0x121fe03 |
3362 | #define ixPSX81_PHY0_RX_DLL_CTL_LANE0 0x1210003 |
3363 | #define ixPSX81_PHY0_RX_DLL_CTL_LANE1 0x1210103 |
3364 | #define ixPSX81_PHY0_RX_DLL_CTL_LANE2 0x1210203 |
3365 | #define ixPSX81_PHY0_RX_DLL_CTL_LANE3 0x1210303 |
3366 | #define ixPSX81_PHY0_RX_DLL_CTL_LANE4 0x1210403 |
3367 | #define ixPSX81_PHY0_RX_DLL_CTL_LANE5 0x1210503 |
3368 | #define ixPSX81_PHY0_RX_DLL_CTL_LANE6 0x1210603 |
3369 | #define ixPSX81_PHY0_RX_DLL_CTL_LANE7 0x1210703 |
3370 | #define ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST 0x121fe04 |
3371 | #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE0 0x1210004 |
3372 | #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE1 0x1210104 |
3373 | #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE2 0x1210204 |
3374 | #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE3 0x1210304 |
3375 | #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE4 0x1210404 |
3376 | #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE5 0x1210504 |
3377 | #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE6 0x1210604 |
3378 | #define ixPSX81_PHY0_RX_RXTEST_REGS_LANE7 0x1210704 |
3379 | #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST 0x121fe05 |
3380 | #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0 0x1210005 |
3381 | #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1 0x1210105 |
3382 | #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2 0x1210205 |
3383 | #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3 0x1210305 |
3384 | #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4 0x1210405 |
3385 | #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5 0x1210505 |
3386 | #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6 0x1210605 |
3387 | #define ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7 0x1210705 |
3388 | #define ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST 0x121fe0a |
3389 | #define ixPSX81_PHY0_RX_ADAPTCTL_LANE0 0x121000a |
3390 | #define ixPSX81_PHY0_RX_ADAPTCTL_LANE1 0x121010a |
3391 | #define ixPSX81_PHY0_RX_ADAPTCTL_LANE2 0x121020a |
3392 | #define ixPSX81_PHY0_RX_ADAPTCTL_LANE3 0x121030a |
3393 | #define ixPSX81_PHY0_RX_ADAPTCTL_LANE4 0x121040a |
3394 | #define ixPSX81_PHY0_RX_ADAPTCTL_LANE5 0x121050a |
3395 | #define ixPSX81_PHY0_RX_ADAPTCTL_LANE6 0x121060a |
3396 | #define ixPSX81_PHY0_RX_ADAPTCTL_LANE7 0x121070a |
3397 | #define ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST 0x121fe0b |
3398 | #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE0 0x121000b |
3399 | #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE1 0x121010b |
3400 | #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE2 0x121020b |
3401 | #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE3 0x121030b |
3402 | #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE4 0x121040b |
3403 | #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE5 0x121050b |
3404 | #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE6 0x121060b |
3405 | #define ixPSX81_PHY0_RX_FOMCALCCTL_LANE7 0x121070b |
3406 | #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST 0x121fe0c |
3407 | #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0 0x121000c |
3408 | #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1 0x121010c |
3409 | #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2 0x121020c |
3410 | #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3 0x121030c |
3411 | #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4 0x121040c |
3412 | #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5 0x121050c |
3413 | #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6 0x121060c |
3414 | #define ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7 0x121070c |
3415 | #define ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST 0x121fe0d |
3416 | #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0 0x121000d |
3417 | #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1 0x121010d |
3418 | #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2 0x121020d |
3419 | #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3 0x121030d |
3420 | #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4 0x121040d |
3421 | #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5 0x121050d |
3422 | #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6 0x121060d |
3423 | #define ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7 0x121070d |
3424 | #define ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST 0x121fe0e |
3425 | #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE0 0x121000e |
3426 | #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE1 0x121010e |
3427 | #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE2 0x121020e |
3428 | #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE3 0x121030e |
3429 | #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE4 0x121040e |
3430 | #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE5 0x121050e |
3431 | #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE6 0x121060e |
3432 | #define ixPSX81_PHY0_RX_ADAPTDBG1_LANE7 0x121070e |
3433 | #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST 0x121ff00 |
3434 | #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0 0x1212000 |
3435 | #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1 0x1212100 |
3436 | #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2 0x1212200 |
3437 | #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3 0x1212300 |
3438 | #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4 0x1212400 |
3439 | #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5 0x1212500 |
3440 | #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6 0x1212600 |
3441 | #define ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7 0x1212700 |
3442 | #define ixPSX81_PHY0_TX_DFX_BROADCAST 0x121ff01 |
3443 | #define ixPSX81_PHY0_TX_DFX_LANE0 0x1212001 |
3444 | #define ixPSX81_PHY0_TX_DFX_LANE1 0x1212101 |
3445 | #define ixPSX81_PHY0_TX_DFX_LANE2 0x1212201 |
3446 | #define ixPSX81_PHY0_TX_DFX_LANE3 0x1212301 |
3447 | #define ixPSX81_PHY0_TX_DFX_LANE4 0x1212401 |
3448 | #define ixPSX81_PHY0_TX_DFX_LANE5 0x1212501 |
3449 | #define ixPSX81_PHY0_TX_DFX_LANE6 0x1212601 |
3450 | #define ixPSX81_PHY0_TX_DFX_LANE7 0x1212701 |
3451 | #define ixPSX81_PHY0_TX_DEEMPH_BROADCAST 0x121ff02 |
3452 | #define ixPSX81_PHY0_TX_DEEMPH_LANE0 0x1212002 |
3453 | #define ixPSX81_PHY0_TX_DEEMPH_LANE1 0x1212102 |
3454 | #define ixPSX81_PHY0_TX_DEEMPH_LANE2 0x1212202 |
3455 | #define ixPSX81_PHY0_TX_DEEMPH_LANE3 0x1212302 |
3456 | #define ixPSX81_PHY0_TX_DEEMPH_LANE4 0x1212402 |
3457 | #define ixPSX81_PHY0_TX_DEEMPH_LANE5 0x1212502 |
3458 | #define ixPSX81_PHY0_TX_DEEMPH_LANE6 0x1212602 |
3459 | #define ixPSX81_PHY0_TX_DEEMPH_LANE7 0x1212702 |
3460 | #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST 0x121ff03 |
3461 | #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0 0x1212003 |
3462 | #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1 0x1212103 |
3463 | #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2 0x1212203 |
3464 | #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3 0x1212303 |
3465 | #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4 0x1212403 |
3466 | #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5 0x1212503 |
3467 | #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6 0x1212603 |
3468 | #define ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7 0x1212703 |
3469 | #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST 0x121ff04 |
3470 | #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0 0x1212004 |
3471 | #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1 0x1212104 |
3472 | #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2 0x1212204 |
3473 | #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3 0x1212304 |
3474 | #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4 0x1212404 |
3475 | #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5 0x1212504 |
3476 | #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6 0x1212604 |
3477 | #define ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7 0x1212704 |
3478 | #define ixPSX81_PHY0_TX_TXCNTRL_BROADCAST 0x121ff06 |
3479 | #define ixPSX81_PHY0_TX_TXCNTRL_LANE0 0x1212006 |
3480 | #define ixPSX81_PHY0_TX_TXCNTRL_LANE1 0x1212106 |
3481 | #define ixPSX81_PHY0_TX_TXCNTRL_LANE2 0x1212206 |
3482 | #define ixPSX81_PHY0_TX_TXCNTRL_LANE3 0x1212306 |
3483 | #define ixPSX81_PHY0_TX_TXCNTRL_LANE4 0x1212406 |
3484 | #define ixPSX81_PHY0_TX_TXCNTRL_LANE5 0x1212506 |
3485 | #define ixPSX81_PHY0_TX_TXCNTRL_LANE6 0x1212606 |
3486 | #define ixPSX81_PHY0_TX_TXCNTRL_LANE7 0x1212706 |
3487 | #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST 0x121ff07 |
3488 | #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x1212007 |
3489 | #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x1212107 |
3490 | #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x1212207 |
3491 | #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x1212307 |
3492 | #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4 0x1212407 |
3493 | #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5 0x1212507 |
3494 | #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6 0x1212607 |
3495 | #define ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7 0x1212707 |
3496 | #define ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn 0x1214180 |
3497 | #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt 0x1214101 |
3498 | #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl 0x1214102 |
3499 | #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1 0x1214103 |
3500 | #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2 0x1214104 |
3501 | #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode 0x1214105 |
3502 | #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl 0x1214108 |
3503 | #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3 0x1214109 |
3504 | #define ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess 0x121410a |
3505 | #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4 0x121410b |
3506 | #define ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5 0x121410c |
3507 | #define ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn 0x1214080 |
3508 | #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt 0x1214001 |
3509 | #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl 0x1214002 |
3510 | #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1 0x1214003 |
3511 | #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2 0x1214004 |
3512 | #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode 0x1214005 |
3513 | #define ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl 0x1214007 |
3514 | #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl 0x1214008 |
3515 | #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3 0x1214009 |
3516 | #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4 0x121400b |
3517 | #define ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5 0x121400c |
3518 | #define ixPSX80_PIF0_SCRATCH 0x1100001 |
3519 | #define ixPSX80_PIF0_HW_DEBUG 0x1100002 |
3520 | #define ixPSX80_PIF0_STRAP_0 0x1100003 |
3521 | #define ixPSX80_PIF0_CTRL 0x1100004 |
3522 | #define ixPSX80_PIF0_TX_CTRL 0x1100008 |
3523 | #define ixPSX80_PIF0_TX_CTRL2 0x1100009 |
3524 | #define ixPSX80_PIF0_RX_CTRL 0x110000a |
3525 | #define ixPSX80_PIF0_RX_CTRL2 0x110000b |
3526 | #define ixPSX80_PIF0_GLB_OVRD 0x110000c |
3527 | #define ixPSX80_PIF0_GLB_OVRD2 0x110000d |
3528 | #define ixPSX80_PIF0_BIF_CMD_STATUS 0x1100010 |
3529 | #define ixPSX80_PIF0_CMD_BUS_CTRL 0x1100011 |
3530 | #define ixPSX80_PIF0_CMD_BUS_GLB_OVRD 0x1100013 |
3531 | #define ixPSX80_PIF0_LANE0_OVRD 0x1100014 |
3532 | #define ixPSX80_PIF0_LANE0_OVRD2 0x1100015 |
3533 | #define ixPSX80_PIF0_LANE1_OVRD 0x1100016 |
3534 | #define ixPSX80_PIF0_LANE1_OVRD2 0x1100017 |
3535 | #define ixPSX80_PIF0_LANE2_OVRD 0x1100018 |
3536 | #define ixPSX80_PIF0_LANE2_OVRD2 0x1100019 |
3537 | #define ixPSX80_PIF0_LANE3_OVRD 0x110001a |
3538 | #define ixPSX80_PIF0_LANE3_OVRD2 0x110001b |
3539 | #define ixPSX80_PIF0_LANE4_OVRD 0x110001c |
3540 | #define ixPSX80_PIF0_LANE4_OVRD2 0x110001d |
3541 | #define ixPSX80_PIF0_LANE5_OVRD 0x110001e |
3542 | #define ixPSX80_PIF0_LANE5_OVRD2 0x110001f |
3543 | #define ixPSX80_PIF0_LANE6_OVRD 0x1100020 |
3544 | #define ixPSX80_PIF0_LANE6_OVRD2 0x1100021 |
3545 | #define ixPSX80_PIF0_LANE7_OVRD 0x1100022 |
3546 | #define ixPSX80_PIF0_LANE7_OVRD2 0x1100023 |
3547 | #define ixPSX81_PIF0_SCRATCH 0x1110001 |
3548 | #define ixPSX81_PIF0_HW_DEBUG 0x1110002 |
3549 | #define ixPSX81_PIF0_STRAP_0 0x1110003 |
3550 | #define ixPSX81_PIF0_CTRL 0x1110004 |
3551 | #define ixPSX81_PIF0_TX_CTRL 0x1110008 |
3552 | #define ixPSX81_PIF0_TX_CTRL2 0x1110009 |
3553 | #define ixPSX81_PIF0_RX_CTRL 0x111000a |
3554 | #define ixPSX81_PIF0_RX_CTRL2 0x111000b |
3555 | #define ixPSX81_PIF0_GLB_OVRD 0x111000c |
3556 | #define ixPSX81_PIF0_GLB_OVRD2 0x111000d |
3557 | #define ixPSX81_PIF0_BIF_CMD_STATUS 0x1110010 |
3558 | #define ixPSX81_PIF0_CMD_BUS_CTRL 0x1110011 |
3559 | #define ixPSX81_PIF0_CMD_BUS_GLB_OVRD 0x1110013 |
3560 | #define ixPSX81_PIF0_LANE0_OVRD 0x1110014 |
3561 | #define ixPSX81_PIF0_LANE0_OVRD2 0x1110015 |
3562 | #define ixPSX81_PIF0_LANE1_OVRD 0x1110016 |
3563 | #define ixPSX81_PIF0_LANE1_OVRD2 0x1110017 |
3564 | #define ixPSX81_PIF0_LANE2_OVRD 0x1110018 |
3565 | #define ixPSX81_PIF0_LANE2_OVRD2 0x1110019 |
3566 | #define ixPSX81_PIF0_LANE3_OVRD 0x111001a |
3567 | #define ixPSX81_PIF0_LANE3_OVRD2 0x111001b |
3568 | #define ixPSX81_PIF0_LANE4_OVRD 0x111001c |
3569 | #define ixPSX81_PIF0_LANE4_OVRD2 0x111001d |
3570 | #define ixPSX81_PIF0_LANE5_OVRD 0x111001e |
3571 | #define ixPSX81_PIF0_LANE5_OVRD2 0x111001f |
3572 | #define ixPSX81_PIF0_LANE6_OVRD 0x1110020 |
3573 | #define ixPSX81_PIF0_LANE6_OVRD2 0x1110021 |
3574 | #define ixPSX81_PIF0_LANE7_OVRD 0x1110022 |
3575 | #define ixPSX81_PIF0_LANE7_OVRD2 0x1110023 |
3576 | |
3577 | #endif /* BIF_5_1_D_H */ |
3578 | |