1/*
2 * Copyright (C) 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _clk_10_0_2_OFFSET_HEADER
22#define _clk_10_0_2_OFFSET_HEADER
23
24
25
26// addressBlock: clk_clk1_0_SmuClkDec
27// base address: 0x5b800
28#define mmCLK1_CLK_PLL_REQ 0x000f
29#define mmCLK1_CLK_PLL_REQ_BASE_IDX 1
30#define mmCLK1_CLK0_BYPASS_CNTL 0x0049
31#define mmCLK1_CLK0_BYPASS_CNTL_BASE_IDX 1
32#define mmCLK1_CLK1_BYPASS_CNTL 0x0053
33#define mmCLK1_CLK1_BYPASS_CNTL_BASE_IDX 1
34#define mmCLK1_CLK2_BYPASS_CNTL 0x005d
35#define mmCLK1_CLK2_BYPASS_CNTL_BASE_IDX 1
36#define mmCLK1_CLK2_STATUS 0x005e
37#define mmCLK1_CLK2_STATUS_BASE_IDX 1
38#define mmCLK1_CLK3_DFS_CNTL 0x005f
39#define mmCLK1_CLK3_DFS_CNTL_BASE_IDX 1
40#define mmCLK1_CLK3_DS_CNTL 0x0060
41#define mmCLK1_CLK3_DS_CNTL_BASE_IDX 1
42#define mmCLK1_CLK3_ALLOW_DS 0x0061
43#define mmCLK1_CLK3_ALLOW_DS_BASE_IDX 1
44#define mmCLK1_CLK3_BYPASS_CNTL 0x0067
45#define mmCLK1_CLK3_BYPASS_CNTL_BASE_IDX 1
46#define mmCLK1_CLK0_CURRENT_CNT 0x008a
47#define mmCLK1_CLK0_CURRENT_CNT_BASE_IDX 1
48#define mmCLK1_CLK1_CURRENT_CNT 0x008b
49#define mmCLK1_CLK1_CURRENT_CNT_BASE_IDX 1
50#define mmCLK1_CLK2_CURRENT_CNT 0x008c
51#define mmCLK1_CLK2_CURRENT_CNT_BASE_IDX 1
52#define mmCLK1_CLK3_CURRENT_CNT 0x008d
53#define mmCLK1_CLK3_CURRENT_CNT_BASE_IDX 1
54
55
56#endif
57

source code of linux/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h