1	/*
2	* DCE_10_0 Register documentation
3	*
4	* Copyright (C) 2014 Advanced Micro Devices, Inc.
5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:
12	*
13	* The above copyright notice and this permission notice shall be included
14	* in all copies or substantial portions of the Software.
15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20	* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22	*/
23
24	#ifndef DCE_10_0_ENUM_H
25	#define DCE_10_0_ENUM_H
26
27	typedef enum DCIO_DC_GENERICA_SEL {
28	DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x0,
29	DCIO_GENERICA_SEL_STEREOSYNC = 0x1,
30	DCIO_GENERICA_SEL_DACA_PIXCLK = 0x2,
31	DCIO_GENERICA_SEL_DACB_PIXCLK = 0x3,
32	DCIO_GENERICA_SEL_DVOA_CTL3 = 0x4,
33	DCIO_GENERICA_SEL_P1_PLLCLK = 0x5,
34	DCIO_GENERICA_SEL_P2_PLLCLK = 0x6,
35	DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x7,
36	DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x8,
37	DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x9,
38	DCIO_GENERICA_SEL_GENERICA_DCCG = 0xa,
39	DCIO_GENERICA_SEL_SYNCEN = 0xb,
40	DCIO_GENERICA_SEL_GENERICA_SCG = 0xc,
41	DCIO_GENERICA_SEL_RESERVED_VALUE13 = 0xd,
42	DCIO_GENERICA_SEL_RESERVED_VALUE14 = 0xe,
43	DCIO_GENERICA_SEL_RESERVED_VALUE15 = 0xf,
44	DCIO_GENERICA_SEL_GENERICA_DPRX = 0x10,
45	DCIO_GENERICA_SEL_GENERICB_DPRX = 0x11,
46	} DCIO_DC_GENERICA_SEL;
47	typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
48	DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x0,
49	DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x1,
50	DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x2,
51	DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x3,
52	DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x4,
53	DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x5,
54	} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
55	typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
56	DCIO_UNIPHYA_FBDIV_CLK = 0x0,
57	DCIO_UNIPHYB_FBDIV_CLK = 0x1,
58	DCIO_UNIPHYC_FBDIV_CLK = 0x2,
59	DCIO_UNIPHYD_FBDIV_CLK = 0x3,
60	DCIO_UNIPHYE_FBDIV_CLK = 0x4,
61	DCIO_UNIPHYF_FBDIV_CLK = 0x5,
62	} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
63	typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
64	DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x0,
65	DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x1,
66	DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x2,
67	DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x3,
68	DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x4,
69	DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x5,
70	} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
71	typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
72	DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x0,
73	DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x1,
74	DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x2,
75	DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x3,
76	DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x4,
77	DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x5,
78	} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
79	typedef enum DCIO_DC_GENERICB_SEL {
80	DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x0,
81	DCIO_GENERICB_SEL_STEREOSYNC = 0x1,
82	DCIO_GENERICB_SEL_DACA_PIXCLK = 0x2,
83	DCIO_GENERICB_SEL_DACB_PIXCLK = 0x3,
84	DCIO_GENERICB_SEL_DVOA_CTL3 = 0x4,
85	DCIO_GENERICB_SEL_P1_PLLCLK = 0x5,
86	DCIO_GENERICB_SEL_P2_PLLCLK = 0x6,
87	DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x7,
88	DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x8,
89	DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x9,
90	DCIO_GENERICB_SEL_GENERICB_DCCG = 0xa,
91	DCIO_GENERICB_SEL_SYNCEN = 0xb,
92	DCIO_GENERICB_SEL_GENERICA_SCG = 0xc,
93	DCIO_GENERICB_SEL_RESERVED_VALUE13 = 0xd,
94	DCIO_GENERICB_SEL_RESERVED_VALUE14 = 0xe,
95	DCIO_GENERICB_SEL_RESERVED_VALUE15 = 0xf,
96	} DCIO_DC_GENERICB_SEL;
97	typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
98	DCIO_DC_PAD_EXTERN_SIG_SEL_MVP = 0x0,
99	DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA = 0x1,
100	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK = 0x2,
101	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC = 0x3,
102	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA = 0x4,
103	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB = 0x5,
104	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC = 0x6,
105	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1 = 0x7,
106	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2 = 0x8,
107	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK = 0x9,
108	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA = 0xa,
109	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK = 0xb,
110	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA = 0xc,
111	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1 = 0xd,
112	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0 = 0xe,
113	DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL = 0xf,
114	} DCIO_DC_PAD_EXTERN_SIG_SEL;
115	typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
116	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA = 0x0,
117	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE = 0x1,
118	DCIO_MVP_PIXEL_SRC_STATUS_CRTC = 0x2,
119	DCIO_MVP_PIXEL_SRC_STATUS_LB = 0x3,
120	} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
121	typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
122	DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x0,
123	DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x1,
124	DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x2,
125	DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x3,
126	} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
127	typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
128	DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x0,
129	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x1,
130	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x2,
131	DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x3,
132	} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
133	typedef enum DCIO_DC_GPIO_VIP_DEBUG {
134	DCIO_DC_GPIO_VIP_DEBUG_NORMAL = 0x0,
135	DCIO_DC_GPIO_VIP_DEBUG_CG_BIG = 0x1,
136	} DCIO_DC_GPIO_VIP_DEBUG;
137	typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
138	DCIO_DC_GPIO_MACRO_DEBUG_NORMAL = 0x0,
139	DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF = 0x1,
140	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2 = 0x2,
141	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3 = 0x3,
142	} DCIO_DC_GPIO_MACRO_DEBUG;
143	typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
144	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL = 0x0,
145	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP = 0x1,
146	} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
147	typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
148	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS = 0x0,
149	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE = 0x1,
150	} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
151	typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
152	DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x0,
153	DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x1,
154	} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
155	typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
156	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0,
157	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1,
158	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2,
159	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3,
160	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4,
161	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5,
162	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6,
163	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7,
164	} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
165	typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
166	DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x0,
167	DCIO_UNIPHY_CHANNEL_INVERTED = 0x1,
168	} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
169	typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
170	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x0,
171	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x1,
172	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2,
173	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3,
174	} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
175	typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
176	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x0,
177	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x1,
178	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x2,
179	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x3,
180	} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
181	typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
182	DCIO_VIP_MUX_EN_DVO = 0x0,
183	DCIO_VIP_MUX_EN_VIP = 0x1,
184	} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
185	typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
186	DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x0,
187	DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x1,
188	} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
189	typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
190	DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x0,
191	DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x1,
192	} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
193	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
194	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0,
195	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1,
196	} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
197	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
198	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x0,
199	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x1,
200	} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
201	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
202	DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x0,
203	DCIO_LVTMA_SYNCEN_POL_INVERT = 0x1,
204	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
205	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
206	DCIO_LVTMA_DIGON_OFF = 0x0,
207	DCIO_LVTMA_DIGON_ON = 0x1,
208	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
209	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
210	DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x0,
211	DCIO_LVTMA_DIGON_POL_INVERT = 0x1,
212	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
213	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
214	DCIO_LVTMA_BLON_OFF = 0x0,
215	DCIO_LVTMA_BLON_ON = 0x1,
216	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
217	typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
218	DCIO_LVTMA_BLON_POL_NON_INVERT = 0x0,
219	DCIO_LVTMA_BLON_POL_INVERT = 0x1,
220	} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
221	typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
222	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x0,
223	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x1,
224	} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
225	typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
226	DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x0,
227	DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x1,
228	} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
229	typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
230	DCIO_BL_PWM_DISABLE = 0x0,
231	DCIO_BL_PWM_ENABLE = 0x1,
232	} DCIO_BL_PWM_CNTL_BL_PWM_EN;
233	typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
234	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x0,
235	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x1,
236	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x2,
237	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x3,
238	} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
239	typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
240	DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x0,
241	DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x1,
242	} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
243	typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
244	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x0,
245	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x1,
246	} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
247	typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
248	DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x0,
249	DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x1,
250	} DCIO_BL_PWM_GRP1_REG_LOCK;
251	typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
252	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x0,
253	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x1,
254	} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
255	typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
256	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0,
257	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1,
258	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2,
259	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3,
260	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4,
261	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5,
262	} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
263	typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
264	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0,
265	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1,
266	} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
267	typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
268	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x0,
269	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x1,
270	} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
271	typedef enum DCIO_GSL_SEL {
272	DCIO_GSL_SEL_GROUP_0 = 0x0,
273	DCIO_GSL_SEL_GROUP_1 = 0x1,
274	DCIO_GSL_SEL_GROUP_2 = 0x2,
275	} DCIO_GSL_SEL;
276	typedef enum DCIO_GENLK_CLK_GSL_MASK {
277	DCIO_GENLK_CLK_GSL_MASK_NO = 0x0,
278	DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x1,
279	DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x2,
280	} DCIO_GENLK_CLK_GSL_MASK;
281	typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
282	DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x0,
283	DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x1,
284	DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x2,
285	} DCIO_GENLK_VSYNC_GSL_MASK;
286	typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
287	DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x0,
288	DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x1,
289	DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x2,
290	} DCIO_SWAPLOCK_A_GSL_MASK;
291	typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
292	DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x0,
293	DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x1,
294	DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x2,
295	} DCIO_SWAPLOCK_B_GSL_MASK;
296	typedef enum DCIO_GSL_VSYNC_SEL {
297	DCIO_GSL_VSYNC_SEL_PIPE0 = 0x0,
298	DCIO_GSL_VSYNC_SEL_PIPE1 = 0x1,
299	DCIO_GSL_VSYNC_SEL_PIPE2 = 0x2,
300	DCIO_GSL_VSYNC_SEL_PIPE3 = 0x3,
301	DCIO_GSL_VSYNC_SEL_PIPE4 = 0x4,
302	DCIO_GSL_VSYNC_SEL_PIPE5 = 0x5,
303	} DCIO_GSL_VSYNC_SEL;
304	typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
305	DCIO_GSL0_TIMING_SYNC_SEL_PIPE = 0x0,
306	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
307	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
308	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
309	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
310	} DCIO_GSL0_TIMING_SYNC_SEL;
311	typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
312	DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
313	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
314	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
315	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
316	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
317	} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
318	typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
319	DCIO_GSL1_TIMING_SYNC_SEL_PIPE = 0x0,
320	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
321	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
322	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
323	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
324	} DCIO_GSL1_TIMING_SYNC_SEL;
325	typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
326	DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
327	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
328	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
329	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
330	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
331	} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
332	typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
333	DCIO_GSL2_TIMING_SYNC_SEL_PIPE = 0x0,
334	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC = 0x1,
335	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK = 0x2,
336	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A = 0x3,
337	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B = 0x4,
338	} DCIO_GSL2_TIMING_SYNC_SEL;
339	typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
340	DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION = 0x0,
341	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC = 0x1,
342	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK = 0x2,
343	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A = 0x3,
344	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B = 0x4,
345	} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
346	typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
347	DCIO_GPU_TIMER_START_0_END_27 = 0x0,
348	DCIO_GPU_TIMER_START_1_END_28 = 0x1,
349	DCIO_GPU_TIMER_START_2_END_29 = 0x2,
350	DCIO_GPU_TIMER_START_3_END_30 = 0x3,
351	DCIO_GPU_TIMER_START_4_END_31 = 0x4,
352	DCIO_GPU_TIMER_START_6_END_33 = 0x5,
353	DCIO_GPU_TIMER_START_8_END_35 = 0x6,
354	DCIO_GPU_TIMER_START_10_END_37 = 0x7,
355	} DCIO_DC_GPU_TIMER_START_POSITION;
356	typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
357	DCIO_TEST_CLK_SEL_DISPCLK = 0x0,
358	DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x1,
359	DCIO_TEST_CLK_SEL_SCLK = 0x2,
360	} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
361	typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
362	DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x0,
363	DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x1,
364	} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
365	typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS {
366	DCIO_DISPCLK_R_DCIO_RAMP_DISABLE = 0x0,
367	DCIO_DISPCLK_R_DCIO_RAMP_ENABLE = 0x1,
368	} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_RAMP_DIS;
369	typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
370	DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x0,
371	DCIO_EXT_VSYNC_MUX_CRTC0 = 0x1,
372	DCIO_EXT_VSYNC_MUX_CRTC1 = 0x2,
373	DCIO_EXT_VSYNC_MUX_CRTC2 = 0x3,
374	DCIO_EXT_VSYNC_MUX_CRTC3 = 0x4,
375	DCIO_EXT_VSYNC_MUX_CRTC4 = 0x5,
376	DCIO_EXT_VSYNC_MUX_CRTC5 = 0x6,
377	DCIO_EXT_VSYNC_MUX_GENERICB = 0x7,
378	} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
379	typedef enum DCIO_DCO_EXT_VSYNC_MASK {
380	DCIO_EXT_VSYNC_MASK_NONE = 0x0,
381	DCIO_EXT_VSYNC_MASK_PIPE0 = 0x1,
382	DCIO_EXT_VSYNC_MASK_PIPE1 = 0x2,
383	DCIO_EXT_VSYNC_MASK_PIPE2 = 0x3,
384	DCIO_EXT_VSYNC_MASK_PIPE3 = 0x4,
385	DCIO_EXT_VSYNC_MASK_PIPE4 = 0x5,
386	DCIO_EXT_VSYNC_MASK_PIPE5 = 0x6,
387	DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x7,
388	} DCIO_DCO_EXT_VSYNC_MASK;
389	typedef enum DCIO_DBG_OUT_PIN_SEL {
390	DCIO_DBG_OUT_PIN_SEL_LOW_12BIT = 0x0,
391	DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT = 0x1,
392	} DCIO_DBG_OUT_PIN_SEL;
393	typedef enum DCIO_DBG_OUT_12BIT_SEL {
394	DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT = 0x0,
395	DCIO_DBG_OUT_12BIT_SEL_MID_12BIT = 0x1,
396	DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT = 0x2,
397	DCIO_DBG_OUT_12BIT_SEL_OVERRIDE = 0x3,
398	} DCIO_DBG_OUT_12BIT_SEL;
399	typedef enum DCIO_DSYNC_SOFT_RESET {
400	DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x0,
401	DCIO_DSYNC_SOFT_RESET_ASSERT = 0x1,
402	} DCIO_DSYNC_SOFT_RESET;
403	typedef enum DCIO_DACA_SOFT_RESET {
404	DCIO_DACA_SOFT_RESET_DEASSERT = 0x0,
405	DCIO_DACA_SOFT_RESET_ASSERT = 0x1,
406	} DCIO_DACA_SOFT_RESET;
407	typedef enum DCIO_DCRXPHY_SOFT_RESET {
408	DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x0,
409	DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x1,
410	} DCIO_DCRXPHY_SOFT_RESET;
411	typedef enum DCIO_DPHY_LANE_SEL {
412	DCIO_DPHY_LANE_SEL_LANE0 = 0x0,
413	DCIO_DPHY_LANE_SEL_LANE1 = 0x1,
414	DCIO_DPHY_LANE_SEL_LANE2 = 0x2,
415	DCIO_DPHY_LANE_SEL_LANE3 = 0x3,
416	} DCIO_DPHY_LANE_SEL;
417	typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
418	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x0,
419	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x1,
420	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE = 0x2,
421	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE = 0x3,
422	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE = 0x4,
423	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE = 0x5,
424	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE = 0x6,
425	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE = 0x7,
426	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE = 0x8,
427	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE = 0x9,
428	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE = 0xa,
429	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE = 0xb,
430	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0xc,
431	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0xd,
432	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP = 0xe,
433	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP = 0xf,
434	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP = 0x10,
435	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP = 0x11,
436	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_P_FLIP = 0x12,
437	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_P_FLIP = 0x13,
438	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_P_FLIP = 0x14,
439	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_P_FLIP = 0x15,
440	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_P_FLIP = 0x16,
441	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_P_FLIP = 0x17,
442	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x18,
443	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x19,
444	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM = 0x1a,
445	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM = 0x1b,
446	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM = 0x1c,
447	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM = 0x1d,
448	DCIO_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM = 0x1e,
449	DCIO_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM = 0x1f,
450	DCIO_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM = 0x20,
451	DCIO_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM = 0x21,
452	DCIO_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM = 0x22,
453	DCIO_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM = 0x23,
454	} DCIO_DC_GPU_TIMER_READ_SELECT;
455	typedef enum DCIO_IMPCAL_STEP_DELAY {
456	DCIO_IMPCAL_STEP_DELAY_1us = 0x0,
457	DCIO_IMPCAL_STEP_DELAY_2us = 0x1,
458	DCIO_IMPCAL_STEP_DELAY_3us = 0x2,
459	DCIO_IMPCAL_STEP_DELAY_4us = 0x3,
460	DCIO_IMPCAL_STEP_DELAY_5us = 0x4,
461	DCIO_IMPCAL_STEP_DELAY_6us = 0x5,
462	DCIO_IMPCAL_STEP_DELAY_7us = 0x6,
463	DCIO_IMPCAL_STEP_DELAY_8us = 0x7,
464	DCIO_IMPCAL_STEP_DELAY_9us = 0x8,
465	DCIO_IMPCAL_STEP_DELAY_10us = 0x9,
466	DCIO_IMPCAL_STEP_DELAY_11us = 0xa,
467	DCIO_IMPCAL_STEP_DELAY_12us = 0xb,
468	DCIO_IMPCAL_STEP_DELAY_13us = 0xc,
469	DCIO_IMPCAL_STEP_DELAY_14us = 0xd,
470	DCIO_IMPCAL_STEP_DELAY_15us = 0xe,
471	DCIO_IMPCAL_STEP_DELAY_16us = 0xf,
472	} DCIO_IMPCAL_STEP_DELAY;
473	typedef enum DCIO_UNIPHY_IMPCAL_SEL {
474	DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x0,
475	DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x1,
476	} DCIO_UNIPHY_IMPCAL_SEL;
477	typedef enum DCIOCHIP_HPD_SEL {
478	DCIOCHIP_HPD_SEL_ASYNC = 0x0,
479	DCIOCHIP_HPD_SEL_CLOCKED = 0x1,
480	} DCIOCHIP_HPD_SEL;
481	typedef enum DCIOCHIP_PAD_MODE {
482	DCIOCHIP_PAD_MODE_DDC = 0x0,
483	DCIOCHIP_PAD_MODE_DP = 0x1,
484	} DCIOCHIP_PAD_MODE;
485	typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
486	DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x0,
487	DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x1,
488	} DCIOCHIP_AUXSLAVE_PAD_MODE;
489	typedef enum DCIOCHIP_INVERT {
490	DCIOCHIP_POL_NON_INVERT = 0x0,
491	DCIOCHIP_POL_INVERT = 0x1,
492	} DCIOCHIP_INVERT;
493	typedef enum DCIOCHIP_PD_EN {
494	DCIOCHIP_PD_EN_NOTALLOW = 0x0,
495	DCIOCHIP_PD_EN_ALLOW = 0x1,
496	} DCIOCHIP_PD_EN;
497	typedef enum DCIOCHIP_GPIO_MASK_EN {
498	DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x0,
499	DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x1,
500	} DCIOCHIP_GPIO_MASK_EN;
501	typedef enum DCIOCHIP_MASK {
502	DCIOCHIP_MASK_DISABLE = 0x0,
503	DCIOCHIP_MASK_ENABLE = 0x1,
504	} DCIOCHIP_MASK;
505	typedef enum DCIOCHIP_GPIO_I2C_MASK {
506	DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x0,
507	DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x1,
508	} DCIOCHIP_GPIO_I2C_MASK;
509	typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
510	DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x0,
511	DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x1,
512	} DCIOCHIP_GPIO_I2C_DRIVE;
513	typedef enum DCIOCHIP_GPIO_I2C_EN {
514	DCIOCHIP_GPIO_I2C_DISABLE = 0x0,
515	DCIOCHIP_GPIO_I2C_ENABLE = 0x1,
516	} DCIOCHIP_GPIO_I2C_EN;
517	typedef enum DCIOCHIP_MASK_4BIT {
518	DCIOCHIP_MASK_4BIT_DISABLE = 0x0,
519	DCIOCHIP_MASK_4BIT_ENABLE = 0xf,
520	} DCIOCHIP_MASK_4BIT;
521	typedef enum DCIOCHIP_ENABLE_4BIT {
522	DCIOCHIP_4BIT_DISABLE = 0x0,
523	DCIOCHIP_4BIT_ENABLE = 0xf,
524	} DCIOCHIP_ENABLE_4BIT;
525	typedef enum DCIOCHIP_MASK_5BIT {
526	DCIOCHIP_MASIK_5BIT_DISABLE = 0x0,
527	DCIOCHIP_MASIK_5BIT_ENABLE = 0x1f,
528	} DCIOCHIP_MASK_5BIT;
529	typedef enum DCIOCHIP_ENABLE_5BIT {
530	DCIOCHIP_5BIT_DISABLE = 0x0,
531	DCIOCHIP_5BIT_ENABLE = 0x1f,
532	} DCIOCHIP_ENABLE_5BIT;
533	typedef enum DCIOCHIP_MASK_2BIT {
534	DCIOCHIP_MASK_2BIT_DISABLE = 0x0,
535	DCIOCHIP_MASK_2BIT_ENABLE = 0x3,
536	} DCIOCHIP_MASK_2BIT;
537	typedef enum DCIOCHIP_ENABLE_2BIT {
538	DCIOCHIP_2BIT_DISABLE = 0x0,
539	DCIOCHIP_2BIT_ENABLE = 0x3,
540	} DCIOCHIP_ENABLE_2BIT;
541	typedef enum DCIOCHIP_REF_27_SRC_SEL {
542	DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x0,
543	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x1,
544	DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x2,
545	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x3,
546	} DCIOCHIP_REF_27_SRC_SEL;
547	typedef enum DCIOCHIP_DVO_VREFPON {
548	DCIOCHIP_DVO_VREFPON_DISABLE = 0x0,
549	DCIOCHIP_DVO_VREFPON_ENABLE = 0x1,
550	} DCIOCHIP_DVO_VREFPON;
551	typedef enum DCIOCHIP_DVO_VREFSEL {
552	DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x0,
553	DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x1,
554	} DCIOCHIP_DVO_VREFSEL;
555	typedef enum COL_MAN_UPDATE_LOCK {
556	COL_MAN_UPDATE_UNLOCKED = 0x0,
557	COL_MAN_UPDATE_LOCKED = 0x1,
558	} COL_MAN_UPDATE_LOCK;
559	typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
560	COL_MAN_MULTIPLE_UPDATE = 0x0,
561	COL_MAN_MULTIPLE_UPDAT_EDISABLE = 0x1,
562	} COL_MAN_DISABLE_MULTIPLE_UPDATE;
563	typedef enum COL_MAN_INPUTCSC_MODE {
564	INPUTCSC_MODE_BYPASS = 0x0,
565	INPUTCSC_MODE_A = 0x1,
566	INPUTCSC_MODE_B = 0x2,
567	INPUTCSC_MODE_UNITY = 0x3,
568	} COL_MAN_INPUTCSC_MODE;
569	typedef enum COL_MAN_INPUTCSC_TYPE {
570	INPUTCSC_TYPE_12_0 = 0x0,
571	INPUTCSC_TYPE_10_2 = 0x1,
572	INPUTCSC_TYPE_8_4 = 0x2,
573	} COL_MAN_INPUTCSC_TYPE;
574	typedef enum COL_MAN_INPUTCSC_CONVERT {
575	INPUTCSC_ROUND = 0x0,
576	INPUTCSC_TRUNCATE = 0x1,
577	} COL_MAN_INPUTCSC_CONVERT;
578	typedef enum COL_MAN_PRESCALE_MODE {
579	PRESCALE_MODE_BYPASS = 0x0,
580	PRESCALE_MODE_PROGRAM = 0x1,
581	PRESCALE_MODE_UNITY = 0x2,
582	} COL_MAN_PRESCALE_MODE;
583	typedef enum COL_MAN_OUTPUT_CSC_MODE {
584	COL_MAN_OUTPUT_CSC_BYPASS = 0x0,
585	COL_MAN_OUTPUT_CSC_RGB = 0x1,
586	COL_MAN_OUTPUT_CSC_YCrCb601 = 0x2,
587	COL_MAN_OUTPUT_CSC_YCrCb709 = 0x3,
588	COL_MAN_OUTPUT_CSC_A = 0x4,
589	COL_MAN_OUTPUT_CSC_B = 0x5,
590	} COL_MAN_OUTPUT_CSC_MODE;
591	typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
592	DENORM_CLAMP_CONTROL_UNITY = 0x0,
593	DENORM_CLAMP_CONTROL_8 = 0x1,
594	DENORM_CLAMP_CONTROL_10 = 0x2,
595	DENORM_CLAMP_CONTROL_12 = 0x3,
596	} COL_MAN_DENORM_CLAMP_CONTROL;
597	typedef enum COL_MAN_GAMMA_CORR_CONTROL {
598	GAMMA_CORR_CONTROL_BYPASS = 0x0,
599	GAMMA_CORR_CONTROL_A = 0x1,
600	GAMMA_CORR_CONTROL_B = 0x2,
601	} COL_MAN_GAMMA_CORR_CONTROL;
602	typedef enum SurfaceEndian {
603	ENDIAN_NONE = 0x0,
604	ENDIAN_8IN16 = 0x1,
605	ENDIAN_8IN32 = 0x2,
606	ENDIAN_8IN64 = 0x3,
607	} SurfaceEndian;
608	typedef enum ArrayMode {
609	ARRAY_LINEAR_GENERAL = 0x0,
610	ARRAY_LINEAR_ALIGNED = 0x1,
611	ARRAY_1D_TILED_THIN1 = 0x2,
612	ARRAY_1D_TILED_THICK = 0x3,
613	ARRAY_2D_TILED_THIN1 = 0x4,
614	ARRAY_PRT_TILED_THIN1 = 0x5,
615	ARRAY_PRT_2D_TILED_THIN1 = 0x6,
616	ARRAY_2D_TILED_THICK = 0x7,
617	ARRAY_2D_TILED_XTHICK = 0x8,
618	ARRAY_PRT_TILED_THICK = 0x9,
619	ARRAY_PRT_2D_TILED_THICK = 0xa,
620	ARRAY_PRT_3D_TILED_THIN1 = 0xb,
621	ARRAY_3D_TILED_THIN1 = 0xc,
622	ARRAY_3D_TILED_THICK = 0xd,
623	ARRAY_3D_TILED_XTHICK = 0xe,
624	ARRAY_PRT_3D_TILED_THICK = 0xf,
625	} ArrayMode;
626	typedef enum PipeTiling {
627	CONFIG_1_PIPE = 0x0,
628	CONFIG_2_PIPE = 0x1,
629	CONFIG_4_PIPE = 0x2,
630	CONFIG_8_PIPE = 0x3,
631	} PipeTiling;
632	typedef enum BankTiling {
633	CONFIG_4_BANK = 0x0,
634	CONFIG_8_BANK = 0x1,
635	} BankTiling;
636	typedef enum GroupInterleave {
637	CONFIG_256B_GROUP = 0x0,
638	CONFIG_512B_GROUP = 0x1,
639	} GroupInterleave;
640	typedef enum RowTiling {
641	CONFIG_1KB_ROW = 0x0,
642	CONFIG_2KB_ROW = 0x1,
643	CONFIG_4KB_ROW = 0x2,
644	CONFIG_8KB_ROW = 0x3,
645	CONFIG_1KB_ROW_OPT = 0x4,
646	CONFIG_2KB_ROW_OPT = 0x5,
647	CONFIG_4KB_ROW_OPT = 0x6,
648	CONFIG_8KB_ROW_OPT = 0x7,
649	} RowTiling;
650	typedef enum BankSwapBytes {
651	CONFIG_128B_SWAPS = 0x0,
652	CONFIG_256B_SWAPS = 0x1,
653	CONFIG_512B_SWAPS = 0x2,
654	CONFIG_1KB_SWAPS = 0x3,
655	} BankSwapBytes;
656	typedef enum SampleSplitBytes {
657	CONFIG_1KB_SPLIT = 0x0,
658	CONFIG_2KB_SPLIT = 0x1,
659	CONFIG_4KB_SPLIT = 0x2,
660	CONFIG_8KB_SPLIT = 0x3,
661	} SampleSplitBytes;
662	typedef enum NumPipes {
663	ADDR_CONFIG_1_PIPE = 0x0,
664	ADDR_CONFIG_2_PIPE = 0x1,
665	ADDR_CONFIG_4_PIPE = 0x2,
666	ADDR_CONFIG_8_PIPE = 0x3,
667	} NumPipes;
668	typedef enum PipeInterleaveSize {
669	ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
670	ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
671	} PipeInterleaveSize;
672	typedef enum BankInterleaveSize {
673	ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
674	ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
675	ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
676	ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
677	} BankInterleaveSize;
678	typedef enum NumShaderEngines {
679	ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
680	ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
681	} NumShaderEngines;
682	typedef enum ShaderEngineTileSize {
683	ADDR_CONFIG_SE_TILE_16 = 0x0,
684	ADDR_CONFIG_SE_TILE_32 = 0x1,
685	} ShaderEngineTileSize;
686	typedef enum NumGPUs {
687	ADDR_CONFIG_1_GPU = 0x0,
688	ADDR_CONFIG_2_GPU = 0x1,
689	ADDR_CONFIG_4_GPU = 0x2,
690	} NumGPUs;
691	typedef enum MultiGPUTileSize {
692	ADDR_CONFIG_GPU_TILE_16 = 0x0,
693	ADDR_CONFIG_GPU_TILE_32 = 0x1,
694	ADDR_CONFIG_GPU_TILE_64 = 0x2,
695	ADDR_CONFIG_GPU_TILE_128 = 0x3,
696	} MultiGPUTileSize;
697	typedef enum RowSize {
698	ADDR_CONFIG_1KB_ROW = 0x0,
699	ADDR_CONFIG_2KB_ROW = 0x1,
700	ADDR_CONFIG_4KB_ROW = 0x2,
701	} RowSize;
702	typedef enum NumLowerPipes {
703	ADDR_CONFIG_1_LOWER_PIPES = 0x0,
704	ADDR_CONFIG_2_LOWER_PIPES = 0x1,
705	} NumLowerPipes;
706	typedef enum DebugBlockId {
707	DBG_CLIENT_BLKID_RESERVED = 0x0,
708	DBG_CLIENT_BLKID_dbg = 0x1,
709	DBG_CLIENT_BLKID_scf2 = 0x2,
710	DBG_CLIENT_BLKID_mcd5 = 0x3,
711	DBG_CLIENT_BLKID_vmc = 0x4,
712	DBG_CLIENT_BLKID_sx30 = 0x5,
713	DBG_CLIENT_BLKID_mcd2 = 0x6,
714	DBG_CLIENT_BLKID_bci1 = 0x7,
715	DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
716	DBG_CLIENT_BLKID_mcc0 = 0x9,
717	DBG_CLIENT_BLKID_uvdf_0 = 0xa,
718	DBG_CLIENT_BLKID_uvdf_1 = 0xb,
719	DBG_CLIENT_BLKID_uvdf_2 = 0xc,
720	DBG_CLIENT_BLKID_uvdi_0 = 0xd,
721	DBG_CLIENT_BLKID_bci0 = 0xe,
722	DBG_CLIENT_BLKID_vcec0_0 = 0xf,
723	DBG_CLIENT_BLKID_cb100 = 0x10,
724	DBG_CLIENT_BLKID_cb001 = 0x11,
725	DBG_CLIENT_BLKID_mcd4 = 0x12,
726	DBG_CLIENT_BLKID_tmonw00 = 0x13,
727	DBG_CLIENT_BLKID_cb101 = 0x14,
728	DBG_CLIENT_BLKID_sx10 = 0x15,
729	DBG_CLIENT_BLKID_cb301 = 0x16,
730	DBG_CLIENT_BLKID_tmonw01 = 0x17,
731	DBG_CLIENT_BLKID_vcea0_0 = 0x18,
732	DBG_CLIENT_BLKID_vcea0_1 = 0x19,
733	DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
734	DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
735	DBG_CLIENT_BLKID_scf1 = 0x1c,
736	DBG_CLIENT_BLKID_sx20 = 0x1d,
737	DBG_CLIENT_BLKID_spim1 = 0x1e,
738	DBG_CLIENT_BLKID_pa10 = 0x1f,
739	DBG_CLIENT_BLKID_pa00 = 0x20,
740	DBG_CLIENT_BLKID_gmcon = 0x21,
741	DBG_CLIENT_BLKID_mcb = 0x22,
742	DBG_CLIENT_BLKID_vgt0 = 0x23,
743	DBG_CLIENT_BLKID_pc0 = 0x24,
744	DBG_CLIENT_BLKID_bci2 = 0x25,
745	DBG_CLIENT_BLKID_uvdb_0 = 0x26,
746	DBG_CLIENT_BLKID_spim3 = 0x27,
747	DBG_CLIENT_BLKID_cpc_0 = 0x28,
748	DBG_CLIENT_BLKID_cpc_1 = 0x29,
749	DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
750	DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
751	DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
752	DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
753	DBG_CLIENT_BLKID_cb000 = 0x2e,
754	DBG_CLIENT_BLKID_spim0 = 0x2f,
755	DBG_CLIENT_BLKID_mcc2 = 0x30,
756	DBG_CLIENT_BLKID_ds0 = 0x31,
757	DBG_CLIENT_BLKID_srbm = 0x32,
758	DBG_CLIENT_BLKID_ih = 0x33,
759	DBG_CLIENT_BLKID_sem = 0x34,
760	DBG_CLIENT_BLKID_sdma_0 = 0x35,
761	DBG_CLIENT_BLKID_sdma_1 = 0x36,
762	DBG_CLIENT_BLKID_hdp = 0x37,
763	DBG_CLIENT_BLKID_acp_0 = 0x38,
764	DBG_CLIENT_BLKID_acp_1 = 0x39,
765	DBG_CLIENT_BLKID_cb200 = 0x3a,
766	DBG_CLIENT_BLKID_scf3 = 0x3b,
767	DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
768	DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
769	DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
770	DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
771	DBG_CLIENT_BLKID_vcea1_3 = 0x40,
772	DBG_CLIENT_BLKID_bci3 = 0x41,
773	DBG_CLIENT_BLKID_mcd0 = 0x42,
774	DBG_CLIENT_BLKID_pa11 = 0x43,
775	DBG_CLIENT_BLKID_pa01 = 0x44,
776	DBG_CLIENT_BLKID_cb201 = 0x45,
777	DBG_CLIENT_BLKID_spim2 = 0x46,
778	DBG_CLIENT_BLKID_vgt2 = 0x47,
779	DBG_CLIENT_BLKID_pc2 = 0x48,
780	DBG_CLIENT_BLKID_smu_0 = 0x49,
781	DBG_CLIENT_BLKID_smu_1 = 0x4a,
782	DBG_CLIENT_BLKID_smu_2 = 0x4b,
783	DBG_CLIENT_BLKID_cb1 = 0x4c,
784	DBG_CLIENT_BLKID_ia0 = 0x4d,
785	DBG_CLIENT_BLKID_wd = 0x4e,
786	DBG_CLIENT_BLKID_ia1 = 0x4f,
787	DBG_CLIENT_BLKID_vcec1_0 = 0x50,
788	DBG_CLIENT_BLKID_scf0 = 0x51,
789	DBG_CLIENT_BLKID_vgt1 = 0x52,
790	DBG_CLIENT_BLKID_pc1 = 0x53,
791	DBG_CLIENT_BLKID_cb0 = 0x54,
792	DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
793	DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
794	DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
795	DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
796	DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
797	DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
798	DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
799	DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
800	DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
801	DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
802	DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
803	DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
804	DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
805	DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
806	DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
807	DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
808	DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
809	DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
810	DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
811	DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
812	DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
813	DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
814	DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
815	DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
816	DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
817	DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
818	DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
819	DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
820	DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
821	DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
822	DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
823	DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
824	DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
825	DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
826	DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
827	DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
828	DBG_CLIENT_BLKID_vceb0_0 = 0x79,
829	DBG_CLIENT_BLKID_vgt3 = 0x7a,
830	DBG_CLIENT_BLKID_pc3 = 0x7b,
831	DBG_CLIENT_BLKID_mcd3 = 0x7c,
832	DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
833	DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
834	DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
835	DBG_CLIENT_BLKID_uvdu_3 = 0x80,
836	DBG_CLIENT_BLKID_uvdu_4 = 0x81,
837	DBG_CLIENT_BLKID_uvdu_5 = 0x82,
838	DBG_CLIENT_BLKID_uvdu_6 = 0x83,
839	DBG_CLIENT_BLKID_cb300 = 0x84,
840	DBG_CLIENT_BLKID_mcd1 = 0x85,
841	DBG_CLIENT_BLKID_sx00 = 0x86,
842	DBG_CLIENT_BLKID_uvdc_0 = 0x87,
843	DBG_CLIENT_BLKID_uvdc_1 = 0x88,
844	DBG_CLIENT_BLKID_mcc3 = 0x89,
845	DBG_CLIENT_BLKID_cpg_0 = 0x8a,
846	DBG_CLIENT_BLKID_cpg_1 = 0x8b,
847	DBG_CLIENT_BLKID_gck = 0x8c,
848	DBG_CLIENT_BLKID_mcc1 = 0x8d,
849	DBG_CLIENT_BLKID_cpf_0 = 0x8e,
850	DBG_CLIENT_BLKID_cpf_1 = 0x8f,
851	DBG_CLIENT_BLKID_rlc = 0x90,
852	DBG_CLIENT_BLKID_grbm = 0x91,
853	DBG_CLIENT_BLKID_sammsp = 0x92,
854	DBG_CLIENT_BLKID_dci_pg = 0x93,
855	DBG_CLIENT_BLKID_dci_0 = 0x94,
856	DBG_CLIENT_BLKID_dccg0_0 = 0x95,
857	DBG_CLIENT_BLKID_dccg0_1 = 0x96,
858	DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
859	DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
860	DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
861	DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
862	DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
863	DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
864	DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
865	} DebugBlockId;
866	typedef enum DebugBlockId_OLD {
867	DBG_BLOCK_ID_RESERVED = 0x0,
868	DBG_BLOCK_ID_DBG = 0x1,
869	DBG_BLOCK_ID_VMC = 0x2,
870	DBG_BLOCK_ID_PDMA = 0x3,
871	DBG_BLOCK_ID_CG = 0x4,
872	DBG_BLOCK_ID_SRBM = 0x5,
873	DBG_BLOCK_ID_GRBM = 0x6,
874	DBG_BLOCK_ID_RLC = 0x7,
875	DBG_BLOCK_ID_CSC = 0x8,
876	DBG_BLOCK_ID_SEM = 0x9,
877	DBG_BLOCK_ID_IH = 0xa,
878	DBG_BLOCK_ID_SC = 0xb,
879	DBG_BLOCK_ID_SQ = 0xc,
880	DBG_BLOCK_ID_AVP = 0xd,
881	DBG_BLOCK_ID_GMCON = 0xe,
882	DBG_BLOCK_ID_SMU = 0xf,
883	DBG_BLOCK_ID_DMA0 = 0x10,
884	DBG_BLOCK_ID_DMA1 = 0x11,
885	DBG_BLOCK_ID_SPIM = 0x12,
886	DBG_BLOCK_ID_GDS = 0x13,
887	DBG_BLOCK_ID_SPIS = 0x14,
888	DBG_BLOCK_ID_UNUSED0 = 0x15,
889	DBG_BLOCK_ID_PA0 = 0x16,
890	DBG_BLOCK_ID_PA1 = 0x17,
891	DBG_BLOCK_ID_CP0 = 0x18,
892	DBG_BLOCK_ID_CP1 = 0x19,
893	DBG_BLOCK_ID_CP2 = 0x1a,
894	DBG_BLOCK_ID_UNUSED1 = 0x1b,
895	DBG_BLOCK_ID_UVDU = 0x1c,
896	DBG_BLOCK_ID_UVDM = 0x1d,
897	DBG_BLOCK_ID_VCE = 0x1e,
898	DBG_BLOCK_ID_UNUSED2 = 0x1f,
899	DBG_BLOCK_ID_VGT0 = 0x20,
900	DBG_BLOCK_ID_VGT1 = 0x21,
901	DBG_BLOCK_ID_IA = 0x22,
902	DBG_BLOCK_ID_UNUSED3 = 0x23,
903	DBG_BLOCK_ID_SCT0 = 0x24,
904	DBG_BLOCK_ID_SCT1 = 0x25,
905	DBG_BLOCK_ID_SPM0 = 0x26,
906	DBG_BLOCK_ID_SPM1 = 0x27,
907	DBG_BLOCK_ID_TCAA = 0x28,
908	DBG_BLOCK_ID_TCAB = 0x29,
909	DBG_BLOCK_ID_TCCA = 0x2a,
910	DBG_BLOCK_ID_TCCB = 0x2b,
911	DBG_BLOCK_ID_MCC0 = 0x2c,
912	DBG_BLOCK_ID_MCC1 = 0x2d,
913	DBG_BLOCK_ID_MCC2 = 0x2e,
914	DBG_BLOCK_ID_MCC3 = 0x2f,
915	DBG_BLOCK_ID_SX0 = 0x30,
916	DBG_BLOCK_ID_SX1 = 0x31,
917	DBG_BLOCK_ID_SX2 = 0x32,
918	DBG_BLOCK_ID_SX3 = 0x33,
919	DBG_BLOCK_ID_UNUSED4 = 0x34,
920	DBG_BLOCK_ID_UNUSED5 = 0x35,
921	DBG_BLOCK_ID_UNUSED6 = 0x36,
922	DBG_BLOCK_ID_UNUSED7 = 0x37,
923	DBG_BLOCK_ID_PC0 = 0x38,
924	DBG_BLOCK_ID_PC1 = 0x39,
925	DBG_BLOCK_ID_UNUSED8 = 0x3a,
926	DBG_BLOCK_ID_UNUSED9 = 0x3b,
927	DBG_BLOCK_ID_UNUSED10 = 0x3c,
928	DBG_BLOCK_ID_UNUSED11 = 0x3d,
929	DBG_BLOCK_ID_MCB = 0x3e,
930	DBG_BLOCK_ID_UNUSED12 = 0x3f,
931	DBG_BLOCK_ID_SCB0 = 0x40,
932	DBG_BLOCK_ID_SCB1 = 0x41,
933	DBG_BLOCK_ID_UNUSED13 = 0x42,
934	DBG_BLOCK_ID_UNUSED14 = 0x43,
935	DBG_BLOCK_ID_SCF0 = 0x44,
936	DBG_BLOCK_ID_SCF1 = 0x45,
937	DBG_BLOCK_ID_UNUSED15 = 0x46,
938	DBG_BLOCK_ID_UNUSED16 = 0x47,
939	DBG_BLOCK_ID_BCI0 = 0x48,
940	DBG_BLOCK_ID_BCI1 = 0x49,
941	DBG_BLOCK_ID_BCI2 = 0x4a,
942	DBG_BLOCK_ID_BCI3 = 0x4b,
943	DBG_BLOCK_ID_UNUSED17 = 0x4c,
944	DBG_BLOCK_ID_UNUSED18 = 0x4d,
945	DBG_BLOCK_ID_UNUSED19 = 0x4e,
946	DBG_BLOCK_ID_UNUSED20 = 0x4f,
947	DBG_BLOCK_ID_CB00 = 0x50,
948	DBG_BLOCK_ID_CB01 = 0x51,
949	DBG_BLOCK_ID_CB02 = 0x52,
950	DBG_BLOCK_ID_CB03 = 0x53,
951	DBG_BLOCK_ID_CB04 = 0x54,
952	DBG_BLOCK_ID_UNUSED21 = 0x55,
953	DBG_BLOCK_ID_UNUSED22 = 0x56,
954	DBG_BLOCK_ID_UNUSED23 = 0x57,
955	DBG_BLOCK_ID_CB10 = 0x58,
956	DBG_BLOCK_ID_CB11 = 0x59,
957	DBG_BLOCK_ID_CB12 = 0x5a,
958	DBG_BLOCK_ID_CB13 = 0x5b,
959	DBG_BLOCK_ID_CB14 = 0x5c,
960	DBG_BLOCK_ID_UNUSED24 = 0x5d,
961	DBG_BLOCK_ID_UNUSED25 = 0x5e,
962	DBG_BLOCK_ID_UNUSED26 = 0x5f,
963	DBG_BLOCK_ID_TCP0 = 0x60,
964	DBG_BLOCK_ID_TCP1 = 0x61,
965	DBG_BLOCK_ID_TCP2 = 0x62,
966	DBG_BLOCK_ID_TCP3 = 0x63,
967	DBG_BLOCK_ID_TCP4 = 0x64,
968	DBG_BLOCK_ID_TCP5 = 0x65,
969	DBG_BLOCK_ID_TCP6 = 0x66,
970	DBG_BLOCK_ID_TCP7 = 0x67,
971	DBG_BLOCK_ID_TCP8 = 0x68,
972	DBG_BLOCK_ID_TCP9 = 0x69,
973	DBG_BLOCK_ID_TCP10 = 0x6a,
974	DBG_BLOCK_ID_TCP11 = 0x6b,
975	DBG_BLOCK_ID_TCP12 = 0x6c,
976	DBG_BLOCK_ID_TCP13 = 0x6d,
977	DBG_BLOCK_ID_TCP14 = 0x6e,
978	DBG_BLOCK_ID_TCP15 = 0x6f,
979	DBG_BLOCK_ID_TCP16 = 0x70,
980	DBG_BLOCK_ID_TCP17 = 0x71,
981	DBG_BLOCK_ID_TCP18 = 0x72,
982	DBG_BLOCK_ID_TCP19 = 0x73,
983	DBG_BLOCK_ID_TCP20 = 0x74,
984	DBG_BLOCK_ID_TCP21 = 0x75,
985	DBG_BLOCK_ID_TCP22 = 0x76,
986	DBG_BLOCK_ID_TCP23 = 0x77,
987	DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
988	DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
989	DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
990	DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
991	DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
992	DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
993	DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
994	DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
995	DBG_BLOCK_ID_DB00 = 0x80,
996	DBG_BLOCK_ID_DB01 = 0x81,
997	DBG_BLOCK_ID_DB02 = 0x82,
998	DBG_BLOCK_ID_DB03 = 0x83,
999	DBG_BLOCK_ID_DB04 = 0x84,
1000	DBG_BLOCK_ID_UNUSED27 = 0x85,
1001	DBG_BLOCK_ID_UNUSED28 = 0x86,
1002	DBG_BLOCK_ID_UNUSED29 = 0x87,
1003	DBG_BLOCK_ID_DB10 = 0x88,
1004	DBG_BLOCK_ID_DB11 = 0x89,
1005	DBG_BLOCK_ID_DB12 = 0x8a,
1006	DBG_BLOCK_ID_DB13 = 0x8b,
1007	DBG_BLOCK_ID_DB14 = 0x8c,
1008	DBG_BLOCK_ID_UNUSED30 = 0x8d,
1009	DBG_BLOCK_ID_UNUSED31 = 0x8e,
1010	DBG_BLOCK_ID_UNUSED32 = 0x8f,
1011	DBG_BLOCK_ID_TCC0 = 0x90,
1012	DBG_BLOCK_ID_TCC1 = 0x91,
1013	DBG_BLOCK_ID_TCC2 = 0x92,
1014	DBG_BLOCK_ID_TCC3 = 0x93,
1015	DBG_BLOCK_ID_TCC4 = 0x94,
1016	DBG_BLOCK_ID_TCC5 = 0x95,
1017	DBG_BLOCK_ID_TCC6 = 0x96,
1018	DBG_BLOCK_ID_TCC7 = 0x97,
1019	DBG_BLOCK_ID_SPS00 = 0x98,
1020	DBG_BLOCK_ID_SPS01 = 0x99,
1021	DBG_BLOCK_ID_SPS02 = 0x9a,
1022	DBG_BLOCK_ID_SPS10 = 0x9b,
1023	DBG_BLOCK_ID_SPS11 = 0x9c,
1024	DBG_BLOCK_ID_SPS12 = 0x9d,
1025	DBG_BLOCK_ID_UNUSED33 = 0x9e,
1026	DBG_BLOCK_ID_UNUSED34 = 0x9f,
1027	DBG_BLOCK_ID_TA00 = 0xa0,
1028	DBG_BLOCK_ID_TA01 = 0xa1,
1029	DBG_BLOCK_ID_TA02 = 0xa2,
1030	DBG_BLOCK_ID_TA03 = 0xa3,
1031	DBG_BLOCK_ID_TA04 = 0xa4,
1032	DBG_BLOCK_ID_TA05 = 0xa5,
1033	DBG_BLOCK_ID_TA06 = 0xa6,
1034	DBG_BLOCK_ID_TA07 = 0xa7,
1035	DBG_BLOCK_ID_TA08 = 0xa8,
1036	DBG_BLOCK_ID_TA09 = 0xa9,
1037	DBG_BLOCK_ID_TA0A = 0xaa,
1038	DBG_BLOCK_ID_TA0B = 0xab,
1039	DBG_BLOCK_ID_UNUSED35 = 0xac,
1040	DBG_BLOCK_ID_UNUSED36 = 0xad,
1041	DBG_BLOCK_ID_UNUSED37 = 0xae,
1042	DBG_BLOCK_ID_UNUSED38 = 0xaf,
1043	DBG_BLOCK_ID_TA10 = 0xb0,
1044	DBG_BLOCK_ID_TA11 = 0xb1,
1045	DBG_BLOCK_ID_TA12 = 0xb2,
1046	DBG_BLOCK_ID_TA13 = 0xb3,
1047	DBG_BLOCK_ID_TA14 = 0xb4,
1048	DBG_BLOCK_ID_TA15 = 0xb5,
1049	DBG_BLOCK_ID_TA16 = 0xb6,
1050	DBG_BLOCK_ID_TA17 = 0xb7,
1051	DBG_BLOCK_ID_TA18 = 0xb8,
1052	DBG_BLOCK_ID_TA19 = 0xb9,
1053	DBG_BLOCK_ID_TA1A = 0xba,
1054	DBG_BLOCK_ID_TA1B = 0xbb,
1055	DBG_BLOCK_ID_UNUSED39 = 0xbc,
1056	DBG_BLOCK_ID_UNUSED40 = 0xbd,
1057	DBG_BLOCK_ID_UNUSED41 = 0xbe,
1058	DBG_BLOCK_ID_UNUSED42 = 0xbf,
1059	DBG_BLOCK_ID_TD00 = 0xc0,
1060	DBG_BLOCK_ID_TD01 = 0xc1,
1061	DBG_BLOCK_ID_TD02 = 0xc2,
1062	DBG_BLOCK_ID_TD03 = 0xc3,
1063	DBG_BLOCK_ID_TD04 = 0xc4,
1064	DBG_BLOCK_ID_TD05 = 0xc5,
1065	DBG_BLOCK_ID_TD06 = 0xc6,
1066	DBG_BLOCK_ID_TD07 = 0xc7,
1067	DBG_BLOCK_ID_TD08 = 0xc8,
1068	DBG_BLOCK_ID_TD09 = 0xc9,
1069	DBG_BLOCK_ID_TD0A = 0xca,
1070	DBG_BLOCK_ID_TD0B = 0xcb,
1071	DBG_BLOCK_ID_UNUSED43 = 0xcc,
1072	DBG_BLOCK_ID_UNUSED44 = 0xcd,
1073	DBG_BLOCK_ID_UNUSED45 = 0xce,
1074	DBG_BLOCK_ID_UNUSED46 = 0xcf,
1075	DBG_BLOCK_ID_TD10 = 0xd0,
1076	DBG_BLOCK_ID_TD11 = 0xd1,
1077	DBG_BLOCK_ID_TD12 = 0xd2,
1078	DBG_BLOCK_ID_TD13 = 0xd3,
1079	DBG_BLOCK_ID_TD14 = 0xd4,
1080	DBG_BLOCK_ID_TD15 = 0xd5,
1081	DBG_BLOCK_ID_TD16 = 0xd6,
1082	DBG_BLOCK_ID_TD17 = 0xd7,
1083	DBG_BLOCK_ID_TD18 = 0xd8,
1084	DBG_BLOCK_ID_TD19 = 0xd9,
1085	DBG_BLOCK_ID_TD1A = 0xda,
1086	DBG_BLOCK_ID_TD1B = 0xdb,
1087	DBG_BLOCK_ID_UNUSED47 = 0xdc,
1088	DBG_BLOCK_ID_UNUSED48 = 0xdd,
1089	DBG_BLOCK_ID_UNUSED49 = 0xde,
1090	DBG_BLOCK_ID_UNUSED50 = 0xdf,
1091	DBG_BLOCK_ID_MCD0 = 0xe0,
1092	DBG_BLOCK_ID_MCD1 = 0xe1,
1093	DBG_BLOCK_ID_MCD2 = 0xe2,
1094	DBG_BLOCK_ID_MCD3 = 0xe3,
1095	DBG_BLOCK_ID_MCD4 = 0xe4,
1096	DBG_BLOCK_ID_MCD5 = 0xe5,
1097	DBG_BLOCK_ID_UNUSED51 = 0xe6,
1098	DBG_BLOCK_ID_UNUSED52 = 0xe7,
1099	} DebugBlockId_OLD;
1100	typedef enum DebugBlockId_BY2 {
1101	DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
1102	DBG_BLOCK_ID_VMC_BY2 = 0x1,
1103	DBG_BLOCK_ID_CG_BY2 = 0x2,
1104	DBG_BLOCK_ID_GRBM_BY2 = 0x3,
1105	DBG_BLOCK_ID_CSC_BY2 = 0x4,
1106	DBG_BLOCK_ID_IH_BY2 = 0x5,
1107	DBG_BLOCK_ID_SQ_BY2 = 0x6,
1108	DBG_BLOCK_ID_GMCON_BY2 = 0x7,
1109	DBG_BLOCK_ID_DMA0_BY2 = 0x8,
1110	DBG_BLOCK_ID_SPIM_BY2 = 0x9,
1111	DBG_BLOCK_ID_SPIS_BY2 = 0xa,
1112	DBG_BLOCK_ID_PA0_BY2 = 0xb,
1113	DBG_BLOCK_ID_CP0_BY2 = 0xc,
1114	DBG_BLOCK_ID_CP2_BY2 = 0xd,
1115	DBG_BLOCK_ID_UVDU_BY2 = 0xe,
1116	DBG_BLOCK_ID_VCE_BY2 = 0xf,
1117	DBG_BLOCK_ID_VGT0_BY2 = 0x10,
1118	DBG_BLOCK_ID_IA_BY2 = 0x11,
1119	DBG_BLOCK_ID_SCT0_BY2 = 0x12,
1120	DBG_BLOCK_ID_SPM0_BY2 = 0x13,
1121	DBG_BLOCK_ID_TCAA_BY2 = 0x14,
1122	DBG_BLOCK_ID_TCCA_BY2 = 0x15,
1123	DBG_BLOCK_ID_MCC0_BY2 = 0x16,
1124	DBG_BLOCK_ID_MCC2_BY2 = 0x17,
1125	DBG_BLOCK_ID_SX0_BY2 = 0x18,
1126	DBG_BLOCK_ID_SX2_BY2 = 0x19,
1127	DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
1128	DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
1129	DBG_BLOCK_ID_PC0_BY2 = 0x1c,
1130	DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
1131	DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
1132	DBG_BLOCK_ID_MCB_BY2 = 0x1f,
1133	DBG_BLOCK_ID_SCB0_BY2 = 0x20,
1134	DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
1135	DBG_BLOCK_ID_SCF0_BY2 = 0x22,
1136	DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
1137	DBG_BLOCK_ID_BCI0_BY2 = 0x24,
1138	DBG_BLOCK_ID_BCI2_BY2 = 0x25,
1139	DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
1140	DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
1141	DBG_BLOCK_ID_CB00_BY2 = 0x28,
1142	DBG_BLOCK_ID_CB02_BY2 = 0x29,
1143	DBG_BLOCK_ID_CB04_BY2 = 0x2a,
1144	DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
1145	DBG_BLOCK_ID_CB10_BY2 = 0x2c,
1146	DBG_BLOCK_ID_CB12_BY2 = 0x2d,
1147	DBG_BLOCK_ID_CB14_BY2 = 0x2e,
1148	DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
1149	DBG_BLOCK_ID_TCP0_BY2 = 0x30,
1150	DBG_BLOCK_ID_TCP2_BY2 = 0x31,
1151	DBG_BLOCK_ID_TCP4_BY2 = 0x32,
1152	DBG_BLOCK_ID_TCP6_BY2 = 0x33,
1153	DBG_BLOCK_ID_TCP8_BY2 = 0x34,
1154	DBG_BLOCK_ID_TCP10_BY2 = 0x35,
1155	DBG_BLOCK_ID_TCP12_BY2 = 0x36,
1156	DBG_BLOCK_ID_TCP14_BY2 = 0x37,
1157	DBG_BLOCK_ID_TCP16_BY2 = 0x38,
1158	DBG_BLOCK_ID_TCP18_BY2 = 0x39,
1159	DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
1160	DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
1161	DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
1162	DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
1163	DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
1164	DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
1165	DBG_BLOCK_ID_DB00_BY2 = 0x40,
1166	DBG_BLOCK_ID_DB02_BY2 = 0x41,
1167	DBG_BLOCK_ID_DB04_BY2 = 0x42,
1168	DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
1169	DBG_BLOCK_ID_DB10_BY2 = 0x44,
1170	DBG_BLOCK_ID_DB12_BY2 = 0x45,
1171	DBG_BLOCK_ID_DB14_BY2 = 0x46,
1172	DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
1173	DBG_BLOCK_ID_TCC0_BY2 = 0x48,
1174	DBG_BLOCK_ID_TCC2_BY2 = 0x49,
1175	DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
1176	DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
1177	DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
1178	DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
1179	DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
1180	DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
1181	DBG_BLOCK_ID_TA00_BY2 = 0x50,
1182	DBG_BLOCK_ID_TA02_BY2 = 0x51,
1183	DBG_BLOCK_ID_TA04_BY2 = 0x52,
1184	DBG_BLOCK_ID_TA06_BY2 = 0x53,
1185	DBG_BLOCK_ID_TA08_BY2 = 0x54,
1186	DBG_BLOCK_ID_TA0A_BY2 = 0x55,
1187	DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
1188	DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
1189	DBG_BLOCK_ID_TA10_BY2 = 0x58,
1190	DBG_BLOCK_ID_TA12_BY2 = 0x59,
1191	DBG_BLOCK_ID_TA14_BY2 = 0x5a,
1192	DBG_BLOCK_ID_TA16_BY2 = 0x5b,
1193	DBG_BLOCK_ID_TA18_BY2 = 0x5c,
1194	DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
1195	DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
1196	DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
1197	DBG_BLOCK_ID_TD00_BY2 = 0x60,
1198	DBG_BLOCK_ID_TD02_BY2 = 0x61,
1199	DBG_BLOCK_ID_TD04_BY2 = 0x62,
1200	DBG_BLOCK_ID_TD06_BY2 = 0x63,
1201	DBG_BLOCK_ID_TD08_BY2 = 0x64,
1202	DBG_BLOCK_ID_TD0A_BY2 = 0x65,
1203	DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
1204	DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
1205	DBG_BLOCK_ID_TD10_BY2 = 0x68,
1206	DBG_BLOCK_ID_TD12_BY2 = 0x69,
1207	DBG_BLOCK_ID_TD14_BY2 = 0x6a,
1208	DBG_BLOCK_ID_TD16_BY2 = 0x6b,
1209	DBG_BLOCK_ID_TD18_BY2 = 0x6c,
1210	DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
1211	DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
1212	DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
1213	DBG_BLOCK_ID_MCD0_BY2 = 0x70,
1214	DBG_BLOCK_ID_MCD2_BY2 = 0x71,
1215	DBG_BLOCK_ID_MCD4_BY2 = 0x72,
1216	DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
1217	} DebugBlockId_BY2;
1218	typedef enum DebugBlockId_BY4 {
1219	DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
1220	DBG_BLOCK_ID_CG_BY4 = 0x1,
1221	DBG_BLOCK_ID_CSC_BY4 = 0x2,
1222	DBG_BLOCK_ID_SQ_BY4 = 0x3,
1223	DBG_BLOCK_ID_DMA0_BY4 = 0x4,
1224	DBG_BLOCK_ID_SPIS_BY4 = 0x5,
1225	DBG_BLOCK_ID_CP0_BY4 = 0x6,
1226	DBG_BLOCK_ID_UVDU_BY4 = 0x7,
1227	DBG_BLOCK_ID_VGT0_BY4 = 0x8,
1228	DBG_BLOCK_ID_SCT0_BY4 = 0x9,
1229	DBG_BLOCK_ID_TCAA_BY4 = 0xa,
1230	DBG_BLOCK_ID_MCC0_BY4 = 0xb,
1231	DBG_BLOCK_ID_SX0_BY4 = 0xc,
1232	DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
1233	DBG_BLOCK_ID_PC0_BY4 = 0xe,
1234	DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
1235	DBG_BLOCK_ID_SCB0_BY4 = 0x10,
1236	DBG_BLOCK_ID_SCF0_BY4 = 0x11,
1237	DBG_BLOCK_ID_BCI0_BY4 = 0x12,
1238	DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
1239	DBG_BLOCK_ID_CB00_BY4 = 0x14,
1240	DBG_BLOCK_ID_CB04_BY4 = 0x15,
1241	DBG_BLOCK_ID_CB10_BY4 = 0x16,
1242	DBG_BLOCK_ID_CB14_BY4 = 0x17,
1243	DBG_BLOCK_ID_TCP0_BY4 = 0x18,
1244	DBG_BLOCK_ID_TCP4_BY4 = 0x19,
1245	DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
1246	DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
1247	DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
1248	DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
1249	DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
1250	DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
1251	DBG_BLOCK_ID_DB_BY4 = 0x20,
1252	DBG_BLOCK_ID_DB04_BY4 = 0x21,
1253	DBG_BLOCK_ID_DB10_BY4 = 0x22,
1254	DBG_BLOCK_ID_DB14_BY4 = 0x23,
1255	DBG_BLOCK_ID_TCC0_BY4 = 0x24,
1256	DBG_BLOCK_ID_TCC4_BY4 = 0x25,
1257	DBG_BLOCK_ID_SPS00_BY4 = 0x26,
1258	DBG_BLOCK_ID_SPS11_BY4 = 0x27,
1259	DBG_BLOCK_ID_TA00_BY4 = 0x28,
1260	DBG_BLOCK_ID_TA04_BY4 = 0x29,
1261	DBG_BLOCK_ID_TA08_BY4 = 0x2a,
1262	DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
1263	DBG_BLOCK_ID_TA10_BY4 = 0x2c,
1264	DBG_BLOCK_ID_TA14_BY4 = 0x2d,
1265	DBG_BLOCK_ID_TA18_BY4 = 0x2e,
1266	DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
1267	DBG_BLOCK_ID_TD00_BY4 = 0x30,
1268	DBG_BLOCK_ID_TD04_BY4 = 0x31,
1269	DBG_BLOCK_ID_TD08_BY4 = 0x32,
1270	DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
1271	DBG_BLOCK_ID_TD10_BY4 = 0x34,
1272	DBG_BLOCK_ID_TD14_BY4 = 0x35,
1273	DBG_BLOCK_ID_TD18_BY4 = 0x36,
1274	DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
1275	DBG_BLOCK_ID_MCD0_BY4 = 0x38,
1276	DBG_BLOCK_ID_MCD4_BY4 = 0x39,
1277	} DebugBlockId_BY4;
1278	typedef enum DebugBlockId_BY8 {
1279	DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
1280	DBG_BLOCK_ID_CSC_BY8 = 0x1,
1281	DBG_BLOCK_ID_DMA0_BY8 = 0x2,
1282	DBG_BLOCK_ID_CP0_BY8 = 0x3,
1283	DBG_BLOCK_ID_VGT0_BY8 = 0x4,
1284	DBG_BLOCK_ID_TCAA_BY8 = 0x5,
1285	DBG_BLOCK_ID_SX0_BY8 = 0x6,
1286	DBG_BLOCK_ID_PC0_BY8 = 0x7,
1287	DBG_BLOCK_ID_SCB0_BY8 = 0x8,
1288	DBG_BLOCK_ID_BCI0_BY8 = 0x9,
1289	DBG_BLOCK_ID_CB00_BY8 = 0xa,
1290	DBG_BLOCK_ID_CB10_BY8 = 0xb,
1291	DBG_BLOCK_ID_TCP0_BY8 = 0xc,
1292	DBG_BLOCK_ID_TCP8_BY8 = 0xd,
1293	DBG_BLOCK_ID_TCP16_BY8 = 0xe,
1294	DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
1295	DBG_BLOCK_ID_DB00_BY8 = 0x10,
1296	DBG_BLOCK_ID_DB10_BY8 = 0x11,
1297	DBG_BLOCK_ID_TCC0_BY8 = 0x12,
1298	DBG_BLOCK_ID_SPS00_BY8 = 0x13,
1299	DBG_BLOCK_ID_TA00_BY8 = 0x14,
1300	DBG_BLOCK_ID_TA08_BY8 = 0x15,
1301	DBG_BLOCK_ID_TA10_BY8 = 0x16,
1302	DBG_BLOCK_ID_TA18_BY8 = 0x17,
1303	DBG_BLOCK_ID_TD00_BY8 = 0x18,
1304	DBG_BLOCK_ID_TD08_BY8 = 0x19,
1305	DBG_BLOCK_ID_TD10_BY8 = 0x1a,
1306	DBG_BLOCK_ID_TD18_BY8 = 0x1b,
1307	DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
1308	} DebugBlockId_BY8;
1309	typedef enum DebugBlockId_BY16 {
1310	DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
1311	DBG_BLOCK_ID_DMA0_BY16 = 0x1,
1312	DBG_BLOCK_ID_VGT0_BY16 = 0x2,
1313	DBG_BLOCK_ID_SX0_BY16 = 0x3,
1314	DBG_BLOCK_ID_SCB0_BY16 = 0x4,
1315	DBG_BLOCK_ID_CB00_BY16 = 0x5,
1316	DBG_BLOCK_ID_TCP0_BY16 = 0x6,
1317	DBG_BLOCK_ID_TCP16_BY16 = 0x7,
1318	DBG_BLOCK_ID_DB00_BY16 = 0x8,
1319	DBG_BLOCK_ID_TCC0_BY16 = 0x9,
1320	DBG_BLOCK_ID_TA00_BY16 = 0xa,
1321	DBG_BLOCK_ID_TA10_BY16 = 0xb,
1322	DBG_BLOCK_ID_TD00_BY16 = 0xc,
1323	DBG_BLOCK_ID_TD10_BY16 = 0xd,
1324	DBG_BLOCK_ID_MCD0_BY16 = 0xe,
1325	} DebugBlockId_BY16;
1326	typedef enum ColorTransform {
1327	DCC_CT_AUTO = 0x0,
1328	DCC_CT_NONE = 0x1,
1329	ABGR_TO_A_BG_G_RB = 0x2,
1330	BGRA_TO_BG_G_RB_A = 0x3,
1331	} ColorTransform;
1332	typedef enum CompareRef {
1333	REF_NEVER = 0x0,
1334	REF_LESS = 0x1,
1335	REF_EQUAL = 0x2,
1336	REF_LEQUAL = 0x3,
1337	REF_GREATER = 0x4,
1338	REF_NOTEQUAL = 0x5,
1339	REF_GEQUAL = 0x6,
1340	REF_ALWAYS = 0x7,
1341	} CompareRef;
1342	typedef enum ReadSize {
1343	READ_256_BITS = 0x0,
1344	READ_512_BITS = 0x1,
1345	} ReadSize;
1346	typedef enum DepthFormat {
1347	DEPTH_INVALID = 0x0,
1348	DEPTH_16 = 0x1,
1349	DEPTH_X8_24 = 0x2,
1350	DEPTH_8_24 = 0x3,
1351	DEPTH_X8_24_FLOAT = 0x4,
1352	DEPTH_8_24_FLOAT = 0x5,
1353	DEPTH_32_FLOAT = 0x6,
1354	DEPTH_X24_8_32_FLOAT = 0x7,
1355	} DepthFormat;
1356	typedef enum ZFormat {
1357	Z_INVALID = 0x0,
1358	Z_16 = 0x1,
1359	Z_24 = 0x2,
1360	Z_32_FLOAT = 0x3,
1361	} ZFormat;
1362	typedef enum StencilFormat {
1363	STENCIL_INVALID = 0x0,
1364	STENCIL_8 = 0x1,
1365	} StencilFormat;
1366	typedef enum CmaskMode {
1367	CMASK_CLEAR_NONE = 0x0,
1368	CMASK_CLEAR_ONE = 0x1,
1369	CMASK_CLEAR_ALL = 0x2,
1370	CMASK_ANY_EXPANDED = 0x3,
1371	CMASK_ALPHA0_FRAG1 = 0x4,
1372	CMASK_ALPHA0_FRAG2 = 0x5,
1373	CMASK_ALPHA0_FRAG4 = 0x6,
1374	CMASK_ALPHA0_FRAGS = 0x7,
1375	CMASK_ALPHA1_FRAG1 = 0x8,
1376	CMASK_ALPHA1_FRAG2 = 0x9,
1377	CMASK_ALPHA1_FRAG4 = 0xa,
1378	CMASK_ALPHA1_FRAGS = 0xb,
1379	CMASK_ALPHAX_FRAG1 = 0xc,
1380	CMASK_ALPHAX_FRAG2 = 0xd,
1381	CMASK_ALPHAX_FRAG4 = 0xe,
1382	CMASK_ALPHAX_FRAGS = 0xf,
1383	} CmaskMode;
1384	typedef enum QuadExportFormat {
1385	EXPORT_UNUSED = 0x0,
1386	EXPORT_32_R = 0x1,
1387	EXPORT_32_GR = 0x2,
1388	EXPORT_32_AR = 0x3,
1389	EXPORT_FP16_ABGR = 0x4,
1390	EXPORT_UNSIGNED16_ABGR = 0x5,
1391	EXPORT_SIGNED16_ABGR = 0x6,
1392	EXPORT_32_ABGR = 0x7,
1393	} QuadExportFormat;
1394	typedef enum QuadExportFormatOld {
1395	EXPORT_4P_32BPC_ABGR = 0x0,
1396	EXPORT_4P_16BPC_ABGR = 0x1,
1397	EXPORT_4P_32BPC_GR = 0x2,
1398	EXPORT_4P_32BPC_AR = 0x3,
1399	EXPORT_2P_32BPC_ABGR = 0x4,
1400	EXPORT_8P_32BPC_R = 0x5,
1401	} QuadExportFormatOld;
1402	typedef enum ColorFormat {
1403	COLOR_INVALID = 0x0,
1404	COLOR_8 = 0x1,
1405	COLOR_16 = 0x2,
1406	COLOR_8_8 = 0x3,
1407	COLOR_32 = 0x4,
1408	COLOR_16_16 = 0x5,
1409	COLOR_10_11_11 = 0x6,
1410	COLOR_11_11_10 = 0x7,
1411	COLOR_10_10_10_2 = 0x8,
1412	COLOR_2_10_10_10 = 0x9,
1413	COLOR_8_8_8_8 = 0xa,
1414	COLOR_32_32 = 0xb,
1415	COLOR_16_16_16_16 = 0xc,
1416	COLOR_RESERVED_13 = 0xd,
1417	COLOR_32_32_32_32 = 0xe,
1418	COLOR_RESERVED_15 = 0xf,
1419	COLOR_5_6_5 = 0x10,
1420	COLOR_1_5_5_5 = 0x11,
1421	COLOR_5_5_5_1 = 0x12,
1422	COLOR_4_4_4_4 = 0x13,
1423	COLOR_8_24 = 0x14,
1424	COLOR_24_8 = 0x15,
1425	COLOR_X24_8_32_FLOAT = 0x16,
1426	COLOR_RESERVED_23 = 0x17,
1427	} ColorFormat;
1428	typedef enum SurfaceFormat {
1429	FMT_INVALID = 0x0,
1430	FMT_8 = 0x1,
1431	FMT_16 = 0x2,
1432	FMT_8_8 = 0x3,
1433	FMT_32 = 0x4,
1434	FMT_16_16 = 0x5,
1435	FMT_10_11_11 = 0x6,
1436	FMT_11_11_10 = 0x7,
1437	FMT_10_10_10_2 = 0x8,
1438	FMT_2_10_10_10 = 0x9,
1439	FMT_8_8_8_8 = 0xa,
1440	FMT_32_32 = 0xb,
1441	FMT_16_16_16_16 = 0xc,
1442	FMT_32_32_32 = 0xd,
1443	FMT_32_32_32_32 = 0xe,
1444	FMT_RESERVED_4 = 0xf,
1445	FMT_5_6_5 = 0x10,
1446	FMT_1_5_5_5 = 0x11,
1447	FMT_5_5_5_1 = 0x12,
1448	FMT_4_4_4_4 = 0x13,
1449	FMT_8_24 = 0x14,
1450	FMT_24_8 = 0x15,
1451	FMT_X24_8_32_FLOAT = 0x16,
1452	FMT_RESERVED_33 = 0x17,
1453	FMT_11_11_10_FLOAT = 0x18,
1454	FMT_16_FLOAT = 0x19,
1455	FMT_32_FLOAT = 0x1a,
1456	FMT_16_16_FLOAT = 0x1b,
1457	FMT_8_24_FLOAT = 0x1c,
1458	FMT_24_8_FLOAT = 0x1d,
1459	FMT_32_32_FLOAT = 0x1e,
1460	FMT_10_11_11_FLOAT = 0x1f,
1461	FMT_16_16_16_16_FLOAT = 0x20,
1462	FMT_3_3_2 = 0x21,
1463	FMT_6_5_5 = 0x22,
1464	FMT_32_32_32_32_FLOAT = 0x23,
1465	FMT_RESERVED_36 = 0x24,
1466	FMT_1 = 0x25,
1467	FMT_1_REVERSED = 0x26,
1468	FMT_GB_GR = 0x27,
1469	FMT_BG_RG = 0x28,
1470	FMT_32_AS_8 = 0x29,
1471	FMT_32_AS_8_8 = 0x2a,
1472	FMT_5_9_9_9_SHAREDEXP = 0x2b,
1473	FMT_8_8_8 = 0x2c,
1474	FMT_16_16_16 = 0x2d,
1475	FMT_16_16_16_FLOAT = 0x2e,
1476	FMT_4_4 = 0x2f,
1477	FMT_32_32_32_FLOAT = 0x30,
1478	FMT_BC1 = 0x31,
1479	FMT_BC2 = 0x32,
1480	FMT_BC3 = 0x33,
1481	FMT_BC4 = 0x34,
1482	FMT_BC5 = 0x35,
1483	FMT_BC6 = 0x36,
1484	FMT_BC7 = 0x37,
1485	FMT_32_AS_32_32_32_32 = 0x38,
1486	FMT_APC3 = 0x39,
1487	FMT_APC4 = 0x3a,
1488	FMT_APC5 = 0x3b,
1489	FMT_APC6 = 0x3c,
1490	FMT_APC7 = 0x3d,
1491	FMT_CTX1 = 0x3e,
1492	FMT_RESERVED_63 = 0x3f,
1493	} SurfaceFormat;
1494	typedef enum BUF_DATA_FORMAT {
1495	BUF_DATA_FORMAT_INVALID = 0x0,
1496	BUF_DATA_FORMAT_8 = 0x1,
1497	BUF_DATA_FORMAT_16 = 0x2,
1498	BUF_DATA_FORMAT_8_8 = 0x3,
1499	BUF_DATA_FORMAT_32 = 0x4,
1500	BUF_DATA_FORMAT_16_16 = 0x5,
1501	BUF_DATA_FORMAT_10_11_11 = 0x6,
1502	BUF_DATA_FORMAT_11_11_10 = 0x7,
1503	BUF_DATA_FORMAT_10_10_10_2 = 0x8,
1504	BUF_DATA_FORMAT_2_10_10_10 = 0x9,
1505	BUF_DATA_FORMAT_8_8_8_8 = 0xa,
1506	BUF_DATA_FORMAT_32_32 = 0xb,
1507	BUF_DATA_FORMAT_16_16_16_16 = 0xc,
1508	BUF_DATA_FORMAT_32_32_32 = 0xd,
1509	BUF_DATA_FORMAT_32_32_32_32 = 0xe,
1510	BUF_DATA_FORMAT_RESERVED_15 = 0xf,
1511	} BUF_DATA_FORMAT;
1512	typedef enum IMG_DATA_FORMAT {
1513	IMG_DATA_FORMAT_INVALID = 0x0,
1514	IMG_DATA_FORMAT_8 = 0x1,
1515	IMG_DATA_FORMAT_16 = 0x2,
1516	IMG_DATA_FORMAT_8_8 = 0x3,
1517	IMG_DATA_FORMAT_32 = 0x4,
1518	IMG_DATA_FORMAT_16_16 = 0x5,
1519	IMG_DATA_FORMAT_10_11_11 = 0x6,
1520	IMG_DATA_FORMAT_11_11_10 = 0x7,
1521	IMG_DATA_FORMAT_10_10_10_2 = 0x8,
1522	IMG_DATA_FORMAT_2_10_10_10 = 0x9,
1523	IMG_DATA_FORMAT_8_8_8_8 = 0xa,
1524	IMG_DATA_FORMAT_32_32 = 0xb,
1525	IMG_DATA_FORMAT_16_16_16_16 = 0xc,
1526	IMG_DATA_FORMAT_32_32_32 = 0xd,
1527	IMG_DATA_FORMAT_32_32_32_32 = 0xe,
1528	IMG_DATA_FORMAT_RESERVED_15 = 0xf,
1529	IMG_DATA_FORMAT_5_6_5 = 0x10,
1530	IMG_DATA_FORMAT_1_5_5_5 = 0x11,
1531	IMG_DATA_FORMAT_5_5_5_1 = 0x12,
1532	IMG_DATA_FORMAT_4_4_4_4 = 0x13,
1533	IMG_DATA_FORMAT_8_24 = 0x14,
1534	IMG_DATA_FORMAT_24_8 = 0x15,
1535	IMG_DATA_FORMAT_X24_8_32 = 0x16,
1536	IMG_DATA_FORMAT_RESERVED_23 = 0x17,
1537	IMG_DATA_FORMAT_RESERVED_24 = 0x18,
1538	IMG_DATA_FORMAT_RESERVED_25 = 0x19,
1539	IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
1540	IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
1541	IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
1542	IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
1543	IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
1544	IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
1545	IMG_DATA_FORMAT_GB_GR = 0x20,
1546	IMG_DATA_FORMAT_BG_RG = 0x21,
1547	IMG_DATA_FORMAT_5_9_9_9 = 0x22,
1548	IMG_DATA_FORMAT_BC1 = 0x23,
1549	IMG_DATA_FORMAT_BC2 = 0x24,
1550	IMG_DATA_FORMAT_BC3 = 0x25,
1551	IMG_DATA_FORMAT_BC4 = 0x26,
1552	IMG_DATA_FORMAT_BC5 = 0x27,
1553	IMG_DATA_FORMAT_BC6 = 0x28,
1554	IMG_DATA_FORMAT_BC7 = 0x29,
1555	IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
1556	IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
1557	IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
1558	IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
1559	IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
1560	IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
1561	IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
1562	IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
1563	IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
1564	IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
1565	IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
1566	IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
1567	IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
1568	IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
1569	IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
1570	IMG_DATA_FORMAT_4_4 = 0x39,
1571	IMG_DATA_FORMAT_6_5_5 = 0x3a,
1572	IMG_DATA_FORMAT_1 = 0x3b,
1573	IMG_DATA_FORMAT_1_REVERSED = 0x3c,
1574	IMG_DATA_FORMAT_32_AS_8 = 0x3d,
1575	IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
1576	IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
1577	} IMG_DATA_FORMAT;
1578	typedef enum BUF_NUM_FORMAT {
1579	BUF_NUM_FORMAT_UNORM = 0x0,
1580	BUF_NUM_FORMAT_SNORM = 0x1,
1581	BUF_NUM_FORMAT_USCALED = 0x2,
1582	BUF_NUM_FORMAT_SSCALED = 0x3,
1583	BUF_NUM_FORMAT_UINT = 0x4,
1584	BUF_NUM_FORMAT_SINT = 0x5,
1585	BUF_NUM_FORMAT_RESERVED_6 = 0x6,
1586	BUF_NUM_FORMAT_FLOAT = 0x7,
1587	} BUF_NUM_FORMAT;
1588	typedef enum IMG_NUM_FORMAT {
1589	IMG_NUM_FORMAT_UNORM = 0x0,
1590	IMG_NUM_FORMAT_SNORM = 0x1,
1591	IMG_NUM_FORMAT_USCALED = 0x2,
1592	IMG_NUM_FORMAT_SSCALED = 0x3,
1593	IMG_NUM_FORMAT_UINT = 0x4,
1594	IMG_NUM_FORMAT_SINT = 0x5,
1595	IMG_NUM_FORMAT_RESERVED_6 = 0x6,
1596	IMG_NUM_FORMAT_FLOAT = 0x7,
1597	IMG_NUM_FORMAT_RESERVED_8 = 0x8,
1598	IMG_NUM_FORMAT_SRGB = 0x9,
1599	IMG_NUM_FORMAT_RESERVED_10 = 0xa,
1600	IMG_NUM_FORMAT_RESERVED_11 = 0xb,
1601	IMG_NUM_FORMAT_RESERVED_12 = 0xc,
1602	IMG_NUM_FORMAT_RESERVED_13 = 0xd,
1603	IMG_NUM_FORMAT_RESERVED_14 = 0xe,
1604	IMG_NUM_FORMAT_RESERVED_15 = 0xf,
1605	} IMG_NUM_FORMAT;
1606	typedef enum TileType {
1607	ARRAY_COLOR_TILE = 0x0,
1608	ARRAY_DEPTH_TILE = 0x1,
1609	} TileType;
1610	typedef enum NonDispTilingOrder {
1611	ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
1612	ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
1613	} NonDispTilingOrder;
1614	typedef enum MicroTileMode {
1615	ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
1616	ADDR_SURF_THIN_MICRO_TILING = 0x1,
1617	ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1618	ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
1619	ADDR_SURF_THICK_MICRO_TILING = 0x4,
1620	} MicroTileMode;
1621	typedef enum TileSplit {
1622	ADDR_SURF_TILE_SPLIT_64B = 0x0,
1623	ADDR_SURF_TILE_SPLIT_128B = 0x1,
1624	ADDR_SURF_TILE_SPLIT_256B = 0x2,
1625	ADDR_SURF_TILE_SPLIT_512B = 0x3,
1626	ADDR_SURF_TILE_SPLIT_1KB = 0x4,
1627	ADDR_SURF_TILE_SPLIT_2KB = 0x5,
1628	ADDR_SURF_TILE_SPLIT_4KB = 0x6,
1629	} TileSplit;
1630	typedef enum SampleSplit {
1631	ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
1632	ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
1633	ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1634	ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
1635	} SampleSplit;
1636	typedef enum PipeConfig {
1637	ADDR_SURF_P2 = 0x0,
1638	ADDR_SURF_P2_RESERVED0 = 0x1,
1639	ADDR_SURF_P2_RESERVED1 = 0x2,
1640	ADDR_SURF_P2_RESERVED2 = 0x3,
1641	ADDR_SURF_P4_8x16 = 0x4,
1642	ADDR_SURF_P4_16x16 = 0x5,
1643	ADDR_SURF_P4_16x32 = 0x6,
1644	ADDR_SURF_P4_32x32 = 0x7,
1645	ADDR_SURF_P8_16x16_8x16 = 0x8,
1646	ADDR_SURF_P8_16x32_8x16 = 0x9,
1647	ADDR_SURF_P8_32x32_8x16 = 0xa,
1648	ADDR_SURF_P8_16x32_16x16 = 0xb,
1649	ADDR_SURF_P8_32x32_16x16 = 0xc,
1650	ADDR_SURF_P8_32x32_16x32 = 0xd,
1651	ADDR_SURF_P8_32x64_32x32 = 0xe,
1652	ADDR_SURF_P8_RESERVED0 = 0xf,
1653	ADDR_SURF_P16_32x32_8x16 = 0x10,
1654	ADDR_SURF_P16_32x32_16x16 = 0x11,
1655	} PipeConfig;
1656	typedef enum NumBanks {
1657	ADDR_SURF_2_BANK = 0x0,
1658	ADDR_SURF_4_BANK = 0x1,
1659	ADDR_SURF_8_BANK = 0x2,
1660	ADDR_SURF_16_BANK = 0x3,
1661	} NumBanks;
1662	typedef enum BankWidth {
1663	ADDR_SURF_BANK_WIDTH_1 = 0x0,
1664	ADDR_SURF_BANK_WIDTH_2 = 0x1,
1665	ADDR_SURF_BANK_WIDTH_4 = 0x2,
1666	ADDR_SURF_BANK_WIDTH_8 = 0x3,
1667	} BankWidth;
1668	typedef enum BankHeight {
1669	ADDR_SURF_BANK_HEIGHT_1 = 0x0,
1670	ADDR_SURF_BANK_HEIGHT_2 = 0x1,
1671	ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1672	ADDR_SURF_BANK_HEIGHT_8 = 0x3,
1673	} BankHeight;
1674	typedef enum BankWidthHeight {
1675	ADDR_SURF_BANK_WH_1 = 0x0,
1676	ADDR_SURF_BANK_WH_2 = 0x1,
1677	ADDR_SURF_BANK_WH_4 = 0x2,
1678	ADDR_SURF_BANK_WH_8 = 0x3,
1679	} BankWidthHeight;
1680	typedef enum MacroTileAspect {
1681	ADDR_SURF_MACRO_ASPECT_1 = 0x0,
1682	ADDR_SURF_MACRO_ASPECT_2 = 0x1,
1683	ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1684	ADDR_SURF_MACRO_ASPECT_8 = 0x3,
1685	} MacroTileAspect;
1686	typedef enum GATCL1RequestType {
1687	GATCL1_TYPE_NORMAL = 0x0,
1688	GATCL1_TYPE_SHOOTDOWN = 0x1,
1689	GATCL1_TYPE_BYPASS = 0x2,
1690	} GATCL1RequestType;
1691	typedef enum TCC_CACHE_POLICIES {
1692	TCC_CACHE_POLICY_LRU = 0x0,
1693	TCC_CACHE_POLICY_STREAM = 0x1,
1694	} TCC_CACHE_POLICIES;
1695	typedef enum MTYPE {
1696	MTYPE_NC_NV = 0x0,
1697	MTYPE_NC = 0x1,
1698	MTYPE_CC = 0x2,
1699	MTYPE_UC = 0x3,
1700	} MTYPE;
1701	typedef enum PERFMON_COUNTER_MODE {
1702	PERFMON_COUNTER_MODE_ACCUM = 0x0,
1703	PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
1704	PERFMON_COUNTER_MODE_MAX = 0x2,
1705	PERFMON_COUNTER_MODE_DIRTY = 0x3,
1706	PERFMON_COUNTER_MODE_SAMPLE = 0x4,
1707	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
1708	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
1709	PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
1710	PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
1711	PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
1712	PERFMON_COUNTER_MODE_RESERVED = 0xf,
1713	} PERFMON_COUNTER_MODE;
1714	typedef enum PERFMON_SPM_MODE {
1715	PERFMON_SPM_MODE_OFF = 0x0,
1716	PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
1717	PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1718	PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
1719	PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
1720	PERFMON_SPM_MODE_RESERVED_5 = 0x5,
1721	PERFMON_SPM_MODE_RESERVED_6 = 0x6,
1722	PERFMON_SPM_MODE_RESERVED_7 = 0x7,
1723	PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
1724	PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
1725	PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
1726	} PERFMON_SPM_MODE;
1727	typedef enum SurfaceTiling {
1728	ARRAY_LINEAR = 0x0,
1729	ARRAY_TILED = 0x1,
1730	} SurfaceTiling;
1731	typedef enum SurfaceArray {
1732	ARRAY_1D = 0x0,
1733	ARRAY_2D = 0x1,
1734	ARRAY_3D = 0x2,
1735	ARRAY_3D_SLICE = 0x3,
1736	} SurfaceArray;
1737	typedef enum ColorArray {
1738	ARRAY_2D_ALT_COLOR = 0x0,
1739	ARRAY_2D_COLOR = 0x1,
1740	ARRAY_3D_SLICE_COLOR = 0x3,
1741	} ColorArray;
1742	typedef enum DepthArray {
1743	ARRAY_2D_ALT_DEPTH = 0x0,
1744	ARRAY_2D_DEPTH = 0x1,
1745	} DepthArray;
1746	typedef enum ENUM_NUM_SIMD_PER_CU {
1747	NUM_SIMD_PER_CU = 0x4,
1748	} ENUM_NUM_SIMD_PER_CU;
1749	typedef enum MEM_PWR_FORCE_CTRL {
1750	NO_FORCE_REQUEST = 0x0,
1751	FORCE_LIGHT_SLEEP_REQUEST = 0x1,
1752	FORCE_DEEP_SLEEP_REQUEST = 0x2,
1753	FORCE_SHUT_DOWN_REQUEST = 0x3,
1754	} MEM_PWR_FORCE_CTRL;
1755	typedef enum MEM_PWR_FORCE_CTRL2 {
1756	NO_FORCE_REQ = 0x0,
1757	FORCE_LIGHT_SLEEP_REQ = 0x1,
1758	} MEM_PWR_FORCE_CTRL2;
1759	typedef enum MEM_PWR_DIS_CTRL {
1760	ENABLE_MEM_PWR_CTRL = 0x0,
1761	DISABLE_MEM_PWR_CTRL = 0x1,
1762	} MEM_PWR_DIS_CTRL;
1763	typedef enum MEM_PWR_SEL_CTRL {
1764	DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
1765	DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
1766	DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
1767	} MEM_PWR_SEL_CTRL;
1768	typedef enum MEM_PWR_SEL_CTRL2 {
1769	DYNAMIC_DEEP_SLEEP_EN = 0x0,
1770	DYNAMIC_LIGHT_SLEEP_EN = 0x1,
1771	} MEM_PWR_SEL_CTRL2;
1772
1773	#endif /* DCE_10_0_ENUM_H */
1774