1 | /* |
2 | * DCE_8_0 Register documentation |
3 | * |
4 | * Copyright (C) 2014 Advanced Micro Devices, Inc. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included |
14 | * in all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
22 | */ |
23 | |
24 | #ifndef DCE_8_0_SH_MASK_H |
25 | #define DCE_8_0_SH_MASK_H |
26 | |
27 | #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1 |
28 | #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0 |
29 | #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1 |
30 | #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0 |
31 | #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff |
32 | #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0 |
33 | #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000 |
34 | #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18 |
35 | #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000 |
36 | #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c |
37 | #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000 |
38 | #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x1d |
39 | #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000 |
40 | #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x1e |
41 | #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x1 |
42 | #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x0 |
43 | #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x1 |
44 | #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x0 |
45 | #define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0xffffff |
46 | #define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x0 |
47 | #define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS_MASK 0x3000000 |
48 | #define PIPE1_PG_STATUS__PIPE1_DEBUG_PWR_STATUS__SHIFT 0x18 |
49 | #define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000 |
50 | #define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x1c |
51 | #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000 |
52 | #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x1d |
53 | #define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000 |
54 | #define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x1e |
55 | #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x1 |
56 | #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x0 |
57 | #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x1 |
58 | #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x0 |
59 | #define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0xffffff |
60 | #define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x0 |
61 | #define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS_MASK 0x3000000 |
62 | #define PIPE2_PG_STATUS__PIPE2_DEBUG_PWR_STATUS__SHIFT 0x18 |
63 | #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000 |
64 | #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x1c |
65 | #define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000 |
66 | #define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x1d |
67 | #define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000 |
68 | #define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x1e |
69 | #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x1 |
70 | #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x0 |
71 | #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x1 |
72 | #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x0 |
73 | #define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0xffffff |
74 | #define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x0 |
75 | #define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS_MASK 0x3000000 |
76 | #define PIPE3_PG_STATUS__PIPE3_DEBUG_PWR_STATUS__SHIFT 0x18 |
77 | #define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000 |
78 | #define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x1c |
79 | #define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000 |
80 | #define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x1d |
81 | #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000 |
82 | #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e |
83 | #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x1 |
84 | #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x0 |
85 | #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x1 |
86 | #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x0 |
87 | #define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0xffffff |
88 | #define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x0 |
89 | #define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS_MASK 0x3000000 |
90 | #define PIPE4_PG_STATUS__PIPE4_DEBUG_PWR_STATUS__SHIFT 0x18 |
91 | #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000 |
92 | #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x1c |
93 | #define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000 |
94 | #define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x1d |
95 | #define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000 |
96 | #define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x1e |
97 | #define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x1 |
98 | #define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x0 |
99 | #define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x1 |
100 | #define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x0 |
101 | #define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0xffffff |
102 | #define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x0 |
103 | #define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS_MASK 0x3000000 |
104 | #define PIPE5_PG_STATUS__PIPE5_DEBUG_PWR_STATUS__SHIFT 0x18 |
105 | #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000 |
106 | #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x1c |
107 | #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000 |
108 | #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x1d |
109 | #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000 |
110 | #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x1e |
111 | #define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x1 |
112 | #define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 |
113 | #define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffff |
114 | #define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x0 |
115 | #define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffff |
116 | #define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x0 |
117 | #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x1 |
118 | #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x0 |
119 | #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x2 |
120 | #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x1 |
121 | #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x4 |
122 | #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x2 |
123 | #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000 |
124 | #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10 |
125 | #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0xff |
126 | #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x0 |
127 | #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x100 |
128 | #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
129 | #define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffff |
130 | #define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x0 |
131 | #define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x1ffff |
132 | #define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 |
133 | #define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x1ffff |
134 | #define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 |
135 | #define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x1ffff |
136 | #define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 |
137 | #define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x1ffff |
138 | #define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 |
139 | #define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x1ffff |
140 | #define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 |
141 | #define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x1ffff |
142 | #define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 |
143 | #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x1 |
144 | #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 |
145 | #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x2 |
146 | #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 |
147 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x4 |
148 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 |
149 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x8 |
150 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 |
151 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000 |
152 | #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 |
153 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x1 |
154 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
155 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 |
156 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
157 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 |
158 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
159 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 |
160 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
161 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
162 | #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
163 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x1 |
164 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x0 |
165 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x100 |
166 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x8 |
167 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x10000 |
168 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 |
169 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0xe0000 |
170 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x11 |
171 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 |
172 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 |
173 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 |
174 | #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f |
175 | #define DC_ABM1_CNTL__ABM1_EN_MASK 0x1 |
176 | #define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 |
177 | #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x700 |
178 | #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x8 |
179 | #define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000 |
180 | #define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x1f |
181 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0xf |
182 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 |
183 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0xf00 |
184 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x8 |
185 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0xf0000 |
186 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 |
187 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
188 | #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
189 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x7fff |
190 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x0 |
191 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x7ff0000 |
192 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 |
193 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000 |
194 | #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x1f |
195 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x7fff |
196 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x0 |
197 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x7ff0000 |
198 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 |
199 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000 |
200 | #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x1f |
201 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x7fff |
202 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x0 |
203 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x7ff0000 |
204 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 |
205 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000 |
206 | #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x1f |
207 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x7fff |
208 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x0 |
209 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x7ff0000 |
210 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 |
211 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000 |
212 | #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x1f |
213 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x7fff |
214 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x0 |
215 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x7ff0000 |
216 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 |
217 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000 |
218 | #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x1f |
219 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x3ff |
220 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x0 |
221 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x3ff0000 |
222 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x10 |
223 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000 |
224 | #define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x1f |
225 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x3ff |
226 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x0 |
227 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x3ff0000 |
228 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x10 |
229 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000 |
230 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c |
231 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000 |
232 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d |
233 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000 |
234 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e |
235 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000 |
236 | #define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x1f |
237 | #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x1 |
238 | #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 |
239 | #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x100 |
240 | #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 |
241 | #define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x1 |
242 | #define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x0 |
243 | #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x100 |
244 | #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x8 |
245 | #define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x10000 |
246 | #define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x10 |
247 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x1 |
248 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 |
249 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x2 |
250 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 |
251 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x4 |
252 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 |
253 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x100 |
254 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 |
255 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x200 |
256 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 |
257 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x400 |
258 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa |
259 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x10000 |
260 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 |
261 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x1000000 |
262 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 |
263 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000 |
264 | #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f |
265 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x3 |
266 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 |
267 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x100 |
268 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 |
269 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x1000 |
270 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0xc |
271 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x30000 |
272 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 |
273 | #define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x100000 |
274 | #define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 |
275 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x800000 |
276 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x17 |
277 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x7000000 |
278 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x18 |
279 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000 |
280 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x1c |
281 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000 |
282 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x1d |
283 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000 |
284 | #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x1e |
285 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
286 | #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
287 | #define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffff |
288 | #define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 |
289 | #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x3ff |
290 | #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 |
291 | #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x3ff0000 |
292 | #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 |
293 | #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x3ff |
294 | #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 |
295 | #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x3ff0000 |
296 | #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 |
297 | #define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0xffffff |
298 | #define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 |
299 | #define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0xffffff |
300 | #define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x0 |
301 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x3ff |
302 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 |
303 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x3ff0000 |
304 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 |
305 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
306 | #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
307 | #define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0xffffff |
308 | #define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 |
309 | #define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0xffffff |
310 | #define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 |
311 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x1 |
312 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
313 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 |
314 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
315 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 |
316 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
317 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 |
318 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
319 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
320 | #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
321 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x1 |
322 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 |
323 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x2 |
324 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x1 |
325 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0xff00 |
326 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 |
327 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0xff0000 |
328 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 |
329 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000 |
330 | #define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x1f |
331 | #define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffff |
332 | #define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 |
333 | #define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffff |
334 | #define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 |
335 | #define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffff |
336 | #define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 |
337 | #define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffff |
338 | #define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 |
339 | #define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffff |
340 | #define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 |
341 | #define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffff |
342 | #define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x0 |
343 | #define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffff |
344 | #define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x0 |
345 | #define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffff |
346 | #define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x0 |
347 | #define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffff |
348 | #define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x0 |
349 | #define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffff |
350 | #define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x0 |
351 | #define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffff |
352 | #define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x0 |
353 | #define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffff |
354 | #define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x0 |
355 | #define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffff |
356 | #define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x0 |
357 | #define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffff |
358 | #define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x0 |
359 | #define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffff |
360 | #define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x0 |
361 | #define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffff |
362 | #define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x0 |
363 | #define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffff |
364 | #define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x0 |
365 | #define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffff |
366 | #define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x0 |
367 | #define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffff |
368 | #define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x0 |
369 | #define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffff |
370 | #define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x0 |
371 | #define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffff |
372 | #define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x0 |
373 | #define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffff |
374 | #define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x0 |
375 | #define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffff |
376 | #define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x0 |
377 | #define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffff |
378 | #define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x0 |
379 | #define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffff |
380 | #define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x0 |
381 | #define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffff |
382 | #define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x0 |
383 | #define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffff |
384 | #define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x0 |
385 | #define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffff |
386 | #define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x0 |
387 | #define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffff |
388 | #define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x0 |
389 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x3ff |
390 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x0 |
391 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0xffc00 |
392 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0xa |
393 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000 |
394 | #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x14 |
395 | #define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000 |
396 | #define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f |
397 | #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0xff |
398 | #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x0 |
399 | #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x100 |
400 | #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
401 | #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffff |
402 | #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x0 |
403 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x10 |
404 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x4 |
405 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x100 |
406 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x8 |
407 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x1000 |
408 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0xc |
409 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000 |
410 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x18 |
411 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000 |
412 | #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x1f |
413 | #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x3ff |
414 | #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x0 |
415 | #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x10000 |
416 | #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x10 |
417 | #define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0xf |
418 | #define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x0 |
419 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS_MASK 0x1 |
420 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS__SHIFT 0x0 |
421 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_LIGHT_SLEEP_DIS_MASK 0x2 |
422 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_LIGHT_SLEEP_DIS__SHIFT 0x1 |
423 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS_MASK 0x4 |
424 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS__SHIFT 0x2 |
425 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS_MASK 0x8 |
426 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS__SHIFT 0x3 |
427 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS_MASK 0x10 |
428 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS__SHIFT 0x4 |
429 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS_MASK 0x20 |
430 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS__SHIFT 0x5 |
431 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS_MASK 0x40 |
432 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS__SHIFT 0x6 |
433 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE_MASK 0x300 |
434 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x8 |
435 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_MEM_PWR_STATE_MASK 0xc00 |
436 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR2_MEM_PWR_STATE__SHIFT 0xa |
437 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE_MASK 0x3000 |
438 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE__SHIFT 0xc |
439 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE_MASK 0xc000 |
440 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE__SHIFT 0xe |
441 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0_MASK 0x30000 |
442 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0__SHIFT 0x10 |
443 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE_MASK 0xc0000 |
444 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE__SHIFT 0x12 |
445 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE_MASK 0x300000 |
446 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE__SHIFT 0x14 |
447 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1_MASK 0xc00000 |
448 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1__SHIFT 0x16 |
449 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2_MASK 0x3000000 |
450 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2__SHIFT 0x18 |
451 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS_MASK 0x10000000 |
452 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS__SHIFT 0x1c |
453 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS_MASK 0x20000000 |
454 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS__SHIFT 0x1d |
455 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS_MASK 0x40000000 |
456 | #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS__SHIFT 0x1e |
457 | #define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x1fff |
458 | #define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x0 |
459 | #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x1fff |
460 | #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x0 |
461 | #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x1fff0000 |
462 | #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x10 |
463 | #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x1fff |
464 | #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x0 |
465 | #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x1fff0000 |
466 | #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x10 |
467 | #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x1 |
468 | #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x0 |
469 | #define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x10000 |
470 | #define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x10 |
471 | #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x20000 |
472 | #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x11 |
473 | #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x1fff |
474 | #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x0 |
475 | #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x1fff0000 |
476 | #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x10 |
477 | #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x1 |
478 | #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x0 |
479 | #define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x10000 |
480 | #define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x10 |
481 | #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x20000 |
482 | #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x11 |
483 | #define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x1fff |
484 | #define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x0 |
485 | #define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x1fff0000 |
486 | #define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x10 |
487 | #define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x1fff |
488 | #define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x0 |
489 | #define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x1fff |
490 | #define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x0 |
491 | #define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x1fff |
492 | #define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x0 |
493 | #define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x10000 |
494 | #define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x10 |
495 | #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x1 |
496 | #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x0 |
497 | #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x10 |
498 | #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x4 |
499 | #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x100 |
500 | #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x8 |
501 | #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x1000 |
502 | #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0xc |
503 | #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN_MASK 0x8000 |
504 | #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_EN__SHIFT 0xf |
505 | #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000 |
506 | #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 |
507 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x1 |
508 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x0 |
509 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x10 |
510 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x4 |
511 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x100 |
512 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x8 |
513 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x1000 |
514 | #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0xc |
515 | #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x1 |
516 | #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x0 |
517 | #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x10 |
518 | #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 |
519 | #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x1fff |
520 | #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x0 |
521 | #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x1fff0000 |
522 | #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x10 |
523 | #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x1fff |
524 | #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x0 |
525 | #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x1fff0000 |
526 | #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x10 |
527 | #define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x1 |
528 | #define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x0 |
529 | #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x1fff |
530 | #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x0 |
531 | #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x1fff0000 |
532 | #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x10 |
533 | #define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x1 |
534 | #define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x0 |
535 | #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x1 |
536 | #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x0 |
537 | #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x1e |
538 | #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x1 |
539 | #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x1fff |
540 | #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x0 |
541 | #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x1fff0000 |
542 | #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x10 |
543 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x1f |
544 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x0 |
545 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0xe0 |
546 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x5 |
547 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x100 |
548 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x8 |
549 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x200 |
550 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x9 |
551 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x400 |
552 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0xa |
553 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x800 |
554 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0xb |
555 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x3000 |
556 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0xc |
557 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 |
558 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 |
559 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x300000 |
560 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 |
561 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000 |
562 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x18 |
563 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000 |
564 | #define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x1f |
565 | #define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x1 |
566 | #define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x0 |
567 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x1f |
568 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x0 |
569 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0xe0 |
570 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x5 |
571 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x100 |
572 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x8 |
573 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x200 |
574 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x9 |
575 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x400 |
576 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0xa |
577 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x800 |
578 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0xb |
579 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x3000 |
580 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0xc |
581 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x30000 |
582 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x10 |
583 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x300000 |
584 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 |
585 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000 |
586 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x18 |
587 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000 |
588 | #define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x1f |
589 | #define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x1 |
590 | #define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x0 |
591 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x3 |
592 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x0 |
593 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x10 |
594 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 |
595 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x100 |
596 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 |
597 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x10000 |
598 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 |
599 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x1000000 |
600 | #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 |
601 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x1f |
602 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x0 |
603 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x100 |
604 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x8 |
605 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x10000 |
606 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x10 |
607 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x1000000 |
608 | #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x18 |
609 | #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x3 |
610 | #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 |
611 | #define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x1 |
612 | #define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x0 |
613 | #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x10 |
614 | #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x4 |
615 | #define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x300 |
616 | #define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x8 |
617 | #define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x1000 |
618 | #define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0xc |
619 | #define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x2000 |
620 | #define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0xd |
621 | #define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY_MASK 0x4000 |
622 | #define CRTC_CONTROL__CRTC_FIELD_NUMBER_POLARITY__SHIFT 0xe |
623 | #define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x10000 |
624 | #define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x10 |
625 | #define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x700000 |
626 | #define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x14 |
627 | #define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x1000000 |
628 | #define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x18 |
629 | #define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000 |
630 | #define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x1d |
631 | #define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x1 |
632 | #define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x0 |
633 | #define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x100 |
634 | #define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x8 |
635 | #define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x10000 |
636 | #define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x10 |
637 | #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x1 |
638 | #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x0 |
639 | #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x30000 |
640 | #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 |
641 | #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x1 |
642 | #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x0 |
643 | #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x2 |
644 | #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x1 |
645 | #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY_MASK 0x1 |
646 | #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_INDICATION_OUTPUT_POLARITY__SHIFT 0x0 |
647 | #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT_MASK 0x2 |
648 | #define CRTC_FIELD_INDICATION_CONTROL__CRTC_FIELD_ALIGNMENT__SHIFT 0x1 |
649 | #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB_MASK 0xfff |
650 | #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_BLUE_CB__SHIFT 0x0 |
651 | #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y_MASK 0xfff0000 |
652 | #define CRTC_PIXEL_DATA_READBACK0__CRTC_PIXEL_DATA_GREEN_Y__SHIFT 0x10 |
653 | #define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR_MASK 0xfff |
654 | #define CRTC_PIXEL_DATA_READBACK1__CRTC_PIXEL_DATA_RED_CR__SHIFT 0x0 |
655 | #define CRTC_STATUS__CRTC_V_BLANK_MASK 0x1 |
656 | #define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x0 |
657 | #define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x2 |
658 | #define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x1 |
659 | #define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x4 |
660 | #define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x2 |
661 | #define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x8 |
662 | #define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x3 |
663 | #define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x10 |
664 | #define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x4 |
665 | #define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x20 |
666 | #define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x5 |
667 | #define CRTC_STATUS__CRTC_H_BLANK_MASK 0x10000 |
668 | #define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x10 |
669 | #define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x20000 |
670 | #define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x11 |
671 | #define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x40000 |
672 | #define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x12 |
673 | #define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x1fff |
674 | #define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x0 |
675 | #define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x1fff0000 |
676 | #define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x10 |
677 | #define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x1fff |
678 | #define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x0 |
679 | #define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0xffffff |
680 | #define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x0 |
681 | #define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x1fffffff |
682 | #define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x0 |
683 | #define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x1fffffff |
684 | #define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x0 |
685 | #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x1 |
686 | #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x0 |
687 | #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x1e |
688 | #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x1 |
689 | #define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x1 |
690 | #define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x0 |
691 | #define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x1 |
692 | #define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 |
693 | #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x1 |
694 | #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 |
695 | #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x100 |
696 | #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 |
697 | #define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x30000 |
698 | #define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 |
699 | #define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x1 |
700 | #define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x0 |
701 | #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x100 |
702 | #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x8 |
703 | #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x10000 |
704 | #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x10 |
705 | #define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x3000000 |
706 | #define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 |
707 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x1fff |
708 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 |
709 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x8000 |
710 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf |
711 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x10000 |
712 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x10 |
713 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x1000000 |
714 | #define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x18 |
715 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x1 |
716 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x0 |
717 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x2 |
718 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x1 |
719 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x4 |
720 | #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 |
721 | #define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x3 |
722 | #define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 |
723 | #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x1fff |
724 | #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x0 |
725 | #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x1fff0000 |
726 | #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 |
727 | #define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0xffffff |
728 | #define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 |
729 | #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x1 |
730 | #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x0 |
731 | #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x100 |
732 | #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x8 |
733 | #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0xf0000 |
734 | #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x10 |
735 | #define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN_MASK 0x100000 |
736 | #define CRTC_START_LINE_CONTROL__CRTC_LEGACY_REQUESTOR_EN__SHIFT 0x14 |
737 | #define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000 |
738 | #define CRTC_START_LINE_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x1c |
739 | #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x1 |
740 | #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x0 |
741 | #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x2 |
742 | #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x1 |
743 | #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x10 |
744 | #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x4 |
745 | #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x20 |
746 | #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x5 |
747 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x100 |
748 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 |
749 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x200 |
750 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 |
751 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x10000 |
752 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 |
753 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x20000 |
754 | #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 |
755 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x1000000 |
756 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x18 |
757 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x2000000 |
758 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x19 |
759 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x4000000 |
760 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x1a |
761 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x8000000 |
762 | #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x1b |
763 | #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000 |
764 | #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x1c |
765 | #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000 |
766 | #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x1d |
767 | #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000 |
768 | #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e |
769 | #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000 |
770 | #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f |
771 | #define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x1 |
772 | #define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x0 |
773 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x1 |
774 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x0 |
775 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x100 |
776 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x8 |
777 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x10000 |
778 | #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x10 |
779 | #define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x1 |
780 | #define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x0 |
781 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x1 |
782 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x0 |
783 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x700 |
784 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x8 |
785 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x10000 |
786 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x10 |
787 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000 |
788 | #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x18 |
789 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0xf |
790 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x0 |
791 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0xf0 |
792 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x4 |
793 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0xf00 |
794 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x8 |
795 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0xf000 |
796 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0xc |
797 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000 |
798 | #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x10 |
799 | #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0xffff |
800 | #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x0 |
801 | #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x3f0000 |
802 | #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x10 |
803 | #define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x1 |
804 | #define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x0 |
805 | #define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x100 |
806 | #define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x8 |
807 | #define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x7 |
808 | #define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x0 |
809 | #define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x30000 |
810 | #define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x10 |
811 | #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x3 |
812 | #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x0 |
813 | #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00 |
814 | #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x8 |
815 | #define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0xff |
816 | #define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x0 |
817 | #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x1 |
818 | #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x0 |
819 | #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x10 |
820 | #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x4 |
821 | #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x10000 |
822 | #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x10 |
823 | #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x100000 |
824 | #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x14 |
825 | #define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x1 |
826 | #define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x0 |
827 | #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0xff |
828 | #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x0 |
829 | #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x10000 |
830 | #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x10 |
831 | #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x1 |
832 | #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x0 |
833 | #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x100 |
834 | #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x8 |
835 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x3ff |
836 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x0 |
837 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0xffc00 |
838 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0xa |
839 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000 |
840 | #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x14 |
841 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT_MASK 0x3 |
842 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_BLUE_EXT__SHIFT 0x0 |
843 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT_MASK 0x300 |
844 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_GREEN_EXT__SHIFT 0x8 |
845 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT_MASK 0x30000 |
846 | #define CRTC_OVERSCAN_COLOR_EXT__CRTC_OVERSCAN_COLOR_RED_EXT__SHIFT 0x10 |
847 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x3ff |
848 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x0 |
849 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0xffc00 |
850 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0xa |
851 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000 |
852 | #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x14 |
853 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT_MASK 0x3 |
854 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT__SHIFT 0x0 |
855 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT_MASK 0x300 |
856 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT__SHIFT 0x8 |
857 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT_MASK 0x30000 |
858 | #define CRTC_BLANK_DATA_COLOR_EXT__CRTC_BLANK_DATA_COLOR_RED_CR_EXT__SHIFT 0x10 |
859 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x3ff |
860 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x0 |
861 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0xffc00 |
862 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0xa |
863 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000 |
864 | #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x14 |
865 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT_MASK 0x3 |
866 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_B_CB_EXT__SHIFT 0x0 |
867 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT_MASK 0x300 |
868 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_G_Y_EXT__SHIFT 0x8 |
869 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT_MASK 0x30000 |
870 | #define CRTC_BLACK_COLOR_EXT__CRTC_BLACK_COLOR_R_CR_EXT__SHIFT 0x10 |
871 | #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START_MASK 0x1fff |
872 | #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 |
873 | #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END_MASK 0x1fff0000 |
874 | #define CRTC_VERTICAL_INTERRUPT0_POSITION__CRTC_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 |
875 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x10 |
876 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 |
877 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x100 |
878 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 |
879 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS_MASK 0x1000 |
880 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc |
881 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x10000 |
882 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 |
883 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK 0x100000 |
884 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 |
885 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x1000000 |
886 | #define CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 |
887 | #define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START_MASK 0x1fff |
888 | #define CRTC_VERTICAL_INTERRUPT1_POSITION__CRTC_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 |
889 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x100 |
890 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 |
891 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS_MASK 0x1000 |
892 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc |
893 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x10000 |
894 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 |
895 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR_MASK 0x100000 |
896 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 |
897 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x1000000 |
898 | #define CRTC_VERTICAL_INTERRUPT1_CONTROL__CRTC_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 |
899 | #define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START_MASK 0x1fff |
900 | #define CRTC_VERTICAL_INTERRUPT2_POSITION__CRTC_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 |
901 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x100 |
902 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 |
903 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS_MASK 0x1000 |
904 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc |
905 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x10000 |
906 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 |
907 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR_MASK 0x100000 |
908 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 |
909 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x1000000 |
910 | #define CRTC_VERTICAL_INTERRUPT2_CONTROL__CRTC_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 |
911 | #define CRTC_CRC_CNTL__CRTC_CRC_EN_MASK 0x1 |
912 | #define CRTC_CRC_CNTL__CRTC_CRC_EN__SHIFT 0x0 |
913 | #define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN_MASK 0x10 |
914 | #define CRTC_CRC_CNTL__CRTC_CRC_CONT_EN__SHIFT 0x4 |
915 | #define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE_MASK 0x300 |
916 | #define CRTC_CRC_CNTL__CRTC_CRC_STEREO_MODE__SHIFT 0x8 |
917 | #define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE_MASK 0x3000 |
918 | #define CRTC_CRC_CNTL__CRTC_CRC_INTERLACE_MODE__SHIFT 0xc |
919 | #define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 |
920 | #define CRTC_CRC_CNTL__CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 |
921 | #define CRTC_CRC_CNTL__CRTC_CRC0_SELECT_MASK 0x700000 |
922 | #define CRTC_CRC_CNTL__CRTC_CRC0_SELECT__SHIFT 0x14 |
923 | #define CRTC_CRC_CNTL__CRTC_CRC1_SELECT_MASK 0x7000000 |
924 | #define CRTC_CRC_CNTL__CRTC_CRC1_SELECT__SHIFT 0x18 |
925 | #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START_MASK 0x1fff |
926 | #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_START__SHIFT 0x0 |
927 | #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END_MASK 0x1fff0000 |
928 | #define CRTC_CRC0_WINDOWA_X_CONTROL__CRTC_CRC0_WINDOWA_X_END__SHIFT 0x10 |
929 | #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START_MASK 0x1fff |
930 | #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_START__SHIFT 0x0 |
931 | #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END_MASK 0x1fff0000 |
932 | #define CRTC_CRC0_WINDOWA_Y_CONTROL__CRTC_CRC0_WINDOWA_Y_END__SHIFT 0x10 |
933 | #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START_MASK 0x1fff |
934 | #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_START__SHIFT 0x0 |
935 | #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END_MASK 0x1fff0000 |
936 | #define CRTC_CRC0_WINDOWB_X_CONTROL__CRTC_CRC0_WINDOWB_X_END__SHIFT 0x10 |
937 | #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START_MASK 0x1fff |
938 | #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_START__SHIFT 0x0 |
939 | #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END_MASK 0x1fff0000 |
940 | #define CRTC_CRC0_WINDOWB_Y_CONTROL__CRTC_CRC0_WINDOWB_Y_END__SHIFT 0x10 |
941 | #define CRTC_CRC0_DATA_RG__CRC0_R_CR_MASK 0xffff |
942 | #define CRTC_CRC0_DATA_RG__CRC0_R_CR__SHIFT 0x0 |
943 | #define CRTC_CRC0_DATA_RG__CRC0_G_Y_MASK 0xffff0000 |
944 | #define CRTC_CRC0_DATA_RG__CRC0_G_Y__SHIFT 0x10 |
945 | #define CRTC_CRC0_DATA_B__CRC0_B_CB_MASK 0xffff |
946 | #define CRTC_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 |
947 | #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START_MASK 0x1fff |
948 | #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_START__SHIFT 0x0 |
949 | #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END_MASK 0x1fff0000 |
950 | #define CRTC_CRC1_WINDOWA_X_CONTROL__CRTC_CRC1_WINDOWA_X_END__SHIFT 0x10 |
951 | #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START_MASK 0x1fff |
952 | #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_START__SHIFT 0x0 |
953 | #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END_MASK 0x1fff0000 |
954 | #define CRTC_CRC1_WINDOWA_Y_CONTROL__CRTC_CRC1_WINDOWA_Y_END__SHIFT 0x10 |
955 | #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START_MASK 0x1fff |
956 | #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_START__SHIFT 0x0 |
957 | #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END_MASK 0x1fff0000 |
958 | #define CRTC_CRC1_WINDOWB_X_CONTROL__CRTC_CRC1_WINDOWB_X_END__SHIFT 0x10 |
959 | #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START_MASK 0x1fff |
960 | #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_START__SHIFT 0x0 |
961 | #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END_MASK 0x1fff0000 |
962 | #define CRTC_CRC1_WINDOWB_Y_CONTROL__CRTC_CRC1_WINDOWB_Y_END__SHIFT 0x10 |
963 | #define CRTC_CRC1_DATA_RG__CRC1_R_CR_MASK 0xffff |
964 | #define CRTC_CRC1_DATA_RG__CRC1_R_CR__SHIFT 0x0 |
965 | #define CRTC_CRC1_DATA_RG__CRC1_G_Y_MASK 0xffff0000 |
966 | #define CRTC_CRC1_DATA_RG__CRC1_G_Y__SHIFT 0x10 |
967 | #define CRTC_CRC1_DATA_B__CRC1_B_CB_MASK 0xffff |
968 | #define CRTC_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 |
969 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE_MASK 0x3 |
970 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_ENABLE__SHIFT 0x0 |
971 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_MASK 0x8 |
972 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE__SHIFT 0x3 |
973 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_MASK 0x10 |
974 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE__SHIFT 0x4 |
975 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_MASK 0x60 |
976 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW__SHIFT 0x5 |
977 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE_MASK 0x100 |
978 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE__SHIFT 0x8 |
979 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE_MASK 0x200 |
980 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE__SHIFT 0x9 |
981 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY_MASK 0x1000 |
982 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY__SHIFT 0xc |
983 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY_MASK 0x2000 |
984 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY__SHIFT 0xd |
985 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE_MASK 0x4000 |
986 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_INTERLACE_MODE__SHIFT 0xe |
987 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE_MASK 0x7000000 |
988 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE__SHIFT 0x18 |
989 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE_MASK 0x70000000 |
990 | #define CRTC_EXT_TIMING_SYNC_CONTROL__CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE__SHIFT 0x1c |
991 | #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X_MASK 0x1fff |
992 | #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_X__SHIFT 0x0 |
993 | #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y_MASK 0x1fff0000 |
994 | #define CRTC_EXT_TIMING_SYNC_WINDOW_START__CRTC_EXT_TIMING_SYNC_WINDOW_START_Y__SHIFT 0x10 |
995 | #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X_MASK 0x1fff |
996 | #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_X__SHIFT 0x0 |
997 | #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y_MASK 0x1fff0000 |
998 | #define CRTC_EXT_TIMING_SYNC_WINDOW_END__CRTC_EXT_TIMING_SYNC_WINDOW_END_Y__SHIFT 0x10 |
999 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE_MASK 0x1 |
1000 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE__SHIFT 0x0 |
1001 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS_MASK 0x10 |
1002 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_STATUS__SHIFT 0x4 |
1003 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS_MASK 0x100 |
1004 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS__SHIFT 0x8 |
1005 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR_MASK 0x10000 |
1006 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_CLEAR__SHIFT 0x10 |
1007 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE_MASK 0x100000 |
1008 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE__SHIFT 0x14 |
1009 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_MASK 0xe0000000 |
1010 | #define CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT__SHIFT 0x1d |
1011 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE_MASK 0x1 |
1012 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_ENABLE__SHIFT 0x0 |
1013 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS_MASK 0x10 |
1014 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_STATUS__SHIFT 0x4 |
1015 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS_MASK 0x100 |
1016 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_STATUS__SHIFT 0x8 |
1017 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR_MASK 0x10000 |
1018 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_CLEAR__SHIFT 0x10 |
1019 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE_MASK 0x100000 |
1020 | #define CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_INT_TYPE__SHIFT 0x14 |
1021 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_MASK 0x1 |
1022 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE__SHIFT 0x0 |
1023 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS_MASK 0x10 |
1024 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS__SHIFT 0x4 |
1025 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS_MASK 0x100 |
1026 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS__SHIFT 0x8 |
1027 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR_MASK 0x10000 |
1028 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR__SHIFT 0x10 |
1029 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_MASK 0x100000 |
1030 | #define CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL__CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE__SHIFT 0x14 |
1031 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK_MASK 0xffff |
1032 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 |
1033 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT_MASK 0xff0000 |
1034 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 |
1035 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE_MASK 0x1000000 |
1036 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_ENABLE__SHIFT 0x18 |
1037 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS_MASK 0x2000000 |
1038 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_SS_STATUS__SHIFT 0x19 |
1039 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS_MASK 0x4000000 |
1040 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_STATUS__SHIFT 0x1a |
1041 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR_MASK 0x8000000 |
1042 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_CLEAR__SHIFT 0x1b |
1043 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE_MASK 0x10000000 |
1044 | #define CRTC_STATIC_SCREEN_CONTROL__CRTC_CPU_SS_INT_TYPE__SHIFT 0x1c |
1045 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x1 |
1046 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x0 |
1047 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x10 |
1048 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x4 |
1049 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x300 |
1050 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 |
1051 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x1000 |
1052 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc |
1053 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x10000 |
1054 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 |
1055 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x20000 |
1056 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 |
1057 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0xc0000 |
1058 | #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x12 |
1059 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0xff |
1060 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 |
1061 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0xff00 |
1062 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 |
1063 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x10000 |
1064 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 |
1065 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x60000 |
1066 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x11 |
1067 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x80000 |
1068 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 |
1069 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x100000 |
1070 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 |
1071 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x800000 |
1072 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 |
1073 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000 |
1074 | #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x18 |
1075 | #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x1fff |
1076 | #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x0 |
1077 | #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x1fff0000 |
1078 | #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x10 |
1079 | #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x1fff |
1080 | #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x0 |
1081 | #define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x1f0000 |
1082 | #define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x10 |
1083 | #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000 |
1084 | #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c |
1085 | #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0xff |
1086 | #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x0 |
1087 | #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x100 |
1088 | #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
1089 | #define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffff |
1090 | #define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x0 |
1091 | #define DAC_ENABLE__DAC_ENABLE_MASK 0x1 |
1092 | #define DAC_ENABLE__DAC_ENABLE__SHIFT 0x0 |
1093 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x2 |
1094 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x1 |
1095 | #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0xc |
1096 | #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x2 |
1097 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x10 |
1098 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x4 |
1099 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x20 |
1100 | #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x5 |
1101 | #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x100 |
1102 | #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x8 |
1103 | #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x7 |
1104 | #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x0 |
1105 | #define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x8 |
1106 | #define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x3 |
1107 | #define DAC_CRC_EN__DAC_CRC_EN_MASK 0x1 |
1108 | #define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x0 |
1109 | #define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x10000 |
1110 | #define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x10 |
1111 | #define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x1 |
1112 | #define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x0 |
1113 | #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb_MASK 0x100 |
1114 | #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb__SHIFT 0x8 |
1115 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x3ff |
1116 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x0 |
1117 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0xffc00 |
1118 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0xa |
1119 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000 |
1120 | #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x14 |
1121 | #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x3f |
1122 | #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x0 |
1123 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x3ff |
1124 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x0 |
1125 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0xffc00 |
1126 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0xa |
1127 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000 |
1128 | #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x14 |
1129 | #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x3f |
1130 | #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x0 |
1131 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x1 |
1132 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x0 |
1133 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x100 |
1134 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x8 |
1135 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x10000 |
1136 | #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x10 |
1137 | #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x7 |
1138 | #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x0 |
1139 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x3 |
1140 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x0 |
1141 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0xff00 |
1142 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x8 |
1143 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x70000 |
1144 | #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x10 |
1145 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0xff |
1146 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x0 |
1147 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x100 |
1148 | #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x8 |
1149 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0xff |
1150 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x0 |
1151 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0xff00 |
1152 | #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x8 |
1153 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x1 |
1154 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x0 |
1155 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x10 |
1156 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x4 |
1157 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x300 |
1158 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x8 |
1159 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x30000 |
1160 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x10 |
1161 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x3000000 |
1162 | #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x18 |
1163 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x1 |
1164 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x0 |
1165 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x10000 |
1166 | #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x10 |
1167 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x1 |
1168 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x0 |
1169 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x700 |
1170 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x8 |
1171 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x1000000 |
1172 | #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x18 |
1173 | #define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x3ff |
1174 | #define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x0 |
1175 | #define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x1 |
1176 | #define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x0 |
1177 | #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x100 |
1178 | #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x8 |
1179 | #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x10000 |
1180 | #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x10 |
1181 | #define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x1000000 |
1182 | #define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x18 |
1183 | #define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x1 |
1184 | #define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x0 |
1185 | #define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x100 |
1186 | #define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x8 |
1187 | #define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x10000 |
1188 | #define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x10 |
1189 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x1 |
1190 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x0 |
1191 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x100 |
1192 | #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x8 |
1193 | #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x10000 |
1194 | #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x10 |
1195 | #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x20000 |
1196 | #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x11 |
1197 | #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x40000 |
1198 | #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x12 |
1199 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x1 |
1200 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x0 |
1201 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x2 |
1202 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x1 |
1203 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x4 |
1204 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x2 |
1205 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x8 |
1206 | #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x3 |
1207 | #define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x3 |
1208 | #define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x0 |
1209 | #define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x30000 |
1210 | #define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x10 |
1211 | #define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffff |
1212 | #define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x0 |
1213 | #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 |
1214 | #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
1215 | #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0xfc |
1216 | #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
1217 | #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 |
1218 | #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
1219 | #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 |
1220 | #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
1221 | #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 |
1222 | #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
1223 | #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000 |
1224 | #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x1d |
1225 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 |
1226 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
1227 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 |
1228 | #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
1229 | #define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x1ff |
1230 | #define PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 |
1231 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x3000 |
1232 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc |
1233 | #define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x4000 |
1234 | #define PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xe |
1235 | #define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x8000 |
1236 | #define PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0xf |
1237 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL_MASK 0x1f0000 |
1238 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x10 |
1239 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x200000 |
1240 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x15 |
1241 | #define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x400000 |
1242 | #define PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x16 |
1243 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x800000 |
1244 | #define PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x17 |
1245 | #define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x1000000 |
1246 | #define PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x18 |
1247 | #define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x2000000 |
1248 | #define PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x19 |
1249 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xe0000000 |
1250 | #define PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d |
1251 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x3 |
1252 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 |
1253 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x4 |
1254 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 |
1255 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x30 |
1256 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 |
1257 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x40 |
1258 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 |
1259 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x300 |
1260 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 |
1261 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x400 |
1262 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa |
1263 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x3000 |
1264 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc |
1265 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x4000 |
1266 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe |
1267 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x30000 |
1268 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 |
1269 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x40000 |
1270 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 |
1271 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x300000 |
1272 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 |
1273 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x400000 |
1274 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 |
1275 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x3000000 |
1276 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 |
1277 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x4000000 |
1278 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a |
1279 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000 |
1280 | #define PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c |
1281 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000 |
1282 | #define PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e |
1283 | #define PERFMON_CNTL__PERFMON_STATE_MASK 0x3 |
1284 | #define PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
1285 | #define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL_MASK 0xf0 |
1286 | #define PERFMON_CNTL__PERFMON_RUN_ENABLE_SEL__SHIFT 0x4 |
1287 | #define PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0xfffff00 |
1288 | #define PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 |
1289 | #define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000 |
1290 | #define PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c |
1291 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000 |
1292 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d |
1293 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000 |
1294 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e |
1295 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000 |
1296 | #define PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f |
1297 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x1 |
1298 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 |
1299 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x2 |
1300 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 |
1301 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x4 |
1302 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 |
1303 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x8 |
1304 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 |
1305 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x10 |
1306 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 |
1307 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x20 |
1308 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 |
1309 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x40 |
1310 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 |
1311 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x80 |
1312 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 |
1313 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x100 |
1314 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 |
1315 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x200 |
1316 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 |
1317 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x400 |
1318 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa |
1319 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x800 |
1320 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb |
1321 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x1000 |
1322 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc |
1323 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x2000 |
1324 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd |
1325 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x4000 |
1326 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe |
1327 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x8000 |
1328 | #define PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf |
1329 | #define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xffff0000 |
1330 | #define PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 |
1331 | #define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xffffffff |
1332 | #define PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 |
1333 | #define PERFMON_HI__PERFMON_HI_MASK 0xffff |
1334 | #define PERFMON_HI__PERFMON_HI__SHIFT 0x0 |
1335 | #define PERFMON_HI__PERFMON_READ_SEL_MASK 0xe0000000 |
1336 | #define PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d |
1337 | #define PERFMON_LOW__PERFMON_LOW_MASK 0xffffffff |
1338 | #define PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 |
1339 | #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX_MASK 0xff |
1340 | #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_INDEX__SHIFT 0x0 |
1341 | #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN_MASK 0x100 |
1342 | #define PERFMON_TEST_DEBUG_INDEX__PERFMON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
1343 | #define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA_MASK 0xffffffff |
1344 | #define PERFMON_TEST_DEBUG_DATA__PERFMON_TEST_DEBUG_DATA__SHIFT 0x0 |
1345 | #define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x3ff |
1346 | #define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x0 |
1347 | #define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x3ff |
1348 | #define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x0 |
1349 | #define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x3ff |
1350 | #define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x0 |
1351 | #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0xf |
1352 | #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x0 |
1353 | #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 |
1354 | #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 |
1355 | #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x7ff0000 |
1356 | #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x10 |
1357 | #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0xf |
1358 | #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x0 |
1359 | #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 |
1360 | #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 |
1361 | #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x7ff0000 |
1362 | #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x10 |
1363 | #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0xf |
1364 | #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x0 |
1365 | #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x30 |
1366 | #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 |
1367 | #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x7ff0000 |
1368 | #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x10 |
1369 | #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f |
1370 | #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 |
1371 | #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 |
1372 | #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 |
1373 | #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 |
1374 | #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x10 |
1375 | #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x7f |
1376 | #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 |
1377 | #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 |
1378 | #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 |
1379 | #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 |
1380 | #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x10 |
1381 | #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x7f |
1382 | #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x0 |
1383 | #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x7f00 |
1384 | #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x8 |
1385 | #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x7f0000 |
1386 | #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x10 |
1387 | #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x1f |
1388 | #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x0 |
1389 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x60 |
1390 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x5 |
1391 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0xf00 |
1392 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x8 |
1393 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x1ff000 |
1394 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0xc |
1395 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000 |
1396 | #define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x18 |
1397 | #define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x1f |
1398 | #define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x0 |
1399 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x60 |
1400 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x5 |
1401 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0xf00 |
1402 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x8 |
1403 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x1ff000 |
1404 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0xc |
1405 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000 |
1406 | #define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x18 |
1407 | #define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x1f |
1408 | #define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x0 |
1409 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x60 |
1410 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x5 |
1411 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0xf00 |
1412 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x8 |
1413 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x1ff000 |
1414 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0xc |
1415 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000 |
1416 | #define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x18 |
1417 | #define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x7 |
1418 | #define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 |
1419 | #define DPREFCLK_CNTL__DPREFCLK_CLOCK_EN_MASK 0x10 |
1420 | #define DPREFCLK_CNTL__DPREFCLK_CLOCK_EN__SHIFT 0x4 |
1421 | #define SCANIN_SOFT_RESET__SCANIN_SOFT_RESET_MASK 0x1 |
1422 | #define SCANIN_SOFT_RESET__SCANIN_SOFT_RESET__SHIFT 0x0 |
1423 | #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x1 |
1424 | #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x0 |
1425 | #define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK 0xffffffff |
1426 | #define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT 0x0 |
1427 | #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffff |
1428 | #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x0 |
1429 | #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffff |
1430 | #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x0 |
1431 | #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK 0xffffffff |
1432 | #define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT 0x0 |
1433 | #define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK 0xffffffff |
1434 | #define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT 0x0 |
1435 | #define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK 0x1 |
1436 | #define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT 0x0 |
1437 | #define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK 0x100 |
1438 | #define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT 0x8 |
1439 | #define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK 0x200 |
1440 | #define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT 0x9 |
1441 | #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK 0x30000 |
1442 | #define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 |
1443 | #define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK 0x1000000 |
1444 | #define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT 0x18 |
1445 | #define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK 0x2000000 |
1446 | #define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT 0x19 |
1447 | #define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK 0xffffffff |
1448 | #define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT 0x0 |
1449 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE_MASK 0x1 |
1450 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_ENABLE__SHIFT 0x0 |
1451 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE_MASK 0x1ff0 |
1452 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_VALUE__SHIFT 0x4 |
1453 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED_MASK 0x10000 |
1454 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED__SHIFT 0x10 |
1455 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR_MASK 0x20000 |
1456 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_DEBUG_COUNT_TRIG_CLEAR__SHIFT 0x11 |
1457 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE_MASK 0x100000 |
1458 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_ENABLE__SHIFT 0x14 |
1459 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL_MASK 0x200000 |
1460 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_SRC_SEL__SHIFT 0x15 |
1461 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT_MASK 0xff000000 |
1462 | #define DCCG_DS_DEBUG_CNTL__DCCG_DS_JITTER_COUNT__SHIFT 0x18 |
1463 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT_MASK 0x1 |
1464 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_INT__SHIFT 0x0 |
1465 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS_MASK 0xffff0000 |
1466 | #define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_STATIC_SCREEN_STATUS__SHIFT 0x10 |
1467 | #define SMU_CONTROL__DISPLAY0_FORCE_VBI_MASK 0x1 |
1468 | #define SMU_CONTROL__DISPLAY0_FORCE_VBI__SHIFT 0x0 |
1469 | #define SMU_CONTROL__DISPLAY1_FORCE_VBI_MASK 0x2 |
1470 | #define SMU_CONTROL__DISPLAY1_FORCE_VBI__SHIFT 0x1 |
1471 | #define SMU_CONTROL__DISPLAY2_FORCE_VBI_MASK 0x4 |
1472 | #define SMU_CONTROL__DISPLAY2_FORCE_VBI__SHIFT 0x2 |
1473 | #define SMU_CONTROL__DISPLAY3_FORCE_VBI_MASK 0x8 |
1474 | #define SMU_CONTROL__DISPLAY3_FORCE_VBI__SHIFT 0x3 |
1475 | #define SMU_CONTROL__DISPLAY4_FORCE_VBI_MASK 0x10 |
1476 | #define SMU_CONTROL__DISPLAY4_FORCE_VBI__SHIFT 0x4 |
1477 | #define SMU_CONTROL__DISPLAY5_FORCE_VBI_MASK 0x20 |
1478 | #define SMU_CONTROL__DISPLAY5_FORCE_VBI__SHIFT 0x5 |
1479 | #define SMU_CONTROL__SMU_DC_INT_CLEAR_MASK 0x10000 |
1480 | #define SMU_CONTROL__SMU_DC_INT_CLEAR__SHIFT 0x10 |
1481 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x1 |
1482 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 |
1483 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x10 |
1484 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 |
1485 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xffff0000 |
1486 | #define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 |
1487 | #define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x1 |
1488 | #define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x0 |
1489 | #define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x10 |
1490 | #define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x4 |
1491 | #define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x1 |
1492 | #define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x0 |
1493 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x1 |
1494 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 |
1495 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x2 |
1496 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 |
1497 | #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x4 |
1498 | #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x2 |
1499 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x8 |
1500 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 |
1501 | #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x10 |
1502 | #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 |
1503 | #define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x20 |
1504 | #define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x5 |
1505 | #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x40 |
1506 | #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 |
1507 | #define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE_MASK 0x100 |
1508 | #define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE__SHIFT 0x8 |
1509 | #define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE_MASK 0x200 |
1510 | #define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE__SHIFT 0x9 |
1511 | #define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE_MASK 0x400 |
1512 | #define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE__SHIFT 0xa |
1513 | #define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK 0x800 |
1514 | #define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE__SHIFT 0xb |
1515 | #define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE_MASK 0x1000 |
1516 | #define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE__SHIFT 0xc |
1517 | #define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE_MASK 0x2000 |
1518 | #define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE__SHIFT 0xd |
1519 | #define DCCG_GATE_DISABLE_CNTL__SYMCLKG_GATE_DISABLE_MASK 0x4000 |
1520 | #define DCCG_GATE_DISABLE_CNTL__SYMCLKG_GATE_DISABLE__SHIFT 0xe |
1521 | #define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x10000 |
1522 | #define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x10 |
1523 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x20000 |
1524 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 |
1525 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x40000 |
1526 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 |
1527 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x80000 |
1528 | #define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 |
1529 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x100000 |
1530 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x14 |
1531 | #define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE_MASK 0x200000 |
1532 | #define DCCG_GATE_DISABLE_CNTL__AUDIO_DTO2_CLK_GATE_DISABLE__SHIFT 0x15 |
1533 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK 0x400000 |
1534 | #define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT 0x16 |
1535 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID_MASK 0x7000000 |
1536 | #define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID__SHIFT 0x18 |
1537 | #define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID_MASK 0x70000000 |
1538 | #define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID__SHIFT 0x1c |
1539 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0xf |
1540 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 |
1541 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0xff0 |
1542 | #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 |
1543 | #define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE_MASK 0x1000 |
1544 | #define DISPCLK_CGTT_BLK_CTRL_REG__CGTT_DISPCLK_OVERRIDE__SHIFT 0xc |
1545 | #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0xf |
1546 | #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x0 |
1547 | #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0xff0 |
1548 | #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x4 |
1549 | #define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE_MASK 0x1000 |
1550 | #define SCLK_CGTT_BLK_CTRL_REG__CGTT_SCLK_OVERRIDE__SHIFT 0xc |
1551 | #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffff |
1552 | #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 |
1553 | #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x1 |
1554 | #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x0 |
1555 | #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x30 |
1556 | #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x4 |
1557 | #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x1 |
1558 | #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x0 |
1559 | #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x30 |
1560 | #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x4 |
1561 | #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x1 |
1562 | #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x0 |
1563 | #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x30 |
1564 | #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x4 |
1565 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x7f |
1566 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 |
1567 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x7f00 |
1568 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 |
1569 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x10000 |
1570 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 |
1571 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x20000 |
1572 | #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 |
1573 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 |
1574 | #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 |
1575 | #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x100 |
1576 | #define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 |
1577 | #define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x1 |
1578 | #define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x0 |
1579 | #define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0xf0 |
1580 | #define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x4 |
1581 | #define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x1 |
1582 | #define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x0 |
1583 | #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x2 |
1584 | #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x1 |
1585 | #define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x10 |
1586 | #define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x4 |
1587 | #define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x20 |
1588 | #define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x5 |
1589 | #define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x100 |
1590 | #define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x8 |
1591 | #define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x200 |
1592 | #define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x9 |
1593 | #define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x1000 |
1594 | #define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0xc |
1595 | #define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x2000 |
1596 | #define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0xd |
1597 | #define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x10000 |
1598 | #define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x10 |
1599 | #define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x20000 |
1600 | #define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x11 |
1601 | #define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x100000 |
1602 | #define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x14 |
1603 | #define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x200000 |
1604 | #define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x15 |
1605 | #define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK 0x1000000 |
1606 | #define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT 0x18 |
1607 | #define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK 0x2000000 |
1608 | #define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT 0x19 |
1609 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x1ffff |
1610 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 |
1611 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x100000 |
1612 | #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 |
1613 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x3fff |
1614 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 |
1615 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0xf0000 |
1616 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 |
1617 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x100000 |
1618 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 |
1619 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0xe000000 |
1620 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x19 |
1621 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000 |
1622 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x1c |
1623 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000 |
1624 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d |
1625 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000 |
1626 | #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e |
1627 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000 |
1628 | #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f |
1629 | #define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS_MASK 0x1 |
1630 | #define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS__SHIFT 0x0 |
1631 | #define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS_MASK 0x100 |
1632 | #define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS__SHIFT 0x8 |
1633 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x1 |
1634 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 |
1635 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x2 |
1636 | #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 |
1637 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x4 |
1638 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 |
1639 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x8 |
1640 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 |
1641 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x10 |
1642 | #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 |
1643 | #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x20 |
1644 | #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 |
1645 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x40 |
1646 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 |
1647 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x80 |
1648 | #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 |
1649 | #define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x700 |
1650 | #define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x8 |
1651 | #define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK 0xfffff800 |
1652 | #define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT 0xb |
1653 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x3 |
1654 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x0 |
1655 | #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x10 |
1656 | #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 |
1657 | #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x20 |
1658 | #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 |
1659 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x100 |
1660 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x8 |
1661 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x200 |
1662 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x9 |
1663 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0xc000 |
1664 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0xe |
1665 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
1666 | #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
1667 | #define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffff |
1668 | #define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 |
1669 | #define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffff |
1670 | #define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 |
1671 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x3 |
1672 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x0 |
1673 | #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x10 |
1674 | #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 |
1675 | #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x20 |
1676 | #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 |
1677 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x100 |
1678 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x8 |
1679 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x200 |
1680 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x9 |
1681 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0xc000 |
1682 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0xe |
1683 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
1684 | #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
1685 | #define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffff |
1686 | #define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 |
1687 | #define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffff |
1688 | #define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 |
1689 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x3 |
1690 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x0 |
1691 | #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x10 |
1692 | #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 |
1693 | #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x20 |
1694 | #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 |
1695 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x100 |
1696 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x8 |
1697 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x200 |
1698 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x9 |
1699 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0xc000 |
1700 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0xe |
1701 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
1702 | #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
1703 | #define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffff |
1704 | #define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 |
1705 | #define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffff |
1706 | #define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 |
1707 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x3 |
1708 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x0 |
1709 | #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x10 |
1710 | #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 |
1711 | #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x20 |
1712 | #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 |
1713 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x100 |
1714 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x8 |
1715 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x200 |
1716 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x9 |
1717 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0xc000 |
1718 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0xe |
1719 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
1720 | #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
1721 | #define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffff |
1722 | #define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 |
1723 | #define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffff |
1724 | #define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 |
1725 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x3 |
1726 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x0 |
1727 | #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x10 |
1728 | #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x4 |
1729 | #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE_MASK 0x20 |
1730 | #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_DS_DISABLE__SHIFT 0x5 |
1731 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x100 |
1732 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x8 |
1733 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x200 |
1734 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x9 |
1735 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0xc000 |
1736 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0xe |
1737 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
1738 | #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
1739 | #define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffff |
1740 | #define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x0 |
1741 | #define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffff |
1742 | #define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x0 |
1743 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x3 |
1744 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x0 |
1745 | #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x10 |
1746 | #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x4 |
1747 | #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE_MASK 0x20 |
1748 | #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_DS_DISABLE__SHIFT 0x5 |
1749 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x100 |
1750 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x8 |
1751 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x200 |
1752 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x9 |
1753 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0xc000 |
1754 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0xe |
1755 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0xfff0000 |
1756 | #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x10 |
1757 | #define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffff |
1758 | #define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x0 |
1759 | #define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffff |
1760 | #define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x0 |
1761 | #define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET_MASK 0x1 |
1762 | #define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET__SHIFT 0x0 |
1763 | #define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET_MASK 0x2 |
1764 | #define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET__SHIFT 0x1 |
1765 | #define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET_MASK 0x4 |
1766 | #define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET__SHIFT 0x2 |
1767 | #define DCFE0_SOFT_RESET__SCL0_SOFT_RESET_MASK 0x8 |
1768 | #define DCFE0_SOFT_RESET__SCL0_SOFT_RESET__SHIFT 0x3 |
1769 | #define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET_MASK 0x10 |
1770 | #define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET__SHIFT 0x4 |
1771 | #define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET_MASK 0x1 |
1772 | #define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET__SHIFT 0x0 |
1773 | #define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET_MASK 0x2 |
1774 | #define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET__SHIFT 0x1 |
1775 | #define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET_MASK 0x4 |
1776 | #define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET__SHIFT 0x2 |
1777 | #define DCFE1_SOFT_RESET__SCL1_SOFT_RESET_MASK 0x8 |
1778 | #define DCFE1_SOFT_RESET__SCL1_SOFT_RESET__SHIFT 0x3 |
1779 | #define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET_MASK 0x10 |
1780 | #define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET__SHIFT 0x4 |
1781 | #define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET_MASK 0x1 |
1782 | #define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET__SHIFT 0x0 |
1783 | #define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET_MASK 0x2 |
1784 | #define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET__SHIFT 0x1 |
1785 | #define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET_MASK 0x4 |
1786 | #define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET__SHIFT 0x2 |
1787 | #define DCFE2_SOFT_RESET__SCL2_SOFT_RESET_MASK 0x8 |
1788 | #define DCFE2_SOFT_RESET__SCL2_SOFT_RESET__SHIFT 0x3 |
1789 | #define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET_MASK 0x10 |
1790 | #define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET__SHIFT 0x4 |
1791 | #define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET_MASK 0x1 |
1792 | #define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET__SHIFT 0x0 |
1793 | #define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET_MASK 0x2 |
1794 | #define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET__SHIFT 0x1 |
1795 | #define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET_MASK 0x4 |
1796 | #define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET__SHIFT 0x2 |
1797 | #define DCFE3_SOFT_RESET__SCL3_SOFT_RESET_MASK 0x8 |
1798 | #define DCFE3_SOFT_RESET__SCL3_SOFT_RESET__SHIFT 0x3 |
1799 | #define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET_MASK 0x10 |
1800 | #define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET__SHIFT 0x4 |
1801 | #define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET_MASK 0x1 |
1802 | #define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET__SHIFT 0x0 |
1803 | #define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET_MASK 0x2 |
1804 | #define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET__SHIFT 0x1 |
1805 | #define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET_MASK 0x4 |
1806 | #define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET__SHIFT 0x2 |
1807 | #define DCFE4_SOFT_RESET__SCL4_SOFT_RESET_MASK 0x8 |
1808 | #define DCFE4_SOFT_RESET__SCL4_SOFT_RESET__SHIFT 0x3 |
1809 | #define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET_MASK 0x10 |
1810 | #define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET__SHIFT 0x4 |
1811 | #define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET_MASK 0x1 |
1812 | #define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET__SHIFT 0x0 |
1813 | #define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET_MASK 0x2 |
1814 | #define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET__SHIFT 0x1 |
1815 | #define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET_MASK 0x4 |
1816 | #define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET__SHIFT 0x2 |
1817 | #define DCFE5_SOFT_RESET__SCL5_SOFT_RESET_MASK 0x8 |
1818 | #define DCFE5_SOFT_RESET__SCL5_SOFT_RESET__SHIFT 0x3 |
1819 | #define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET_MASK 0x10 |
1820 | #define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET__SHIFT 0x4 |
1821 | #define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x1 |
1822 | #define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x0 |
1823 | #define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x2 |
1824 | #define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x1 |
1825 | #define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x4 |
1826 | #define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x2 |
1827 | #define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x8 |
1828 | #define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x3 |
1829 | #define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x10 |
1830 | #define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x4 |
1831 | #define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x20 |
1832 | #define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x5 |
1833 | #define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x40 |
1834 | #define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x6 |
1835 | #define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x80 |
1836 | #define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x7 |
1837 | #define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x100 |
1838 | #define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x8 |
1839 | #define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x200 |
1840 | #define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x9 |
1841 | #define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x1000 |
1842 | #define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0xc |
1843 | #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x1 |
1844 | #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 |
1845 | #define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x10 |
1846 | #define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 |
1847 | #define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x100 |
1848 | #define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 |
1849 | #define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x1000 |
1850 | #define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc |
1851 | #define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x2000 |
1852 | #define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd |
1853 | #define DCCG_SOFT_RESET__CASCADED_AMCLK0_SOFT_RESET_MASK 0x4000 |
1854 | #define DCCG_SOFT_RESET__CASCADED_AMCLK0_SOFT_RESET__SHIFT 0xe |
1855 | #define DCCG_SOFT_RESET__CASCADED_AMCLK1_SOFT_RESET_MASK 0x8000 |
1856 | #define DCCG_SOFT_RESET__CASCADED_AMCLK1_SOFT_RESET__SHIFT 0xf |
1857 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x1 |
1858 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 |
1859 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x10 |
1860 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x4 |
1861 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x700 |
1862 | #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x8 |
1863 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x1 |
1864 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 |
1865 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x10 |
1866 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x4 |
1867 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x700 |
1868 | #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x8 |
1869 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x1 |
1870 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 |
1871 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x10 |
1872 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x4 |
1873 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x700 |
1874 | #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x8 |
1875 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x1 |
1876 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 |
1877 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x10 |
1878 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x4 |
1879 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x700 |
1880 | #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x8 |
1881 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x1 |
1882 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 |
1883 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x10 |
1884 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x4 |
1885 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x700 |
1886 | #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x8 |
1887 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x1 |
1888 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x0 |
1889 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x10 |
1890 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x4 |
1891 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x700 |
1892 | #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x8 |
1893 | #define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE_MASK 0x1 |
1894 | #define SYMCLKG_CLOCK_ENABLE__SYMCLKG_CLOCK_ENABLE__SHIFT 0x0 |
1895 | #define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN_MASK 0x10 |
1896 | #define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_EN__SHIFT 0x4 |
1897 | #define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC_MASK 0x700 |
1898 | #define SYMCLKG_CLOCK_ENABLE__SYMCLKG_FE_FORCE_SRC__SHIFT 0x8 |
1899 | #define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x1 |
1900 | #define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x0 |
1901 | #define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x2 |
1902 | #define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x1 |
1903 | #define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x4 |
1904 | #define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x2 |
1905 | #define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x8 |
1906 | #define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x3 |
1907 | #define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x10 |
1908 | #define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x4 |
1909 | #define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x20 |
1910 | #define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0x5 |
1911 | #define UNIPHY_SOFT_RESET__DSYNCG_SOFT_RESET_MASK 0x40 |
1912 | #define UNIPHY_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT 0x6 |
1913 | #define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x1 |
1914 | #define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x0 |
1915 | #define DCO_SOFT_RESET__DACB_SOFT_RESET_MASK 0x2 |
1916 | #define DCO_SOFT_RESET__DACB_SOFT_RESET__SHIFT 0x1 |
1917 | #define DCO_SOFT_RESET__SOFT_RESET_DVO_MASK 0x4 |
1918 | #define DCO_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 |
1919 | #define DCO_SOFT_RESET__DVO_ENABLE_RST_MASK 0x8 |
1920 | #define DCO_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 |
1921 | #define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET_MASK 0x10 |
1922 | #define DCO_SOFT_RESET__I2S0_SPDIF0_SOFT_RESET__SHIFT 0x4 |
1923 | #define DCO_SOFT_RESET__I2S1_SOFT_RESET_MASK 0x20 |
1924 | #define DCO_SOFT_RESET__I2S1_SOFT_RESET__SHIFT 0x5 |
1925 | #define DCO_SOFT_RESET__SPDIF1_SOFT_RESET_MASK 0x40 |
1926 | #define DCO_SOFT_RESET__SPDIF1_SOFT_RESET__SHIFT 0x6 |
1927 | #define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x10000 |
1928 | #define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x10 |
1929 | #define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x20000 |
1930 | #define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x11 |
1931 | #define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x40000 |
1932 | #define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x12 |
1933 | #define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x80000 |
1934 | #define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x13 |
1935 | #define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x100000 |
1936 | #define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x14 |
1937 | #define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x200000 |
1938 | #define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x15 |
1939 | #define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x1000000 |
1940 | #define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x18 |
1941 | #define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x2000000 |
1942 | #define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x19 |
1943 | #define DCO_SOFT_RESET__TVOUT_SOFT_RESET_MASK 0x4000000 |
1944 | #define DCO_SOFT_RESET__TVOUT_SOFT_RESET__SHIFT 0x1a |
1945 | #define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x8000000 |
1946 | #define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x1b |
1947 | #define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE_MASK 0x10000000 |
1948 | #define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE__SHIFT 0x1c |
1949 | #define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET_MASK 0x20000000 |
1950 | #define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET__SHIFT 0x1d |
1951 | #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x7 |
1952 | #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x0 |
1953 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x1f00 |
1954 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x8 |
1955 | #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x10000 |
1956 | #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x10 |
1957 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x20000 |
1958 | #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x11 |
1959 | #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x40000 |
1960 | #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x12 |
1961 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x7 |
1962 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x0 |
1963 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x1f00 |
1964 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x8 |
1965 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x10000 |
1966 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x10 |
1967 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x20000 |
1968 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x11 |
1969 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x40000 |
1970 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x12 |
1971 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x100000 |
1972 | #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x14 |
1973 | #define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x3000000 |
1974 | #define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x18 |
1975 | #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000 |
1976 | #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x1c |
1977 | #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x7 |
1978 | #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x0 |
1979 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x1f00 |
1980 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x8 |
1981 | #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x10000 |
1982 | #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x10 |
1983 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x20000 |
1984 | #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x11 |
1985 | #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x40000 |
1986 | #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x12 |
1987 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x7 |
1988 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 |
1989 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x30 |
1990 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 |
1991 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL_MASK 0x3000 |
1992 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_SOURCE_SEL__SHIFT 0xc |
1993 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN_MASK 0x10000 |
1994 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_CLOCK_EN__SHIFT 0x10 |
1995 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x100000 |
1996 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 |
1997 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x1000000 |
1998 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 |
1999 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000 |
2000 | #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c |
2001 | #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffff |
2002 | #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 |
2003 | #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffff |
2004 | #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 |
2005 | #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffff |
2006 | #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 |
2007 | #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffff |
2008 | #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 |
2009 | #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0xff |
2010 | #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x0 |
2011 | #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x100 |
2012 | #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
2013 | #define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL_MASK 0x1000 |
2014 | #define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL__SHIFT 0xc |
2015 | #define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffff |
2016 | #define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x0 |
2017 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x1ff |
2018 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 |
2019 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x1000 |
2020 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc |
2021 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x1ff0000 |
2022 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x10 |
2023 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x10000000 |
2024 | #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x1c |
2025 | #define PLL_REF_DIV__PLL_REF_DIV_MASK 0x3ff |
2026 | #define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x0 |
2027 | #define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0xf000 |
2028 | #define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0xc |
2029 | #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0xf |
2030 | #define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x0 |
2031 | #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x30 |
2032 | #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x4 |
2033 | #define PLL_FB_DIV__PLL_FB_DIV_MASK 0xfff0000 |
2034 | #define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x10 |
2035 | #define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x7f |
2036 | #define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x0 |
2037 | #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x80 |
2038 | #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x7 |
2039 | #define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x7f00 |
2040 | #define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x8 |
2041 | #define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x8000 |
2042 | #define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0xf |
2043 | #define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x7f0000 |
2044 | #define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x10 |
2045 | #define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0xffff |
2046 | #define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x0 |
2047 | #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0xff |
2048 | #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x0 |
2049 | #define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0xf00 |
2050 | #define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x8 |
2051 | #define PLL_SS_CNTL__PLL_SS_EN_MASK 0x1000 |
2052 | #define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0xc |
2053 | #define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x2000 |
2054 | #define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0xd |
2055 | #define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000 |
2056 | #define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x10 |
2057 | #define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0xffff |
2058 | #define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x0 |
2059 | #define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x30000 |
2060 | #define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x10 |
2061 | #define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x40000 |
2062 | #define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x12 |
2063 | #define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x80000 |
2064 | #define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x13 |
2065 | #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x1 |
2066 | #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x0 |
2067 | #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x2 |
2068 | #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x1 |
2069 | #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x4 |
2070 | #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x2 |
2071 | #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x8 |
2072 | #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x3 |
2073 | #define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN_MASK 0x10 |
2074 | #define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN__SHIFT 0x4 |
2075 | #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x100 |
2076 | #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x8 |
2077 | #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x1000 |
2078 | #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0xc |
2079 | #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0xf0000 |
2080 | #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x10 |
2081 | #define PLL_IDCLK_CNTL__PLL_CUR_LTDP_MASK 0x300000 |
2082 | #define PLL_IDCLK_CNTL__PLL_CUR_LTDP__SHIFT 0x14 |
2083 | #define PLL_IDCLK_CNTL__PLL_CUR_PREDRV_MASK 0xc00000 |
2084 | #define PLL_IDCLK_CNTL__PLL_CUR_PREDRV__SHIFT 0x16 |
2085 | #define PLL_IDCLK_CNTL__PLL_CUR_TMDP_MASK 0x3000000 |
2086 | #define PLL_IDCLK_CNTL__PLL_CUR_TMDP__SHIFT 0x18 |
2087 | #define PLL_CNTL__PLL_RESET_MASK 0x1 |
2088 | #define PLL_CNTL__PLL_RESET__SHIFT 0x0 |
2089 | #define PLL_CNTL__PLL_POWER_DOWN_MASK 0x2 |
2090 | #define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x1 |
2091 | #define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x4 |
2092 | #define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x2 |
2093 | #define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x8 |
2094 | #define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x3 |
2095 | #define PLL_CNTL__PLL_VCOREF_MASK 0x30 |
2096 | #define PLL_CNTL__PLL_VCOREF__SHIFT 0x4 |
2097 | #define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x40 |
2098 | #define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x6 |
2099 | #define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x80 |
2100 | #define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x7 |
2101 | #define PLL_CNTL__PLL_CALREF_MASK 0x300 |
2102 | #define PLL_CNTL__PLL_CALREF__SHIFT 0x8 |
2103 | #define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x400 |
2104 | #define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0xa |
2105 | #define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x1800 |
2106 | #define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0xb |
2107 | #define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x2000 |
2108 | #define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0xd |
2109 | #define PLL_CNTL__PLL_XOCLK_DRV_R_EN_MASK 0x4000 |
2110 | #define PLL_CNTL__PLL_XOCLK_DRV_R_EN__SHIFT 0xe |
2111 | #define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x70000 |
2112 | #define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x10 |
2113 | #define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x80000 |
2114 | #define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x13 |
2115 | #define PLL_CNTL__PLL_CALIB_DONE_MASK 0x100000 |
2116 | #define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x14 |
2117 | #define PLL_CNTL__PLL_LOCKED_MASK 0x200000 |
2118 | #define PLL_CNTL__PLL_LOCKED__SHIFT 0x15 |
2119 | #define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x3000000 |
2120 | #define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x18 |
2121 | #define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000 |
2122 | #define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x1a |
2123 | #define PLL_ANALOG__PLL_CAL_MODE_MASK 0x1f |
2124 | #define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x0 |
2125 | #define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x60 |
2126 | #define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x5 |
2127 | #define PLL_ANALOG__PLL_CP_MASK 0xf00 |
2128 | #define PLL_ANALOG__PLL_CP__SHIFT 0x8 |
2129 | #define PLL_ANALOG__PLL_LF_MODE_MASK 0x1ff000 |
2130 | #define PLL_ANALOG__PLL_LF_MODE__SHIFT 0xc |
2131 | #define PLL_ANALOG__PLL_VREG_FB_TRIM_MASK 0xe00000 |
2132 | #define PLL_ANALOG__PLL_VREG_FB_TRIM__SHIFT 0x15 |
2133 | #define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000 |
2134 | #define PLL_ANALOG__PLL_IBIAS__SHIFT 0x18 |
2135 | #define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN_MASK 0x1 |
2136 | #define PLL_ANALOG_CNTL__PLL_ANALOG_TEST_EN__SHIFT 0x0 |
2137 | #define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL_MASK 0x1e |
2138 | #define PLL_ANALOG_CNTL__PLL_ANALOG_MUX_CNTL__SHIFT 0x1 |
2139 | #define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL_MASK 0x1e0 |
2140 | #define PLL_ANALOG_CNTL__PLL_ANALOGOUT_MUX_CNTL__SHIFT 0x5 |
2141 | #define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0xfffff |
2142 | #define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x0 |
2143 | #define PLL_VREG_CNTL__PLL_BG_VREG_BIAS_MASK 0x300000 |
2144 | #define PLL_VREG_CNTL__PLL_BG_VREG_BIAS__SHIFT 0x14 |
2145 | #define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x4000000 |
2146 | #define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x1a |
2147 | #define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000 |
2148 | #define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x1c |
2149 | #define PLL_XOR_LOCK__PLL_XOR_LOCK_MASK 0x1 |
2150 | #define PLL_XOR_LOCK__PLL_XOR_LOCK__SHIFT 0x0 |
2151 | #define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK_MASK 0x2 |
2152 | #define PLL_XOR_LOCK__PLL_XOR_LOCK_READBACK__SHIFT 0x1 |
2153 | #define PLL_XOR_LOCK__PLL_SPARE_MASK 0x3f00 |
2154 | #define PLL_XOR_LOCK__PLL_SPARE__SHIFT 0x8 |
2155 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x1 |
2156 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x0 |
2157 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x2 |
2158 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x1 |
2159 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x4 |
2160 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x2 |
2161 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR_MASK 0x8 |
2162 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR__SHIFT 0x3 |
2163 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x70 |
2164 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x4 |
2165 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST_MASK 0x80 |
2166 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_RST_TEST__SHIFT 0x7 |
2167 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK_MASK 0x100 |
2168 | #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCKED_STICKY_TEST_READBACK__SHIFT 0x8 |
2169 | #define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x1 |
2170 | #define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x0 |
2171 | #define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0xf0 |
2172 | #define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x4 |
2173 | #define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x1f00 |
2174 | #define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x8 |
2175 | #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL_MASK 0xff0000 |
2176 | #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_CNTL__SHIFT 0x10 |
2177 | #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK_MASK 0x7000000 |
2178 | #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_READBACK__SHIFT 0x18 |
2179 | #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN_MASK 0x8000000 |
2180 | #define PLL_DEBUG_CNTL__PLL_DEBUG_ADC_EN__SHIFT 0x1b |
2181 | #define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x1 |
2182 | #define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x0 |
2183 | #define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x1 |
2184 | #define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x0 |
2185 | #define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x100 |
2186 | #define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x8 |
2187 | #define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x10000 |
2188 | #define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x10 |
2189 | #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE_MASK 0x1ff |
2190 | #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE__SHIFT 0x0 |
2191 | #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS_MASK 0x10000 |
2192 | #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS__SHIFT 0x10 |
2193 | #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE_MASK 0x60000 |
2194 | #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE__SHIFT 0x11 |
2195 | #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING_MASK 0x100000 |
2196 | #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING__SHIFT 0x14 |
2197 | #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ_MASK 0x200000 |
2198 | #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ__SHIFT 0x15 |
2199 | #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK_MASK 0x400000 |
2200 | #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK__SHIFT 0x16 |
2201 | #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY_MASK 0xff000000 |
2202 | #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY__SHIFT 0x18 |
2203 | #define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE_MASK 0x1ff |
2204 | #define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE__SHIFT 0x0 |
2205 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x7f |
2206 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 |
2207 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x7f00 |
2208 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 |
2209 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x18000 |
2210 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf |
2211 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x20000 |
2212 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 |
2213 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x40000 |
2214 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 |
2215 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x80000 |
2216 | #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 |
2217 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x100000 |
2218 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x14 |
2219 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x200000 |
2220 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x15 |
2221 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x400000 |
2222 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x16 |
2223 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000 |
2224 | #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x18 |
2225 | #define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffff |
2226 | #define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x0 |
2227 | #define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffff |
2228 | #define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x0 |
2229 | #define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffff |
2230 | #define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x0 |
2231 | #define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffff |
2232 | #define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x0 |
2233 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0xf |
2234 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x0 |
2235 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x1f0 |
2236 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x4 |
2237 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x1000 |
2238 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0xc |
2239 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0xf0000 |
2240 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0x10 |
2241 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x1f00000 |
2242 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x14 |
2243 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000 |
2244 | #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x1c |
2245 | #define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x1f |
2246 | #define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x0 |
2247 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN_MASK 0x20 |
2248 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN__SHIFT 0x5 |
2249 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL_MASK 0x40 |
2250 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL__SHIFT 0x6 |
2251 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN_MASK 0x80 |
2252 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN__SHIFT 0x7 |
2253 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_MASK 0xfff00 |
2254 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA__SHIFT 0x8 |
2255 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL_MASK 0x300000 |
2256 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL__SHIFT 0x14 |
2257 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL_MASK 0x400000 |
2258 | #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_24BIT_SEL__SHIFT 0x16 |
2259 | #define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffff |
2260 | #define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x0 |
2261 | #define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 |
2262 | #define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
2263 | #define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 |
2264 | #define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
2265 | #define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 |
2266 | #define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 |
2267 | #define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 |
2268 | #define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc |
2269 | #define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 |
2270 | #define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 |
2271 | #define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 |
2272 | #define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c |
2273 | #define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 |
2274 | #define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e |
2275 | #define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x3 |
2276 | #define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x0 |
2277 | #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x4 |
2278 | #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x2 |
2279 | #define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x10 |
2280 | #define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x4 |
2281 | #define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x700 |
2282 | #define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x8 |
2283 | #define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0xf000 |
2284 | #define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0xc |
2285 | #define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x3f0000 |
2286 | #define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x10 |
2287 | #define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000 |
2288 | #define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x18 |
2289 | #define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000 |
2290 | #define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x1d |
2291 | #define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x3f |
2292 | #define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x0 |
2293 | #define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x3f00 |
2294 | #define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x8 |
2295 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x10000 |
2296 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x10 |
2297 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x20000 |
2298 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x11 |
2299 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x700000 |
2300 | #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x14 |
2301 | #define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x7000000 |
2302 | #define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x18 |
2303 | #define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000 |
2304 | #define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x1c |
2305 | #define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffff |
2306 | #define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x0 |
2307 | #define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0xffff |
2308 | #define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x0 |
2309 | #define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000 |
2310 | #define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x10 |
2311 | #define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
2312 | #define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
2313 | #define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
2314 | #define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
2315 | #define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
2316 | #define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
2317 | #define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
2318 | #define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
2319 | #define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
2320 | #define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
2321 | #define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0xffff |
2322 | #define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x0 |
2323 | #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0xff |
2324 | #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x0 |
2325 | #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x100 |
2326 | #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
2327 | #define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffff |
2328 | #define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x0 |
2329 | #define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0xffff |
2330 | #define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x0 |
2331 | #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x10000 |
2332 | #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x10 |
2333 | #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0xffe0000 |
2334 | #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x11 |
2335 | #define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0xffff |
2336 | #define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x0 |
2337 | #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x10000 |
2338 | #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x10 |
2339 | #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0xffe0000 |
2340 | #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x11 |
2341 | #define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x70 |
2342 | #define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
2343 | #define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000 |
2344 | #define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x1c |
2345 | #define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x1 |
2346 | #define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x0 |
2347 | #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x2 |
2348 | #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x1 |
2349 | #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x4 |
2350 | #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x2 |
2351 | #define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x8 |
2352 | #define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x3 |
2353 | #define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x10 |
2354 | #define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x4 |
2355 | #define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x20 |
2356 | #define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x5 |
2357 | #define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x100 |
2358 | #define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x8 |
2359 | #define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x200 |
2360 | #define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x9 |
2361 | #define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
2362 | #define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
2363 | #define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
2364 | #define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
2365 | #define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
2366 | #define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
2367 | #define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
2368 | #define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
2369 | #define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
2370 | #define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
2371 | #define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x3ff |
2372 | #define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x0 |
2373 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x1 |
2374 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x0 |
2375 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x18 |
2376 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x3 |
2377 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0xe0 |
2378 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x5 |
2379 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x700 |
2380 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x8 |
2381 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x800 |
2382 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0xb |
2383 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x7000 |
2384 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0xc |
2385 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0xfff0000 |
2386 | #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x10 |
2387 | #define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x3 |
2388 | #define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x0 |
2389 | #define MCIF_CONTROL__MCIF_SCANIN_DISABLE_MASK 0x8 |
2390 | #define MCIF_CONTROL__MCIF_SCANIN_DISABLE__SHIFT 0x3 |
2391 | #define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x10 |
2392 | #define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x4 |
2393 | #define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x100 |
2394 | #define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x8 |
2395 | #define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0xf000 |
2396 | #define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0xc |
2397 | #define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0xff0000 |
2398 | #define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x10 |
2399 | #define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000 |
2400 | #define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x18 |
2401 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000 |
2402 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x1e |
2403 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000 |
2404 | #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x1f |
2405 | #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0xff |
2406 | #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x0 |
2407 | #define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0xff00 |
2408 | #define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x8 |
2409 | #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0xff |
2410 | #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x0 |
2411 | #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x100 |
2412 | #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
2413 | #define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffff |
2414 | #define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x0 |
2415 | #define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff |
2416 | #define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 |
2417 | #define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffff |
2418 | #define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x0 |
2419 | #define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffff |
2420 | #define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x0 |
2421 | #define MCIF_VMID__MCIF_WR_VMID_MASK 0xf |
2422 | #define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x0 |
2423 | #define MCIF_VMID__VIP_WR_VMID_MASK 0xf0 |
2424 | #define MCIF_VMID__VIP_WR_VMID__SHIFT 0x4 |
2425 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x1 |
2426 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x0 |
2427 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x30 |
2428 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x4 |
2429 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0xff00 |
2430 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x8 |
2431 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x70000 |
2432 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x10 |
2433 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x180000 |
2434 | #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x13 |
2435 | #define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x7e |
2436 | #define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x1 |
2437 | #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x1 |
2438 | #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x0 |
2439 | #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x10 |
2440 | #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x4 |
2441 | #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x100 |
2442 | #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x8 |
2443 | #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x1000 |
2444 | #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0xc |
2445 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x10000 |
2446 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x10 |
2447 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x100000 |
2448 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x14 |
2449 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x1000000 |
2450 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x18 |
2451 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000 |
2452 | #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x1c |
2453 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY_MASK 0xf |
2454 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY__SHIFT 0x0 |
2455 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS_MASK 0x20 |
2456 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS__SHIFT 0x5 |
2457 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY_MASK 0x3c0 |
2458 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY__SHIFT 0x6 |
2459 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK 0x800 |
2460 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS__SHIFT 0xb |
2461 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY_MASK 0xf000 |
2462 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY__SHIFT 0xc |
2463 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS_MASK 0x20000 |
2464 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS__SHIFT 0x11 |
2465 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY_MASK 0x3c0000 |
2466 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY__SHIFT 0x12 |
2467 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS_MASK 0x800000 |
2468 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS__SHIFT 0x17 |
2469 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY_MASK 0xf000000 |
2470 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY__SHIFT 0x18 |
2471 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS_MASK 0x20000000 |
2472 | #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS__SHIFT 0x1d |
2473 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_DELAY_MASK 0xf |
2474 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_DELAY__SHIFT 0x0 |
2475 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_TIMEOUT_DIS_MASK 0x20 |
2476 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT5_RDWR_TIMEOUT_DIS__SHIFT 0x5 |
2477 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_DELAY_MASK 0x3c0 |
2478 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_DELAY__SHIFT 0x6 |
2479 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS_MASK 0x800 |
2480 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS__SHIFT 0xb |
2481 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_DELAY_MASK 0xf000 |
2482 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_DELAY__SHIFT 0xc |
2483 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_TIMEOUT_DIS_MASK 0x20000 |
2484 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT7_RDWR_TIMEOUT_DIS__SHIFT 0x11 |
2485 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY_MASK 0x3c0000 |
2486 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY__SHIFT 0x12 |
2487 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS_MASK 0x800000 |
2488 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS__SHIFT 0x17 |
2489 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY_MASK 0xf000000 |
2490 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY__SHIFT 0x18 |
2491 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS_MASK 0x20000000 |
2492 | #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS__SHIFT 0x1d |
2493 | #define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_DELAY_MASK 0xf |
2494 | #define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_DELAY__SHIFT 0x0 |
2495 | #define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_TIMEOUT_DIS_MASK 0x20 |
2496 | #define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_CLIENT10_RDWR_TIMEOUT_DIS__SHIFT 0x5 |
2497 | #define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_TIMEOUT_DELAY_MASK 0x1ffff000 |
2498 | #define DC_RBBMIF_RDWR_CNTL3__DC_RBBMIF_TIMEOUT_DELAY__SHIFT 0xc |
2499 | #define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE_MASK 0x3 |
2500 | #define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE__SHIFT 0x0 |
2501 | #define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE_MASK 0xc |
2502 | #define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE__SHIFT 0x2 |
2503 | #define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE_MASK 0x30 |
2504 | #define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE__SHIFT 0x4 |
2505 | #define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE_MASK 0xc0 |
2506 | #define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE__SHIFT 0x6 |
2507 | #define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE_MASK 0x300 |
2508 | #define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE__SHIFT 0x8 |
2509 | #define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE_MASK 0xc00 |
2510 | #define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE__SHIFT 0xa |
2511 | #define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK 0x3000 |
2512 | #define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE__SHIFT 0xc |
2513 | #define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE_MASK 0xc000 |
2514 | #define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE__SHIFT 0xe |
2515 | #define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE_MASK 0x30000 |
2516 | #define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE__SHIFT 0x10 |
2517 | #define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE_MASK 0xc0000 |
2518 | #define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE__SHIFT 0x12 |
2519 | #define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE_MASK 0x300000 |
2520 | #define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE__SHIFT 0x14 |
2521 | #define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE_MASK 0xc00000 |
2522 | #define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE__SHIFT 0x16 |
2523 | #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE_MASK 0x3000000 |
2524 | #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE__SHIFT 0x18 |
2525 | #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 0xc000000 |
2526 | #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE__SHIFT 0x1a |
2527 | #define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE_MASK 0x30000000 |
2528 | #define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE__SHIFT 0x1c |
2529 | #define DCI_MEM_PWR_STATE__MCIFWB_MEM_PWR_STATE_MASK 0xc0000000 |
2530 | #define DCI_MEM_PWR_STATE__MCIFWB_MEM_PWR_STATE__SHIFT 0x1e |
2531 | #define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE_MASK 0x3 |
2532 | #define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE__SHIFT 0x0 |
2533 | #define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE_MASK 0xc |
2534 | #define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE__SHIFT 0x2 |
2535 | #define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE_MASK 0x30 |
2536 | #define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE__SHIFT 0x4 |
2537 | #define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x1f |
2538 | #define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x0 |
2539 | #define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x20 |
2540 | #define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x5 |
2541 | #define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x40 |
2542 | #define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x6 |
2543 | #define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x80 |
2544 | #define DCI_CLK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x7 |
2545 | #define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x100 |
2546 | #define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x8 |
2547 | #define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x200 |
2548 | #define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x9 |
2549 | #define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS_MASK 0x400 |
2550 | #define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS__SHIFT 0xa |
2551 | #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x800 |
2552 | #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0xb |
2553 | #define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS_MASK 0x1000 |
2554 | #define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS__SHIFT 0xc |
2555 | #define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x2000 |
2556 | #define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0xd |
2557 | #define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS_MASK 0x4000 |
2558 | #define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS__SHIFT 0xe |
2559 | #define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x8000 |
2560 | #define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0xf |
2561 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x10000 |
2562 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x10 |
2563 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x20000 |
2564 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x11 |
2565 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x40000 |
2566 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x12 |
2567 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x80000 |
2568 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x13 |
2569 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x100000 |
2570 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x14 |
2571 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x200000 |
2572 | #define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x15 |
2573 | #define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x400000 |
2574 | #define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x16 |
2575 | #define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x800000 |
2576 | #define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x17 |
2577 | #define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x1000000 |
2578 | #define DCI_CLK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x18 |
2579 | #define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000 |
2580 | #define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x1b |
2581 | #define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL_MASK 0x1 |
2582 | #define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL__SHIFT 0x0 |
2583 | #define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE_MASK 0x2 |
2584 | #define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x1 |
2585 | #define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS_MASK 0x4 |
2586 | #define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS__SHIFT 0x2 |
2587 | #define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS_MASK 0x8 |
2588 | #define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS__SHIFT 0x3 |
2589 | #define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE_MASK 0x10 |
2590 | #define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x4 |
2591 | #define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE_MASK 0x20 |
2592 | #define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x5 |
2593 | #define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS_MASK 0x100 |
2594 | #define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS__SHIFT 0x8 |
2595 | #define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS_MASK 0x200 |
2596 | #define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS__SHIFT 0x9 |
2597 | #define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS_MASK 0x400 |
2598 | #define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS__SHIFT 0xa |
2599 | #define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK 0x800 |
2600 | #define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS__SHIFT 0xb |
2601 | #define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS_MASK 0x1000 |
2602 | #define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS__SHIFT 0xc |
2603 | #define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS_MASK 0x2000 |
2604 | #define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS__SHIFT 0xd |
2605 | #define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS_MASK 0x4000 |
2606 | #define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS__SHIFT 0xe |
2607 | #define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS_MASK 0x8000 |
2608 | #define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS__SHIFT 0xf |
2609 | #define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS_MASK 0x10000 |
2610 | #define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS__SHIFT 0x10 |
2611 | #define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE_MASK 0x20000 |
2612 | #define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x11 |
2613 | #define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE_MASK 0x40000 |
2614 | #define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x12 |
2615 | #define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS_MASK 0x80000 |
2616 | #define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS__SHIFT 0x13 |
2617 | #define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS_MASK 0x100000 |
2618 | #define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS__SHIFT 0x14 |
2619 | #define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS_MASK 0x200000 |
2620 | #define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS__SHIFT 0x15 |
2621 | #define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS_MASK 0x400000 |
2622 | #define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS__SHIFT 0x16 |
2623 | #define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS_MASK 0x800000 |
2624 | #define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS__SHIFT 0x17 |
2625 | #define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS_MASK 0x1000000 |
2626 | #define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS__SHIFT 0x18 |
2627 | #define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS_MASK 0x2000000 |
2628 | #define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS__SHIFT 0x19 |
2629 | #define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS_MASK 0x4000000 |
2630 | #define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS__SHIFT 0x1a |
2631 | #define DCCG_VPCLK_CNTL__MCIFWB_LIGHT_SLEEP_MODE_FORCE_MASK 0x8000000 |
2632 | #define DCCG_VPCLK_CNTL__MCIFWB_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x1b |
2633 | #define DCCG_VPCLK_CNTL__MCIFWB_MEM_SHUTDOWN_MODE_FORCE_MASK 0x10000000 |
2634 | #define DCCG_VPCLK_CNTL__MCIFWB_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x1c |
2635 | #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS_MASK 0x1 |
2636 | #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x0 |
2637 | #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS_MASK 0x2 |
2638 | #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x1 |
2639 | #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS_MASK 0x4 |
2640 | #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x2 |
2641 | #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS_MASK 0x8 |
2642 | #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x3 |
2643 | #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS_MASK 0x10 |
2644 | #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x4 |
2645 | #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS_MASK 0x20 |
2646 | #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x5 |
2647 | #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x40 |
2648 | #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x6 |
2649 | #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x80 |
2650 | #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x7 |
2651 | #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x100 |
2652 | #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x8 |
2653 | #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x200 |
2654 | #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x9 |
2655 | #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x400 |
2656 | #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0xa |
2657 | #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x800 |
2658 | #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0xb |
2659 | #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x3000 |
2660 | #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0xc |
2661 | #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0xc000 |
2662 | #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0xe |
2663 | #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x30000 |
2664 | #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x10 |
2665 | #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0xc0000 |
2666 | #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0x12 |
2667 | #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x300000 |
2668 | #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0x14 |
2669 | #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0xc00000 |
2670 | #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x16 |
2671 | #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE_MASK 0x3f |
2672 | #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE__SHIFT 0x0 |
2673 | #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL_MASK 0x700 |
2674 | #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL__SHIFT 0x8 |
2675 | #define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING_MASK 0x10000 |
2676 | #define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING__SHIFT 0x10 |
2677 | #define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP_MASK 0x100000 |
2678 | #define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP__SHIFT 0x14 |
2679 | #define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP_MASK 0x200000 |
2680 | #define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP__SHIFT 0x15 |
2681 | #define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP_MASK 0x400000 |
2682 | #define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP__SHIFT 0x16 |
2683 | #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0xff |
2684 | #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x0 |
2685 | #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x100 |
2686 | #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
2687 | #define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffff |
2688 | #define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x0 |
2689 | #define DCI_DEBUG_CONFIG__DCI_DBG_SEL_MASK 0xf |
2690 | #define DCI_DEBUG_CONFIG__DCI_DBG_SEL__SHIFT 0x0 |
2691 | #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
2692 | #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
2693 | #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
2694 | #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
2695 | #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
2696 | #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
2697 | #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
2698 | #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
2699 | #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
2700 | #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
2701 | #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
2702 | #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
2703 | #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
2704 | #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
2705 | #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
2706 | #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
2707 | #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
2708 | #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
2709 | #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
2710 | #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
2711 | #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x7 |
2712 | #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x0 |
2713 | #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x10 |
2714 | #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x4 |
2715 | #define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_ENABLE_MASK 0x1 |
2716 | #define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_ENABLE__SHIFT 0x0 |
2717 | #define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_EN_MASK 0x10 |
2718 | #define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_EN__SHIFT 0x4 |
2719 | #define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_ACK_MASK 0x20 |
2720 | #define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_INT_ACK__SHIFT 0x5 |
2721 | #define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_SLICE_INT_EN_MASK 0x40 |
2722 | #define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 |
2723 | #define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_LOCK_MASK 0xf00 |
2724 | #define MCIF_BUFMGR_SW_CONTROL__MCIF_BUFMGR_SW_LOCK__SHIFT 0x8 |
2725 | #define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_SW_INT_STATUS_MASK 0x2 |
2726 | #define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_SW_INT_STATUS__SHIFT 0x1 |
2727 | #define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_BUF_MASK 0x70 |
2728 | #define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_BUF__SHIFT 0x4 |
2729 | #define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_BUFTAG_MASK 0xf00 |
2730 | #define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_BUFTAG__SHIFT 0x8 |
2731 | #define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_LINE_MASK 0x1fff000 |
2732 | #define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_CUR_LINE__SHIFT 0xc |
2733 | #define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_NEXT_BUF_MASK 0x70000000 |
2734 | #define MCIF_BUFMGR_STATUS__MCIF_BUFMGR_NEXT_BUF__SHIFT 0x1c |
2735 | #define MCIF_BUF_PITCH__MCIF_BUF_LUMA_PITCH_MASK 0xffff |
2736 | #define MCIF_BUF_PITCH__MCIF_BUF_LUMA_PITCH__SHIFT 0x0 |
2737 | #define MCIF_BUF_PITCH__MCIF_BUF_CHROMA_PITCH_MASK 0xffff0000 |
2738 | #define MCIF_BUF_PITCH__MCIF_BUF_CHROMA_PITCH__SHIFT 0x10 |
2739 | #define MCIF_BUF_1_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff |
2740 | #define MCIF_BUF_1_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0 |
2741 | #define MCIF_BUF_2_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff |
2742 | #define MCIF_BUF_2_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0 |
2743 | #define MCIF_BUF_3_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff |
2744 | #define MCIF_BUF_3_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0 |
2745 | #define MCIF_BUF_4_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW_MASK 0xffffffff |
2746 | #define MCIF_BUF_4_ADDR_Y_LOW__MCIF_BUF_ADDR_Y_LOW__SHIFT 0x0 |
2747 | #define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff |
2748 | #define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0 |
2749 | #define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000 |
2750 | #define MCIF_BUF_1_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10 |
2751 | #define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff |
2752 | #define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0 |
2753 | #define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000 |
2754 | #define MCIF_BUF_2_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10 |
2755 | #define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff |
2756 | #define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0 |
2757 | #define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000 |
2758 | #define MCIF_BUF_3_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10 |
2759 | #define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_Y_UP_MASK 0xff |
2760 | #define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_Y_UP__SHIFT 0x0 |
2761 | #define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_C_UP_MASK 0xff0000 |
2762 | #define MCIF_BUF_4_ADDR_UP__MCIF_BUF_ADDR_C_UP__SHIFT 0x10 |
2763 | #define MCIF_BUF_1_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff |
2764 | #define MCIF_BUF_1_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0 |
2765 | #define MCIF_BUF_2_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff |
2766 | #define MCIF_BUF_2_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0 |
2767 | #define MCIF_BUF_3_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff |
2768 | #define MCIF_BUF_3_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0 |
2769 | #define MCIF_BUF_4_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW_MASK 0xffffffff |
2770 | #define MCIF_BUF_4_ADDR_C_LOW__MCIF_BUF_ADDR_C_LOW__SHIFT 0x0 |
2771 | #define MCIF_BUF_1_STATUS__MCIF_BUF_ACTIVE_MASK 0x1 |
2772 | #define MCIF_BUF_1_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0 |
2773 | #define MCIF_BUF_1_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2 |
2774 | #define MCIF_BUF_1_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1 |
2775 | #define MCIF_BUF_1_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8 |
2776 | #define MCIF_BUF_1_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3 |
2777 | #define MCIF_BUF_1_STATUS__MCIF_BUF_DISABLE_MASK 0x10 |
2778 | #define MCIF_BUF_1_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4 |
2779 | #define MCIF_BUF_1_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20 |
2780 | #define MCIF_BUF_1_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5 |
2781 | #define MCIF_BUF_1_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40 |
2782 | #define MCIF_BUF_1_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6 |
2783 | #define MCIF_BUF_1_STATUS__MCIF_BUF_MODE_MASK 0x80 |
2784 | #define MCIF_BUF_1_STATUS__MCIF_BUF_MODE__SHIFT 0x7 |
2785 | #define MCIF_BUF_1_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00 |
2786 | #define MCIF_BUF_1_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8 |
2787 | #define MCIF_BUF_1_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000 |
2788 | #define MCIF_BUF_1_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc |
2789 | #define MCIF_BUF_1_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000 |
2790 | #define MCIF_BUF_1_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10 |
2791 | #define MCIF_BUF_2_STATUS__MCIF_BUF_ACTIVE_MASK 0x1 |
2792 | #define MCIF_BUF_2_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0 |
2793 | #define MCIF_BUF_2_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2 |
2794 | #define MCIF_BUF_2_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1 |
2795 | #define MCIF_BUF_2_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8 |
2796 | #define MCIF_BUF_2_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3 |
2797 | #define MCIF_BUF_2_STATUS__MCIF_BUF_DISABLE_MASK 0x10 |
2798 | #define MCIF_BUF_2_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4 |
2799 | #define MCIF_BUF_2_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20 |
2800 | #define MCIF_BUF_2_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5 |
2801 | #define MCIF_BUF_2_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40 |
2802 | #define MCIF_BUF_2_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6 |
2803 | #define MCIF_BUF_2_STATUS__MCIF_BUF_MODE_MASK 0x80 |
2804 | #define MCIF_BUF_2_STATUS__MCIF_BUF_MODE__SHIFT 0x7 |
2805 | #define MCIF_BUF_2_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00 |
2806 | #define MCIF_BUF_2_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8 |
2807 | #define MCIF_BUF_2_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000 |
2808 | #define MCIF_BUF_2_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc |
2809 | #define MCIF_BUF_2_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000 |
2810 | #define MCIF_BUF_2_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10 |
2811 | #define MCIF_BUF_3_STATUS__MCIF_BUF_ACTIVE_MASK 0x1 |
2812 | #define MCIF_BUF_3_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0 |
2813 | #define MCIF_BUF_3_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2 |
2814 | #define MCIF_BUF_3_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1 |
2815 | #define MCIF_BUF_3_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8 |
2816 | #define MCIF_BUF_3_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3 |
2817 | #define MCIF_BUF_3_STATUS__MCIF_BUF_DISABLE_MASK 0x10 |
2818 | #define MCIF_BUF_3_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4 |
2819 | #define MCIF_BUF_3_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20 |
2820 | #define MCIF_BUF_3_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5 |
2821 | #define MCIF_BUF_3_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40 |
2822 | #define MCIF_BUF_3_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6 |
2823 | #define MCIF_BUF_3_STATUS__MCIF_BUF_MODE_MASK 0x80 |
2824 | #define MCIF_BUF_3_STATUS__MCIF_BUF_MODE__SHIFT 0x7 |
2825 | #define MCIF_BUF_3_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00 |
2826 | #define MCIF_BUF_3_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8 |
2827 | #define MCIF_BUF_3_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000 |
2828 | #define MCIF_BUF_3_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc |
2829 | #define MCIF_BUF_3_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000 |
2830 | #define MCIF_BUF_3_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10 |
2831 | #define MCIF_BUF_4_STATUS__MCIF_BUF_ACTIVE_MASK 0x1 |
2832 | #define MCIF_BUF_4_STATUS__MCIF_BUF_ACTIVE__SHIFT 0x0 |
2833 | #define MCIF_BUF_4_STATUS__MCIF_BUF_SW_LOCKED_MASK 0x2 |
2834 | #define MCIF_BUF_4_STATUS__MCIF_BUF_SW_LOCKED__SHIFT 0x1 |
2835 | #define MCIF_BUF_4_STATUS__MCIF_BUF_OVERFLOW_MASK 0x8 |
2836 | #define MCIF_BUF_4_STATUS__MCIF_BUF_OVERFLOW__SHIFT 0x3 |
2837 | #define MCIF_BUF_4_STATUS__MCIF_BUF_DISABLE_MASK 0x10 |
2838 | #define MCIF_BUF_4_STATUS__MCIF_BUF_DISABLE__SHIFT 0x4 |
2839 | #define MCIF_BUF_4_STATUS__MCIF_BUF_NEW_CONTENT_MASK 0x20 |
2840 | #define MCIF_BUF_4_STATUS__MCIF_BUF_NEW_CONTENT__SHIFT 0x5 |
2841 | #define MCIF_BUF_4_STATUS__MCIF_BUF_STEREOSYNC_MASK 0x40 |
2842 | #define MCIF_BUF_4_STATUS__MCIF_BUF_STEREOSYNC__SHIFT 0x6 |
2843 | #define MCIF_BUF_4_STATUS__MCIF_BUF_MODE_MASK 0x80 |
2844 | #define MCIF_BUF_4_STATUS__MCIF_BUF_MODE__SHIFT 0x7 |
2845 | #define MCIF_BUF_4_STATUS__MCIF_BUF_BUFTAG_MASK 0xf00 |
2846 | #define MCIF_BUF_4_STATUS__MCIF_BUF_BUFTAG__SHIFT 0x8 |
2847 | #define MCIF_BUF_4_STATUS__MCIF_BUF_NXT_BUF_MASK 0x7000 |
2848 | #define MCIF_BUF_4_STATUS__MCIF_BUF_NXT_BUF__SHIFT 0xc |
2849 | #define MCIF_BUF_4_STATUS__MCIF_BUF_CUR_LINE_MASK 0x1fff0000 |
2850 | #define MCIF_BUF_4_STATUS__MCIF_BUF_CUR_LINE__SHIFT 0x10 |
2851 | #define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT0_ARBITRATION_SLICE_MASK 0x3 |
2852 | #define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT0_ARBITRATION_SLICE__SHIFT 0x0 |
2853 | #define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT1_ARBITRATION_SLICE_MASK 0x30 |
2854 | #define MCIF_SI_ARBITRATION_CONTROL__MCIF_SI_CLIENT1_ARBITRATION_SLICE__SHIFT 0x4 |
2855 | #define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT0_URGENCY_WATERMARK_MASK 0xffff |
2856 | #define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT0_URGENCY_WATERMARK__SHIFT 0x0 |
2857 | #define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT1_URGENCY_WATERMARK_MASK 0xffff0000 |
2858 | #define MCIF_URGENCY_WATERMARK__MCIF_SI_CLIENT1_URGENCY_WATERMARK__SHIFT 0x10 |
2859 | #define DC_GENERICA__GENERICA_EN_MASK 0x1 |
2860 | #define DC_GENERICA__GENERICA_EN__SHIFT 0x0 |
2861 | #define DC_GENERICA__GENERICA_SEL_MASK 0xf00 |
2862 | #define DC_GENERICA__GENERICA_SEL__SHIFT 0x8 |
2863 | #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000 |
2864 | #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc |
2865 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000 |
2866 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 |
2867 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000 |
2868 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 |
2869 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000 |
2870 | #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 |
2871 | #define DC_GENERICB__GENERICB_EN_MASK 0x1 |
2872 | #define DC_GENERICB__GENERICB_EN__SHIFT 0x0 |
2873 | #define DC_GENERICB__GENERICB_SEL_MASK 0xf00 |
2874 | #define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 |
2875 | #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x7000 |
2876 | #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0xc |
2877 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x70000 |
2878 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x10 |
2879 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x700000 |
2880 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x14 |
2881 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x7000000 |
2882 | #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x18 |
2883 | #define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0xf |
2884 | #define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x0 |
2885 | #define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x30 |
2886 | #define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x4 |
2887 | #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x3 |
2888 | #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 |
2889 | #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x300 |
2890 | #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 |
2891 | #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x1 |
2892 | #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x0 |
2893 | #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x300 |
2894 | #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x8 |
2895 | #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x10000 |
2896 | #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x10 |
2897 | #define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN_MASK 0x20000 |
2898 | #define DC_GPIO_DEBUG__DC_GPIO_DEBUG_BUS_FLOP_EN__SHIFT 0x11 |
2899 | #define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE_MASK 0x3 |
2900 | #define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE__SHIFT 0x0 |
2901 | #define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE_MASK 0xc |
2902 | #define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE__SHIFT 0x2 |
2903 | #define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE_MASK 0x30 |
2904 | #define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE__SHIFT 0x4 |
2905 | #define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE_MASK 0xc0 |
2906 | #define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE__SHIFT 0x6 |
2907 | #define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE_MASK 0x300 |
2908 | #define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE__SHIFT 0x8 |
2909 | #define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE_MASK 0xc00 |
2910 | #define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE__SHIFT 0xa |
2911 | #define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE_MASK 0x3000 |
2912 | #define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE__SHIFT 0xc |
2913 | #define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE_MASK 0xc000 |
2914 | #define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE__SHIFT 0xe |
2915 | #define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE_MASK 0x30000 |
2916 | #define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE__SHIFT 0x10 |
2917 | #define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE_MASK 0xc0000 |
2918 | #define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 0x12 |
2919 | #define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE_MASK 0x300000 |
2920 | #define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE__SHIFT 0x14 |
2921 | #define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE_MASK 0xc00000 |
2922 | #define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE__SHIFT 0x16 |
2923 | #define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE_MASK 0x3000000 |
2924 | #define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE__SHIFT 0x18 |
2925 | #define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE_MASK 0xc000000 |
2926 | #define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE__SHIFT 0x1a |
2927 | #define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE_MASK 0x30000000 |
2928 | #define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 0x1c |
2929 | #define DCO_MEM_POWER_STATE_2__DPG_MEM_PWR_STATE_MASK 0x3 |
2930 | #define DCO_MEM_POWER_STATE_2__DPG_MEM_PWR_STATE__SHIFT 0x0 |
2931 | #define DCO_MEM_POWER_STATE_2__HDMI6_MEM_PWR_STATE_MASK 0xc |
2932 | #define DCO_MEM_POWER_STATE_2__HDMI6_MEM_PWR_STATE__SHIFT 0x2 |
2933 | #define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS_MASK 0x1 |
2934 | #define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x0 |
2935 | #define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE_MASK 0x2 |
2936 | #define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x1 |
2937 | #define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS_MASK 0x4 |
2938 | #define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS__SHIFT 0x2 |
2939 | #define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS_MASK 0x8 |
2940 | #define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS__SHIFT 0x3 |
2941 | #define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS_MASK 0x10 |
2942 | #define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS__SHIFT 0x4 |
2943 | #define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS_MASK 0x20 |
2944 | #define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS__SHIFT 0x5 |
2945 | #define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS_MASK 0x40 |
2946 | #define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS__SHIFT 0x6 |
2947 | #define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS_MASK 0x80 |
2948 | #define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS__SHIFT 0x7 |
2949 | #define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS_MASK 0x100 |
2950 | #define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS__SHIFT 0x8 |
2951 | #define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS_MASK 0x200 |
2952 | #define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS__SHIFT 0x9 |
2953 | #define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS_MASK 0x400 |
2954 | #define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS__SHIFT 0xa |
2955 | #define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS_MASK 0x800 |
2956 | #define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS__SHIFT 0xb |
2957 | #define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS_MASK 0x1000 |
2958 | #define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS__SHIFT 0xc |
2959 | #define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS_MASK 0x2000 |
2960 | #define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS__SHIFT 0xd |
2961 | #define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS_MASK 0x4000 |
2962 | #define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS__SHIFT 0xe |
2963 | #define DCO_LIGHT_SLEEP_DIS__HDMI6_LIGHT_SLEEP_DIS_MASK 0x8000 |
2964 | #define DCO_LIGHT_SLEEP_DIS__HDMI6_LIGHT_SLEEP_DIS__SHIFT 0xf |
2965 | #define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS_MASK 0x10000 |
2966 | #define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS__SHIFT 0x10 |
2967 | #define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS_MASK 0x20000 |
2968 | #define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS__SHIFT 0x11 |
2969 | #define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS_MASK 0x40000 |
2970 | #define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS__SHIFT 0x12 |
2971 | #define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS_MASK 0x80000 |
2972 | #define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS__SHIFT 0x13 |
2973 | #define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS_MASK 0x100000 |
2974 | #define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS__SHIFT 0x14 |
2975 | #define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS_MASK 0x200000 |
2976 | #define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS__SHIFT 0x15 |
2977 | #define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS_MASK 0x400000 |
2978 | #define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS__SHIFT 0x16 |
2979 | #define DCO_LIGHT_SLEEP_DIS__DPG_MEM_SHUTDOWN_DIS_MASK 0x800000 |
2980 | #define DCO_LIGHT_SLEEP_DIS__DPG_MEM_SHUTDOWN_DIS__SHIFT 0x17 |
2981 | #define DCO_LIGHT_SLEEP_DIS__DPG_LIGHT_SLEEP_DIS_MASK 0x1000000 |
2982 | #define DCO_LIGHT_SLEEP_DIS__DPG_LIGHT_SLEEP_DIS__SHIFT 0x18 |
2983 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x1 |
2984 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x0 |
2985 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x100 |
2986 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x8 |
2987 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x200 |
2988 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x9 |
2989 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x400 |
2990 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0xa |
2991 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0xf0000 |
2992 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x10 |
2993 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0xf00000 |
2994 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x14 |
2995 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0xf000000 |
2996 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x18 |
2997 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000 |
2998 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x1c |
2999 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000 |
3000 | #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x1e |
3001 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x1 |
3002 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x0 |
3003 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x100 |
3004 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x8 |
3005 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x200 |
3006 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x9 |
3007 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x400 |
3008 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0xa |
3009 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0xf0000 |
3010 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x10 |
3011 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0xf00000 |
3012 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x14 |
3013 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0xf000000 |
3014 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x18 |
3015 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000 |
3016 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x1c |
3017 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000 |
3018 | #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x1e |
3019 | #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffff |
3020 | #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x0 |
3021 | #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x1 |
3022 | #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x0 |
3023 | #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x100 |
3024 | #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x8 |
3025 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x200 |
3026 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x9 |
3027 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x400 |
3028 | #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0xa |
3029 | #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0xf0000 |
3030 | #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x10 |
3031 | #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0xf00000 |
3032 | #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x14 |
3033 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0xf000000 |
3034 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x18 |
3035 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 |
3036 | #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c |
3037 | #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x1 |
3038 | #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x0 |
3039 | #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x100 |
3040 | #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x8 |
3041 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x200 |
3042 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x9 |
3043 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x400 |
3044 | #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0xa |
3045 | #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0xf0000 |
3046 | #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x10 |
3047 | #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0xf00000 |
3048 | #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x14 |
3049 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0xf000000 |
3050 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x18 |
3051 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000 |
3052 | #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x1c |
3053 | #define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE_MASK 0xf |
3054 | #define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE__SHIFT 0x0 |
3055 | #define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET_MASK 0x20 |
3056 | #define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET__SHIFT 0x5 |
3057 | #define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS_MASK 0x300 |
3058 | #define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS__SHIFT 0x8 |
3059 | #define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE_MASK 0x7000 |
3060 | #define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE__SHIFT 0xc |
3061 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x7fff |
3062 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x0 |
3063 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000 |
3064 | #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x10 |
3065 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x1 |
3066 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x0 |
3067 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x100 |
3068 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x8 |
3069 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x200 |
3070 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x9 |
3071 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x400 |
3072 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0xa |
3073 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0xf0000 |
3074 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x10 |
3075 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0xf00000 |
3076 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x14 |
3077 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0xf000000 |
3078 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x18 |
3079 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000 |
3080 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x1c |
3081 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000 |
3082 | #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x1e |
3083 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x1 |
3084 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x0 |
3085 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x100 |
3086 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x8 |
3087 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x200 |
3088 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x9 |
3089 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x400 |
3090 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0xa |
3091 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0xf0000 |
3092 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x10 |
3093 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0xf00000 |
3094 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x14 |
3095 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0xf000000 |
3096 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x18 |
3097 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000 |
3098 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x1c |
3099 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000 |
3100 | #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x1e |
3101 | #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0xf |
3102 | #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x0 |
3103 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x20 |
3104 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x5 |
3105 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x300 |
3106 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x8 |
3107 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x7000 |
3108 | #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0xc |
3109 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x7fff |
3110 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x0 |
3111 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000 |
3112 | #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x10 |
3113 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x1 |
3114 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x0 |
3115 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x100 |
3116 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x8 |
3117 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x200 |
3118 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x9 |
3119 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x400 |
3120 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0xa |
3121 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0xf0000 |
3122 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x10 |
3123 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0xf00000 |
3124 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x14 |
3125 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0xf000000 |
3126 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x18 |
3127 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000 |
3128 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x1c |
3129 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000 |
3130 | #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x1e |
3131 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x1 |
3132 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x0 |
3133 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x100 |
3134 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x8 |
3135 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x200 |
3136 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x9 |
3137 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x400 |
3138 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0xa |
3139 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0xf0000 |
3140 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x10 |
3141 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0xf00000 |
3142 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x14 |
3143 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0xf000000 |
3144 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x18 |
3145 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000 |
3146 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x1c |
3147 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000 |
3148 | #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x1e |
3149 | #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0xf |
3150 | #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x0 |
3151 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x20 |
3152 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x5 |
3153 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x300 |
3154 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x8 |
3155 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x7000 |
3156 | #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0xc |
3157 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x7fff |
3158 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x0 |
3159 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000 |
3160 | #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x10 |
3161 | #define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x400 |
3162 | #define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0xa |
3163 | #define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_MASK 0x800 |
3164 | #define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE__SHIFT 0xb |
3165 | #define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x2000 |
3166 | #define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd |
3167 | #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0xc000 |
3168 | #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe |
3169 | #define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x10000 |
3170 | #define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 |
3171 | #define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x80000 |
3172 | #define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x13 |
3173 | #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x100000 |
3174 | #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x14 |
3175 | #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x200000 |
3176 | #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x15 |
3177 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x1 |
3178 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x0 |
3179 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x2 |
3180 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x1 |
3181 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x10 |
3182 | #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x4 |
3183 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x100 |
3184 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x8 |
3185 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x200 |
3186 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x9 |
3187 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x400 |
3188 | #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0xa |
3189 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x10000 |
3190 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x10 |
3191 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x20000 |
3192 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 |
3193 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x40000 |
3194 | #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 |
3195 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x1000000 |
3196 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x18 |
3197 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x2000000 |
3198 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x19 |
3199 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x4000000 |
3200 | #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x1a |
3201 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x1 |
3202 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x0 |
3203 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x2 |
3204 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x1 |
3205 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x4 |
3206 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x2 |
3207 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x8 |
3208 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x3 |
3209 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x10 |
3210 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x4 |
3211 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0xf00 |
3212 | #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x8 |
3213 | #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0xfff |
3214 | #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x0 |
3215 | #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000 |
3216 | #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x10 |
3217 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0xff |
3218 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x0 |
3219 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0xff00 |
3220 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x8 |
3221 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0xff0000 |
3222 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x10 |
3223 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000 |
3224 | #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x18 |
3225 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0xff |
3226 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x0 |
3227 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0xff00 |
3228 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x8 |
3229 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0xff0000 |
3230 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x10 |
3231 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x1000000 |
3232 | #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x18 |
3233 | #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0xffff |
3234 | #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x0 |
3235 | #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000 |
3236 | #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x1e |
3237 | #define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000 |
3238 | #define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x1f |
3239 | #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0xffff |
3240 | #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x0 |
3241 | #define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000 |
3242 | #define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x1c |
3243 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000 |
3244 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x1e |
3245 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000 |
3246 | #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x1f |
3247 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0xffff |
3248 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x0 |
3249 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0xf0000 |
3250 | #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x10 |
3251 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x1 |
3252 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x0 |
3253 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x100 |
3254 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x8 |
3255 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x10000 |
3256 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x10 |
3257 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0xe0000 |
3258 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x11 |
3259 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x1000000 |
3260 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x18 |
3261 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000 |
3262 | #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x1f |
3263 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x3 |
3264 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x0 |
3265 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x30 |
3266 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x4 |
3267 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x300 |
3268 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 |
3269 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x30000 |
3270 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x10 |
3271 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x300000 |
3272 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x14 |
3273 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x3000000 |
3274 | #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 |
3275 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x3 |
3276 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x0 |
3277 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x30 |
3278 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x4 |
3279 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x300 |
3280 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 |
3281 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x30000 |
3282 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x10 |
3283 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x300000 |
3284 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x14 |
3285 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x3000000 |
3286 | #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 |
3287 | #define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x7 |
3288 | #define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x0 |
3289 | #define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x700 |
3290 | #define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x8 |
3291 | #define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x70000 |
3292 | #define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x10 |
3293 | #define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x7 |
3294 | #define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x0 |
3295 | #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x700 |
3296 | #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x8 |
3297 | #define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x70000 |
3298 | #define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x10 |
3299 | #define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x7 |
3300 | #define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x0 |
3301 | #define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x700 |
3302 | #define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x8 |
3303 | #define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x70000 |
3304 | #define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x10 |
3305 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x7 |
3306 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 |
3307 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x70 |
3308 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 |
3309 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x700 |
3310 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 |
3311 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x7000 |
3312 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc |
3313 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x70000 |
3314 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 |
3315 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x700000 |
3316 | #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 |
3317 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x7 |
3318 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x0 |
3319 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x70 |
3320 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x4 |
3321 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x700 |
3322 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x8 |
3323 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x7000 |
3324 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0xc |
3325 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x70000 |
3326 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x10 |
3327 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x700000 |
3328 | #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x14 |
3329 | #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffff |
3330 | #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 |
3331 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x3f |
3332 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 |
3333 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x700 |
3334 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 |
3335 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x3800 |
3336 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb |
3337 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x1c000 |
3338 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe |
3339 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0xe0000 |
3340 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 |
3341 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x700000 |
3342 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 |
3343 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x3800000 |
3344 | #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 |
3345 | #define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x1f |
3346 | #define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x0 |
3347 | #define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x20 |
3348 | #define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x5 |
3349 | #define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x40 |
3350 | #define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x6 |
3351 | #define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x80 |
3352 | #define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x7 |
3353 | #define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x100 |
3354 | #define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x8 |
3355 | #define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x200 |
3356 | #define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x9 |
3357 | #define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS_MASK 0x1000 |
3358 | #define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS__SHIFT 0xc |
3359 | #define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x10000 |
3360 | #define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x10 |
3361 | #define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x20000 |
3362 | #define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x11 |
3363 | #define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x40000 |
3364 | #define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x12 |
3365 | #define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x80000 |
3366 | #define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x13 |
3367 | #define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x100000 |
3368 | #define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x14 |
3369 | #define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x200000 |
3370 | #define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x15 |
3371 | #define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x1000000 |
3372 | #define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x18 |
3373 | #define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x2000000 |
3374 | #define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x19 |
3375 | #define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x4000000 |
3376 | #define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x1a |
3377 | #define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x8000000 |
3378 | #define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x1b |
3379 | #define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000 |
3380 | #define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x1c |
3381 | #define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000 |
3382 | #define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x1d |
3383 | #define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK 0x40000000 |
3384 | #define DCO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT 0x1e |
3385 | #define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x20 |
3386 | #define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x5 |
3387 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x40 |
3388 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x6 |
3389 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x80 |
3390 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x7 |
3391 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x100 |
3392 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x8 |
3393 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x200 |
3394 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x9 |
3395 | #define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS_MASK 0x1000 |
3396 | #define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS__SHIFT 0xc |
3397 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x10000 |
3398 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x10 |
3399 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x20000 |
3400 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x11 |
3401 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x40000 |
3402 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x12 |
3403 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x80000 |
3404 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x13 |
3405 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x100000 |
3406 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x14 |
3407 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x200000 |
3408 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x15 |
3409 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x1000000 |
3410 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x18 |
3411 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x2000000 |
3412 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x19 |
3413 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x4000000 |
3414 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x1a |
3415 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x8000000 |
3416 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x1b |
3417 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000 |
3418 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x1c |
3419 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000 |
3420 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x1d |
3421 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS_MASK 0x40000000 |
3422 | #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGG_RAMP_DIS__SHIFT 0x1e |
3423 | #define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffff |
3424 | #define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0 |
3425 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX_MASK 0x7 |
3426 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE0_EXT_VSYNC_MUX__SHIFT 0x0 |
3427 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX_MASK 0x70 |
3428 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE1_EXT_VSYNC_MUX__SHIFT 0x4 |
3429 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX_MASK 0x700 |
3430 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE2_EXT_VSYNC_MUX__SHIFT 0x8 |
3431 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX_MASK 0x7000 |
3432 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE3_EXT_VSYNC_MUX__SHIFT 0xc |
3433 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX_MASK 0x70000 |
3434 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE4_EXT_VSYNC_MUX__SHIFT 0x10 |
3435 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX_MASK 0x700000 |
3436 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_DCFE5_EXT_VSYNC_MUX__SHIFT 0x14 |
3437 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK_MASK 0x7000000 |
3438 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_SWAPLOCKB_EXT_VSYNC_MASK__SHIFT 0x18 |
3439 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK_MASK 0x70000000 |
3440 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_GENERICB_EXT_VSYNC_MASK__SHIFT 0x1c |
3441 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL_MASK 0x80000000 |
3442 | #define DCO_DCFE_EXT_VSYNC_CNTL__DCO_CRTC_MANUAL_FLOW_CONTROL__SHIFT 0x1f |
3443 | #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0xff |
3444 | #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0 |
3445 | #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x100 |
3446 | #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
3447 | #define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffff |
3448 | #define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0 |
3449 | #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x3 |
3450 | #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x0 |
3451 | #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0xc |
3452 | #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x2 |
3453 | #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x30 |
3454 | #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x4 |
3455 | #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_MASK 0xc0 |
3456 | #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0__SHIFT 0x6 |
3457 | #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0_MASK 0x300 |
3458 | #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x8 |
3459 | #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_MASK 0xc00 |
3460 | #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN__SHIFT 0xa |
3461 | #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C_MASK 0x1000 |
3462 | #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C__SHIFT 0xc |
3463 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG_MASK 0x2000 |
3464 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG__SHIFT 0xd |
3465 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x4000 |
3466 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0xe |
3467 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_MASK 0x8000 |
3468 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0__SHIFT 0xf |
3469 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG_MASK 0x10000 |
3470 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG__SHIFT 0x10 |
3471 | #define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE_MASK 0x20000 |
3472 | #define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x11 |
3473 | #define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE_MASK 0x40000 |
3474 | #define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE__SHIFT 0x12 |
3475 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x80000 |
3476 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x13 |
3477 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_MASK 0x100000 |
3478 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN__SHIFT 0x14 |
3479 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX_MASK 0x200000 |
3480 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX__SHIFT 0x15 |
3481 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG_MASK 0x400000 |
3482 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x16 |
3483 | #define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE_MASK 0x800000 |
3484 | #define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE__SHIFT 0x17 |
3485 | #define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE_MASK 0x1000000 |
3486 | #define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x18 |
3487 | #define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL_MASK 0x2000000 |
3488 | #define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL__SHIFT 0x19 |
3489 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x4000000 |
3490 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x1a |
3491 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_MASK 0x8000000 |
3492 | #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0__SHIFT 0x1b |
3493 | #define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffff |
3494 | #define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x0 |
3495 | #define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffff |
3496 | #define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x0 |
3497 | #define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffff |
3498 | #define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x0 |
3499 | #define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffff |
3500 | #define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x0 |
3501 | #define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffff |
3502 | #define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x0 |
3503 | #define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffff |
3504 | #define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x0 |
3505 | #define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffff |
3506 | #define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x0 |
3507 | #define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffff |
3508 | #define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x0 |
3509 | #define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffff |
3510 | #define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x0 |
3511 | #define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffff |
3512 | #define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x0 |
3513 | #define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffff |
3514 | #define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x0 |
3515 | #define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffff |
3516 | #define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x0 |
3517 | #define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffff |
3518 | #define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x0 |
3519 | #define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffff |
3520 | #define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x0 |
3521 | #define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffff |
3522 | #define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x0 |
3523 | #define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffff |
3524 | #define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x0 |
3525 | #define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffff |
3526 | #define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x0 |
3527 | #define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffff |
3528 | #define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x0 |
3529 | #define DCIO_DEBUG14__DCIO_DIGG_DEBUG_MASK 0xffffffff |
3530 | #define DCIO_DEBUG14__DCIO_DIGG_DEBUG__SHIFT 0x0 |
3531 | #define DCIO_DEBUG15__DCIO_DEBUG15_MASK 0xffffffff |
3532 | #define DCIO_DEBUG15__DCIO_DEBUG15__SHIFT 0x0 |
3533 | #define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffff |
3534 | #define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x0 |
3535 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x1 |
3536 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x0 |
3537 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x2 |
3538 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x1 |
3539 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x4 |
3540 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x2 |
3541 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x10 |
3542 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x4 |
3543 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x20 |
3544 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x5 |
3545 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x40 |
3546 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x6 |
3547 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x100 |
3548 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x8 |
3549 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x200 |
3550 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x9 |
3551 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x400 |
3552 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0xa |
3553 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x1000 |
3554 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0xc |
3555 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x2000 |
3556 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0xd |
3557 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x4000 |
3558 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0xe |
3559 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x10000 |
3560 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x10 |
3561 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x20000 |
3562 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x11 |
3563 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x40000 |
3564 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x12 |
3565 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x100000 |
3566 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x14 |
3567 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x200000 |
3568 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x15 |
3569 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x400000 |
3570 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x16 |
3571 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x1000000 |
3572 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x18 |
3573 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x2000000 |
3574 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x19 |
3575 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x4000000 |
3576 | #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x1a |
3577 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x1 |
3578 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x0 |
3579 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x100 |
3580 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x8 |
3581 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x10000 |
3582 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x10 |
3583 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x100000 |
3584 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x14 |
3585 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x200000 |
3586 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x15 |
3587 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x400000 |
3588 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x16 |
3589 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x800000 |
3590 | #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x17 |
3591 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x1 |
3592 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x0 |
3593 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x100 |
3594 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x8 |
3595 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x10000 |
3596 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x10 |
3597 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x100000 |
3598 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x14 |
3599 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x200000 |
3600 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x15 |
3601 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x400000 |
3602 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x16 |
3603 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x800000 |
3604 | #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x17 |
3605 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x1 |
3606 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x0 |
3607 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x100 |
3608 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x8 |
3609 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x10000 |
3610 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x10 |
3611 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x100000 |
3612 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x14 |
3613 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x200000 |
3614 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x15 |
3615 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x400000 |
3616 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x16 |
3617 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x800000 |
3618 | #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x17 |
3619 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0xffffff |
3620 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x0 |
3621 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x1f000000 |
3622 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x18 |
3623 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x20000000 |
3624 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x1d |
3625 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000 |
3626 | #define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x1e |
3627 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0xffffff |
3628 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x0 |
3629 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x1f000000 |
3630 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x18 |
3631 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x20000000 |
3632 | #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x1d |
3633 | #define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000 |
3634 | #define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x1e |
3635 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0xffffff |
3636 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x0 |
3637 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x1f000000 |
3638 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x18 |
3639 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x20000000 |
3640 | #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x1d |
3641 | #define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000 |
3642 | #define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x1e |
3643 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0xffffff |
3644 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x0 |
3645 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x1f000000 |
3646 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x18 |
3647 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x20000000 |
3648 | #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x1d |
3649 | #define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000 |
3650 | #define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x1e |
3651 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x1 |
3652 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 |
3653 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x10 |
3654 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 |
3655 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x40 |
3656 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 |
3657 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x100 |
3658 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 |
3659 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x1000 |
3660 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc |
3661 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x4000 |
3662 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe |
3663 | #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x10000 |
3664 | #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 |
3665 | #define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x100000 |
3666 | #define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 |
3667 | #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x400000 |
3668 | #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 |
3669 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0xf000000 |
3670 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x18 |
3671 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000 |
3672 | #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x1c |
3673 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x1 |
3674 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 |
3675 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x100 |
3676 | #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 |
3677 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x1 |
3678 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 |
3679 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x100 |
3680 | #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 |
3681 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x1 |
3682 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 |
3683 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x100 |
3684 | #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 |
3685 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x1 |
3686 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 |
3687 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x10 |
3688 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 |
3689 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x40 |
3690 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 |
3691 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x100 |
3692 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 |
3693 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x1000 |
3694 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc |
3695 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x4000 |
3696 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe |
3697 | #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x10000 |
3698 | #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 |
3699 | #define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x100000 |
3700 | #define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 |
3701 | #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x400000 |
3702 | #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 |
3703 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0xf000000 |
3704 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x18 |
3705 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000 |
3706 | #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x1c |
3707 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x1 |
3708 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 |
3709 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x100 |
3710 | #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 |
3711 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x1 |
3712 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 |
3713 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x100 |
3714 | #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 |
3715 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x1 |
3716 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 |
3717 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x100 |
3718 | #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 |
3719 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x1 |
3720 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 |
3721 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x10 |
3722 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 |
3723 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x40 |
3724 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 |
3725 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x100 |
3726 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 |
3727 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x1000 |
3728 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc |
3729 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x4000 |
3730 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe |
3731 | #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x10000 |
3732 | #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 |
3733 | #define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x100000 |
3734 | #define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 |
3735 | #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x400000 |
3736 | #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 |
3737 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0xf000000 |
3738 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x18 |
3739 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000 |
3740 | #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x1c |
3741 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x1 |
3742 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 |
3743 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x100 |
3744 | #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 |
3745 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x1 |
3746 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 |
3747 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x100 |
3748 | #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 |
3749 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x1 |
3750 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 |
3751 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x100 |
3752 | #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 |
3753 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x1 |
3754 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 |
3755 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x10 |
3756 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 |
3757 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x40 |
3758 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 |
3759 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x100 |
3760 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 |
3761 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x1000 |
3762 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc |
3763 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x4000 |
3764 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe |
3765 | #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x10000 |
3766 | #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 |
3767 | #define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x100000 |
3768 | #define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 |
3769 | #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x400000 |
3770 | #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 |
3771 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0xf000000 |
3772 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x18 |
3773 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000 |
3774 | #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x1c |
3775 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x1 |
3776 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 |
3777 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x100 |
3778 | #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 |
3779 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x1 |
3780 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 |
3781 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x100 |
3782 | #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 |
3783 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x1 |
3784 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 |
3785 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x100 |
3786 | #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 |
3787 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x1 |
3788 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 |
3789 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x10 |
3790 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 |
3791 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x40 |
3792 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 |
3793 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x100 |
3794 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 |
3795 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x1000 |
3796 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc |
3797 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x4000 |
3798 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe |
3799 | #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x10000 |
3800 | #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 |
3801 | #define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x100000 |
3802 | #define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 |
3803 | #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x400000 |
3804 | #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 |
3805 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0xf000000 |
3806 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x18 |
3807 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000 |
3808 | #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x1c |
3809 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x1 |
3810 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 |
3811 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x100 |
3812 | #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 |
3813 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x1 |
3814 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 |
3815 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x100 |
3816 | #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 |
3817 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x1 |
3818 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 |
3819 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x100 |
3820 | #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 |
3821 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x1 |
3822 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x0 |
3823 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x10 |
3824 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x4 |
3825 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x40 |
3826 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x6 |
3827 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x100 |
3828 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x8 |
3829 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x1000 |
3830 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0xc |
3831 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x4000 |
3832 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0xe |
3833 | #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x10000 |
3834 | #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x10 |
3835 | #define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x100000 |
3836 | #define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x14 |
3837 | #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x400000 |
3838 | #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x16 |
3839 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0xf000000 |
3840 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x18 |
3841 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000 |
3842 | #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x1c |
3843 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x1 |
3844 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x0 |
3845 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x100 |
3846 | #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x8 |
3847 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x1 |
3848 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x0 |
3849 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x100 |
3850 | #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x8 |
3851 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x1 |
3852 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x0 |
3853 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x100 |
3854 | #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x8 |
3855 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x1 |
3856 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 |
3857 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x40 |
3858 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 |
3859 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x100 |
3860 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 |
3861 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x1000 |
3862 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc |
3863 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x4000 |
3864 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe |
3865 | #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x10000 |
3866 | #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x10 |
3867 | #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x100000 |
3868 | #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x14 |
3869 | #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x400000 |
3870 | #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 |
3871 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0xf000000 |
3872 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x18 |
3873 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000 |
3874 | #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c |
3875 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x1 |
3876 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 |
3877 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x100 |
3878 | #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 |
3879 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x1 |
3880 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 |
3881 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x100 |
3882 | #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 |
3883 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x1 |
3884 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 |
3885 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x100 |
3886 | #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 |
3887 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x1 |
3888 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x0 |
3889 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x10 |
3890 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x4 |
3891 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x40 |
3892 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x6 |
3893 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x100 |
3894 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x8 |
3895 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x1000 |
3896 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0xc |
3897 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x4000 |
3898 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0xe |
3899 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x7000000 |
3900 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x18 |
3901 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000 |
3902 | #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x1c |
3903 | #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x1 |
3904 | #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x0 |
3905 | #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x100 |
3906 | #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x8 |
3907 | #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x1 |
3908 | #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x0 |
3909 | #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x100 |
3910 | #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x8 |
3911 | #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x1 |
3912 | #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x0 |
3913 | #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x100 |
3914 | #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x8 |
3915 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x1 |
3916 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x0 |
3917 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x2 |
3918 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x1 |
3919 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x4 |
3920 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x2 |
3921 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x8 |
3922 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x3 |
3923 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x100 |
3924 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x8 |
3925 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x200 |
3926 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x9 |
3927 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x400 |
3928 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0xa |
3929 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x800 |
3930 | #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0xb |
3931 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x10000 |
3932 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x10 |
3933 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x20000 |
3934 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x11 |
3935 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x40000 |
3936 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x12 |
3937 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x80000 |
3938 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x13 |
3939 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x1000000 |
3940 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x18 |
3941 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x2000000 |
3942 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x19 |
3943 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x4000000 |
3944 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x1a |
3945 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x8000000 |
3946 | #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x1b |
3947 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x1 |
3948 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x0 |
3949 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x100 |
3950 | #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x8 |
3951 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x10000 |
3952 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x10 |
3953 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x1000000 |
3954 | #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x18 |
3955 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x1 |
3956 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x0 |
3957 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x100 |
3958 | #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x8 |
3959 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x10000 |
3960 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x10 |
3961 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x1000000 |
3962 | #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x18 |
3963 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x1 |
3964 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x0 |
3965 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x100 |
3966 | #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x8 |
3967 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x10000 |
3968 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x10 |
3969 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x1000000 |
3970 | #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x18 |
3971 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x1 |
3972 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x0 |
3973 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x10 |
3974 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x4 |
3975 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x40 |
3976 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x6 |
3977 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x100 |
3978 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x8 |
3979 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x200 |
3980 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x9 |
3981 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x400 |
3982 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0xa |
3983 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x10000 |
3984 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x10 |
3985 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x20000 |
3986 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x11 |
3987 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x40000 |
3988 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x12 |
3989 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x100000 |
3990 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x14 |
3991 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x200000 |
3992 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x15 |
3993 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x400000 |
3994 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x16 |
3995 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x1000000 |
3996 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x18 |
3997 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x2000000 |
3998 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x19 |
3999 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x4000000 |
4000 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x1a |
4001 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000 |
4002 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x1c |
4003 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000 |
4004 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x1d |
4005 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000 |
4006 | #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x1e |
4007 | #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x1 |
4008 | #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x0 |
4009 | #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x100 |
4010 | #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x8 |
4011 | #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x10000 |
4012 | #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x10 |
4013 | #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x1000000 |
4014 | #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x18 |
4015 | #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x4000000 |
4016 | #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x1a |
4017 | #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000 |
4018 | #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x1c |
4019 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x1 |
4020 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x0 |
4021 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x100 |
4022 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x8 |
4023 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x10000 |
4024 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x10 |
4025 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x1000000 |
4026 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x18 |
4027 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x4000000 |
4028 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x1a |
4029 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000 |
4030 | #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x1c |
4031 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x1 |
4032 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x0 |
4033 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x100 |
4034 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x8 |
4035 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x10000 |
4036 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x10 |
4037 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x1000000 |
4038 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x18 |
4039 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x4000000 |
4040 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x1a |
4041 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000 |
4042 | #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x1c |
4043 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x1 |
4044 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x0 |
4045 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x10 |
4046 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x4 |
4047 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x40 |
4048 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x6 |
4049 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x100 |
4050 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x8 |
4051 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x1000 |
4052 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0xc |
4053 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x4000 |
4054 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0xe |
4055 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x10000 |
4056 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x10 |
4057 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x100000 |
4058 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x14 |
4059 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x400000 |
4060 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x16 |
4061 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK_MASK 0x1000000 |
4062 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_MASK__SHIFT 0x18 |
4063 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS_MASK 0x2000000 |
4064 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_PD_DIS__SHIFT 0x19 |
4065 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV_MASK 0x4000000 |
4066 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_VSYNC_IN_RECV__SHIFT 0x1a |
4067 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK_MASK 0x10000000 |
4068 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_MASK__SHIFT 0x1c |
4069 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS_MASK 0x20000000 |
4070 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_PD_DIS__SHIFT 0x1d |
4071 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV_MASK 0x40000000 |
4072 | #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_HSYNC_IN_RECV__SHIFT 0x1e |
4073 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x1 |
4074 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x0 |
4075 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x100 |
4076 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x8 |
4077 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x10000 |
4078 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x10 |
4079 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A_MASK 0x1000000 |
4080 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_VSYNC_IN_A__SHIFT 0x18 |
4081 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A_MASK 0x80000000 |
4082 | #define DC_GPIO_PWRSEQ_A__DC_GPIO_HSYNC_IN_A__SHIFT 0x1f |
4083 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x1 |
4084 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x0 |
4085 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x2 |
4086 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1 |
4087 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x100 |
4088 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x8 |
4089 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x10000 |
4090 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x10 |
4091 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN_MASK 0x1000000 |
4092 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VSYNC_IN_EN__SHIFT 0x18 |
4093 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN_MASK 0x80000000 |
4094 | #define DC_GPIO_PWRSEQ_EN__DC_GPIO_HSYNC_IN_EN__SHIFT 0x1f |
4095 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x1 |
4096 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x0 |
4097 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x100 |
4098 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x8 |
4099 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x10000 |
4100 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x10 |
4101 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN_MASK 0x1000000 |
4102 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_VSYNC_IN__SHIFT 0x18 |
4103 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN_MASK 0x80000000 |
4104 | #define DC_GPIO_PWRSEQ_Y__DC_GPIO_HSYNC_IN__SHIFT 0x1f |
4105 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0xf |
4106 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 |
4107 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0xf0 |
4108 | #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 |
4109 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0xf000000 |
4110 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 |
4111 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000 |
4112 | #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c |
4113 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0xf |
4114 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x0 |
4115 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0xf0 |
4116 | #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x4 |
4117 | #define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK 0x700 |
4118 | #define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT 0x8 |
4119 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK 0x7000 |
4120 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT 0xc |
4121 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0xf0000 |
4122 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x10 |
4123 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0xf00000 |
4124 | #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x14 |
4125 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK 0xc0000000 |
4126 | #define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT 0x1e |
4127 | #define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x1000 |
4128 | #define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0xc |
4129 | #define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x4000 |
4130 | #define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0xe |
4131 | #define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x10000 |
4132 | #define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x10 |
4133 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x1 |
4134 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x0 |
4135 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x2 |
4136 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x1 |
4137 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x4 |
4138 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x2 |
4139 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x10 |
4140 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x4 |
4141 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x20 |
4142 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x5 |
4143 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x40 |
4144 | #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x6 |
4145 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x1 |
4146 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x0 |
4147 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x2 |
4148 | #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x1 |
4149 | #define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x1 |
4150 | #define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x0 |
4151 | #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x2 |
4152 | #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x1 |
4153 | #define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x1 |
4154 | #define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x0 |
4155 | #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x2 |
4156 | #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x1 |
4157 | #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0xf |
4158 | #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x0 |
4159 | #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0xf0 |
4160 | #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x4 |
4161 | #define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0xf |
4162 | #define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x0 |
4163 | #define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0xf0 |
4164 | #define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x4 |
4165 | #define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0xf00 |
4166 | #define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x8 |
4167 | #define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0xf000 |
4168 | #define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0xc |
4169 | #define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH_MASK 0x70000 |
4170 | #define DVO_STRENGTH_CONTROL__DVO_DRVSTRENGTH__SHIFT 0x10 |
4171 | #define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH_MASK 0x700000 |
4172 | #define DVO_STRENGTH_CONTROL__DVOCLK_DRVSTRENGTH__SHIFT 0x14 |
4173 | #define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH_MASK 0x7000000 |
4174 | #define DVO_STRENGTH_CONTROL__FLDO_VITNE_DRVSTRENGTH__SHIFT 0x18 |
4175 | #define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000 |
4176 | #define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x1c |
4177 | #define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000 |
4178 | #define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x1d |
4179 | #define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x1 |
4180 | #define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x0 |
4181 | #define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x2 |
4182 | #define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x1 |
4183 | #define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0xf0 |
4184 | #define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x4 |
4185 | #define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffff |
4186 | #define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x0 |
4187 | #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN_MASK 0x3ff |
4188 | #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN__SHIFT 0x0 |
4189 | #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN_MASK 0x10000 |
4190 | #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN__SHIFT 0x10 |
4191 | #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL_MASK 0xe0000 |
4192 | #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL__SHIFT 0x11 |
4193 | #define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED_MASK 0x7fffff |
4194 | #define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED__SHIFT 0x0 |
4195 | #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN_MASK 0x3ff |
4196 | #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN__SHIFT 0x0 |
4197 | #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN_MASK 0x10000 |
4198 | #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN__SHIFT 0x10 |
4199 | #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL_MASK 0xe0000 |
4200 | #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT 0x11 |
4201 | #define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED_MASK 0x7fffff |
4202 | #define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED__SHIFT 0x0 |
4203 | #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN_MASK 0x3ff |
4204 | #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN__SHIFT 0x0 |
4205 | #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN_MASK 0x10000 |
4206 | #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN__SHIFT 0x10 |
4207 | #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL_MASK 0xe0000 |
4208 | #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL__SHIFT 0x11 |
4209 | #define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED_MASK 0x7fffff |
4210 | #define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED__SHIFT 0x0 |
4211 | #define UNIPHYGH_TPG_CONTROL__UNIPHYGH_STATIC_TEST_PATTERN_MASK 0x3ff |
4212 | #define UNIPHYGH_TPG_CONTROL__UNIPHYGH_STATIC_TEST_PATTERN__SHIFT 0x0 |
4213 | #define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_EN_MASK 0x10000 |
4214 | #define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_EN__SHIFT 0x10 |
4215 | #define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_SEL_MASK 0xe0000 |
4216 | #define UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_SEL__SHIFT 0x11 |
4217 | #define UNIPHYGH_TPG_SEED__UNIPHYGH_TPG_SEED_MASK 0x7fffff |
4218 | #define UNIPHYGH_TPG_SEED__UNIPHYGH_TPG_SEED__SHIFT 0x0 |
4219 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK_MASK 0xf |
4220 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA0_MASK__SHIFT 0x0 |
4221 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK_MASK 0x10 |
4222 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK0_MASK__SHIFT 0x4 |
4223 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK_MASK 0x20 |
4224 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK0_MASK__SHIFT 0x5 |
4225 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK_MASK 0x40 |
4226 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK0_MASK__SHIFT 0x6 |
4227 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK_MASK 0x80 |
4228 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF0_MASK__SHIFT 0x7 |
4229 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK_MASK 0x100 |
4230 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_I2SDATA1_MASK__SHIFT 0x8 |
4231 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK_MASK 0x200 |
4232 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_MCLK1_MASK__SHIFT 0x9 |
4233 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK_MASK 0x400 |
4234 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_BCLK1_MASK__SHIFT 0xa |
4235 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK_MASK 0x800 |
4236 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_LRCK1_MASK__SHIFT 0xb |
4237 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK_MASK 0x1000 |
4238 | #define DC_GPIO_I2S_SPDIF_MASK__DC_GPIO_SPDIF1_MASK__SHIFT 0xc |
4239 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A_MASK 0xf |
4240 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA0_A__SHIFT 0x0 |
4241 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A_MASK 0x10 |
4242 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK0_A__SHIFT 0x4 |
4243 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A_MASK 0x20 |
4244 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK0_A__SHIFT 0x5 |
4245 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A_MASK 0x40 |
4246 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK0_A__SHIFT 0x6 |
4247 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A_MASK 0x80 |
4248 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF0_A__SHIFT 0x7 |
4249 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A_MASK 0x100 |
4250 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_I2SDATA1_A__SHIFT 0x8 |
4251 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A_MASK 0x200 |
4252 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_MCLK1_A__SHIFT 0x9 |
4253 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A_MASK 0x400 |
4254 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_BCLK1_A__SHIFT 0xa |
4255 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A_MASK 0x800 |
4256 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_LRCK1_A__SHIFT 0xb |
4257 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A_MASK 0x1000 |
4258 | #define DC_GPIO_I2S_SPDIF_A__DC_GPIO_SPDIF1_A__SHIFT 0xc |
4259 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN_MASK 0xf |
4260 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA0_EN__SHIFT 0x0 |
4261 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN_MASK 0x10 |
4262 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK0_EN__SHIFT 0x4 |
4263 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN_MASK 0x20 |
4264 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK0_EN__SHIFT 0x5 |
4265 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN_MASK 0x40 |
4266 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK0_EN__SHIFT 0x6 |
4267 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN_MASK 0x80 |
4268 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF0_EN__SHIFT 0x7 |
4269 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN_MASK 0x100 |
4270 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_I2SDATA1_EN__SHIFT 0x8 |
4271 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN_MASK 0x200 |
4272 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_MCLK1_EN__SHIFT 0x9 |
4273 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN_MASK 0x400 |
4274 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_BCLK1_EN__SHIFT 0xa |
4275 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN_MASK 0x800 |
4276 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_LRCK1_EN__SHIFT 0xb |
4277 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN_MASK 0x1000 |
4278 | #define DC_GPIO_I2S_SPDIF_EN__DC_GPIO_SPDIF1_EN__SHIFT 0xc |
4279 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y_MASK 0xf |
4280 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA0_Y__SHIFT 0x0 |
4281 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y_MASK 0x10 |
4282 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK0_Y__SHIFT 0x4 |
4283 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y_MASK 0x20 |
4284 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK0_Y__SHIFT 0x5 |
4285 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y_MASK 0x40 |
4286 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK0_Y__SHIFT 0x6 |
4287 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y_MASK 0x80 |
4288 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF0_Y__SHIFT 0x7 |
4289 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y_MASK 0x100 |
4290 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_I2SDATA1_Y__SHIFT 0x8 |
4291 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y_MASK 0x200 |
4292 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_MCLK1_Y__SHIFT 0x9 |
4293 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y_MASK 0x400 |
4294 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_BCLK1_Y__SHIFT 0xa |
4295 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y_MASK 0x800 |
4296 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_LRCK1_Y__SHIFT 0xb |
4297 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y_MASK 0x1000 |
4298 | #define DC_GPIO_I2S_SPDIF_Y__DC_GPIO_SPDIF1_Y__SHIFT 0xc |
4299 | #define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH_MASK 0x7 |
4300 | #define DC_GPIO_I2S_SPDIF_STRENGTH__I2S0_DRVSTRENGTH__SHIFT 0x0 |
4301 | #define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH_MASK 0x700 |
4302 | #define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF0_DRVSTRENGTH__SHIFT 0x8 |
4303 | #define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH_MASK 0x70000 |
4304 | #define DC_GPIO_I2S_SPDIF_STRENGTH__I2S1_DRVSTRENGTH__SHIFT 0x10 |
4305 | #define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH_MASK 0x7000000 |
4306 | #define DC_GPIO_I2S_SPDIF_STRENGTH__SPDIF1_DRVSTRENGTH__SHIFT 0x18 |
4307 | #define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff |
4308 | #define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 |
4309 | #define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff |
4310 | #define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 |
4311 | #define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff |
4312 | #define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 |
4313 | #define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffff |
4314 | #define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x0 |
4315 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x7 |
4316 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x0 |
4317 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x70 |
4318 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x4 |
4319 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x700 |
4320 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x8 |
4321 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x7000 |
4322 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0xc |
4323 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x70000 |
4324 | #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x10 |
4325 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x300000 |
4326 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x14 |
4327 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0xc00000 |
4328 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x16 |
4329 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x3000000 |
4330 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x18 |
4331 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0xc000000 |
4332 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x1a |
4333 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000 |
4334 | #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x1c |
4335 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x3 |
4336 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x0 |
4337 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x30 |
4338 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x4 |
4339 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x300 |
4340 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x8 |
4341 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x3000 |
4342 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0xc |
4343 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x30000 |
4344 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x10 |
4345 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x100000 |
4346 | #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x14 |
4347 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x600000 |
4348 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x15 |
4349 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x1800000 |
4350 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x17 |
4351 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x6000000 |
4352 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x19 |
4353 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000 |
4354 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x1b |
4355 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000 |
4356 | #define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x1d |
4357 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x3 |
4358 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x0 |
4359 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0xc |
4360 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x2 |
4361 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0xf0 |
4362 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x4 |
4363 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0xf00 |
4364 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x8 |
4365 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0x7000 |
4366 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0xc |
4367 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0x70000 |
4368 | #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x10 |
4369 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x100000 |
4370 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x14 |
4371 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x200000 |
4372 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x15 |
4373 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x400000 |
4374 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x16 |
4375 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x800000 |
4376 | #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x17 |
4377 | #define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000 |
4378 | #define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x18 |
4379 | #define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000 |
4380 | #define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x1f |
4381 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x1f |
4382 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x0 |
4383 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x3e0 |
4384 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x5 |
4385 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x1f000 |
4386 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0xc |
4387 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x3e0000 |
4388 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x11 |
4389 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x7000000 |
4390 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x18 |
4391 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000 |
4392 | #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x1c |
4393 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x1 |
4394 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x0 |
4395 | #define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x2 |
4396 | #define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x1 |
4397 | #define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0x4 |
4398 | #define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x2 |
4399 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0xf00 |
4400 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x8 |
4401 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0xf000 |
4402 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0xc |
4403 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0xf0000 |
4404 | #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x10 |
4405 | #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0xfffc |
4406 | #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x2 |
4407 | #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0xfff0000 |
4408 | #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x10 |
4409 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x1 |
4410 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x0 |
4411 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x2 |
4412 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x1 |
4413 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x4 |
4414 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x2 |
4415 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x8 |
4416 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x3 |
4417 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0xf0 |
4418 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x4 |
4419 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x7f00 |
4420 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x8 |
4421 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0xff0000 |
4422 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x10 |
4423 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x1000000 |
4424 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x18 |
4425 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x2000000 |
4426 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x19 |
4427 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x4000000 |
4428 | #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x1a |
4429 | #define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000 |
4430 | #define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x1c |
4431 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x3 |
4432 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x0 |
4433 | #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0xc |
4434 | #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x2 |
4435 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x10 |
4436 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x4 |
4437 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x20 |
4438 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x5 |
4439 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x40 |
4440 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x6 |
4441 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x700 |
4442 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x8 |
4443 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x800 |
4444 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0xb |
4445 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x1000 |
4446 | #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0xc |
4447 | #define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x2000 |
4448 | #define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0xd |
4449 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x10000 |
4450 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x10 |
4451 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x80000 |
4452 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x13 |
4453 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x100000 |
4454 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x14 |
4455 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000 |
4456 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x18 |
4457 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000 |
4458 | #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x1d |
4459 | #define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x3ffffff |
4460 | #define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x0 |
4461 | #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0xfff |
4462 | #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x0 |
4463 | #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x1000 |
4464 | #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0xc |
4465 | #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x2000 |
4466 | #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0xd |
4467 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x1 |
4468 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x0 |
4469 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x30 |
4470 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x4 |
4471 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x40 |
4472 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x6 |
4473 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x100 |
4474 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x8 |
4475 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE_MASK 0x1000 |
4476 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE__SHIFT 0xc |
4477 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x10000 |
4478 | #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x10 |
4479 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x1f |
4480 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x0 |
4481 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK 0x1e0 |
4482 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT 0x5 |
4483 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK 0x200 |
4484 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT 0x9 |
4485 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK 0x400 |
4486 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT 0xa |
4487 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x8000 |
4488 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0xf |
4489 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x10000 |
4490 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x10 |
4491 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x20000 |
4492 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x11 |
4493 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x1f00000 |
4494 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x14 |
4495 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0xe000000 |
4496 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x19 |
4497 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK_MASK 0x10000000 |
4498 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK__SHIFT 0x1c |
4499 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000 |
4500 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x1d |
4501 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK 0x40000000 |
4502 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT 0x1e |
4503 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK 0x80000000 |
4504 | #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT 0x1f |
4505 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x1 |
4506 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x0 |
4507 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x2 |
4508 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x1 |
4509 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0xf00 |
4510 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x8 |
4511 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x1f0000 |
4512 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x10 |
4513 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x1000000 |
4514 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x18 |
4515 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK 0x2000000 |
4516 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT 0x19 |
4517 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK 0x4000000 |
4518 | #define UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT 0x1a |
4519 | #define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x1 |
4520 | #define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x0 |
4521 | #define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x10 |
4522 | #define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x4 |
4523 | #define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x700 |
4524 | #define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x8 |
4525 | #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x1000 |
4526 | #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc |
4527 | #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x2000 |
4528 | #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd |
4529 | #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x4000 |
4530 | #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe |
4531 | #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x8000 |
4532 | #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf |
4533 | #define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x30000 |
4534 | #define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x10 |
4535 | #define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x700000 |
4536 | #define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x14 |
4537 | #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x3 |
4538 | #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 |
4539 | #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x300 |
4540 | #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 |
4541 | #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x30000 |
4542 | #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 |
4543 | #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x3000000 |
4544 | #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 |
4545 | #define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK 0xffff |
4546 | #define UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT 0x0 |
4547 | #define GRPH_ENABLE__GRPH_ENABLE_MASK 0x1 |
4548 | #define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x0 |
4549 | #define GRPH_CONTROL__GRPH_DEPTH_MASK 0x3 |
4550 | #define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x0 |
4551 | #define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0xc |
4552 | #define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x2 |
4553 | #define GRPH_CONTROL__GRPH_Z_MASK 0x30 |
4554 | #define GRPH_CONTROL__GRPH_Z__SHIFT 0x4 |
4555 | #define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0xc0 |
4556 | #define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x6 |
4557 | #define GRPH_CONTROL__GRPH_FORMAT_MASK 0x700 |
4558 | #define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x8 |
4559 | #define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x1800 |
4560 | #define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0xb |
4561 | #define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0xe000 |
4562 | #define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0xd |
4563 | #define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 |
4564 | #define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 |
4565 | #define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 |
4566 | #define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 |
4567 | #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0xc0000 |
4568 | #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x12 |
4569 | #define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0xf00000 |
4570 | #define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x14 |
4571 | #define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000 |
4572 | #define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x18 |
4573 | #define GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK 0x60000000 |
4574 | #define GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT 0x1d |
4575 | #define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000 |
4576 | #define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x1f |
4577 | #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x100 |
4578 | #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x8 |
4579 | #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x10000 |
4580 | #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x10 |
4581 | #define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x3 |
4582 | #define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x0 |
4583 | #define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x30 |
4584 | #define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x4 |
4585 | #define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0xc0 |
4586 | #define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x6 |
4587 | #define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x300 |
4588 | #define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x8 |
4589 | #define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0xc00 |
4590 | #define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0xa |
4591 | #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x1 |
4592 | #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x0 |
4593 | #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00 |
4594 | #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x8 |
4595 | #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x1 |
4596 | #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x0 |
4597 | #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00 |
4598 | #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8 |
4599 | #define GRPH_PITCH__GRPH_PITCH_MASK 0x7fff |
4600 | #define GRPH_PITCH__GRPH_PITCH__SHIFT 0x0 |
4601 | #define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0xff |
4602 | #define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
4603 | #define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff |
4604 | #define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
4605 | #define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x3fff |
4606 | #define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x0 |
4607 | #define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x3fff |
4608 | #define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x0 |
4609 | #define GRPH_X_START__GRPH_X_START_MASK 0x3fff |
4610 | #define GRPH_X_START__GRPH_X_START__SHIFT 0x0 |
4611 | #define GRPH_Y_START__GRPH_Y_START_MASK 0x3fff |
4612 | #define GRPH_Y_START__GRPH_Y_START__SHIFT 0x0 |
4613 | #define GRPH_X_END__GRPH_X_END_MASK 0x7fff |
4614 | #define GRPH_X_END__GRPH_X_END__SHIFT 0x0 |
4615 | #define GRPH_Y_END__GRPH_Y_END_MASK 0x7fff |
4616 | #define GRPH_Y_END__GRPH_Y_END__SHIFT 0x0 |
4617 | #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x3 |
4618 | #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x0 |
4619 | #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x30 |
4620 | #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x4 |
4621 | #define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x1 |
4622 | #define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x0 |
4623 | #define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x2 |
4624 | #define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x1 |
4625 | #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x4 |
4626 | #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x2 |
4627 | #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x8 |
4628 | #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x3 |
4629 | #define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x100 |
4630 | #define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x8 |
4631 | #define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x10000 |
4632 | #define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x10 |
4633 | #define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK 0x100000 |
4634 | #define GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT 0x14 |
4635 | #define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 |
4636 | #define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 |
4637 | #define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000 |
4638 | #define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x1c |
4639 | #define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x1 |
4640 | #define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x0 |
4641 | #define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00 |
4642 | #define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x8 |
4643 | #define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x1 |
4644 | #define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x0 |
4645 | #define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x70 |
4646 | #define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x4 |
4647 | #define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x700 |
4648 | #define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 |
4649 | #define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0xf |
4650 | #define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x0 |
4651 | #define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 |
4652 | #define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 |
4653 | #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x100 |
4654 | #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x8 |
4655 | #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x200 |
4656 | #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x9 |
4657 | #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x1 |
4658 | #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x0 |
4659 | #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x100 |
4660 | #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x8 |
4661 | #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x1 |
4662 | #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x0 |
4663 | #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x100 |
4664 | #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x8 |
4665 | #define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff |
4666 | #define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0 |
4667 | #define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00 |
4668 | #define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x8 |
4669 | #define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x1ffc0 |
4670 | #define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x6 |
4671 | #define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0xff |
4672 | #define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
4673 | #define OVL_ENABLE__OVL_ENABLE_MASK 0x1 |
4674 | #define OVL_ENABLE__OVL_ENABLE__SHIFT 0x0 |
4675 | #define OVL_ENABLE__OVLSCL_EN_MASK 0x100 |
4676 | #define OVL_ENABLE__OVLSCL_EN__SHIFT 0x8 |
4677 | #define OVL_CONTROL1__OVL_DEPTH_MASK 0x3 |
4678 | #define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x0 |
4679 | #define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0xc |
4680 | #define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x2 |
4681 | #define OVL_CONTROL1__OVL_Z_MASK 0x30 |
4682 | #define OVL_CONTROL1__OVL_Z__SHIFT 0x4 |
4683 | #define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0xc0 |
4684 | #define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x6 |
4685 | #define OVL_CONTROL1__OVL_FORMAT_MASK 0x700 |
4686 | #define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x8 |
4687 | #define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x1800 |
4688 | #define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0xb |
4689 | #define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0xe000 |
4690 | #define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0xd |
4691 | #define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x10000 |
4692 | #define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x10 |
4693 | #define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x20000 |
4694 | #define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x11 |
4695 | #define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0xc0000 |
4696 | #define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x12 |
4697 | #define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0xf00000 |
4698 | #define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x14 |
4699 | #define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x1000000 |
4700 | #define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x18 |
4701 | #define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000 |
4702 | #define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x19 |
4703 | #define OVL_CONTROL1__OVL_MICRO_TILE_MODE_MASK 0xc0000000 |
4704 | #define OVL_CONTROL1__OVL_MICRO_TILE_MODE__SHIFT 0x1e |
4705 | #define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x1 |
4706 | #define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x0 |
4707 | #define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x3 |
4708 | #define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x0 |
4709 | #define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x30 |
4710 | #define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x4 |
4711 | #define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0xc0 |
4712 | #define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x6 |
4713 | #define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x300 |
4714 | #define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x8 |
4715 | #define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0xc00 |
4716 | #define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0xa |
4717 | #define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x1 |
4718 | #define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x0 |
4719 | #define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00 |
4720 | #define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x8 |
4721 | #define OVL_PITCH__OVL_PITCH_MASK 0x7fff |
4722 | #define OVL_PITCH__OVL_PITCH__SHIFT 0x0 |
4723 | #define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0xff |
4724 | #define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
4725 | #define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x3fff |
4726 | #define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x0 |
4727 | #define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x3fff |
4728 | #define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x0 |
4729 | #define OVL_START__OVL_Y_START_MASK 0x3fff |
4730 | #define OVL_START__OVL_Y_START__SHIFT 0x0 |
4731 | #define OVL_START__OVL_X_START_MASK 0x3fff0000 |
4732 | #define OVL_START__OVL_X_START__SHIFT 0x10 |
4733 | #define OVL_END__OVL_Y_END_MASK 0x7fff |
4734 | #define OVL_END__OVL_Y_END__SHIFT 0x0 |
4735 | #define OVL_END__OVL_X_END_MASK 0x7fff0000 |
4736 | #define OVL_END__OVL_X_END__SHIFT 0x10 |
4737 | #define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x1 |
4738 | #define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x0 |
4739 | #define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x2 |
4740 | #define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x1 |
4741 | #define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x10000 |
4742 | #define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x10 |
4743 | #define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 |
4744 | #define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 |
4745 | #define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00 |
4746 | #define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x8 |
4747 | #define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x1 |
4748 | #define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x0 |
4749 | #define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x70 |
4750 | #define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x4 |
4751 | #define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x700 |
4752 | #define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x8 |
4753 | #define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0xf |
4754 | #define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x0 |
4755 | #define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0xf0 |
4756 | #define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x4 |
4757 | #define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x100 |
4758 | #define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x8 |
4759 | #define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x200 |
4760 | #define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x9 |
4761 | #define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0xff |
4762 | #define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x0 |
4763 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x3ff |
4764 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x0 |
4765 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0xffc00 |
4766 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0xa |
4767 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000 |
4768 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x14 |
4769 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000 |
4770 | #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x1f |
4771 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x1 |
4772 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x0 |
4773 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x2 |
4774 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x1 |
4775 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x4 |
4776 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x2 |
4777 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x8 |
4778 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x3 |
4779 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x10 |
4780 | #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x4 |
4781 | #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0xffff |
4782 | #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x0 |
4783 | #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000 |
4784 | #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x10 |
4785 | #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0xffff |
4786 | #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x0 |
4787 | #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000 |
4788 | #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x10 |
4789 | #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0xffff |
4790 | #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x0 |
4791 | #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000 |
4792 | #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x10 |
4793 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x1 |
4794 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x0 |
4795 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x2 |
4796 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x1 |
4797 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x4 |
4798 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x2 |
4799 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x8 |
4800 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x3 |
4801 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x10 |
4802 | #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x4 |
4803 | #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0xffff |
4804 | #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x0 |
4805 | #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000 |
4806 | #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x10 |
4807 | #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0xffff |
4808 | #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x0 |
4809 | #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000 |
4810 | #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x10 |
4811 | #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0xffff |
4812 | #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x0 |
4813 | #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000 |
4814 | #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x10 |
4815 | #define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x3 |
4816 | #define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x0 |
4817 | #define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x30 |
4818 | #define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x4 |
4819 | #define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0xffff |
4820 | #define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x0 |
4821 | #define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000 |
4822 | #define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x10 |
4823 | #define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0xffff |
4824 | #define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x0 |
4825 | #define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000 |
4826 | #define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x10 |
4827 | #define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0xffff |
4828 | #define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x0 |
4829 | #define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000 |
4830 | #define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x10 |
4831 | #define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0xffff |
4832 | #define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x0 |
4833 | #define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000 |
4834 | #define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x10 |
4835 | #define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0xffff |
4836 | #define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x0 |
4837 | #define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000 |
4838 | #define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x10 |
4839 | #define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0xffff |
4840 | #define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x0 |
4841 | #define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000 |
4842 | #define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x10 |
4843 | #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x7 |
4844 | #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x0 |
4845 | #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x70 |
4846 | #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x4 |
4847 | #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0xffff |
4848 | #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x0 |
4849 | #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000 |
4850 | #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x10 |
4851 | #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0xffff |
4852 | #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x0 |
4853 | #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000 |
4854 | #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x10 |
4855 | #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0xffff |
4856 | #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x0 |
4857 | #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000 |
4858 | #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x10 |
4859 | #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0xffff |
4860 | #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x0 |
4861 | #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000 |
4862 | #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x10 |
4863 | #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0xffff |
4864 | #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x0 |
4865 | #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000 |
4866 | #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x10 |
4867 | #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0xffff |
4868 | #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x0 |
4869 | #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000 |
4870 | #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x10 |
4871 | #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0xffff |
4872 | #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x0 |
4873 | #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000 |
4874 | #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x10 |
4875 | #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0xffff |
4876 | #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x0 |
4877 | #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000 |
4878 | #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x10 |
4879 | #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0xffff |
4880 | #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x0 |
4881 | #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000 |
4882 | #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x10 |
4883 | #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0xffff |
4884 | #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x0 |
4885 | #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000 |
4886 | #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x10 |
4887 | #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0xffff |
4888 | #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x0 |
4889 | #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000 |
4890 | #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x10 |
4891 | #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0xffff |
4892 | #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x0 |
4893 | #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000 |
4894 | #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x10 |
4895 | #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0xffff |
4896 | #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x0 |
4897 | #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000 |
4898 | #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x10 |
4899 | #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0xffff |
4900 | #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x0 |
4901 | #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000 |
4902 | #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x10 |
4903 | #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0xffff |
4904 | #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x0 |
4905 | #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000 |
4906 | #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x10 |
4907 | #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0xffff |
4908 | #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x0 |
4909 | #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000 |
4910 | #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x10 |
4911 | #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0xffff |
4912 | #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x0 |
4913 | #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000 |
4914 | #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x10 |
4915 | #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0xffff |
4916 | #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x0 |
4917 | #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000 |
4918 | #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x10 |
4919 | #define DENORM_CONTROL__DENORM_MODE_MASK 0x7 |
4920 | #define DENORM_CONTROL__DENORM_MODE__SHIFT 0x0 |
4921 | #define DENORM_CONTROL__DENORM_14BIT_OUT_MASK 0x10 |
4922 | #define DENORM_CONTROL__DENORM_14BIT_OUT__SHIFT 0x4 |
4923 | #define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0xf |
4924 | #define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x0 |
4925 | #define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR_MASK 0x3fff |
4926 | #define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MAX_R_CR__SHIFT 0x0 |
4927 | #define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR_MASK 0x3fff0000 |
4928 | #define OUT_CLAMP_CONTROL_R_CR__OUT_CLAMP_MIN_R_CR__SHIFT 0x10 |
4929 | #define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y_MASK 0x3fff |
4930 | #define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MAX_G_Y__SHIFT 0x0 |
4931 | #define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y_MASK 0x3fff0000 |
4932 | #define OUT_CLAMP_CONTROL_G_Y__OUT_CLAMP_MIN_G_Y__SHIFT 0x10 |
4933 | #define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB_MASK 0x3fff |
4934 | #define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MAX_B_CB__SHIFT 0x0 |
4935 | #define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB_MASK 0x3fff0000 |
4936 | #define OUT_CLAMP_CONTROL_B_CB__OUT_CLAMP_MIN_B_CB__SHIFT 0x10 |
4937 | #define KEY_CONTROL__KEY_SELECT_MASK 0x1 |
4938 | #define KEY_CONTROL__KEY_SELECT__SHIFT 0x0 |
4939 | #define KEY_CONTROL__KEY_MODE_MASK 0x6 |
4940 | #define KEY_CONTROL__KEY_MODE__SHIFT 0x1 |
4941 | #define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000 |
4942 | #define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x1c |
4943 | #define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0xffff |
4944 | #define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x0 |
4945 | #define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000 |
4946 | #define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x10 |
4947 | #define KEY_RANGE_RED__KEY_RED_LOW_MASK 0xffff |
4948 | #define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x0 |
4949 | #define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000 |
4950 | #define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x10 |
4951 | #define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0xffff |
4952 | #define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x0 |
4953 | #define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000 |
4954 | #define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x10 |
4955 | #define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0xffff |
4956 | #define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x0 |
4957 | #define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000 |
4958 | #define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x10 |
4959 | #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x3 |
4960 | #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x0 |
4961 | #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x30 |
4962 | #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x4 |
4963 | #define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE_MASK 0x300 |
4964 | #define DEGAMMA_CONTROL__CURSOR2_DEGAMMA_MODE__SHIFT 0x8 |
4965 | #define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x3000 |
4966 | #define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0xc |
4967 | #define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x3 |
4968 | #define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x0 |
4969 | #define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x30 |
4970 | #define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x4 |
4971 | #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0xffff |
4972 | #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x0 |
4973 | #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000 |
4974 | #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x10 |
4975 | #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0xffff |
4976 | #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x0 |
4977 | #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000 |
4978 | #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x10 |
4979 | #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0xffff |
4980 | #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x0 |
4981 | #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000 |
4982 | #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x10 |
4983 | #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0xffff |
4984 | #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x0 |
4985 | #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000 |
4986 | #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x10 |
4987 | #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0xffff |
4988 | #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x0 |
4989 | #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000 |
4990 | #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x10 |
4991 | #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0xffff |
4992 | #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x0 |
4993 | #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000 |
4994 | #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x10 |
4995 | #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x1 |
4996 | #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x0 |
4997 | #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x30 |
4998 | #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x4 |
4999 | #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0xc0 |
5000 | #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x6 |
5001 | #define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x100 |
5002 | #define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x8 |
5003 | #define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x200 |
5004 | #define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x9 |
5005 | #define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x400 |
5006 | #define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0xa |
5007 | #define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0xff |
5008 | #define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x0 |
5009 | #define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0xff00 |
5010 | #define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x8 |
5011 | #define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0xff0000 |
5012 | #define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x10 |
5013 | #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x3ffff |
5014 | #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x0 |
5015 | #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x7f00000 |
5016 | #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x14 |
5017 | #define CUR_CONTROL__CURSOR_EN_MASK 0x1 |
5018 | #define CUR_CONTROL__CURSOR_EN__SHIFT 0x0 |
5019 | #define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x10 |
5020 | #define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x4 |
5021 | #define CUR_CONTROL__CURSOR_MODE_MASK 0x300 |
5022 | #define CUR_CONTROL__CURSOR_MODE__SHIFT 0x8 |
5023 | #define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x10000 |
5024 | #define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x10 |
5025 | #define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x100000 |
5026 | #define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x14 |
5027 | #define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x7000000 |
5028 | #define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x18 |
5029 | #define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffff |
5030 | #define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 |
5031 | #define CUR_SIZE__CURSOR_HEIGHT_MASK 0x7f |
5032 | #define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 |
5033 | #define CUR_SIZE__CURSOR_WIDTH_MASK 0x7f0000 |
5034 | #define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x10 |
5035 | #define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0xff |
5036 | #define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
5037 | #define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x3fff |
5038 | #define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 |
5039 | #define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000 |
5040 | #define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 |
5041 | #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x7f |
5042 | #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 |
5043 | #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x7f0000 |
5044 | #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 |
5045 | #define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0xff |
5046 | #define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x0 |
5047 | #define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0xff00 |
5048 | #define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x8 |
5049 | #define CUR_COLOR1__CUR_COLOR1_RED_MASK 0xff0000 |
5050 | #define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x10 |
5051 | #define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0xff |
5052 | #define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x0 |
5053 | #define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0xff00 |
5054 | #define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x8 |
5055 | #define CUR_COLOR2__CUR_COLOR2_RED_MASK 0xff0000 |
5056 | #define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x10 |
5057 | #define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x1 |
5058 | #define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x0 |
5059 | #define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x2 |
5060 | #define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x1 |
5061 | #define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x10000 |
5062 | #define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x10 |
5063 | #define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 |
5064 | #define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 |
5065 | #define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE_MASK 0x6000000 |
5066 | #define CUR_UPDATE__CURSOR_UPDATE_STEREO_MODE__SHIFT 0x19 |
5067 | #define CUR2_CONTROL__CURSOR2_EN_MASK 0x1 |
5068 | #define CUR2_CONTROL__CURSOR2_EN__SHIFT 0x0 |
5069 | #define CUR2_CONTROL__CUR2_INV_TRANS_CLAMP_MASK 0x10 |
5070 | #define CUR2_CONTROL__CUR2_INV_TRANS_CLAMP__SHIFT 0x4 |
5071 | #define CUR2_CONTROL__CURSOR2_MODE_MASK 0x300 |
5072 | #define CUR2_CONTROL__CURSOR2_MODE__SHIFT 0x8 |
5073 | #define CUR2_CONTROL__CURSOR2_2X_MAGNIFY_MASK 0x10000 |
5074 | #define CUR2_CONTROL__CURSOR2_2X_MAGNIFY__SHIFT 0x10 |
5075 | #define CUR2_CONTROL__CURSOR2_FORCE_MC_ON_MASK 0x100000 |
5076 | #define CUR2_CONTROL__CURSOR2_FORCE_MC_ON__SHIFT 0x14 |
5077 | #define CUR2_CONTROL__CURSOR2_URGENT_CONTROL_MASK 0x7000000 |
5078 | #define CUR2_CONTROL__CURSOR2_URGENT_CONTROL__SHIFT 0x18 |
5079 | #define CUR2_SURFACE_ADDRESS__CURSOR2_SURFACE_ADDRESS_MASK 0xffffffff |
5080 | #define CUR2_SURFACE_ADDRESS__CURSOR2_SURFACE_ADDRESS__SHIFT 0x0 |
5081 | #define CUR2_SIZE__CURSOR2_HEIGHT_MASK 0x7f |
5082 | #define CUR2_SIZE__CURSOR2_HEIGHT__SHIFT 0x0 |
5083 | #define CUR2_SIZE__CURSOR2_WIDTH_MASK 0x7f0000 |
5084 | #define CUR2_SIZE__CURSOR2_WIDTH__SHIFT 0x10 |
5085 | #define CUR2_SURFACE_ADDRESS_HIGH__CURSOR2_SURFACE_ADDRESS_HIGH_MASK 0xff |
5086 | #define CUR2_SURFACE_ADDRESS_HIGH__CURSOR2_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
5087 | #define CUR2_POSITION__CURSOR2_Y_POSITION_MASK 0x3fff |
5088 | #define CUR2_POSITION__CURSOR2_Y_POSITION__SHIFT 0x0 |
5089 | #define CUR2_POSITION__CURSOR2_X_POSITION_MASK 0x3fff0000 |
5090 | #define CUR2_POSITION__CURSOR2_X_POSITION__SHIFT 0x10 |
5091 | #define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_Y_MASK 0x7f |
5092 | #define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_Y__SHIFT 0x0 |
5093 | #define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_X_MASK 0x7f0000 |
5094 | #define CUR2_HOT_SPOT__CURSOR2_HOT_SPOT_X__SHIFT 0x10 |
5095 | #define CUR2_COLOR1__CUR2_COLOR1_BLUE_MASK 0xff |
5096 | #define CUR2_COLOR1__CUR2_COLOR1_BLUE__SHIFT 0x0 |
5097 | #define CUR2_COLOR1__CUR2_COLOR1_GREEN_MASK 0xff00 |
5098 | #define CUR2_COLOR1__CUR2_COLOR1_GREEN__SHIFT 0x8 |
5099 | #define CUR2_COLOR1__CUR2_COLOR1_RED_MASK 0xff0000 |
5100 | #define CUR2_COLOR1__CUR2_COLOR1_RED__SHIFT 0x10 |
5101 | #define CUR2_COLOR2__CUR2_COLOR2_BLUE_MASK 0xff |
5102 | #define CUR2_COLOR2__CUR2_COLOR2_BLUE__SHIFT 0x0 |
5103 | #define CUR2_COLOR2__CUR2_COLOR2_GREEN_MASK 0xff00 |
5104 | #define CUR2_COLOR2__CUR2_COLOR2_GREEN__SHIFT 0x8 |
5105 | #define CUR2_COLOR2__CUR2_COLOR2_RED_MASK 0xff0000 |
5106 | #define CUR2_COLOR2__CUR2_COLOR2_RED__SHIFT 0x10 |
5107 | #define CUR2_UPDATE__CURSOR2_UPDATE_PENDING_MASK 0x1 |
5108 | #define CUR2_UPDATE__CURSOR2_UPDATE_PENDING__SHIFT 0x0 |
5109 | #define CUR2_UPDATE__CURSOR2_UPDATE_TAKEN_MASK 0x2 |
5110 | #define CUR2_UPDATE__CURSOR2_UPDATE_TAKEN__SHIFT 0x1 |
5111 | #define CUR2_UPDATE__CURSOR2_UPDATE_LOCK_MASK 0x10000 |
5112 | #define CUR2_UPDATE__CURSOR2_UPDATE_LOCK__SHIFT 0x10 |
5113 | #define CUR2_UPDATE__CURSOR2_DISABLE_MULTIPLE_UPDATE_MASK 0x1000000 |
5114 | #define CUR2_UPDATE__CURSOR2_DISABLE_MULTIPLE_UPDATE__SHIFT 0x18 |
5115 | #define CUR2_UPDATE__CURSOR2_UPDATE_STEREO_MODE_MASK 0x6000000 |
5116 | #define CUR2_UPDATE__CURSOR2_UPDATE_STEREO_MODE__SHIFT 0x19 |
5117 | #define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x1 |
5118 | #define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x0 |
5119 | #define CUR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x1 |
5120 | #define CUR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 |
5121 | #define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX_MASK 0x2 |
5122 | #define CUR_STEREO_CONTROL__CURSOR_STEREO_OFFSET_YNX__SHIFT 0x1 |
5123 | #define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x3ff0 |
5124 | #define CUR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 |
5125 | #define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0x3ff0000 |
5126 | #define CUR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x10 |
5127 | #define CUR2_STEREO_CONTROL__CURSOR2_STEREO_EN_MASK 0x1 |
5128 | #define CUR2_STEREO_CONTROL__CURSOR2_STEREO_EN__SHIFT 0x0 |
5129 | #define CUR2_STEREO_CONTROL__CURSOR2_STEREO_OFFSET_YNX_MASK 0x2 |
5130 | #define CUR2_STEREO_CONTROL__CURSOR2_STEREO_OFFSET_YNX__SHIFT 0x1 |
5131 | #define CUR2_STEREO_CONTROL__CURSOR2_PRIMARY_OFFSET_MASK 0x3ff0 |
5132 | #define CUR2_STEREO_CONTROL__CURSOR2_PRIMARY_OFFSET__SHIFT 0x4 |
5133 | #define CUR2_STEREO_CONTROL__CURSOR2_SECONDARY_OFFSET_MASK 0x3ff0000 |
5134 | #define CUR2_STEREO_CONTROL__CURSOR2_SECONDARY_OFFSET__SHIFT 0x10 |
5135 | #define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x1 |
5136 | #define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x0 |
5137 | #define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0xff |
5138 | #define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x0 |
5139 | #define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0xffff |
5140 | #define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x0 |
5141 | #define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0xffff |
5142 | #define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x0 |
5143 | #define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000 |
5144 | #define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x10 |
5145 | #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x3ff |
5146 | #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x0 |
5147 | #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0xffc00 |
5148 | #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0xa |
5149 | #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000 |
5150 | #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x14 |
5151 | #define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x1 |
5152 | #define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x0 |
5153 | #define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x7 |
5154 | #define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x0 |
5155 | #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x1 |
5156 | #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x0 |
5157 | #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x2 |
5158 | #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x1 |
5159 | #define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0xf |
5160 | #define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x0 |
5161 | #define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x10 |
5162 | #define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x4 |
5163 | #define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x20 |
5164 | #define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x5 |
5165 | #define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0xc0 |
5166 | #define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x6 |
5167 | #define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0xf00 |
5168 | #define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x8 |
5169 | #define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x1000 |
5170 | #define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0xc |
5171 | #define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x2000 |
5172 | #define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0xd |
5173 | #define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0xc000 |
5174 | #define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0xe |
5175 | #define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0xf0000 |
5176 | #define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x10 |
5177 | #define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x100000 |
5178 | #define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x14 |
5179 | #define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x200000 |
5180 | #define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x15 |
5181 | #define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0xc00000 |
5182 | #define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x16 |
5183 | #define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0xffff |
5184 | #define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x0 |
5185 | #define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0xffff |
5186 | #define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x0 |
5187 | #define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0xffff |
5188 | #define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x0 |
5189 | #define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0xffff |
5190 | #define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x0 |
5191 | #define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0xffff |
5192 | #define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x0 |
5193 | #define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0xffff |
5194 | #define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x0 |
5195 | #define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x1 |
5196 | #define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x0 |
5197 | #define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x1c |
5198 | #define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x2 |
5199 | #define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x300 |
5200 | #define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x8 |
5201 | #define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffff |
5202 | #define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x0 |
5203 | #define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffff |
5204 | #define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x0 |
5205 | #define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffff |
5206 | #define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x0 |
5207 | #define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffff |
5208 | #define DCP_DEBUG__DCP_DEBUG__SHIFT 0x0 |
5209 | #define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK 0x7 |
5210 | #define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT 0x0 |
5211 | #define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK 0x8 |
5212 | #define GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT 0x3 |
5213 | #define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x1 |
5214 | #define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x0 |
5215 | #define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x2 |
5216 | #define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x1 |
5217 | #define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x4 |
5218 | #define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x2 |
5219 | #define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x300 |
5220 | #define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x8 |
5221 | #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0xf000 |
5222 | #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0xc |
5223 | #define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x10000 |
5224 | #define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x10 |
5225 | #define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x3000000 |
5226 | #define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x18 |
5227 | #define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x8000000 |
5228 | #define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x1b |
5229 | #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000 |
5230 | #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x1c |
5231 | #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0xf |
5232 | #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x0 |
5233 | #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0xf0 |
5234 | #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x4 |
5235 | #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x1 |
5236 | #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x0 |
5237 | #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00 |
5238 | #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x8 |
5239 | #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x1 |
5240 | #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x0 |
5241 | #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x300 |
5242 | #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x8 |
5243 | #define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x10000 |
5244 | #define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x10 |
5245 | #define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x20000 |
5246 | #define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x11 |
5247 | #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 |
5248 | #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c |
5249 | #define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0xff |
5250 | #define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
5251 | #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0xff |
5252 | #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x0 |
5253 | #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x100 |
5254 | #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
5255 | #define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffff |
5256 | #define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x0 |
5257 | #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x1 |
5258 | #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x0 |
5259 | #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x300 |
5260 | #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x8 |
5261 | #define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x10000 |
5262 | #define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x10 |
5263 | #define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x20000 |
5264 | #define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x11 |
5265 | #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000 |
5266 | #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x1c |
5267 | #define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffff |
5268 | #define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x0 |
5269 | #define HW_ROTATION__GRPH_ROTATION_ANGLE_MASK 0x7 |
5270 | #define HW_ROTATION__GRPH_ROTATION_ANGLE__SHIFT 0x0 |
5271 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_MASK 0x1 |
5272 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN__SHIFT 0x0 |
5273 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_MASK 0x2 |
5274 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE__SHIFT 0x1 |
5275 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT_MASK 0x1fff0 |
5276 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT__SHIFT 0x4 |
5277 | #define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x7 |
5278 | #define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x0 |
5279 | #define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x70 |
5280 | #define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x4 |
5281 | #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x1ff |
5282 | #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x0 |
5283 | #define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x7ffff |
5284 | #define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x0 |
5285 | #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x7 |
5286 | #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x0 |
5287 | #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x3ffff |
5288 | #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x0 |
5289 | #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x7f00000 |
5290 | #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x14 |
5291 | #define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff |
5292 | #define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 |
5293 | #define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0xffff |
5294 | #define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x0 |
5295 | #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0xffff |
5296 | #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x0 |
5297 | #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000 |
5298 | #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x10 |
5299 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x1ff |
5300 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
5301 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 |
5302 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
5303 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 |
5304 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
5305 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 |
5306 | #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
5307 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x1ff |
5308 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
5309 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 |
5310 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
5311 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 |
5312 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
5313 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 |
5314 | #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
5315 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x1ff |
5316 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
5317 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 |
5318 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
5319 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 |
5320 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
5321 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 |
5322 | #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
5323 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x1ff |
5324 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
5325 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 |
5326 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
5327 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 |
5328 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
5329 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 |
5330 | #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
5331 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x1ff |
5332 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
5333 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 |
5334 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
5335 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 |
5336 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
5337 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 |
5338 | #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
5339 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x1ff |
5340 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
5341 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 |
5342 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
5343 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 |
5344 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
5345 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 |
5346 | #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
5347 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x1ff |
5348 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
5349 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 |
5350 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
5351 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 |
5352 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
5353 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 |
5354 | #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
5355 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x1ff |
5356 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
5357 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 |
5358 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
5359 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 |
5360 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
5361 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 |
5362 | #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
5363 | #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x3ffff |
5364 | #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x0 |
5365 | #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x7f00000 |
5366 | #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x14 |
5367 | #define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x3ffff |
5368 | #define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x0 |
5369 | #define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0xffff |
5370 | #define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x0 |
5371 | #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0xffff |
5372 | #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x0 |
5373 | #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000 |
5374 | #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x10 |
5375 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x1ff |
5376 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 |
5377 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x7000 |
5378 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc |
5379 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x1ff0000 |
5380 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 |
5381 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000 |
5382 | #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c |
5383 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x1ff |
5384 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 |
5385 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x7000 |
5386 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc |
5387 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x1ff0000 |
5388 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 |
5389 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000 |
5390 | #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c |
5391 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x1ff |
5392 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 |
5393 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x7000 |
5394 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc |
5395 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x1ff0000 |
5396 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 |
5397 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000 |
5398 | #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c |
5399 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x1ff |
5400 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 |
5401 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x7000 |
5402 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc |
5403 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x1ff0000 |
5404 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 |
5405 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000 |
5406 | #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c |
5407 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x1ff |
5408 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 |
5409 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x7000 |
5410 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc |
5411 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x1ff0000 |
5412 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 |
5413 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000 |
5414 | #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c |
5415 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x1ff |
5416 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 |
5417 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x7000 |
5418 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc |
5419 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x1ff0000 |
5420 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 |
5421 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000 |
5422 | #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c |
5423 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x1ff |
5424 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 |
5425 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x7000 |
5426 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc |
5427 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x1ff0000 |
5428 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 |
5429 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000 |
5430 | #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c |
5431 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x1ff |
5432 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 |
5433 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x7000 |
5434 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc |
5435 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x1ff0000 |
5436 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 |
5437 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000 |
5438 | #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c |
5439 | #define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE_MASK 0x1 |
5440 | #define ALPHA_CONTROL__ALPHA_ROUND_TRUNC_MODE__SHIFT 0x0 |
5441 | #define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK 0x2 |
5442 | #define ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA__SHIFT 0x1 |
5443 | #define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_MASK 0xffffff00 |
5444 | #define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS__SHIFT 0x8 |
5445 | #define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH_MASK 0xff |
5446 | #define GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 |
5447 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_MASK 0xfffff |
5448 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT__SHIFT 0x0 |
5449 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS_MASK 0x1000000 |
5450 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS__SHIFT 0x18 |
5451 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_MASK 0x2000000 |
5452 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK__SHIFT 0x19 |
5453 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_MASK 0x4000000 |
5454 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK__SHIFT 0x1a |
5455 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK 0x10000000 |
5456 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT__SHIFT 0x1c |
5457 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_MASK 0x20000000 |
5458 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK__SHIFT 0x1d |
5459 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_MASK 0x40000000 |
5460 | #define GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS__GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK__SHIFT 0x1e |
5461 | #define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x7 |
5462 | #define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 |
5463 | #define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x70 |
5464 | #define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 |
5465 | #define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x100 |
5466 | #define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 |
5467 | #define DIG_FE_CNTL__DIG_START_MASK 0x400 |
5468 | #define DIG_FE_CNTL__DIG_START__SHIFT 0xa |
5469 | #define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x10000 |
5470 | #define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x10 |
5471 | #define DIG_FE_CNTL__DIG_SWAP_MASK 0x40000 |
5472 | #define DIG_FE_CNTL__DIG_SWAP__SHIFT 0x12 |
5473 | #define DIG_FE_CNTL__DIG_RB_SWITCH_EN_MASK 0x100000 |
5474 | #define DIG_FE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x14 |
5475 | #define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x1000000 |
5476 | #define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x18 |
5477 | #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x1 |
5478 | #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 |
5479 | #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x10 |
5480 | #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 |
5481 | #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x300 |
5482 | #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 |
5483 | #define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffff |
5484 | #define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 |
5485 | #define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x3ff |
5486 | #define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 |
5487 | #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x1 |
5488 | #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 |
5489 | #define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x2 |
5490 | #define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 |
5491 | #define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x4 |
5492 | #define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x2 |
5493 | #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x10 |
5494 | #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 |
5495 | #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x20 |
5496 | #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 |
5497 | #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x40 |
5498 | #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 |
5499 | #define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x100 |
5500 | #define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x8 |
5501 | #define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x3ff0000 |
5502 | #define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 |
5503 | #define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0xffffff |
5504 | #define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 |
5505 | #define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x1000000 |
5506 | #define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 |
5507 | #define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x1 |
5508 | #define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x0 |
5509 | #define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 |
5510 | #define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
5511 | #define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0xfc |
5512 | #define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
5513 | #define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x100 |
5514 | #define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x8 |
5515 | #define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 |
5516 | #define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
5517 | #define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x1f0000 |
5518 | #define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
5519 | #define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 |
5520 | #define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
5521 | #define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000 |
5522 | #define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x1d |
5523 | #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 |
5524 | #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
5525 | #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 |
5526 | #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
5527 | #define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x1 |
5528 | #define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x0 |
5529 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x1 |
5530 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x0 |
5531 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x10 |
5532 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x4 |
5533 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x100 |
5534 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x8 |
5535 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x1000 |
5536 | #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0xc |
5537 | #define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x1 |
5538 | #define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x0 |
5539 | #define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x10 |
5540 | #define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x4 |
5541 | #define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x100 |
5542 | #define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 |
5543 | #define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x200 |
5544 | #define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 |
5545 | #define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x1000000 |
5546 | #define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 |
5547 | #define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000 |
5548 | #define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c |
5549 | #define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x1 |
5550 | #define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 |
5551 | #define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x10000 |
5552 | #define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 |
5553 | #define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x100000 |
5554 | #define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x14 |
5555 | #define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x8000000 |
5556 | #define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b |
5557 | #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x30 |
5558 | #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 |
5559 | #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x100 |
5560 | #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x8 |
5561 | #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x1f0000 |
5562 | #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x10 |
5563 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x1 |
5564 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 |
5565 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x2 |
5566 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 |
5567 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x30 |
5568 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 |
5569 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x100 |
5570 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 |
5571 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x1000 |
5572 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc |
5573 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x70000 |
5574 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 |
5575 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000 |
5576 | #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f |
5577 | #define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x1 |
5578 | #define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 |
5579 | #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x10 |
5580 | #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 |
5581 | #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x20 |
5582 | #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 |
5583 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x100 |
5584 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 |
5585 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x200 |
5586 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 |
5587 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x1000 |
5588 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc |
5589 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x3f0000 |
5590 | #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 |
5591 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x1 |
5592 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x0 |
5593 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x2 |
5594 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x1 |
5595 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x10 |
5596 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 |
5597 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x20 |
5598 | #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x5 |
5599 | #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x100 |
5600 | #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x8 |
5601 | #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x200 |
5602 | #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x9 |
5603 | #define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x3f |
5604 | #define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x0 |
5605 | #define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x3f00 |
5606 | #define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 |
5607 | #define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x3f0000 |
5608 | #define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x10 |
5609 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x1 |
5610 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 |
5611 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x2 |
5612 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 |
5613 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x10 |
5614 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 |
5615 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x20 |
5616 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 |
5617 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x3f0000 |
5618 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x10 |
5619 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000 |
5620 | #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x18 |
5621 | #define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x1 |
5622 | #define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 |
5623 | #define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x4 |
5624 | #define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 |
5625 | #define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x10 |
5626 | #define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 |
5627 | #define HDMI_GC__HDMI_PACKING_PHASE_MASK 0xf00 |
5628 | #define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 |
5629 | #define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x1000 |
5630 | #define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc |
5631 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x1 |
5632 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x0 |
5633 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x2 |
5634 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x1 |
5635 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0xff00 |
5636 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 |
5637 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0xff0000 |
5638 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x10 |
5639 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x1000000 |
5640 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x18 |
5641 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000 |
5642 | #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x1c |
5643 | #define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x7 |
5644 | #define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x0 |
5645 | #define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x40 |
5646 | #define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x6 |
5647 | #define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x80 |
5648 | #define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x7 |
5649 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0xff |
5650 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x0 |
5651 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0xff00 |
5652 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x8 |
5653 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0xff0000 |
5654 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x10 |
5655 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000 |
5656 | #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x18 |
5657 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0xff |
5658 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x0 |
5659 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0xff00 |
5660 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x8 |
5661 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0xff0000 |
5662 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x10 |
5663 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000 |
5664 | #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x18 |
5665 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0xff |
5666 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x0 |
5667 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0xff00 |
5668 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x8 |
5669 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0xff0000 |
5670 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x10 |
5671 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000 |
5672 | #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x18 |
5673 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0xff |
5674 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x0 |
5675 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0xff00 |
5676 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x8 |
5677 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0xff0000 |
5678 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x10 |
5679 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000 |
5680 | #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x18 |
5681 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0xff |
5682 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x0 |
5683 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0xff00 |
5684 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x8 |
5685 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0xff0000 |
5686 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x10 |
5687 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000 |
5688 | #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x18 |
5689 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0xff |
5690 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x0 |
5691 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0xff00 |
5692 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x8 |
5693 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0xff0000 |
5694 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x10 |
5695 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000 |
5696 | #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x18 |
5697 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0xff |
5698 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x0 |
5699 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0xff00 |
5700 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x8 |
5701 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0xff0000 |
5702 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x10 |
5703 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000 |
5704 | #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x18 |
5705 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0xff |
5706 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x0 |
5707 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0xff00 |
5708 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x8 |
5709 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0xff0000 |
5710 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x10 |
5711 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000 |
5712 | #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x18 |
5713 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0xff |
5714 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x0 |
5715 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x300 |
5716 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x8 |
5717 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0xc00 |
5718 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0xa |
5719 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x1000 |
5720 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0xc |
5721 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x6000 |
5722 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0xd |
5723 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x8000 |
5724 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0xf |
5725 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0xf0000 |
5726 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x10 |
5727 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x300000 |
5728 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x14 |
5729 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0xc00000 |
5730 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x16 |
5731 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x3000000 |
5732 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x18 |
5733 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0xc000000 |
5734 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x1a |
5735 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000 |
5736 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x1c |
5737 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000 |
5738 | #define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x1f |
5739 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x7f |
5740 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x0 |
5741 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x80 |
5742 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x7 |
5743 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0xf00 |
5744 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x8 |
5745 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x3000 |
5746 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0xc |
5747 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0xc000 |
5748 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0xe |
5749 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000 |
5750 | #define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x10 |
5751 | #define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0xffff |
5752 | #define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x0 |
5753 | #define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000 |
5754 | #define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x10 |
5755 | #define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0xffff |
5756 | #define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x0 |
5757 | #define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000 |
5758 | #define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x18 |
5759 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0xff |
5760 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x0 |
5761 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0xff00 |
5762 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x8 |
5763 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0xff0000 |
5764 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x10 |
5765 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000 |
5766 | #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x18 |
5767 | #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0xff |
5768 | #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x0 |
5769 | #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x300 |
5770 | #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x8 |
5771 | #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x1000 |
5772 | #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0xc |
5773 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0xff |
5774 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x0 |
5775 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0xff00 |
5776 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x8 |
5777 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0xff0000 |
5778 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x10 |
5779 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000 |
5780 | #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x18 |
5781 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0xff |
5782 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x0 |
5783 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0xff00 |
5784 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x8 |
5785 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0xff0000 |
5786 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x10 |
5787 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000 |
5788 | #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x18 |
5789 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0xff |
5790 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x0 |
5791 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0xff00 |
5792 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x8 |
5793 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0xff0000 |
5794 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x10 |
5795 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000 |
5796 | #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x18 |
5797 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0xff |
5798 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x0 |
5799 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0xff00 |
5800 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x8 |
5801 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0xff0000 |
5802 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x10 |
5803 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000 |
5804 | #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x18 |
5805 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0xff |
5806 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x0 |
5807 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0xff00 |
5808 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x8 |
5809 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0xff0000 |
5810 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x10 |
5811 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000 |
5812 | #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x18 |
5813 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0xff |
5814 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x0 |
5815 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0xff00 |
5816 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x8 |
5817 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0xff0000 |
5818 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x10 |
5819 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000 |
5820 | #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x18 |
5821 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0xff |
5822 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x0 |
5823 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0xff00 |
5824 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x8 |
5825 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0xff0000 |
5826 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x10 |
5827 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000 |
5828 | #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x18 |
5829 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0xff |
5830 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x0 |
5831 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0xff00 |
5832 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x8 |
5833 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0xff0000 |
5834 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x10 |
5835 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000 |
5836 | #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x18 |
5837 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0xff |
5838 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x0 |
5839 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0xff00 |
5840 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x8 |
5841 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0xff0000 |
5842 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x10 |
5843 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000 |
5844 | #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x18 |
5845 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x1 |
5846 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x0 |
5847 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x2 |
5848 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x1 |
5849 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x10 |
5850 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x4 |
5851 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x20 |
5852 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x5 |
5853 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x3f0000 |
5854 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x10 |
5855 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000 |
5856 | #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x18 |
5857 | #define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000 |
5858 | #define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc |
5859 | #define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0xfffff |
5860 | #define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 |
5861 | #define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000 |
5862 | #define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc |
5863 | #define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0xfffff |
5864 | #define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 |
5865 | #define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000 |
5866 | #define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc |
5867 | #define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0xfffff |
5868 | #define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 |
5869 | #define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000 |
5870 | #define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc |
5871 | #define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0xfffff |
5872 | #define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 |
5873 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0xff |
5874 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x0 |
5875 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x700 |
5876 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x8 |
5877 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x7800 |
5878 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0xb |
5879 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0xff0000 |
5880 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x10 |
5881 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000 |
5882 | #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x18 |
5883 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0xff |
5884 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x0 |
5885 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x7800 |
5886 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0xb |
5887 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x8000 |
5888 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0xf |
5889 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x30000 |
5890 | #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x10 |
5891 | #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x1 |
5892 | #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x0 |
5893 | #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x2 |
5894 | #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x1 |
5895 | #define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x4 |
5896 | #define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x2 |
5897 | #define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x38 |
5898 | #define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x3 |
5899 | #define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0xc0 |
5900 | #define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x6 |
5901 | #define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0xff00 |
5902 | #define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x8 |
5903 | #define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0xf0000 |
5904 | #define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x10 |
5905 | #define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0xf00000 |
5906 | #define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 |
5907 | #define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0xf000000 |
5908 | #define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 |
5909 | #define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000 |
5910 | #define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c |
5911 | #define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0xf |
5912 | #define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x0 |
5913 | #define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf0 |
5914 | #define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 |
5915 | #define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x10000 |
5916 | #define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x10 |
5917 | #define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x40000 |
5918 | #define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x12 |
5919 | #define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0xf00000 |
5920 | #define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 |
5921 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x1 |
5922 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x0 |
5923 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x10 |
5924 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x4 |
5925 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x100 |
5926 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x8 |
5927 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0xf000 |
5928 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0xc |
5929 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000 |
5930 | #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x10 |
5931 | #define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0xffffff |
5932 | #define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x0 |
5933 | #define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000 |
5934 | #define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x1f |
5935 | #define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0xffffff |
5936 | #define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x0 |
5937 | #define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000 |
5938 | #define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 |
5939 | #define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0xffffff |
5940 | #define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x0 |
5941 | #define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0xffffff |
5942 | #define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x0 |
5943 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0xf |
5944 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
5945 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 |
5946 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
5947 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0xf00 |
5948 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 |
5949 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0xf000 |
5950 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc |
5951 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0xf0000 |
5952 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 |
5953 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0xf00000 |
5954 | #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 |
5955 | #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x1 |
5956 | #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x0 |
5957 | #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00 |
5958 | #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x8 |
5959 | #define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x10 |
5960 | #define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x4 |
5961 | #define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x100 |
5962 | #define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x8 |
5963 | #define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x1000000 |
5964 | #define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x18 |
5965 | #define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000 |
5966 | #define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x1e |
5967 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x1 |
5968 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x0 |
5969 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x800 |
5970 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0xb |
5971 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x1000 |
5972 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0xc |
5973 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x4000 |
5974 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0xe |
5975 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x800000 |
5976 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x17 |
5977 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x1000000 |
5978 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x18 |
5979 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x4000000 |
5980 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x1a |
5981 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000 |
5982 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x1e |
5983 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000 |
5984 | #define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x1f |
5985 | #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x4 |
5986 | #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x2 |
5987 | #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x8 |
5988 | #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x3 |
5989 | #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000 |
5990 | #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x1e |
5991 | #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x40 |
5992 | #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x6 |
5993 | #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x80 |
5994 | #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x7 |
5995 | #define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x400 |
5996 | #define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0xa |
5997 | #define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x7 |
5998 | #define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x0 |
5999 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x7 |
6000 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x0 |
6001 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x100 |
6002 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x8 |
6003 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x7000 |
6004 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0xc |
6005 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x70000 |
6006 | #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x10 |
6007 | #define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x7f00 |
6008 | #define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 |
6009 | #define DIG_BE_CNTL__DIG_MODE_MASK 0x70000 |
6010 | #define DIG_BE_CNTL__DIG_MODE__SHIFT 0x10 |
6011 | #define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000 |
6012 | #define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c |
6013 | #define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x1 |
6014 | #define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x0 |
6015 | #define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x100 |
6016 | #define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x8 |
6017 | #define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x1 |
6018 | #define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 |
6019 | #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x10 |
6020 | #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x4 |
6021 | #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x300 |
6022 | #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x8 |
6023 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x1 |
6024 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 |
6025 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x2 |
6026 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 |
6027 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x4 |
6028 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 |
6029 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x8 |
6030 | #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 |
6031 | #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x3 |
6032 | #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 |
6033 | #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x300 |
6034 | #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 |
6035 | #define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x3 |
6036 | #define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 |
6037 | #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x3ff |
6038 | #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 |
6039 | #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x3ff0000 |
6040 | #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 |
6041 | #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x3ff |
6042 | #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 |
6043 | #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x3ff0000 |
6044 | #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 |
6045 | #define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x1 |
6046 | #define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x0 |
6047 | #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x100 |
6048 | #define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x8 |
6049 | #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x200 |
6050 | #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x9 |
6051 | #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x10000 |
6052 | #define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x10 |
6053 | #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x20000 |
6054 | #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x11 |
6055 | #define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x1000000 |
6056 | #define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x18 |
6057 | #define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x2000000 |
6058 | #define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x19 |
6059 | #define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x1 |
6060 | #define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 |
6061 | #define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x100 |
6062 | #define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 |
6063 | #define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x10000 |
6064 | #define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 |
6065 | #define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x1000000 |
6066 | #define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 |
6067 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x1 |
6068 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 |
6069 | #define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x70 |
6070 | #define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 |
6071 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x100 |
6072 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 |
6073 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0xf0000 |
6074 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 |
6075 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x1000000 |
6076 | #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 |
6077 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0xf |
6078 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 |
6079 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x70 |
6080 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 |
6081 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x80 |
6082 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 |
6083 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x300 |
6084 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 |
6085 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x400 |
6086 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa |
6087 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x800 |
6088 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb |
6089 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x1000 |
6090 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc |
6091 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0xf0000 |
6092 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 |
6093 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x700000 |
6094 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 |
6095 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x800000 |
6096 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 |
6097 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x3000000 |
6098 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 |
6099 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x4000000 |
6100 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a |
6101 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x8000000 |
6102 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b |
6103 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000 |
6104 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c |
6105 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000 |
6106 | #define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f |
6107 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0xf |
6108 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 |
6109 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x70 |
6110 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 |
6111 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x80 |
6112 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 |
6113 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x300 |
6114 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 |
6115 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x400 |
6116 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa |
6117 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x800 |
6118 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb |
6119 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x1000 |
6120 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc |
6121 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0xf0000 |
6122 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 |
6123 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x700000 |
6124 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 |
6125 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x800000 |
6126 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 |
6127 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x3000000 |
6128 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 |
6129 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x4000000 |
6130 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a |
6131 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x8000000 |
6132 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b |
6133 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000 |
6134 | #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c |
6135 | #define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x1 |
6136 | #define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x0 |
6137 | #define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x10 |
6138 | #define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x4 |
6139 | #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x100 |
6140 | #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x8 |
6141 | #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x200 |
6142 | #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x9 |
6143 | #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x400 |
6144 | #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0xa |
6145 | #define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x7000 |
6146 | #define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0xc |
6147 | #define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x10000 |
6148 | #define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x10 |
6149 | #define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x20000 |
6150 | #define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x11 |
6151 | #define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x40000 |
6152 | #define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x12 |
6153 | #define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x1 |
6154 | #define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x0 |
6155 | #define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x2 |
6156 | #define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x1 |
6157 | #define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x4 |
6158 | #define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x2 |
6159 | #define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x8 |
6160 | #define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x3 |
6161 | #define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x100 |
6162 | #define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x8 |
6163 | #define DOUT_SCRATCH0__DOUT_SCRATCH0_MASK 0xffffffff |
6164 | #define DOUT_SCRATCH0__DOUT_SCRATCH0__SHIFT 0x0 |
6165 | #define DOUT_SCRATCH1__DOUT_SCRATCH1_MASK 0xffffffff |
6166 | #define DOUT_SCRATCH1__DOUT_SCRATCH1__SHIFT 0x0 |
6167 | #define DOUT_SCRATCH2__DOUT_SCRATCH2_MASK 0xffffffff |
6168 | #define DOUT_SCRATCH2__DOUT_SCRATCH2__SHIFT 0x0 |
6169 | #define DOUT_SCRATCH3__DOUT_SCRATCH3_MASK 0xffffffff |
6170 | #define DOUT_SCRATCH3__DOUT_SCRATCH3__SHIFT 0x0 |
6171 | #define DOUT_SCRATCH4__DOUT_SCRATCH4_MASK 0xffffffff |
6172 | #define DOUT_SCRATCH4__DOUT_SCRATCH4__SHIFT 0x0 |
6173 | #define DOUT_SCRATCH5__DOUT_SCRATCH5_MASK 0xffffffff |
6174 | #define DOUT_SCRATCH5__DOUT_SCRATCH5__SHIFT 0x0 |
6175 | #define DOUT_SCRATCH6__DOUT_SCRATCH6_MASK 0xffffffff |
6176 | #define DOUT_SCRATCH6__DOUT_SCRATCH6__SHIFT 0x0 |
6177 | #define DOUT_SCRATCH7__DOUT_SCRATCH7_MASK 0xffffffff |
6178 | #define DOUT_SCRATCH7__DOUT_SCRATCH7__SHIFT 0x0 |
6179 | #define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x7 |
6180 | #define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x0 |
6181 | #define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x70 |
6182 | #define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x4 |
6183 | #define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS_MASK 0x1 |
6184 | #define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS__SHIFT 0x0 |
6185 | #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK 0x2 |
6186 | #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE__SHIFT 0x1 |
6187 | #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK 0x10 |
6188 | #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT 0x4 |
6189 | #define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS_MASK 0x100 |
6190 | #define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS__SHIFT 0x8 |
6191 | #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 |
6192 | #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc |
6193 | #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 |
6194 | #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 |
6195 | #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x1 |
6196 | #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK__SHIFT 0x0 |
6197 | #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK 0x100 |
6198 | #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT 0x8 |
6199 | #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK 0x10000 |
6200 | #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN__SHIFT 0x10 |
6201 | #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK 0x100000 |
6202 | #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK__SHIFT 0x14 |
6203 | #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK 0x1000000 |
6204 | #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN__SHIFT 0x18 |
6205 | #define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER_MASK 0x1fff |
6206 | #define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT 0x0 |
6207 | #define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER_MASK 0x3ff0000 |
6208 | #define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT 0x10 |
6209 | #define DC_HPD1_CONTROL__DC_HPD1_EN_MASK 0x10000000 |
6210 | #define DC_HPD1_CONTROL__DC_HPD1_EN__SHIFT 0x1c |
6211 | #define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS_MASK 0x1 |
6212 | #define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS__SHIFT 0x0 |
6213 | #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK 0x2 |
6214 | #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE__SHIFT 0x1 |
6215 | #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED_MASK 0x10 |
6216 | #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED__SHIFT 0x4 |
6217 | #define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS_MASK 0x100 |
6218 | #define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS__SHIFT 0x8 |
6219 | #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 |
6220 | #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc |
6221 | #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 |
6222 | #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 |
6223 | #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK_MASK 0x1 |
6224 | #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK__SHIFT 0x0 |
6225 | #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK 0x100 |
6226 | #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY__SHIFT 0x8 |
6227 | #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN_MASK 0x10000 |
6228 | #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN__SHIFT 0x10 |
6229 | #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK_MASK 0x100000 |
6230 | #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK__SHIFT 0x14 |
6231 | #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN_MASK 0x1000000 |
6232 | #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN__SHIFT 0x18 |
6233 | #define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER_MASK 0x1fff |
6234 | #define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER__SHIFT 0x0 |
6235 | #define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER_MASK 0x3ff0000 |
6236 | #define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER__SHIFT 0x10 |
6237 | #define DC_HPD2_CONTROL__DC_HPD2_EN_MASK 0x10000000 |
6238 | #define DC_HPD2_CONTROL__DC_HPD2_EN__SHIFT 0x1c |
6239 | #define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS_MASK 0x1 |
6240 | #define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS__SHIFT 0x0 |
6241 | #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK 0x2 |
6242 | #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE__SHIFT 0x1 |
6243 | #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED_MASK 0x10 |
6244 | #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED__SHIFT 0x4 |
6245 | #define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS_MASK 0x100 |
6246 | #define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS__SHIFT 0x8 |
6247 | #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 |
6248 | #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc |
6249 | #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 |
6250 | #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 |
6251 | #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK_MASK 0x1 |
6252 | #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK__SHIFT 0x0 |
6253 | #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK 0x100 |
6254 | #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY__SHIFT 0x8 |
6255 | #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN_MASK 0x10000 |
6256 | #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN__SHIFT 0x10 |
6257 | #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK_MASK 0x100000 |
6258 | #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK__SHIFT 0x14 |
6259 | #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN_MASK 0x1000000 |
6260 | #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN__SHIFT 0x18 |
6261 | #define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER_MASK 0x1fff |
6262 | #define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER__SHIFT 0x0 |
6263 | #define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER_MASK 0x3ff0000 |
6264 | #define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER__SHIFT 0x10 |
6265 | #define DC_HPD3_CONTROL__DC_HPD3_EN_MASK 0x10000000 |
6266 | #define DC_HPD3_CONTROL__DC_HPD3_EN__SHIFT 0x1c |
6267 | #define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS_MASK 0x1 |
6268 | #define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS__SHIFT 0x0 |
6269 | #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK 0x2 |
6270 | #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE__SHIFT 0x1 |
6271 | #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED_MASK 0x10 |
6272 | #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED__SHIFT 0x4 |
6273 | #define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS_MASK 0x100 |
6274 | #define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS__SHIFT 0x8 |
6275 | #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 |
6276 | #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc |
6277 | #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 |
6278 | #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 |
6279 | #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK_MASK 0x1 |
6280 | #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK__SHIFT 0x0 |
6281 | #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK 0x100 |
6282 | #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY__SHIFT 0x8 |
6283 | #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN_MASK 0x10000 |
6284 | #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN__SHIFT 0x10 |
6285 | #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK_MASK 0x100000 |
6286 | #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK__SHIFT 0x14 |
6287 | #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN_MASK 0x1000000 |
6288 | #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN__SHIFT 0x18 |
6289 | #define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER_MASK 0x1fff |
6290 | #define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER__SHIFT 0x0 |
6291 | #define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER_MASK 0x3ff0000 |
6292 | #define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER__SHIFT 0x10 |
6293 | #define DC_HPD4_CONTROL__DC_HPD4_EN_MASK 0x10000000 |
6294 | #define DC_HPD4_CONTROL__DC_HPD4_EN__SHIFT 0x1c |
6295 | #define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS_MASK 0x1 |
6296 | #define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS__SHIFT 0x0 |
6297 | #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK 0x2 |
6298 | #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE__SHIFT 0x1 |
6299 | #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED_MASK 0x10 |
6300 | #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED__SHIFT 0x4 |
6301 | #define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS_MASK 0x100 |
6302 | #define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS__SHIFT 0x8 |
6303 | #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 |
6304 | #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc |
6305 | #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 |
6306 | #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 |
6307 | #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK_MASK 0x1 |
6308 | #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK__SHIFT 0x0 |
6309 | #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK 0x100 |
6310 | #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY__SHIFT 0x8 |
6311 | #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN_MASK 0x10000 |
6312 | #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN__SHIFT 0x10 |
6313 | #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK_MASK 0x100000 |
6314 | #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK__SHIFT 0x14 |
6315 | #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN_MASK 0x1000000 |
6316 | #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN__SHIFT 0x18 |
6317 | #define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER_MASK 0x1fff |
6318 | #define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER__SHIFT 0x0 |
6319 | #define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER_MASK 0x3ff0000 |
6320 | #define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER__SHIFT 0x10 |
6321 | #define DC_HPD5_CONTROL__DC_HPD5_EN_MASK 0x10000000 |
6322 | #define DC_HPD5_CONTROL__DC_HPD5_EN__SHIFT 0x1c |
6323 | #define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS_MASK 0x1 |
6324 | #define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS__SHIFT 0x0 |
6325 | #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK 0x2 |
6326 | #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE__SHIFT 0x1 |
6327 | #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED_MASK 0x10 |
6328 | #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED__SHIFT 0x4 |
6329 | #define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS_MASK 0x100 |
6330 | #define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS__SHIFT 0x8 |
6331 | #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL_MASK 0xff000 |
6332 | #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc |
6333 | #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000 |
6334 | #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 |
6335 | #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK_MASK 0x1 |
6336 | #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK__SHIFT 0x0 |
6337 | #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK 0x100 |
6338 | #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY__SHIFT 0x8 |
6339 | #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN_MASK 0x10000 |
6340 | #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN__SHIFT 0x10 |
6341 | #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK_MASK 0x100000 |
6342 | #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK__SHIFT 0x14 |
6343 | #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN_MASK 0x1000000 |
6344 | #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN__SHIFT 0x18 |
6345 | #define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER_MASK 0x1fff |
6346 | #define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER__SHIFT 0x0 |
6347 | #define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER_MASK 0x3ff0000 |
6348 | #define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER__SHIFT 0x10 |
6349 | #define DC_HPD6_CONTROL__DC_HPD6_EN_MASK 0x10000000 |
6350 | #define DC_HPD6_CONTROL__DC_HPD6_EN__SHIFT 0x1c |
6351 | #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY_MASK 0xff |
6352 | #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY__SHIFT 0x0 |
6353 | #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 |
6354 | #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc |
6355 | #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN_MASK 0x1000000 |
6356 | #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN__SHIFT 0x18 |
6357 | #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 |
6358 | #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c |
6359 | #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY_MASK 0xff |
6360 | #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY__SHIFT 0x0 |
6361 | #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 |
6362 | #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc |
6363 | #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN_MASK 0x1000000 |
6364 | #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN__SHIFT 0x18 |
6365 | #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 |
6366 | #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c |
6367 | #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY_MASK 0xff |
6368 | #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY__SHIFT 0x0 |
6369 | #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 |
6370 | #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc |
6371 | #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN_MASK 0x1000000 |
6372 | #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN__SHIFT 0x18 |
6373 | #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 |
6374 | #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c |
6375 | #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY_MASK 0xff |
6376 | #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY__SHIFT 0x0 |
6377 | #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 |
6378 | #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc |
6379 | #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN_MASK 0x1000000 |
6380 | #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN__SHIFT 0x18 |
6381 | #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 |
6382 | #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c |
6383 | #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY_MASK 0xff |
6384 | #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY__SHIFT 0x0 |
6385 | #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 |
6386 | #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc |
6387 | #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN_MASK 0x1000000 |
6388 | #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN__SHIFT 0x18 |
6389 | #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 |
6390 | #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c |
6391 | #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY_MASK 0xff |
6392 | #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY__SHIFT 0x0 |
6393 | #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY_MASK 0xff000 |
6394 | #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc |
6395 | #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN_MASK 0x1000000 |
6396 | #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN__SHIFT 0x18 |
6397 | #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN_MASK 0x10000000 |
6398 | #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c |
6399 | #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY_MASK 0xff |
6400 | #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY__SHIFT 0x0 |
6401 | #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY_MASK 0xff00000 |
6402 | #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY__SHIFT 0x14 |
6403 | #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY_MASK 0xff |
6404 | #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY__SHIFT 0x0 |
6405 | #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY_MASK 0xff00000 |
6406 | #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY__SHIFT 0x14 |
6407 | #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY_MASK 0xff |
6408 | #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY__SHIFT 0x0 |
6409 | #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY_MASK 0xff00000 |
6410 | #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY__SHIFT 0x14 |
6411 | #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY_MASK 0xff |
6412 | #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY__SHIFT 0x0 |
6413 | #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY_MASK 0xff00000 |
6414 | #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY__SHIFT 0x14 |
6415 | #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY_MASK 0xff |
6416 | #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY__SHIFT 0x0 |
6417 | #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY_MASK 0xff00000 |
6418 | #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY__SHIFT 0x14 |
6419 | #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY_MASK 0xff |
6420 | #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY__SHIFT 0x0 |
6421 | #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY_MASK 0xff00000 |
6422 | #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY__SHIFT 0x14 |
6423 | #define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x1 |
6424 | #define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 |
6425 | #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x2 |
6426 | #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 |
6427 | #define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x4 |
6428 | #define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 |
6429 | #define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x8 |
6430 | #define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 |
6431 | #define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x700 |
6432 | #define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 |
6433 | #define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x300000 |
6434 | #define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 |
6435 | #define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000 |
6436 | #define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f |
6437 | #define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x3 |
6438 | #define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 |
6439 | #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0xc |
6440 | #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 |
6441 | #define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x10 |
6442 | #define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 |
6443 | #define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x100 |
6444 | #define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 |
6445 | #define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x1000 |
6446 | #define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc |
6447 | #define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x100000 |
6448 | #define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 |
6449 | #define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x200000 |
6450 | #define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 |
6451 | #define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x1000000 |
6452 | #define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 |
6453 | #define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x2000000 |
6454 | #define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 |
6455 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x1 |
6456 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 |
6457 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x2 |
6458 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 |
6459 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x4 |
6460 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 |
6461 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x10 |
6462 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 |
6463 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x20 |
6464 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 |
6465 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x40 |
6466 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 |
6467 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x100 |
6468 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 |
6469 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x200 |
6470 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 |
6471 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x400 |
6472 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa |
6473 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x1000 |
6474 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc |
6475 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x2000 |
6476 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd |
6477 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x4000 |
6478 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe |
6479 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x10000 |
6480 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 |
6481 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x20000 |
6482 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 |
6483 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x40000 |
6484 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 |
6485 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x100000 |
6486 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 |
6487 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x200000 |
6488 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 |
6489 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x400000 |
6490 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 |
6491 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x1000000 |
6492 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 |
6493 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x2000000 |
6494 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 |
6495 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x4000000 |
6496 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a |
6497 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x8000000 |
6498 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b |
6499 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000 |
6500 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c |
6501 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000 |
6502 | #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d |
6503 | #define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x3 |
6504 | #define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 |
6505 | #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x4 |
6506 | #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 |
6507 | #define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x10 |
6508 | #define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 |
6509 | #define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x20 |
6510 | #define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 |
6511 | #define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x40 |
6512 | #define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 |
6513 | #define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x80 |
6514 | #define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 |
6515 | #define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x100 |
6516 | #define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 |
6517 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x1000 |
6518 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc |
6519 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x2000 |
6520 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd |
6521 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x4000 |
6522 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe |
6523 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x8000 |
6524 | #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf |
6525 | #define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x40000 |
6526 | #define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 |
6527 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x3 |
6528 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 |
6529 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x8 |
6530 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 |
6531 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x10000 |
6532 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 |
6533 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x20000 |
6534 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 |
6535 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x100000 |
6536 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 |
6537 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 |
6538 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
6539 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000 |
6540 | #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c |
6541 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x3 |
6542 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 |
6543 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x8 |
6544 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 |
6545 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x10000 |
6546 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 |
6547 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x20000 |
6548 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 |
6549 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x100000 |
6550 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 |
6551 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 |
6552 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
6553 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000 |
6554 | #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c |
6555 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x3 |
6556 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 |
6557 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x8 |
6558 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 |
6559 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x10000 |
6560 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 |
6561 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x20000 |
6562 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 |
6563 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x100000 |
6564 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 |
6565 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 |
6566 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
6567 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000 |
6568 | #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c |
6569 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x3 |
6570 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 |
6571 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x8 |
6572 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 |
6573 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x10000 |
6574 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 |
6575 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x20000 |
6576 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 |
6577 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x100000 |
6578 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 |
6579 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 |
6580 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
6581 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000 |
6582 | #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c |
6583 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x3 |
6584 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 |
6585 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x8 |
6586 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 |
6587 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x10000 |
6588 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 |
6589 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x20000 |
6590 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 |
6591 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x100000 |
6592 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 |
6593 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 |
6594 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
6595 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000 |
6596 | #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c |
6597 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x3 |
6598 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x0 |
6599 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x8 |
6600 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x3 |
6601 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x10000 |
6602 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x10 |
6603 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x20000 |
6604 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x11 |
6605 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x100000 |
6606 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x14 |
6607 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 |
6608 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
6609 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000 |
6610 | #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x1c |
6611 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x3 |
6612 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 |
6613 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
6614 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
6615 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000 |
6616 | #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 |
6617 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x1 |
6618 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 |
6619 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x2 |
6620 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 |
6621 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x10 |
6622 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 |
6623 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x20 |
6624 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 |
6625 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x40 |
6626 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 |
6627 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x80 |
6628 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 |
6629 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0xff00 |
6630 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 |
6631 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0xff0000 |
6632 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
6633 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000 |
6634 | #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 |
6635 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x3 |
6636 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 |
6637 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
6638 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
6639 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000 |
6640 | #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 |
6641 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x1 |
6642 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 |
6643 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x2 |
6644 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 |
6645 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x10 |
6646 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 |
6647 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x20 |
6648 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 |
6649 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x40 |
6650 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 |
6651 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x80 |
6652 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 |
6653 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0xff00 |
6654 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 |
6655 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0xff0000 |
6656 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
6657 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000 |
6658 | #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 |
6659 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x3 |
6660 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 |
6661 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
6662 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
6663 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000 |
6664 | #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 |
6665 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x1 |
6666 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 |
6667 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x2 |
6668 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 |
6669 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x10 |
6670 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 |
6671 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x20 |
6672 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 |
6673 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x40 |
6674 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 |
6675 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x80 |
6676 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 |
6677 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0xff00 |
6678 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 |
6679 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0xff0000 |
6680 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
6681 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000 |
6682 | #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 |
6683 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x3 |
6684 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 |
6685 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
6686 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
6687 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000 |
6688 | #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 |
6689 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x1 |
6690 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 |
6691 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x2 |
6692 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 |
6693 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x10 |
6694 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 |
6695 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x20 |
6696 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 |
6697 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x40 |
6698 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 |
6699 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x80 |
6700 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 |
6701 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0xff00 |
6702 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 |
6703 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0xff0000 |
6704 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
6705 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000 |
6706 | #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 |
6707 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x3 |
6708 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 |
6709 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
6710 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
6711 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000 |
6712 | #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 |
6713 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x1 |
6714 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 |
6715 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x2 |
6716 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 |
6717 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x10 |
6718 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 |
6719 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x20 |
6720 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 |
6721 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x40 |
6722 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 |
6723 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x80 |
6724 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 |
6725 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0xff00 |
6726 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 |
6727 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0xff0000 |
6728 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
6729 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000 |
6730 | #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 |
6731 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x3 |
6732 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x0 |
6733 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
6734 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
6735 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000 |
6736 | #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x10 |
6737 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x1 |
6738 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x0 |
6739 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x2 |
6740 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x1 |
6741 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x10 |
6742 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x4 |
6743 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x20 |
6744 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x5 |
6745 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x40 |
6746 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x6 |
6747 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x80 |
6748 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x7 |
6749 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0xff00 |
6750 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x8 |
6751 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0xff0000 |
6752 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
6753 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000 |
6754 | #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x18 |
6755 | #define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x1 |
6756 | #define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 |
6757 | #define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x100 |
6758 | #define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 |
6759 | #define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x1000 |
6760 | #define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc |
6761 | #define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x2000 |
6762 | #define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd |
6763 | #define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0xff0000 |
6764 | #define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 |
6765 | #define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x1 |
6766 | #define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 |
6767 | #define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x100 |
6768 | #define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 |
6769 | #define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x1000 |
6770 | #define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc |
6771 | #define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x2000 |
6772 | #define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd |
6773 | #define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0xff0000 |
6774 | #define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 |
6775 | #define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x1 |
6776 | #define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 |
6777 | #define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x100 |
6778 | #define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 |
6779 | #define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x1000 |
6780 | #define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc |
6781 | #define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x2000 |
6782 | #define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd |
6783 | #define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0xff0000 |
6784 | #define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 |
6785 | #define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x1 |
6786 | #define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 |
6787 | #define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x100 |
6788 | #define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 |
6789 | #define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x1000 |
6790 | #define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc |
6791 | #define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x2000 |
6792 | #define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd |
6793 | #define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0xff0000 |
6794 | #define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 |
6795 | #define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x1 |
6796 | #define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 |
6797 | #define DC_I2C_DATA__DC_I2C_DATA_MASK 0xff00 |
6798 | #define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 |
6799 | #define DC_I2C_DATA__DC_I2C_INDEX_MASK 0xff0000 |
6800 | #define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 |
6801 | #define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000 |
6802 | #define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f |
6803 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x1 |
6804 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x0 |
6805 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x2 |
6806 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x1 |
6807 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x4 |
6808 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x2 |
6809 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x8 |
6810 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x3 |
6811 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000 |
6812 | #define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x1f |
6813 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x1 |
6814 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x0 |
6815 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x2 |
6816 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x1 |
6817 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x4 |
6818 | #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x2 |
6819 | #define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0xf |
6820 | #define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x0 |
6821 | #define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x10 |
6822 | #define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x4 |
6823 | #define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x20 |
6824 | #define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x5 |
6825 | #define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x40 |
6826 | #define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x6 |
6827 | #define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x200 |
6828 | #define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x9 |
6829 | #define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x400 |
6830 | #define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0xa |
6831 | #define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x3 |
6832 | #define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x0 |
6833 | #define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
6834 | #define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
6835 | #define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000 |
6836 | #define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x10 |
6837 | #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x1 |
6838 | #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x0 |
6839 | #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x2 |
6840 | #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x1 |
6841 | #define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x80 |
6842 | #define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x7 |
6843 | #define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0xff00 |
6844 | #define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x8 |
6845 | #define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000 |
6846 | #define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x18 |
6847 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x1 |
6848 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x0 |
6849 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x100 |
6850 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x8 |
6851 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x200 |
6852 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x9 |
6853 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x1000 |
6854 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0xc |
6855 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x2000 |
6856 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0xd |
6857 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0xf0000 |
6858 | #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x10 |
6859 | #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x1 |
6860 | #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x0 |
6861 | #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0xff00 |
6862 | #define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x8 |
6863 | #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0xf0000 |
6864 | #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x10 |
6865 | #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000 |
6866 | #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x1f |
6867 | #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x7f |
6868 | #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x0 |
6869 | #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x7f00 |
6870 | #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x8 |
6871 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x1 |
6872 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x0 |
6873 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x2 |
6874 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x1 |
6875 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x4 |
6876 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x2 |
6877 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x10 |
6878 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x4 |
6879 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x20 |
6880 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x5 |
6881 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x40 |
6882 | #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x6 |
6883 | #define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x1 |
6884 | #define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x0 |
6885 | #define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 |
6886 | #define DISP_INTERRUPT_STATUS__D1BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
6887 | #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x4 |
6888 | #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x2 |
6889 | #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x8 |
6890 | #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x3 |
6891 | #define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x10 |
6892 | #define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
6893 | #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 |
6894 | #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
6895 | #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 |
6896 | #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
6897 | #define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x80 |
6898 | #define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x7 |
6899 | #define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x100 |
6900 | #define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x8 |
6901 | #define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x200 |
6902 | #define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
6903 | #define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 |
6904 | #define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
6905 | #define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 |
6906 | #define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
6907 | #define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 |
6908 | #define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
6909 | #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x20000 |
6910 | #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 |
6911 | #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x40000 |
6912 | #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 |
6913 | #define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x80000 |
6914 | #define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 |
6915 | #define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x100000 |
6916 | #define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 |
6917 | #define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x200000 |
6918 | #define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x15 |
6919 | #define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x400000 |
6920 | #define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x16 |
6921 | #define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x800000 |
6922 | #define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x17 |
6923 | #define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x1000000 |
6924 | #define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 |
6925 | #define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x2000000 |
6926 | #define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x19 |
6927 | #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x4000000 |
6928 | #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x1a |
6929 | #define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x8000000 |
6930 | #define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x1b |
6931 | #define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000 |
6932 | #define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x1c |
6933 | #define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000 |
6934 | #define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x1d |
6935 | #define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000 |
6936 | #define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x1e |
6937 | #define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000 |
6938 | #define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f |
6939 | #define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x1 |
6940 | #define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x0 |
6941 | #define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 |
6942 | #define DISP_INTERRUPT_STATUS_CONTINUE__D2BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
6943 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x4 |
6944 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x2 |
6945 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x8 |
6946 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x3 |
6947 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x10 |
6948 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
6949 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 |
6950 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
6951 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 |
6952 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
6953 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x80 |
6954 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x7 |
6955 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x100 |
6956 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x8 |
6957 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x200 |
6958 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
6959 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 |
6960 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
6961 | #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 |
6962 | #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
6963 | #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 |
6964 | #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
6965 | #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x20000 |
6966 | #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 |
6967 | #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x40000 |
6968 | #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 |
6969 | #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x80000 |
6970 | #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 |
6971 | #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x100000 |
6972 | #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 |
6973 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT_MASK 0x200000 |
6974 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D1_VLINE2_INTERRUPT__SHIFT 0x15 |
6975 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT_MASK 0x400000 |
6976 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE2_INTERRUPT__SHIFT 0x16 |
6977 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT_MASK 0x800000 |
6978 | #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D3_VLINE2_INTERRUPT__SHIFT 0x17 |
6979 | #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT_MASK 0x1000000 |
6980 | #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT__SHIFT 0x18 |
6981 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 |
6982 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 |
6983 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 |
6984 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a |
6985 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 |
6986 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b |
6987 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0_MASK 0x10000000 |
6988 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT0__SHIFT 0x1c |
6989 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1_MASK 0x20000000 |
6990 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT1__SHIFT 0x1d |
6991 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2_MASK 0x40000000 |
6992 | #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC1_VERTICAL_INTERRUPT2__SHIFT 0x1e |
6993 | #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000 |
6994 | #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f |
6995 | #define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x1 |
6996 | #define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x0 |
6997 | #define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 |
6998 | #define DISP_INTERRUPT_STATUS_CONTINUE2__D3BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
6999 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x4 |
7000 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x2 |
7001 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x8 |
7002 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x3 |
7003 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x10 |
7004 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
7005 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 |
7006 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
7007 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 |
7008 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
7009 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x80 |
7010 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x7 |
7011 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x100 |
7012 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x8 |
7013 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x200 |
7014 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
7015 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 |
7016 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
7017 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 |
7018 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
7019 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 |
7020 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
7021 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x20000 |
7022 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 |
7023 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x40000 |
7024 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 |
7025 | #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x80000 |
7026 | #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 |
7027 | #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x100000 |
7028 | #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 |
7029 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT_MASK 0x200000 |
7030 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D4_VLINE2_INTERRUPT__SHIFT 0x15 |
7031 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT_MASK 0x400000 |
7032 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D5_VLINE2_INTERRUPT__SHIFT 0x16 |
7033 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT_MASK 0x800000 |
7034 | #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D6_VLINE2_INTERRUPT__SHIFT 0x17 |
7035 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 |
7036 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 |
7037 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 |
7038 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a |
7039 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 |
7040 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b |
7041 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0_MASK 0x10000000 |
7042 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT0__SHIFT 0x1c |
7043 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1_MASK 0x20000000 |
7044 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT1__SHIFT 0x1d |
7045 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2_MASK 0x40000000 |
7046 | #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC2_VERTICAL_INTERRUPT2__SHIFT 0x1e |
7047 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000 |
7048 | #define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f |
7049 | #define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x1 |
7050 | #define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x0 |
7051 | #define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 |
7052 | #define DISP_INTERRUPT_STATUS_CONTINUE3__D4BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
7053 | #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x4 |
7054 | #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x2 |
7055 | #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x8 |
7056 | #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x3 |
7057 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x10 |
7058 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
7059 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 |
7060 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
7061 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 |
7062 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
7063 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x80 |
7064 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x7 |
7065 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x100 |
7066 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x8 |
7067 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x200 |
7068 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
7069 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 |
7070 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
7071 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 |
7072 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
7073 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 |
7074 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
7075 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x20000 |
7076 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 |
7077 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x40000 |
7078 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 |
7079 | #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x80000 |
7080 | #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 |
7081 | #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x100000 |
7082 | #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 |
7083 | #define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT_MASK 0x200000 |
7084 | #define DISP_INTERRUPT_STATUS_CONTINUE3__BUFMGR_IHIF_INTERRUPT__SHIFT 0x15 |
7085 | #define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_HOST_CONFLICT_INTERRUPT_MASK 0x400000 |
7086 | #define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_HOST_CONFLICT_INTERRUPT__SHIFT 0x16 |
7087 | #define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_DATA_OVERFLOW_INTERRUPT_MASK 0x800000 |
7088 | #define DISP_INTERRUPT_STATUS_CONTINUE3__SISCL_DATA_OVERFLOW_INTERRUPT__SHIFT 0x17 |
7089 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 |
7090 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 |
7091 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 |
7092 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a |
7093 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 |
7094 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b |
7095 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0_MASK 0x10000000 |
7096 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT0__SHIFT 0x1c |
7097 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1_MASK 0x20000000 |
7098 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT1__SHIFT 0x1d |
7099 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2_MASK 0x40000000 |
7100 | #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC3_VERTICAL_INTERRUPT2__SHIFT 0x1e |
7101 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000 |
7102 | #define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f |
7103 | #define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x1 |
7104 | #define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x0 |
7105 | #define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 |
7106 | #define DISP_INTERRUPT_STATUS_CONTINUE4__D5BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
7107 | #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x4 |
7108 | #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x2 |
7109 | #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x8 |
7110 | #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x3 |
7111 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x10 |
7112 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
7113 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 |
7114 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
7115 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 |
7116 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
7117 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x80 |
7118 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x7 |
7119 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x100 |
7120 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x8 |
7121 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x200 |
7122 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
7123 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 |
7124 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
7125 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 |
7126 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
7127 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 |
7128 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
7129 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x20000 |
7130 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 |
7131 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x40000 |
7132 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 |
7133 | #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x80000 |
7134 | #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 |
7135 | #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x100000 |
7136 | #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 |
7137 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 |
7138 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 |
7139 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 |
7140 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 |
7141 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 |
7142 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 |
7143 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x2000000 |
7144 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x19 |
7145 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT_MASK 0x4000000 |
7146 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x1a |
7147 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x8000000 |
7148 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x1b |
7149 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0_MASK 0x10000000 |
7150 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT0__SHIFT 0x1c |
7151 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1_MASK 0x20000000 |
7152 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT1__SHIFT 0x1d |
7153 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2_MASK 0x40000000 |
7154 | #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC4_VERTICAL_INTERRUPT2__SHIFT 0x1e |
7155 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000 |
7156 | #define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f |
7157 | #define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x1 |
7158 | #define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x0 |
7159 | #define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT_MASK 0x2 |
7160 | #define DISP_INTERRUPT_STATUS_CONTINUE5__D6BLND_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 |
7161 | #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x4 |
7162 | #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x2 |
7163 | #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x8 |
7164 | #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x3 |
7165 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x10 |
7166 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x4 |
7167 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x20 |
7168 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 |
7169 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x40 |
7170 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 |
7171 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x80 |
7172 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x7 |
7173 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x100 |
7174 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x8 |
7175 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x200 |
7176 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x9 |
7177 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x400 |
7178 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa |
7179 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 |
7180 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
7181 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 |
7182 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
7183 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x20000 |
7184 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 |
7185 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x40000 |
7186 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 |
7187 | #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x80000 |
7188 | #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 |
7189 | #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x100000 |
7190 | #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 |
7191 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT_MASK 0x400000 |
7192 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT__SHIFT 0x16 |
7193 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT_MASK 0x800000 |
7194 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_INTERRUPT__SHIFT 0x17 |
7195 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_MASK 0x1000000 |
7196 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT__SHIFT 0x18 |
7197 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0_MASK 0x2000000 |
7198 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT0__SHIFT 0x19 |
7199 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1_MASK 0x4000000 |
7200 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT1__SHIFT 0x1a |
7201 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2_MASK 0x8000000 |
7202 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC5_VERTICAL_INTERRUPT2__SHIFT 0x1b |
7203 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0_MASK 0x10000000 |
7204 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT0__SHIFT 0x1c |
7205 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1_MASK 0x20000000 |
7206 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT1__SHIFT 0x1d |
7207 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2_MASK 0x40000000 |
7208 | #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VERTICAL_INTERRUPT2__SHIFT 0x1e |
7209 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000 |
7210 | #define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f |
7211 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x8000 |
7212 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf |
7213 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x10000 |
7214 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 |
7215 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x20000 |
7216 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x11 |
7217 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK 0x40000 |
7218 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x12 |
7219 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x80000 |
7220 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x13 |
7221 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK 0x100000 |
7222 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x14 |
7223 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x200000 |
7224 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x15 |
7225 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK 0x400000 |
7226 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x16 |
7227 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x800000 |
7228 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x17 |
7229 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK 0x1000000 |
7230 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x18 |
7231 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x2000000 |
7232 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x19 |
7233 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK 0x4000000 |
7234 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1a |
7235 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK 0x8000000 |
7236 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT 0x1b |
7237 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK 0x10000000 |
7238 | #define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT 0x1c |
7239 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000 |
7240 | #define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f |
7241 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 |
7242 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
7243 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 |
7244 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
7245 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 |
7246 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 |
7247 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 |
7248 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 |
7249 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 |
7250 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 |
7251 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 |
7252 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 |
7253 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 |
7254 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 |
7255 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 |
7256 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 |
7257 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 |
7258 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 |
7259 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 |
7260 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 |
7261 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 |
7262 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa |
7263 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 |
7264 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb |
7265 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 |
7266 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc |
7267 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 |
7268 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd |
7269 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 |
7270 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe |
7271 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 |
7272 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf |
7273 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 |
7274 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 |
7275 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 |
7276 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCI_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 |
7277 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 |
7278 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 |
7279 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 |
7280 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 |
7281 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 |
7282 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 |
7283 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 |
7284 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 |
7285 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 |
7286 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 |
7287 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 |
7288 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 |
7289 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 |
7290 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 |
7291 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 |
7292 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 |
7293 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 |
7294 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DCO_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a |
7295 | #define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER0_INTERRUPT_MASK 0x8000000 |
7296 | #define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b |
7297 | #define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000 |
7298 | #define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c |
7299 | #define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER2_INTERRUPT_MASK 0x20000000 |
7300 | #define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x1d |
7301 | #define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER3_INTERRUPT_MASK 0x40000000 |
7302 | #define DISP_INTERRUPT_STATUS_CONTINUE7__SCANIN_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x1e |
7303 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000 |
7304 | #define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f |
7305 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 |
7306 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
7307 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 |
7308 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
7309 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 |
7310 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 |
7311 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 |
7312 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 |
7313 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 |
7314 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 |
7315 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 |
7316 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 |
7317 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 |
7318 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 |
7319 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 |
7320 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 |
7321 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 |
7322 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE0_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 |
7323 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 |
7324 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 |
7325 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 |
7326 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa |
7327 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 |
7328 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb |
7329 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 |
7330 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc |
7331 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 |
7332 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd |
7333 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 |
7334 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe |
7335 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 |
7336 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf |
7337 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 |
7338 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 |
7339 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 |
7340 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE1_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 |
7341 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 |
7342 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 |
7343 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 |
7344 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 |
7345 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 |
7346 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 |
7347 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 |
7348 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 |
7349 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 |
7350 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 |
7351 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 |
7352 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 |
7353 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 |
7354 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 |
7355 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 |
7356 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 |
7357 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 |
7358 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DCFE2_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a |
7359 | #define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER4_INTERRUPT_MASK 0x8000000 |
7360 | #define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x1b |
7361 | #define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER5_INTERRUPT_MASK 0x10000000 |
7362 | #define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x1c |
7363 | #define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER6_INTERRUPT_MASK 0x20000000 |
7364 | #define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x1d |
7365 | #define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER7_INTERRUPT_MASK 0x40000000 |
7366 | #define DISP_INTERRUPT_STATUS_CONTINUE8__SCANIN_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x1e |
7367 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000 |
7368 | #define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f |
7369 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT_MASK 0x1 |
7370 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 |
7371 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT_MASK 0x2 |
7372 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 |
7373 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT_MASK 0x4 |
7374 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x2 |
7375 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT_MASK 0x8 |
7376 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x3 |
7377 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT_MASK 0x10 |
7378 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x4 |
7379 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT_MASK 0x20 |
7380 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x5 |
7381 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT_MASK 0x40 |
7382 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x6 |
7383 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT_MASK 0x80 |
7384 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x7 |
7385 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x100 |
7386 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE3_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x8 |
7387 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT_MASK 0x200 |
7388 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 |
7389 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT_MASK 0x400 |
7390 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa |
7391 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT_MASK 0x800 |
7392 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER2_INTERRUPT__SHIFT 0xb |
7393 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT_MASK 0x1000 |
7394 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER3_INTERRUPT__SHIFT 0xc |
7395 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT_MASK 0x2000 |
7396 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER4_INTERRUPT__SHIFT 0xd |
7397 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT_MASK 0x4000 |
7398 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER5_INTERRUPT__SHIFT 0xe |
7399 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT_MASK 0x8000 |
7400 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER6_INTERRUPT__SHIFT 0xf |
7401 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT_MASK 0x10000 |
7402 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x10 |
7403 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x20000 |
7404 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE4_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x11 |
7405 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT_MASK 0x40000 |
7406 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 |
7407 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT_MASK 0x80000 |
7408 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 |
7409 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT_MASK 0x100000 |
7410 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER2_INTERRUPT__SHIFT 0x14 |
7411 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT_MASK 0x200000 |
7412 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER3_INTERRUPT__SHIFT 0x15 |
7413 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT_MASK 0x400000 |
7414 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER4_INTERRUPT__SHIFT 0x16 |
7415 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT_MASK 0x800000 |
7416 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER5_INTERRUPT__SHIFT 0x17 |
7417 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT_MASK 0x1000000 |
7418 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER6_INTERRUPT__SHIFT 0x18 |
7419 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT_MASK 0x2000000 |
7420 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER7_INTERRUPT__SHIFT 0x19 |
7421 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x4000000 |
7422 | #define DISP_INTERRUPT_STATUS_CONTINUE9__DCFE5_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1a |
7423 | #define DISP_INTERRUPT_STATUS_CONTINUE9__SCANIN_PERFMON_COUNTER_OFF_INTERRUPT_MASK 0x8000000 |
7424 | #define DISP_INTERRUPT_STATUS_CONTINUE9__SCANIN_PERFMON_COUNTER_OFF_INTERRUPT__SHIFT 0x1b |
7425 | #define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x1 |
7426 | #define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 |
7427 | #define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x100 |
7428 | #define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 |
7429 | #define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff |
7430 | #define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 |
7431 | #define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 |
7432 | #define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 |
7433 | #define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x4000000 |
7434 | #define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x1a |
7435 | #define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK_MASK 0x8000000 |
7436 | #define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK__SHIFT 0x1b |
7437 | #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000 |
7438 | #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x1c |
7439 | #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000 |
7440 | #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1d |
7441 | #define DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK 0x40000000 |
7442 | #define DISP_TIMER_CONTROL__DISP_TIMER_INT__SHIFT 0x1e |
7443 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x3 |
7444 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x0 |
7445 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x8 |
7446 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x3 |
7447 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x10000 |
7448 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x10 |
7449 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x20000 |
7450 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x11 |
7451 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x100000 |
7452 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x14 |
7453 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0xf000000 |
7454 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 |
7455 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000 |
7456 | #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x1c |
7457 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x3 |
7458 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x0 |
7459 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x10 |
7460 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 |
7461 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000 |
7462 | #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x10 |
7463 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x1 |
7464 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x0 |
7465 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x2 |
7466 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x1 |
7467 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x10 |
7468 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x4 |
7469 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x20 |
7470 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x5 |
7471 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x40 |
7472 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x6 |
7473 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x80 |
7474 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x7 |
7475 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0xff00 |
7476 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x8 |
7477 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0xff0000 |
7478 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x10 |
7479 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000 |
7480 | #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x18 |
7481 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0xffff |
7482 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 |
7483 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0xf00000 |
7484 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 |
7485 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000 |
7486 | #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c |
7487 | #define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x7 |
7488 | #define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x0 |
7489 | #define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x70000 |
7490 | #define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x10 |
7491 | #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX_MASK 0xff |
7492 | #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX__SHIFT 0x0 |
7493 | #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN_MASK 0x100 |
7494 | #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
7495 | #define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA_MASK 0xffffffff |
7496 | #define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA__SHIFT 0x0 |
7497 | #define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A_MASK 0xffffffff |
7498 | #define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A__SHIFT 0x0 |
7499 | #define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B_MASK 0xffffffff |
7500 | #define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B__SHIFT 0x0 |
7501 | #define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C_MASK 0xffffffff |
7502 | #define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C__SHIFT 0x0 |
7503 | #define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D_MASK 0xffffffff |
7504 | #define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D__SHIFT 0x0 |
7505 | #define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E_MASK 0xffffffff |
7506 | #define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E__SHIFT 0x0 |
7507 | #define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F_MASK 0xffffffff |
7508 | #define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F__SHIFT 0x0 |
7509 | #define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G_MASK 0xffffffff |
7510 | #define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G__SHIFT 0x0 |
7511 | #define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H_MASK 0xffffffff |
7512 | #define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H__SHIFT 0x0 |
7513 | #define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I_MASK 0xffffffff |
7514 | #define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I__SHIFT 0x0 |
7515 | #define DP_AUX1_DEBUG_J__DP_AUX1_DEBUG_J_MASK 0xffffffff |
7516 | #define DP_AUX1_DEBUG_J__DP_AUX1_DEBUG_J__SHIFT 0x0 |
7517 | #define DP_AUX1_DEBUG_K__DP_AUX1_DEBUG_K_MASK 0xffffffff |
7518 | #define DP_AUX1_DEBUG_K__DP_AUX1_DEBUG_K__SHIFT 0x0 |
7519 | #define DP_AUX1_DEBUG_L__DP_AUX1_DEBUG_L_MASK 0xffffffff |
7520 | #define DP_AUX1_DEBUG_L__DP_AUX1_DEBUG_L__SHIFT 0x0 |
7521 | #define DP_AUX1_DEBUG_M__DP_AUX1_DEBUG_M_MASK 0xffffffff |
7522 | #define DP_AUX1_DEBUG_M__DP_AUX1_DEBUG_M__SHIFT 0x0 |
7523 | #define DP_AUX1_DEBUG_N__DP_AUX1_DEBUG_N_MASK 0xffffffff |
7524 | #define DP_AUX1_DEBUG_N__DP_AUX1_DEBUG_N__SHIFT 0x0 |
7525 | #define DP_AUX1_DEBUG_O__DP_AUX1_DEBUG_O_MASK 0xffffffff |
7526 | #define DP_AUX1_DEBUG_O__DP_AUX1_DEBUG_O__SHIFT 0x0 |
7527 | #define DP_AUX1_DEBUG_P__DP_AUX1_DEBUG_P_MASK 0xffffffff |
7528 | #define DP_AUX1_DEBUG_P__DP_AUX1_DEBUG_P__SHIFT 0x0 |
7529 | #define DP_AUX1_DEBUG_Q__DP_AUX1_DEBUG_Q_MASK 0xffffffff |
7530 | #define DP_AUX1_DEBUG_Q__DP_AUX1_DEBUG_Q__SHIFT 0x0 |
7531 | #define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A_MASK 0xffffffff |
7532 | #define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A__SHIFT 0x0 |
7533 | #define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B_MASK 0xffffffff |
7534 | #define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B__SHIFT 0x0 |
7535 | #define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C_MASK 0xffffffff |
7536 | #define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C__SHIFT 0x0 |
7537 | #define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D_MASK 0xffffffff |
7538 | #define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D__SHIFT 0x0 |
7539 | #define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E_MASK 0xffffffff |
7540 | #define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E__SHIFT 0x0 |
7541 | #define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F_MASK 0xffffffff |
7542 | #define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F__SHIFT 0x0 |
7543 | #define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G_MASK 0xffffffff |
7544 | #define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G__SHIFT 0x0 |
7545 | #define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H_MASK 0xffffffff |
7546 | #define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H__SHIFT 0x0 |
7547 | #define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I_MASK 0xffffffff |
7548 | #define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I__SHIFT 0x0 |
7549 | #define DP_AUX2_DEBUG_J__DP_AUX2_DEBUG_J_MASK 0xffffffff |
7550 | #define DP_AUX2_DEBUG_J__DP_AUX2_DEBUG_J__SHIFT 0x0 |
7551 | #define DP_AUX2_DEBUG_K__DP_AUX2_DEBUG_K_MASK 0xffffffff |
7552 | #define DP_AUX2_DEBUG_K__DP_AUX2_DEBUG_K__SHIFT 0x0 |
7553 | #define DP_AUX2_DEBUG_L__DP_AUX2_DEBUG_L_MASK 0xffffffff |
7554 | #define DP_AUX2_DEBUG_L__DP_AUX2_DEBUG_L__SHIFT 0x0 |
7555 | #define DP_AUX2_DEBUG_M__DP_AUX2_DEBUG_M_MASK 0xffffffff |
7556 | #define DP_AUX2_DEBUG_M__DP_AUX2_DEBUG_M__SHIFT 0x0 |
7557 | #define DP_AUX2_DEBUG_N__DP_AUX2_DEBUG_N_MASK 0xffffffff |
7558 | #define DP_AUX2_DEBUG_N__DP_AUX2_DEBUG_N__SHIFT 0x0 |
7559 | #define DP_AUX2_DEBUG_O__DP_AUX2_DEBUG_O_MASK 0xffffffff |
7560 | #define DP_AUX2_DEBUG_O__DP_AUX2_DEBUG_O__SHIFT 0x0 |
7561 | #define DP_AUX2_DEBUG_P__DP_AUX2_DEBUG_P_MASK 0xffffffff |
7562 | #define DP_AUX2_DEBUG_P__DP_AUX2_DEBUG_P__SHIFT 0x0 |
7563 | #define DP_AUX2_DEBUG_Q__DP_AUX2_DEBUG_Q_MASK 0xffffffff |
7564 | #define DP_AUX2_DEBUG_Q__DP_AUX2_DEBUG_Q__SHIFT 0x0 |
7565 | #define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A_MASK 0xffffffff |
7566 | #define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A__SHIFT 0x0 |
7567 | #define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B_MASK 0xffffffff |
7568 | #define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B__SHIFT 0x0 |
7569 | #define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C_MASK 0xffffffff |
7570 | #define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C__SHIFT 0x0 |
7571 | #define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D_MASK 0xffffffff |
7572 | #define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D__SHIFT 0x0 |
7573 | #define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E_MASK 0xffffffff |
7574 | #define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E__SHIFT 0x0 |
7575 | #define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F_MASK 0xffffffff |
7576 | #define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F__SHIFT 0x0 |
7577 | #define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G_MASK 0xffffffff |
7578 | #define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G__SHIFT 0x0 |
7579 | #define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H_MASK 0xffffffff |
7580 | #define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H__SHIFT 0x0 |
7581 | #define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I_MASK 0xffffffff |
7582 | #define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I__SHIFT 0x0 |
7583 | #define DP_AUX3_DEBUG_J__DP_AUX3_DEBUG_J_MASK 0xffffffff |
7584 | #define DP_AUX3_DEBUG_J__DP_AUX3_DEBUG_J__SHIFT 0x0 |
7585 | #define DP_AUX3_DEBUG_K__DP_AUX3_DEBUG_K_MASK 0xffffffff |
7586 | #define DP_AUX3_DEBUG_K__DP_AUX3_DEBUG_K__SHIFT 0x0 |
7587 | #define DP_AUX3_DEBUG_L__DP_AUX3_DEBUG_L_MASK 0xffffffff |
7588 | #define DP_AUX3_DEBUG_L__DP_AUX3_DEBUG_L__SHIFT 0x0 |
7589 | #define DP_AUX3_DEBUG_M__DP_AUX3_DEBUG_M_MASK 0xffffffff |
7590 | #define DP_AUX3_DEBUG_M__DP_AUX3_DEBUG_M__SHIFT 0x0 |
7591 | #define DP_AUX3_DEBUG_N__DP_AUX3_DEBUG_N_MASK 0xffffffff |
7592 | #define DP_AUX3_DEBUG_N__DP_AUX3_DEBUG_N__SHIFT 0x0 |
7593 | #define DP_AUX3_DEBUG_O__DP_AUX3_DEBUG_O_MASK 0xffffffff |
7594 | #define DP_AUX3_DEBUG_O__DP_AUX3_DEBUG_O__SHIFT 0x0 |
7595 | #define DP_AUX3_DEBUG_P__DP_AUX3_DEBUG_P_MASK 0xffffffff |
7596 | #define DP_AUX3_DEBUG_P__DP_AUX3_DEBUG_P__SHIFT 0x0 |
7597 | #define DP_AUX3_DEBUG_Q__DP_AUX3_DEBUG_Q_MASK 0xffffffff |
7598 | #define DP_AUX3_DEBUG_Q__DP_AUX3_DEBUG_Q__SHIFT 0x0 |
7599 | #define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A_MASK 0xffffffff |
7600 | #define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A__SHIFT 0x0 |
7601 | #define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B_MASK 0xffffffff |
7602 | #define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B__SHIFT 0x0 |
7603 | #define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C_MASK 0xffffffff |
7604 | #define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C__SHIFT 0x0 |
7605 | #define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D_MASK 0xffffffff |
7606 | #define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D__SHIFT 0x0 |
7607 | #define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E_MASK 0xffffffff |
7608 | #define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E__SHIFT 0x0 |
7609 | #define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F_MASK 0xffffffff |
7610 | #define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F__SHIFT 0x0 |
7611 | #define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G_MASK 0xffffffff |
7612 | #define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G__SHIFT 0x0 |
7613 | #define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H_MASK 0xffffffff |
7614 | #define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H__SHIFT 0x0 |
7615 | #define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I_MASK 0xffffffff |
7616 | #define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I__SHIFT 0x0 |
7617 | #define DP_AUX4_DEBUG_J__DP_AUX4_DEBUG_J_MASK 0xffffffff |
7618 | #define DP_AUX4_DEBUG_J__DP_AUX4_DEBUG_J__SHIFT 0x0 |
7619 | #define DP_AUX4_DEBUG_K__DP_AUX4_DEBUG_K_MASK 0xffffffff |
7620 | #define DP_AUX4_DEBUG_K__DP_AUX4_DEBUG_K__SHIFT 0x0 |
7621 | #define DP_AUX4_DEBUG_L__DP_AUX4_DEBUG_L_MASK 0xffffffff |
7622 | #define DP_AUX4_DEBUG_L__DP_AUX4_DEBUG_L__SHIFT 0x0 |
7623 | #define DP_AUX4_DEBUG_M__DP_AUX4_DEBUG_M_MASK 0xffffffff |
7624 | #define DP_AUX4_DEBUG_M__DP_AUX4_DEBUG_M__SHIFT 0x0 |
7625 | #define DP_AUX4_DEBUG_N__DP_AUX4_DEBUG_N_MASK 0xffffffff |
7626 | #define DP_AUX4_DEBUG_N__DP_AUX4_DEBUG_N__SHIFT 0x0 |
7627 | #define DP_AUX4_DEBUG_O__DP_AUX4_DEBUG_O_MASK 0xffffffff |
7628 | #define DP_AUX4_DEBUG_O__DP_AUX4_DEBUG_O__SHIFT 0x0 |
7629 | #define DP_AUX4_DEBUG_P__DP_AUX4_DEBUG_P_MASK 0xffffffff |
7630 | #define DP_AUX4_DEBUG_P__DP_AUX4_DEBUG_P__SHIFT 0x0 |
7631 | #define DP_AUX4_DEBUG_Q__DP_AUX4_DEBUG_Q_MASK 0xffffffff |
7632 | #define DP_AUX4_DEBUG_Q__DP_AUX4_DEBUG_Q__SHIFT 0x0 |
7633 | #define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A_MASK 0xffffffff |
7634 | #define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A__SHIFT 0x0 |
7635 | #define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B_MASK 0xffffffff |
7636 | #define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B__SHIFT 0x0 |
7637 | #define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C_MASK 0xffffffff |
7638 | #define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C__SHIFT 0x0 |
7639 | #define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D_MASK 0xffffffff |
7640 | #define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D__SHIFT 0x0 |
7641 | #define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E_MASK 0xffffffff |
7642 | #define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E__SHIFT 0x0 |
7643 | #define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F_MASK 0xffffffff |
7644 | #define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F__SHIFT 0x0 |
7645 | #define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G_MASK 0xffffffff |
7646 | #define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G__SHIFT 0x0 |
7647 | #define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H_MASK 0xffffffff |
7648 | #define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H__SHIFT 0x0 |
7649 | #define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I_MASK 0xffffffff |
7650 | #define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I__SHIFT 0x0 |
7651 | #define DP_AUX5_DEBUG_J__DP_AUX5_DEBUG_J_MASK 0xffffffff |
7652 | #define DP_AUX5_DEBUG_J__DP_AUX5_DEBUG_J__SHIFT 0x0 |
7653 | #define DP_AUX5_DEBUG_K__DP_AUX5_DEBUG_K_MASK 0xffffffff |
7654 | #define DP_AUX5_DEBUG_K__DP_AUX5_DEBUG_K__SHIFT 0x0 |
7655 | #define DP_AUX5_DEBUG_L__DP_AUX5_DEBUG_L_MASK 0xffffffff |
7656 | #define DP_AUX5_DEBUG_L__DP_AUX5_DEBUG_L__SHIFT 0x0 |
7657 | #define DP_AUX5_DEBUG_M__DP_AUX5_DEBUG_M_MASK 0xffffffff |
7658 | #define DP_AUX5_DEBUG_M__DP_AUX5_DEBUG_M__SHIFT 0x0 |
7659 | #define DP_AUX5_DEBUG_N__DP_AUX5_DEBUG_N_MASK 0xffffffff |
7660 | #define DP_AUX5_DEBUG_N__DP_AUX5_DEBUG_N__SHIFT 0x0 |
7661 | #define DP_AUX5_DEBUG_O__DP_AUX5_DEBUG_O_MASK 0xffffffff |
7662 | #define DP_AUX5_DEBUG_O__DP_AUX5_DEBUG_O__SHIFT 0x0 |
7663 | #define DP_AUX5_DEBUG_P__DP_AUX5_DEBUG_P_MASK 0xffffffff |
7664 | #define DP_AUX5_DEBUG_P__DP_AUX5_DEBUG_P__SHIFT 0x0 |
7665 | #define DP_AUX5_DEBUG_Q__DP_AUX5_DEBUG_Q_MASK 0xffffffff |
7666 | #define DP_AUX5_DEBUG_Q__DP_AUX5_DEBUG_Q__SHIFT 0x0 |
7667 | #define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A_MASK 0xffffffff |
7668 | #define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A__SHIFT 0x0 |
7669 | #define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B_MASK 0xffffffff |
7670 | #define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B__SHIFT 0x0 |
7671 | #define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C_MASK 0xffffffff |
7672 | #define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C__SHIFT 0x0 |
7673 | #define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D_MASK 0xffffffff |
7674 | #define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D__SHIFT 0x0 |
7675 | #define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E_MASK 0xffffffff |
7676 | #define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E__SHIFT 0x0 |
7677 | #define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F_MASK 0xffffffff |
7678 | #define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F__SHIFT 0x0 |
7679 | #define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G_MASK 0xffffffff |
7680 | #define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G__SHIFT 0x0 |
7681 | #define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H_MASK 0xffffffff |
7682 | #define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H__SHIFT 0x0 |
7683 | #define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I_MASK 0xffffffff |
7684 | #define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I__SHIFT 0x0 |
7685 | #define DP_AUX6_DEBUG_J__DP_AUX6_DEBUG_J_MASK 0xffffffff |
7686 | #define DP_AUX6_DEBUG_J__DP_AUX6_DEBUG_J__SHIFT 0x0 |
7687 | #define DP_AUX6_DEBUG_K__DP_AUX6_DEBUG_K_MASK 0xffffffff |
7688 | #define DP_AUX6_DEBUG_K__DP_AUX6_DEBUG_K__SHIFT 0x0 |
7689 | #define DP_AUX6_DEBUG_L__DP_AUX6_DEBUG_L_MASK 0xffffffff |
7690 | #define DP_AUX6_DEBUG_L__DP_AUX6_DEBUG_L__SHIFT 0x0 |
7691 | #define DP_AUX6_DEBUG_M__DP_AUX6_DEBUG_M_MASK 0xffffffff |
7692 | #define DP_AUX6_DEBUG_M__DP_AUX6_DEBUG_M__SHIFT 0x0 |
7693 | #define DP_AUX6_DEBUG_N__DP_AUX6_DEBUG_N_MASK 0xffffffff |
7694 | #define DP_AUX6_DEBUG_N__DP_AUX6_DEBUG_N__SHIFT 0x0 |
7695 | #define DP_AUX6_DEBUG_O__DP_AUX6_DEBUG_O_MASK 0xffffffff |
7696 | #define DP_AUX6_DEBUG_O__DP_AUX6_DEBUG_O__SHIFT 0x0 |
7697 | #define DP_AUX6_DEBUG_P__DP_AUX6_DEBUG_P_MASK 0xffffffff |
7698 | #define DP_AUX6_DEBUG_P__DP_AUX6_DEBUG_P__SHIFT 0x0 |
7699 | #define DP_AUX6_DEBUG_Q__DP_AUX6_DEBUG_Q_MASK 0xffffffff |
7700 | #define DP_AUX6_DEBUG_Q__DP_AUX6_DEBUG_Q__SHIFT 0x0 |
7701 | #define DMCU_CTRL__RESET_UC_MASK 0x1 |
7702 | #define DMCU_CTRL__RESET_UC__SHIFT 0x0 |
7703 | #define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x2 |
7704 | #define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x1 |
7705 | #define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x4 |
7706 | #define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x2 |
7707 | #define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x8 |
7708 | #define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x3 |
7709 | #define DMCU_CTRL__DMCU_ENABLE_MASK 0x10 |
7710 | #define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x4 |
7711 | #define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffc00000 |
7712 | #define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x16 |
7713 | #define DMCU_STATUS__UC_IN_RESET_MASK 0x1 |
7714 | #define DMCU_STATUS__UC_IN_RESET__SHIFT 0x0 |
7715 | #define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x2 |
7716 | #define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x1 |
7717 | #define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x4 |
7718 | #define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x2 |
7719 | #define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0xff |
7720 | #define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x0 |
7721 | #define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0xff00 |
7722 | #define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x8 |
7723 | #define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0xff |
7724 | #define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x0 |
7725 | #define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0xff00 |
7726 | #define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x8 |
7727 | #define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0xff |
7728 | #define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x0 |
7729 | #define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0xff00 |
7730 | #define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x8 |
7731 | #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0xff |
7732 | #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x0 |
7733 | #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0xff00 |
7734 | #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x8 |
7735 | #define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffff |
7736 | #define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x0 |
7737 | #define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffff |
7738 | #define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x0 |
7739 | #define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x1 |
7740 | #define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x0 |
7741 | #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x2 |
7742 | #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x1 |
7743 | #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x4 |
7744 | #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x2 |
7745 | #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x8 |
7746 | #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x3 |
7747 | #define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x10 |
7748 | #define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x4 |
7749 | #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x20 |
7750 | #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x5 |
7751 | #define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0xff00 |
7752 | #define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x8 |
7753 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0xffff |
7754 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x0 |
7755 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0xf0000 |
7756 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x10 |
7757 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x100000 |
7758 | #define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x14 |
7759 | #define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffff |
7760 | #define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x0 |
7761 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0xffff |
7762 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x0 |
7763 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0xf0000 |
7764 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x10 |
7765 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x100000 |
7766 | #define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x14 |
7767 | #define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffff |
7768 | #define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x0 |
7769 | #define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x3ff |
7770 | #define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x0 |
7771 | #define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0xff |
7772 | #define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x0 |
7773 | #define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x3ff |
7774 | #define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x0 |
7775 | #define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0xff |
7776 | #define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x0 |
7777 | #define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x1 |
7778 | #define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x0 |
7779 | #define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x7f0000 |
7780 | #define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x10 |
7781 | #define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x800000 |
7782 | #define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x17 |
7783 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x1 |
7784 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x0 |
7785 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x2 |
7786 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x1 |
7787 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x4 |
7788 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x2 |
7789 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x8 |
7790 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x3 |
7791 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x10 |
7792 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x4 |
7793 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x20 |
7794 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x5 |
7795 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x40 |
7796 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x6 |
7797 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x80 |
7798 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x7 |
7799 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x100 |
7800 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x8 |
7801 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x200 |
7802 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x9 |
7803 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x400 |
7804 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0xa |
7805 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x800 |
7806 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0xb |
7807 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x1000 |
7808 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0xc |
7809 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x2000 |
7810 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0xd |
7811 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x4000 |
7812 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0xe |
7813 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x8000 |
7814 | #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0xf |
7815 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_TO_UC_EN_MASK 0x1 |
7816 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT 0x0 |
7817 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_TO_UC_EN_MASK 0x2 |
7818 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT 0x1 |
7819 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_TO_UC_EN_MASK 0x4 |
7820 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT 0x2 |
7821 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_TO_UC_EN_MASK 0x8 |
7822 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT 0x3 |
7823 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_TO_UC_EN_MASK 0x10 |
7824 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT 0x4 |
7825 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_TO_UC_EN_MASK 0x20 |
7826 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT 0x5 |
7827 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK 0x40 |
7828 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
7829 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK 0x80 |
7830 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
7831 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK 0x100 |
7832 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
7833 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK 0x200 |
7834 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT 0x9 |
7835 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK 0x400 |
7836 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT 0xa |
7837 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK 0x800 |
7838 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT 0xb |
7839 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK 0x2000 |
7840 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT 0xd |
7841 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK 0x4000 |
7842 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT 0xe |
7843 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK 0x4000 |
7844 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT 0xe |
7845 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK 0x8000 |
7846 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT 0xf |
7847 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK 0x10000 |
7848 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT 0x10 |
7849 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK 0x10000 |
7850 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT 0x10 |
7851 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK 0x20000 |
7852 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT 0x11 |
7853 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK 0x40000 |
7854 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT 0x12 |
7855 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK 0x40000 |
7856 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT 0x12 |
7857 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK 0x80000 |
7858 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT 0x13 |
7859 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK 0x100000 |
7860 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT 0x14 |
7861 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK 0x100000 |
7862 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT 0x14 |
7863 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK 0x200000 |
7864 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT 0x15 |
7865 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK 0x400000 |
7866 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT 0x16 |
7867 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK 0x400000 |
7868 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT 0x16 |
7869 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK 0x800000 |
7870 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT 0x17 |
7871 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK 0x1000000 |
7872 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT 0x18 |
7873 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK 0x1000000 |
7874 | #define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT 0x18 |
7875 | #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x1 |
7876 | #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x0 |
7877 | #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x1 |
7878 | #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x0 |
7879 | #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x2 |
7880 | #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x1 |
7881 | #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x2 |
7882 | #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x1 |
7883 | #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x4 |
7884 | #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x2 |
7885 | #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x4 |
7886 | #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x2 |
7887 | #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x8 |
7888 | #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x3 |
7889 | #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x100 |
7890 | #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x8 |
7891 | #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x100 |
7892 | #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x8 |
7893 | #define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x200 |
7894 | #define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x9 |
7895 | #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x400 |
7896 | #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0xa |
7897 | #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x400 |
7898 | #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0xa |
7899 | #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x800 |
7900 | #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0xb |
7901 | #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x800 |
7902 | #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0xb |
7903 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x1000 |
7904 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0xc |
7905 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x1000 |
7906 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0xc |
7907 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x2000 |
7908 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0xd |
7909 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x2000 |
7910 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0xd |
7911 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x4000 |
7912 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0xe |
7913 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x4000 |
7914 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0xe |
7915 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x8000 |
7916 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0xf |
7917 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x8000 |
7918 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0xf |
7919 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x10000 |
7920 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x10 |
7921 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x10000 |
7922 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x10 |
7923 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x20000 |
7924 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x11 |
7925 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x20000 |
7926 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x11 |
7927 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x40000 |
7928 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x12 |
7929 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x40000 |
7930 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x12 |
7931 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x80000 |
7932 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x13 |
7933 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x80000 |
7934 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x13 |
7935 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x100000 |
7936 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x14 |
7937 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x100000 |
7938 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x14 |
7939 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x200000 |
7940 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x15 |
7941 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x200000 |
7942 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x15 |
7943 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x400000 |
7944 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x16 |
7945 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x400000 |
7946 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x16 |
7947 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x800000 |
7948 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x17 |
7949 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x800000 |
7950 | #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x17 |
7951 | #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x1000000 |
7952 | #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x18 |
7953 | #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x1000000 |
7954 | #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x18 |
7955 | #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x2000000 |
7956 | #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x19 |
7957 | #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x2000000 |
7958 | #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x19 |
7959 | #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x4000000 |
7960 | #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x1a |
7961 | #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x4000000 |
7962 | #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x1a |
7963 | #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x8000000 |
7964 | #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x1b |
7965 | #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x8000000 |
7966 | #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x1b |
7967 | #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000 |
7968 | #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x1c |
7969 | #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000 |
7970 | #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x1c |
7971 | #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000 |
7972 | #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x1d |
7973 | #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000 |
7974 | #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x1d |
7975 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x1 |
7976 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x0 |
7977 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x2 |
7978 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x1 |
7979 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x4 |
7980 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x2 |
7981 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x200 |
7982 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x9 |
7983 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x400 |
7984 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0xa |
7985 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x800 |
7986 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0xb |
7987 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x1000 |
7988 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0xc |
7989 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x2000 |
7990 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0xd |
7991 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x4000 |
7992 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0xe |
7993 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x8000 |
7994 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0xf |
7995 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x10000 |
7996 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x10 |
7997 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x20000 |
7998 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x11 |
7999 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x40000 |
8000 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x12 |
8001 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x80000 |
8002 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x13 |
8003 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x100000 |
8004 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x14 |
8005 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x200000 |
8006 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x15 |
8007 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x400000 |
8008 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x16 |
8009 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x800000 |
8010 | #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x17 |
8011 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x1 |
8012 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x0 |
8013 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x2 |
8014 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x1 |
8015 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x4 |
8016 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x2 |
8017 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x8 |
8018 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x3 |
8019 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x100 |
8020 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x8 |
8021 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x1000 |
8022 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0xc |
8023 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x2000 |
8024 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0xd |
8025 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x4000 |
8026 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0xe |
8027 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x8000 |
8028 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0xf |
8029 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x10000 |
8030 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x10 |
8031 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x20000 |
8032 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x11 |
8033 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x40000 |
8034 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x12 |
8035 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x80000 |
8036 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x13 |
8037 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x100000 |
8038 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x14 |
8039 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x200000 |
8040 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x15 |
8041 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x400000 |
8042 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x16 |
8043 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x800000 |
8044 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x17 |
8045 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x1000000 |
8046 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x18 |
8047 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x2000000 |
8048 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x19 |
8049 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x4000000 |
8050 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x1a |
8051 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x8000000 |
8052 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x1b |
8053 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000 |
8054 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x1c |
8055 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000 |
8056 | #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x1d |
8057 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x1 |
8058 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
8059 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x2 |
8060 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
8061 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x4 |
8062 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
8063 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x8 |
8064 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
8065 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x100 |
8066 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
8067 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x1000 |
8068 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xc |
8069 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x2000 |
8070 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xd |
8071 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x4000 |
8072 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xe |
8073 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x8000 |
8074 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0xf |
8075 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x10000 |
8076 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x10 |
8077 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x20000 |
8078 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x11 |
8079 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x40000 |
8080 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x12 |
8081 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x80000 |
8082 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x13 |
8083 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x100000 |
8084 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x14 |
8085 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x200000 |
8086 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x15 |
8087 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x400000 |
8088 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x16 |
8089 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x800000 |
8090 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x17 |
8091 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x1000000 |
8092 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x18 |
8093 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x2000000 |
8094 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x19 |
8095 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x4000000 |
8096 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x1a |
8097 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x8000000 |
8098 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x1b |
8099 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000 |
8100 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x1c |
8101 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000 |
8102 | #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x1d |
8103 | #define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffff |
8104 | #define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x0 |
8105 | #define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0xff |
8106 | #define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x0 |
8107 | #define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0xff00 |
8108 | #define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x8 |
8109 | #define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0xff0000 |
8110 | #define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x10 |
8111 | #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x3 |
8112 | #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x0 |
8113 | #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0xc |
8114 | #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x2 |
8115 | #define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x7 |
8116 | #define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x0 |
8117 | #define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x700 |
8118 | #define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x8 |
8119 | #define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x10000 |
8120 | #define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x10 |
8121 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0xff |
8122 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x0 |
8123 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0xff00 |
8124 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x8 |
8125 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0xff0000 |
8126 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x10 |
8127 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000 |
8128 | #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x18 |
8129 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0xff |
8130 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x0 |
8131 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0xff00 |
8132 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x8 |
8133 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0xff0000 |
8134 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x10 |
8135 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000 |
8136 | #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x18 |
8137 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0xff |
8138 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x0 |
8139 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0xff00 |
8140 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x8 |
8141 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0xff0000 |
8142 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x10 |
8143 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000 |
8144 | #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x18 |
8145 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0xff |
8146 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x0 |
8147 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0xff00 |
8148 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x8 |
8149 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0xff0000 |
8150 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 |
8151 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000 |
8152 | #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x18 |
8153 | #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x1 |
8154 | #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x0 |
8155 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0xff |
8156 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x0 |
8157 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0xff00 |
8158 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x8 |
8159 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0xff0000 |
8160 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x10 |
8161 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000 |
8162 | #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x18 |
8163 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0xff |
8164 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x0 |
8165 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0xff00 |
8166 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x8 |
8167 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0xff0000 |
8168 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x10 |
8169 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000 |
8170 | #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x18 |
8171 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0xff |
8172 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x0 |
8173 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0xff00 |
8174 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x8 |
8175 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0xff0000 |
8176 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x10 |
8177 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000 |
8178 | #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x18 |
8179 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0xff |
8180 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x0 |
8181 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0xff00 |
8182 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x8 |
8183 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0xff0000 |
8184 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x10 |
8185 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000 |
8186 | #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x18 |
8187 | #define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x1 |
8188 | #define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x0 |
8189 | #define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x100 |
8190 | #define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x8 |
8191 | #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0xff |
8192 | #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x0 |
8193 | #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x100 |
8194 | #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
8195 | #define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffff |
8196 | #define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x0 |
8197 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 |
8198 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 |
8199 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 |
8200 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 |
8201 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 |
8202 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 |
8203 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 |
8204 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 |
8205 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 |
8206 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 |
8207 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 |
8208 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 |
8209 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 |
8210 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 |
8211 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 |
8212 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 |
8213 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 |
8214 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 |
8215 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 |
8216 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 |
8217 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 |
8218 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 |
8219 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 |
8220 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 |
8221 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 |
8222 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 |
8223 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 |
8224 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 |
8225 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 |
8226 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 |
8227 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 |
8228 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 |
8229 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 |
8230 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 |
8231 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 |
8232 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 |
8233 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 |
8234 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 |
8235 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 |
8236 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 |
8237 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 |
8238 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa |
8239 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 |
8240 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa |
8241 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 |
8242 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb |
8243 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 |
8244 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb |
8245 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 |
8246 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc |
8247 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 |
8248 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc |
8249 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 |
8250 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd |
8251 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 |
8252 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd |
8253 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 |
8254 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe |
8255 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 |
8256 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe |
8257 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 |
8258 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf |
8259 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 |
8260 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf |
8261 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 |
8262 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 |
8263 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 |
8264 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 |
8265 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 |
8266 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 |
8267 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 |
8268 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 |
8269 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 |
8270 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 |
8271 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 |
8272 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 |
8273 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 |
8274 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 |
8275 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 |
8276 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 |
8277 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 |
8278 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 |
8279 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 |
8280 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 |
8281 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 |
8282 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 |
8283 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 |
8284 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 |
8285 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 |
8286 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 |
8287 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 |
8288 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 |
8289 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 |
8290 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 |
8291 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 |
8292 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 |
8293 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 |
8294 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 |
8295 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 |
8296 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCI_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 |
8297 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 |
8298 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 |
8299 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 |
8300 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCO_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 |
8301 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 |
8302 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a |
8303 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 |
8304 | #define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a |
8305 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 |
8306 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 |
8307 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 |
8308 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 |
8309 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 |
8310 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 |
8311 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 |
8312 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 |
8313 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 |
8314 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 |
8315 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 |
8316 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 |
8317 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 |
8318 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 |
8319 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 |
8320 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 |
8321 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 |
8322 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 |
8323 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 |
8324 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 |
8325 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 |
8326 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 |
8327 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 |
8328 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 |
8329 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 |
8330 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 |
8331 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 |
8332 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 |
8333 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 |
8334 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 |
8335 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 |
8336 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 |
8337 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 |
8338 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 |
8339 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 |
8340 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 |
8341 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 |
8342 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 |
8343 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 |
8344 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 |
8345 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 |
8346 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa |
8347 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 |
8348 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa |
8349 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 |
8350 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb |
8351 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 |
8352 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb |
8353 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 |
8354 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc |
8355 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 |
8356 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc |
8357 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 |
8358 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd |
8359 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 |
8360 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd |
8361 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 |
8362 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe |
8363 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 |
8364 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe |
8365 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 |
8366 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf |
8367 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 |
8368 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf |
8369 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 |
8370 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 |
8371 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 |
8372 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 |
8373 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 |
8374 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 |
8375 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 |
8376 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 |
8377 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 |
8378 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 |
8379 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 |
8380 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 |
8381 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 |
8382 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 |
8383 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 |
8384 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 |
8385 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 |
8386 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 |
8387 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 |
8388 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 |
8389 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 |
8390 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 |
8391 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 |
8392 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 |
8393 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 |
8394 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 |
8395 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 |
8396 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 |
8397 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 |
8398 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 |
8399 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 |
8400 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 |
8401 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 |
8402 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 |
8403 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 |
8404 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 |
8405 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 |
8406 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 |
8407 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 |
8408 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 |
8409 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 |
8410 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a |
8411 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 |
8412 | #define DMCU_PERFMON_INTERRUPT_STATUS2__DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a |
8413 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 |
8414 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 |
8415 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 |
8416 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 |
8417 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 |
8418 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 |
8419 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 |
8420 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 |
8421 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 |
8422 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 |
8423 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 |
8424 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 |
8425 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 |
8426 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 |
8427 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 |
8428 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 |
8429 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 |
8430 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 |
8431 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 |
8432 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 |
8433 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 |
8434 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 |
8435 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 |
8436 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 |
8437 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 |
8438 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 |
8439 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 |
8440 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 |
8441 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 |
8442 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 |
8443 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 |
8444 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 |
8445 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x100 |
8446 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x8 |
8447 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR_MASK 0x100 |
8448 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x8 |
8449 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x200 |
8450 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x9 |
8451 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR_MASK 0x200 |
8452 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x9 |
8453 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x400 |
8454 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0xa |
8455 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR_MASK 0x400 |
8456 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0xa |
8457 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x800 |
8458 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0xb |
8459 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR_MASK 0x800 |
8460 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0xb |
8461 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x1000 |
8462 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0xc |
8463 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR_MASK 0x1000 |
8464 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0xc |
8465 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x2000 |
8466 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0xd |
8467 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR_MASK 0x2000 |
8468 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0xd |
8469 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x4000 |
8470 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0xe |
8471 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR_MASK 0x4000 |
8472 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0xe |
8473 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x8000 |
8474 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0xf |
8475 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR_MASK 0x8000 |
8476 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0xf |
8477 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x10000 |
8478 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x10 |
8479 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR_MASK 0x10000 |
8480 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x10 |
8481 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x20000 |
8482 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x11 |
8483 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR_MASK 0x20000 |
8484 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x11 |
8485 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x40000 |
8486 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x12 |
8487 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR_MASK 0x40000 |
8488 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x12 |
8489 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x80000 |
8490 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x13 |
8491 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR_MASK 0x80000 |
8492 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x13 |
8493 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x100000 |
8494 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x14 |
8495 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR_MASK 0x100000 |
8496 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x14 |
8497 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x200000 |
8498 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x15 |
8499 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR_MASK 0x200000 |
8500 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x15 |
8501 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x400000 |
8502 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x16 |
8503 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR_MASK 0x400000 |
8504 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x16 |
8505 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x800000 |
8506 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x17 |
8507 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR_MASK 0x800000 |
8508 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x17 |
8509 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 |
8510 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 |
8511 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 |
8512 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 |
8513 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x2000000 |
8514 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x19 |
8515 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x2000000 |
8516 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x19 |
8517 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x4000000 |
8518 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x1a |
8519 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x4000000 |
8520 | #define DMCU_PERFMON_INTERRUPT_STATUS3__DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x1a |
8521 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_OCCURRED_MASK 0x1 |
8522 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_OCCURRED__SHIFT 0x0 |
8523 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_CLEAR_MASK 0x1 |
8524 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER0_INT_CLEAR__SHIFT 0x0 |
8525 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_OCCURRED_MASK 0x2 |
8526 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_OCCURRED__SHIFT 0x1 |
8527 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_CLEAR_MASK 0x2 |
8528 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER1_INT_CLEAR__SHIFT 0x1 |
8529 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_OCCURRED_MASK 0x4 |
8530 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_OCCURRED__SHIFT 0x2 |
8531 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_CLEAR_MASK 0x4 |
8532 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER2_INT_CLEAR__SHIFT 0x2 |
8533 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_OCCURRED_MASK 0x8 |
8534 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_OCCURRED__SHIFT 0x3 |
8535 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_CLEAR_MASK 0x8 |
8536 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER3_INT_CLEAR__SHIFT 0x3 |
8537 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_OCCURRED_MASK 0x10 |
8538 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_OCCURRED__SHIFT 0x4 |
8539 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_CLEAR_MASK 0x10 |
8540 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER4_INT_CLEAR__SHIFT 0x4 |
8541 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_OCCURRED_MASK 0x20 |
8542 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_OCCURRED__SHIFT 0x5 |
8543 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_CLEAR_MASK 0x20 |
8544 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER5_INT_CLEAR__SHIFT 0x5 |
8545 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_OCCURRED_MASK 0x40 |
8546 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_OCCURRED__SHIFT 0x6 |
8547 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_CLEAR_MASK 0x40 |
8548 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER6_INT_CLEAR__SHIFT 0x6 |
8549 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_OCCURRED_MASK 0x80 |
8550 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_OCCURRED__SHIFT 0x7 |
8551 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_CLEAR_MASK 0x80 |
8552 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER7_INT_CLEAR__SHIFT 0x7 |
8553 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_OCCURRED_MASK 0x1000000 |
8554 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_OCCURRED__SHIFT 0x18 |
8555 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_CLEAR_MASK 0x1000000 |
8556 | #define DMCU_PERFMON_INTERRUPT_STATUS4__SCANIN_PERFMON_COUNTER_OFF_INT_CLEAR__SHIFT 0x18 |
8557 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 |
8558 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 |
8559 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 |
8560 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 |
8561 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 |
8562 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 |
8563 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 |
8564 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 |
8565 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 |
8566 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 |
8567 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 |
8568 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 |
8569 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 |
8570 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 |
8571 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 |
8572 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 |
8573 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 |
8574 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 |
8575 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 |
8576 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 |
8577 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 |
8578 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa |
8579 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 |
8580 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb |
8581 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 |
8582 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc |
8583 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 |
8584 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd |
8585 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 |
8586 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe |
8587 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 |
8588 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf |
8589 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 |
8590 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 |
8591 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 |
8592 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 |
8593 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 |
8594 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 |
8595 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 |
8596 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 |
8597 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 |
8598 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 |
8599 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 |
8600 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 |
8601 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 |
8602 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 |
8603 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 |
8604 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 |
8605 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 |
8606 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 |
8607 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 |
8608 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 |
8609 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 |
8610 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a |
8611 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 |
8612 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 |
8613 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 |
8614 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 |
8615 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 |
8616 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 |
8617 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 |
8618 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 |
8619 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 |
8620 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 |
8621 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 |
8622 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 |
8623 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 |
8624 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 |
8625 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 |
8626 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 |
8627 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 |
8628 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 |
8629 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 |
8630 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 |
8631 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 |
8632 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa |
8633 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 |
8634 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb |
8635 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 |
8636 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc |
8637 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 |
8638 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd |
8639 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 |
8640 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe |
8641 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 |
8642 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf |
8643 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 |
8644 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 |
8645 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 |
8646 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 |
8647 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 |
8648 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 |
8649 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 |
8650 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 |
8651 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 |
8652 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 |
8653 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 |
8654 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 |
8655 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 |
8656 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 |
8657 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 |
8658 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 |
8659 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 |
8660 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 |
8661 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 |
8662 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 |
8663 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 |
8664 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a |
8665 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 |
8666 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 |
8667 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 |
8668 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 |
8669 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 |
8670 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 |
8671 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 |
8672 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 |
8673 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 |
8674 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 |
8675 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 |
8676 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 |
8677 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 |
8678 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 |
8679 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 |
8680 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 |
8681 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x100 |
8682 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x8 |
8683 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x200 |
8684 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x9 |
8685 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x400 |
8686 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0xa |
8687 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x800 |
8688 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0xb |
8689 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x1000 |
8690 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0xc |
8691 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x2000 |
8692 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0xd |
8693 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x4000 |
8694 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0xe |
8695 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x8000 |
8696 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0xf |
8697 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x10000 |
8698 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x10 |
8699 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x20000 |
8700 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x11 |
8701 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x40000 |
8702 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x12 |
8703 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x80000 |
8704 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x13 |
8705 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x100000 |
8706 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x14 |
8707 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x200000 |
8708 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x15 |
8709 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x400000 |
8710 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x16 |
8711 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x800000 |
8712 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x17 |
8713 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 |
8714 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 |
8715 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x2000000 |
8716 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x19 |
8717 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x4000000 |
8718 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x1a |
8719 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_TO_UC_EN_MASK 0x1 |
8720 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_TO_UC_EN__SHIFT 0x0 |
8721 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_TO_UC_EN_MASK 0x2 |
8722 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_TO_UC_EN__SHIFT 0x1 |
8723 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_TO_UC_EN_MASK 0x4 |
8724 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_TO_UC_EN__SHIFT 0x2 |
8725 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_TO_UC_EN_MASK 0x8 |
8726 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_TO_UC_EN__SHIFT 0x3 |
8727 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_TO_UC_EN_MASK 0x10 |
8728 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_TO_UC_EN__SHIFT 0x4 |
8729 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_TO_UC_EN_MASK 0x20 |
8730 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_TO_UC_EN__SHIFT 0x5 |
8731 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_TO_UC_EN_MASK 0x40 |
8732 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_TO_UC_EN__SHIFT 0x6 |
8733 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_TO_UC_EN_MASK 0x80 |
8734 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_TO_UC_EN__SHIFT 0x7 |
8735 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_TO_UC_EN_MASK 0x1000000 |
8736 | #define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_TO_UC_EN__SHIFT 0x18 |
8737 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 |
8738 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
8739 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 |
8740 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
8741 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 |
8742 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
8743 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 |
8744 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
8745 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 |
8746 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
8747 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 |
8748 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
8749 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 |
8750 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
8751 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 |
8752 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
8753 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 |
8754 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
8755 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 |
8756 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 |
8757 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 |
8758 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa |
8759 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 |
8760 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb |
8761 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 |
8762 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc |
8763 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 |
8764 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd |
8765 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 |
8766 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe |
8767 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 |
8768 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf |
8769 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 |
8770 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 |
8771 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 |
8772 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 |
8773 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 |
8774 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 |
8775 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 |
8776 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 |
8777 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 |
8778 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 |
8779 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 |
8780 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 |
8781 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 |
8782 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 |
8783 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 |
8784 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 |
8785 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 |
8786 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 |
8787 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 |
8788 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 |
8789 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 |
8790 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a |
8791 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 |
8792 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
8793 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 |
8794 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
8795 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 |
8796 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
8797 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 |
8798 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
8799 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 |
8800 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
8801 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 |
8802 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
8803 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 |
8804 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
8805 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 |
8806 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
8807 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 |
8808 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
8809 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 |
8810 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 |
8811 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 |
8812 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa |
8813 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 |
8814 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb |
8815 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 |
8816 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc |
8817 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 |
8818 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd |
8819 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 |
8820 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe |
8821 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 |
8822 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf |
8823 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 |
8824 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 |
8825 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 |
8826 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 |
8827 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 |
8828 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 |
8829 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 |
8830 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 |
8831 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 |
8832 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 |
8833 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 |
8834 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 |
8835 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 |
8836 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 |
8837 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 |
8838 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 |
8839 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 |
8840 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 |
8841 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 |
8842 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 |
8843 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 |
8844 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a |
8845 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 |
8846 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
8847 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 |
8848 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
8849 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 |
8850 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
8851 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 |
8852 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
8853 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 |
8854 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
8855 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 |
8856 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
8857 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 |
8858 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
8859 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 |
8860 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
8861 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x100 |
8862 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x8 |
8863 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x200 |
8864 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x9 |
8865 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x400 |
8866 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0xa |
8867 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x800 |
8868 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0xb |
8869 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x1000 |
8870 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0xc |
8871 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x2000 |
8872 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0xd |
8873 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x4000 |
8874 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0xe |
8875 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x8000 |
8876 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0xf |
8877 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x10000 |
8878 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x10 |
8879 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x20000 |
8880 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x11 |
8881 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x40000 |
8882 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x12 |
8883 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x80000 |
8884 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x13 |
8885 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x100000 |
8886 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x14 |
8887 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x200000 |
8888 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x15 |
8889 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x400000 |
8890 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x16 |
8891 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x800000 |
8892 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x17 |
8893 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 |
8894 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 |
8895 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x2000000 |
8896 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x19 |
8897 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x4000000 |
8898 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x1a |
8899 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL_MASK 0x1 |
8900 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL__SHIFT 0x0 |
8901 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL_MASK 0x2 |
8902 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL__SHIFT 0x1 |
8903 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL_MASK 0x4 |
8904 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL__SHIFT 0x2 |
8905 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL_MASK 0x8 |
8906 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL__SHIFT 0x3 |
8907 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL_MASK 0x10 |
8908 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL__SHIFT 0x4 |
8909 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL_MASK 0x20 |
8910 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL__SHIFT 0x5 |
8911 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL_MASK 0x40 |
8912 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL__SHIFT 0x6 |
8913 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL_MASK 0x80 |
8914 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL__SHIFT 0x7 |
8915 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL_MASK 0x1000000 |
8916 | #define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__SCANIN_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL__SHIFT 0x18 |
8917 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK_MASK 0x1 |
8918 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 |
8919 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK_MASK 0x2 |
8920 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 |
8921 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK_MASK 0x4 |
8922 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 |
8923 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK_MASK 0x8 |
8924 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 |
8925 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK_MASK 0x10 |
8926 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 |
8927 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK_MASK 0x20 |
8928 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 |
8929 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK_MASK 0x40 |
8930 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 |
8931 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK_MASK 0x80 |
8932 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 |
8933 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK_MASK 0x100 |
8934 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 |
8935 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK_MASK 0x200 |
8936 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 |
8937 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK_MASK 0x400 |
8938 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa |
8939 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK_MASK 0x800 |
8940 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb |
8941 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 |
8942 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc |
8943 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 |
8944 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd |
8945 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 |
8946 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe |
8947 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 |
8948 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf |
8949 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 |
8950 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 |
8951 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 |
8952 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 |
8953 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 |
8954 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 |
8955 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 |
8956 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 |
8957 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 |
8958 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 |
8959 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 |
8960 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 |
8961 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 |
8962 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 |
8963 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 |
8964 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 |
8965 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 |
8966 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCI_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 |
8967 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 |
8968 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCO_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 |
8969 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 |
8970 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1__DCCG_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a |
8971 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK_MASK 0x1 |
8972 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 |
8973 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK_MASK 0x2 |
8974 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 |
8975 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK_MASK 0x4 |
8976 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 |
8977 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK_MASK 0x8 |
8978 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 |
8979 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK_MASK 0x10 |
8980 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 |
8981 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK_MASK 0x20 |
8982 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 |
8983 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK_MASK 0x40 |
8984 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 |
8985 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK_MASK 0x80 |
8986 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 |
8987 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK_MASK 0x100 |
8988 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 |
8989 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK_MASK 0x200 |
8990 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 |
8991 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK_MASK 0x400 |
8992 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa |
8993 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK_MASK 0x800 |
8994 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb |
8995 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 |
8996 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc |
8997 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 |
8998 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd |
8999 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 |
9000 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe |
9001 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 |
9002 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf |
9003 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 |
9004 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 |
9005 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 |
9006 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 |
9007 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 |
9008 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 |
9009 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 |
9010 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 |
9011 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 |
9012 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 |
9013 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 |
9014 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 |
9015 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 |
9016 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 |
9017 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 |
9018 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 |
9019 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 |
9020 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE0_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 |
9021 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 |
9022 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE1_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 |
9023 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 |
9024 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2__DCFE2_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a |
9025 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK_MASK 0x1 |
9026 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 |
9027 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK_MASK 0x2 |
9028 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 |
9029 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK_MASK 0x4 |
9030 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 |
9031 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK_MASK 0x8 |
9032 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 |
9033 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK_MASK 0x10 |
9034 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 |
9035 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK_MASK 0x20 |
9036 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 |
9037 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK_MASK 0x40 |
9038 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 |
9039 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK_MASK 0x80 |
9040 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 |
9041 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK_MASK 0x100 |
9042 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER0_INT_MASK__SHIFT 0x8 |
9043 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK_MASK 0x200 |
9044 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER1_INT_MASK__SHIFT 0x9 |
9045 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK_MASK 0x400 |
9046 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER2_INT_MASK__SHIFT 0xa |
9047 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK_MASK 0x800 |
9048 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER3_INT_MASK__SHIFT 0xb |
9049 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK_MASK 0x1000 |
9050 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER4_INT_MASK__SHIFT 0xc |
9051 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK_MASK 0x2000 |
9052 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER5_INT_MASK__SHIFT 0xd |
9053 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK_MASK 0x4000 |
9054 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER6_INT_MASK__SHIFT 0xe |
9055 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK_MASK 0x8000 |
9056 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER7_INT_MASK__SHIFT 0xf |
9057 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK_MASK 0x10000 |
9058 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER0_INT_MASK__SHIFT 0x10 |
9059 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK_MASK 0x20000 |
9060 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER1_INT_MASK__SHIFT 0x11 |
9061 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK_MASK 0x40000 |
9062 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER2_INT_MASK__SHIFT 0x12 |
9063 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK_MASK 0x80000 |
9064 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER3_INT_MASK__SHIFT 0x13 |
9065 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK_MASK 0x100000 |
9066 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER4_INT_MASK__SHIFT 0x14 |
9067 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK_MASK 0x200000 |
9068 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER5_INT_MASK__SHIFT 0x15 |
9069 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK_MASK 0x400000 |
9070 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER6_INT_MASK__SHIFT 0x16 |
9071 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK_MASK 0x800000 |
9072 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER7_INT_MASK__SHIFT 0x17 |
9073 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 |
9074 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE3_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 |
9075 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x2000000 |
9076 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE4_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x19 |
9077 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x4000000 |
9078 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3__DCFE5_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x1a |
9079 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_MASK_MASK 0x1 |
9080 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER0_INT_MASK__SHIFT 0x0 |
9081 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_MASK_MASK 0x2 |
9082 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER1_INT_MASK__SHIFT 0x1 |
9083 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_MASK_MASK 0x4 |
9084 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER2_INT_MASK__SHIFT 0x2 |
9085 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_MASK_MASK 0x8 |
9086 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER3_INT_MASK__SHIFT 0x3 |
9087 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_MASK_MASK 0x10 |
9088 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER4_INT_MASK__SHIFT 0x4 |
9089 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_MASK_MASK 0x20 |
9090 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER5_INT_MASK__SHIFT 0x5 |
9091 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_MASK_MASK 0x40 |
9092 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER6_INT_MASK__SHIFT 0x6 |
9093 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_MASK_MASK 0x80 |
9094 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER7_INT_MASK__SHIFT 0x7 |
9095 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_MASK_MASK 0x1000000 |
9096 | #define DMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4__SCANIN_PERFMON_COUNTER_OFF_INT_MASK__SHIFT 0x18 |
9097 | #define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x10 |
9098 | #define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 |
9099 | #define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x100 |
9100 | #define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 |
9101 | #define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x20000 |
9102 | #define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x11 |
9103 | #define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x7 |
9104 | #define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x0 |
9105 | #define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x100 |
9106 | #define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x8 |
9107 | #define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x10000 |
9108 | #define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x10 |
9109 | #define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x7000000 |
9110 | #define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x18 |
9111 | #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0xff |
9112 | #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x0 |
9113 | #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x100 |
9114 | #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x8 |
9115 | #define DP_CONFIG__DP_UDI_LANES_MASK 0x3 |
9116 | #define DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 |
9117 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x1 |
9118 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 |
9119 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x300 |
9120 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 |
9121 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x10000 |
9122 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 |
9123 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x100000 |
9124 | #define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 |
9125 | #define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x1 |
9126 | #define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x0 |
9127 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x10 |
9128 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 |
9129 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x20 |
9130 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 |
9131 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x40 |
9132 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 |
9133 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x80 |
9134 | #define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 |
9135 | #define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x100 |
9136 | #define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 |
9137 | #define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x1000 |
9138 | #define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0xc |
9139 | #define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x78 |
9140 | #define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x3 |
9141 | #define DP_MSA_MISC__DP_MSA_MISC2_MASK 0xff00 |
9142 | #define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 |
9143 | #define DP_MSA_MISC__DP_MSA_MISC3_MASK 0xff0000 |
9144 | #define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 |
9145 | #define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000 |
9146 | #define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 |
9147 | #define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x1 |
9148 | #define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x0 |
9149 | #define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x100 |
9150 | #define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 |
9151 | #define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000 |
9152 | #define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 |
9153 | #define DP_VID_N__DP_VID_N_MASK 0xffffff |
9154 | #define DP_VID_N__DP_VID_N__SHIFT 0x0 |
9155 | #define DP_VID_M__DP_VID_M_MASK 0xffffff |
9156 | #define DP_VID_M__DP_VID_M__SHIFT 0x0 |
9157 | #define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x3ffff |
9158 | #define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 |
9159 | #define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x1000000 |
9160 | #define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 |
9161 | #define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000 |
9162 | #define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c |
9163 | #define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x1 |
9164 | #define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 |
9165 | #define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0xfff |
9166 | #define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 |
9167 | #define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x10000 |
9168 | #define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x10 |
9169 | #define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x1000000 |
9170 | #define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 |
9171 | #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x1 |
9172 | #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 |
9173 | #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x2 |
9174 | #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 |
9175 | #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x4 |
9176 | #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 |
9177 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x1 |
9178 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 |
9179 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x2 |
9180 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 |
9181 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x4 |
9182 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 |
9183 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x8 |
9184 | #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 |
9185 | #define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x10000 |
9186 | #define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 |
9187 | #define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x1000000 |
9188 | #define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 |
9189 | #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x3 |
9190 | #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 |
9191 | #define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x3ff |
9192 | #define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 |
9193 | #define DP_DPHY_SYM0__DPHY_SYM2_MASK 0xffc00 |
9194 | #define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa |
9195 | #define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000 |
9196 | #define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 |
9197 | #define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x3ff |
9198 | #define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 |
9199 | #define DP_DPHY_SYM1__DPHY_SYM5_MASK 0xffc00 |
9200 | #define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa |
9201 | #define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000 |
9202 | #define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 |
9203 | #define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x3ff |
9204 | #define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 |
9205 | #define DP_DPHY_SYM2__DPHY_SYM8_MASK 0xffc00 |
9206 | #define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa |
9207 | #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x100 |
9208 | #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 |
9209 | #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x10000 |
9210 | #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 |
9211 | #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x1000000 |
9212 | #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 |
9213 | #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x1 |
9214 | #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 |
9215 | #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x30 |
9216 | #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 |
9217 | #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00 |
9218 | #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 |
9219 | #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x10 |
9220 | #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 |
9221 | #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x3ff00 |
9222 | #define DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 |
9223 | #define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x1 |
9224 | #define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x0 |
9225 | #define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x10 |
9226 | #define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x4 |
9227 | #define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x100 |
9228 | #define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x8 |
9229 | #define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x1 |
9230 | #define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x0 |
9231 | #define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x30 |
9232 | #define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x4 |
9233 | #define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0xff0000 |
9234 | #define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x10 |
9235 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0xff |
9236 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x0 |
9237 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0xff00 |
9238 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x8 |
9239 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0xff0000 |
9240 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x10 |
9241 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000 |
9242 | #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x18 |
9243 | #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x3f |
9244 | #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 |
9245 | #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x3f00 |
9246 | #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 |
9247 | #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x1 |
9248 | #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x0 |
9249 | #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x100 |
9250 | #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x8 |
9251 | #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x10000 |
9252 | #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 |
9253 | #define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x1 |
9254 | #define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 |
9255 | #define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x2 |
9256 | #define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 |
9257 | #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x4 |
9258 | #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 |
9259 | #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0xfff00 |
9260 | #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 |
9261 | #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000 |
9262 | #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 |
9263 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x7 |
9264 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 |
9265 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x10 |
9266 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 |
9267 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x100 |
9268 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 |
9269 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x1000 |
9270 | #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc |
9271 | #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x1 |
9272 | #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x0 |
9273 | #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x1fff0 |
9274 | #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x4 |
9275 | #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x1fff |
9276 | #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x0 |
9277 | #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x1fff0000 |
9278 | #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x10 |
9279 | #define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x1 |
9280 | #define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 |
9281 | #define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x10 |
9282 | #define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 |
9283 | #define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x100 |
9284 | #define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 |
9285 | #define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x1000 |
9286 | #define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc |
9287 | #define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x10000 |
9288 | #define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 |
9289 | #define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x100000 |
9290 | #define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 |
9291 | #define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x200000 |
9292 | #define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 |
9293 | #define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x400000 |
9294 | #define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 |
9295 | #define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x800000 |
9296 | #define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 |
9297 | #define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x1000000 |
9298 | #define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x18 |
9299 | #define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000 |
9300 | #define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x1c |
9301 | #define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x1 |
9302 | #define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 |
9303 | #define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0xfff |
9304 | #define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 |
9305 | #define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 |
9306 | #define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
9307 | #define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0xffff |
9308 | #define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 |
9309 | #define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000 |
9310 | #define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 |
9311 | #define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x3fff |
9312 | #define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 |
9313 | #define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000 |
9314 | #define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 |
9315 | #define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x100000 |
9316 | #define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 |
9317 | #define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x1000000 |
9318 | #define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 |
9319 | #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000 |
9320 | #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c |
9321 | #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000 |
9322 | #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d |
9323 | #define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0xffffff |
9324 | #define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 |
9325 | #define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0xffffff |
9326 | #define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 |
9327 | #define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0xffffff |
9328 | #define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 |
9329 | #define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0xffffff |
9330 | #define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 |
9331 | #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x1 |
9332 | #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 |
9333 | #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0xe |
9334 | #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x1 |
9335 | #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x10 |
9336 | #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 |
9337 | #define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x3f00 |
9338 | #define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x8 |
9339 | #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x10000 |
9340 | #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x10 |
9341 | #define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x3ffffff |
9342 | #define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 |
9343 | #define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000 |
9344 | #define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a |
9345 | #define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x1 |
9346 | #define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 |
9347 | #define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x7 |
9348 | #define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 |
9349 | #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x3f00 |
9350 | #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 |
9351 | #define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x70000 |
9352 | #define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 |
9353 | #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000 |
9354 | #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 |
9355 | #define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x7 |
9356 | #define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 |
9357 | #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x3f00 |
9358 | #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 |
9359 | #define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x70000 |
9360 | #define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 |
9361 | #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000 |
9362 | #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 |
9363 | #define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x7 |
9364 | #define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 |
9365 | #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x3f00 |
9366 | #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 |
9367 | #define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x70000 |
9368 | #define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 |
9369 | #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000 |
9370 | #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 |
9371 | #define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x3 |
9372 | #define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 |
9373 | #define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x100 |
9374 | #define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 |
9375 | #define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x3ff |
9376 | #define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 |
9377 | #define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x30000 |
9378 | #define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 |
9379 | #define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x1 |
9380 | #define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 |
9381 | #define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x10 |
9382 | #define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 |
9383 | #define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x100 |
9384 | #define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 |
9385 | #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0xff |
9386 | #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x0 |
9387 | #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x100 |
9388 | #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
9389 | #define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffff |
9390 | #define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x0 |
9391 | #define AUX_CONTROL__AUX_EN_MASK 0x1 |
9392 | #define AUX_CONTROL__AUX_EN__SHIFT 0x0 |
9393 | #define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x100 |
9394 | #define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 |
9395 | #define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x1000 |
9396 | #define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc |
9397 | #define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x10000 |
9398 | #define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 |
9399 | #define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x40000 |
9400 | #define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 |
9401 | #define AUX_CONTROL__AUX_HPD_SEL_MASK 0x700000 |
9402 | #define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 |
9403 | #define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x1000000 |
9404 | #define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 |
9405 | #define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000 |
9406 | #define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c |
9407 | #define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000 |
9408 | #define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x1d |
9409 | #define AUX_CONTROL__SPARE_0_MASK 0x40000000 |
9410 | #define AUX_CONTROL__SPARE_0__SHIFT 0x1e |
9411 | #define AUX_CONTROL__SPARE_1_MASK 0x80000000 |
9412 | #define AUX_CONTROL__SPARE_1__SHIFT 0x1f |
9413 | #define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x1 |
9414 | #define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 |
9415 | #define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x4 |
9416 | #define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 |
9417 | #define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0xf0 |
9418 | #define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 |
9419 | #define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x1f0000 |
9420 | #define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 |
9421 | #define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x3 |
9422 | #define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 |
9423 | #define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0xc |
9424 | #define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 |
9425 | #define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x100 |
9426 | #define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 |
9427 | #define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x400 |
9428 | #define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa |
9429 | #define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x10000 |
9430 | #define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 |
9431 | #define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x10000 |
9432 | #define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 |
9433 | #define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x20000 |
9434 | #define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 |
9435 | #define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x1000000 |
9436 | #define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 |
9437 | #define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x1000000 |
9438 | #define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 |
9439 | #define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x2000000 |
9440 | #define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 |
9441 | #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x1 |
9442 | #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 |
9443 | #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x2 |
9444 | #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 |
9445 | #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x4 |
9446 | #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 |
9447 | #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x10 |
9448 | #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 |
9449 | #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x20 |
9450 | #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 |
9451 | #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x40 |
9452 | #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 |
9453 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK 0x100 |
9454 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT 0x8 |
9455 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK 0x200 |
9456 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT 0x9 |
9457 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK 0x400 |
9458 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT 0xa |
9459 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK 0x1000 |
9460 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT 0xc |
9461 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK 0x2000 |
9462 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT 0xd |
9463 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK 0x4000 |
9464 | #define AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT 0xe |
9465 | #define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x1 |
9466 | #define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 |
9467 | #define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x2 |
9468 | #define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 |
9469 | #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x70 |
9470 | #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 |
9471 | #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x80 |
9472 | #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 |
9473 | #define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x100 |
9474 | #define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 |
9475 | #define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x200 |
9476 | #define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 |
9477 | #define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x400 |
9478 | #define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa |
9479 | #define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x800 |
9480 | #define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb |
9481 | #define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x1000 |
9482 | #define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc |
9483 | #define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x4000 |
9484 | #define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe |
9485 | #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x20000 |
9486 | #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 |
9487 | #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x40000 |
9488 | #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 |
9489 | #define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x80000 |
9490 | #define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 |
9491 | #define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x100000 |
9492 | #define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 |
9493 | #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x400000 |
9494 | #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 |
9495 | #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x800000 |
9496 | #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 |
9497 | #define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000 |
9498 | #define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 |
9499 | #define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000 |
9500 | #define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1e |
9501 | #define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x1 |
9502 | #define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 |
9503 | #define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x2 |
9504 | #define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 |
9505 | #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x70 |
9506 | #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 |
9507 | #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x80 |
9508 | #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 |
9509 | #define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x100 |
9510 | #define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 |
9511 | #define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x200 |
9512 | #define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 |
9513 | #define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x400 |
9514 | #define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa |
9515 | #define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x800 |
9516 | #define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb |
9517 | #define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x1000 |
9518 | #define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc |
9519 | #define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x4000 |
9520 | #define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe |
9521 | #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x20000 |
9522 | #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 |
9523 | #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x40000 |
9524 | #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 |
9525 | #define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x80000 |
9526 | #define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 |
9527 | #define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x100000 |
9528 | #define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 |
9529 | #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x400000 |
9530 | #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 |
9531 | #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x800000 |
9532 | #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 |
9533 | #define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000 |
9534 | #define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 |
9535 | #define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000 |
9536 | #define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d |
9537 | #define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000 |
9538 | #define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e |
9539 | #define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000 |
9540 | #define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f |
9541 | #define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x1 |
9542 | #define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 |
9543 | #define AUX_SW_DATA__AUX_SW_DATA_MASK 0xff00 |
9544 | #define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 |
9545 | #define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x1f0000 |
9546 | #define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 |
9547 | #define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000 |
9548 | #define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f |
9549 | #define AUX_LS_DATA__AUX_LS_DATA_MASK 0xff00 |
9550 | #define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 |
9551 | #define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x1f0000 |
9552 | #define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 |
9553 | #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x1 |
9554 | #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 |
9555 | #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x30 |
9556 | #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 |
9557 | #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x1ff0000 |
9558 | #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 |
9559 | #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x7 |
9560 | #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 |
9561 | #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x3f00 |
9562 | #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 |
9563 | #define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x70000 |
9564 | #define AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 |
9565 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x70 |
9566 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 |
9567 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x700 |
9568 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 |
9569 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x3000 |
9570 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc |
9571 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x10000 |
9572 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 |
9573 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x20000 |
9574 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 |
9575 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x40000 |
9576 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 |
9577 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x80000 |
9578 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 |
9579 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x300000 |
9580 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 |
9581 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x7000000 |
9582 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x18 |
9583 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000 |
9584 | #define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c |
9585 | #define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0xff |
9586 | #define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 |
9587 | #define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x1 |
9588 | #define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 |
9589 | #define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x70 |
9590 | #define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 |
9591 | #define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x1ff0000 |
9592 | #define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 |
9593 | #define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x7 |
9594 | #define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 |
9595 | #define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x1f00 |
9596 | #define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 |
9597 | #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x1f0000 |
9598 | #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 |
9599 | #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000 |
9600 | #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 |
9601 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x1 |
9602 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x0 |
9603 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK 0x10 |
9604 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT 0x4 |
9605 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK 0xf00 |
9606 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT 0x8 |
9607 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK 0xf000 |
9608 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT 0xc |
9609 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK 0x70000 |
9610 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT 0x10 |
9611 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK 0x100000 |
9612 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT 0x14 |
9613 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK 0xc00000 |
9614 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT 0x16 |
9615 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK 0x3000000 |
9616 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT 0x18 |
9617 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK 0xf0000000 |
9618 | #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT 0x1c |
9619 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK 0x1f |
9620 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT 0x0 |
9621 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK 0x1f00 |
9622 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT 0x8 |
9623 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK 0x30000 |
9624 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT 0x10 |
9625 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK 0x300000 |
9626 | #define AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT 0x14 |
9627 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK 0x1 |
9628 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT 0x0 |
9629 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK 0x10 |
9630 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT 0x4 |
9631 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK 0x100 |
9632 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT 0x8 |
9633 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK 0x1e00 |
9634 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT 0x9 |
9635 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK 0x10000 |
9636 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT 0x10 |
9637 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK 0x100000 |
9638 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT 0x14 |
9639 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK 0x200000 |
9640 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT 0x15 |
9641 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK 0x400000 |
9642 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT 0x16 |
9643 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK 0x800000 |
9644 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT 0x17 |
9645 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK 0x1000000 |
9646 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT 0x18 |
9647 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK 0x2000000 |
9648 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT 0x19 |
9649 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK 0xf0000000 |
9650 | #define AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT 0x1c |
9651 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK 0x1 |
9652 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT 0x0 |
9653 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK 0x2 |
9654 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT 0x1 |
9655 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK 0x70 |
9656 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT 0x4 |
9657 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK 0x80 |
9658 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT 0x7 |
9659 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK 0x100 |
9660 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT 0x8 |
9661 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK 0x200 |
9662 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT 0x9 |
9663 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK 0x400 |
9664 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT 0xa |
9665 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK 0x800 |
9666 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT 0xb |
9667 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK 0x1000 |
9668 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT 0xc |
9669 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK 0x4000 |
9670 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT 0xe |
9671 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK 0x20000 |
9672 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT 0x11 |
9673 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK 0x40000 |
9674 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT 0x12 |
9675 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK 0x80000 |
9676 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT 0x13 |
9677 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK 0x100000 |
9678 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT 0x14 |
9679 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK 0x400000 |
9680 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT 0x16 |
9681 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK 0x800000 |
9682 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT 0x17 |
9683 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK 0x1f000000 |
9684 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT 0x18 |
9685 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK 0x20000000 |
9686 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT 0x1d |
9687 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK 0x40000000 |
9688 | #define AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT 0x1e |
9689 | #define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW_MASK 0x1 |
9690 | #define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_RW__SHIFT 0x0 |
9691 | #define AUX_GTC_SYNC_DATA__AUX_GTC_DATA_MASK 0xff00 |
9692 | #define AUX_GTC_SYNC_DATA__AUX_GTC_DATA__SHIFT 0x8 |
9693 | #define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_MASK 0x3f0000 |
9694 | #define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX__SHIFT 0x10 |
9695 | #define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE_MASK 0x80000000 |
9696 | #define AUX_GTC_SYNC_DATA__AUX_GTC_INDEX_AUTOINCREMENT_DISABLE__SHIFT 0x1f |
9697 | #define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN_MASK 0x1 |
9698 | #define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN__SHIFT 0x0 |
9699 | #define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE_MASK 0xffff0 |
9700 | #define AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE__AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE__SHIFT 0x4 |
9701 | #define DVO_ENABLE__DVO_ENABLE_MASK 0x1 |
9702 | #define DVO_ENABLE__DVO_ENABLE__SHIFT 0x0 |
9703 | #define DVO_ENABLE__DVO_PIXEL_WIDTH_MASK 0x30 |
9704 | #define DVO_ENABLE__DVO_PIXEL_WIDTH__SHIFT 0x4 |
9705 | #define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x7 |
9706 | #define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x0 |
9707 | #define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x70000 |
9708 | #define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x10 |
9709 | #define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x3 |
9710 | #define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x0 |
9711 | #define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x100 |
9712 | #define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x8 |
9713 | #define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x1 |
9714 | #define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x0 |
9715 | #define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x2 |
9716 | #define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x1 |
9717 | #define DVO_CONTROL__DVO_DVPDATA_WIDTH_MASK 0x30 |
9718 | #define DVO_CONTROL__DVO_DVPDATA_WIDTH__SHIFT 0x4 |
9719 | #define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x100 |
9720 | #define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x8 |
9721 | #define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x10000 |
9722 | #define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x10 |
9723 | #define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x20000 |
9724 | #define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x11 |
9725 | #define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x40000 |
9726 | #define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x12 |
9727 | #define DVO_CONTROL__DVO_HSYNC_POLARITY_MASK 0x100000 |
9728 | #define DVO_CONTROL__DVO_HSYNC_POLARITY__SHIFT 0x14 |
9729 | #define DVO_CONTROL__DVO_VSYNC_POLARITY_MASK 0x200000 |
9730 | #define DVO_CONTROL__DVO_VSYNC_POLARITY__SHIFT 0x15 |
9731 | #define DVO_CONTROL__DVO_DE_POLARITY_MASK 0x400000 |
9732 | #define DVO_CONTROL__DVO_DE_POLARITY__SHIFT 0x16 |
9733 | #define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x3000000 |
9734 | #define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x18 |
9735 | #define DVO_CONTROL__DVO_CTL3_MASK 0x80000000 |
9736 | #define DVO_CONTROL__DVO_CTL3__SHIFT 0x1f |
9737 | #define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x10000 |
9738 | #define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x10 |
9739 | #define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x7ffffff |
9740 | #define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x0 |
9741 | #define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x7ffffff |
9742 | #define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x0 |
9743 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x1 |
9744 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x0 |
9745 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x2 |
9746 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 |
9747 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0xfc |
9748 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 |
9749 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x100 |
9750 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x8 |
9751 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0xfc00 |
9752 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa |
9753 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0xf0000 |
9754 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 |
9755 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x3c00000 |
9756 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x16 |
9757 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000 |
9758 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x1d |
9759 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000 |
9760 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e |
9761 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000 |
9762 | #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f |
9763 | #define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x1 |
9764 | #define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x0 |
9765 | #define FBC_CNTL__FBC_SRC_SEL_MASK 0xe |
9766 | #define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x1 |
9767 | #define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x30000 |
9768 | #define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x10 |
9769 | #define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x2000000 |
9770 | #define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x19 |
9771 | #define FBC_CNTL__FBC_EN_MASK 0x80000000 |
9772 | #define FBC_CNTL__FBC_EN__SHIFT 0x1f |
9773 | #define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffff |
9774 | #define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x0 |
9775 | #define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffff |
9776 | #define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x0 |
9777 | #define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x1f |
9778 | #define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x0 |
9779 | #define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x80 |
9780 | #define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x7 |
9781 | #define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x1f00 |
9782 | #define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x8 |
9783 | #define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0xf |
9784 | #define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x0 |
9785 | #define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x10000 |
9786 | #define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x10 |
9787 | #define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x20000 |
9788 | #define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x11 |
9789 | #define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x40000 |
9790 | #define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x12 |
9791 | #define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x80000 |
9792 | #define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x13 |
9793 | #define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x100000 |
9794 | #define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x14 |
9795 | #define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x1 |
9796 | #define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x0 |
9797 | #define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x100 |
9798 | #define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x8 |
9799 | #define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x200 |
9800 | #define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x9 |
9801 | #define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x400 |
9802 | #define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0xa |
9803 | #define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x800 |
9804 | #define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0xb |
9805 | #define FBC_COMP_MODE__FBC_IND_EN_MASK 0x10000 |
9806 | #define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x10 |
9807 | #define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0xff |
9808 | #define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x0 |
9809 | #define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0xff00 |
9810 | #define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x8 |
9811 | #define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x10000 |
9812 | #define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x10 |
9813 | #define FBC_DEBUG0__FBC_DEBUG0_MASK 0xfe0000 |
9814 | #define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x11 |
9815 | #define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000 |
9816 | #define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x18 |
9817 | #define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffff |
9818 | #define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x0 |
9819 | #define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffff |
9820 | #define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x0 |
9821 | #define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0xffffff |
9822 | #define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x0 |
9823 | #define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0xffffff |
9824 | #define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x0 |
9825 | #define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0xffffff |
9826 | #define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x0 |
9827 | #define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0xffffff |
9828 | #define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x0 |
9829 | #define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0xffffff |
9830 | #define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x0 |
9831 | #define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0xffffff |
9832 | #define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x0 |
9833 | #define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0xffffff |
9834 | #define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x0 |
9835 | #define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0xffffff |
9836 | #define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x0 |
9837 | #define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0xffffff |
9838 | #define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x0 |
9839 | #define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0xffffff |
9840 | #define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x0 |
9841 | #define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0xffffff |
9842 | #define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x0 |
9843 | #define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0xffffff |
9844 | #define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x0 |
9845 | #define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0xffffff |
9846 | #define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x0 |
9847 | #define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0xffffff |
9848 | #define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x0 |
9849 | #define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0xffffff |
9850 | #define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x0 |
9851 | #define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0xffffff |
9852 | #define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x0 |
9853 | #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x3ff |
9854 | #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x0 |
9855 | #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x3ff0000 |
9856 | #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x10 |
9857 | #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x3ff |
9858 | #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x0 |
9859 | #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x3ff0000 |
9860 | #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x10 |
9861 | #define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0xf0000 |
9862 | #define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x10 |
9863 | #define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x3 |
9864 | #define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x0 |
9865 | #define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x8 |
9866 | #define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x3 |
9867 | #define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0xf0 |
9868 | #define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x4 |
9869 | #define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x300 |
9870 | #define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x8 |
9871 | #define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x400 |
9872 | #define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0xa |
9873 | #define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x800 |
9874 | #define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0xb |
9875 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x3ff |
9876 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x0 |
9877 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x10000 |
9878 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x10 |
9879 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x20000 |
9880 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x11 |
9881 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000 |
9882 | #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x1f |
9883 | #define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffff |
9884 | #define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x0 |
9885 | #define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffff |
9886 | #define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x0 |
9887 | #define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0xff |
9888 | #define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x0 |
9889 | #define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0xff |
9890 | #define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x0 |
9891 | #define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x3 |
9892 | #define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x0 |
9893 | #define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x4 |
9894 | #define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x2 |
9895 | #define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x8 |
9896 | #define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x3 |
9897 | #define FBC_MISC__FBC_ERROR_PIXEL_MASK 0xf0 |
9898 | #define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x4 |
9899 | #define FBC_MISC__FBC_DIVIDE_X_MASK 0x300 |
9900 | #define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x8 |
9901 | #define FBC_MISC__FBC_DIVIDE_Y_MASK 0x400 |
9902 | #define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0xa |
9903 | #define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x800 |
9904 | #define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0xb |
9905 | #define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x1000 |
9906 | #define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0xc |
9907 | #define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x10000 |
9908 | #define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x10 |
9909 | #define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x100000 |
9910 | #define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x14 |
9911 | #define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x200000 |
9912 | #define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x15 |
9913 | #define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0xf0000000 |
9914 | #define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x1c |
9915 | #define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x1 |
9916 | #define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x0 |
9917 | #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0xff |
9918 | #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x0 |
9919 | #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x100 |
9920 | #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
9921 | #define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffff |
9922 | #define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x0 |
9923 | #define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0xffff |
9924 | #define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 |
9925 | #define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xffff0000 |
9926 | #define FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 |
9927 | #define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0xffff |
9928 | #define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 |
9929 | #define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xffff0000 |
9930 | #define FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 |
9931 | #define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0xffff |
9932 | #define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 |
9933 | #define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xffff0000 |
9934 | #define FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 |
9935 | #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x1 |
9936 | #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 |
9937 | #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x10 |
9938 | #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 |
9939 | #define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x1 |
9940 | #define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 |
9941 | #define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x10 |
9942 | #define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x4 |
9943 | #define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x10000 |
9944 | #define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 |
9945 | #define FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x20000 |
9946 | #define FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x11 |
9947 | #define FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x40000 |
9948 | #define FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x12 |
9949 | #define FMT_CONTROL__FMT_SRC_SELECT_MASK 0x7000000 |
9950 | #define FMT_CONTROL__FMT_SRC_SELECT__SHIFT 0x18 |
9951 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x1 |
9952 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x0 |
9953 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x700 |
9954 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x8 |
9955 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0xf000 |
9956 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0xc |
9957 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x10000 |
9958 | #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x10 |
9959 | #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0xffff |
9960 | #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x0 |
9961 | #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000 |
9962 | #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x10 |
9963 | #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0xffff |
9964 | #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x0 |
9965 | #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000 |
9966 | #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x10 |
9967 | #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x1 |
9968 | #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 |
9969 | #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x2 |
9970 | #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 |
9971 | #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x30 |
9972 | #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 |
9973 | #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x100 |
9974 | #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 |
9975 | #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x600 |
9976 | #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 |
9977 | #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x1800 |
9978 | #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb |
9979 | #define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x2000 |
9980 | #define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd |
9981 | #define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x4000 |
9982 | #define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe |
9983 | #define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x8000 |
9984 | #define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf |
9985 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x10000 |
9986 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 |
9987 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x60000 |
9988 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 |
9989 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x600000 |
9990 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 |
9991 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x1000000 |
9992 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 |
9993 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x2000000 |
9994 | #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 |
9995 | #define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0xc000000 |
9996 | #define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a |
9997 | #define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000 |
9998 | #define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c |
9999 | #define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000 |
10000 | #define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e |
10001 | #define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0xff |
10002 | #define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 |
10003 | #define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xffff0000 |
10004 | #define FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 |
10005 | #define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0xff |
10006 | #define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 |
10007 | #define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xffff0000 |
10008 | #define FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 |
10009 | #define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0xff |
10010 | #define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 |
10011 | #define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xffff0000 |
10012 | #define FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 |
10013 | #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x1 |
10014 | #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x0 |
10015 | #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x10 |
10016 | #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x4 |
10017 | #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffff |
10018 | #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x0 |
10019 | #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffff |
10020 | #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x0 |
10021 | #define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x1 |
10022 | #define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 |
10023 | #define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x70000 |
10024 | #define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 |
10025 | #define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x1 |
10026 | #define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x0 |
10027 | #define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN_MASK 0x2 |
10028 | #define FMT_CRC_CNTL__FMT_DTMTEST_CRC_EN__SHIFT 0x1 |
10029 | #define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x10 |
10030 | #define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x4 |
10031 | #define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb_MASK 0x100 |
10032 | #define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb__SHIFT 0x8 |
10033 | #define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x3000 |
10034 | #define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0xc |
10035 | #define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x10000 |
10036 | #define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x10 |
10037 | #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x100000 |
10038 | #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x14 |
10039 | #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x1000000 |
10040 | #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x18 |
10041 | #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0xffff |
10042 | #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x0 |
10043 | #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000 |
10044 | #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x10 |
10045 | #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0xffff |
10046 | #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x0 |
10047 | #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000 |
10048 | #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x10 |
10049 | #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0xffff |
10050 | #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x0 |
10051 | #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000 |
10052 | #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x10 |
10053 | #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0xffff |
10054 | #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x0 |
10055 | #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000 |
10056 | #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x10 |
10057 | #define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x3 |
10058 | #define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x0 |
10059 | #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0xff |
10060 | #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x0 |
10061 | #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x100 |
10062 | #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
10063 | #define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffff |
10064 | #define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x0 |
10065 | #define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffff |
10066 | #define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x0 |
10067 | #define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffff |
10068 | #define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x0 |
10069 | #define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffff |
10070 | #define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x0 |
10071 | #define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffff |
10072 | #define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x0 |
10073 | #define LB_DATA_FORMAT__PIXEL_DEPTH_MASK 0x3 |
10074 | #define LB_DATA_FORMAT__PIXEL_DEPTH__SHIFT 0x0 |
10075 | #define LB_DATA_FORMAT__PIXEL_EXPAN_MODE_MASK 0x4 |
10076 | #define LB_DATA_FORMAT__PIXEL_EXPAN_MODE__SHIFT 0x2 |
10077 | #define LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x8 |
10078 | #define LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x3 |
10079 | #define LB_DATA_FORMAT__PREFETCH_MASK 0x1000 |
10080 | #define LB_DATA_FORMAT__PREFETCH__SHIFT 0xc |
10081 | #define LB_DATA_FORMAT__REQUEST_MODE_MASK 0x1000000 |
10082 | #define LB_DATA_FORMAT__REQUEST_MODE__SHIFT 0x18 |
10083 | #define LB_DATA_FORMAT__ALPHA_EN_MASK 0x80000000 |
10084 | #define LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x1f |
10085 | #define LB_MEMORY_CTRL__LB_MEMORY_SIZE_MASK 0xfff |
10086 | #define LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT 0x0 |
10087 | #define LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0xf0000 |
10088 | #define LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 |
10089 | #define LB_MEMORY_CTRL__LB_MEMORY_CONFIG_MASK 0x300000 |
10090 | #define LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT 0x14 |
10091 | #define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS_MASK 0xfff |
10092 | #define LB_MEMORY_SIZE_STATUS__LB_MEMORY_SIZE_STATUS__SHIFT 0x0 |
10093 | #define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT_MASK 0x7fff |
10094 | #define LB_DESKTOP_HEIGHT__DESKTOP_HEIGHT__SHIFT 0x0 |
10095 | #define LB_VLINE_START_END__VLINE_START_MASK 0x3fff |
10096 | #define LB_VLINE_START_END__VLINE_START__SHIFT 0x0 |
10097 | #define LB_VLINE_START_END__VLINE_END_MASK 0x7fff0000 |
10098 | #define LB_VLINE_START_END__VLINE_END__SHIFT 0x10 |
10099 | #define LB_VLINE_START_END__VLINE_INV_MASK 0x80000000 |
10100 | #define LB_VLINE_START_END__VLINE_INV__SHIFT 0x1f |
10101 | #define LB_VLINE2_START_END__VLINE2_START_MASK 0x3fff |
10102 | #define LB_VLINE2_START_END__VLINE2_START__SHIFT 0x0 |
10103 | #define LB_VLINE2_START_END__VLINE2_END_MASK 0x7fff0000 |
10104 | #define LB_VLINE2_START_END__VLINE2_END__SHIFT 0x10 |
10105 | #define LB_VLINE2_START_END__VLINE2_INV_MASK 0x80000000 |
10106 | #define LB_VLINE2_START_END__VLINE2_INV__SHIFT 0x1f |
10107 | #define LB_V_COUNTER__V_COUNTER_MASK 0x7fff |
10108 | #define LB_V_COUNTER__V_COUNTER__SHIFT 0x0 |
10109 | #define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER_MASK 0x7fff |
10110 | #define LB_SNAPSHOT_V_COUNTER__SNAPSHOT_V_COUNTER__SHIFT 0x0 |
10111 | #define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK 0x1 |
10112 | #define LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK__SHIFT 0x0 |
10113 | #define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK 0x10 |
10114 | #define LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK__SHIFT 0x4 |
10115 | #define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK_MASK 0x100 |
10116 | #define LB_INTERRUPT_MASK__VLINE2_INTERRUPT_MASK__SHIFT 0x8 |
10117 | #define LB_VLINE_STATUS__VLINE_OCCURRED_MASK 0x1 |
10118 | #define LB_VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x0 |
10119 | #define LB_VLINE_STATUS__VLINE_ACK_MASK 0x10 |
10120 | #define LB_VLINE_STATUS__VLINE_ACK__SHIFT 0x4 |
10121 | #define LB_VLINE_STATUS__VLINE_STAT_MASK 0x1000 |
10122 | #define LB_VLINE_STATUS__VLINE_STAT__SHIFT 0xc |
10123 | #define LB_VLINE_STATUS__VLINE_INTERRUPT_MASK 0x10000 |
10124 | #define LB_VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x10 |
10125 | #define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x20000 |
10126 | #define LB_VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x11 |
10127 | #define LB_VLINE2_STATUS__VLINE2_OCCURRED_MASK 0x1 |
10128 | #define LB_VLINE2_STATUS__VLINE2_OCCURRED__SHIFT 0x0 |
10129 | #define LB_VLINE2_STATUS__VLINE2_ACK_MASK 0x10 |
10130 | #define LB_VLINE2_STATUS__VLINE2_ACK__SHIFT 0x4 |
10131 | #define LB_VLINE2_STATUS__VLINE2_STAT_MASK 0x1000 |
10132 | #define LB_VLINE2_STATUS__VLINE2_STAT__SHIFT 0xc |
10133 | #define LB_VLINE2_STATUS__VLINE2_INTERRUPT_MASK 0x10000 |
10134 | #define LB_VLINE2_STATUS__VLINE2_INTERRUPT__SHIFT 0x10 |
10135 | #define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE_MASK 0x20000 |
10136 | #define LB_VLINE2_STATUS__VLINE2_INTERRUPT_TYPE__SHIFT 0x11 |
10137 | #define LB_VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x1 |
10138 | #define LB_VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x0 |
10139 | #define LB_VBLANK_STATUS__VBLANK_ACK_MASK 0x10 |
10140 | #define LB_VBLANK_STATUS__VBLANK_ACK__SHIFT 0x4 |
10141 | #define LB_VBLANK_STATUS__VBLANK_STAT_MASK 0x1000 |
10142 | #define LB_VBLANK_STATUS__VBLANK_STAT__SHIFT 0xc |
10143 | #define LB_VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x10000 |
10144 | #define LB_VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x10 |
10145 | #define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x20000 |
10146 | #define LB_VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x11 |
10147 | #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x3 |
10148 | #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x0 |
10149 | #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x10 |
10150 | #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x4 |
10151 | #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY_MASK 0xff00 |
10152 | #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_DELAY__SHIFT 0x8 |
10153 | #define LB_SYNC_RESET_SEL__LB_SYNC_DURATION_MASK 0xc00000 |
10154 | #define LB_SYNC_RESET_SEL__LB_SYNC_DURATION__SHIFT 0x16 |
10155 | #define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR_MASK 0xfff0 |
10156 | #define LB_BLACK_KEYER_R_CR__LB_BLACK_KEYER_R_CR__SHIFT 0x4 |
10157 | #define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y_MASK 0xfff0 |
10158 | #define LB_BLACK_KEYER_G_Y__LB_BLACK_KEYER_G_Y__SHIFT 0x4 |
10159 | #define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB_MASK 0xfff0 |
10160 | #define LB_BLACK_KEYER_B_CB__LB_BLACK_KEYER_B_CB__SHIFT 0x4 |
10161 | #define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN_MASK 0x1 |
10162 | #define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_EN__SHIFT 0x0 |
10163 | #define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN_MASK 0x100 |
10164 | #define LB_KEYER_COLOR_CTRL__LB_KEYER_COLOR_REP_EN__SHIFT 0x8 |
10165 | #define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR_MASK 0xfff0 |
10166 | #define LB_KEYER_COLOR_R_CR__LB_KEYER_COLOR_R_CR__SHIFT 0x4 |
10167 | #define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y_MASK 0xfff0 |
10168 | #define LB_KEYER_COLOR_G_Y__LB_KEYER_COLOR_G_Y__SHIFT 0x4 |
10169 | #define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB_MASK 0xfff0 |
10170 | #define LB_KEYER_COLOR_B_CB__LB_KEYER_COLOR_B_CB__SHIFT 0x4 |
10171 | #define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR_MASK 0xfff0 |
10172 | #define LB_KEYER_COLOR_REP_R_CR__LB_KEYER_COLOR_REP_R_CR__SHIFT 0x4 |
10173 | #define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y_MASK 0xfff0 |
10174 | #define LB_KEYER_COLOR_REP_G_Y__LB_KEYER_COLOR_REP_G_Y__SHIFT 0x4 |
10175 | #define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB_MASK 0xfff0 |
10176 | #define LB_KEYER_COLOR_REP_B_CB__LB_KEYER_COLOR_REP_B_CB__SHIFT 0x4 |
10177 | #define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL_MASK 0x3f |
10178 | #define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_LEVEL__SHIFT 0x0 |
10179 | #define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL_MASK 0xfc00 |
10180 | #define LB_BUFFER_LEVEL_STATUS__REQ_FIFO_FULL_CNTL__SHIFT 0xa |
10181 | #define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL_MASK 0xfff0000 |
10182 | #define LB_BUFFER_LEVEL_STATUS__DATA_BUFFER_LEVEL__SHIFT 0x10 |
10183 | #define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL_MASK 0xf0000000 |
10184 | #define LB_BUFFER_LEVEL_STATUS__DATA_FIFO_FULL_CNTL__SHIFT 0x1c |
10185 | #define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON_MASK 0xfff |
10186 | #define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_ON__SHIFT 0x0 |
10187 | #define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF_MASK 0xfff0000 |
10188 | #define LB_BUFFER_URGENCY_CTRL__LB_BUFFER_URGENCY_MARK_OFF__SHIFT 0x10 |
10189 | #define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL_MASK 0xfff |
10190 | #define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_LEVEL__SHIFT 0x0 |
10191 | #define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT_MASK 0x10000 |
10192 | #define LB_BUFFER_URGENCY_STATUS__LB_BUFFER_URGENCY_STAT__SHIFT 0x10 |
10193 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN_MASK 0xf |
10194 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_MARGIN__SHIFT 0x0 |
10195 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT_MASK 0x10 |
10196 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_STAT__SHIFT 0x4 |
10197 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED_MASK 0x100 |
10198 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_OCCURRED__SHIFT 0x8 |
10199 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK_MASK 0x1000 |
10200 | #define LB_BUFFER_STATUS__LB_BUFFER_EMPTY_ACK__SHIFT 0xc |
10201 | #define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT_MASK 0x10000 |
10202 | #define LB_BUFFER_STATUS__LB_BUFFER_FULL_STAT__SHIFT 0x10 |
10203 | #define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED_MASK 0x100000 |
10204 | #define LB_BUFFER_STATUS__LB_BUFFER_FULL_OCCURRED__SHIFT 0x14 |
10205 | #define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK_MASK 0x1000000 |
10206 | #define LB_BUFFER_STATUS__LB_BUFFER_FULL_ACK__SHIFT 0x18 |
10207 | #define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x1 |
10208 | #define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x0 |
10209 | #define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x3 |
10210 | #define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x0 |
10211 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0xf |
10212 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x0 |
10213 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x10 |
10214 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x4 |
10215 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x100 |
10216 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x8 |
10217 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x1000 |
10218 | #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0xc |
10219 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x3 |
10220 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x0 |
10221 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x7fff00 |
10222 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x8 |
10223 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000 |
10224 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x18 |
10225 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000 |
10226 | #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x1e |
10227 | #define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x3 |
10228 | #define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x0 |
10229 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x100 |
10230 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x8 |
10231 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x1000 |
10232 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0xc |
10233 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x10000 |
10234 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x10 |
10235 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x100000 |
10236 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x14 |
10237 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000 |
10238 | #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x1c |
10239 | #define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000 |
10240 | #define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x1f |
10241 | #define LB_DEBUG__LB_DEBUG_MASK 0xffffffff |
10242 | #define LB_DEBUG__LB_DEBUG__SHIFT 0x0 |
10243 | #define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffff |
10244 | #define LB_DEBUG2__LB_DEBUG2__SHIFT 0x0 |
10245 | #define LB_DEBUG3__LB_DEBUG3_MASK 0xffffffff |
10246 | #define LB_DEBUG3__LB_DEBUG3__SHIFT 0x0 |
10247 | #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0xff |
10248 | #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x0 |
10249 | #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x100 |
10250 | #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
10251 | #define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffff |
10252 | #define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x0 |
10253 | #define MVP_CONTROL1__MVP_EN_MASK 0x1 |
10254 | #define MVP_CONTROL1__MVP_EN__SHIFT 0x0 |
10255 | #define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x70 |
10256 | #define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x4 |
10257 | #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x100 |
10258 | #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x8 |
10259 | #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x200 |
10260 | #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x9 |
10261 | #define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x400 |
10262 | #define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0xa |
10263 | #define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x1000 |
10264 | #define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0xc |
10265 | #define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x10000 |
10266 | #define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x10 |
10267 | #define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x300000 |
10268 | #define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x14 |
10269 | #define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x1000000 |
10270 | #define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x18 |
10271 | #define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000 |
10272 | #define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x1c |
10273 | #define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000 |
10274 | #define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x1e |
10275 | #define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000 |
10276 | #define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x1f |
10277 | #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x1 |
10278 | #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x0 |
10279 | #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x10 |
10280 | #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x4 |
10281 | #define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x100 |
10282 | #define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x8 |
10283 | #define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x1000 |
10284 | #define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0xc |
10285 | #define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x10000 |
10286 | #define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x10 |
10287 | #define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x100000 |
10288 | #define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x14 |
10289 | #define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x1000000 |
10290 | #define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x18 |
10291 | #define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000 |
10292 | #define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x1c |
10293 | #define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0xff |
10294 | #define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x0 |
10295 | #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0xff00 |
10296 | #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x8 |
10297 | #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0xff0000 |
10298 | #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x10 |
10299 | #define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0xff |
10300 | #define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x0 |
10301 | #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x100 |
10302 | #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x8 |
10303 | #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x1000 |
10304 | #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0xc |
10305 | #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x10000 |
10306 | #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x10 |
10307 | #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x100000 |
10308 | #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x14 |
10309 | #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x1000000 |
10310 | #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x18 |
10311 | #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000 |
10312 | #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x1c |
10313 | #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000 |
10314 | #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x1e |
10315 | #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000 |
10316 | #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x1f |
10317 | #define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x1fff |
10318 | #define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x0 |
10319 | #define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000 |
10320 | #define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x10 |
10321 | #define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x1 |
10322 | #define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x0 |
10323 | #define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x10 |
10324 | #define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x4 |
10325 | #define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00 |
10326 | #define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x8 |
10327 | #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x3ff |
10328 | #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x0 |
10329 | #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0xffc00 |
10330 | #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0xa |
10331 | #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000 |
10332 | #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x14 |
10333 | #define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0xff |
10334 | #define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x0 |
10335 | #define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0xff00 |
10336 | #define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x8 |
10337 | #define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0xff0000 |
10338 | #define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x10 |
10339 | #define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000 |
10340 | #define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x1c |
10341 | #define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000 |
10342 | #define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x1d |
10343 | #define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000 |
10344 | #define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x1e |
10345 | #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0xffff |
10346 | #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x0 |
10347 | #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000 |
10348 | #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x10 |
10349 | #define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0xffff |
10350 | #define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x0 |
10351 | #define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x1 |
10352 | #define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x0 |
10353 | #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x10 |
10354 | #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x4 |
10355 | #define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x100 |
10356 | #define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x8 |
10357 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x1000 |
10358 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0xc |
10359 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x10000 |
10360 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x10 |
10361 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x100000 |
10362 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x14 |
10363 | #define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x1000000 |
10364 | #define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x18 |
10365 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000 |
10366 | #define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x1c |
10367 | #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x1fff |
10368 | #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x0 |
10369 | #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000 |
10370 | #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x10 |
10371 | #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000 |
10372 | #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x1f |
10373 | #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x1fff |
10374 | #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x0 |
10375 | #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000 |
10376 | #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x1f |
10377 | #define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x1 |
10378 | #define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x0 |
10379 | #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x2 |
10380 | #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x1 |
10381 | #define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x4 |
10382 | #define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x2 |
10383 | #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x8 |
10384 | #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x3 |
10385 | #define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x10 |
10386 | #define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x4 |
10387 | #define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x20 |
10388 | #define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x5 |
10389 | #define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x40 |
10390 | #define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x6 |
10391 | #define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x80 |
10392 | #define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x7 |
10393 | #define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00 |
10394 | #define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x8 |
10395 | #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0xff |
10396 | #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x0 |
10397 | #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x100 |
10398 | #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
10399 | #define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffff |
10400 | #define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x0 |
10401 | #define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x6 |
10402 | #define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1 |
10403 | #define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x6 |
10404 | #define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x1 |
10405 | #define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x1 |
10406 | #define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x0 |
10407 | #define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x1fffffe |
10408 | #define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x1 |
10409 | #define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x1 |
10410 | #define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x0 |
10411 | #define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x1fffffe |
10412 | #define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x1 |
10413 | #define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x2000000 |
10414 | #define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x19 |
10415 | #define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x4000000 |
10416 | #define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x1a |
10417 | #define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000 |
10418 | #define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x1b |
10419 | #define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x7 |
10420 | #define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x0 |
10421 | #define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x38 |
10422 | #define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x3 |
10423 | #define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x1c0 |
10424 | #define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x6 |
10425 | #define MVP_DEBUG_14__IDEE_START_READ_MASK 0x200 |
10426 | #define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x9 |
10427 | #define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x400 |
10428 | #define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0xa |
10429 | #define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x800 |
10430 | #define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0xb |
10431 | #define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x1000 |
10432 | #define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0xc |
10433 | #define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x2000 |
10434 | #define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0xd |
10435 | #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x4000 |
10436 | #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0xe |
10437 | #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x8000 |
10438 | #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0xf |
10439 | #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x10000 |
10440 | #define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x10 |
10441 | #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x20000 |
10442 | #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x11 |
10443 | #define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x40000 |
10444 | #define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x12 |
10445 | #define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x80000 |
10446 | #define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x13 |
10447 | #define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x100000 |
10448 | #define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x14 |
10449 | #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x1 |
10450 | #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x0 |
10451 | #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0 |
10452 | #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x4 |
10453 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x1 |
10454 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x0 |
10455 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x2 |
10456 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x1 |
10457 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x4 |
10458 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x2 |
10459 | #define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x8 |
10460 | #define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x3 |
10461 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0xff0 |
10462 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x4 |
10463 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x1000 |
10464 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0xc |
10465 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x2000 |
10466 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0xd |
10467 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0xff0000 |
10468 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x10 |
10469 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000 |
10470 | #define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x18 |
10471 | #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x1 |
10472 | #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x0 |
10473 | #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x2 |
10474 | #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x1 |
10475 | #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffc |
10476 | #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x2 |
10477 | #define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0xf |
10478 | #define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x0 |
10479 | #define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0xf00 |
10480 | #define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x8 |
10481 | #define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x70000 |
10482 | #define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x10 |
10483 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x3fff |
10484 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x0 |
10485 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 |
10486 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf |
10487 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000 |
10488 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x10 |
10489 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 |
10490 | #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f |
10491 | #define SCL_MODE__SCL_MODE_MASK 0x3 |
10492 | #define SCL_MODE__SCL_MODE__SHIFT 0x0 |
10493 | #define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x7 |
10494 | #define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x0 |
10495 | #define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0xf00 |
10496 | #define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x8 |
10497 | #define SCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x1 |
10498 | #define SCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 |
10499 | #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x3 |
10500 | #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x0 |
10501 | #define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0xf |
10502 | #define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 |
10503 | #define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0xf00 |
10504 | #define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 |
10505 | #define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN_MASK 0x1 |
10506 | #define SCL_AUTOMATIC_MODE_CONTROL__SCL_V_CALC_AUTO_RATIO_EN__SHIFT 0x0 |
10507 | #define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN_MASK 0x10000 |
10508 | #define SCL_AUTOMATIC_MODE_CONTROL__SCL_H_CALC_AUTO_RATIO_EN__SHIFT 0x10 |
10509 | #define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x1 |
10510 | #define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x0 |
10511 | #define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x100 |
10512 | #define SCL_HORZ_FILTER_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 |
10513 | #define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x3ffffff |
10514 | #define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 |
10515 | #define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0xffffff |
10516 | #define SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 |
10517 | #define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0xf000000 |
10518 | #define SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 |
10519 | #define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x1 |
10520 | #define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x0 |
10521 | #define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x100 |
10522 | #define SCL_VERT_FILTER_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x8 |
10523 | #define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x3ffffff |
10524 | #define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 |
10525 | #define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0xffffff |
10526 | #define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 |
10527 | #define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x7000000 |
10528 | #define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 |
10529 | #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0xffffff |
10530 | #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 |
10531 | #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x7000000 |
10532 | #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 |
10533 | #define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y_MASK 0xffff |
10534 | #define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_RGB_Y__SHIFT 0x0 |
10535 | #define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 |
10536 | #define SCL_ROUND_OFFSET__SCL_ROUND_OFFSET_CBCR__SHIFT 0x10 |
10537 | #define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x1 |
10538 | #define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 |
10539 | #define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x100 |
10540 | #define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x8 |
10541 | #define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x10000 |
10542 | #define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x10 |
10543 | #define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE_MASK 0x1000000 |
10544 | #define SCL_UPDATE__SCL_COEF_UPDATE_COMPLETE__SHIFT 0x18 |
10545 | #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x7 |
10546 | #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x0 |
10547 | #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x10 |
10548 | #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x4 |
10549 | #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x700 |
10550 | #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x8 |
10551 | #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x1000 |
10552 | #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0xc |
10553 | #define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x1 |
10554 | #define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x0 |
10555 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x1 |
10556 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x0 |
10557 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x100 |
10558 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x8 |
10559 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x1000 |
10560 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0xc |
10561 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000 |
10562 | #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 |
10563 | #define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x3fff |
10564 | #define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x0 |
10565 | #define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000 |
10566 | #define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x10 |
10567 | #define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x3fff |
10568 | #define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x0 |
10569 | #define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000 |
10570 | #define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x10 |
10571 | #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x1fff |
10572 | #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 |
10573 | #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000 |
10574 | #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 |
10575 | #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x1fff |
10576 | #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 |
10577 | #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000 |
10578 | #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 |
10579 | #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x1 |
10580 | #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x0 |
10581 | #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x10 |
10582 | #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x4 |
10583 | #define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0xfffff80 |
10584 | #define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x7 |
10585 | #define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x1fffff |
10586 | #define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x0 |
10587 | #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x3fff |
10588 | #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x0 |
10589 | #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000 |
10590 | #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x10 |
10591 | #define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x1 |
10592 | #define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x0 |
10593 | #define SCL_DEBUG2__SCL_DEBUG_REQ_MODE_MASK 0x1 |
10594 | #define SCL_DEBUG2__SCL_DEBUG_REQ_MODE__SHIFT 0x0 |
10595 | #define SCL_DEBUG2__SCL_DEBUG_EOF_MODE_MASK 0x6 |
10596 | #define SCL_DEBUG2__SCL_DEBUG_EOF_MODE__SHIFT 0x1 |
10597 | #define SCL_DEBUG2__SCL_DEBUG2_MASK 0xfffffff8 |
10598 | #define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x3 |
10599 | #define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffff |
10600 | #define SCL_DEBUG__SCL_DEBUG__SHIFT 0x0 |
10601 | #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0xff |
10602 | #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x0 |
10603 | #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x100 |
10604 | #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
10605 | #define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffff |
10606 | #define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x0 |
10607 | #define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x1 |
10608 | #define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x0 |
10609 | #define GENMO_WT__VGA_RAM_EN_MASK 0x2 |
10610 | #define GENMO_WT__VGA_RAM_EN__SHIFT 0x1 |
10611 | #define GENMO_WT__VGA_CKSEL_MASK 0xc |
10612 | #define GENMO_WT__VGA_CKSEL__SHIFT 0x2 |
10613 | #define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x20 |
10614 | #define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x5 |
10615 | #define GENMO_WT__VGA_HSYNC_POL_MASK 0x40 |
10616 | #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x6 |
10617 | #define GENMO_WT__VGA_VSYNC_POL_MASK 0x80 |
10618 | #define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x7 |
10619 | #define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x1 |
10620 | #define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x0 |
10621 | #define GENMO_RD__VGA_RAM_EN_MASK 0x2 |
10622 | #define GENMO_RD__VGA_RAM_EN__SHIFT 0x1 |
10623 | #define GENMO_RD__VGA_CKSEL_MASK 0xc |
10624 | #define GENMO_RD__VGA_CKSEL__SHIFT 0x2 |
10625 | #define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x20 |
10626 | #define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x5 |
10627 | #define GENMO_RD__VGA_HSYNC_POL_MASK 0x40 |
10628 | #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x6 |
10629 | #define GENMO_RD__VGA_VSYNC_POL_MASK 0x80 |
10630 | #define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x7 |
10631 | #define GENENB__BLK_IO_BASE_MASK 0xff |
10632 | #define GENENB__BLK_IO_BASE__SHIFT 0x0 |
10633 | #define GENFC_WT__VSYNC_SEL_W_MASK 0x8 |
10634 | #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x3 |
10635 | #define GENFC_RD__VSYNC_SEL_R_MASK 0x8 |
10636 | #define GENFC_RD__VSYNC_SEL_R__SHIFT 0x3 |
10637 | #define GENS0__SENSE_SWITCH_MASK 0x10 |
10638 | #define GENS0__SENSE_SWITCH__SHIFT 0x4 |
10639 | #define GENS0__CRT_INTR_MASK 0x80 |
10640 | #define GENS0__CRT_INTR__SHIFT 0x7 |
10641 | #define GENS1__NO_DISPLAY_MASK 0x1 |
10642 | #define GENS1__NO_DISPLAY__SHIFT 0x0 |
10643 | #define GENS1__VGA_VSTATUS_MASK 0x8 |
10644 | #define GENS1__VGA_VSTATUS__SHIFT 0x3 |
10645 | #define GENS1__PIXEL_READ_BACK_MASK 0x30 |
10646 | #define GENS1__PIXEL_READ_BACK__SHIFT 0x4 |
10647 | #define DAC_DATA__DAC_DATA_MASK 0x3f |
10648 | #define DAC_DATA__DAC_DATA__SHIFT 0x0 |
10649 | #define DAC_MASK__DAC_MASK_MASK 0xff |
10650 | #define DAC_MASK__DAC_MASK__SHIFT 0x0 |
10651 | #define DAC_R_INDEX__DAC_R_INDEX_MASK 0xff |
10652 | #define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x0 |
10653 | #define DAC_W_INDEX__DAC_W_INDEX_MASK 0xff |
10654 | #define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x0 |
10655 | #define SEQ8_IDX__SEQ_IDX_MASK 0x7 |
10656 | #define SEQ8_IDX__SEQ_IDX__SHIFT 0x0 |
10657 | #define SEQ8_DATA__SEQ_DATA_MASK 0xff |
10658 | #define SEQ8_DATA__SEQ_DATA__SHIFT 0x0 |
10659 | #define SEQ00__SEQ_RST0B_MASK 0x1 |
10660 | #define SEQ00__SEQ_RST0B__SHIFT 0x0 |
10661 | #define SEQ00__SEQ_RST1B_MASK 0x2 |
10662 | #define SEQ00__SEQ_RST1B__SHIFT 0x1 |
10663 | #define SEQ01__SEQ_DOT8_MASK 0x1 |
10664 | #define SEQ01__SEQ_DOT8__SHIFT 0x0 |
10665 | #define SEQ01__SEQ_SHIFT2_MASK 0x4 |
10666 | #define SEQ01__SEQ_SHIFT2__SHIFT 0x2 |
10667 | #define SEQ01__SEQ_PCLKBY2_MASK 0x8 |
10668 | #define SEQ01__SEQ_PCLKBY2__SHIFT 0x3 |
10669 | #define SEQ01__SEQ_SHIFT4_MASK 0x10 |
10670 | #define SEQ01__SEQ_SHIFT4__SHIFT 0x4 |
10671 | #define SEQ01__SEQ_MAXBW_MASK 0x20 |
10672 | #define SEQ01__SEQ_MAXBW__SHIFT 0x5 |
10673 | #define SEQ02__SEQ_MAP0_EN_MASK 0x1 |
10674 | #define SEQ02__SEQ_MAP0_EN__SHIFT 0x0 |
10675 | #define SEQ02__SEQ_MAP1_EN_MASK 0x2 |
10676 | #define SEQ02__SEQ_MAP1_EN__SHIFT 0x1 |
10677 | #define SEQ02__SEQ_MAP2_EN_MASK 0x4 |
10678 | #define SEQ02__SEQ_MAP2_EN__SHIFT 0x2 |
10679 | #define SEQ02__SEQ_MAP3_EN_MASK 0x8 |
10680 | #define SEQ02__SEQ_MAP3_EN__SHIFT 0x3 |
10681 | #define SEQ03__SEQ_FONT_B1_MASK 0x1 |
10682 | #define SEQ03__SEQ_FONT_B1__SHIFT 0x0 |
10683 | #define SEQ03__SEQ_FONT_B2_MASK 0x2 |
10684 | #define SEQ03__SEQ_FONT_B2__SHIFT 0x1 |
10685 | #define SEQ03__SEQ_FONT_A1_MASK 0x4 |
10686 | #define SEQ03__SEQ_FONT_A1__SHIFT 0x2 |
10687 | #define SEQ03__SEQ_FONT_A2_MASK 0x8 |
10688 | #define SEQ03__SEQ_FONT_A2__SHIFT 0x3 |
10689 | #define SEQ03__SEQ_FONT_B0_MASK 0x10 |
10690 | #define SEQ03__SEQ_FONT_B0__SHIFT 0x4 |
10691 | #define SEQ03__SEQ_FONT_A0_MASK 0x20 |
10692 | #define SEQ03__SEQ_FONT_A0__SHIFT 0x5 |
10693 | #define SEQ04__SEQ_256K_MASK 0x2 |
10694 | #define SEQ04__SEQ_256K__SHIFT 0x1 |
10695 | #define SEQ04__SEQ_ODDEVEN_MASK 0x4 |
10696 | #define SEQ04__SEQ_ODDEVEN__SHIFT 0x2 |
10697 | #define SEQ04__SEQ_CHAIN_MASK 0x8 |
10698 | #define SEQ04__SEQ_CHAIN__SHIFT 0x3 |
10699 | #define CRTC8_IDX__VCRTC_IDX_MASK 0x3f |
10700 | #define CRTC8_IDX__VCRTC_IDX__SHIFT 0x0 |
10701 | #define CRTC8_DATA__VCRTC_DATA_MASK 0xff |
10702 | #define CRTC8_DATA__VCRTC_DATA__SHIFT 0x0 |
10703 | #define CRT00__H_TOTAL_MASK 0xff |
10704 | #define CRT00__H_TOTAL__SHIFT 0x0 |
10705 | #define CRT01__H_DISP_END_MASK 0xff |
10706 | #define CRT01__H_DISP_END__SHIFT 0x0 |
10707 | #define CRT02__H_BLANK_START_MASK 0xff |
10708 | #define CRT02__H_BLANK_START__SHIFT 0x0 |
10709 | #define CRT03__H_BLANK_END_MASK 0x1f |
10710 | #define CRT03__H_BLANK_END__SHIFT 0x0 |
10711 | #define CRT03__H_DE_SKEW_MASK 0x60 |
10712 | #define CRT03__H_DE_SKEW__SHIFT 0x5 |
10713 | #define CRT03__CR10CR11_R_DIS_B_MASK 0x80 |
10714 | #define CRT03__CR10CR11_R_DIS_B__SHIFT 0x7 |
10715 | #define CRT04__H_SYNC_START_MASK 0xff |
10716 | #define CRT04__H_SYNC_START__SHIFT 0x0 |
10717 | #define CRT05__H_SYNC_END_MASK 0x1f |
10718 | #define CRT05__H_SYNC_END__SHIFT 0x0 |
10719 | #define CRT05__H_SYNC_SKEW_MASK 0x60 |
10720 | #define CRT05__H_SYNC_SKEW__SHIFT 0x5 |
10721 | #define CRT05__H_BLANK_END_B5_MASK 0x80 |
10722 | #define CRT05__H_BLANK_END_B5__SHIFT 0x7 |
10723 | #define CRT06__V_TOTAL_MASK 0xff |
10724 | #define CRT06__V_TOTAL__SHIFT 0x0 |
10725 | #define CRT07__V_TOTAL_B8_MASK 0x1 |
10726 | #define CRT07__V_TOTAL_B8__SHIFT 0x0 |
10727 | #define CRT07__V_DISP_END_B8_MASK 0x2 |
10728 | #define CRT07__V_DISP_END_B8__SHIFT 0x1 |
10729 | #define CRT07__V_SYNC_START_B8_MASK 0x4 |
10730 | #define CRT07__V_SYNC_START_B8__SHIFT 0x2 |
10731 | #define CRT07__V_BLANK_START_B8_MASK 0x8 |
10732 | #define CRT07__V_BLANK_START_B8__SHIFT 0x3 |
10733 | #define CRT07__LINE_CMP_B8_MASK 0x10 |
10734 | #define CRT07__LINE_CMP_B8__SHIFT 0x4 |
10735 | #define CRT07__V_TOTAL_B9_MASK 0x20 |
10736 | #define CRT07__V_TOTAL_B9__SHIFT 0x5 |
10737 | #define CRT07__V_DISP_END_B9_MASK 0x40 |
10738 | #define CRT07__V_DISP_END_B9__SHIFT 0x6 |
10739 | #define CRT07__V_SYNC_START_B9_MASK 0x80 |
10740 | #define CRT07__V_SYNC_START_B9__SHIFT 0x7 |
10741 | #define CRT08__ROW_SCAN_START_MASK 0x1f |
10742 | #define CRT08__ROW_SCAN_START__SHIFT 0x0 |
10743 | #define CRT08__BYTE_PAN_MASK 0x60 |
10744 | #define CRT08__BYTE_PAN__SHIFT 0x5 |
10745 | #define CRT09__MAX_ROW_SCAN_MASK 0x1f |
10746 | #define CRT09__MAX_ROW_SCAN__SHIFT 0x0 |
10747 | #define CRT09__V_BLANK_START_B9_MASK 0x20 |
10748 | #define CRT09__V_BLANK_START_B9__SHIFT 0x5 |
10749 | #define CRT09__LINE_CMP_B9_MASK 0x40 |
10750 | #define CRT09__LINE_CMP_B9__SHIFT 0x6 |
10751 | #define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x80 |
10752 | #define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x7 |
10753 | #define CRT0A__CURSOR_START_MASK 0x1f |
10754 | #define CRT0A__CURSOR_START__SHIFT 0x0 |
10755 | #define CRT0A__CURSOR_DISABLE_MASK 0x20 |
10756 | #define CRT0A__CURSOR_DISABLE__SHIFT 0x5 |
10757 | #define CRT0B__CURSOR_END_MASK 0x1f |
10758 | #define CRT0B__CURSOR_END__SHIFT 0x0 |
10759 | #define CRT0B__CURSOR_SKEW_MASK 0x60 |
10760 | #define CRT0B__CURSOR_SKEW__SHIFT 0x5 |
10761 | #define CRT0C__DISP_START_MASK 0xff |
10762 | #define CRT0C__DISP_START__SHIFT 0x0 |
10763 | #define CRT0D__DISP_START_MASK 0xff |
10764 | #define CRT0D__DISP_START__SHIFT 0x0 |
10765 | #define CRT0E__CURSOR_LOC_HI_MASK 0xff |
10766 | #define CRT0E__CURSOR_LOC_HI__SHIFT 0x0 |
10767 | #define CRT0F__CURSOR_LOC_LO_MASK 0xff |
10768 | #define CRT0F__CURSOR_LOC_LO__SHIFT 0x0 |
10769 | #define CRT10__V_SYNC_START_MASK 0xff |
10770 | #define CRT10__V_SYNC_START__SHIFT 0x0 |
10771 | #define CRT11__V_SYNC_END_MASK 0xf |
10772 | #define CRT11__V_SYNC_END__SHIFT 0x0 |
10773 | #define CRT11__V_INTR_CLR_MASK 0x10 |
10774 | #define CRT11__V_INTR_CLR__SHIFT 0x4 |
10775 | #define CRT11__V_INTR_EN_MASK 0x20 |
10776 | #define CRT11__V_INTR_EN__SHIFT 0x5 |
10777 | #define CRT11__SEL5_REFRESH_CYC_MASK 0x40 |
10778 | #define CRT11__SEL5_REFRESH_CYC__SHIFT 0x6 |
10779 | #define CRT11__C0T7_WR_ONLY_MASK 0x80 |
10780 | #define CRT11__C0T7_WR_ONLY__SHIFT 0x7 |
10781 | #define CRT12__V_DISP_END_MASK 0xff |
10782 | #define CRT12__V_DISP_END__SHIFT 0x0 |
10783 | #define CRT13__DISP_PITCH_MASK 0xff |
10784 | #define CRT13__DISP_PITCH__SHIFT 0x0 |
10785 | #define CRT14__UNDRLN_LOC_MASK 0x1f |
10786 | #define CRT14__UNDRLN_LOC__SHIFT 0x0 |
10787 | #define CRT14__ADDR_CNT_BY4_MASK 0x20 |
10788 | #define CRT14__ADDR_CNT_BY4__SHIFT 0x5 |
10789 | #define CRT14__DOUBLE_WORD_MASK 0x40 |
10790 | #define CRT14__DOUBLE_WORD__SHIFT 0x6 |
10791 | #define CRT15__V_BLANK_START_MASK 0xff |
10792 | #define CRT15__V_BLANK_START__SHIFT 0x0 |
10793 | #define CRT16__V_BLANK_END_MASK 0xff |
10794 | #define CRT16__V_BLANK_END__SHIFT 0x0 |
10795 | #define CRT17__RA0_AS_A13B_MASK 0x1 |
10796 | #define CRT17__RA0_AS_A13B__SHIFT 0x0 |
10797 | #define CRT17__RA1_AS_A14B_MASK 0x2 |
10798 | #define CRT17__RA1_AS_A14B__SHIFT 0x1 |
10799 | #define CRT17__VCOUNT_BY2_MASK 0x4 |
10800 | #define CRT17__VCOUNT_BY2__SHIFT 0x2 |
10801 | #define CRT17__ADDR_CNT_BY2_MASK 0x8 |
10802 | #define CRT17__ADDR_CNT_BY2__SHIFT 0x3 |
10803 | #define CRT17__WRAP_A15TOA0_MASK 0x20 |
10804 | #define CRT17__WRAP_A15TOA0__SHIFT 0x5 |
10805 | #define CRT17__BYTE_MODE_MASK 0x40 |
10806 | #define CRT17__BYTE_MODE__SHIFT 0x6 |
10807 | #define CRT17__CRTC_SYNC_EN_MASK 0x80 |
10808 | #define CRT17__CRTC_SYNC_EN__SHIFT 0x7 |
10809 | #define CRT18__LINE_CMP_MASK 0xff |
10810 | #define CRT18__LINE_CMP__SHIFT 0x0 |
10811 | #define CRT1E__GRPH_DEC_RD1_MASK 0x2 |
10812 | #define CRT1E__GRPH_DEC_RD1__SHIFT 0x1 |
10813 | #define CRT1F__GRPH_DEC_RD0_MASK 0xff |
10814 | #define CRT1F__GRPH_DEC_RD0__SHIFT 0x0 |
10815 | #define CRT22__GRPH_LATCH_DATA_MASK 0xff |
10816 | #define CRT22__GRPH_LATCH_DATA__SHIFT 0x0 |
10817 | #define GRPH8_IDX__GRPH_IDX_MASK 0xf |
10818 | #define GRPH8_IDX__GRPH_IDX__SHIFT 0x0 |
10819 | #define GRPH8_DATA__GRPH_DATA_MASK 0xff |
10820 | #define GRPH8_DATA__GRPH_DATA__SHIFT 0x0 |
10821 | #define GRA00__GRPH_SET_RESET0_MASK 0x1 |
10822 | #define GRA00__GRPH_SET_RESET0__SHIFT 0x0 |
10823 | #define GRA00__GRPH_SET_RESET1_MASK 0x2 |
10824 | #define GRA00__GRPH_SET_RESET1__SHIFT 0x1 |
10825 | #define GRA00__GRPH_SET_RESET2_MASK 0x4 |
10826 | #define GRA00__GRPH_SET_RESET2__SHIFT 0x2 |
10827 | #define GRA00__GRPH_SET_RESET3_MASK 0x8 |
10828 | #define GRA00__GRPH_SET_RESET3__SHIFT 0x3 |
10829 | #define GRA01__GRPH_SET_RESET_ENA0_MASK 0x1 |
10830 | #define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x0 |
10831 | #define GRA01__GRPH_SET_RESET_ENA1_MASK 0x2 |
10832 | #define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x1 |
10833 | #define GRA01__GRPH_SET_RESET_ENA2_MASK 0x4 |
10834 | #define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x2 |
10835 | #define GRA01__GRPH_SET_RESET_ENA3_MASK 0x8 |
10836 | #define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x3 |
10837 | #define GRA02__GRPH_CCOMP_MASK 0xf |
10838 | #define GRA02__GRPH_CCOMP__SHIFT 0x0 |
10839 | #define GRA03__GRPH_ROTATE_MASK 0x7 |
10840 | #define GRA03__GRPH_ROTATE__SHIFT 0x0 |
10841 | #define GRA03__GRPH_FN_SEL_MASK 0x18 |
10842 | #define GRA03__GRPH_FN_SEL__SHIFT 0x3 |
10843 | #define GRA04__GRPH_RMAP_MASK 0x3 |
10844 | #define GRA04__GRPH_RMAP__SHIFT 0x0 |
10845 | #define GRA05__GRPH_WRITE_MODE_MASK 0x3 |
10846 | #define GRA05__GRPH_WRITE_MODE__SHIFT 0x0 |
10847 | #define GRA05__GRPH_READ1_MASK 0x8 |
10848 | #define GRA05__GRPH_READ1__SHIFT 0x3 |
10849 | #define GRA05__CGA_ODDEVEN_MASK 0x10 |
10850 | #define GRA05__CGA_ODDEVEN__SHIFT 0x4 |
10851 | #define GRA05__GRPH_OES_MASK 0x20 |
10852 | #define GRA05__GRPH_OES__SHIFT 0x5 |
10853 | #define GRA05__GRPH_PACK_MASK 0x40 |
10854 | #define GRA05__GRPH_PACK__SHIFT 0x6 |
10855 | #define GRA06__GRPH_GRAPHICS_MASK 0x1 |
10856 | #define GRA06__GRPH_GRAPHICS__SHIFT 0x0 |
10857 | #define GRA06__GRPH_ODDEVEN_MASK 0x2 |
10858 | #define GRA06__GRPH_ODDEVEN__SHIFT 0x1 |
10859 | #define GRA06__GRPH_ADRSEL_MASK 0xc |
10860 | #define GRA06__GRPH_ADRSEL__SHIFT 0x2 |
10861 | #define GRA07__GRPH_XCARE0_MASK 0x1 |
10862 | #define GRA07__GRPH_XCARE0__SHIFT 0x0 |
10863 | #define GRA07__GRPH_XCARE1_MASK 0x2 |
10864 | #define GRA07__GRPH_XCARE1__SHIFT 0x1 |
10865 | #define GRA07__GRPH_XCARE2_MASK 0x4 |
10866 | #define GRA07__GRPH_XCARE2__SHIFT 0x2 |
10867 | #define GRA07__GRPH_XCARE3_MASK 0x8 |
10868 | #define GRA07__GRPH_XCARE3__SHIFT 0x3 |
10869 | #define GRA08__GRPH_BMSK_MASK 0xff |
10870 | #define GRA08__GRPH_BMSK__SHIFT 0x0 |
10871 | #define ATTRX__ATTR_IDX_MASK 0x1f |
10872 | #define ATTRX__ATTR_IDX__SHIFT 0x0 |
10873 | #define ATTRX__ATTR_PAL_RW_ENB_MASK 0x20 |
10874 | #define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x5 |
10875 | #define ATTRDW__ATTR_DATA_MASK 0xff |
10876 | #define ATTRDW__ATTR_DATA__SHIFT 0x0 |
10877 | #define ATTRDR__ATTR_DATA_MASK 0xff |
10878 | #define ATTRDR__ATTR_DATA__SHIFT 0x0 |
10879 | #define ATTR00__ATTR_PAL_MASK 0x3f |
10880 | #define ATTR00__ATTR_PAL__SHIFT 0x0 |
10881 | #define ATTR01__ATTR_PAL_MASK 0x3f |
10882 | #define ATTR01__ATTR_PAL__SHIFT 0x0 |
10883 | #define ATTR02__ATTR_PAL_MASK 0x3f |
10884 | #define ATTR02__ATTR_PAL__SHIFT 0x0 |
10885 | #define ATTR03__ATTR_PAL_MASK 0x3f |
10886 | #define ATTR03__ATTR_PAL__SHIFT 0x0 |
10887 | #define ATTR04__ATTR_PAL_MASK 0x3f |
10888 | #define ATTR04__ATTR_PAL__SHIFT 0x0 |
10889 | #define ATTR05__ATTR_PAL_MASK 0x3f |
10890 | #define ATTR05__ATTR_PAL__SHIFT 0x0 |
10891 | #define ATTR06__ATTR_PAL_MASK 0x3f |
10892 | #define ATTR06__ATTR_PAL__SHIFT 0x0 |
10893 | #define ATTR07__ATTR_PAL_MASK 0x3f |
10894 | #define ATTR07__ATTR_PAL__SHIFT 0x0 |
10895 | #define ATTR08__ATTR_PAL_MASK 0x3f |
10896 | #define ATTR08__ATTR_PAL__SHIFT 0x0 |
10897 | #define ATTR09__ATTR_PAL_MASK 0x3f |
10898 | #define ATTR09__ATTR_PAL__SHIFT 0x0 |
10899 | #define ATTR0A__ATTR_PAL_MASK 0x3f |
10900 | #define ATTR0A__ATTR_PAL__SHIFT 0x0 |
10901 | #define ATTR0B__ATTR_PAL_MASK 0x3f |
10902 | #define ATTR0B__ATTR_PAL__SHIFT 0x0 |
10903 | #define ATTR0C__ATTR_PAL_MASK 0x3f |
10904 | #define ATTR0C__ATTR_PAL__SHIFT 0x0 |
10905 | #define ATTR0D__ATTR_PAL_MASK 0x3f |
10906 | #define ATTR0D__ATTR_PAL__SHIFT 0x0 |
10907 | #define ATTR0E__ATTR_PAL_MASK 0x3f |
10908 | #define ATTR0E__ATTR_PAL__SHIFT 0x0 |
10909 | #define ATTR0F__ATTR_PAL_MASK 0x3f |
10910 | #define ATTR0F__ATTR_PAL__SHIFT 0x0 |
10911 | #define ATTR10__ATTR_GRPH_MODE_MASK 0x1 |
10912 | #define ATTR10__ATTR_GRPH_MODE__SHIFT 0x0 |
10913 | #define ATTR10__ATTR_MONO_EN_MASK 0x2 |
10914 | #define ATTR10__ATTR_MONO_EN__SHIFT 0x1 |
10915 | #define ATTR10__ATTR_LGRPH_EN_MASK 0x4 |
10916 | #define ATTR10__ATTR_LGRPH_EN__SHIFT 0x2 |
10917 | #define ATTR10__ATTR_BLINK_EN_MASK 0x8 |
10918 | #define ATTR10__ATTR_BLINK_EN__SHIFT 0x3 |
10919 | #define ATTR10__ATTR_PANTOPONLY_MASK 0x20 |
10920 | #define ATTR10__ATTR_PANTOPONLY__SHIFT 0x5 |
10921 | #define ATTR10__ATTR_PCLKBY2_MASK 0x40 |
10922 | #define ATTR10__ATTR_PCLKBY2__SHIFT 0x6 |
10923 | #define ATTR10__ATTR_CSEL_EN_MASK 0x80 |
10924 | #define ATTR10__ATTR_CSEL_EN__SHIFT 0x7 |
10925 | #define ATTR11__ATTR_OVSC_MASK 0xff |
10926 | #define ATTR11__ATTR_OVSC__SHIFT 0x0 |
10927 | #define ATTR12__ATTR_MAP_EN_MASK 0xf |
10928 | #define ATTR12__ATTR_MAP_EN__SHIFT 0x0 |
10929 | #define ATTR12__ATTR_VSMUX_MASK 0x30 |
10930 | #define ATTR12__ATTR_VSMUX__SHIFT 0x4 |
10931 | #define ATTR13__ATTR_PPAN_MASK 0xf |
10932 | #define ATTR13__ATTR_PPAN__SHIFT 0x0 |
10933 | #define ATTR14__ATTR_CSEL1_MASK 0x3 |
10934 | #define ATTR14__ATTR_CSEL1__SHIFT 0x0 |
10935 | #define ATTR14__ATTR_CSEL2_MASK 0xc |
10936 | #define ATTR14__ATTR_CSEL2__SHIFT 0x2 |
10937 | #define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x1f |
10938 | #define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0 |
10939 | #define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x60 |
10940 | #define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5 |
10941 | #define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x80 |
10942 | #define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x7 |
10943 | #define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x100 |
10944 | #define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x8 |
10945 | #define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x30000 |
10946 | #define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 |
10947 | #define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x1000000 |
10948 | #define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x18 |
10949 | #define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x2000000 |
10950 | #define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x19 |
10951 | #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x7 |
10952 | #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x0 |
10953 | #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x700 |
10954 | #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x8 |
10955 | #define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x1 |
10956 | #define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x0 |
10957 | #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x2 |
10958 | #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x1 |
10959 | #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x4 |
10960 | #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x2 |
10961 | #define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x8 |
10962 | #define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x3 |
10963 | #define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x10 |
10964 | #define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x4 |
10965 | #define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x20 |
10966 | #define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x5 |
10967 | #define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x100 |
10968 | #define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x8 |
10969 | #define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x200 |
10970 | #define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x9 |
10971 | #define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x400 |
10972 | #define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xa |
10973 | #define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x800 |
10974 | #define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xb |
10975 | #define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x1000 |
10976 | #define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xc |
10977 | #define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x2000 |
10978 | #define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0xd |
10979 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x10000 |
10980 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 |
10981 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x20000 |
10982 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x11 |
10983 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0xfc0000 |
10984 | #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x12 |
10985 | #define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x1 |
10986 | #define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x0 |
10987 | #define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x30 |
10988 | #define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x4 |
10989 | #define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x100 |
10990 | #define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x8 |
10991 | #define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x10000 |
10992 | #define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 |
10993 | #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x3 |
10994 | #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x0 |
10995 | #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x300 |
10996 | #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x8 |
10997 | #define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffff |
10998 | #define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x0 |
10999 | #define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0xff |
11000 | #define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x0 |
11001 | #define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x1ffffff |
11002 | #define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x0 |
11003 | #define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x1ffffff |
11004 | #define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x0 |
11005 | #define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x1 |
11006 | #define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x0 |
11007 | #define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x10 |
11008 | #define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x4 |
11009 | #define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x100 |
11010 | #define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x8 |
11011 | #define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x10000 |
11012 | #define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 |
11013 | #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000 |
11014 | #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x18 |
11015 | #define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x1 |
11016 | #define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x0 |
11017 | #define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x100 |
11018 | #define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x8 |
11019 | #define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x10000 |
11020 | #define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 |
11021 | #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x100000 |
11022 | #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x14 |
11023 | #define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000 |
11024 | #define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x18 |
11025 | #define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x1 |
11026 | #define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x0 |
11027 | #define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x100 |
11028 | #define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x8 |
11029 | #define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x200 |
11030 | #define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
11031 | #define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x10000 |
11032 | #define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
11033 | #define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x3000000 |
11034 | #define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x18 |
11035 | #define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x1 |
11036 | #define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x0 |
11037 | #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x100 |
11038 | #define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x8 |
11039 | #define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x200 |
11040 | #define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
11041 | #define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x10000 |
11042 | #define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
11043 | #define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x3000000 |
11044 | #define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x18 |
11045 | #define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x1 |
11046 | #define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x0 |
11047 | #define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x100 |
11048 | #define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x8 |
11049 | #define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x200 |
11050 | #define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
11051 | #define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x10000 |
11052 | #define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
11053 | #define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x3000000 |
11054 | #define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x18 |
11055 | #define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x1 |
11056 | #define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x0 |
11057 | #define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x100 |
11058 | #define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x8 |
11059 | #define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x200 |
11060 | #define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
11061 | #define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x10000 |
11062 | #define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
11063 | #define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x3000000 |
11064 | #define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x18 |
11065 | #define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x1 |
11066 | #define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x0 |
11067 | #define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x100 |
11068 | #define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x8 |
11069 | #define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x200 |
11070 | #define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
11071 | #define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x10000 |
11072 | #define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
11073 | #define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x3000000 |
11074 | #define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x18 |
11075 | #define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x1 |
11076 | #define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x0 |
11077 | #define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x100 |
11078 | #define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x8 |
11079 | #define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x200 |
11080 | #define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x9 |
11081 | #define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x10000 |
11082 | #define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 |
11083 | #define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x3000000 |
11084 | #define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x18 |
11085 | #define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffff |
11086 | #define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x0 |
11087 | #define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x1 |
11088 | #define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x0 |
11089 | #define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x2 |
11090 | #define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x1 |
11091 | #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x4 |
11092 | #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x2 |
11093 | #define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x8 |
11094 | #define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x3 |
11095 | #define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x1 |
11096 | #define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x0 |
11097 | #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x100 |
11098 | #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x8 |
11099 | #define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x10000 |
11100 | #define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 |
11101 | #define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x1000000 |
11102 | #define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x18 |
11103 | #define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x1 |
11104 | #define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x0 |
11105 | #define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x100 |
11106 | #define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x8 |
11107 | #define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x10000 |
11108 | #define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x10 |
11109 | #define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x1000000 |
11110 | #define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x18 |
11111 | #define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x1 |
11112 | #define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x0 |
11113 | #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2 |
11114 | #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x1 |
11115 | #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x4 |
11116 | #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x2 |
11117 | #define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x8 |
11118 | #define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x3 |
11119 | #define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x3 |
11120 | #define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x0 |
11121 | #define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x18 |
11122 | #define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x3 |
11123 | #define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0xe0 |
11124 | #define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x5 |
11125 | #define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x300 |
11126 | #define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x8 |
11127 | #define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x30000 |
11128 | #define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x10 |
11129 | #define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x3000000 |
11130 | #define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x18 |
11131 | #define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x4000000 |
11132 | #define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x1a |
11133 | #define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x8000000 |
11134 | #define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x1b |
11135 | #define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000 |
11136 | #define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x1c |
11137 | #define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000 |
11138 | #define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x1d |
11139 | #define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000 |
11140 | #define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x1f |
11141 | #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x1 |
11142 | #define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x0 |
11143 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x100 |
11144 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x8 |
11145 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x10000 |
11146 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x10 |
11147 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x1000000 |
11148 | #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x18 |
11149 | #define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0xff |
11150 | #define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x0 |
11151 | #define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffff |
11152 | #define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x0 |
11153 | #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x3ff |
11154 | #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0 |
11155 | #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x3ff0000 |
11156 | #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 |
11157 | #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x3ff |
11158 | #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0 |
11159 | #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x3ff0000 |
11160 | #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 |
11161 | #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0xff |
11162 | #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x0 |
11163 | #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x100 |
11164 | #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
11165 | #define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffff |
11166 | #define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x0 |
11167 | #define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffff |
11168 | #define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x0 |
11169 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x3 |
11170 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x0 |
11171 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x3f00 |
11172 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x8 |
11173 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x3f0000 |
11174 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x10 |
11175 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0xf000000 |
11176 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x18 |
11177 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000 |
11178 | #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x1c |
11179 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x1 |
11180 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x0 |
11181 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x2 |
11182 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x1 |
11183 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x4 |
11184 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x2 |
11185 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x3ff0 |
11186 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x4 |
11187 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x700000 |
11188 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x14 |
11189 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000 |
11190 | #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x1c |
11191 | #define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0xffff |
11192 | #define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x0 |
11193 | #define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000 |
11194 | #define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x10 |
11195 | #define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0xffff |
11196 | #define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x0 |
11197 | #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000 |
11198 | #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x10 |
11199 | #define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x3 |
11200 | #define DPG_WATERMARK_MASK_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0 |
11201 | #define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK_MASK 0x300 |
11202 | #define DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT 0x8 |
11203 | #define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x30000 |
11204 | #define DPG_WATERMARK_MASK_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x10 |
11205 | #define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0xffff |
11206 | #define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x0 |
11207 | #define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000 |
11208 | #define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x10 |
11209 | #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x1 |
11210 | #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x0 |
11211 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x10 |
11212 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x4 |
11213 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x100 |
11214 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x8 |
11215 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x3000 |
11216 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0xc |
11217 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000 |
11218 | #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x10 |
11219 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x1 |
11220 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x0 |
11221 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x10 |
11222 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x4 |
11223 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x20 |
11224 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x5 |
11225 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x40 |
11226 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x6 |
11227 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x80 |
11228 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x7 |
11229 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x100 |
11230 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x8 |
11231 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x200 |
11232 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x9 |
11233 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x400 |
11234 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0xa |
11235 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x800 |
11236 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0xb |
11237 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000 |
11238 | #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x10 |
11239 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x1 |
11240 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x0 |
11241 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x10 |
11242 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x4 |
11243 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x100 |
11244 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x8 |
11245 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x200 |
11246 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x9 |
11247 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x400 |
11248 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0xa |
11249 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000 |
11250 | #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x10 |
11251 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x1 |
11252 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x0 |
11253 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x10 |
11254 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x4 |
11255 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x20 |
11256 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x5 |
11257 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x40 |
11258 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x6 |
11259 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x80 |
11260 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x7 |
11261 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x100 |
11262 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x8 |
11263 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x200 |
11264 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x9 |
11265 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x400 |
11266 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0xa |
11267 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x800 |
11268 | #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0xb |
11269 | #define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER_MASK 0x7 |
11270 | #define DPG_REPEATER_PROGRAM__REG_DPG_DMIFRC_REPEATER__SHIFT 0x0 |
11271 | #define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER_MASK 0x70 |
11272 | #define DPG_REPEATER_PROGRAM__REG_DMIFRC_DPG_REPEATER__SHIFT 0x4 |
11273 | #define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A_MASK 0xffffffff |
11274 | #define DPG_HW_DEBUG_A__DPG_HW_DEBUG_A__SHIFT 0x0 |
11275 | #define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B_MASK 0xffffffff |
11276 | #define DPG_HW_DEBUG_B__DPG_HW_DEBUG_B__SHIFT 0x0 |
11277 | #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0xff |
11278 | #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x0 |
11279 | #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x100 |
11280 | #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
11281 | #define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffff |
11282 | #define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x0 |
11283 | #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff |
11284 | #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
11285 | #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff |
11286 | #define AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
11287 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff |
11288 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 |
11289 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff |
11290 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 |
11291 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff |
11292 | #define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 |
11293 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffff |
11294 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 |
11295 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff |
11296 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 |
11297 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff |
11298 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
11299 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 |
11300 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
11301 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff |
11302 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 |
11303 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff |
11304 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 |
11305 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 |
11306 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e |
11307 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 |
11308 | #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f |
11309 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf |
11310 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 |
11311 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 |
11312 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 |
11313 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 |
11314 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 |
11315 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 |
11316 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa |
11317 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 |
11318 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 |
11319 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff |
11320 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 |
11321 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 |
11322 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 |
11323 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 |
11324 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 |
11325 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 |
11326 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 |
11327 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0xff |
11328 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 |
11329 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0xff |
11330 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 |
11331 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0xff |
11332 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 |
11333 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f |
11334 | #define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 |
11335 | #define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffff |
11336 | #define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 |
11337 | #define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffff |
11338 | #define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 |
11339 | #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x7 |
11340 | #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 |
11341 | #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x70 |
11342 | #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 |
11343 | #define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x3f |
11344 | #define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 |
11345 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffff |
11346 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 |
11347 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff |
11348 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
11349 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 |
11350 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
11351 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffff |
11352 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 |
11353 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffff |
11354 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 |
11355 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000 |
11356 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e |
11357 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000 |
11358 | #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f |
11359 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0xf |
11360 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 |
11361 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0xf0 |
11362 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 |
11363 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x200 |
11364 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 |
11365 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x400 |
11366 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa |
11367 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x1 |
11368 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 |
11369 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0xff |
11370 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 |
11371 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0xff00 |
11372 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 |
11373 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0xff0000 |
11374 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 |
11375 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000 |
11376 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 |
11377 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x7f |
11378 | #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 |
11379 | #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x7 |
11380 | #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 |
11381 | #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x10 |
11382 | #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 |
11383 | #define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffff |
11384 | #define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x0 |
11385 | #define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK 0xffffffff |
11386 | #define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT 0x0 |
11387 | #define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK 0xffffffff |
11388 | #define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT 0x0 |
11389 | #define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK 0xffffffff |
11390 | #define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT 0x0 |
11391 | #define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK 0xffffffff |
11392 | #define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT 0x0 |
11393 | #define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK 0xffffffff |
11394 | #define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT 0x0 |
11395 | #define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK 0xffffffff |
11396 | #define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT 0x0 |
11397 | #define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK 0xffffffff |
11398 | #define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT 0x0 |
11399 | #define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x1 |
11400 | #define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0 |
11401 | #define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 |
11402 | #define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 |
11403 | #define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0xf8 |
11404 | #define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3 |
11405 | #define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0xf00 |
11406 | #define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8 |
11407 | #define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xf000 |
11408 | #define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc |
11409 | #define MINOR_VERSION__MINOR_VERSION_MASK 0xff |
11410 | #define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0 |
11411 | #define MAJOR_VERSION__MAJOR_VERSION_MASK 0xff |
11412 | #define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0 |
11413 | #define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff |
11414 | #define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 |
11415 | #define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xffff |
11416 | #define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 |
11417 | #define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x1 |
11418 | #define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0 |
11419 | #define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x2 |
11420 | #define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1 |
11421 | #define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x100 |
11422 | #define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8 |
11423 | #define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x1 |
11424 | #define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0 |
11425 | #define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x1 |
11426 | #define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0 |
11427 | #define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x2 |
11428 | #define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1 |
11429 | #define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff |
11430 | #define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0 |
11431 | #define INTERRUPT_CONTROL__OUTPUT_STREAM_0_INTERRUPT_ENABLE_MASK 0x1 |
11432 | #define INTERRUPT_CONTROL__OUTPUT_STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0 |
11433 | #define INTERRUPT_CONTROL__OUTPUT_STREAM_1_INTERRUPT_ENABLE_MASK 0x2 |
11434 | #define INTERRUPT_CONTROL__OUTPUT_STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1 |
11435 | #define INTERRUPT_CONTROL__OUTPUT_STREAM_2_INTERRUPT_ENABLE_MASK 0x4 |
11436 | #define INTERRUPT_CONTROL__OUTPUT_STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2 |
11437 | #define INTERRUPT_CONTROL__OUTPUT_STREAM_3_INTERRUPT_ENABLE_MASK 0x8 |
11438 | #define INTERRUPT_CONTROL__OUTPUT_STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3 |
11439 | #define INTERRUPT_CONTROL__OUTPUT_STREAM_4_INTERRUPT_ENABLE_MASK 0x10 |
11440 | #define INTERRUPT_CONTROL__OUTPUT_STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4 |
11441 | #define INTERRUPT_CONTROL__OUTPUT_STREAM_5_INTERRUPT_ENABLE_MASK 0x20 |
11442 | #define INTERRUPT_CONTROL__OUTPUT_STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5 |
11443 | #define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000 |
11444 | #define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e |
11445 | #define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000 |
11446 | #define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f |
11447 | #define INTERRUPT_STATUS__OUTPUT_STREAM_0_INTERRUPT_STATUS_MASK 0x1 |
11448 | #define INTERRUPT_STATUS__OUTPUT_STREAM_0_INTERRUPT_STATUS__SHIFT 0x0 |
11449 | #define INTERRUPT_STATUS__OUTPUT_STREAM_1_INTERRUPT_STATUS_MASK 0x2 |
11450 | #define INTERRUPT_STATUS__OUTPUT_STREAM_1_INTERRUPT_STATUS__SHIFT 0x1 |
11451 | #define INTERRUPT_STATUS__OUTPUT_STREAM_2_INTERRUPT_STATUS_MASK 0x4 |
11452 | #define INTERRUPT_STATUS__OUTPUT_STREAM_2_INTERRUPT_STATUS__SHIFT 0x2 |
11453 | #define INTERRUPT_STATUS__OUTPUT_STREAM_3_INTERRUPT_STATUS_MASK 0x8 |
11454 | #define INTERRUPT_STATUS__OUTPUT_STREAM_3_INTERRUPT_STATUS__SHIFT 0x3 |
11455 | #define INTERRUPT_STATUS__OUTPUT_STREAM_4_INTERRUPT_STATUS_MASK 0x10 |
11456 | #define INTERRUPT_STATUS__OUTPUT_STREAM_4_INTERRUPT_STATUS__SHIFT 0x4 |
11457 | #define INTERRUPT_STATUS__OUTPUT_STREAM_5_INTERRUPT_STATUS_MASK 0x20 |
11458 | #define INTERRUPT_STATUS__OUTPUT_STREAM_5_INTERRUPT_STATUS__SHIFT 0x5 |
11459 | #define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000 |
11460 | #define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e |
11461 | #define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000 |
11462 | #define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f |
11463 | #define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xffffffff |
11464 | #define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0 |
11465 | #define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x1 |
11466 | #define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0 |
11467 | #define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x2 |
11468 | #define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1 |
11469 | #define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x4 |
11470 | #define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2 |
11471 | #define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x8 |
11472 | #define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3 |
11473 | #define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x10 |
11474 | #define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4 |
11475 | #define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x20 |
11476 | #define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5 |
11477 | #define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f |
11478 | #define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 |
11479 | #define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xffffff80 |
11480 | #define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7 |
11481 | #define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xffffffff |
11482 | #define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0 |
11483 | #define CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0xff |
11484 | #define CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 |
11485 | #define CORB_READ_POINTER__CORB_READ_POINTER_MASK 0xff |
11486 | #define CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 |
11487 | #define CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000 |
11488 | #define CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf |
11489 | #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x1 |
11490 | #define CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 |
11491 | #define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x2 |
11492 | #define CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 |
11493 | #define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x1 |
11494 | #define CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 |
11495 | #define CORB_SIZE__CORB_SIZE_MASK 0x3 |
11496 | #define CORB_SIZE__CORB_SIZE__SHIFT 0x0 |
11497 | #define CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0xf0 |
11498 | #define CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 |
11499 | #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7f |
11500 | #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 |
11501 | #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xffffff80 |
11502 | #define RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 |
11503 | #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff |
11504 | #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 |
11505 | #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0xff |
11506 | #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 |
11507 | #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000 |
11508 | #define RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf |
11509 | #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0xff |
11510 | #define RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 |
11511 | #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x1 |
11512 | #define RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 |
11513 | #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2 |
11514 | #define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 |
11515 | #define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x4 |
11516 | #define RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 |
11517 | #define RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x1 |
11518 | #define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 |
11519 | #define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x4 |
11520 | #define RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 |
11521 | #define RIRB_SIZE__RIRB_SIZE_MASK 0x3 |
11522 | #define RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 |
11523 | #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0 |
11524 | #define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 |
11525 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0xfffffff |
11526 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 |
11527 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xf0000000 |
11528 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c |
11529 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff |
11530 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
11531 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff |
11532 | #define IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
11533 | #define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xffffffff |
11534 | #define IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 |
11535 | #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x1 |
11536 | #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 |
11537 | #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x2 |
11538 | #define IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 |
11539 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x1 |
11540 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 |
11541 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x7e |
11542 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 |
11543 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xffffff80 |
11544 | #define DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 |
11545 | #define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xffffffff |
11546 | #define DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 |
11547 | #define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xffffffff |
11548 | #define WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 |
11549 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x1 |
11550 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 |
11551 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x2 |
11552 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 |
11553 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x4 |
11554 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 |
11555 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x8 |
11556 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 |
11557 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x10 |
11558 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 |
11559 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x30000 |
11560 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 |
11561 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x40000 |
11562 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 |
11563 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0xf00000 |
11564 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 |
11565 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x4000000 |
11566 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a |
11567 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x8000000 |
11568 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b |
11569 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000 |
11570 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c |
11571 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000 |
11572 | #define OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d |
11573 | #define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xffffffff |
11574 | #define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 |
11575 | #define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xffffffff |
11576 | #define OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 |
11577 | #define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0xff |
11578 | #define OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 |
11579 | #define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xffff |
11580 | #define OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 |
11581 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf |
11582 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
11583 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x70 |
11584 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
11585 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 |
11586 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
11587 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 |
11588 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
11589 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 |
11590 | #define OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
11591 | #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x7f |
11592 | #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 |
11593 | #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xffffff80 |
11594 | #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 |
11595 | #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xffffffff |
11596 | #define OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 |
11597 | #define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xffffffff |
11598 | #define OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 |
11599 | #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0xffff |
11600 | #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
11601 | #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xffffffff |
11602 | #define AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 |
11603 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 |
11604 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
11605 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 |
11606 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
11607 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 |
11608 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
11609 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 |
11610 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
11611 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 |
11612 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
11613 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 |
11614 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
11615 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 |
11616 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
11617 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 |
11618 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
11619 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 |
11620 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
11621 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 |
11622 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
11623 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 |
11624 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
11625 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 |
11626 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
11627 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 |
11628 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
11629 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 |
11630 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
11631 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff |
11632 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
11633 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 |
11634 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
11635 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff |
11636 | #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
11637 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf |
11638 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
11639 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 |
11640 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
11641 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 |
11642 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
11643 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 |
11644 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
11645 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 |
11646 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
11647 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 |
11648 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
11649 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x8000 |
11650 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf |
11651 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf |
11652 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
11653 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 |
11654 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
11655 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 |
11656 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
11657 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 |
11658 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
11659 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 |
11660 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
11661 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 |
11662 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
11663 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 |
11664 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
11665 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 |
11666 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
11667 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 |
11668 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
11669 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 |
11670 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
11671 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 |
11672 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
11673 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 |
11674 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
11675 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x7f |
11676 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 |
11677 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x80 |
11678 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 |
11679 | #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 |
11680 | #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 |
11681 | #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 |
11682 | #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 |
11683 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff |
11684 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 |
11685 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 |
11686 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 |
11687 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 |
11688 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 |
11689 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 |
11690 | #define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 |
11691 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 |
11692 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
11693 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 |
11694 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
11695 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 |
11696 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
11697 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 |
11698 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
11699 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 |
11700 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
11701 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 |
11702 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
11703 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 |
11704 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
11705 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 |
11706 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
11707 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 |
11708 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
11709 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 |
11710 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
11711 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 |
11712 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
11713 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 |
11714 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
11715 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 |
11716 | #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
11717 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 |
11718 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
11719 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 |
11720 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
11721 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 |
11722 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
11723 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 |
11724 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
11725 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 |
11726 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
11727 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 |
11728 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
11729 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 |
11730 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
11731 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 |
11732 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
11733 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 |
11734 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
11735 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 |
11736 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
11737 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 |
11738 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
11739 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffff |
11740 | #define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 |
11741 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffff |
11742 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 |
11743 | #define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 |
11744 | #define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 |
11745 | #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f |
11746 | #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
11747 | #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 |
11748 | #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
11749 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff |
11750 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
11751 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000 |
11752 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f |
11753 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf |
11754 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
11755 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 |
11756 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
11757 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 |
11758 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
11759 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 |
11760 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
11761 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 |
11762 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
11763 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 |
11764 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
11765 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 |
11766 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
11767 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 |
11768 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
11769 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0xf |
11770 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 |
11771 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0xf0 |
11772 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 |
11773 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0xf |
11774 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 |
11775 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0xf0 |
11776 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 |
11777 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x3f |
11778 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 |
11779 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0xc0 |
11780 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 |
11781 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x7f |
11782 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 |
11783 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x100 |
11784 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 |
11785 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x200 |
11786 | #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 |
11787 | #define 0xfc00 |
11788 | #define 0xa |
11789 | #define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0xff |
11790 | #define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 |
11791 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x78 |
11792 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 |
11793 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x80 |
11794 | #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 |
11795 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x7 |
11796 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 |
11797 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x78 |
11798 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 |
11799 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11800 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11801 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11802 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11803 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11804 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11805 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffff |
11806 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 |
11807 | #define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 |
11808 | #define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 |
11809 | #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11810 | #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11811 | #define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11812 | #define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11813 | #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11814 | #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11815 | #define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 |
11816 | #define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 |
11817 | #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11818 | #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11819 | #define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11820 | #define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11821 | #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11822 | #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11823 | #define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 |
11824 | #define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 |
11825 | #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11826 | #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11827 | #define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11828 | #define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11829 | #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11830 | #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11831 | #define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 |
11832 | #define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 |
11833 | #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11834 | #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11835 | #define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11836 | #define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11837 | #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11838 | #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11839 | #define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 |
11840 | #define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 |
11841 | #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11842 | #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11843 | #define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11844 | #define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11845 | #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11846 | #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11847 | #define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 |
11848 | #define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 |
11849 | #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11850 | #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11851 | #define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11852 | #define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11853 | #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11854 | #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11855 | #define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 |
11856 | #define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 |
11857 | #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11858 | #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11859 | #define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11860 | #define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11861 | #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11862 | #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11863 | #define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 |
11864 | #define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 |
11865 | #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11866 | #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11867 | #define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11868 | #define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11869 | #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11870 | #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11871 | #define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 |
11872 | #define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 |
11873 | #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11874 | #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11875 | #define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11876 | #define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11877 | #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11878 | #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11879 | #define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 |
11880 | #define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 |
11881 | #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11882 | #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11883 | #define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11884 | #define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11885 | #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11886 | #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11887 | #define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 |
11888 | #define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 |
11889 | #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11890 | #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11891 | #define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11892 | #define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11893 | #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11894 | #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11895 | #define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 |
11896 | #define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 |
11897 | #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11898 | #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11899 | #define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11900 | #define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11901 | #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11902 | #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11903 | #define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 |
11904 | #define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 |
11905 | #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11906 | #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11907 | #define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11908 | #define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11909 | #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11910 | #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11911 | #define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 |
11912 | #define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 |
11913 | #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 |
11914 | #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
11915 | #define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
11916 | #define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
11917 | #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
11918 | #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
11919 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 |
11920 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 |
11921 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 |
11922 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 |
11923 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 |
11924 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 |
11925 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x1 |
11926 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 |
11927 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x2 |
11928 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 |
11929 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf0 |
11930 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 |
11931 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x1 |
11932 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 |
11933 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x2 |
11934 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 |
11935 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf0 |
11936 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 |
11937 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1 |
11938 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 |
11939 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2 |
11940 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 |
11941 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0 |
11942 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 |
11943 | #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff |
11944 | #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 |
11945 | #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 |
11946 | #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 |
11947 | #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x1 |
11948 | #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 |
11949 | #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x10 |
11950 | #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 |
11951 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0xff |
11952 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 |
11953 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffff |
11954 | #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 |
11955 | #define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0xffff |
11956 | #define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 |
11957 | #define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0xffff |
11958 | #define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 |
11959 | #define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0xff |
11960 | #define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 |
11961 | #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffff |
11962 | #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 |
11963 | #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffff |
11964 | #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 |
11965 | #define SINK_DESCRIPTION0__DESCRIPTION_MASK 0xff |
11966 | #define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 |
11967 | #define SINK_DESCRIPTION1__DESCRIPTION_MASK 0xff |
11968 | #define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 |
11969 | #define SINK_DESCRIPTION2__DESCRIPTION_MASK 0xff |
11970 | #define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 |
11971 | #define SINK_DESCRIPTION3__DESCRIPTION_MASK 0xff |
11972 | #define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 |
11973 | #define SINK_DESCRIPTION4__DESCRIPTION_MASK 0xff |
11974 | #define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 |
11975 | #define SINK_DESCRIPTION5__DESCRIPTION_MASK 0xff |
11976 | #define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 |
11977 | #define SINK_DESCRIPTION6__DESCRIPTION_MASK 0xff |
11978 | #define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 |
11979 | #define SINK_DESCRIPTION7__DESCRIPTION_MASK 0xff |
11980 | #define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 |
11981 | #define SINK_DESCRIPTION8__DESCRIPTION_MASK 0xff |
11982 | #define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 |
11983 | #define SINK_DESCRIPTION9__DESCRIPTION_MASK 0xff |
11984 | #define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 |
11985 | #define SINK_DESCRIPTION10__DESCRIPTION_MASK 0xff |
11986 | #define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 |
11987 | #define SINK_DESCRIPTION11__DESCRIPTION_MASK 0xff |
11988 | #define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 |
11989 | #define SINK_DESCRIPTION12__DESCRIPTION_MASK 0xff |
11990 | #define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 |
11991 | #define SINK_DESCRIPTION13__DESCRIPTION_MASK 0xff |
11992 | #define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 |
11993 | #define SINK_DESCRIPTION14__DESCRIPTION_MASK 0xff |
11994 | #define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 |
11995 | #define SINK_DESCRIPTION15__DESCRIPTION_MASK 0xff |
11996 | #define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 |
11997 | #define SINK_DESCRIPTION16__DESCRIPTION_MASK 0xff |
11998 | #define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 |
11999 | #define SINK_DESCRIPTION17__DESCRIPTION_MASK 0xff |
12000 | #define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 |
12001 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x1 |
12002 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
12003 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x2 |
12004 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 |
12005 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 |
12006 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
12007 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x1 |
12008 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 |
12009 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x2 |
12010 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 |
12011 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xf0 |
12012 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 |
12013 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x1 |
12014 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 |
12015 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x2 |
12016 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 |
12017 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0xf0 |
12018 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 |
12019 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x1 |
12020 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 |
12021 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x2 |
12022 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 |
12023 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0 |
12024 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 |
12025 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 |
12026 | #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 |
12027 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 |
12028 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 |
12029 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c |
12030 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 |
12031 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 |
12032 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 |
12033 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 |
12034 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 |
12035 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 |
12036 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 |
12037 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 |
12038 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 |
12039 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f |
12040 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 |
12041 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 |
12042 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 |
12043 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf |
12044 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 |
12045 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 |
12046 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 |
12047 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf |
12048 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 |
12049 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 |
12050 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 |
12051 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 |
12052 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 |
12053 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 |
12054 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 |
12055 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf |
12056 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 |
12057 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 |
12058 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 |
12059 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf |
12060 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
12061 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 |
12062 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
12063 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf |
12064 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 |
12065 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 |
12066 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 |
12067 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf |
12068 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 |
12069 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 |
12070 | #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 |
12071 | #define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff |
12072 | #define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 |
12073 | #define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 |
12074 | #define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 |
12075 | #define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x1 |
12076 | #define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 |
12077 | #define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x10 |
12078 | #define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 |
12079 | #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0xffff |
12080 | #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 |
12081 | #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000 |
12082 | #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 |
12083 | #define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x300 |
12084 | #define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 |
12085 | #define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x30 |
12086 | #define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x4 |
12087 | #define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffff |
12088 | #define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 |
12089 | #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x3 |
12090 | #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 |
12091 | #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x30 |
12092 | #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 |
12093 | #define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x10000 |
12094 | #define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 |
12095 | #define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x20000 |
12096 | #define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 |
12097 | #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x3 |
12098 | #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 |
12099 | #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x30 |
12100 | #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 |
12101 | #define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x1 |
12102 | #define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 |
12103 | #define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x10 |
12104 | #define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 |
12105 | #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x1 |
12106 | #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 |
12107 | #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x10 |
12108 | #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 |
12109 | #define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffff |
12110 | #define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x0 |
12111 | #define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x1 |
12112 | #define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x0 |
12113 | #define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x6 |
12114 | #define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 |
12115 | #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xffff |
12116 | #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 |
12117 | #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000 |
12118 | #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 |
12119 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0xff |
12120 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 |
12121 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x100 |
12122 | #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 |
12123 | #define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffff |
12124 | #define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x0 |
12125 | #define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x1 |
12126 | #define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 |
12127 | #define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 |
12128 | #define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 |
12129 | #define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 |
12130 | #define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 |
12131 | #define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 |
12132 | #define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc |
12133 | #define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff |
12134 | #define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 |
12135 | #define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff |
12136 | #define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 |
12137 | #define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x1 |
12138 | #define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 |
12139 | #define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 |
12140 | #define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 |
12141 | #define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 |
12142 | #define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 |
12143 | #define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xffffffff |
12144 | #define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 |
12145 | #define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff |
12146 | #define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 |
12147 | #define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff |
12148 | #define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 |
12149 | #define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff |
12150 | #define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 |
12151 | #define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff |
12152 | #define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 |
12153 | #define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff |
12154 | #define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 |
12155 | #define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff |
12156 | #define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 |
12157 | #define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff |
12158 | #define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 |
12159 | #define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff |
12160 | #define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 |
12161 | #define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x1 |
12162 | #define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 |
12163 | #define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x10 |
12164 | #define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 |
12165 | #define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x700 |
12166 | #define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 |
12167 | #define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x1000 |
12168 | #define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc |
12169 | #define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xffffffff |
12170 | #define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 |
12171 | #define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0xffff |
12172 | #define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 |
12173 | #define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x1 |
12174 | #define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 |
12175 | #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x10 |
12176 | #define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 |
12177 | #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x700 |
12178 | #define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 |
12179 | #define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xffffffff |
12180 | #define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 |
12181 | #define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xffffffff |
12182 | #define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 |
12183 | #define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xffffffff |
12184 | #define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 |
12185 | #define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xffffffff |
12186 | #define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 |
12187 | #define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xffffffff |
12188 | #define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 |
12189 | #define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xffffffff |
12190 | #define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 |
12191 | #define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xffffffff |
12192 | #define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 |
12193 | #define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xffffffff |
12194 | #define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 |
12195 | #define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xffffffff |
12196 | #define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 |
12197 | #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0xff |
12198 | #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x0 |
12199 | #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x100 |
12200 | #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
12201 | #define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffff |
12202 | #define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x0 |
12203 | #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0xff |
12204 | #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 |
12205 | #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x100 |
12206 | #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 |
12207 | #define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffff |
12208 | #define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 |
12209 | #define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x7f |
12210 | #define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 |
12211 | #define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x7f00 |
12212 | #define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 |
12213 | #define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0xff0000 |
12214 | #define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 |
12215 | #define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x1 |
12216 | #define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 |
12217 | #define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffff |
12218 | #define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 |
12219 | #define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffff |
12220 | #define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 |
12221 | #define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffff |
12222 | #define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 |
12223 | #define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffff |
12224 | #define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 |
12225 | #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x3fff |
12226 | #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 |
12227 | #define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffff |
12228 | #define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 |
12229 | #define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 |
12230 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 |
12231 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
12232 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 |
12233 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
12234 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 |
12235 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
12236 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 |
12237 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
12238 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x10 |
12239 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 |
12240 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 |
12241 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
12242 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 |
12243 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
12244 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 |
12245 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
12246 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 |
12247 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
12248 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 |
12249 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
12250 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 |
12251 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
12252 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 |
12253 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
12254 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 |
12255 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
12256 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 |
12257 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
12258 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0xf |
12259 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 |
12260 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x70 |
12261 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 |
12262 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x700 |
12263 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 |
12264 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800 |
12265 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb |
12266 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000 |
12267 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe |
12268 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x8000 |
12269 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf |
12270 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0xf |
12271 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 |
12272 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0xf0 |
12273 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 |
12274 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x1 |
12275 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 |
12276 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x2 |
12277 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 |
12278 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x4 |
12279 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 |
12280 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x8 |
12281 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 |
12282 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x10 |
12283 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 |
12284 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x20 |
12285 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 |
12286 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x40 |
12287 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 |
12288 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x80 |
12289 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 |
12290 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x7f00 |
12291 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 |
12292 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x800000 |
12293 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 |
12294 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffff |
12295 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 |
12296 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0xfff |
12297 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 |
12298 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x1f0000 |
12299 | #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 |
12300 | #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x3 |
12301 | #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 |
12302 | #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x700000 |
12303 | #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 |
12304 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0xff |
12305 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 |
12306 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x1 |
12307 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x0 |
12308 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK 0x2 |
12309 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT 0x1 |
12310 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK 0x4 |
12311 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT 0x2 |
12312 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK 0x70 |
12313 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT 0x4 |
12314 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG_MASK 0xffffffff |
12315 | #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG__PRESENTATION_TIME_OFFSET_DEBUG__SHIFT 0x0 |
12316 | #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK 0xffffffff |
12317 | #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT 0x0 |
12318 | #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK 0xffffffff |
12319 | #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT 0x0 |
12320 | #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK 0xffffffff |
12321 | #define AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT 0x0 |
12322 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x1 |
12323 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 |
12324 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x2 |
12325 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 |
12326 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x4 |
12327 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 |
12328 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x8 |
12329 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 |
12330 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x20 |
12331 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 |
12332 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x40 |
12333 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 |
12334 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x80 |
12335 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 |
12336 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x100 |
12337 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 |
12338 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x200 |
12339 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 |
12340 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x400 |
12341 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa |
12342 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x800 |
12343 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb |
12344 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0xf0000 |
12345 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 |
12346 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0xf00000 |
12347 | #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 |
12348 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x1 |
12349 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 |
12350 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x2 |
12351 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 |
12352 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x4 |
12353 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 |
12354 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x8 |
12355 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 |
12356 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x10 |
12357 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 |
12358 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x20 |
12359 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 |
12360 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x40 |
12361 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 |
12362 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x80 |
12363 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 |
12364 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0xff00 |
12365 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 |
12366 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x10000 |
12367 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 |
12368 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x1000000 |
12369 | #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 |
12370 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x3f |
12371 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 |
12372 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x80 |
12373 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 |
12374 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffff |
12375 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 |
12376 | #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x40 |
12377 | #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 |
12378 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x7f |
12379 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 |
12380 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0xff00 |
12381 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 |
12382 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x10000 |
12383 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 |
12384 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x20000 |
12385 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 |
12386 | #define 0xfc0000 |
12387 | #define 0x12 |
12388 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000 |
12389 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b |
12390 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000 |
12391 | #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f |
12392 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x7 |
12393 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 |
12394 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0xff00 |
12395 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
12396 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
12397 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
12398 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000 |
12399 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 |
12400 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x7 |
12401 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 |
12402 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0xff00 |
12403 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
12404 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
12405 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
12406 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x7 |
12407 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 |
12408 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0xff00 |
12409 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
12410 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
12411 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
12412 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x7 |
12413 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 |
12414 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0xff00 |
12415 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
12416 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
12417 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
12418 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x7 |
12419 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 |
12420 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0xff00 |
12421 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
12422 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
12423 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
12424 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x7 |
12425 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 |
12426 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0xff00 |
12427 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
12428 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
12429 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
12430 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x7 |
12431 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 |
12432 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0xff00 |
12433 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
12434 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
12435 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
12436 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x7 |
12437 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 |
12438 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0xff00 |
12439 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
12440 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
12441 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
12442 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x7 |
12443 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 |
12444 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0xff00 |
12445 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
12446 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
12447 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
12448 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x7 |
12449 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 |
12450 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0xff00 |
12451 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
12452 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
12453 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
12454 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x7 |
12455 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 |
12456 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0xff00 |
12457 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
12458 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
12459 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
12460 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x7 |
12461 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 |
12462 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0xff00 |
12463 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
12464 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
12465 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
12466 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x7 |
12467 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 |
12468 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0xff00 |
12469 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
12470 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
12471 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
12472 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x7 |
12473 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 |
12474 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0xff00 |
12475 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 |
12476 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0xff0000 |
12477 | #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 |
12478 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x1 |
12479 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 |
12480 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x2 |
12481 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 |
12482 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0xf0 |
12483 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 |
12484 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x100 |
12485 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 |
12486 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x200 |
12487 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 |
12488 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0xf000 |
12489 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc |
12490 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x10000 |
12491 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 |
12492 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x20000 |
12493 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 |
12494 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0xf00000 |
12495 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 |
12496 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x1000000 |
12497 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 |
12498 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x2000000 |
12499 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 |
12500 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000 |
12501 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c |
12502 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x1 |
12503 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 |
12504 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x2 |
12505 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 |
12506 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0xf0 |
12507 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 |
12508 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x100 |
12509 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 |
12510 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x200 |
12511 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 |
12512 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0xf000 |
12513 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc |
12514 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x10000 |
12515 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 |
12516 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x20000 |
12517 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 |
12518 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0xf00000 |
12519 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 |
12520 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x1000000 |
12521 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 |
12522 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x2000000 |
12523 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 |
12524 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000 |
12525 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c |
12526 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x1 |
12527 | #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 |
12528 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0xff |
12529 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 |
12530 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0xff00 |
12531 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 |
12532 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x1 |
12533 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 |
12534 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x10 |
12535 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 |
12536 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0xffff |
12537 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 |
12538 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000 |
12539 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 |
12540 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0xff |
12541 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 |
12542 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffff |
12543 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 |
12544 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffff |
12545 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 |
12546 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0xff |
12547 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 |
12548 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0xff00 |
12549 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 |
12550 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0xff0000 |
12551 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 |
12552 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000 |
12553 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 |
12554 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0xff |
12555 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 |
12556 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0xff00 |
12557 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 |
12558 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0xff0000 |
12559 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 |
12560 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000 |
12561 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 |
12562 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0xff |
12563 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 |
12564 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0xff00 |
12565 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 |
12566 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0xff0000 |
12567 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 |
12568 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000 |
12569 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 |
12570 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0xff |
12571 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 |
12572 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0xff00 |
12573 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 |
12574 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0xff0000 |
12575 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 |
12576 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000 |
12577 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 |
12578 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0xff |
12579 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 |
12580 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0xff00 |
12581 | #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 |
12582 | #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x1 |
12583 | #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 |
12584 | #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x10 |
12585 | #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 |
12586 | #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000 |
12587 | #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f |
12588 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x3ffffff |
12589 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 |
12590 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000 |
12591 | #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c |
12592 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0xf |
12593 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 |
12594 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0xf0 |
12595 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 |
12596 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0xf00 |
12597 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 |
12598 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0xf000 |
12599 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc |
12600 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0xf0000 |
12601 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 |
12602 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0xf00000 |
12603 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 |
12604 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000 |
12605 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 |
12606 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000 |
12607 | #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e |
12608 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x3 |
12609 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 |
12610 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x3c |
12611 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 |
12612 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x3 |
12613 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 |
12614 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x4 |
12615 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 |
12616 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x78 |
12617 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 |
12618 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x80 |
12619 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 |
12620 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x3f |
12621 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 |
12622 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x40 |
12623 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 |
12624 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0xf |
12625 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 |
12626 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x10 |
12627 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 |
12628 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0xf |
12629 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 |
12630 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x10 |
12631 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 |
12632 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x60 |
12633 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 |
12634 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x80 |
12635 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 |
12636 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0xf |
12637 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 |
12638 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0xf0 |
12639 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 |
12640 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0xf |
12641 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 |
12642 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0xf0 |
12643 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 |
12644 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0xf |
12645 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 |
12646 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0xf0 |
12647 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 |
12648 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0xf |
12649 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 |
12650 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0xf0 |
12651 | #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 |
12652 | #define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffff |
12653 | #define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 |
12654 | #define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x1 |
12655 | #define AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 |
12656 | #define BLND_CONTROL__BLND_MODE_MASK 0x300 |
12657 | #define BLND_CONTROL__BLND_MODE__SHIFT 0x8 |
12658 | #define BLND_CONTROL__BLND_ALPHA_MODE_MASK 0x30000 |
12659 | #define BLND_CONTROL__BLND_ALPHA_MODE__SHIFT 0x10 |
12660 | #define BLND_CONTROL__BLND_MULTIPLIED_MODE_MASK 0x100000 |
12661 | #define BLND_CONTROL__BLND_MULTIPLIED_MODE__SHIFT 0x14 |
12662 | #define BLND_CONTROL__BLND_GLOBAL_ALPHA_MASK 0xff000000 |
12663 | #define BLND_CONTROL__BLND_GLOBAL_ALPHA__SHIFT 0x18 |
12664 | #define SM_CONTROL2__SM_MODE_MASK 0x7 |
12665 | #define SM_CONTROL2__SM_MODE__SHIFT 0x0 |
12666 | #define SM_CONTROL2__SM_FRAME_ALTERNATE_MASK 0x10 |
12667 | #define SM_CONTROL2__SM_FRAME_ALTERNATE__SHIFT 0x4 |
12668 | #define SM_CONTROL2__SM_FIELD_ALTERNATE_MASK 0x20 |
12669 | #define SM_CONTROL2__SM_FIELD_ALTERNATE__SHIFT 0x5 |
12670 | #define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL_MASK 0x300 |
12671 | #define SM_CONTROL2__SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 |
12672 | #define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL_MASK 0x30000 |
12673 | #define SM_CONTROL2__SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 |
12674 | #define SM_CONTROL2__SM_CURRENT_FRAME_POL_MASK 0x1000000 |
12675 | #define SM_CONTROL2__SM_CURRENT_FRAME_POL__SHIFT 0x18 |
12676 | #define PTI_CONTROL__PTI_ENABLE_MASK 0x1 |
12677 | #define PTI_CONTROL__PTI_ENABLE__SHIFT 0x0 |
12678 | #define PTI_CONTROL__PTI_NEW_PIXEL_GAP_MASK 0x30 |
12679 | #define PTI_CONTROL__PTI_NEW_PIXEL_GAP__SHIFT 0x4 |
12680 | #define PTI_CONTROL__BLND_NEW_PIXEL_MODE_MASK 0x40 |
12681 | #define PTI_CONTROL__BLND_NEW_PIXEL_MODE__SHIFT 0x6 |
12682 | #define BLND_UPDATE__BLND_UPDATE_PENDING_MASK 0x1 |
12683 | #define BLND_UPDATE__BLND_UPDATE_PENDING__SHIFT 0x0 |
12684 | #define BLND_UPDATE__BLND_UPDATE_TAKEN_MASK 0x100 |
12685 | #define BLND_UPDATE__BLND_UPDATE_TAKEN__SHIFT 0x8 |
12686 | #define BLND_UPDATE__BLND_UPDATE_LOCK_MASK 0x10000 |
12687 | #define BLND_UPDATE__BLND_UPDATE_LOCK__SHIFT 0x10 |
12688 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED_MASK 0x1 |
12689 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_OCCURED__SHIFT 0x0 |
12690 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK_MASK 0x100 |
12691 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_ACK__SHIFT 0x8 |
12692 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK_MASK 0x1000 |
12693 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_MASK__SHIFT 0xc |
12694 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX_MASK 0x30000 |
12695 | #define BLND_UNDERFLOW_INTERRUPT__BLND_UNDERFLOW_INT_PIPE_INDEX__SHIFT 0x10 |
12696 | #define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK_MASK 0x1 |
12697 | #define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_V_UPDATE_LOCK__SHIFT 0x0 |
12698 | #define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_MASK 0x2 |
12699 | #define BLND_V_UPDATE_LOCK__BLND_DCP_GRPH_SURF_V_UPDATE_LOCK__SHIFT 0x1 |
12700 | #define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK_MASK 0x100 |
12701 | #define BLND_V_UPDATE_LOCK__BLND_DCP_OVL_V_UPDATE_LOCK__SHIFT 0x8 |
12702 | #define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK_MASK 0x10000 |
12703 | #define BLND_V_UPDATE_LOCK__BLND_DCP_CUR_V_UPDATE_LOCK__SHIFT 0x10 |
12704 | #define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK_MASK 0x1000000 |
12705 | #define BLND_V_UPDATE_LOCK__BLND_DCP_CUR2_V_UPDATE_LOCK__SHIFT 0x18 |
12706 | #define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK_MASK 0x10000000 |
12707 | #define BLND_V_UPDATE_LOCK__BLND_SCL_V_UPDATE_LOCK__SHIFT 0x1c |
12708 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_UPDATE_PENDING_MASK 0x1 |
12709 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_UPDATE_PENDING__SHIFT 0x0 |
12710 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_UPDATE_PENDING_MASK 0x2 |
12711 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_UPDATE_PENDING__SHIFT 0x1 |
12712 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_SURF_UPDATE_PENDING_MASK 0x4 |
12713 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDc_GRPH_SURF_UPDATE_PENDING__SHIFT 0x2 |
12714 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_SURF_UPDATE_PENDING_MASK 0x8 |
12715 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDo_GRPH_SURF_UPDATE_PENDING__SHIFT 0x3 |
12716 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDc_OVL_UPDATE_PENDING_MASK 0x10 |
12717 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDc_OVL_UPDATE_PENDING__SHIFT 0x4 |
12718 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDo_OVL_UPDATE_PENDING_MASK 0x20 |
12719 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDo_OVL_UPDATE_PENDING__SHIFT 0x5 |
12720 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDc_CUR_UPDATE_PENDING_MASK 0x40 |
12721 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDc_CUR_UPDATE_PENDING__SHIFT 0x6 |
12722 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDo_CUR_UPDATE_PENDING_MASK 0x80 |
12723 | #define BLND_REG_UPDATE_STATUS__DCP_BLNDo_CUR_UPDATE_PENDING__SHIFT 0x7 |
12724 | #define BLND_REG_UPDATE_STATUS__SCL_BLNDc_UPDATE_PENDING_MASK 0x100 |
12725 | #define BLND_REG_UPDATE_STATUS__SCL_BLNDc_UPDATE_PENDING__SHIFT 0x8 |
12726 | #define BLND_REG_UPDATE_STATUS__SCL_BLNDo_UPDATE_PENDING_MASK 0x200 |
12727 | #define BLND_REG_UPDATE_STATUS__SCL_BLNDo_UPDATE_PENDING__SHIFT 0x9 |
12728 | #define BLND_DEBUG__BLND_CNV_MUX_SELECT_MASK 0x1 |
12729 | #define BLND_DEBUG__BLND_CNV_MUX_SELECT__SHIFT 0x0 |
12730 | #define BLND_DEBUG__BLND_DEBUG_MASK 0xfffffffe |
12731 | #define BLND_DEBUG__BLND_DEBUG__SHIFT 0x1 |
12732 | #define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX_MASK 0xff |
12733 | #define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_INDEX__SHIFT 0x0 |
12734 | #define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN_MASK 0x100 |
12735 | #define BLND_TEST_DEBUG_INDEX__BLND_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
12736 | #define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA_MASK 0xffffffff |
12737 | #define BLND_TEST_DEBUG_DATA__BLND_TEST_DEBUG_DATA__SHIFT 0x0 |
12738 | #define SI_ENABLE__SI_ENABLE_MASK 0x1 |
12739 | #define SI_ENABLE__SI_ENABLE__SHIFT 0x0 |
12740 | #define SI_EC_CONFIG__DISPCLK_R_SCANIN_GATE_DIS_MASK 0x1 |
12741 | #define SI_EC_CONFIG__DISPCLK_R_SCANIN_GATE_DIS__SHIFT 0x0 |
12742 | #define SI_EC_CONFIG__DISPCLK_G_SCANIN_GATE_DIS_MASK 0x2 |
12743 | #define SI_EC_CONFIG__DISPCLK_G_SCANIN_GATE_DIS__SHIFT 0x1 |
12744 | #define SI_EC_CONFIG__DISPCLK_G_SISCL_GATE_DIS_MASK 0x4 |
12745 | #define SI_EC_CONFIG__DISPCLK_G_SISCL_GATE_DIS__SHIFT 0x2 |
12746 | #define SI_EC_CONFIG__DISPCLK_R_SCANIN_RAMP_DIS_MASK 0x8 |
12747 | #define SI_EC_CONFIG__DISPCLK_R_SCANIN_RAMP_DIS__SHIFT 0x3 |
12748 | #define SI_EC_CONFIG__DISPCLK_G_SCANIN_RAMP_DIS_MASK 0x10 |
12749 | #define SI_EC_CONFIG__DISPCLK_G_SCANIN_RAMP_DIS__SHIFT 0x4 |
12750 | #define SI_EC_CONFIG__DISPCLK_G_SISCL_RAMP_DIS_MASK 0x20 |
12751 | #define SI_EC_CONFIG__DISPCLK_G_SISCL_RAMP_DIS__SHIFT 0x5 |
12752 | #define SI_EC_CONFIG__SI_LB_LS_DIS_MASK 0x40 |
12753 | #define SI_EC_CONFIG__SI_LB_LS_DIS__SHIFT 0x6 |
12754 | #define SI_EC_CONFIG__SI_LB_SD_DIS_MASK 0x80 |
12755 | #define SI_EC_CONFIG__SI_LB_SD_DIS__SHIFT 0x7 |
12756 | #define SI_EC_CONFIG__SI_LUT_LS_DIS_MASK 0x100 |
12757 | #define SI_EC_CONFIG__SI_LUT_LS_DIS__SHIFT 0x8 |
12758 | #define SI_EC_CONFIG__SCANIN_TEST_CLK_SEL_MASK 0xf000 |
12759 | #define SI_EC_CONFIG__SCANIN_TEST_CLK_SEL__SHIFT 0xc |
12760 | #define SI_EC_CONFIG__SI_RAM_PW_SAVE_MODE_MASK 0x800000 |
12761 | #define SI_EC_CONFIG__SI_RAM_PW_SAVE_MODE__SHIFT 0x17 |
12762 | #define SI_EC_CONFIG__LB_MEM_PWR_STATE_MASK 0x30000000 |
12763 | #define SI_EC_CONFIG__LB_MEM_PWR_STATE__SHIFT 0x1c |
12764 | #define SI_EC_CONFIG__LUT_MEM_PWR_STATE_MASK 0xc0000000 |
12765 | #define SI_EC_CONFIG__LUT_MEM_PWR_STATE__SHIFT 0x1e |
12766 | #define CNV_MODE__CNV_INPUT_SRC_SELECT_MASK 0x3 |
12767 | #define CNV_MODE__CNV_INPUT_SRC_SELECT__SHIFT 0x0 |
12768 | #define CNV_MODE__CNV_INPUT_PIPE_SELECT_MASK 0x1c |
12769 | #define CNV_MODE__CNV_INPUT_PIPE_SELECT__SHIFT 0x2 |
12770 | #define CNV_MODE__CNV_FRAME_COUNT_MASK 0x300 |
12771 | #define CNV_MODE__CNV_FRAME_COUNT__SHIFT 0x8 |
12772 | #define CNV_MODE__CNV_WINDOW_EN_MASK 0x1000 |
12773 | #define CNV_MODE__CNV_WINDOW_EN__SHIFT 0xc |
12774 | #define CNV_MODE__CNV_EYE_SELECTION_MASK 0x30000 |
12775 | #define CNV_MODE__CNV_EYE_SELECTION__SHIFT 0x10 |
12776 | #define CNV_MODE__CNV_STEREO_EYE_ORDER_MASK 0x40000 |
12777 | #define CNV_MODE__CNV_STEREO_EYE_ORDER__SHIFT 0x12 |
12778 | #define CNV_MODE__CNV_NEW_CONTENT_MASK 0x1000000 |
12779 | #define CNV_MODE__CNV_NEW_CONTENT__SHIFT 0x18 |
12780 | #define CNV_MODE__CNV_FRAME_EN_MASK 0x80000000 |
12781 | #define CNV_MODE__CNV_FRAME_EN__SHIFT 0x1f |
12782 | #define CNV_WINDOW_START__CNV_WINDOW_START_X_MASK 0xfff |
12783 | #define CNV_WINDOW_START__CNV_WINDOW_START_X__SHIFT 0x0 |
12784 | #define CNV_WINDOW_START__CNV_WINDOW_START_Y_MASK 0xfff0000 |
12785 | #define CNV_WINDOW_START__CNV_WINDOW_START_Y__SHIFT 0x10 |
12786 | #define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH_MASK 0xfff |
12787 | #define CNV_WINDOW_SIZE__CNV_WINDOW_WIDTH__SHIFT 0x0 |
12788 | #define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT_MASK 0xfff0000 |
12789 | #define CNV_WINDOW_SIZE__CNV_WINDOW_HEIGHT__SHIFT 0x10 |
12790 | #define CNV_UPDATE__CNV_UPDATE_PENDING_MASK 0x1 |
12791 | #define CNV_UPDATE__CNV_UPDATE_PENDING__SHIFT 0x0 |
12792 | #define CNV_UPDATE__CNV_UPDATE_TAKEN_MASK 0x100 |
12793 | #define CNV_UPDATE__CNV_UPDATE_TAKEN__SHIFT 0x8 |
12794 | #define CNV_UPDATE__CNV_UPDATE_LOCK_MASK 0x10000 |
12795 | #define CNV_UPDATE__CNV_UPDATE_LOCK__SHIFT 0x10 |
12796 | #define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH_MASK 0x7fff |
12797 | #define CNV_SOURCE_SIZE__CNV_SOURCE_WIDTH__SHIFT 0x0 |
12798 | #define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT_MASK 0x7fff0000 |
12799 | #define CNV_SOURCE_SIZE__CNV_SOURCE_HEIGHT__SHIFT 0x10 |
12800 | #define CNV_CSC_CONTROL__CNV_CSC_bypass_MASK 0x1 |
12801 | #define CNV_CSC_CONTROL__CNV_CSC_bypass__SHIFT 0x0 |
12802 | #define CNV_CSC_C11_C12__CNV_CSC_C11_MASK 0x1fff |
12803 | #define CNV_CSC_C11_C12__CNV_CSC_C11__SHIFT 0x0 |
12804 | #define CNV_CSC_C11_C12__CNV_CSC_C12_MASK 0x1fff0000 |
12805 | #define CNV_CSC_C11_C12__CNV_CSC_C12__SHIFT 0x10 |
12806 | #define CNV_CSC_C13_C14__CNV_CSC_C13_MASK 0x1fff |
12807 | #define CNV_CSC_C13_C14__CNV_CSC_C13__SHIFT 0x0 |
12808 | #define CNV_CSC_C13_C14__CNV_CSC_C14_MASK 0x7fff0000 |
12809 | #define CNV_CSC_C13_C14__CNV_CSC_C14__SHIFT 0x10 |
12810 | #define CNV_CSC_C21_C22__CNV_CSC_C21_MASK 0x1fff |
12811 | #define CNV_CSC_C21_C22__CNV_CSC_C21__SHIFT 0x0 |
12812 | #define CNV_CSC_C21_C22__CNV_CSC_C22_MASK 0x1fff0000 |
12813 | #define CNV_CSC_C21_C22__CNV_CSC_C22__SHIFT 0x10 |
12814 | #define CNV_CSC_C23_C24__CNV_CSC_C23_MASK 0x1fff |
12815 | #define CNV_CSC_C23_C24__CNV_CSC_C23__SHIFT 0x0 |
12816 | #define CNV_CSC_C23_C24__CNV_CSC_C24_MASK 0x7fff0000 |
12817 | #define CNV_CSC_C23_C24__CNV_CSC_C24__SHIFT 0x10 |
12818 | #define CNV_CSC_C31_C32__CNV_CSC_C31_MASK 0x1fff |
12819 | #define CNV_CSC_C31_C32__CNV_CSC_C31__SHIFT 0x0 |
12820 | #define CNV_CSC_C31_C32__CNV_CSC_C32_MASK 0x1fff0000 |
12821 | #define CNV_CSC_C31_C32__CNV_CSC_C32__SHIFT 0x10 |
12822 | #define CNV_CSC_C33_C34__CNV_CSC_C33_MASK 0x1fff |
12823 | #define CNV_CSC_C33_C34__CNV_CSC_C33__SHIFT 0x0 |
12824 | #define CNV_CSC_C33_C34__CNV_CSC_C34_MASK 0x7fff0000 |
12825 | #define CNV_CSC_C33_C34__CNV_CSC_C34__SHIFT 0x10 |
12826 | #define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R_MASK 0xffff |
12827 | #define CNV_CSC_ROUND_OFFSET_R__CNV_CSC_ROUND_OFFSET_R__SHIFT 0x0 |
12828 | #define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G_MASK 0xffff |
12829 | #define CNV_CSC_ROUND_OFFSET_G__CNV_CSC_ROUND_OFFSET_G__SHIFT 0x0 |
12830 | #define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B_MASK 0xffff |
12831 | #define CNV_CSC_ROUND_OFFSET_B__CNV_CSC_ROUND_OFFSET_B__SHIFT 0x0 |
12832 | #define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R_MASK 0xffff |
12833 | #define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_UPPER_R__SHIFT 0x0 |
12834 | #define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R_MASK 0xffff0000 |
12835 | #define CNV_CSC_CLAMP_R__CNV_CSC_CLAMP_LOWER_R__SHIFT 0x10 |
12836 | #define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G_MASK 0xffff |
12837 | #define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_UPPER_G__SHIFT 0x0 |
12838 | #define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G_MASK 0xffff0000 |
12839 | #define CNV_CSC_CLAMP_G__CNV_CSC_CLAMP_LOWER_G__SHIFT 0x10 |
12840 | #define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B_MASK 0xffff |
12841 | #define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_UPPER_B__SHIFT 0x0 |
12842 | #define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B_MASK 0xffff0000 |
12843 | #define CNV_CSC_CLAMP_B__CNV_CSC_CLAMP_LOWER_B__SHIFT 0x10 |
12844 | #define CNV_TEST_CNTL__CNV_TEST_CRC_EN_MASK 0x10 |
12845 | #define CNV_TEST_CNTL__CNV_TEST_CRC_EN__SHIFT 0x4 |
12846 | #define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN_MASK 0x100 |
12847 | #define CNV_TEST_CNTL__CNV_TEST_CRC_CONT_EN__SHIFT 0x8 |
12848 | #define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY_MASK 0x10000 |
12849 | #define CNV_TEST_CNTL__CNV_TEST_CRC_DE_ONLY__SHIFT 0x10 |
12850 | #define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK_MASK 0xffff |
12851 | #define CNV_TEST_CRC_RED__CNV_TEST_CRC_RED_MASK__SHIFT 0x0 |
12852 | #define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED_MASK 0xffff0000 |
12853 | #define CNV_TEST_CRC_RED__CNV_TEST_CRC_SIG_RED__SHIFT 0x10 |
12854 | #define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK_MASK 0xffff |
12855 | #define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_GREEN_MASK__SHIFT 0x0 |
12856 | #define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN_MASK 0xffff0000 |
12857 | #define CNV_TEST_CRC_GREEN__CNV_TEST_CRC_SIG_GREEN__SHIFT 0x10 |
12858 | #define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK_MASK 0xffff |
12859 | #define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_BLUE_MASK__SHIFT 0x0 |
12860 | #define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE_MASK 0xffff0000 |
12861 | #define CNV_TEST_CRC_BLUE__CNV_TEST_CRC_SIG_BLUE__SHIFT 0x10 |
12862 | #define SI_DEBUG_CTRL__SI_DEBUG_SEL_MASK 0x3 |
12863 | #define SI_DEBUG_CTRL__SI_DEBUG_SEL__SHIFT 0x0 |
12864 | #define SI_DBG_MODE__SI_DBG_MODE_EN_MASK 0x1 |
12865 | #define SI_DBG_MODE__SI_DBG_MODE_EN__SHIFT 0x0 |
12866 | #define SI_DBG_MODE__SI_DBG_DIN_FMT_MASK 0x2 |
12867 | #define SI_DBG_MODE__SI_DBG_DIN_FMT__SHIFT 0x1 |
12868 | #define SI_DBG_MODE__SI_DBG_36MODE_MASK 0x4 |
12869 | #define SI_DBG_MODE__SI_DBG_36MODE__SHIFT 0x2 |
12870 | #define SI_DBG_MODE__SI_DBG_CMAP_MASK 0x8 |
12871 | #define SI_DBG_MODE__SI_DBG_CMAP__SHIFT 0x3 |
12872 | #define SI_DBG_MODE__SI_DBG_PXLRATE_ERROR_MASK 0x100 |
12873 | #define SI_DBG_MODE__SI_DBG_PXLRATE_ERROR__SHIFT 0x8 |
12874 | #define SI_DBG_MODE__SI_DBG_SOURCE_WIDTH_MASK 0x7fff0000 |
12875 | #define SI_DBG_MODE__SI_DBG_SOURCE_WIDTH__SHIFT 0x10 |
12876 | #define SI_HARD_DEBUG__SI_HARD_DEBUG_MASK 0xffffffff |
12877 | #define SI_HARD_DEBUG__SI_HARD_DEBUG__SHIFT 0x0 |
12878 | #define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX_MASK 0xff |
12879 | #define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_INDEX__SHIFT 0x0 |
12880 | #define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN_MASK 0x100 |
12881 | #define CNV_TEST_DEBUG_INDEX__CNV_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
12882 | #define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA_MASK 0xffffffff |
12883 | #define CNV_TEST_DEBUG_DATA__CNV_TEST_DEBUG_DATA__SHIFT 0x0 |
12884 | #define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x7 |
12885 | #define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 |
12886 | #define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_PHASE_MASK 0xf00 |
12887 | #define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_PHASE__SHIFT 0x8 |
12888 | #define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_FILTER_TYPE_MASK 0x30000 |
12889 | #define SISCL_COEF_RAM_SELECT__SISCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 |
12890 | #define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x3fff |
12891 | #define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 |
12892 | #define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x8000 |
12893 | #define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf |
12894 | #define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3fff0000 |
12895 | #define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 |
12896 | #define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000 |
12897 | #define SISCL_COEF_RAM_TAP_DATA__SISCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f |
12898 | #define SISCL_MODE__SISCL_MODE_MASK 0x3 |
12899 | #define SISCL_MODE__SISCL_MODE__SHIFT 0x0 |
12900 | #define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_Y_RGB_MASK 0xf |
12901 | #define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_Y_RGB__SHIFT 0x0 |
12902 | #define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_CBCR_MASK 0xf0 |
12903 | #define SISCL_TAP_CONTROL__SISCL_V_NUM_OF_TAPS_CBCR__SHIFT 0x4 |
12904 | #define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_Y_RGB_MASK 0xf00 |
12905 | #define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_Y_RGB__SHIFT 0x8 |
12906 | #define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_CBCR_MASK 0xf000 |
12907 | #define SISCL_TAP_CONTROL__SISCL_H_NUM_OF_TAPS_CBCR__SHIFT 0xc |
12908 | #define SISCL_DEST_SIZE__SISCL_DEST_HEIGHT_MASK 0x7fff |
12909 | #define SISCL_DEST_SIZE__SISCL_DEST_HEIGHT__SHIFT 0x0 |
12910 | #define SISCL_DEST_SIZE__SISCL_DEST_WIDTH_MASK 0x7fff0000 |
12911 | #define SISCL_DEST_SIZE__SISCL_DEST_WIDTH__SHIFT 0x10 |
12912 | #define SISCL_HORZ_FILTER_SCALE_RATIO__SISCL_H_SCALE_RATIO_MASK 0x7ffffff |
12913 | #define SISCL_HORZ_FILTER_SCALE_RATIO__SISCL_H_SCALE_RATIO__SHIFT 0x0 |
12914 | #define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_FRAC_Y_RGB_MASK 0xffffff |
12915 | #define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_FRAC_Y_RGB__SHIFT 0x0 |
12916 | #define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_INT_Y_RGB_MASK 0x1f000000 |
12917 | #define SISCL_HORZ_FILTER_INIT_Y_RGB__SISCL_H_INIT_INT_Y_RGB__SHIFT 0x18 |
12918 | #define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_FRAC_CBCR_MASK 0xffffff |
12919 | #define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_FRAC_CBCR__SHIFT 0x0 |
12920 | #define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_INT_CBCR_MASK 0x1f000000 |
12921 | #define SISCL_HORZ_FILTER_INIT_CBCR__SISCL_H_INIT_INT_CBCR__SHIFT 0x18 |
12922 | #define SISCL_VERT_FILTER_SCALE_RATIO__SISCL_V_SCALE_RATIO_MASK 0x7ffffff |
12923 | #define SISCL_VERT_FILTER_SCALE_RATIO__SISCL_V_SCALE_RATIO__SHIFT 0x0 |
12924 | #define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_FRAC_Y_RGB_MASK 0xffffff |
12925 | #define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_FRAC_Y_RGB__SHIFT 0x0 |
12926 | #define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_INT_Y_RGB_MASK 0x1f000000 |
12927 | #define SISCL_VERT_FILTER_INIT_Y_RGB__SISCL_V_INIT_INT_Y_RGB__SHIFT 0x18 |
12928 | #define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_FRAC_CBCR_MASK 0xffffff |
12929 | #define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_FRAC_CBCR__SHIFT 0x0 |
12930 | #define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_INT_CBCR_MASK 0x1f000000 |
12931 | #define SISCL_VERT_FILTER_INIT_CBCR__SISCL_V_INIT_INT_CBCR__SHIFT 0x18 |
12932 | #define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_Y_RGB_MASK 0xffff |
12933 | #define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_Y_RGB__SHIFT 0x0 |
12934 | #define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_CBCR_MASK 0xffff0000 |
12935 | #define SISCL_ROUND_OFFSET__SISCL_ROUND_OFFSET_CBCR__SHIFT 0x10 |
12936 | #define SISCL_CLAMP__SISCL_CLAMP_UPPER_Y_RGB_MASK 0xff |
12937 | #define SISCL_CLAMP__SISCL_CLAMP_UPPER_Y_RGB__SHIFT 0x0 |
12938 | #define SISCL_CLAMP__SISCL_CLAMP_LOWER_Y_RGB_MASK 0xff00 |
12939 | #define SISCL_CLAMP__SISCL_CLAMP_LOWER_Y_RGB__SHIFT 0x8 |
12940 | #define SISCL_CLAMP__SISCL_CLAMP_UPPER_CBCR_MASK 0xff0000 |
12941 | #define SISCL_CLAMP__SISCL_CLAMP_UPPER_CBCR__SHIFT 0x10 |
12942 | #define SISCL_CLAMP__SISCL_CLAMP_LOWER_CBCR_MASK 0xff000000 |
12943 | #define SISCL_CLAMP__SISCL_CLAMP_LOWER_CBCR__SHIFT 0x18 |
12944 | #define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_FLAG_MASK 0x1 |
12945 | #define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_FLAG__SHIFT 0x0 |
12946 | #define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_ACK_MASK 0x100 |
12947 | #define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_ACK__SHIFT 0x8 |
12948 | #define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_MASK_MASK 0x1000 |
12949 | #define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_MASK__SHIFT 0xc |
12950 | #define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_STATUS_MASK 0x10000 |
12951 | #define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 |
12952 | #define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_TYPE_MASK 0x100000 |
12953 | #define SISCL_OVERFLOW_STATUS__SISCL_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 |
12954 | #define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_FLAG_MASK 0x1 |
12955 | #define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_FLAG__SHIFT 0x0 |
12956 | #define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_ACK_MASK 0x100 |
12957 | #define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_ACK__SHIFT 0x8 |
12958 | #define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_MASK_MASK 0x1000 |
12959 | #define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_MASK__SHIFT 0xc |
12960 | #define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_STATUS_MASK 0x10000 |
12961 | #define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x10 |
12962 | #define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_TYPE_MASK 0x100000 |
12963 | #define SISCL_COEF_RAM_CONFLICT_STATUS__SISCL_HOST_CONFLICT_INT_TYPE__SHIFT 0x14 |
12964 | #define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_OUTSIDE_PIX_STRATEGY_MASK 0x1 |
12965 | #define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_OUTSIDE_PIX_STRATEGY__SHIFT 0x0 |
12966 | #define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_B_CB_MASK 0xff00 |
12967 | #define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_B_CB__SHIFT 0x8 |
12968 | #define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_G_Y_MASK 0xff0000 |
12969 | #define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_G_Y__SHIFT 0x10 |
12970 | #define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_R_CR_MASK 0xff000000 |
12971 | #define SISCL_OUTSIDE_PIX_STRATEGY__SISCL_BLACK_COLOR_R_CR__SHIFT 0x18 |
12972 | #define SISCL_TEST_CNTL__SISCL_TEST_CRC_EN_MASK 0x10 |
12973 | #define SISCL_TEST_CNTL__SISCL_TEST_CRC_EN__SHIFT 0x4 |
12974 | #define SISCL_TEST_CNTL__SISCL_TEST_CRC_CONT_EN_MASK 0x100 |
12975 | #define SISCL_TEST_CNTL__SISCL_TEST_CRC_CONT_EN__SHIFT 0x8 |
12976 | #define SISCL_TEST_CNTL__SISCL_TEST_CRC_DE_ONLY_MASK 0x10000 |
12977 | #define SISCL_TEST_CNTL__SISCL_TEST_CRC_DE_ONLY__SHIFT 0x10 |
12978 | #define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_RED_MASK_MASK 0xffff |
12979 | #define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_RED_MASK__SHIFT 0x0 |
12980 | #define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_SIG_RED_MASK 0xffff0000 |
12981 | #define SISCL_TEST_CRC_RED__SISCL_TEST_CRC_SIG_RED__SHIFT 0x10 |
12982 | #define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_GREEN_MASK_MASK 0xffff |
12983 | #define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_GREEN_MASK__SHIFT 0x0 |
12984 | #define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_SIG_GREEN_MASK 0xffff0000 |
12985 | #define SISCL_TEST_CRC_GREEN__SISCL_TEST_CRC_SIG_GREEN__SHIFT 0x10 |
12986 | #define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_BLUE_MASK_MASK 0xffff |
12987 | #define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_BLUE_MASK__SHIFT 0x0 |
12988 | #define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_SIG_BLUE_MASK 0xffff0000 |
12989 | #define SISCL_TEST_CRC_BLUE__SISCL_TEST_CRC_SIG_BLUE__SHIFT 0x10 |
12990 | #define SISCL_BACKPRESSURE_CNT_EN__SISCL_BACKPRESSURE_CNT_EN_MASK 0x1 |
12991 | #define SISCL_BACKPRESSURE_CNT_EN__SISCL_BACKPRESSURE_CNT_EN__SHIFT 0x0 |
12992 | #define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_Y_MAX_BACKPRESSURE_MASK 0xffff |
12993 | #define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_Y_MAX_BACKPRESSURE__SHIFT 0x0 |
12994 | #define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_C_MAX_BACKPRESSURE_MASK 0xffff0000 |
12995 | #define SISCL_MCIF_BACKPRESSURE_CNT__SISCL_MCIF_C_MAX_BACKPRESSURE__SHIFT 0x10 |
12996 | #define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_INDEX_MASK 0xff |
12997 | #define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_INDEX__SHIFT 0x0 |
12998 | #define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_WRITE_EN_MASK 0x100 |
12999 | #define SISCL_TEST_DEBUG_INDEX__SISCL_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
13000 | #define SISCL_TEST_DEBUG_DATA__SISCL_TEST_DEBUG_DATA_MASK 0xffffffff |
13001 | #define SISCL_TEST_DEBUG_DATA__SISCL_TEST_DEBUG_DATA__SHIFT 0x0 |
13002 | #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x300 |
13003 | #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x8 |
13004 | #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0xf000 |
13005 | #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0xc |
13006 | #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x10000 |
13007 | #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x10 |
13008 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0xf |
13009 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x0 |
13010 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x70 |
13011 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x4 |
13012 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x300 |
13013 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x8 |
13014 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0xc00 |
13015 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0xa |
13016 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x3000 |
13017 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0xc |
13018 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x300000 |
13019 | #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x14 |
13020 | #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x7 |
13021 | #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x0 |
13022 | #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x700000 |
13023 | #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x14 |
13024 | #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000 |
13025 | #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x1b |
13026 | #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x100 |
13027 | #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x8 |
13028 | #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x200 |
13029 | #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x9 |
13030 | #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x400 |
13031 | #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0xa |
13032 | #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT_MASK 0x1000 |
13033 | #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT__SHIFT 0xc |
13034 | #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK_MASK 0x2000 |
13035 | #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK__SHIFT 0xd |
13036 | #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK_MASK 0x4000 |
13037 | #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK__SHIFT 0xe |
13038 | #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x10000 |
13039 | #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x10 |
13040 | #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x20000 |
13041 | #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x11 |
13042 | #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x40000 |
13043 | #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x12 |
13044 | #define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT_MASK 0x100000 |
13045 | #define XDMA_INTERRUPT__XDMA_PERF_MEAS_STAT__SHIFT 0x14 |
13046 | #define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK_MASK 0x200000 |
13047 | #define XDMA_INTERRUPT__XDMA_PERF_MEAS_MASK__SHIFT 0x15 |
13048 | #define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK_MASK 0x400000 |
13049 | #define XDMA_INTERRUPT__XDMA_PERF_MEAS_ACK__SHIFT 0x16 |
13050 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0xf |
13051 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x0 |
13052 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0xff0 |
13053 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x4 |
13054 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x8000 |
13055 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0xf |
13056 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x10000 |
13057 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x10 |
13058 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0_MASK 0x20000 |
13059 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0__SHIFT 0x11 |
13060 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1_MASK 0x40000 |
13061 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1__SHIFT 0x12 |
13062 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2_MASK 0x80000 |
13063 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2__SHIFT 0x13 |
13064 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3_MASK 0x100000 |
13065 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3__SHIFT 0x14 |
13066 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4_MASK 0x200000 |
13067 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4__SHIFT 0x15 |
13068 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5_MASK 0x400000 |
13069 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5__SHIFT 0x16 |
13070 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x800000 |
13071 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x17 |
13072 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x1000000 |
13073 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x18 |
13074 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x2000000 |
13075 | #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x19 |
13076 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS_MASK 0x1 |
13077 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 |
13078 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS_MASK 0x100 |
13079 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS__SHIFT 0x8 |
13080 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE_MASK 0x10000 |
13081 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x10 |
13082 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE_MASK 0x1000000 |
13083 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x18 |
13084 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE_MASK 0xc0000000 |
13085 | #define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE__SHIFT 0x1e |
13086 | #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0xf |
13087 | #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x0 |
13088 | #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x100 |
13089 | #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x8 |
13090 | #define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS_MASK 0xff |
13091 | #define XDMA_PERF_MEAS_STATUS__XDMA_PERF_MEAS_STATUS__SHIFT 0x0 |
13092 | #define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY_MASK 0x1 |
13093 | #define XDMA_IF_STATUS__XDMA_MC_PCIEWR_BUSY__SHIFT 0x0 |
13094 | #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0xff |
13095 | #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x0 |
13096 | #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x100 |
13097 | #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
13098 | #define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffff |
13099 | #define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x0 |
13100 | #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x7 |
13101 | #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x0 |
13102 | #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x8 |
13103 | #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x3 |
13104 | #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000 |
13105 | #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0xf |
13106 | #define XDMA_PG_CONTROL__XDMA_PG_CONTROL_MASK 0xffffffff |
13107 | #define XDMA_PG_CONTROL__XDMA_PG_CONTROL__SHIFT 0x0 |
13108 | #define XDMA_PG_WDATA__XDMA_PG_WDATA_MASK 0xffffffff |
13109 | #define XDMA_PG_WDATA__XDMA_PG_WDATA__SHIFT 0x0 |
13110 | #define XDMA_PG_STATUS__XDMA_SERDES_RDATA_MASK 0xffffff |
13111 | #define XDMA_PG_STATUS__XDMA_SERDES_RDATA__SHIFT 0x0 |
13112 | #define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY_MASK 0x1000000 |
13113 | #define XDMA_PG_STATUS__XDMA_PGFSM_READ_READY__SHIFT 0x18 |
13114 | #define XDMA_PG_STATUS__XDMA_SERDES_BUSY_MASK 0x2000000 |
13115 | #define XDMA_PG_STATUS__XDMA_SERDES_BUSY__SHIFT 0x19 |
13116 | #define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS_MASK 0x4000000 |
13117 | #define XDMA_PG_STATUS__XDMA_SERDES_SMU_POWER_STATUS__SHIFT 0x1a |
13118 | #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX_MASK 0xff |
13119 | #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_INDEX__SHIFT 0x0 |
13120 | #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN_MASK 0x100 |
13121 | #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_AON_TEST_DEBUG_WRITE_EN__SHIFT 0x8 |
13122 | #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL_MASK 0x200 |
13123 | #define XDMA_AON_TEST_DEBUG_INDEX__XDMA_DEBUG_SEL__SHIFT 0x9 |
13124 | #define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA_MASK 0xffffffff |
13125 | #define XDMA_AON_TEST_DEBUG_DATA__XDMA_AON_TEST_DEBUG_DATA__SHIFT 0x0 |
13126 | |
13127 | #endif /* DCE_8_0_SH_MASK_H */ |
13128 | |