| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright 2023 Advanced Micro Devices, Inc. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the "Software"), |
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| 7 | * to deal in the Software without restriction, including without limitation |
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 10 | * Software is furnished to do so, subject to the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice shall be included in |
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| 13 | * all copies or substantial portions of the Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | * |
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| 23 | */ |
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| 24 | #ifndef _dcn_3_5_0_OFFSET_HEADER |
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| 25 | #define |
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| 26 | |
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| 27 | // addressBlock: dce_dc_hda_azcontroller_azdec |
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| 28 | // base address: 0x1300000 |
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| 29 | #define regGLOBAL_CAPABILITIES 0x4b7000 |
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| 30 | #define regGLOBAL_CAPABILITIES_BASE_IDX 3 |
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| 31 | #define regMINOR_VERSION 0x4b7000 |
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| 32 | #define regMINOR_VERSION_BASE_IDX 3 |
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| 33 | #define regMAJOR_VERSION 0x4b7000 |
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| 34 | #define regMAJOR_VERSION_BASE_IDX 3 |
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| 35 | #define regOUTPUT_PAYLOAD_CAPABILITY 0x4b7001 |
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| 36 | #define regOUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 |
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| 37 | #define regINPUT_PAYLOAD_CAPABILITY 0x4b7001 |
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| 38 | #define regINPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 |
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| 39 | #define regGLOBAL_CONTROL 0x4b7002 |
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| 40 | #define regGLOBAL_CONTROL_BASE_IDX 3 |
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| 41 | #define regWAKE_ENABLE 0x4b7003 |
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| 42 | #define regWAKE_ENABLE_BASE_IDX 3 |
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| 43 | #define regSTATE_CHANGE_STATUS 0x4b7003 |
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| 44 | #define regSTATE_CHANGE_STATUS_BASE_IDX 3 |
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| 45 | #define regGLOBAL_STATUS 0x4b7004 |
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| 46 | #define regGLOBAL_STATUS_BASE_IDX 3 |
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| 47 | #define regOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 |
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| 48 | #define regOUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 |
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| 49 | #define regINPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 |
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| 50 | #define regINPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 |
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| 51 | #define regINTERRUPT_CONTROL 0x4b7008 |
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| 52 | #define regINTERRUPT_CONTROL_BASE_IDX 3 |
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| 53 | #define regINTERRUPT_STATUS 0x4b7009 |
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| 54 | #define regINTERRUPT_STATUS_BASE_IDX 3 |
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| 55 | #define regWALL_CLOCK_COUNTER 0x4b700c |
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| 56 | #define regWALL_CLOCK_COUNTER_BASE_IDX 3 |
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| 57 | #define regSTREAM_SYNCHRONIZATION 0x4b700e |
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| 58 | #define regSTREAM_SYNCHRONIZATION_BASE_IDX 3 |
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| 59 | #define regCORB_LOWER_BASE_ADDRESS 0x4b7010 |
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| 60 | #define regCORB_LOWER_BASE_ADDRESS_BASE_IDX 3 |
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| 61 | #define regCORB_UPPER_BASE_ADDRESS 0x4b7011 |
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| 62 | #define regCORB_UPPER_BASE_ADDRESS_BASE_IDX 3 |
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| 63 | #define regAZCONTROLLER0_CORB_WRITE_POINTER 0x4b7012 |
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| 64 | #define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 3 |
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| 65 | #define regAZCONTROLLER0_CORB_READ_POINTER 0x4b7012 |
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| 66 | #define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 3 |
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| 67 | #define regAZCONTROLLER0_CORB_CONTROL 0x4b7013 |
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| 68 | #define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 3 |
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| 69 | #define regAZCONTROLLER0_CORB_STATUS 0x4b7013 |
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| 70 | #define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 3 |
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| 71 | #define regAZCONTROLLER0_CORB_SIZE 0x4b7013 |
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| 72 | #define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 3 |
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| 73 | #define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x4b7014 |
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| 74 | #define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 3 |
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| 75 | #define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x4b7015 |
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| 76 | #define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 3 |
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| 77 | #define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x4b7016 |
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| 78 | #define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 3 |
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| 79 | #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x4b7016 |
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| 80 | #define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 3 |
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| 81 | #define regAZCONTROLLER0_RIRB_CONTROL 0x4b7017 |
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| 82 | #define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 3 |
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| 83 | #define regAZCONTROLLER0_RIRB_STATUS 0x4b7017 |
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| 84 | #define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 3 |
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| 85 | #define regAZCONTROLLER0_RIRB_SIZE 0x4b7017 |
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| 86 | #define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 3 |
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| 87 | #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018 |
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| 88 | #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3 |
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| 89 | #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 |
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| 90 | #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 |
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| 91 | #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 |
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| 92 | #define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 |
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| 93 | #define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019 |
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| 94 | #define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3 |
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| 95 | #define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x4b701a |
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| 96 | #define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 3 |
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| 97 | #define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c |
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| 98 | #define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3 |
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| 99 | #define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d |
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| 100 | #define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3 |
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| 101 | #define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS 0x4b780c |
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| 102 | #define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 3 |
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| 103 | |
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| 104 | // addressBlock: azendpoint_sinkinfoind |
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| 105 | // base address: 0x0 |
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| 106 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 |
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| 107 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 |
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| 108 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 |
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| 109 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 |
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| 110 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 |
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| 111 | #define ixSINK_DESCRIPTION0 0x0005 |
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| 112 | #define ixSINK_DESCRIPTION1 0x0006 |
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| 113 | #define ixSINK_DESCRIPTION2 0x0007 |
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| 114 | #define ixSINK_DESCRIPTION3 0x0008 |
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| 115 | #define ixSINK_DESCRIPTION4 0x0009 |
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| 116 | #define ixSINK_DESCRIPTION5 0x000a |
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| 117 | #define ixSINK_DESCRIPTION6 0x000b |
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| 118 | #define ixSINK_DESCRIPTION7 0x000c |
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| 119 | #define ixSINK_DESCRIPTION8 0x000d |
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| 120 | #define ixSINK_DESCRIPTION9 0x000e |
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| 121 | #define ixSINK_DESCRIPTION10 0x000f |
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| 122 | #define ixSINK_DESCRIPTION11 0x0010 |
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| 123 | #define ixSINK_DESCRIPTION12 0x0011 |
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| 124 | #define ixSINK_DESCRIPTION13 0x0012 |
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| 125 | #define ixSINK_DESCRIPTION14 0x0013 |
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| 126 | #define ixSINK_DESCRIPTION15 0x0014 |
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| 127 | #define ixSINK_DESCRIPTION16 0x0015 |
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| 128 | #define ixSINK_DESCRIPTION17 0x0016 |
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| 129 | |
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| 130 | |
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| 131 | // addressBlock: azf0controller_azinputcrc0resultind |
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| 132 | // base address: 0x0 |
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| 133 | #define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 |
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| 134 | #define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 |
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| 135 | #define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 |
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| 136 | #define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 |
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| 137 | #define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 |
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| 138 | #define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 |
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| 139 | #define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 |
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| 140 | #define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 |
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| 141 | |
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| 142 | |
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| 143 | // addressBlock: azf0controller_azinputcrc1resultind |
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| 144 | // base address: 0x0 |
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| 145 | #define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 |
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| 146 | #define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 |
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| 147 | #define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 |
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| 148 | #define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 |
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| 149 | #define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 |
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| 150 | #define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 |
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| 151 | #define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 |
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| 152 | #define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 |
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| 153 | |
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| 154 | |
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| 155 | // addressBlock: azf0controller_azcrc0resultind |
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| 156 | // base address: 0x0 |
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| 157 | #define ixAZALIA_CRC0_CHANNEL0 0x0000 |
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| 158 | #define ixAZALIA_CRC0_CHANNEL1 0x0001 |
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| 159 | #define ixAZALIA_CRC0_CHANNEL2 0x0002 |
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| 160 | #define ixAZALIA_CRC0_CHANNEL3 0x0003 |
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| 161 | #define ixAZALIA_CRC0_CHANNEL4 0x0004 |
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| 162 | #define ixAZALIA_CRC0_CHANNEL5 0x0005 |
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| 163 | #define ixAZALIA_CRC0_CHANNEL6 0x0006 |
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| 164 | #define ixAZALIA_CRC0_CHANNEL7 0x0007 |
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| 165 | |
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| 166 | |
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| 167 | // addressBlock: azf0controller_azcrc1resultind |
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| 168 | // base address: 0x0 |
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| 169 | #define ixAZALIA_CRC1_CHANNEL0 0x0000 |
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| 170 | #define ixAZALIA_CRC1_CHANNEL1 0x0001 |
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| 171 | #define ixAZALIA_CRC1_CHANNEL2 0x0002 |
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| 172 | #define ixAZALIA_CRC1_CHANNEL3 0x0003 |
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| 173 | #define ixAZALIA_CRC1_CHANNEL4 0x0004 |
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| 174 | #define ixAZALIA_CRC1_CHANNEL5 0x0005 |
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| 175 | #define ixAZALIA_CRC1_CHANNEL6 0x0006 |
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| 176 | #define ixAZALIA_CRC1_CHANNEL7 0x0007 |
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| 177 | |
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| 178 | |
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| 179 | // addressBlock: azf0stream0_streamind |
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| 180 | // base address: 0x0 |
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| 181 | #define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 182 | #define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 183 | #define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 184 | #define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 185 | #define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 186 | |
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| 187 | |
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| 188 | // addressBlock: azf0stream1_streamind |
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| 189 | // base address: 0x0 |
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| 190 | #define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 191 | #define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 192 | #define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 193 | #define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 194 | #define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 195 | |
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| 196 | |
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| 197 | // addressBlock: azf0stream2_streamind |
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| 198 | // base address: 0x0 |
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| 199 | #define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 200 | #define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 201 | #define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 202 | #define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 203 | #define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 204 | |
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| 205 | |
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| 206 | // addressBlock: azf0stream3_streamind |
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| 207 | // base address: 0x0 |
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| 208 | #define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 209 | #define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 210 | #define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 211 | #define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 212 | #define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 213 | |
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| 214 | |
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| 215 | // addressBlock: azf0stream4_streamind |
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| 216 | // base address: 0x0 |
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| 217 | #define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 218 | #define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 219 | #define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 220 | #define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 221 | #define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 222 | |
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| 223 | |
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| 224 | // addressBlock: azf0stream5_streamind |
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| 225 | // base address: 0x0 |
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| 226 | #define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 227 | #define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 228 | #define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 229 | #define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 230 | #define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 231 | |
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| 232 | |
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| 233 | // addressBlock: azf0stream6_streamind |
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| 234 | // base address: 0x0 |
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| 235 | #define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 236 | #define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 237 | #define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 238 | #define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 239 | #define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 240 | |
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| 241 | |
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| 242 | // addressBlock: azf0stream7_streamind |
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| 243 | // base address: 0x0 |
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| 244 | #define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 245 | #define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 246 | #define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 247 | #define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 248 | #define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 249 | |
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| 250 | |
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| 251 | // addressBlock: azf0stream8_streamind |
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| 252 | // base address: 0x0 |
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| 253 | #define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 254 | #define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 255 | #define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 256 | #define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 257 | #define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 258 | |
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| 259 | |
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| 260 | // addressBlock: azf0stream9_streamind |
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| 261 | // base address: 0x0 |
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| 262 | #define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 263 | #define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 264 | #define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 265 | #define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 266 | #define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 267 | |
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| 268 | |
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| 269 | // addressBlock: azf0stream10_streamind |
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| 270 | // base address: 0x0 |
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| 271 | #define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 272 | #define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 273 | #define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 274 | #define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 275 | #define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 276 | |
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| 277 | |
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| 278 | // addressBlock: azf0stream11_streamind |
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| 279 | // base address: 0x0 |
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| 280 | #define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 281 | #define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 282 | #define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 283 | #define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 284 | #define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 285 | |
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| 286 | |
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| 287 | // addressBlock: azf0stream12_streamind |
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| 288 | // base address: 0x0 |
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| 289 | #define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 290 | #define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 291 | #define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 292 | #define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 293 | #define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 294 | |
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| 295 | |
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| 296 | // addressBlock: azf0stream13_streamind |
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| 297 | // base address: 0x0 |
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| 298 | #define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 299 | #define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 300 | #define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 301 | #define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 302 | #define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 303 | |
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| 304 | |
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| 305 | // addressBlock: azf0stream14_streamind |
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| 306 | // base address: 0x0 |
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| 307 | #define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 308 | #define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 309 | #define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 310 | #define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 311 | #define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 312 | |
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| 313 | |
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| 314 | // addressBlock: azf0stream15_streamind |
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| 315 | // base address: 0x0 |
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| 316 | #define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 |
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| 317 | #define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 |
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| 318 | #define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 |
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| 319 | #define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 |
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| 320 | #define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 |
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| 321 | |
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| 322 | |
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| 323 | // addressBlock: azf0endpoint0_endpointind |
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| 324 | // base address: 0x0 |
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| 325 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
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| 326 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
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| 327 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
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| 328 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
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| 329 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
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| 330 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
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| 331 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
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| 332 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
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| 333 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
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| 334 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
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| 335 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
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| 336 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
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| 337 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
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| 338 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
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| 339 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
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| 340 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
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| 341 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
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| 342 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
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| 343 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
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| 344 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
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| 345 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
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| 346 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
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| 347 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
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| 348 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
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| 349 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
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| 350 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
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| 351 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
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| 352 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
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| 353 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
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| 354 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
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| 355 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
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| 356 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
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| 357 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
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| 358 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
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| 359 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
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| 360 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
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| 361 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
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| 362 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
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| 363 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
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| 364 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
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| 365 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
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| 366 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
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| 367 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
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| 368 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
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| 369 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
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| 370 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
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| 371 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
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| 372 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
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| 373 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
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| 374 | #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
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| 375 | #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
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| 376 | #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
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| 377 | #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
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| 378 | #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
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| 379 | #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
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| 380 | #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
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| 381 | #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
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| 382 | #define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
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| 383 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
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| 384 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
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| 385 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
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| 386 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
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| 387 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
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| 388 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
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| 389 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
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| 390 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
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| 391 | #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
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| 392 | #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
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| 393 | #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
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| 394 | #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
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| 395 | #define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
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| 396 | #define ixAZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 |
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| 397 | |
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| 398 | |
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| 399 | // addressBlock: azf0endpoint1_endpointind |
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| 400 | // base address: 0x0 |
|---|
| 401 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
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| 402 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
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| 403 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
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| 404 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
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| 405 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
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| 406 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
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| 407 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
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| 408 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
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| 409 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
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| 410 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
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| 411 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
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| 412 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
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| 413 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
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| 414 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
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| 415 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
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| 416 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
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| 417 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
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| 418 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
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| 419 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
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| 420 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
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| 421 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
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| 422 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
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| 423 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
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| 424 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
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| 425 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
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| 426 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
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| 427 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
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| 428 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
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| 429 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
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| 430 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
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| 431 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
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| 432 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
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| 433 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
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| 434 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
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| 435 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
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| 436 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
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| 437 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
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| 438 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
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| 439 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
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| 440 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
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| 441 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
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| 442 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
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| 443 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
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| 444 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
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| 445 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
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| 446 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
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| 447 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
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| 448 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
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| 449 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
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| 450 | #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
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| 451 | #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
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| 452 | #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
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| 453 | #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
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| 454 | #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
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| 455 | #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
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| 456 | #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
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| 457 | #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
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| 458 | #define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
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| 459 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
|---|
| 460 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
|---|
| 461 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 462 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
|---|
| 463 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 464 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
|---|
| 465 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
|---|
| 466 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
|---|
| 467 | #define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
|---|
| 468 | #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
|---|
| 469 | #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
|---|
| 470 | #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
|---|
| 471 | #define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
|---|
| 472 | #define ixAZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 |
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| 473 | |
|---|
| 474 | |
|---|
| 475 | // addressBlock: azf0endpoint2_endpointind |
|---|
| 476 | // base address: 0x0 |
|---|
| 477 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
|---|
| 478 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
|---|
| 479 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
|---|
| 480 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
|---|
| 481 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
|---|
| 482 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
|---|
| 483 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
|---|
| 484 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
|---|
| 485 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
|---|
| 486 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
|---|
| 487 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
|---|
| 488 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
|---|
| 489 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
|---|
| 490 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
|---|
| 491 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
|---|
| 492 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
|---|
| 493 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
|---|
| 494 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
|---|
| 495 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
|---|
| 496 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
|---|
| 497 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
|---|
| 498 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
|---|
| 499 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
|---|
| 500 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
|---|
| 501 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
|---|
| 502 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
|---|
| 503 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
|---|
| 504 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
|---|
| 505 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
|---|
| 506 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
|---|
| 507 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
|---|
| 508 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
|---|
| 509 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
|---|
| 510 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
|---|
| 511 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
|---|
| 512 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
|---|
| 513 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
|---|
| 514 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
|---|
| 515 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
|---|
| 516 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
|---|
| 517 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
|---|
| 518 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
|---|
| 519 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
|---|
| 520 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
|---|
| 521 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
|---|
| 522 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
|---|
| 523 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
|---|
| 524 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
|---|
| 525 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
|---|
| 526 | #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
|---|
| 527 | #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
|---|
| 528 | #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
|---|
| 529 | #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
|---|
| 530 | #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
|---|
| 531 | #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
|---|
| 532 | #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
|---|
| 533 | #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
|---|
| 534 | #define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
|---|
| 535 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
|---|
| 536 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
|---|
| 537 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 538 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
|---|
| 539 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 540 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
|---|
| 541 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
|---|
| 542 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
|---|
| 543 | #define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
|---|
| 544 | #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
|---|
| 545 | #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
|---|
| 546 | #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
|---|
| 547 | #define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
|---|
| 548 | #define ixAZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 |
|---|
| 549 | |
|---|
| 550 | |
|---|
| 551 | // addressBlock: azf0endpoint3_endpointind |
|---|
| 552 | // base address: 0x0 |
|---|
| 553 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
|---|
| 554 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
|---|
| 555 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
|---|
| 556 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
|---|
| 557 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
|---|
| 558 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
|---|
| 559 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
|---|
| 560 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
|---|
| 561 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
|---|
| 562 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
|---|
| 563 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
|---|
| 564 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
|---|
| 565 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
|---|
| 566 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
|---|
| 567 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
|---|
| 568 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
|---|
| 569 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
|---|
| 570 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
|---|
| 571 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
|---|
| 572 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
|---|
| 573 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
|---|
| 574 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
|---|
| 575 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
|---|
| 576 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
|---|
| 577 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
|---|
| 578 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
|---|
| 579 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
|---|
| 580 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
|---|
| 581 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
|---|
| 582 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
|---|
| 583 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
|---|
| 584 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
|---|
| 585 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
|---|
| 586 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
|---|
| 587 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
|---|
| 588 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
|---|
| 589 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
|---|
| 590 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
|---|
| 591 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
|---|
| 592 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
|---|
| 593 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
|---|
| 594 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
|---|
| 595 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
|---|
| 596 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
|---|
| 597 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
|---|
| 598 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
|---|
| 599 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
|---|
| 600 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
|---|
| 601 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
|---|
| 602 | #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
|---|
| 603 | #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
|---|
| 604 | #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
|---|
| 605 | #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
|---|
| 606 | #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
|---|
| 607 | #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
|---|
| 608 | #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
|---|
| 609 | #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
|---|
| 610 | #define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
|---|
| 611 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
|---|
| 612 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
|---|
| 613 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 614 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
|---|
| 615 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 616 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
|---|
| 617 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
|---|
| 618 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
|---|
| 619 | #define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
|---|
| 620 | #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
|---|
| 621 | #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
|---|
| 622 | #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
|---|
| 623 | #define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
|---|
| 624 | #define ixAZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 |
|---|
| 625 | |
|---|
| 626 | |
|---|
| 627 | // addressBlock: azf0endpoint4_endpointind |
|---|
| 628 | // base address: 0x0 |
|---|
| 629 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
|---|
| 630 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
|---|
| 631 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
|---|
| 632 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
|---|
| 633 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
|---|
| 634 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
|---|
| 635 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
|---|
| 636 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
|---|
| 637 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
|---|
| 638 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
|---|
| 639 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
|---|
| 640 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
|---|
| 641 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
|---|
| 642 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
|---|
| 643 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
|---|
| 644 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
|---|
| 645 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
|---|
| 646 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
|---|
| 647 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
|---|
| 648 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
|---|
| 649 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
|---|
| 650 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
|---|
| 651 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
|---|
| 652 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
|---|
| 653 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
|---|
| 654 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
|---|
| 655 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
|---|
| 656 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
|---|
| 657 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
|---|
| 658 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
|---|
| 659 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
|---|
| 660 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
|---|
| 661 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
|---|
| 662 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
|---|
| 663 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
|---|
| 664 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
|---|
| 665 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
|---|
| 666 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
|---|
| 667 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
|---|
| 668 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
|---|
| 669 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
|---|
| 670 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
|---|
| 671 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
|---|
| 672 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
|---|
| 673 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
|---|
| 674 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
|---|
| 675 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
|---|
| 676 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
|---|
| 677 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
|---|
| 678 | #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
|---|
| 679 | #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
|---|
| 680 | #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
|---|
| 681 | #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
|---|
| 682 | #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
|---|
| 683 | #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
|---|
| 684 | #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
|---|
| 685 | #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
|---|
| 686 | #define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
|---|
| 687 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
|---|
| 688 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
|---|
| 689 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 690 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
|---|
| 691 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 692 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
|---|
| 693 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
|---|
| 694 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
|---|
| 695 | #define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
|---|
| 696 | #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
|---|
| 697 | #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
|---|
| 698 | #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
|---|
| 699 | #define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
|---|
| 700 | #define ixAZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 |
|---|
| 701 | |
|---|
| 702 | |
|---|
| 703 | // addressBlock: azf0endpoint5_endpointind |
|---|
| 704 | // base address: 0x0 |
|---|
| 705 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
|---|
| 706 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
|---|
| 707 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
|---|
| 708 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
|---|
| 709 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
|---|
| 710 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
|---|
| 711 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
|---|
| 712 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
|---|
| 713 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
|---|
| 714 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
|---|
| 715 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
|---|
| 716 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
|---|
| 717 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
|---|
| 718 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
|---|
| 719 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
|---|
| 720 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
|---|
| 721 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
|---|
| 722 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
|---|
| 723 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
|---|
| 724 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
|---|
| 725 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
|---|
| 726 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
|---|
| 727 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
|---|
| 728 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
|---|
| 729 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
|---|
| 730 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
|---|
| 731 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
|---|
| 732 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
|---|
| 733 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
|---|
| 734 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
|---|
| 735 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
|---|
| 736 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
|---|
| 737 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
|---|
| 738 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
|---|
| 739 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
|---|
| 740 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
|---|
| 741 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
|---|
| 742 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
|---|
| 743 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
|---|
| 744 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
|---|
| 745 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
|---|
| 746 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
|---|
| 747 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
|---|
| 748 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
|---|
| 749 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
|---|
| 750 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
|---|
| 751 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
|---|
| 752 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
|---|
| 753 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
|---|
| 754 | #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
|---|
| 755 | #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
|---|
| 756 | #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
|---|
| 757 | #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
|---|
| 758 | #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
|---|
| 759 | #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
|---|
| 760 | #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
|---|
| 761 | #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
|---|
| 762 | #define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
|---|
| 763 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
|---|
| 764 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
|---|
| 765 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 766 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
|---|
| 767 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 768 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
|---|
| 769 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
|---|
| 770 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
|---|
| 771 | #define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
|---|
| 772 | #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
|---|
| 773 | #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
|---|
| 774 | #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
|---|
| 775 | #define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
|---|
| 776 | #define ixAZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 |
|---|
| 777 | |
|---|
| 778 | |
|---|
| 779 | // addressBlock: azf0endpoint6_endpointind |
|---|
| 780 | // base address: 0x0 |
|---|
| 781 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
|---|
| 782 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
|---|
| 783 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
|---|
| 784 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
|---|
| 785 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
|---|
| 786 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
|---|
| 787 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
|---|
| 788 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
|---|
| 789 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
|---|
| 790 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
|---|
| 791 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
|---|
| 792 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
|---|
| 793 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
|---|
| 794 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
|---|
| 795 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
|---|
| 796 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
|---|
| 797 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
|---|
| 798 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
|---|
| 799 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
|---|
| 800 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
|---|
| 801 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
|---|
| 802 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
|---|
| 803 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
|---|
| 804 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
|---|
| 805 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
|---|
| 806 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
|---|
| 807 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
|---|
| 808 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
|---|
| 809 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
|---|
| 810 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
|---|
| 811 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
|---|
| 812 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
|---|
| 813 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
|---|
| 814 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
|---|
| 815 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
|---|
| 816 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
|---|
| 817 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
|---|
| 818 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
|---|
| 819 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
|---|
| 820 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
|---|
| 821 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
|---|
| 822 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
|---|
| 823 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
|---|
| 824 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
|---|
| 825 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
|---|
| 826 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
|---|
| 827 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
|---|
| 828 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
|---|
| 829 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
|---|
| 830 | #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
|---|
| 831 | #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
|---|
| 832 | #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
|---|
| 833 | #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
|---|
| 834 | #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
|---|
| 835 | #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
|---|
| 836 | #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
|---|
| 837 | #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
|---|
| 838 | #define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
|---|
| 839 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
|---|
| 840 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
|---|
| 841 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 842 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
|---|
| 843 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 844 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
|---|
| 845 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
|---|
| 846 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
|---|
| 847 | #define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
|---|
| 848 | #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
|---|
| 849 | #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
|---|
| 850 | #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
|---|
| 851 | #define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
|---|
| 852 | #define ixAZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 |
|---|
| 853 | |
|---|
| 854 | |
|---|
| 855 | // addressBlock: azf0endpoint7_endpointind |
|---|
| 856 | // base address: 0x0 |
|---|
| 857 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
|---|
| 858 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
|---|
| 859 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
|---|
| 860 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
|---|
| 861 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
|---|
| 862 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
|---|
| 863 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 |
|---|
| 864 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 |
|---|
| 865 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 |
|---|
| 866 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c |
|---|
| 867 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d |
|---|
| 868 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e |
|---|
| 869 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
|---|
| 870 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 |
|---|
| 871 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
|---|
| 872 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 |
|---|
| 873 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
|---|
| 874 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 |
|---|
| 875 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 |
|---|
| 876 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 |
|---|
| 877 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a |
|---|
| 878 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b |
|---|
| 879 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c |
|---|
| 880 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d |
|---|
| 881 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e |
|---|
| 882 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f |
|---|
| 883 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 |
|---|
| 884 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 |
|---|
| 885 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 |
|---|
| 886 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 |
|---|
| 887 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 |
|---|
| 888 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 |
|---|
| 889 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
|---|
| 890 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 |
|---|
| 891 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 |
|---|
| 892 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a |
|---|
| 893 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b |
|---|
| 894 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c |
|---|
| 895 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d |
|---|
| 896 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e |
|---|
| 897 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f |
|---|
| 898 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 |
|---|
| 899 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 |
|---|
| 900 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 |
|---|
| 901 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
|---|
| 902 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
|---|
| 903 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
|---|
| 904 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 |
|---|
| 905 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 |
|---|
| 906 | #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 |
|---|
| 907 | #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a |
|---|
| 908 | #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b |
|---|
| 909 | #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c |
|---|
| 910 | #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d |
|---|
| 911 | #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e |
|---|
| 912 | #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f |
|---|
| 913 | #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 |
|---|
| 914 | #define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 |
|---|
| 915 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 |
|---|
| 916 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 |
|---|
| 917 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 918 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 |
|---|
| 919 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 920 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 |
|---|
| 921 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 |
|---|
| 922 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 |
|---|
| 923 | #define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a |
|---|
| 924 | #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b |
|---|
| 925 | #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c |
|---|
| 926 | #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d |
|---|
| 927 | #define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e |
|---|
| 928 | #define ixAZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 |
|---|
| 929 | |
|---|
| 930 | |
|---|
| 931 | // addressBlock: azf0inputendpoint0_inputendpointind |
|---|
| 932 | // base address: 0x0 |
|---|
| 933 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
|---|
| 934 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
|---|
| 935 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
|---|
| 936 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
|---|
| 937 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
|---|
| 938 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
|---|
| 939 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
|---|
| 940 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
|---|
| 941 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
|---|
| 942 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
|---|
| 943 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
|---|
| 944 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
|---|
| 945 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
|---|
| 946 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
|---|
| 947 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
|---|
| 948 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
|---|
| 949 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
|---|
| 950 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
|---|
| 951 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 952 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
|---|
| 953 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 954 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
|---|
| 955 | #define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
|---|
| 956 | |
|---|
| 957 | |
|---|
| 958 | // addressBlock: azf0inputendpoint1_inputendpointind |
|---|
| 959 | // base address: 0x0 |
|---|
| 960 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
|---|
| 961 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
|---|
| 962 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
|---|
| 963 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
|---|
| 964 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
|---|
| 965 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
|---|
| 966 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
|---|
| 967 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
|---|
| 968 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
|---|
| 969 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
|---|
| 970 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
|---|
| 971 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
|---|
| 972 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
|---|
| 973 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
|---|
| 974 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
|---|
| 975 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
|---|
| 976 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
|---|
| 977 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
|---|
| 978 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 979 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
|---|
| 980 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 981 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
|---|
| 982 | #define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
|---|
| 983 | |
|---|
| 984 | |
|---|
| 985 | // addressBlock: azf0inputendpoint2_inputendpointind |
|---|
| 986 | // base address: 0x0 |
|---|
| 987 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
|---|
| 988 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
|---|
| 989 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
|---|
| 990 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
|---|
| 991 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
|---|
| 992 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
|---|
| 993 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
|---|
| 994 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
|---|
| 995 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
|---|
| 996 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
|---|
| 997 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
|---|
| 998 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
|---|
| 999 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
|---|
| 1000 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
|---|
| 1001 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
|---|
| 1002 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
|---|
| 1003 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
|---|
| 1004 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
|---|
| 1005 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 1006 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
|---|
| 1007 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 1008 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
|---|
| 1009 | #define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
|---|
| 1010 | |
|---|
| 1011 | |
|---|
| 1012 | // addressBlock: azf0inputendpoint3_inputendpointind |
|---|
| 1013 | // base address: 0x0 |
|---|
| 1014 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
|---|
| 1015 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
|---|
| 1016 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
|---|
| 1017 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
|---|
| 1018 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
|---|
| 1019 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
|---|
| 1020 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
|---|
| 1021 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
|---|
| 1022 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
|---|
| 1023 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
|---|
| 1024 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
|---|
| 1025 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
|---|
| 1026 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
|---|
| 1027 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
|---|
| 1028 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
|---|
| 1029 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
|---|
| 1030 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
|---|
| 1031 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
|---|
| 1032 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 1033 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
|---|
| 1034 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 1035 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
|---|
| 1036 | #define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
|---|
| 1037 | |
|---|
| 1038 | |
|---|
| 1039 | // addressBlock: azf0inputendpoint4_inputendpointind |
|---|
| 1040 | // base address: 0x0 |
|---|
| 1041 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
|---|
| 1042 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
|---|
| 1043 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
|---|
| 1044 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
|---|
| 1045 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
|---|
| 1046 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
|---|
| 1047 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
|---|
| 1048 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
|---|
| 1049 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
|---|
| 1050 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
|---|
| 1051 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
|---|
| 1052 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
|---|
| 1053 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
|---|
| 1054 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
|---|
| 1055 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
|---|
| 1056 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
|---|
| 1057 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
|---|
| 1058 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
|---|
| 1059 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 1060 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
|---|
| 1061 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 1062 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
|---|
| 1063 | #define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
|---|
| 1064 | |
|---|
| 1065 | |
|---|
| 1066 | // addressBlock: azf0inputendpoint5_inputendpointind |
|---|
| 1067 | // base address: 0x0 |
|---|
| 1068 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
|---|
| 1069 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
|---|
| 1070 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
|---|
| 1071 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
|---|
| 1072 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
|---|
| 1073 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
|---|
| 1074 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
|---|
| 1075 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
|---|
| 1076 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
|---|
| 1077 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
|---|
| 1078 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
|---|
| 1079 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
|---|
| 1080 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
|---|
| 1081 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
|---|
| 1082 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
|---|
| 1083 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
|---|
| 1084 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
|---|
| 1085 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
|---|
| 1086 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 1087 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
|---|
| 1088 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 1089 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
|---|
| 1090 | #define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
|---|
| 1091 | |
|---|
| 1092 | |
|---|
| 1093 | // addressBlock: azf0inputendpoint6_inputendpointind |
|---|
| 1094 | // base address: 0x0 |
|---|
| 1095 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
|---|
| 1096 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
|---|
| 1097 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
|---|
| 1098 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
|---|
| 1099 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
|---|
| 1100 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
|---|
| 1101 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
|---|
| 1102 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
|---|
| 1103 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
|---|
| 1104 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
|---|
| 1105 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
|---|
| 1106 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
|---|
| 1107 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
|---|
| 1108 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
|---|
| 1109 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
|---|
| 1110 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
|---|
| 1111 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
|---|
| 1112 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
|---|
| 1113 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 1114 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
|---|
| 1115 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 1116 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
|---|
| 1117 | #define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
|---|
| 1118 | |
|---|
| 1119 | |
|---|
| 1120 | // addressBlock: azf0inputendpoint7_inputendpointind |
|---|
| 1121 | // base address: 0x0 |
|---|
| 1122 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 |
|---|
| 1123 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 |
|---|
| 1124 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 |
|---|
| 1125 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 |
|---|
| 1126 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 |
|---|
| 1127 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 |
|---|
| 1128 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 |
|---|
| 1129 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 |
|---|
| 1130 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 |
|---|
| 1131 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 |
|---|
| 1132 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 |
|---|
| 1133 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 |
|---|
| 1134 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 |
|---|
| 1135 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 |
|---|
| 1136 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 |
|---|
| 1137 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 |
|---|
| 1138 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 |
|---|
| 1139 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 |
|---|
| 1140 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 |
|---|
| 1141 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 |
|---|
| 1142 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 |
|---|
| 1143 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 |
|---|
| 1144 | #define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 |
|---|
| 1145 | |
|---|
| 1146 | |
|---|
| 1147 | // addressBlock: azendpoint_descriptorind |
|---|
| 1148 | // base address: 0x0 |
|---|
| 1149 | #define ixAUDIO_DESCRIPTOR0 0x0001 |
|---|
| 1150 | #define ixAUDIO_DESCRIPTOR1 0x0002 |
|---|
| 1151 | #define ixAUDIO_DESCRIPTOR2 0x0003 |
|---|
| 1152 | #define ixAUDIO_DESCRIPTOR3 0x0004 |
|---|
| 1153 | #define ixAUDIO_DESCRIPTOR4 0x0005 |
|---|
| 1154 | #define ixAUDIO_DESCRIPTOR5 0x0006 |
|---|
| 1155 | #define ixAUDIO_DESCRIPTOR6 0x0007 |
|---|
| 1156 | #define ixAUDIO_DESCRIPTOR7 0x0008 |
|---|
| 1157 | #define ixAUDIO_DESCRIPTOR8 0x0009 |
|---|
| 1158 | #define ixAUDIO_DESCRIPTOR9 0x000a |
|---|
| 1159 | #define ixAUDIO_DESCRIPTOR10 0x000b |
|---|
| 1160 | #define ixAUDIO_DESCRIPTOR11 0x000c |
|---|
| 1161 | #define ixAUDIO_DESCRIPTOR12 0x000d |
|---|
| 1162 | #define ixAUDIO_DESCRIPTOR13 0x000e |
|---|
| 1163 | |
|---|
| 1164 | // addressBlock: dce_dc_hda_azendpoint_azdec |
|---|
| 1165 | // base address: 0x1300000 |
|---|
| 1166 | #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 |
|---|
| 1167 | #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 |
|---|
| 1168 | #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 |
|---|
| 1169 | #define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 |
|---|
| 1170 | |
|---|
| 1171 | |
|---|
| 1172 | // addressBlock: dce_dc_hda_azinputendpoint_azdec |
|---|
| 1173 | // base address: 0x1300000 |
|---|
| 1174 | #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x4b7018 |
|---|
| 1175 | #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 3 |
|---|
| 1176 | #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x4b7018 |
|---|
| 1177 | #define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 3 |
|---|
| 1178 | |
|---|
| 1179 | |
|---|
| 1180 | // addressBlock: dce_dc_dccg_dccg_dispdec |
|---|
| 1181 | // base address: 0x0 |
|---|
| 1182 | #define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 |
|---|
| 1183 | #define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 |
|---|
| 1184 | #define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 |
|---|
| 1185 | #define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 |
|---|
| 1186 | #define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 |
|---|
| 1187 | #define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 |
|---|
| 1188 | #define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 |
|---|
| 1189 | #define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 |
|---|
| 1190 | #define regDP_DTO_DBUF_EN 0x0044 |
|---|
| 1191 | #define regDP_DTO_DBUF_EN_BASE_IDX 1 |
|---|
| 1192 | #define regDSCCLK3_DTO_PARAM 0x0045 |
|---|
| 1193 | #define regDSCCLK3_DTO_PARAM_BASE_IDX 1 |
|---|
| 1194 | #define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 |
|---|
| 1195 | #define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 |
|---|
| 1196 | #define regDCCG_GATE_DISABLE_CNTL4 0x0049 |
|---|
| 1197 | #define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 |
|---|
| 1198 | #define regDPSTREAMCLK_CNTL 0x004a |
|---|
| 1199 | #define regDPSTREAMCLK_CNTL_BASE_IDX 1 |
|---|
| 1200 | #define regREFCLK_CGTT_BLK_CTRL_REG 0x004b |
|---|
| 1201 | #define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 |
|---|
| 1202 | #define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c |
|---|
| 1203 | #define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 |
|---|
| 1204 | #define regDCCG_PERFMON_CNTL2 0x004e |
|---|
| 1205 | #define regDCCG_PERFMON_CNTL2_BASE_IDX 1 |
|---|
| 1206 | #define regDCCG_GLOBAL_FGCG_REP_CNTL 0x0050 |
|---|
| 1207 | #define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX 1 |
|---|
| 1208 | #define regDCCG_DS_DTO_INCR 0x0053 |
|---|
| 1209 | #define regDCCG_DS_DTO_INCR_BASE_IDX 1 |
|---|
| 1210 | #define regDCCG_DS_DTO_MODULO 0x0054 |
|---|
| 1211 | #define regDCCG_DS_DTO_MODULO_BASE_IDX 1 |
|---|
| 1212 | #define regDCCG_DS_CNTL 0x0055 |
|---|
| 1213 | #define regDCCG_DS_CNTL_BASE_IDX 1 |
|---|
| 1214 | #define regDCCG_DS_HW_CAL_INTERVAL 0x0056 |
|---|
| 1215 | #define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 |
|---|
| 1216 | #define regDPREFCLK_CNTL 0x0058 |
|---|
| 1217 | #define regDPREFCLK_CNTL_BASE_IDX 1 |
|---|
| 1218 | #define regDCE_VERSION 0x005e |
|---|
| 1219 | #define regDCE_VERSION_BASE_IDX 1 |
|---|
| 1220 | #define regDCCG_GTC_CNTL 0x0060 |
|---|
| 1221 | #define regDCCG_GTC_CNTL_BASE_IDX 1 |
|---|
| 1222 | #define regDCCG_GTC_DTO_INCR 0x0061 |
|---|
| 1223 | #define regDCCG_GTC_DTO_INCR_BASE_IDX 1 |
|---|
| 1224 | #define regDCCG_GTC_DTO_MODULO 0x0062 |
|---|
| 1225 | #define regDCCG_GTC_DTO_MODULO_BASE_IDX 1 |
|---|
| 1226 | #define regDCCG_GTC_CURRENT 0x0063 |
|---|
| 1227 | #define regDCCG_GTC_CURRENT_BASE_IDX 1 |
|---|
| 1228 | #define regSYMCLK32_SE_CNTL 0x0065 |
|---|
| 1229 | #define regSYMCLK32_SE_CNTL_BASE_IDX 1 |
|---|
| 1230 | #define regSYMCLK32_LE_CNTL 0x0066 |
|---|
| 1231 | #define regSYMCLK32_LE_CNTL_BASE_IDX 1 |
|---|
| 1232 | #define regDTBCLK_P_CNTL 0x0068 |
|---|
| 1233 | #define regDTBCLK_P_CNTL_BASE_IDX 1 |
|---|
| 1234 | #define regDCCG_GATE_DISABLE_CNTL5 0x0069 |
|---|
| 1235 | #define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX 1 |
|---|
| 1236 | #define regDSCCLK0_DTO_PARAM 0x006c |
|---|
| 1237 | #define regDSCCLK0_DTO_PARAM_BASE_IDX 1 |
|---|
| 1238 | #define regDSCCLK1_DTO_PARAM 0x006d |
|---|
| 1239 | #define regDSCCLK1_DTO_PARAM_BASE_IDX 1 |
|---|
| 1240 | #define regDSCCLK2_DTO_PARAM 0x006e |
|---|
| 1241 | #define regDSCCLK2_DTO_PARAM_BASE_IDX 1 |
|---|
| 1242 | #define regOTG_PIXEL_RATE_DIV 0x006f |
|---|
| 1243 | #define regOTG_PIXEL_RATE_DIV_BASE_IDX 1 |
|---|
| 1244 | #define regMILLISECOND_TIME_BASE_DIV 0x0070 |
|---|
| 1245 | #define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 |
|---|
| 1246 | #define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 |
|---|
| 1247 | #define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 |
|---|
| 1248 | #define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 |
|---|
| 1249 | #define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 |
|---|
| 1250 | #define regDCCG_PERFMON_CNTL 0x0073 |
|---|
| 1251 | #define regDCCG_PERFMON_CNTL_BASE_IDX 1 |
|---|
| 1252 | #define regDCCG_GATE_DISABLE_CNTL 0x0074 |
|---|
| 1253 | #define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 |
|---|
| 1254 | #define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 |
|---|
| 1255 | #define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 |
|---|
| 1256 | #define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 |
|---|
| 1257 | #define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 |
|---|
| 1258 | #define regDCCG_CAC_STATUS 0x0077 |
|---|
| 1259 | #define regDCCG_CAC_STATUS_BASE_IDX 1 |
|---|
| 1260 | #define regMICROSECOND_TIME_BASE_DIV 0x007b |
|---|
| 1261 | #define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 |
|---|
| 1262 | #define regDCCG_GATE_DISABLE_CNTL2 0x007c |
|---|
| 1263 | #define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 |
|---|
| 1264 | #define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d |
|---|
| 1265 | #define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 |
|---|
| 1266 | #define regDCCG_DISP_CNTL_REG 0x007f |
|---|
| 1267 | #define regDCCG_DISP_CNTL_REG_BASE_IDX 1 |
|---|
| 1268 | #define regOTG0_PIXEL_RATE_CNTL 0x0080 |
|---|
| 1269 | #define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 |
|---|
| 1270 | #define regDP_DTO0_PHASE 0x0081 |
|---|
| 1271 | #define regDP_DTO0_PHASE_BASE_IDX 1 |
|---|
| 1272 | #define regDP_DTO0_MODULO 0x0082 |
|---|
| 1273 | #define regDP_DTO0_MODULO_BASE_IDX 1 |
|---|
| 1274 | #define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 |
|---|
| 1275 | #define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 |
|---|
| 1276 | #define regOTG1_PIXEL_RATE_CNTL 0x0084 |
|---|
| 1277 | #define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 |
|---|
| 1278 | #define regDP_DTO1_PHASE 0x0085 |
|---|
| 1279 | #define regDP_DTO1_PHASE_BASE_IDX 1 |
|---|
| 1280 | #define regDP_DTO1_MODULO 0x0086 |
|---|
| 1281 | #define regDP_DTO1_MODULO_BASE_IDX 1 |
|---|
| 1282 | #define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 |
|---|
| 1283 | #define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 |
|---|
| 1284 | #define regOTG2_PIXEL_RATE_CNTL 0x0088 |
|---|
| 1285 | #define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 |
|---|
| 1286 | #define regDP_DTO2_PHASE 0x0089 |
|---|
| 1287 | #define regDP_DTO2_PHASE_BASE_IDX 1 |
|---|
| 1288 | #define regDP_DTO2_MODULO 0x008a |
|---|
| 1289 | #define regDP_DTO2_MODULO_BASE_IDX 1 |
|---|
| 1290 | #define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b |
|---|
| 1291 | #define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 |
|---|
| 1292 | #define regOTG3_PIXEL_RATE_CNTL 0x008c |
|---|
| 1293 | #define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 |
|---|
| 1294 | #define regDP_DTO3_PHASE 0x008d |
|---|
| 1295 | #define regDP_DTO3_PHASE_BASE_IDX 1 |
|---|
| 1296 | #define regDP_DTO3_MODULO 0x008e |
|---|
| 1297 | #define regDP_DTO3_MODULO_BASE_IDX 1 |
|---|
| 1298 | #define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f |
|---|
| 1299 | #define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 |
|---|
| 1300 | #define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 |
|---|
| 1301 | #define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 |
|---|
| 1302 | #define regDPPCLK0_DTO_PARAM 0x0099 |
|---|
| 1303 | #define regDPPCLK0_DTO_PARAM_BASE_IDX 1 |
|---|
| 1304 | #define regDPPCLK1_DTO_PARAM 0x009a |
|---|
| 1305 | #define regDPPCLK1_DTO_PARAM_BASE_IDX 1 |
|---|
| 1306 | #define regDPPCLK2_DTO_PARAM 0x009b |
|---|
| 1307 | #define regDPPCLK2_DTO_PARAM_BASE_IDX 1 |
|---|
| 1308 | #define regDPPCLK3_DTO_PARAM 0x009c |
|---|
| 1309 | #define regDPPCLK3_DTO_PARAM_BASE_IDX 1 |
|---|
| 1310 | #define regDCCG_CAC_STATUS2 0x009f |
|---|
| 1311 | #define regDCCG_CAC_STATUS2_BASE_IDX 1 |
|---|
| 1312 | #define regSYMCLKA_CLOCK_ENABLE 0x00a0 |
|---|
| 1313 | #define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 |
|---|
| 1314 | #define regSYMCLKB_CLOCK_ENABLE 0x00a1 |
|---|
| 1315 | #define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 |
|---|
| 1316 | #define regSYMCLKC_CLOCK_ENABLE 0x00a2 |
|---|
| 1317 | #define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 |
|---|
| 1318 | #define regSYMCLKD_CLOCK_ENABLE 0x00a3 |
|---|
| 1319 | #define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 |
|---|
| 1320 | #define regSYMCLKE_CLOCK_ENABLE 0x00a4 |
|---|
| 1321 | #define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 |
|---|
| 1322 | #define regDCCG_SOFT_RESET 0x00a6 |
|---|
| 1323 | #define regDCCG_SOFT_RESET_BASE_IDX 1 |
|---|
| 1324 | #define regDSCCLK_DTO_CTRL 0x00a7 |
|---|
| 1325 | #define regDSCCLK_DTO_CTRL_BASE_IDX 1 |
|---|
| 1326 | #define regDPPCLK_CTRL 0x00a8 |
|---|
| 1327 | #define regDPPCLK_CTRL_BASE_IDX 1 |
|---|
| 1328 | #define regDCCG_GATE_DISABLE_CNTL6 0x00a9 |
|---|
| 1329 | #define regDCCG_GATE_DISABLE_CNTL6_BASE_IDX 1 |
|---|
| 1330 | #define regSYMCLK_PSP_CNTL 0x00aa |
|---|
| 1331 | #define regSYMCLK_PSP_CNTL_BASE_IDX 1 |
|---|
| 1332 | #define regDCCG_AUDIO_DTO_SOURCE 0x00ab |
|---|
| 1333 | #define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 |
|---|
| 1334 | #define regDCCG_AUDIO_DTO0_PHASE 0x00ac |
|---|
| 1335 | #define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 |
|---|
| 1336 | #define regDCCG_AUDIO_DTO0_MODULE 0x00ad |
|---|
| 1337 | #define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 |
|---|
| 1338 | #define regDCCG_AUDIO_DTO1_PHASE 0x00ae |
|---|
| 1339 | #define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 |
|---|
| 1340 | #define regDCCG_AUDIO_DTO1_MODULE 0x00af |
|---|
| 1341 | #define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 |
|---|
| 1342 | #define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 |
|---|
| 1343 | #define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 |
|---|
| 1344 | #define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 |
|---|
| 1345 | #define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 |
|---|
| 1346 | #define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 |
|---|
| 1347 | #define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 |
|---|
| 1348 | #define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 |
|---|
| 1349 | #define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 |
|---|
| 1350 | #define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 |
|---|
| 1351 | #define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 |
|---|
| 1352 | #define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 |
|---|
| 1353 | #define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 |
|---|
| 1354 | #define regDPPCLK_DTO_CTRL 0x00b6 |
|---|
| 1355 | #define regDPPCLK_DTO_CTRL_BASE_IDX 1 |
|---|
| 1356 | #define regDCCG_VSYNC_CNT_CTRL 0x00b8 |
|---|
| 1357 | #define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 |
|---|
| 1358 | #define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 |
|---|
| 1359 | #define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 |
|---|
| 1360 | #define regFORCE_SYMCLK_DISABLE 0x00ba |
|---|
| 1361 | #define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 |
|---|
| 1362 | #define regDTBCLK_DTO0_PHASE 0x0018 |
|---|
| 1363 | #define regDTBCLK_DTO0_PHASE_BASE_IDX 2 |
|---|
| 1364 | #define regDTBCLK_DTO1_PHASE 0x0019 |
|---|
| 1365 | #define regDTBCLK_DTO1_PHASE_BASE_IDX 2 |
|---|
| 1366 | #define regDTBCLK_DTO2_PHASE 0x001a |
|---|
| 1367 | #define regDTBCLK_DTO2_PHASE_BASE_IDX 2 |
|---|
| 1368 | #define regDTBCLK_DTO3_PHASE 0x001b |
|---|
| 1369 | #define regDTBCLK_DTO3_PHASE_BASE_IDX 2 |
|---|
| 1370 | #define regDTBCLK_DTO0_MODULO 0x001f |
|---|
| 1371 | #define regDTBCLK_DTO0_MODULO_BASE_IDX 2 |
|---|
| 1372 | #define regDTBCLK_DTO1_MODULO 0x0020 |
|---|
| 1373 | #define regDTBCLK_DTO1_MODULO_BASE_IDX 2 |
|---|
| 1374 | #define regDTBCLK_DTO2_MODULO 0x0021 |
|---|
| 1375 | #define regDTBCLK_DTO2_MODULO_BASE_IDX 2 |
|---|
| 1376 | #define regDTBCLK_DTO3_MODULO 0x0022 |
|---|
| 1377 | #define regDTBCLK_DTO3_MODULO_BASE_IDX 2 |
|---|
| 1378 | #define regHDMICHARCLK0_CLOCK_CNTL 0x004a |
|---|
| 1379 | #define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2 |
|---|
| 1380 | #define regPHYASYMCLK_CLOCK_CNTL 0x0052 |
|---|
| 1381 | #define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 |
|---|
| 1382 | #define regPHYBSYMCLK_CLOCK_CNTL 0x0053 |
|---|
| 1383 | #define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 |
|---|
| 1384 | #define regPHYCSYMCLK_CLOCK_CNTL 0x0054 |
|---|
| 1385 | #define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 |
|---|
| 1386 | #define regPHYDSYMCLK_CLOCK_CNTL 0x0055 |
|---|
| 1387 | #define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 |
|---|
| 1388 | #define regPHYESYMCLK_CLOCK_CNTL 0x0056 |
|---|
| 1389 | #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 |
|---|
| 1390 | #define regHDMISTREAMCLK_CNTL 0x0059 |
|---|
| 1391 | #define regHDMISTREAMCLK_CNTL_BASE_IDX 2 |
|---|
| 1392 | #define regDCCG_GATE_DISABLE_CNTL3 0x005a |
|---|
| 1393 | #define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 |
|---|
| 1394 | #define regHDMISTREAMCLK0_DTO_PARAM 0x005b |
|---|
| 1395 | #define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2 |
|---|
| 1396 | #define regDCCG_AUDIO_DTBCLK_DTO_PHASE 0x0061 |
|---|
| 1397 | #define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX 2 |
|---|
| 1398 | #define regDCCG_AUDIO_DTBCLK_DTO_MODULO 0x0062 |
|---|
| 1399 | #define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX 2 |
|---|
| 1400 | #define regDTBCLK_DTO_DBUF_EN 0x0063 |
|---|
| 1401 | #define regDTBCLK_DTO_DBUF_EN_BASE_IDX 2 |
|---|
| 1402 | |
|---|
| 1403 | // addressBlock: dce_dc_dccg_dccg_dfs_dispdec |
|---|
| 1404 | // base address: 0x0 |
|---|
| 1405 | #define regDENTIST_DISPCLK_CNTL 0x0064 |
|---|
| 1406 | #define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 |
|---|
| 1407 | |
|---|
| 1408 | |
|---|
| 1409 | // addressBlock: azroot_f2codecind |
|---|
| 1410 | // base address: 0x0 |
|---|
| 1411 | #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 |
|---|
| 1412 | #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 |
|---|
| 1413 | #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 |
|---|
| 1414 | #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 |
|---|
| 1415 | #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 |
|---|
| 1416 | #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 |
|---|
| 1417 | #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 |
|---|
| 1418 | #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 |
|---|
| 1419 | #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 |
|---|
| 1420 | #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff |
|---|
| 1421 | #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 |
|---|
| 1422 | #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 |
|---|
| 1423 | #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a |
|---|
| 1424 | #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b |
|---|
| 1425 | #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f |
|---|
| 1426 | |
|---|
| 1427 | |
|---|
| 1428 | // addressBlock: azendpoint_f2codecind |
|---|
| 1429 | // base address: 0x0 |
|---|
| 1430 | #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 |
|---|
| 1431 | #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 |
|---|
| 1432 | #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d |
|---|
| 1433 | #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e |
|---|
| 1434 | #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 |
|---|
| 1435 | #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e |
|---|
| 1436 | #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 |
|---|
| 1437 | #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 |
|---|
| 1438 | #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 |
|---|
| 1439 | #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a |
|---|
| 1440 | #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b |
|---|
| 1441 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 |
|---|
| 1442 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 |
|---|
| 1443 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 |
|---|
| 1444 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 |
|---|
| 1445 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c |
|---|
| 1446 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d |
|---|
| 1447 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e |
|---|
| 1448 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f |
|---|
| 1449 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 |
|---|
| 1450 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 |
|---|
| 1451 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 |
|---|
| 1452 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 |
|---|
| 1453 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 |
|---|
| 1454 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 |
|---|
| 1455 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 |
|---|
| 1456 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 |
|---|
| 1457 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a |
|---|
| 1458 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b |
|---|
| 1459 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c |
|---|
| 1460 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 |
|---|
| 1461 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 |
|---|
| 1462 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 |
|---|
| 1463 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 |
|---|
| 1464 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 |
|---|
| 1465 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 |
|---|
| 1466 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 |
|---|
| 1467 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a |
|---|
| 1468 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b |
|---|
| 1469 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c |
|---|
| 1470 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d |
|---|
| 1471 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e |
|---|
| 1472 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f |
|---|
| 1473 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 |
|---|
| 1474 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 |
|---|
| 1475 | #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 |
|---|
| 1476 | #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 |
|---|
| 1477 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 |
|---|
| 1478 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 |
|---|
| 1479 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 |
|---|
| 1480 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a |
|---|
| 1481 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b |
|---|
| 1482 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c |
|---|
| 1483 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d |
|---|
| 1484 | #define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e |
|---|
| 1485 | #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 |
|---|
| 1486 | #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c |
|---|
| 1487 | #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e |
|---|
| 1488 | |
|---|
| 1489 | |
|---|
| 1490 | // addressBlock: azinputendpoint_f2codecind |
|---|
| 1491 | // base address: 0x0 |
|---|
| 1492 | #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 |
|---|
| 1493 | #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 |
|---|
| 1494 | #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d |
|---|
| 1495 | #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 |
|---|
| 1496 | #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a |
|---|
| 1497 | #define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b |
|---|
| 1498 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 |
|---|
| 1499 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 |
|---|
| 1500 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 |
|---|
| 1501 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c |
|---|
| 1502 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d |
|---|
| 1503 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e |
|---|
| 1504 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f |
|---|
| 1505 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 |
|---|
| 1506 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 |
|---|
| 1507 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 |
|---|
| 1508 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 |
|---|
| 1509 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a |
|---|
| 1510 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c |
|---|
| 1511 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 |
|---|
| 1512 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 |
|---|
| 1513 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 |
|---|
| 1514 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 |
|---|
| 1515 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 |
|---|
| 1516 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 |
|---|
| 1517 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a |
|---|
| 1518 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b |
|---|
| 1519 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c |
|---|
| 1520 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d |
|---|
| 1521 | #define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e |
|---|
| 1522 | #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 |
|---|
| 1523 | #define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c |
|---|
| 1524 | |
|---|
| 1525 | |
|---|
| 1526 | // addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec |
|---|
| 1527 | // base address: 0x0 |
|---|
| 1528 | #define regDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 |
|---|
| 1529 | #define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 1530 | #define regDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 |
|---|
| 1531 | #define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 1532 | #define regDC_PERFMON0_PERFCOUNTER_STATE 0x0002 |
|---|
| 1533 | #define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 1534 | #define regDC_PERFMON0_PERFMON_CNTL 0x0003 |
|---|
| 1535 | #define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 1536 | #define regDC_PERFMON0_PERFMON_CNTL2 0x0004 |
|---|
| 1537 | #define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 1538 | #define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 |
|---|
| 1539 | #define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 1540 | #define regDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 |
|---|
| 1541 | #define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 1542 | #define regDC_PERFMON0_PERFMON_HI 0x0007 |
|---|
| 1543 | #define regDC_PERFMON0_PERFMON_HI_BASE_IDX 2 |
|---|
| 1544 | #define regDC_PERFMON0_PERFMON_LOW 0x0008 |
|---|
| 1545 | #define regDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 |
|---|
| 1546 | |
|---|
| 1547 | |
|---|
| 1548 | // addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec |
|---|
| 1549 | // base address: 0x30 |
|---|
| 1550 | #define regDC_PERFMON1_PERFCOUNTER_CNTL 0x000c |
|---|
| 1551 | #define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 1552 | #define regDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d |
|---|
| 1553 | #define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 1554 | #define regDC_PERFMON1_PERFCOUNTER_STATE 0x000e |
|---|
| 1555 | #define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 1556 | #define regDC_PERFMON1_PERFMON_CNTL 0x000f |
|---|
| 1557 | #define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 1558 | #define regDC_PERFMON1_PERFMON_CNTL2 0x0010 |
|---|
| 1559 | #define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 1560 | #define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 |
|---|
| 1561 | #define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 1562 | #define regDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 |
|---|
| 1563 | #define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 1564 | #define regDC_PERFMON1_PERFMON_HI 0x0013 |
|---|
| 1565 | #define regDC_PERFMON1_PERFMON_HI_BASE_IDX 2 |
|---|
| 1566 | #define regDC_PERFMON1_PERFMON_LOW 0x0014 |
|---|
| 1567 | #define regDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 |
|---|
| 1568 | |
|---|
| 1569 | |
|---|
| 1570 | // addressBlock: dce_dc_dmu_dc_pg_dispdec |
|---|
| 1571 | // base address: 0x0 |
|---|
| 1572 | #define regDOMAIN0_PG_CONFIG 0x0080 |
|---|
| 1573 | #define regDOMAIN0_PG_CONFIG_BASE_IDX 2 |
|---|
| 1574 | #define regDOMAIN0_PG_STATUS 0x0081 |
|---|
| 1575 | #define regDOMAIN0_PG_STATUS_BASE_IDX 2 |
|---|
| 1576 | #define regDOMAIN1_PG_CONFIG 0x0082 |
|---|
| 1577 | #define regDOMAIN1_PG_CONFIG_BASE_IDX 2 |
|---|
| 1578 | #define regDOMAIN1_PG_STATUS 0x0083 |
|---|
| 1579 | #define regDOMAIN1_PG_STATUS_BASE_IDX 2 |
|---|
| 1580 | #define regDOMAIN2_PG_CONFIG 0x0084 |
|---|
| 1581 | #define regDOMAIN2_PG_CONFIG_BASE_IDX 2 |
|---|
| 1582 | #define regDOMAIN2_PG_STATUS 0x0085 |
|---|
| 1583 | #define regDOMAIN2_PG_STATUS_BASE_IDX 2 |
|---|
| 1584 | #define regDOMAIN3_PG_CONFIG 0x0086 |
|---|
| 1585 | #define regDOMAIN3_PG_CONFIG_BASE_IDX 2 |
|---|
| 1586 | #define regDOMAIN3_PG_STATUS 0x0087 |
|---|
| 1587 | #define regDOMAIN3_PG_STATUS_BASE_IDX 2 |
|---|
| 1588 | #define regDOMAIN16_PG_CONFIG 0x0089 |
|---|
| 1589 | #define regDOMAIN16_PG_CONFIG_BASE_IDX 2 |
|---|
| 1590 | #define regDOMAIN16_PG_STATUS 0x008a |
|---|
| 1591 | #define regDOMAIN16_PG_STATUS_BASE_IDX 2 |
|---|
| 1592 | #define regDOMAIN17_PG_CONFIG 0x008b |
|---|
| 1593 | #define regDOMAIN17_PG_CONFIG_BASE_IDX 2 |
|---|
| 1594 | #define regDOMAIN17_PG_STATUS 0x008c |
|---|
| 1595 | #define regDOMAIN17_PG_STATUS_BASE_IDX 2 |
|---|
| 1596 | #define regDOMAIN18_PG_CONFIG 0x008d |
|---|
| 1597 | #define regDOMAIN18_PG_CONFIG_BASE_IDX 2 |
|---|
| 1598 | #define regDOMAIN18_PG_STATUS 0x008e |
|---|
| 1599 | #define regDOMAIN18_PG_STATUS_BASE_IDX 2 |
|---|
| 1600 | #define regDOMAIN19_PG_CONFIG 0x008f |
|---|
| 1601 | #define regDOMAIN19_PG_CONFIG_BASE_IDX 2 |
|---|
| 1602 | #define regDOMAIN19_PG_STATUS 0x0090 |
|---|
| 1603 | #define regDOMAIN19_PG_STATUS_BASE_IDX 2 |
|---|
| 1604 | #define regDOMAIN22_PG_CONFIG 0x0092 |
|---|
| 1605 | #define regDOMAIN22_PG_CONFIG_BASE_IDX 2 |
|---|
| 1606 | #define regDOMAIN22_PG_STATUS 0x0093 |
|---|
| 1607 | #define regDOMAIN22_PG_STATUS_BASE_IDX 2 |
|---|
| 1608 | #define regDOMAIN23_PG_CONFIG 0x0094 |
|---|
| 1609 | #define regDOMAIN23_PG_CONFIG_BASE_IDX 2 |
|---|
| 1610 | #define regDOMAIN23_PG_STATUS 0x0095 |
|---|
| 1611 | #define regDOMAIN23_PG_STATUS_BASE_IDX 2 |
|---|
| 1612 | #define regDOMAIN24_PG_CONFIG 0x0096 |
|---|
| 1613 | #define regDOMAIN24_PG_CONFIG_BASE_IDX 2 |
|---|
| 1614 | #define regDOMAIN24_PG_STATUS 0x0097 |
|---|
| 1615 | #define regDOMAIN24_PG_STATUS_BASE_IDX 2 |
|---|
| 1616 | #define regDOMAIN25_PG_CONFIG 0x0098 |
|---|
| 1617 | #define regDOMAIN25_PG_CONFIG_BASE_IDX 2 |
|---|
| 1618 | #define regDOMAIN25_PG_STATUS 0x0099 |
|---|
| 1619 | #define regDOMAIN25_PG_STATUS_BASE_IDX 2 |
|---|
| 1620 | #define regDCPG_INTERRUPT_STATUS 0x009a |
|---|
| 1621 | #define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 |
|---|
| 1622 | #define regDCPG_INTERRUPT_STATUS_2 0x009b |
|---|
| 1623 | #define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 |
|---|
| 1624 | #define regDCPG_INTERRUPT_STATUS_3 0x009c |
|---|
| 1625 | #define regDCPG_INTERRUPT_STATUS_3_BASE_IDX 2 |
|---|
| 1626 | #define regDCPG_INTERRUPT_CONTROL_1 0x009d |
|---|
| 1627 | #define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 |
|---|
| 1628 | #define regDCPG_INTERRUPT_CONTROL_2 0x009e |
|---|
| 1629 | #define regDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2 |
|---|
| 1630 | #define regDCPG_INTERRUPT_CONTROL_3 0x009f |
|---|
| 1631 | #define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 |
|---|
| 1632 | #define regDC_IP_REQUEST_CNTL 0x00a0 |
|---|
| 1633 | #define regDC_IP_REQUEST_CNTL_BASE_IDX 2 |
|---|
| 1634 | #define regLONO_MEM_PWR_REQ_CNTL 0x00a4 |
|---|
| 1635 | #define regLONO_MEM_PWR_REQ_CNTL_BASE_IDX 2 |
|---|
| 1636 | |
|---|
| 1637 | |
|---|
| 1638 | // addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec |
|---|
| 1639 | // base address: 0x2f8 |
|---|
| 1640 | #define regDC_PERFMON2_PERFCOUNTER_CNTL 0x00be |
|---|
| 1641 | #define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 1642 | #define regDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf |
|---|
| 1643 | #define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 1644 | #define regDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 |
|---|
| 1645 | #define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 1646 | #define regDC_PERFMON2_PERFMON_CNTL 0x00c1 |
|---|
| 1647 | #define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 1648 | #define regDC_PERFMON2_PERFMON_CNTL2 0x00c2 |
|---|
| 1649 | #define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 1650 | #define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 |
|---|
| 1651 | #define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 1652 | #define regDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 |
|---|
| 1653 | #define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 1654 | #define regDC_PERFMON2_PERFMON_HI 0x00c5 |
|---|
| 1655 | #define regDC_PERFMON2_PERFMON_HI_BASE_IDX 2 |
|---|
| 1656 | #define regDC_PERFMON2_PERFMON_LOW 0x00c6 |
|---|
| 1657 | #define regDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 |
|---|
| 1658 | |
|---|
| 1659 | |
|---|
| 1660 | // addressBlock: dce_dc_dmu_dmu_misc_dispdec |
|---|
| 1661 | // base address: 0x0 |
|---|
| 1662 | #define regCC_DC_PIPE_DIS 0x00ca |
|---|
| 1663 | #define regCC_DC_PIPE_DIS_BASE_IDX 2 |
|---|
| 1664 | #define regDMU_CLK_CNTL 0x00cb |
|---|
| 1665 | #define regDMU_CLK_CNTL_BASE_IDX 2 |
|---|
| 1666 | #define regDMCUB_SMU_INTERRUPT_CNTL 0x00cd |
|---|
| 1667 | #define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX 2 |
|---|
| 1668 | #define regSMU_INTERRUPT_CONTROL 0x00ce |
|---|
| 1669 | #define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 |
|---|
| 1670 | #define regZSC_CNTL 0x00cf |
|---|
| 1671 | #define regZSC_CNTL_BASE_IDX 2 |
|---|
| 1672 | #define regZSC_CNTL2 0x00d0 |
|---|
| 1673 | #define regZSC_CNTL2_BASE_IDX 2 |
|---|
| 1674 | #define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 |
|---|
| 1675 | #define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 |
|---|
| 1676 | #define regZSC_STATUS 0x00d7 |
|---|
| 1677 | #define regZSC_STATUS_BASE_IDX 2 |
|---|
| 1678 | #define regDMU_DISPCLK_CGTT_BLK_CTRL_REG 0x00d8 |
|---|
| 1679 | #define regDMU_DISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 2 |
|---|
| 1680 | #define regDMU_SOCCLK_CGTT_BLK_CTRL_REG 0x00d9 |
|---|
| 1681 | #define regDMU_SOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 2 |
|---|
| 1682 | #define regZPR_CLK_UNGATE_DELAY 0x00da |
|---|
| 1683 | #define regZPR_CLK_UNGATE_DELAY_BASE_IDX 2 |
|---|
| 1684 | |
|---|
| 1685 | |
|---|
| 1686 | |
|---|
| 1687 | // addressBlock: dce_dc_dmu_ihc_dispdec |
|---|
| 1688 | // base address: 0x0 |
|---|
| 1689 | #define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 |
|---|
| 1690 | #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 |
|---|
| 1691 | #define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 |
|---|
| 1692 | #define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 |
|---|
| 1693 | #define regDC_GPU_TIMER_READ 0x0128 |
|---|
| 1694 | #define regDC_GPU_TIMER_READ_BASE_IDX 2 |
|---|
| 1695 | #define regDC_GPU_TIMER_READ_CNTL 0x0129 |
|---|
| 1696 | #define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 |
|---|
| 1697 | #define regDISP_INTERRUPT_STATUS 0x012a |
|---|
| 1698 | #define regDISP_INTERRUPT_STATUS_BASE_IDX 2 |
|---|
| 1699 | #define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b |
|---|
| 1700 | #define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 |
|---|
| 1701 | #define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c |
|---|
| 1702 | #define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 |
|---|
| 1703 | #define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d |
|---|
| 1704 | #define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 |
|---|
| 1705 | #define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e |
|---|
| 1706 | #define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 |
|---|
| 1707 | #define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f |
|---|
| 1708 | #define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 |
|---|
| 1709 | #define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 |
|---|
| 1710 | #define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 |
|---|
| 1711 | #define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 |
|---|
| 1712 | #define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 |
|---|
| 1713 | #define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 |
|---|
| 1714 | #define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 |
|---|
| 1715 | #define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 |
|---|
| 1716 | #define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 |
|---|
| 1717 | #define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 |
|---|
| 1718 | #define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 |
|---|
| 1719 | #define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 |
|---|
| 1720 | #define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 |
|---|
| 1721 | #define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 |
|---|
| 1722 | #define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 |
|---|
| 1723 | #define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 |
|---|
| 1724 | #define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 |
|---|
| 1725 | #define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 |
|---|
| 1726 | #define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 |
|---|
| 1727 | #define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 |
|---|
| 1728 | #define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 |
|---|
| 1729 | #define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a |
|---|
| 1730 | #define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 |
|---|
| 1731 | #define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b |
|---|
| 1732 | #define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 |
|---|
| 1733 | #define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c |
|---|
| 1734 | #define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 |
|---|
| 1735 | #define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d |
|---|
| 1736 | #define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 |
|---|
| 1737 | #define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e |
|---|
| 1738 | #define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 |
|---|
| 1739 | #define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f |
|---|
| 1740 | #define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 |
|---|
| 1741 | #define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 |
|---|
| 1742 | #define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 |
|---|
| 1743 | #define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 |
|---|
| 1744 | #define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 |
|---|
| 1745 | #define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 |
|---|
| 1746 | #define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 |
|---|
| 1747 | #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 |
|---|
| 1748 | #define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 |
|---|
| 1749 | #define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 |
|---|
| 1750 | #define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 |
|---|
| 1751 | #define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 |
|---|
| 1752 | #define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 |
|---|
| 1753 | #define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 |
|---|
| 1754 | #define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 |
|---|
| 1755 | #define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 |
|---|
| 1756 | #define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 |
|---|
| 1757 | #define regDCCG_INTERRUPT_DEST 0x0148 |
|---|
| 1758 | #define regDCCG_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1759 | #define regDMU_INTERRUPT_DEST 0x0149 |
|---|
| 1760 | #define regDMU_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1761 | #define regDMU_INTERRUPT_DEST2 0x014a |
|---|
| 1762 | #define regDMU_INTERRUPT_DEST2_BASE_IDX 2 |
|---|
| 1763 | #define regDCPG_INTERRUPT_DEST 0x014b |
|---|
| 1764 | #define regDCPG_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1765 | #define regDCPG_INTERRUPT_DEST2 0x014c |
|---|
| 1766 | #define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 |
|---|
| 1767 | #define regMMHUBBUB_INTERRUPT_DEST 0x014d |
|---|
| 1768 | #define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1769 | #define regWB_INTERRUPT_DEST 0x014e |
|---|
| 1770 | #define regWB_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1771 | #define regDCHUB_INTERRUPT_DEST 0x014f |
|---|
| 1772 | #define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1773 | #define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 |
|---|
| 1774 | #define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1775 | #define regDCHUB_INTERRUPT_DEST2 0x0151 |
|---|
| 1776 | #define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 |
|---|
| 1777 | #define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 |
|---|
| 1778 | #define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1779 | #define regMPC_INTERRUPT_DEST 0x0153 |
|---|
| 1780 | #define regMPC_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1781 | #define regOPP_INTERRUPT_DEST 0x0154 |
|---|
| 1782 | #define regOPP_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1783 | #define regOPTC_INTERRUPT_DEST 0x0155 |
|---|
| 1784 | #define regOPTC_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1785 | #define regOTG0_INTERRUPT_DEST 0x0156 |
|---|
| 1786 | #define regOTG0_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1787 | #define regOTG1_INTERRUPT_DEST 0x0157 |
|---|
| 1788 | #define regOTG1_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1789 | #define regOTG2_INTERRUPT_DEST 0x0158 |
|---|
| 1790 | #define regOTG2_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1791 | #define regOTG3_INTERRUPT_DEST 0x0159 |
|---|
| 1792 | #define regOTG3_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1793 | #define regOTG4_INTERRUPT_DEST 0x015a |
|---|
| 1794 | #define regOTG4_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1795 | #define regOTG5_INTERRUPT_DEST 0x015b |
|---|
| 1796 | #define regOTG5_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1797 | #define regDIG_INTERRUPT_DEST 0x015c |
|---|
| 1798 | #define regDIG_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1799 | #define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d |
|---|
| 1800 | #define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1801 | #define regDIO_INTERRUPT_DEST 0x015f |
|---|
| 1802 | #define regDIO_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1803 | #define regDCIO_INTERRUPT_DEST 0x0160 |
|---|
| 1804 | #define regDCIO_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1805 | #define regHPD_INTERRUPT_DEST 0x0161 |
|---|
| 1806 | #define regHPD_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1807 | #define regAZ_INTERRUPT_DEST 0x0162 |
|---|
| 1808 | #define regAZ_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1809 | #define regAUX_INTERRUPT_DEST 0x0163 |
|---|
| 1810 | #define regAUX_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1811 | #define regDSC_INTERRUPT_DEST 0x0164 |
|---|
| 1812 | #define regDSC_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1813 | #define regHPO_INTERRUPT_DEST 0x0165 |
|---|
| 1814 | #define regHPO_INTERRUPT_DEST_BASE_IDX 2 |
|---|
| 1815 | |
|---|
| 1816 | |
|---|
| 1817 | // addressBlock: dce_dc_dmu_fgsec_dispdec |
|---|
| 1818 | // base address: 0x0 |
|---|
| 1819 | #define regDMCUB_RBBMIF_SEC_CNTL 0x017a |
|---|
| 1820 | #define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 |
|---|
| 1821 | |
|---|
| 1822 | |
|---|
| 1823 | // addressBlock: dce_dc_dmu_rbbmif_dispdec |
|---|
| 1824 | // base address: 0x0 |
|---|
| 1825 | #define regRBBMIF_TIMEOUT 0x017f |
|---|
| 1826 | #define regRBBMIF_TIMEOUT_BASE_IDX 2 |
|---|
| 1827 | #define regRBBMIF_STATUS 0x0180 |
|---|
| 1828 | #define regRBBMIF_STATUS_BASE_IDX 2 |
|---|
| 1829 | #define regRBBMIF_STATUS_2 0x0181 |
|---|
| 1830 | #define regRBBMIF_STATUS_2_BASE_IDX 2 |
|---|
| 1831 | #define regRBBMIF_INT_STATUS 0x0182 |
|---|
| 1832 | #define regRBBMIF_INT_STATUS_BASE_IDX 2 |
|---|
| 1833 | #define regRBBMIF_TIMEOUT_DIS 0x0183 |
|---|
| 1834 | #define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 |
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| 1835 | #define regRBBMIF_TIMEOUT_DIS_2 0x0184 |
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| 1836 | #define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 |
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| 1837 | #define regRBBMIF_STATUS_FLAG 0x0185 |
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| 1838 | #define regRBBMIF_STATUS_FLAG_BASE_IDX 2 |
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| 1839 | |
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| 1840 | |
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| 1841 | // addressBlock: dce_dc_dmu_dmcub_dispdec |
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| 1842 | // base address: 0x0 |
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| 1843 | #define regDMCUB_REGION0_OFFSET 0x018e |
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| 1844 | #define regDMCUB_REGION0_OFFSET_BASE_IDX 2 |
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| 1845 | #define regDMCUB_REGION0_OFFSET_HIGH 0x018f |
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| 1846 | #define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 |
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| 1847 | #define regDMCUB_REGION1_OFFSET 0x0190 |
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| 1848 | #define regDMCUB_REGION1_OFFSET_BASE_IDX 2 |
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| 1849 | #define regDMCUB_REGION1_OFFSET_HIGH 0x0191 |
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| 1850 | #define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 |
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| 1851 | #define regDMCUB_REGION2_OFFSET 0x0192 |
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| 1852 | #define regDMCUB_REGION2_OFFSET_BASE_IDX 2 |
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| 1853 | #define regDMCUB_REGION2_OFFSET_HIGH 0x0193 |
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| 1854 | #define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 |
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| 1855 | #define regDMCUB_REGION4_OFFSET 0x0196 |
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| 1856 | #define regDMCUB_REGION4_OFFSET_BASE_IDX 2 |
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| 1857 | #define regDMCUB_REGION4_OFFSET_HIGH 0x0197 |
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| 1858 | #define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 |
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| 1859 | #define regDMCUB_REGION5_OFFSET 0x0198 |
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| 1860 | #define regDMCUB_REGION5_OFFSET_BASE_IDX 2 |
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| 1861 | #define regDMCUB_REGION5_OFFSET_HIGH 0x0199 |
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| 1862 | #define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 |
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| 1863 | #define regDMCUB_REGION6_OFFSET 0x019a |
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| 1864 | #define regDMCUB_REGION6_OFFSET_BASE_IDX 2 |
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| 1865 | #define regDMCUB_REGION6_OFFSET_HIGH 0x019b |
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| 1866 | #define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 |
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| 1867 | #define regDMCUB_REGION7_OFFSET 0x019c |
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| 1868 | #define regDMCUB_REGION7_OFFSET_BASE_IDX 2 |
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| 1869 | #define regDMCUB_REGION7_OFFSET_HIGH 0x019d |
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| 1870 | #define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 |
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| 1871 | #define regDMCUB_REGION0_TOP_ADDRESS 0x019e |
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| 1872 | #define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 |
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| 1873 | #define regDMCUB_REGION1_TOP_ADDRESS 0x019f |
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| 1874 | #define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 |
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| 1875 | #define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 |
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| 1876 | #define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 |
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| 1877 | #define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 |
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| 1878 | #define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 |
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| 1879 | #define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 |
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| 1880 | #define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 |
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| 1881 | #define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 |
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| 1882 | #define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 |
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| 1883 | #define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 |
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| 1884 | #define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 |
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| 1885 | #define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 |
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| 1886 | #define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 |
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| 1887 | #define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 |
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| 1888 | #define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 |
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| 1889 | #define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 |
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| 1890 | #define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 |
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| 1891 | #define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 |
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| 1892 | #define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 |
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| 1893 | #define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 |
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| 1894 | #define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 |
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| 1895 | #define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa |
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| 1896 | #define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 |
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| 1897 | #define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab |
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| 1898 | #define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 |
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| 1899 | #define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac |
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| 1900 | #define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 |
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| 1901 | #define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad |
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| 1902 | #define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 |
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| 1903 | #define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae |
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| 1904 | #define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 |
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| 1905 | #define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af |
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| 1906 | #define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 |
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| 1907 | #define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 |
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| 1908 | #define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 |
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| 1909 | #define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 |
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| 1910 | #define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 |
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| 1911 | #define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 |
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| 1912 | #define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 |
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| 1913 | #define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 |
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| 1914 | #define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 |
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| 1915 | #define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 |
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| 1916 | #define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 |
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| 1917 | #define regDMCUB_REGION3_CW0_OFFSET 0x01b5 |
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| 1918 | #define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 |
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| 1919 | #define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 |
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| 1920 | #define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 |
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| 1921 | #define regDMCUB_REGION3_CW1_OFFSET 0x01b7 |
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| 1922 | #define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 |
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| 1923 | #define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 |
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| 1924 | #define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 |
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| 1925 | #define regDMCUB_REGION3_CW2_OFFSET 0x01b9 |
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| 1926 | #define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 |
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| 1927 | #define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba |
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| 1928 | #define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 |
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| 1929 | #define regDMCUB_REGION3_CW3_OFFSET 0x01bb |
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| 1930 | #define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 |
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| 1931 | #define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc |
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| 1932 | #define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 |
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| 1933 | #define regDMCUB_REGION3_CW4_OFFSET 0x01bd |
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| 1934 | #define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 |
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| 1935 | #define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be |
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| 1936 | #define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 |
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| 1937 | #define regDMCUB_REGION3_CW5_OFFSET 0x01bf |
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| 1938 | #define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 |
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| 1939 | #define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 |
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| 1940 | #define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 |
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| 1941 | #define regDMCUB_REGION3_CW6_OFFSET 0x01c1 |
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| 1942 | #define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 |
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| 1943 | #define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 |
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| 1944 | #define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 |
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| 1945 | #define regDMCUB_REGION3_CW7_OFFSET 0x01c3 |
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| 1946 | #define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 |
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| 1947 | #define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 |
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| 1948 | #define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 |
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| 1949 | #define regDMCUB_INTERRUPT_ENABLE 0x01c5 |
|---|
| 1950 | #define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 |
|---|
| 1951 | #define regDMCUB_INTERRUPT_ACK 0x01c6 |
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| 1952 | #define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 |
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| 1953 | #define regDMCUB_INTERRUPT_STATUS 0x01c7 |
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| 1954 | #define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 |
|---|
| 1955 | #define regDMCUB_INTERRUPT_TYPE 0x01c8 |
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| 1956 | #define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 |
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| 1957 | #define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 |
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| 1958 | #define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 |
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| 1959 | #define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca |
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| 1960 | #define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 |
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| 1961 | #define regDMCUB_EXT_INTERRUPT_ACK 0x01cb |
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| 1962 | #define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 |
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| 1963 | #define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc |
|---|
| 1964 | #define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 |
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| 1965 | #define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd |
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| 1966 | #define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 |
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| 1967 | #define regDMCUB_SEC_CNTL 0x01ce |
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| 1968 | #define regDMCUB_SEC_CNTL_BASE_IDX 2 |
|---|
| 1969 | #define regDMCUB_MEM_CNTL 0x01cf |
|---|
| 1970 | #define regDMCUB_MEM_CNTL_BASE_IDX 2 |
|---|
| 1971 | #define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 |
|---|
| 1972 | #define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 |
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| 1973 | #define regDMCUB_INBOX0_SIZE 0x01d1 |
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| 1974 | #define regDMCUB_INBOX0_SIZE_BASE_IDX 2 |
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| 1975 | #define regDMCUB_INBOX0_WPTR 0x01d2 |
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| 1976 | #define regDMCUB_INBOX0_WPTR_BASE_IDX 2 |
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| 1977 | #define regDMCUB_INBOX0_RPTR 0x01d3 |
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| 1978 | #define regDMCUB_INBOX0_RPTR_BASE_IDX 2 |
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| 1979 | #define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 |
|---|
| 1980 | #define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 |
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| 1981 | #define regDMCUB_INBOX1_SIZE 0x01d5 |
|---|
| 1982 | #define regDMCUB_INBOX1_SIZE_BASE_IDX 2 |
|---|
| 1983 | #define regDMCUB_INBOX1_WPTR 0x01d6 |
|---|
| 1984 | #define regDMCUB_INBOX1_WPTR_BASE_IDX 2 |
|---|
| 1985 | #define regDMCUB_INBOX1_RPTR 0x01d7 |
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| 1986 | #define regDMCUB_INBOX1_RPTR_BASE_IDX 2 |
|---|
| 1987 | #define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 |
|---|
| 1988 | #define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 |
|---|
| 1989 | #define regDMCUB_OUTBOX0_SIZE 0x01d9 |
|---|
| 1990 | #define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 |
|---|
| 1991 | #define regDMCUB_OUTBOX0_WPTR 0x01da |
|---|
| 1992 | #define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 |
|---|
| 1993 | #define regDMCUB_OUTBOX0_RPTR 0x01db |
|---|
| 1994 | #define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 |
|---|
| 1995 | #define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc |
|---|
| 1996 | #define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 |
|---|
| 1997 | #define regDMCUB_OUTBOX1_SIZE 0x01dd |
|---|
| 1998 | #define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 |
|---|
| 1999 | #define regDMCUB_OUTBOX1_WPTR 0x01de |
|---|
| 2000 | #define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 |
|---|
| 2001 | #define regDMCUB_OUTBOX1_RPTR 0x01df |
|---|
| 2002 | #define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 |
|---|
| 2003 | #define regDMCUB_TIMER_TRIGGER0 0x01e0 |
|---|
| 2004 | #define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 |
|---|
| 2005 | #define regDMCUB_TIMER_TRIGGER1 0x01e1 |
|---|
| 2006 | #define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 |
|---|
| 2007 | #define regDMCUB_TIMER_WINDOW 0x01e2 |
|---|
| 2008 | #define regDMCUB_TIMER_WINDOW_BASE_IDX 2 |
|---|
| 2009 | #define regDMCUB_SCRATCH0 0x01e3 |
|---|
| 2010 | #define regDMCUB_SCRATCH0_BASE_IDX 2 |
|---|
| 2011 | #define regDMCUB_SCRATCH1 0x01e4 |
|---|
| 2012 | #define regDMCUB_SCRATCH1_BASE_IDX 2 |
|---|
| 2013 | #define regDMCUB_SCRATCH2 0x01e5 |
|---|
| 2014 | #define regDMCUB_SCRATCH2_BASE_IDX 2 |
|---|
| 2015 | #define regDMCUB_SCRATCH3 0x01e6 |
|---|
| 2016 | #define regDMCUB_SCRATCH3_BASE_IDX 2 |
|---|
| 2017 | #define regDMCUB_SCRATCH4 0x01e7 |
|---|
| 2018 | #define regDMCUB_SCRATCH4_BASE_IDX 2 |
|---|
| 2019 | #define regDMCUB_SCRATCH5 0x01e8 |
|---|
| 2020 | #define regDMCUB_SCRATCH5_BASE_IDX 2 |
|---|
| 2021 | #define regDMCUB_SCRATCH6 0x01e9 |
|---|
| 2022 | #define regDMCUB_SCRATCH6_BASE_IDX 2 |
|---|
| 2023 | #define regDMCUB_SCRATCH7 0x01ea |
|---|
| 2024 | #define regDMCUB_SCRATCH7_BASE_IDX 2 |
|---|
| 2025 | #define regDMCUB_SCRATCH8 0x01eb |
|---|
| 2026 | #define regDMCUB_SCRATCH8_BASE_IDX 2 |
|---|
| 2027 | #define regDMCUB_SCRATCH9 0x01ec |
|---|
| 2028 | #define regDMCUB_SCRATCH9_BASE_IDX 2 |
|---|
| 2029 | #define regDMCUB_SCRATCH10 0x01ed |
|---|
| 2030 | #define regDMCUB_SCRATCH10_BASE_IDX 2 |
|---|
| 2031 | #define regDMCUB_SCRATCH11 0x01ee |
|---|
| 2032 | #define regDMCUB_SCRATCH11_BASE_IDX 2 |
|---|
| 2033 | #define regDMCUB_SCRATCH12 0x01ef |
|---|
| 2034 | #define regDMCUB_SCRATCH12_BASE_IDX 2 |
|---|
| 2035 | #define regDMCUB_SCRATCH13 0x01f0 |
|---|
| 2036 | #define regDMCUB_SCRATCH13_BASE_IDX 2 |
|---|
| 2037 | #define regDMCUB_SCRATCH14 0x01f1 |
|---|
| 2038 | #define regDMCUB_SCRATCH14_BASE_IDX 2 |
|---|
| 2039 | #define regDMCUB_SCRATCH15 0x01f2 |
|---|
| 2040 | #define regDMCUB_SCRATCH15_BASE_IDX 2 |
|---|
| 2041 | #define regDMCUB_SCRATCH16 0x01f3 |
|---|
| 2042 | #define regDMCUB_SCRATCH16_BASE_IDX 2 |
|---|
| 2043 | #define regDMCUB_SCRATCH17 0x01f4 |
|---|
| 2044 | #define regDMCUB_SCRATCH17_BASE_IDX 2 |
|---|
| 2045 | #define regDMCUB_SCRATCH18 0x01f5 |
|---|
| 2046 | #define regDMCUB_SCRATCH18_BASE_IDX 2 |
|---|
| 2047 | #define regDMCUB_CNTL 0x01f6 |
|---|
| 2048 | #define regDMCUB_CNTL_BASE_IDX 2 |
|---|
| 2049 | #define regDMCUB_GPINT_DATAIN0 0x01f7 |
|---|
| 2050 | #define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 |
|---|
| 2051 | #define regDMCUB_GPINT_DATAIN1 0x01f8 |
|---|
| 2052 | #define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 |
|---|
| 2053 | #define regDMCUB_GPINT_DATAOUT 0x01f9 |
|---|
| 2054 | #define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 |
|---|
| 2055 | #define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa |
|---|
| 2056 | #define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 |
|---|
| 2057 | #define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb |
|---|
| 2058 | #define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 |
|---|
| 2059 | #define regDMCUB_MEM_PWR_CNTL 0x01fc |
|---|
| 2060 | #define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 |
|---|
| 2061 | #define regDMCUB_TIMER_CURRENT 0x01fd |
|---|
| 2062 | #define regDMCUB_TIMER_CURRENT_BASE_IDX 2 |
|---|
| 2063 | #define regDMCUB_PROC_ID 0x01ff |
|---|
| 2064 | #define regDMCUB_PROC_ID_BASE_IDX 2 |
|---|
| 2065 | #define regDMCUB_CNTL2 0x0200 |
|---|
| 2066 | #define regDMCUB_CNTL2_BASE_IDX 2 |
|---|
| 2067 | #define regDMCUB_GPINT_DATAIN2 0x0215 |
|---|
| 2068 | #define regDMCUB_GPINT_DATAIN2_BASE_IDX 2 |
|---|
| 2069 | #define regDMCUB_GPINT_DATAIN3 0x0216 |
|---|
| 2070 | #define regDMCUB_GPINT_DATAIN3_BASE_IDX 2 |
|---|
| 2071 | #define regDMCUB_GPINT_DATAIN4 0x0217 |
|---|
| 2072 | #define regDMCUB_GPINT_DATAIN4_BASE_IDX 2 |
|---|
| 2073 | #define regDMCUB_GPINT_DATAIN5 0x0218 |
|---|
| 2074 | #define regDMCUB_GPINT_DATAIN5_BASE_IDX 2 |
|---|
| 2075 | #define regDMCUB_GPINT_DATAIN6 0x0219 |
|---|
| 2076 | #define regDMCUB_GPINT_DATAIN6_BASE_IDX 2 |
|---|
| 2077 | #define regDMCUB_REGION3_TMR_AXI_SPACE 0x021a |
|---|
| 2078 | #define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX 2 |
|---|
| 2079 | #define regDMCUB_SCRATCH19 0x022e |
|---|
| 2080 | #define regDMCUB_SCRATCH19_BASE_IDX 2 |
|---|
| 2081 | #define regDMCUB_SCRATCH20 0x022f |
|---|
| 2082 | #define regDMCUB_SCRATCH20_BASE_IDX 2 |
|---|
| 2083 | #define regDMCUB_SCRATCH21 0x0230 |
|---|
| 2084 | #define regDMCUB_SCRATCH21_BASE_IDX 2 |
|---|
| 2085 | #define regDMCUB_SCRATCH22 0x0231 |
|---|
| 2086 | #define regDMCUB_SCRATCH22_BASE_IDX 2 |
|---|
| 2087 | #define regDMCUB_SCRATCH23 0x0232 |
|---|
| 2088 | #define regDMCUB_SCRATCH23_BASE_IDX 2 |
|---|
| 2089 | |
|---|
| 2090 | |
|---|
| 2091 | // addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec |
|---|
| 2092 | // base address: 0x0 |
|---|
| 2093 | #define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 |
|---|
| 2094 | #define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 |
|---|
| 2095 | #define regMCIF_WB_BUFMGR_STATUS 0x0274 |
|---|
| 2096 | #define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 |
|---|
| 2097 | #define regMCIF_WB_BUF_PITCH 0x0275 |
|---|
| 2098 | #define regMCIF_WB_BUF_PITCH_BASE_IDX 2 |
|---|
| 2099 | #define regMCIF_WB_BUF_1_STATUS 0x0276 |
|---|
| 2100 | #define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 |
|---|
| 2101 | #define regMCIF_WB_BUF_1_STATUS2 0x0277 |
|---|
| 2102 | #define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 |
|---|
| 2103 | #define regMCIF_WB_BUF_2_STATUS 0x0278 |
|---|
| 2104 | #define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 |
|---|
| 2105 | #define regMCIF_WB_BUF_2_STATUS2 0x0279 |
|---|
| 2106 | #define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 |
|---|
| 2107 | #define regMCIF_WB_BUF_3_STATUS 0x027a |
|---|
| 2108 | #define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 |
|---|
| 2109 | #define regMCIF_WB_BUF_3_STATUS2 0x027b |
|---|
| 2110 | #define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 |
|---|
| 2111 | #define regMCIF_WB_BUF_4_STATUS 0x027c |
|---|
| 2112 | #define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 |
|---|
| 2113 | #define regMCIF_WB_BUF_4_STATUS2 0x027d |
|---|
| 2114 | #define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 |
|---|
| 2115 | #define regMCIF_WB_ARBITRATION_CONTROL 0x027e |
|---|
| 2116 | #define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 |
|---|
| 2117 | #define regMCIF_WB_SCLK_CHANGE 0x027f |
|---|
| 2118 | #define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 |
|---|
| 2119 | #define regMCIF_WB_BUF_1_ADDR_Y 0x0282 |
|---|
| 2120 | #define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 |
|---|
| 2121 | #define regMCIF_WB_BUF_1_ADDR_C 0x0284 |
|---|
| 2122 | #define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 |
|---|
| 2123 | #define regMCIF_WB_BUF_2_ADDR_Y 0x0286 |
|---|
| 2124 | #define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 |
|---|
| 2125 | #define regMCIF_WB_BUF_2_ADDR_C 0x0288 |
|---|
| 2126 | #define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 |
|---|
| 2127 | #define regMCIF_WB_BUF_3_ADDR_Y 0x028a |
|---|
| 2128 | #define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 |
|---|
| 2129 | #define regMCIF_WB_BUF_3_ADDR_C 0x028c |
|---|
| 2130 | #define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 |
|---|
| 2131 | #define regMCIF_WB_BUF_4_ADDR_Y 0x028e |
|---|
| 2132 | #define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 |
|---|
| 2133 | #define regMCIF_WB_BUF_4_ADDR_C 0x0290 |
|---|
| 2134 | #define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 |
|---|
| 2135 | #define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 |
|---|
| 2136 | #define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 |
|---|
| 2137 | #define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 |
|---|
| 2138 | #define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 |
|---|
| 2139 | #define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 |
|---|
| 2140 | #define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 |
|---|
| 2141 | #define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 |
|---|
| 2142 | #define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 |
|---|
| 2143 | #define regMULTI_LEVEL_QOS_CTRL 0x0297 |
|---|
| 2144 | #define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 |
|---|
| 2145 | #define regMCIF_WB_SECURITY_LEVEL 0x0298 |
|---|
| 2146 | #define regMCIF_WB_SECURITY_LEVEL_BASE_IDX 2 |
|---|
| 2147 | #define regMCIF_WB_BUF_LUMA_SIZE 0x0299 |
|---|
| 2148 | #define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 |
|---|
| 2149 | #define regMCIF_WB_BUF_CHROMA_SIZE 0x029a |
|---|
| 2150 | #define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 |
|---|
| 2151 | #define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b |
|---|
| 2152 | #define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 |
|---|
| 2153 | #define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c |
|---|
| 2154 | #define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 |
|---|
| 2155 | #define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d |
|---|
| 2156 | #define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 |
|---|
| 2157 | #define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e |
|---|
| 2158 | #define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 |
|---|
| 2159 | #define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f |
|---|
| 2160 | #define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 |
|---|
| 2161 | #define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 |
|---|
| 2162 | #define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 |
|---|
| 2163 | #define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 |
|---|
| 2164 | #define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 |
|---|
| 2165 | #define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 |
|---|
| 2166 | #define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 |
|---|
| 2167 | #define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 |
|---|
| 2168 | #define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 |
|---|
| 2169 | #define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 |
|---|
| 2170 | #define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 |
|---|
| 2171 | #define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 |
|---|
| 2172 | #define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 |
|---|
| 2173 | #define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 |
|---|
| 2174 | #define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 |
|---|
| 2175 | #define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI 0x02a7 |
|---|
| 2176 | #define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX 2 |
|---|
| 2177 | #define regMCIF_WB_VMID_CONTROL 0x02a8 |
|---|
| 2178 | #define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 |
|---|
| 2179 | #define regMCIF_WB_MIN_TTO 0x02a9 |
|---|
| 2180 | #define regMCIF_WB_MIN_TTO_BASE_IDX 2 |
|---|
| 2181 | |
|---|
| 2182 | |
|---|
| 2183 | // addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec |
|---|
| 2184 | // base address: 0x0 |
|---|
| 2185 | #define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa |
|---|
| 2186 | #define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 |
|---|
| 2187 | #define regMCIF_WB_WATERMARK 0x02ab |
|---|
| 2188 | #define regMCIF_WB_WATERMARK_BASE_IDX 2 |
|---|
| 2189 | #define regMMHUBBUB_WARMUP_CONFIG 0x02ac |
|---|
| 2190 | #define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 |
|---|
| 2191 | #define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad |
|---|
| 2192 | #define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 |
|---|
| 2193 | #define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae |
|---|
| 2194 | #define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 |
|---|
| 2195 | #define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af |
|---|
| 2196 | #define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 |
|---|
| 2197 | #define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 |
|---|
| 2198 | #define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 |
|---|
| 2199 | #define regMMHUBBUB_MIN_TTO 0x02b1 |
|---|
| 2200 | #define regMMHUBBUB_MIN_TTO_BASE_IDX 2 |
|---|
| 2201 | #define regMMHUBBUB_CTRL 0x0333 |
|---|
| 2202 | #define regMMHUBBUB_CTRL_BASE_IDX 2 |
|---|
| 2203 | #define regWBIF_SMU_WM_CONTROL 0x0334 |
|---|
| 2204 | #define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 |
|---|
| 2205 | #define regWBIF0_MISC_CTRL 0x0335 |
|---|
| 2206 | #define regWBIF0_MISC_CTRL_BASE_IDX 2 |
|---|
| 2207 | #define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 |
|---|
| 2208 | #define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 |
|---|
| 2209 | #define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 |
|---|
| 2210 | #define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 |
|---|
| 2211 | #define regMMHUBBUB_MEM_PWR_STATUS 0x033e |
|---|
| 2212 | #define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 2213 | #define regMMHUBBUB_MEM_PWR_CNTL 0x033f |
|---|
| 2214 | #define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 |
|---|
| 2215 | #define regMMHUBBUB_CLOCK_CNTL 0x0340 |
|---|
| 2216 | #define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 |
|---|
| 2217 | #define regMMHUBBUB_SOFT_RESET 0x0341 |
|---|
| 2218 | #define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 |
|---|
| 2219 | #define regDMU_IF_ERR_STATUS 0x0345 |
|---|
| 2220 | #define regDMU_IF_ERR_STATUS_BASE_IDX 2 |
|---|
| 2221 | #define regMMHUBBUB_CLIENT_UNIT_ID 0x0346 |
|---|
| 2222 | #define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 |
|---|
| 2223 | #define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0348 |
|---|
| 2224 | #define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 |
|---|
| 2225 | |
|---|
| 2226 | |
|---|
| 2227 | // addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec |
|---|
| 2228 | // base address: 0xd48 |
|---|
| 2229 | #define regDC_PERFMON4_PERFCOUNTER_CNTL 0x0352 |
|---|
| 2230 | #define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 2231 | #define regDC_PERFMON4_PERFCOUNTER_CNTL2 0x0353 |
|---|
| 2232 | #define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 2233 | #define regDC_PERFMON4_PERFCOUNTER_STATE 0x0354 |
|---|
| 2234 | #define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 2235 | #define regDC_PERFMON4_PERFMON_CNTL 0x0355 |
|---|
| 2236 | #define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 2237 | #define regDC_PERFMON4_PERFMON_CNTL2 0x0356 |
|---|
| 2238 | #define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 2239 | #define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0357 |
|---|
| 2240 | #define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 2241 | #define regDC_PERFMON4_PERFMON_CVALUE_LOW 0x0358 |
|---|
| 2242 | #define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 2243 | #define regDC_PERFMON4_PERFMON_HI 0x0359 |
|---|
| 2244 | #define regDC_PERFMON4_PERFMON_HI_BASE_IDX 2 |
|---|
| 2245 | #define regDC_PERFMON4_PERFMON_LOW 0x035a |
|---|
| 2246 | #define regDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 |
|---|
| 2247 | |
|---|
| 2248 | |
|---|
| 2249 | |
|---|
| 2250 | |
|---|
| 2251 | // addressBlock: dce_dc_hda_azf0stream0_dispdec |
|---|
| 2252 | // base address: 0x0 |
|---|
| 2253 | #define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e |
|---|
| 2254 | #define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2255 | #define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f |
|---|
| 2256 | #define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2257 | |
|---|
| 2258 | |
|---|
| 2259 | // addressBlock: dce_dc_hda_azf0stream1_dispdec |
|---|
| 2260 | // base address: 0x8 |
|---|
| 2261 | #define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 |
|---|
| 2262 | #define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2263 | #define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 |
|---|
| 2264 | #define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2265 | |
|---|
| 2266 | |
|---|
| 2267 | // addressBlock: dce_dc_hda_azf0stream2_dispdec |
|---|
| 2268 | // base address: 0x10 |
|---|
| 2269 | #define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 |
|---|
| 2270 | #define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2271 | #define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 |
|---|
| 2272 | #define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2273 | |
|---|
| 2274 | |
|---|
| 2275 | // addressBlock: dce_dc_hda_azf0stream3_dispdec |
|---|
| 2276 | // base address: 0x18 |
|---|
| 2277 | #define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 |
|---|
| 2278 | #define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2279 | #define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 |
|---|
| 2280 | #define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2281 | |
|---|
| 2282 | |
|---|
| 2283 | // addressBlock: dce_dc_hda_azf0stream4_dispdec |
|---|
| 2284 | // base address: 0x20 |
|---|
| 2285 | #define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 |
|---|
| 2286 | #define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2287 | #define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 |
|---|
| 2288 | #define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2289 | |
|---|
| 2290 | |
|---|
| 2291 | // addressBlock: dce_dc_hda_azf0stream5_dispdec |
|---|
| 2292 | // base address: 0x28 |
|---|
| 2293 | #define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 |
|---|
| 2294 | #define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2295 | #define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 |
|---|
| 2296 | #define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2297 | |
|---|
| 2298 | |
|---|
| 2299 | // addressBlock: dce_dc_hda_azf0stream6_dispdec |
|---|
| 2300 | // base address: 0x30 |
|---|
| 2301 | #define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a |
|---|
| 2302 | #define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2303 | #define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b |
|---|
| 2304 | #define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2305 | |
|---|
| 2306 | |
|---|
| 2307 | // addressBlock: dce_dc_hda_azf0stream7_dispdec |
|---|
| 2308 | // base address: 0x38 |
|---|
| 2309 | #define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c |
|---|
| 2310 | #define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2311 | #define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d |
|---|
| 2312 | #define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2313 | |
|---|
| 2314 | |
|---|
| 2315 | // addressBlock: dce_dc_hda_az_misc_dispdec |
|---|
| 2316 | // base address: 0x0 |
|---|
| 2317 | #define regAZ_CLOCK_CNTL 0x0372 |
|---|
| 2318 | #define regAZ_CLOCK_CNTL_BASE_IDX 2 |
|---|
| 2319 | #define regAZ_MEM_GLOBAL_PWR_REQ_CNTL 0x0373 |
|---|
| 2320 | #define regAZ_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 2 |
|---|
| 2321 | |
|---|
| 2322 | // addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec |
|---|
| 2323 | // base address: 0xde8 |
|---|
| 2324 | #define regDC_PERFMON5_PERFCOUNTER_CNTL 0x037a |
|---|
| 2325 | #define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 2326 | #define regDC_PERFMON5_PERFCOUNTER_CNTL2 0x037b |
|---|
| 2327 | #define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 2328 | #define regDC_PERFMON5_PERFCOUNTER_STATE 0x037c |
|---|
| 2329 | #define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 2330 | #define regDC_PERFMON5_PERFMON_CNTL 0x037d |
|---|
| 2331 | #define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 2332 | #define regDC_PERFMON5_PERFMON_CNTL2 0x037e |
|---|
| 2333 | #define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 2334 | #define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x037f |
|---|
| 2335 | #define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 2336 | #define regDC_PERFMON5_PERFMON_CVALUE_LOW 0x0380 |
|---|
| 2337 | #define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 2338 | #define regDC_PERFMON5_PERFMON_HI 0x0381 |
|---|
| 2339 | #define regDC_PERFMON5_PERFMON_HI_BASE_IDX 2 |
|---|
| 2340 | #define regDC_PERFMON5_PERFMON_LOW 0x0382 |
|---|
| 2341 | #define regDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 |
|---|
| 2342 | |
|---|
| 2343 | |
|---|
| 2344 | |
|---|
| 2345 | // addressBlock: dce_dc_hda_azf0endpoint0_dispdec |
|---|
| 2346 | // base address: 0x0 |
|---|
| 2347 | #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 |
|---|
| 2348 | #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2349 | #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 |
|---|
| 2350 | #define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2351 | |
|---|
| 2352 | |
|---|
| 2353 | // addressBlock: dce_dc_hda_azf0endpoint1_dispdec |
|---|
| 2354 | // base address: 0x18 |
|---|
| 2355 | #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c |
|---|
| 2356 | #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2357 | #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d |
|---|
| 2358 | #define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2359 | |
|---|
| 2360 | |
|---|
| 2361 | // addressBlock: dce_dc_hda_azf0endpoint2_dispdec |
|---|
| 2362 | // base address: 0x30 |
|---|
| 2363 | #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 |
|---|
| 2364 | #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2365 | #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 |
|---|
| 2366 | #define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2367 | |
|---|
| 2368 | |
|---|
| 2369 | // addressBlock: dce_dc_hda_azf0endpoint3_dispdec |
|---|
| 2370 | // base address: 0x48 |
|---|
| 2371 | #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 |
|---|
| 2372 | #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2373 | #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 |
|---|
| 2374 | #define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2375 | |
|---|
| 2376 | |
|---|
| 2377 | // addressBlock: dce_dc_hda_azf0endpoint4_dispdec |
|---|
| 2378 | // base address: 0x60 |
|---|
| 2379 | #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e |
|---|
| 2380 | #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2381 | #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f |
|---|
| 2382 | #define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2383 | |
|---|
| 2384 | |
|---|
| 2385 | // addressBlock: dce_dc_hda_azf0endpoint5_dispdec |
|---|
| 2386 | // base address: 0x78 |
|---|
| 2387 | #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 |
|---|
| 2388 | #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2389 | #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 |
|---|
| 2390 | #define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2391 | |
|---|
| 2392 | |
|---|
| 2393 | // addressBlock: dce_dc_hda_azf0endpoint6_dispdec |
|---|
| 2394 | // base address: 0x90 |
|---|
| 2395 | #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa |
|---|
| 2396 | #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2397 | #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab |
|---|
| 2398 | #define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2399 | |
|---|
| 2400 | |
|---|
| 2401 | // addressBlock: dce_dc_hda_azf0endpoint7_dispdec |
|---|
| 2402 | // base address: 0xa8 |
|---|
| 2403 | #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 |
|---|
| 2404 | #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2405 | #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 |
|---|
| 2406 | #define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2407 | |
|---|
| 2408 | |
|---|
| 2409 | // addressBlock: dce_dc_hda_azf0controller_dispdec |
|---|
| 2410 | // base address: 0x0 |
|---|
| 2411 | #define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 |
|---|
| 2412 | #define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 |
|---|
| 2413 | #define regAZALIA_AUDIO_DTO 0x03c3 |
|---|
| 2414 | #define regAZALIA_AUDIO_DTO_BASE_IDX 2 |
|---|
| 2415 | #define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 |
|---|
| 2416 | #define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 |
|---|
| 2417 | #define regAZALIA_SOCCLK_CONTROL 0x03c5 |
|---|
| 2418 | #define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 |
|---|
| 2419 | #define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 |
|---|
| 2420 | #define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 |
|---|
| 2421 | #define regAZALIA_DATA_DMA_CONTROL 0x03c7 |
|---|
| 2422 | #define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 |
|---|
| 2423 | #define regAZALIA_BDL_DMA_CONTROL 0x03c8 |
|---|
| 2424 | #define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 |
|---|
| 2425 | #define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 |
|---|
| 2426 | #define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 |
|---|
| 2427 | #define regAZALIA_CORB_DMA_CONTROL 0x03ca |
|---|
| 2428 | #define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 |
|---|
| 2429 | #define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 |
|---|
| 2430 | #define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 |
|---|
| 2431 | #define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 |
|---|
| 2432 | #define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 |
|---|
| 2433 | #define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 |
|---|
| 2434 | #define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 |
|---|
| 2435 | #define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 |
|---|
| 2436 | #define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 |
|---|
| 2437 | #define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 |
|---|
| 2438 | #define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 |
|---|
| 2439 | #define regAZALIA_INPUT_CRC0_CONTROL1 0x03da |
|---|
| 2440 | #define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 |
|---|
| 2441 | #define regAZALIA_INPUT_CRC0_CONTROL2 0x03db |
|---|
| 2442 | #define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 |
|---|
| 2443 | #define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc |
|---|
| 2444 | #define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 |
|---|
| 2445 | #define regAZALIA_INPUT_CRC0_RESULT 0x03dd |
|---|
| 2446 | #define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 |
|---|
| 2447 | #define regAZALIA_INPUT_CRC1_CONTROL0 0x03de |
|---|
| 2448 | #define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 |
|---|
| 2449 | #define regAZALIA_INPUT_CRC1_CONTROL1 0x03df |
|---|
| 2450 | #define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 |
|---|
| 2451 | #define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 |
|---|
| 2452 | #define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 |
|---|
| 2453 | #define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 |
|---|
| 2454 | #define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 |
|---|
| 2455 | #define regAZALIA_INPUT_CRC1_RESULT 0x03e2 |
|---|
| 2456 | #define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 |
|---|
| 2457 | #define regAZALIA_CRC0_CONTROL0 0x03e3 |
|---|
| 2458 | #define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 |
|---|
| 2459 | #define regAZALIA_CRC0_CONTROL1 0x03e4 |
|---|
| 2460 | #define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 |
|---|
| 2461 | #define regAZALIA_CRC0_CONTROL2 0x03e5 |
|---|
| 2462 | #define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 |
|---|
| 2463 | #define regAZALIA_CRC0_CONTROL3 0x03e6 |
|---|
| 2464 | #define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 |
|---|
| 2465 | #define regAZALIA_CRC0_RESULT 0x03e7 |
|---|
| 2466 | #define regAZALIA_CRC0_RESULT_BASE_IDX 2 |
|---|
| 2467 | #define regAZALIA_CRC1_CONTROL0 0x03e8 |
|---|
| 2468 | #define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 |
|---|
| 2469 | #define regAZALIA_CRC1_CONTROL1 0x03e9 |
|---|
| 2470 | #define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 |
|---|
| 2471 | #define regAZALIA_CRC1_CONTROL2 0x03ea |
|---|
| 2472 | #define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 |
|---|
| 2473 | #define regAZALIA_CRC1_CONTROL3 0x03eb |
|---|
| 2474 | #define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 |
|---|
| 2475 | #define regAZALIA_CRC1_RESULT 0x03ec |
|---|
| 2476 | #define regAZALIA_CRC1_RESULT_BASE_IDX 2 |
|---|
| 2477 | #define regAZALIA_MEM_PWR_CTRL 0x03ee |
|---|
| 2478 | #define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 2479 | #define regAZALIA_MEM_PWR_STATUS 0x03ef |
|---|
| 2480 | #define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 2481 | |
|---|
| 2482 | |
|---|
| 2483 | |
|---|
| 2484 | // addressBlock: dce_dc_hda_azf0root_dispdec |
|---|
| 2485 | // base address: 0x0 |
|---|
| 2486 | #define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 |
|---|
| 2487 | #define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 |
|---|
| 2488 | #define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 |
|---|
| 2489 | #define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 |
|---|
| 2490 | #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 |
|---|
| 2491 | #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 2492 | #define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 |
|---|
| 2493 | #define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 |
|---|
| 2494 | #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a |
|---|
| 2495 | #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 |
|---|
| 2496 | #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b |
|---|
| 2497 | #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 |
|---|
| 2498 | #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c |
|---|
| 2499 | #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 |
|---|
| 2500 | #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d |
|---|
| 2501 | #define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 |
|---|
| 2502 | #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e |
|---|
| 2503 | #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 |
|---|
| 2504 | #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f |
|---|
| 2505 | #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 |
|---|
| 2506 | #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 |
|---|
| 2507 | #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 |
|---|
| 2508 | #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 |
|---|
| 2509 | #define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 |
|---|
| 2510 | #define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 |
|---|
| 2511 | #define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 |
|---|
| 2512 | #define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 |
|---|
| 2513 | #define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 |
|---|
| 2514 | #define regAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 |
|---|
| 2515 | #define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 |
|---|
| 2516 | #define regAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 |
|---|
| 2517 | #define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 |
|---|
| 2518 | #define regAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 |
|---|
| 2519 | #define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 |
|---|
| 2520 | #define regAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 |
|---|
| 2521 | #define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 |
|---|
| 2522 | #define regAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 |
|---|
| 2523 | #define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 |
|---|
| 2524 | #define regAZALIA_F0_GTC_GROUP_OFFSET5 0x041a |
|---|
| 2525 | #define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 |
|---|
| 2526 | #define regAZALIA_F0_GTC_GROUP_OFFSET6 0x041b |
|---|
| 2527 | #define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 |
|---|
| 2528 | #define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c |
|---|
| 2529 | #define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 |
|---|
| 2530 | #define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d |
|---|
| 2531 | #define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 |
|---|
| 2532 | |
|---|
| 2533 | |
|---|
| 2534 | |
|---|
| 2535 | // addressBlock: dce_dc_hda_azf0stream8_dispdec |
|---|
| 2536 | // base address: 0x320 |
|---|
| 2537 | #define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 |
|---|
| 2538 | #define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2539 | #define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 |
|---|
| 2540 | #define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2541 | |
|---|
| 2542 | |
|---|
| 2543 | // addressBlock: dce_dc_hda_azf0stream9_dispdec |
|---|
| 2544 | // base address: 0x328 |
|---|
| 2545 | #define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 |
|---|
| 2546 | #define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2547 | #define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 |
|---|
| 2548 | #define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2549 | |
|---|
| 2550 | |
|---|
| 2551 | // addressBlock: dce_dc_hda_azf0stream10_dispdec |
|---|
| 2552 | // base address: 0x330 |
|---|
| 2553 | #define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a |
|---|
| 2554 | #define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2555 | #define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b |
|---|
| 2556 | #define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2557 | |
|---|
| 2558 | |
|---|
| 2559 | // addressBlock: dce_dc_hda_azf0stream11_dispdec |
|---|
| 2560 | // base address: 0x338 |
|---|
| 2561 | #define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c |
|---|
| 2562 | #define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2563 | #define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d |
|---|
| 2564 | #define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2565 | |
|---|
| 2566 | |
|---|
| 2567 | // addressBlock: dce_dc_hda_azf0stream12_dispdec |
|---|
| 2568 | // base address: 0x340 |
|---|
| 2569 | #define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e |
|---|
| 2570 | #define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2571 | #define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f |
|---|
| 2572 | #define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2573 | |
|---|
| 2574 | |
|---|
| 2575 | // addressBlock: dce_dc_hda_azf0stream13_dispdec |
|---|
| 2576 | // base address: 0x348 |
|---|
| 2577 | #define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 |
|---|
| 2578 | #define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2579 | #define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 |
|---|
| 2580 | #define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2581 | |
|---|
| 2582 | |
|---|
| 2583 | // addressBlock: dce_dc_hda_azf0stream14_dispdec |
|---|
| 2584 | // base address: 0x350 |
|---|
| 2585 | #define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 |
|---|
| 2586 | #define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2587 | #define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 |
|---|
| 2588 | #define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2589 | |
|---|
| 2590 | |
|---|
| 2591 | // addressBlock: dce_dc_hda_azf0stream15_dispdec |
|---|
| 2592 | // base address: 0x358 |
|---|
| 2593 | #define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 |
|---|
| 2594 | #define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 |
|---|
| 2595 | #define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 |
|---|
| 2596 | #define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 |
|---|
| 2597 | |
|---|
| 2598 | |
|---|
| 2599 | |
|---|
| 2600 | // addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec |
|---|
| 2601 | // base address: 0x0 |
|---|
| 2602 | #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a |
|---|
| 2603 | #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2604 | #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b |
|---|
| 2605 | #define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2606 | |
|---|
| 2607 | |
|---|
| 2608 | // addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec |
|---|
| 2609 | // base address: 0x10 |
|---|
| 2610 | #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e |
|---|
| 2611 | #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2612 | #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f |
|---|
| 2613 | #define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2614 | |
|---|
| 2615 | |
|---|
| 2616 | // addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec |
|---|
| 2617 | // base address: 0x20 |
|---|
| 2618 | #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 |
|---|
| 2619 | #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2620 | #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 |
|---|
| 2621 | #define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2622 | |
|---|
| 2623 | |
|---|
| 2624 | // addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec |
|---|
| 2625 | // base address: 0x30 |
|---|
| 2626 | #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 |
|---|
| 2627 | #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2628 | #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 |
|---|
| 2629 | #define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2630 | |
|---|
| 2631 | |
|---|
| 2632 | // addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec |
|---|
| 2633 | // base address: 0x40 |
|---|
| 2634 | #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a |
|---|
| 2635 | #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2636 | #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b |
|---|
| 2637 | #define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2638 | |
|---|
| 2639 | |
|---|
| 2640 | // addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec |
|---|
| 2641 | // base address: 0x50 |
|---|
| 2642 | #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e |
|---|
| 2643 | #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2644 | #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f |
|---|
| 2645 | #define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2646 | |
|---|
| 2647 | |
|---|
| 2648 | // addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec |
|---|
| 2649 | // base address: 0x60 |
|---|
| 2650 | #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 |
|---|
| 2651 | #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2652 | #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 |
|---|
| 2653 | #define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2654 | |
|---|
| 2655 | |
|---|
| 2656 | // addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec |
|---|
| 2657 | // base address: 0x70 |
|---|
| 2658 | #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 |
|---|
| 2659 | #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 |
|---|
| 2660 | #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 |
|---|
| 2661 | #define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 |
|---|
| 2662 | |
|---|
| 2663 | |
|---|
| 2664 | |
|---|
| 2665 | // addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec |
|---|
| 2666 | // base address: 0x0 |
|---|
| 2667 | #define regDCHUBBUB_SDPIF_CFG0 0x046f |
|---|
| 2668 | #define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 |
|---|
| 2669 | #define regDCHUBBUB_SDPIF_CFG1 0x0470 |
|---|
| 2670 | #define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 |
|---|
| 2671 | #define regDCHUBBUB_SDPIF_CFG2 0x0471 |
|---|
| 2672 | #define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 |
|---|
| 2673 | #define regVM_REQUEST_PHYSICAL 0x0472 |
|---|
| 2674 | #define regVM_REQUEST_PHYSICAL_BASE_IDX 2 |
|---|
| 2675 | #define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 |
|---|
| 2676 | #define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 |
|---|
| 2677 | #define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 |
|---|
| 2678 | #define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 |
|---|
| 2679 | #define regDCN_VM_FB_LOCATION_BASE 0x0475 |
|---|
| 2680 | #define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 |
|---|
| 2681 | #define regDCN_VM_FB_LOCATION_TOP 0x0476 |
|---|
| 2682 | #define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 |
|---|
| 2683 | #define regDCN_VM_FB_OFFSET 0x0477 |
|---|
| 2684 | #define regDCN_VM_FB_OFFSET_BASE_IDX 2 |
|---|
| 2685 | #define regDCN_VM_AGP_BOT 0x0478 |
|---|
| 2686 | #define regDCN_VM_AGP_BOT_BASE_IDX 2 |
|---|
| 2687 | #define regDCN_VM_AGP_TOP 0x0479 |
|---|
| 2688 | #define regDCN_VM_AGP_TOP_BASE_IDX 2 |
|---|
| 2689 | #define regDCN_VM_AGP_BASE 0x047a |
|---|
| 2690 | #define regDCN_VM_AGP_BASE_BASE_IDX 2 |
|---|
| 2691 | #define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b |
|---|
| 2692 | #define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 |
|---|
| 2693 | #define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c |
|---|
| 2694 | #define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 |
|---|
| 2695 | #define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d |
|---|
| 2696 | #define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 |
|---|
| 2697 | #define regDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x047e |
|---|
| 2698 | #define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 |
|---|
| 2699 | #define regDCHUBBUB_SDPIF_PIPE_NOALLOC 0x047f |
|---|
| 2700 | #define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX 2 |
|---|
| 2701 | #define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x0480 |
|---|
| 2702 | #define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2 |
|---|
| 2703 | #define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL 0x0481 |
|---|
| 2704 | #define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX 2 |
|---|
| 2705 | #define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL 0x0482 |
|---|
| 2706 | #define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX 2 |
|---|
| 2707 | #define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL 0x0483 |
|---|
| 2708 | #define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX 2 |
|---|
| 2709 | #define regSDPIF_REQUEST_RATE_LIMIT 0x0484 |
|---|
| 2710 | #define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX 2 |
|---|
| 2711 | #define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0485 |
|---|
| 2712 | #define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 2713 | #define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0486 |
|---|
| 2714 | #define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 2715 | |
|---|
| 2716 | |
|---|
| 2717 | // addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec |
|---|
| 2718 | // base address: 0x0 |
|---|
| 2719 | #define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04af |
|---|
| 2720 | #define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 2721 | #define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04b0 |
|---|
| 2722 | #define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 2723 | #define regDCHUBBUB_CRC_CTRL 0x04b1 |
|---|
| 2724 | #define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 |
|---|
| 2725 | #define regDCHUBBUB_CRC0_VAL_R_G 0x04b2 |
|---|
| 2726 | #define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 |
|---|
| 2727 | #define regDCHUBBUB_CRC0_VAL_B_A 0x04b3 |
|---|
| 2728 | #define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 |
|---|
| 2729 | #define regDCHUBBUB_CRC1_VAL_R_G 0x04b4 |
|---|
| 2730 | #define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 |
|---|
| 2731 | #define regDCHUBBUB_CRC1_VAL_B_A 0x04b5 |
|---|
| 2732 | #define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 |
|---|
| 2733 | #define regDCHUBBUB_DCC_STAT_CNTL 0x04b6 |
|---|
| 2734 | #define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 |
|---|
| 2735 | #define regDCHUBBUB_DCC_STAT0 0x04b7 |
|---|
| 2736 | #define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 |
|---|
| 2737 | #define regDCHUBBUB_DCC_STAT1 0x04b8 |
|---|
| 2738 | #define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 |
|---|
| 2739 | #define regDCHUBBUB_DCC_STAT2 0x04b9 |
|---|
| 2740 | #define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 |
|---|
| 2741 | #define regDCHUBBUB_COMPBUF_CTRL 0x04ba |
|---|
| 2742 | #define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 |
|---|
| 2743 | #define regDCHUBBUB_DET0_CTRL 0x04bb |
|---|
| 2744 | #define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 |
|---|
| 2745 | #define regDCHUBBUB_DET1_CTRL 0x04bc |
|---|
| 2746 | #define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 |
|---|
| 2747 | #define regDCHUBBUB_DET2_CTRL 0x04bd |
|---|
| 2748 | #define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 |
|---|
| 2749 | #define regDCHUBBUB_DET3_CTRL 0x04be |
|---|
| 2750 | #define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 |
|---|
| 2751 | #define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04c0 |
|---|
| 2752 | #define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 |
|---|
| 2753 | #define regCOMPBUF_MEM_PWR_CTRL_1 0x04c1 |
|---|
| 2754 | #define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 |
|---|
| 2755 | #define regCOMPBUF_MEM_PWR_CTRL_2 0x04c2 |
|---|
| 2756 | #define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 |
|---|
| 2757 | #define regDCHUBBUB_MEM_PWR_STATUS 0x04c3 |
|---|
| 2758 | #define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 2759 | #define regCOMPBUF_RESERVED_SPACE 0x04c4 |
|---|
| 2760 | #define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 |
|---|
| 2761 | #define regDCHUBBUB_DEBUG_CTRL_0 0x04c5 |
|---|
| 2762 | #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 |
|---|
| 2763 | |
|---|
| 2764 | |
|---|
| 2765 | // addressBlock: dce_dc_dchubbubl_hubbub_dispdec |
|---|
| 2766 | // base address: 0x0 |
|---|
| 2767 | #define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04f9 |
|---|
| 2768 | #define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 |
|---|
| 2769 | #define regDCHUBBUB_ARB_SAT_LEVEL 0x04fa |
|---|
| 2770 | #define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 |
|---|
| 2771 | #define regDCHUBBUB_ARB_QOS_FORCE 0x04fb |
|---|
| 2772 | #define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 |
|---|
| 2773 | #define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04fc |
|---|
| 2774 | #define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 |
|---|
| 2775 | #define regDCHUBBUB_ARB_USR_RETRAINING_CNTL 0x04fd |
|---|
| 2776 | #define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX 2 |
|---|
| 2777 | #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04fe |
|---|
| 2778 | #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 |
|---|
| 2779 | #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A 0x04ff |
|---|
| 2780 | #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX 2 |
|---|
| 2781 | #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x0500 |
|---|
| 2782 | #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 |
|---|
| 2783 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x0501 |
|---|
| 2784 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 |
|---|
| 2785 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A 0x0502 |
|---|
| 2786 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX 2 |
|---|
| 2787 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x0503 |
|---|
| 2788 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 |
|---|
| 2789 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A 0x0504 |
|---|
| 2790 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX 2 |
|---|
| 2791 | #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A 0x0505 |
|---|
| 2792 | #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 |
|---|
| 2793 | #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A 0x0506 |
|---|
| 2794 | #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 |
|---|
| 2795 | #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x0507 |
|---|
| 2796 | #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 |
|---|
| 2797 | #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0508 |
|---|
| 2798 | #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 |
|---|
| 2799 | #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0509 |
|---|
| 2800 | #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 |
|---|
| 2801 | #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B 0x050a |
|---|
| 2802 | #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX 2 |
|---|
| 2803 | #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x050b |
|---|
| 2804 | #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 |
|---|
| 2805 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x050c |
|---|
| 2806 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 |
|---|
| 2807 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B 0x050d |
|---|
| 2808 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX 2 |
|---|
| 2809 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x050e |
|---|
| 2810 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 |
|---|
| 2811 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B 0x050f |
|---|
| 2812 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX 2 |
|---|
| 2813 | #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B 0x0510 |
|---|
| 2814 | #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 |
|---|
| 2815 | #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B 0x0511 |
|---|
| 2816 | #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 |
|---|
| 2817 | #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0512 |
|---|
| 2818 | #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 |
|---|
| 2819 | #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x0513 |
|---|
| 2820 | #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 |
|---|
| 2821 | #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0514 |
|---|
| 2822 | #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 |
|---|
| 2823 | #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C 0x0515 |
|---|
| 2824 | #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX 2 |
|---|
| 2825 | #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0516 |
|---|
| 2826 | #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 |
|---|
| 2827 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0517 |
|---|
| 2828 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 |
|---|
| 2829 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C 0x0518 |
|---|
| 2830 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX 2 |
|---|
| 2831 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0519 |
|---|
| 2832 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 |
|---|
| 2833 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C 0x051a |
|---|
| 2834 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX 2 |
|---|
| 2835 | #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C 0x051b |
|---|
| 2836 | #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 |
|---|
| 2837 | #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C 0x051c |
|---|
| 2838 | #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 |
|---|
| 2839 | #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x051d |
|---|
| 2840 | #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 |
|---|
| 2841 | #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x051e |
|---|
| 2842 | #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 |
|---|
| 2843 | #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x051f |
|---|
| 2844 | #define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 |
|---|
| 2845 | #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D 0x0520 |
|---|
| 2846 | #define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX 2 |
|---|
| 2847 | #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0521 |
|---|
| 2848 | #define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 |
|---|
| 2849 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x0522 |
|---|
| 2850 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 |
|---|
| 2851 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D 0x0523 |
|---|
| 2852 | #define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX 2 |
|---|
| 2853 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x0524 |
|---|
| 2854 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 |
|---|
| 2855 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 0x0525 |
|---|
| 2856 | #define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX 2 |
|---|
| 2857 | #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D 0x0526 |
|---|
| 2858 | #define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 |
|---|
| 2859 | #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D 0x0527 |
|---|
| 2860 | #define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 |
|---|
| 2861 | #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0528 |
|---|
| 2862 | #define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 |
|---|
| 2863 | #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0529 |
|---|
| 2864 | #define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 |
|---|
| 2865 | #define regDCHUBBUB_ARB_HOSTVM_CNTL 0x052a |
|---|
| 2866 | #define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2 |
|---|
| 2867 | #define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x052b |
|---|
| 2868 | #define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 |
|---|
| 2869 | #define regDCHUBBUB_ARB_MALL_CNTL 0x052c |
|---|
| 2870 | #define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX 2 |
|---|
| 2871 | #define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x052d |
|---|
| 2872 | #define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 |
|---|
| 2873 | #define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x052e |
|---|
| 2874 | #define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 |
|---|
| 2875 | #define regSURFACE_CHECK0_ADDRESS_LSB 0x052f |
|---|
| 2876 | #define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 |
|---|
| 2877 | #define regSURFACE_CHECK0_ADDRESS_MSB 0x0530 |
|---|
| 2878 | #define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 |
|---|
| 2879 | #define regSURFACE_CHECK1_ADDRESS_LSB 0x0531 |
|---|
| 2880 | #define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 |
|---|
| 2881 | #define regSURFACE_CHECK1_ADDRESS_MSB 0x0532 |
|---|
| 2882 | #define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 |
|---|
| 2883 | #define regSURFACE_CHECK2_ADDRESS_LSB 0x0533 |
|---|
| 2884 | #define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 |
|---|
| 2885 | #define regSURFACE_CHECK2_ADDRESS_MSB 0x0534 |
|---|
| 2886 | #define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 |
|---|
| 2887 | #define regSURFACE_CHECK3_ADDRESS_LSB 0x0535 |
|---|
| 2888 | #define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 |
|---|
| 2889 | #define regSURFACE_CHECK3_ADDRESS_MSB 0x0536 |
|---|
| 2890 | #define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 |
|---|
| 2891 | #define regVTG0_CONTROL 0x0537 |
|---|
| 2892 | #define regVTG0_CONTROL_BASE_IDX 2 |
|---|
| 2893 | #define regVTG1_CONTROL 0x0538 |
|---|
| 2894 | #define regVTG1_CONTROL_BASE_IDX 2 |
|---|
| 2895 | #define regVTG2_CONTROL 0x0539 |
|---|
| 2896 | #define regVTG2_CONTROL_BASE_IDX 2 |
|---|
| 2897 | #define regVTG3_CONTROL 0x053a |
|---|
| 2898 | #define regVTG3_CONTROL_BASE_IDX 2 |
|---|
| 2899 | #define regDCHUBBUB_SOFT_RESET 0x053b |
|---|
| 2900 | #define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 |
|---|
| 2901 | #define regDCHUBBUB_CLOCK_CNTL 0x053c |
|---|
| 2902 | #define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 |
|---|
| 2903 | #define regDCFCLK_CNTL 0x053d |
|---|
| 2904 | #define regDCFCLK_CNTL_BASE_IDX 2 |
|---|
| 2905 | #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x053e |
|---|
| 2906 | #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 |
|---|
| 2907 | #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x053f |
|---|
| 2908 | #define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 |
|---|
| 2909 | #define regDCHUBBUB_VLINE_SNAPSHOT 0x0540 |
|---|
| 2910 | #define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 |
|---|
| 2911 | #define regDCHUBBUB_CTRL_STATUS 0x0541 |
|---|
| 2912 | #define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 |
|---|
| 2913 | #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x0547 |
|---|
| 2914 | #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 |
|---|
| 2915 | #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x0548 |
|---|
| 2916 | #define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 |
|---|
| 2917 | #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x0549 |
|---|
| 2918 | #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 |
|---|
| 2919 | #define regFMON_CTRL 0x054a |
|---|
| 2920 | #define regFMON_CTRL_BASE_IDX 2 |
|---|
| 2921 | #define regDCHUBBUB_TEST_DEBUG_INDEX 0x054b |
|---|
| 2922 | #define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 |
|---|
| 2923 | #define regDCHUBBUB_TEST_DEBUG_DATA 0x054c |
|---|
| 2924 | #define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 |
|---|
| 2925 | |
|---|
| 2926 | // addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec |
|---|
| 2927 | // base address: 0x1534 |
|---|
| 2928 | #define regDC_PERFMON6_PERFCOUNTER_CNTL 0x054d |
|---|
| 2929 | #define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 2930 | #define regDC_PERFMON6_PERFCOUNTER_CNTL2 0x054e |
|---|
| 2931 | #define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 2932 | #define regDC_PERFMON6_PERFCOUNTER_STATE 0x054f |
|---|
| 2933 | #define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 2934 | #define regDC_PERFMON6_PERFMON_CNTL 0x0550 |
|---|
| 2935 | #define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 2936 | #define regDC_PERFMON6_PERFMON_CNTL2 0x0551 |
|---|
| 2937 | #define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 2938 | #define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0552 |
|---|
| 2939 | #define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 2940 | #define regDC_PERFMON6_PERFMON_CVALUE_LOW 0x0553 |
|---|
| 2941 | #define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 2942 | #define regDC_PERFMON6_PERFMON_HI 0x0554 |
|---|
| 2943 | #define regDC_PERFMON6_PERFMON_HI_BASE_IDX 2 |
|---|
| 2944 | #define regDC_PERFMON6_PERFMON_LOW 0x0555 |
|---|
| 2945 | #define regDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 |
|---|
| 2946 | |
|---|
| 2947 | |
|---|
| 2948 | // addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec |
|---|
| 2949 | // base address: 0x0 |
|---|
| 2950 | #define regDCN_VM_CONTEXT0_CNTL 0x0559 |
|---|
| 2951 | #define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 |
|---|
| 2952 | #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a |
|---|
| 2953 | #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 2954 | #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b |
|---|
| 2955 | #define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 2956 | #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c |
|---|
| 2957 | #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 2958 | #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d |
|---|
| 2959 | #define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 2960 | #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e |
|---|
| 2961 | #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 2962 | #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f |
|---|
| 2963 | #define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 2964 | #define regDCN_VM_CONTEXT1_CNTL 0x0560 |
|---|
| 2965 | #define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 |
|---|
| 2966 | #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 |
|---|
| 2967 | #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 2968 | #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 |
|---|
| 2969 | #define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 2970 | #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 |
|---|
| 2971 | #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 2972 | #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 |
|---|
| 2973 | #define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 2974 | #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 |
|---|
| 2975 | #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 2976 | #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 |
|---|
| 2977 | #define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 2978 | #define regDCN_VM_CONTEXT2_CNTL 0x0567 |
|---|
| 2979 | #define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 |
|---|
| 2980 | #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 |
|---|
| 2981 | #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 2982 | #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 |
|---|
| 2983 | #define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 2984 | #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a |
|---|
| 2985 | #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 2986 | #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b |
|---|
| 2987 | #define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 2988 | #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c |
|---|
| 2989 | #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 2990 | #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d |
|---|
| 2991 | #define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 2992 | #define regDCN_VM_CONTEXT3_CNTL 0x056e |
|---|
| 2993 | #define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 |
|---|
| 2994 | #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f |
|---|
| 2995 | #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 2996 | #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 |
|---|
| 2997 | #define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 2998 | #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 |
|---|
| 2999 | #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 3000 | #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 |
|---|
| 3001 | #define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 3002 | #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 |
|---|
| 3003 | #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 3004 | #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 |
|---|
| 3005 | #define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 3006 | #define regDCN_VM_CONTEXT4_CNTL 0x0575 |
|---|
| 3007 | #define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 |
|---|
| 3008 | #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 |
|---|
| 3009 | #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 3010 | #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 |
|---|
| 3011 | #define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 3012 | #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 |
|---|
| 3013 | #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 3014 | #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 |
|---|
| 3015 | #define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 3016 | #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a |
|---|
| 3017 | #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 3018 | #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b |
|---|
| 3019 | #define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 3020 | #define regDCN_VM_CONTEXT5_CNTL 0x057c |
|---|
| 3021 | #define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 |
|---|
| 3022 | #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d |
|---|
| 3023 | #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 3024 | #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e |
|---|
| 3025 | #define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 3026 | #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f |
|---|
| 3027 | #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 3028 | #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 |
|---|
| 3029 | #define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 3030 | #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 |
|---|
| 3031 | #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 3032 | #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 |
|---|
| 3033 | #define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 3034 | #define regDCN_VM_CONTEXT6_CNTL 0x0583 |
|---|
| 3035 | #define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 |
|---|
| 3036 | #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 |
|---|
| 3037 | #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 3038 | #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 |
|---|
| 3039 | #define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 3040 | #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 |
|---|
| 3041 | #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 3042 | #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 |
|---|
| 3043 | #define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 3044 | #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 |
|---|
| 3045 | #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 3046 | #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 |
|---|
| 3047 | #define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 3048 | #define regDCN_VM_CONTEXT7_CNTL 0x058a |
|---|
| 3049 | #define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 |
|---|
| 3050 | #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b |
|---|
| 3051 | #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 3052 | #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c |
|---|
| 3053 | #define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 3054 | #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d |
|---|
| 3055 | #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 3056 | #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e |
|---|
| 3057 | #define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 3058 | #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f |
|---|
| 3059 | #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 3060 | #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 |
|---|
| 3061 | #define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 3062 | #define regDCN_VM_CONTEXT8_CNTL 0x0591 |
|---|
| 3063 | #define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 |
|---|
| 3064 | #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 |
|---|
| 3065 | #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 3066 | #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 |
|---|
| 3067 | #define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 3068 | #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 |
|---|
| 3069 | #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 3070 | #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 |
|---|
| 3071 | #define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 3072 | #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 |
|---|
| 3073 | #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 3074 | #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 |
|---|
| 3075 | #define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 3076 | #define regDCN_VM_CONTEXT9_CNTL 0x0598 |
|---|
| 3077 | #define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 |
|---|
| 3078 | #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 |
|---|
| 3079 | #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 3080 | #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a |
|---|
| 3081 | #define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 3082 | #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b |
|---|
| 3083 | #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 3084 | #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c |
|---|
| 3085 | #define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 3086 | #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d |
|---|
| 3087 | #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 3088 | #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e |
|---|
| 3089 | #define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 3090 | #define regDCN_VM_CONTEXT10_CNTL 0x059f |
|---|
| 3091 | #define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 |
|---|
| 3092 | #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 |
|---|
| 3093 | #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 3094 | #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 |
|---|
| 3095 | #define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 3096 | #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 |
|---|
| 3097 | #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 3098 | #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 |
|---|
| 3099 | #define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 3100 | #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 |
|---|
| 3101 | #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 3102 | #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 |
|---|
| 3103 | #define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 3104 | #define regDCN_VM_CONTEXT11_CNTL 0x05a6 |
|---|
| 3105 | #define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 |
|---|
| 3106 | #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 |
|---|
| 3107 | #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 3108 | #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 |
|---|
| 3109 | #define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 3110 | #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 |
|---|
| 3111 | #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 3112 | #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa |
|---|
| 3113 | #define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 3114 | #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab |
|---|
| 3115 | #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 3116 | #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac |
|---|
| 3117 | #define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 3118 | #define regDCN_VM_CONTEXT12_CNTL 0x05ad |
|---|
| 3119 | #define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 |
|---|
| 3120 | #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae |
|---|
| 3121 | #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 3122 | #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af |
|---|
| 3123 | #define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 3124 | #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 |
|---|
| 3125 | #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 3126 | #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 |
|---|
| 3127 | #define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 3128 | #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 |
|---|
| 3129 | #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 3130 | #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 |
|---|
| 3131 | #define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 3132 | #define regDCN_VM_CONTEXT13_CNTL 0x05b4 |
|---|
| 3133 | #define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 |
|---|
| 3134 | #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 |
|---|
| 3135 | #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 3136 | #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 |
|---|
| 3137 | #define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 3138 | #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 |
|---|
| 3139 | #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 3140 | #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 |
|---|
| 3141 | #define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 3142 | #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 |
|---|
| 3143 | #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 3144 | #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba |
|---|
| 3145 | #define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 3146 | #define regDCN_VM_CONTEXT14_CNTL 0x05bb |
|---|
| 3147 | #define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 |
|---|
| 3148 | #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc |
|---|
| 3149 | #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 3150 | #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd |
|---|
| 3151 | #define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 3152 | #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be |
|---|
| 3153 | #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 3154 | #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf |
|---|
| 3155 | #define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 3156 | #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 |
|---|
| 3157 | #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 3158 | #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 |
|---|
| 3159 | #define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 3160 | #define regDCN_VM_CONTEXT15_CNTL 0x05c2 |
|---|
| 3161 | #define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 |
|---|
| 3162 | #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 |
|---|
| 3163 | #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 |
|---|
| 3164 | #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 |
|---|
| 3165 | #define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 |
|---|
| 3166 | #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 |
|---|
| 3167 | #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 |
|---|
| 3168 | #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 |
|---|
| 3169 | #define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 |
|---|
| 3170 | #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 |
|---|
| 3171 | #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 |
|---|
| 3172 | #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 |
|---|
| 3173 | #define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 |
|---|
| 3174 | #define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 |
|---|
| 3175 | #define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 |
|---|
| 3176 | #define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca |
|---|
| 3177 | #define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 |
|---|
| 3178 | #define regDCN_VM_FAULT_CNTL 0x05cb |
|---|
| 3179 | #define regDCN_VM_FAULT_CNTL_BASE_IDX 2 |
|---|
| 3180 | #define regDCN_VM_FAULT_STATUS 0x05cc |
|---|
| 3181 | #define regDCN_VM_FAULT_STATUS_BASE_IDX 2 |
|---|
| 3182 | #define regDCN_VM_FAULT_ADDR_MSB 0x05cd |
|---|
| 3183 | #define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 |
|---|
| 3184 | #define regDCN_VM_FAULT_ADDR_LSB 0x05ce |
|---|
| 3185 | #define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 |
|---|
| 3186 | |
|---|
| 3187 | |
|---|
| 3188 | |
|---|
| 3189 | // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec |
|---|
| 3190 | // base address: 0x0 |
|---|
| 3191 | #define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 |
|---|
| 3192 | #define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 |
|---|
| 3193 | #define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 |
|---|
| 3194 | #define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 |
|---|
| 3195 | #define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 |
|---|
| 3196 | #define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 |
|---|
| 3197 | #define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 |
|---|
| 3198 | #define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 |
|---|
| 3199 | #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea |
|---|
| 3200 | #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 |
|---|
| 3201 | #define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb |
|---|
| 3202 | #define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 |
|---|
| 3203 | #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec |
|---|
| 3204 | #define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
|---|
| 3205 | #define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed |
|---|
| 3206 | #define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 |
|---|
| 3207 | #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee |
|---|
| 3208 | #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 |
|---|
| 3209 | #define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef |
|---|
| 3210 | #define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 |
|---|
| 3211 | #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 |
|---|
| 3212 | #define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
|---|
| 3213 | #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 |
|---|
| 3214 | #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 |
|---|
| 3215 | #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 |
|---|
| 3216 | #define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 |
|---|
| 3217 | #define regHUBP0_DCHUBP_CNTL 0x05f3 |
|---|
| 3218 | #define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 |
|---|
| 3219 | #define regHUBP0_HUBP_CLK_CNTL 0x05f4 |
|---|
| 3220 | #define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 |
|---|
| 3221 | #define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 |
|---|
| 3222 | #define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 |
|---|
| 3223 | #define regHUBP0_DCHUBP_MALL_CONFIG 0x05f6 |
|---|
| 3224 | #define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX 2 |
|---|
| 3225 | #define regHUBP0_DCHUBP_MALL_SUB_VP 0x05f7 |
|---|
| 3226 | #define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX 2 |
|---|
| 3227 | #define regHUBP0_HUBPREQ_DEBUG_DB 0x05f8 |
|---|
| 3228 | #define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 |
|---|
| 3229 | #define regHUBP0_HUBPREQ_DEBUG 0x05f9 |
|---|
| 3230 | #define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 |
|---|
| 3231 | #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fd |
|---|
| 3232 | #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 |
|---|
| 3233 | #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fe |
|---|
| 3234 | #define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 |
|---|
| 3235 | #define regHUBP0_HUBP_MALL_STATUS 0x05ff |
|---|
| 3236 | #define regHUBP0_HUBP_MALL_STATUS_BASE_IDX 2 |
|---|
| 3237 | |
|---|
| 3238 | |
|---|
| 3239 | // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec |
|---|
| 3240 | // base address: 0x0 |
|---|
| 3241 | #define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 |
|---|
| 3242 | #define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 |
|---|
| 3243 | #define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 |
|---|
| 3244 | #define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 |
|---|
| 3245 | #define regHUBPREQ0_VMID_SETTINGS_0 0x0609 |
|---|
| 3246 | #define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 |
|---|
| 3247 | #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a |
|---|
| 3248 | #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 3249 | #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b |
|---|
| 3250 | #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3251 | #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c |
|---|
| 3252 | #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 3253 | #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d |
|---|
| 3254 | #define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 3255 | #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e |
|---|
| 3256 | #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 3257 | #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f |
|---|
| 3258 | #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3259 | #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 |
|---|
| 3260 | #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 3261 | #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 |
|---|
| 3262 | #define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 3263 | #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 |
|---|
| 3264 | #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 3265 | #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 |
|---|
| 3266 | #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3267 | #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 |
|---|
| 3268 | #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 3269 | #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 |
|---|
| 3270 | #define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 3271 | #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 |
|---|
| 3272 | #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 3273 | #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 |
|---|
| 3274 | #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3275 | #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 |
|---|
| 3276 | #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 3277 | #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 |
|---|
| 3278 | #define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 3279 | #define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a |
|---|
| 3280 | #define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 |
|---|
| 3281 | #define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b |
|---|
| 3282 | #define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 |
|---|
| 3283 | #define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c |
|---|
| 3284 | #define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 |
|---|
| 3285 | #define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x061f |
|---|
| 3286 | #define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 |
|---|
| 3287 | #define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0620 |
|---|
| 3288 | #define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 |
|---|
| 3289 | #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0621 |
|---|
| 3290 | #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 |
|---|
| 3291 | #define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0622 |
|---|
| 3292 | #define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 |
|---|
| 3293 | #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0623 |
|---|
| 3294 | #define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 |
|---|
| 3295 | #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0624 |
|---|
| 3296 | #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 |
|---|
| 3297 | #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0625 |
|---|
| 3298 | #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 |
|---|
| 3299 | #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0626 |
|---|
| 3300 | #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 |
|---|
| 3301 | #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0627 |
|---|
| 3302 | #define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 |
|---|
| 3303 | #define regHUBPREQ0_DCN_EXPANSION_MODE 0x0628 |
|---|
| 3304 | #define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 |
|---|
| 3305 | #define regHUBPREQ0_DCN_TTU_QOS_WM 0x0629 |
|---|
| 3306 | #define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 |
|---|
| 3307 | #define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062a |
|---|
| 3308 | #define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 |
|---|
| 3309 | #define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062b |
|---|
| 3310 | #define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 |
|---|
| 3311 | #define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062c |
|---|
| 3312 | #define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 |
|---|
| 3313 | #define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062d |
|---|
| 3314 | #define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 |
|---|
| 3315 | #define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062e |
|---|
| 3316 | #define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 |
|---|
| 3317 | #define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x062f |
|---|
| 3318 | #define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 |
|---|
| 3319 | #define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0630 |
|---|
| 3320 | #define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 |
|---|
| 3321 | #define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0631 |
|---|
| 3322 | #define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 |
|---|
| 3323 | #define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0632 |
|---|
| 3324 | #define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 |
|---|
| 3325 | #define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0633 |
|---|
| 3326 | #define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 |
|---|
| 3327 | #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0634 |
|---|
| 3328 | #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 |
|---|
| 3329 | #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0635 |
|---|
| 3330 | #define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 |
|---|
| 3331 | #define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0642 |
|---|
| 3332 | #define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 |
|---|
| 3333 | #define regHUBPREQ0_BLANK_OFFSET_0 0x0643 |
|---|
| 3334 | #define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 |
|---|
| 3335 | #define regHUBPREQ0_BLANK_OFFSET_1 0x0644 |
|---|
| 3336 | #define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 |
|---|
| 3337 | #define regHUBPREQ0_DST_DIMENSIONS 0x0645 |
|---|
| 3338 | #define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 |
|---|
| 3339 | #define regHUBPREQ0_DST_AFTER_SCALER 0x0646 |
|---|
| 3340 | #define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 |
|---|
| 3341 | #define regHUBPREQ0_PREFETCH_SETTINGS 0x0647 |
|---|
| 3342 | #define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 |
|---|
| 3343 | #define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0648 |
|---|
| 3344 | #define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 |
|---|
| 3345 | #define regHUBPREQ0_VBLANK_PARAMETERS_0 0x0649 |
|---|
| 3346 | #define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 |
|---|
| 3347 | #define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064a |
|---|
| 3348 | #define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 |
|---|
| 3349 | #define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064b |
|---|
| 3350 | #define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 |
|---|
| 3351 | #define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064c |
|---|
| 3352 | #define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 |
|---|
| 3353 | #define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064d |
|---|
| 3354 | #define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 |
|---|
| 3355 | #define regHUBPREQ0_FLIP_PARAMETERS_0 0x064e |
|---|
| 3356 | #define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 |
|---|
| 3357 | #define regHUBPREQ0_FLIP_PARAMETERS_1 0x064f |
|---|
| 3358 | #define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 |
|---|
| 3359 | #define regHUBPREQ0_FLIP_PARAMETERS_2 0x0650 |
|---|
| 3360 | #define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 |
|---|
| 3361 | #define regHUBPREQ0_NOM_PARAMETERS_0 0x0651 |
|---|
| 3362 | #define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 |
|---|
| 3363 | #define regHUBPREQ0_NOM_PARAMETERS_1 0x0652 |
|---|
| 3364 | #define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 |
|---|
| 3365 | #define regHUBPREQ0_NOM_PARAMETERS_2 0x0653 |
|---|
| 3366 | #define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 |
|---|
| 3367 | #define regHUBPREQ0_NOM_PARAMETERS_3 0x0654 |
|---|
| 3368 | #define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 |
|---|
| 3369 | #define regHUBPREQ0_NOM_PARAMETERS_4 0x0655 |
|---|
| 3370 | #define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 |
|---|
| 3371 | #define regHUBPREQ0_NOM_PARAMETERS_5 0x0656 |
|---|
| 3372 | #define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 |
|---|
| 3373 | #define regHUBPREQ0_NOM_PARAMETERS_6 0x0657 |
|---|
| 3374 | #define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 |
|---|
| 3375 | #define regHUBPREQ0_NOM_PARAMETERS_7 0x0658 |
|---|
| 3376 | #define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 |
|---|
| 3377 | #define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x0659 |
|---|
| 3378 | #define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 |
|---|
| 3379 | #define regHUBPREQ0_PER_LINE_DELIVERY 0x065a |
|---|
| 3380 | #define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 |
|---|
| 3381 | #define regHUBPREQ0_CURSOR_SETTINGS 0x065b |
|---|
| 3382 | #define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 |
|---|
| 3383 | #define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065c |
|---|
| 3384 | #define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 |
|---|
| 3385 | #define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065d |
|---|
| 3386 | #define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 |
|---|
| 3387 | #define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065e |
|---|
| 3388 | #define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 3389 | #define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x065f |
|---|
| 3390 | #define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 3391 | #define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0662 |
|---|
| 3392 | #define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 |
|---|
| 3393 | #define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0663 |
|---|
| 3394 | #define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 |
|---|
| 3395 | #define regHUBPREQ0_FLIP_PARAMETERS_3 0x0664 |
|---|
| 3396 | #define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 |
|---|
| 3397 | #define regHUBPREQ0_FLIP_PARAMETERS_4 0x0665 |
|---|
| 3398 | #define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 |
|---|
| 3399 | #define regHUBPREQ0_FLIP_PARAMETERS_5 0x0666 |
|---|
| 3400 | #define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 |
|---|
| 3401 | #define regHUBPREQ0_FLIP_PARAMETERS_6 0x0667 |
|---|
| 3402 | #define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 |
|---|
| 3403 | #define regHUBPREQ0_UCLK_PSTATE_FORCE 0x0668 |
|---|
| 3404 | #define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX 2 |
|---|
| 3405 | #define regHUBPREQ0_HUBPREQ_STATUS_REG0 0x0669 |
|---|
| 3406 | #define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX 2 |
|---|
| 3407 | #define regHUBPREQ0_HUBPREQ_STATUS_REG1 0x066a |
|---|
| 3408 | #define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX 2 |
|---|
| 3409 | #define regHUBPREQ0_HUBPREQ_STATUS_REG2 0x066b |
|---|
| 3410 | #define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX 2 |
|---|
| 3411 | |
|---|
| 3412 | |
|---|
| 3413 | // addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec |
|---|
| 3414 | // base address: 0x0 |
|---|
| 3415 | #define regHUBPRET0_HUBPRET_CONTROL 0x066c |
|---|
| 3416 | #define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 |
|---|
| 3417 | #define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d |
|---|
| 3418 | #define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 3419 | #define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e |
|---|
| 3420 | #define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 3421 | #define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f |
|---|
| 3422 | #define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 |
|---|
| 3423 | #define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 |
|---|
| 3424 | #define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 |
|---|
| 3425 | #define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 |
|---|
| 3426 | #define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 |
|---|
| 3427 | #define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 |
|---|
| 3428 | #define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 |
|---|
| 3429 | #define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 |
|---|
| 3430 | #define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 |
|---|
| 3431 | #define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 |
|---|
| 3432 | #define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 |
|---|
| 3433 | #define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 |
|---|
| 3434 | #define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 |
|---|
| 3435 | |
|---|
| 3436 | |
|---|
| 3437 | // addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec |
|---|
| 3438 | // base address: 0x0 |
|---|
| 3439 | #define regCURSOR0_0_CURSOR_CONTROL 0x0678 |
|---|
| 3440 | #define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 |
|---|
| 3441 | #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 |
|---|
| 3442 | #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 3443 | #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a |
|---|
| 3444 | #define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3445 | #define regCURSOR0_0_CURSOR_SIZE 0x067b |
|---|
| 3446 | #define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 |
|---|
| 3447 | #define regCURSOR0_0_CURSOR_POSITION 0x067c |
|---|
| 3448 | #define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 |
|---|
| 3449 | #define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d |
|---|
| 3450 | #define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 |
|---|
| 3451 | #define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e |
|---|
| 3452 | #define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 |
|---|
| 3453 | #define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f |
|---|
| 3454 | #define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 |
|---|
| 3455 | #define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 |
|---|
| 3456 | #define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 3457 | #define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 |
|---|
| 3458 | #define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 3459 | #define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 |
|---|
| 3460 | #define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3461 | #define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 |
|---|
| 3462 | #define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 |
|---|
| 3463 | #define regCURSOR0_0_DMDATA_CNTL 0x0684 |
|---|
| 3464 | #define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 |
|---|
| 3465 | #define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 |
|---|
| 3466 | #define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 |
|---|
| 3467 | #define regCURSOR0_0_DMDATA_STATUS 0x0686 |
|---|
| 3468 | #define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 |
|---|
| 3469 | #define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 |
|---|
| 3470 | #define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 |
|---|
| 3471 | #define regCURSOR0_0_DMDATA_SW_DATA 0x0688 |
|---|
| 3472 | #define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 |
|---|
| 3473 | |
|---|
| 3474 | |
|---|
| 3475 | // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec |
|---|
| 3476 | // base address: 0x1a74 |
|---|
| 3477 | #define regDC_PERFMON7_PERFCOUNTER_CNTL 0x069d |
|---|
| 3478 | #define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 3479 | #define regDC_PERFMON7_PERFCOUNTER_CNTL2 0x069e |
|---|
| 3480 | #define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 3481 | #define regDC_PERFMON7_PERFCOUNTER_STATE 0x069f |
|---|
| 3482 | #define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 3483 | #define regDC_PERFMON7_PERFMON_CNTL 0x06a0 |
|---|
| 3484 | #define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 3485 | #define regDC_PERFMON7_PERFMON_CNTL2 0x06a1 |
|---|
| 3486 | #define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 3487 | #define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x06a2 |
|---|
| 3488 | #define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 3489 | #define regDC_PERFMON7_PERFMON_CVALUE_LOW 0x06a3 |
|---|
| 3490 | #define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 3491 | #define regDC_PERFMON7_PERFMON_HI 0x06a4 |
|---|
| 3492 | #define regDC_PERFMON7_PERFMON_HI_BASE_IDX 2 |
|---|
| 3493 | #define regDC_PERFMON7_PERFMON_LOW 0x06a5 |
|---|
| 3494 | #define regDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 |
|---|
| 3495 | |
|---|
| 3496 | |
|---|
| 3497 | // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec |
|---|
| 3498 | // base address: 0x370 |
|---|
| 3499 | #define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 |
|---|
| 3500 | #define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 |
|---|
| 3501 | #define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 |
|---|
| 3502 | #define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 |
|---|
| 3503 | #define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 |
|---|
| 3504 | #define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 |
|---|
| 3505 | #define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 |
|---|
| 3506 | #define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 |
|---|
| 3507 | #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 |
|---|
| 3508 | #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 |
|---|
| 3509 | #define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 |
|---|
| 3510 | #define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 |
|---|
| 3511 | #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 |
|---|
| 3512 | #define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
|---|
| 3513 | #define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 |
|---|
| 3514 | #define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 |
|---|
| 3515 | #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca |
|---|
| 3516 | #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 |
|---|
| 3517 | #define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb |
|---|
| 3518 | #define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 |
|---|
| 3519 | #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc |
|---|
| 3520 | #define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
|---|
| 3521 | #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd |
|---|
| 3522 | #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 |
|---|
| 3523 | #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce |
|---|
| 3524 | #define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 |
|---|
| 3525 | #define regHUBP1_DCHUBP_CNTL 0x06cf |
|---|
| 3526 | #define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 |
|---|
| 3527 | #define regHUBP1_HUBP_CLK_CNTL 0x06d0 |
|---|
| 3528 | #define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 |
|---|
| 3529 | #define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 |
|---|
| 3530 | #define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 |
|---|
| 3531 | #define regHUBP1_DCHUBP_MALL_CONFIG 0x06d2 |
|---|
| 3532 | #define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX 2 |
|---|
| 3533 | #define regHUBP1_DCHUBP_MALL_SUB_VP 0x06d3 |
|---|
| 3534 | #define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX 2 |
|---|
| 3535 | #define regHUBP1_HUBPREQ_DEBUG_DB 0x06d4 |
|---|
| 3536 | #define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 |
|---|
| 3537 | #define regHUBP1_HUBPREQ_DEBUG 0x06d5 |
|---|
| 3538 | #define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 |
|---|
| 3539 | #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d9 |
|---|
| 3540 | #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 |
|---|
| 3541 | #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06da |
|---|
| 3542 | #define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 |
|---|
| 3543 | #define regHUBP1_HUBP_MALL_STATUS 0x06db |
|---|
| 3544 | #define regHUBP1_HUBP_MALL_STATUS_BASE_IDX 2 |
|---|
| 3545 | |
|---|
| 3546 | |
|---|
| 3547 | // addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec |
|---|
| 3548 | // base address: 0x370 |
|---|
| 3549 | #define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 |
|---|
| 3550 | #define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 |
|---|
| 3551 | #define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 |
|---|
| 3552 | #define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 |
|---|
| 3553 | #define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 |
|---|
| 3554 | #define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 |
|---|
| 3555 | #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 |
|---|
| 3556 | #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 3557 | #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 |
|---|
| 3558 | #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3559 | #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 |
|---|
| 3560 | #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 3561 | #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 |
|---|
| 3562 | #define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 3563 | #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea |
|---|
| 3564 | #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 3565 | #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb |
|---|
| 3566 | #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3567 | #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec |
|---|
| 3568 | #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 3569 | #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed |
|---|
| 3570 | #define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 3571 | #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee |
|---|
| 3572 | #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 3573 | #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef |
|---|
| 3574 | #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3575 | #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 |
|---|
| 3576 | #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 3577 | #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 |
|---|
| 3578 | #define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 3579 | #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 |
|---|
| 3580 | #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 3581 | #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 |
|---|
| 3582 | #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3583 | #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 |
|---|
| 3584 | #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 3585 | #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 |
|---|
| 3586 | #define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 3587 | #define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 |
|---|
| 3588 | #define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 |
|---|
| 3589 | #define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 |
|---|
| 3590 | #define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 |
|---|
| 3591 | #define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 |
|---|
| 3592 | #define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 |
|---|
| 3593 | #define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fb |
|---|
| 3594 | #define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 |
|---|
| 3595 | #define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fc |
|---|
| 3596 | #define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 |
|---|
| 3597 | #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fd |
|---|
| 3598 | #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 |
|---|
| 3599 | #define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06fe |
|---|
| 3600 | #define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 |
|---|
| 3601 | #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x06ff |
|---|
| 3602 | #define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 |
|---|
| 3603 | #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0700 |
|---|
| 3604 | #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 |
|---|
| 3605 | #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0701 |
|---|
| 3606 | #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 |
|---|
| 3607 | #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0702 |
|---|
| 3608 | #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 |
|---|
| 3609 | #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0703 |
|---|
| 3610 | #define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 |
|---|
| 3611 | #define regHUBPREQ1_DCN_EXPANSION_MODE 0x0704 |
|---|
| 3612 | #define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 |
|---|
| 3613 | #define regHUBPREQ1_DCN_TTU_QOS_WM 0x0705 |
|---|
| 3614 | #define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 |
|---|
| 3615 | #define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0706 |
|---|
| 3616 | #define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 |
|---|
| 3617 | #define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0707 |
|---|
| 3618 | #define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 |
|---|
| 3619 | #define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0708 |
|---|
| 3620 | #define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 |
|---|
| 3621 | #define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0709 |
|---|
| 3622 | #define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 |
|---|
| 3623 | #define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070a |
|---|
| 3624 | #define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 |
|---|
| 3625 | #define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070b |
|---|
| 3626 | #define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 |
|---|
| 3627 | #define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070c |
|---|
| 3628 | #define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 |
|---|
| 3629 | #define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070d |
|---|
| 3630 | #define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 |
|---|
| 3631 | #define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070e |
|---|
| 3632 | #define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 |
|---|
| 3633 | #define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x070f |
|---|
| 3634 | #define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 |
|---|
| 3635 | #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0710 |
|---|
| 3636 | #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 |
|---|
| 3637 | #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0711 |
|---|
| 3638 | #define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 |
|---|
| 3639 | #define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071e |
|---|
| 3640 | #define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 |
|---|
| 3641 | #define regHUBPREQ1_BLANK_OFFSET_0 0x071f |
|---|
| 3642 | #define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 |
|---|
| 3643 | #define regHUBPREQ1_BLANK_OFFSET_1 0x0720 |
|---|
| 3644 | #define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 |
|---|
| 3645 | #define regHUBPREQ1_DST_DIMENSIONS 0x0721 |
|---|
| 3646 | #define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 |
|---|
| 3647 | #define regHUBPREQ1_DST_AFTER_SCALER 0x0722 |
|---|
| 3648 | #define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 |
|---|
| 3649 | #define regHUBPREQ1_PREFETCH_SETTINGS 0x0723 |
|---|
| 3650 | #define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 |
|---|
| 3651 | #define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0724 |
|---|
| 3652 | #define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 |
|---|
| 3653 | #define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0725 |
|---|
| 3654 | #define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 |
|---|
| 3655 | #define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0726 |
|---|
| 3656 | #define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 |
|---|
| 3657 | #define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0727 |
|---|
| 3658 | #define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 |
|---|
| 3659 | #define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0728 |
|---|
| 3660 | #define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 |
|---|
| 3661 | #define regHUBPREQ1_VBLANK_PARAMETERS_4 0x0729 |
|---|
| 3662 | #define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 |
|---|
| 3663 | #define regHUBPREQ1_FLIP_PARAMETERS_0 0x072a |
|---|
| 3664 | #define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 |
|---|
| 3665 | #define regHUBPREQ1_FLIP_PARAMETERS_1 0x072b |
|---|
| 3666 | #define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 |
|---|
| 3667 | #define regHUBPREQ1_FLIP_PARAMETERS_2 0x072c |
|---|
| 3668 | #define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 |
|---|
| 3669 | #define regHUBPREQ1_NOM_PARAMETERS_0 0x072d |
|---|
| 3670 | #define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 |
|---|
| 3671 | #define regHUBPREQ1_NOM_PARAMETERS_1 0x072e |
|---|
| 3672 | #define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 |
|---|
| 3673 | #define regHUBPREQ1_NOM_PARAMETERS_2 0x072f |
|---|
| 3674 | #define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 |
|---|
| 3675 | #define regHUBPREQ1_NOM_PARAMETERS_3 0x0730 |
|---|
| 3676 | #define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 |
|---|
| 3677 | #define regHUBPREQ1_NOM_PARAMETERS_4 0x0731 |
|---|
| 3678 | #define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 |
|---|
| 3679 | #define regHUBPREQ1_NOM_PARAMETERS_5 0x0732 |
|---|
| 3680 | #define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 |
|---|
| 3681 | #define regHUBPREQ1_NOM_PARAMETERS_6 0x0733 |
|---|
| 3682 | #define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 |
|---|
| 3683 | #define regHUBPREQ1_NOM_PARAMETERS_7 0x0734 |
|---|
| 3684 | #define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 |
|---|
| 3685 | #define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0735 |
|---|
| 3686 | #define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 |
|---|
| 3687 | #define regHUBPREQ1_PER_LINE_DELIVERY 0x0736 |
|---|
| 3688 | #define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 |
|---|
| 3689 | #define regHUBPREQ1_CURSOR_SETTINGS 0x0737 |
|---|
| 3690 | #define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 |
|---|
| 3691 | #define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0738 |
|---|
| 3692 | #define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 |
|---|
| 3693 | #define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x0739 |
|---|
| 3694 | #define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 |
|---|
| 3695 | #define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073a |
|---|
| 3696 | #define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 3697 | #define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073b |
|---|
| 3698 | #define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 3699 | #define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073e |
|---|
| 3700 | #define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 |
|---|
| 3701 | #define regHUBPREQ1_VBLANK_PARAMETERS_6 0x073f |
|---|
| 3702 | #define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 |
|---|
| 3703 | #define regHUBPREQ1_FLIP_PARAMETERS_3 0x0740 |
|---|
| 3704 | #define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 |
|---|
| 3705 | #define regHUBPREQ1_FLIP_PARAMETERS_4 0x0741 |
|---|
| 3706 | #define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 |
|---|
| 3707 | #define regHUBPREQ1_FLIP_PARAMETERS_5 0x0742 |
|---|
| 3708 | #define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 |
|---|
| 3709 | #define regHUBPREQ1_FLIP_PARAMETERS_6 0x0743 |
|---|
| 3710 | #define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 |
|---|
| 3711 | #define regHUBPREQ1_UCLK_PSTATE_FORCE 0x0744 |
|---|
| 3712 | #define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX 2 |
|---|
| 3713 | #define regHUBPREQ1_HUBPREQ_STATUS_REG0 0x0745 |
|---|
| 3714 | #define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX 2 |
|---|
| 3715 | #define regHUBPREQ1_HUBPREQ_STATUS_REG1 0x0746 |
|---|
| 3716 | #define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX 2 |
|---|
| 3717 | #define regHUBPREQ1_HUBPREQ_STATUS_REG2 0x0747 |
|---|
| 3718 | #define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX 2 |
|---|
| 3719 | |
|---|
| 3720 | |
|---|
| 3721 | // addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec |
|---|
| 3722 | // base address: 0x370 |
|---|
| 3723 | #define regHUBPRET1_HUBPRET_CONTROL 0x0748 |
|---|
| 3724 | #define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 |
|---|
| 3725 | #define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 |
|---|
| 3726 | #define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 3727 | #define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a |
|---|
| 3728 | #define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 3729 | #define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b |
|---|
| 3730 | #define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 |
|---|
| 3731 | #define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c |
|---|
| 3732 | #define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 |
|---|
| 3733 | #define regHUBPRET1_HUBPRET_READ_LINE0 0x074d |
|---|
| 3734 | #define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 |
|---|
| 3735 | #define regHUBPRET1_HUBPRET_READ_LINE1 0x074e |
|---|
| 3736 | #define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 |
|---|
| 3737 | #define regHUBPRET1_HUBPRET_INTERRUPT 0x074f |
|---|
| 3738 | #define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 |
|---|
| 3739 | #define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 |
|---|
| 3740 | #define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 |
|---|
| 3741 | #define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 |
|---|
| 3742 | #define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 |
|---|
| 3743 | |
|---|
| 3744 | |
|---|
| 3745 | // addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec |
|---|
| 3746 | // base address: 0x370 |
|---|
| 3747 | #define regCURSOR0_1_CURSOR_CONTROL 0x0754 |
|---|
| 3748 | #define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 |
|---|
| 3749 | #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 |
|---|
| 3750 | #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 3751 | #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 |
|---|
| 3752 | #define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3753 | #define regCURSOR0_1_CURSOR_SIZE 0x0757 |
|---|
| 3754 | #define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 |
|---|
| 3755 | #define regCURSOR0_1_CURSOR_POSITION 0x0758 |
|---|
| 3756 | #define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 |
|---|
| 3757 | #define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 |
|---|
| 3758 | #define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 |
|---|
| 3759 | #define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a |
|---|
| 3760 | #define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 |
|---|
| 3761 | #define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b |
|---|
| 3762 | #define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 |
|---|
| 3763 | #define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c |
|---|
| 3764 | #define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 3765 | #define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d |
|---|
| 3766 | #define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 3767 | #define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e |
|---|
| 3768 | #define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3769 | #define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f |
|---|
| 3770 | #define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 |
|---|
| 3771 | #define regCURSOR0_1_DMDATA_CNTL 0x0760 |
|---|
| 3772 | #define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 |
|---|
| 3773 | #define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 |
|---|
| 3774 | #define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 |
|---|
| 3775 | #define regCURSOR0_1_DMDATA_STATUS 0x0762 |
|---|
| 3776 | #define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 |
|---|
| 3777 | #define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 |
|---|
| 3778 | #define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 |
|---|
| 3779 | #define regCURSOR0_1_DMDATA_SW_DATA 0x0764 |
|---|
| 3780 | #define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 |
|---|
| 3781 | |
|---|
| 3782 | |
|---|
| 3783 | // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec |
|---|
| 3784 | // base address: 0x1de4 |
|---|
| 3785 | #define regDC_PERFMON8_PERFCOUNTER_CNTL 0x0779 |
|---|
| 3786 | #define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 3787 | #define regDC_PERFMON8_PERFCOUNTER_CNTL2 0x077a |
|---|
| 3788 | #define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 3789 | #define regDC_PERFMON8_PERFCOUNTER_STATE 0x077b |
|---|
| 3790 | #define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 3791 | #define regDC_PERFMON8_PERFMON_CNTL 0x077c |
|---|
| 3792 | #define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 3793 | #define regDC_PERFMON8_PERFMON_CNTL2 0x077d |
|---|
| 3794 | #define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 3795 | #define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x077e |
|---|
| 3796 | #define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 3797 | #define regDC_PERFMON8_PERFMON_CVALUE_LOW 0x077f |
|---|
| 3798 | #define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 3799 | #define regDC_PERFMON8_PERFMON_HI 0x0780 |
|---|
| 3800 | #define regDC_PERFMON8_PERFMON_HI_BASE_IDX 2 |
|---|
| 3801 | #define regDC_PERFMON8_PERFMON_LOW 0x0781 |
|---|
| 3802 | #define regDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 |
|---|
| 3803 | |
|---|
| 3804 | |
|---|
| 3805 | // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec |
|---|
| 3806 | // base address: 0x6e0 |
|---|
| 3807 | #define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d |
|---|
| 3808 | #define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 |
|---|
| 3809 | #define regHUBP2_DCSURF_ADDR_CONFIG 0x079e |
|---|
| 3810 | #define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 |
|---|
| 3811 | #define regHUBP2_DCSURF_TILING_CONFIG 0x079f |
|---|
| 3812 | #define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 |
|---|
| 3813 | #define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 |
|---|
| 3814 | #define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 |
|---|
| 3815 | #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 |
|---|
| 3816 | #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 |
|---|
| 3817 | #define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 |
|---|
| 3818 | #define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 |
|---|
| 3819 | #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 |
|---|
| 3820 | #define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
|---|
| 3821 | #define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 |
|---|
| 3822 | #define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 |
|---|
| 3823 | #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 |
|---|
| 3824 | #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 |
|---|
| 3825 | #define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 |
|---|
| 3826 | #define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 |
|---|
| 3827 | #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 |
|---|
| 3828 | #define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
|---|
| 3829 | #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 |
|---|
| 3830 | #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 |
|---|
| 3831 | #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa |
|---|
| 3832 | #define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 |
|---|
| 3833 | #define regHUBP2_DCHUBP_CNTL 0x07ab |
|---|
| 3834 | #define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 |
|---|
| 3835 | #define regHUBP2_HUBP_CLK_CNTL 0x07ac |
|---|
| 3836 | #define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 |
|---|
| 3837 | #define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad |
|---|
| 3838 | #define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 |
|---|
| 3839 | #define regHUBP2_DCHUBP_MALL_CONFIG 0x07ae |
|---|
| 3840 | #define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX 2 |
|---|
| 3841 | #define regHUBP2_DCHUBP_MALL_SUB_VP 0x07af |
|---|
| 3842 | #define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX 2 |
|---|
| 3843 | #define regHUBP2_HUBPREQ_DEBUG_DB 0x07b0 |
|---|
| 3844 | #define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 |
|---|
| 3845 | #define regHUBP2_HUBPREQ_DEBUG 0x07b1 |
|---|
| 3846 | #define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 |
|---|
| 3847 | #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b5 |
|---|
| 3848 | #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 |
|---|
| 3849 | #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b6 |
|---|
| 3850 | #define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 |
|---|
| 3851 | #define regHUBP2_HUBP_MALL_STATUS 0x07b7 |
|---|
| 3852 | #define regHUBP2_HUBP_MALL_STATUS_BASE_IDX 2 |
|---|
| 3853 | |
|---|
| 3854 | |
|---|
| 3855 | // addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec |
|---|
| 3856 | // base address: 0x6e0 |
|---|
| 3857 | #define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf |
|---|
| 3858 | #define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 |
|---|
| 3859 | #define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 |
|---|
| 3860 | #define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 |
|---|
| 3861 | #define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 |
|---|
| 3862 | #define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 |
|---|
| 3863 | #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 |
|---|
| 3864 | #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 3865 | #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 |
|---|
| 3866 | #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3867 | #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 |
|---|
| 3868 | #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 3869 | #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 |
|---|
| 3870 | #define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 3871 | #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 |
|---|
| 3872 | #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 3873 | #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 |
|---|
| 3874 | #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3875 | #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 |
|---|
| 3876 | #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 3877 | #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 |
|---|
| 3878 | #define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 3879 | #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca |
|---|
| 3880 | #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 3881 | #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb |
|---|
| 3882 | #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3883 | #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc |
|---|
| 3884 | #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 3885 | #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd |
|---|
| 3886 | #define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 3887 | #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce |
|---|
| 3888 | #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 3889 | #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf |
|---|
| 3890 | #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 3891 | #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 |
|---|
| 3892 | #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 3893 | #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 |
|---|
| 3894 | #define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 3895 | #define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 |
|---|
| 3896 | #define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 |
|---|
| 3897 | #define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 |
|---|
| 3898 | #define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 |
|---|
| 3899 | #define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 |
|---|
| 3900 | #define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 |
|---|
| 3901 | #define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d7 |
|---|
| 3902 | #define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 |
|---|
| 3903 | #define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d8 |
|---|
| 3904 | #define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 |
|---|
| 3905 | #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07d9 |
|---|
| 3906 | #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 |
|---|
| 3907 | #define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07da |
|---|
| 3908 | #define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 |
|---|
| 3909 | #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07db |
|---|
| 3910 | #define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 |
|---|
| 3911 | #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dc |
|---|
| 3912 | #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 |
|---|
| 3913 | #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07dd |
|---|
| 3914 | #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 |
|---|
| 3915 | #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07de |
|---|
| 3916 | #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 |
|---|
| 3917 | #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07df |
|---|
| 3918 | #define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 |
|---|
| 3919 | #define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e0 |
|---|
| 3920 | #define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 |
|---|
| 3921 | #define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e1 |
|---|
| 3922 | #define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 |
|---|
| 3923 | #define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e2 |
|---|
| 3924 | #define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 |
|---|
| 3925 | #define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e3 |
|---|
| 3926 | #define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 |
|---|
| 3927 | #define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e4 |
|---|
| 3928 | #define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 |
|---|
| 3929 | #define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e5 |
|---|
| 3930 | #define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 |
|---|
| 3931 | #define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e6 |
|---|
| 3932 | #define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 |
|---|
| 3933 | #define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e7 |
|---|
| 3934 | #define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 |
|---|
| 3935 | #define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e8 |
|---|
| 3936 | #define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 |
|---|
| 3937 | #define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07e9 |
|---|
| 3938 | #define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 |
|---|
| 3939 | #define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ea |
|---|
| 3940 | #define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 |
|---|
| 3941 | #define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07eb |
|---|
| 3942 | #define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 |
|---|
| 3943 | #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ec |
|---|
| 3944 | #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 |
|---|
| 3945 | #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ed |
|---|
| 3946 | #define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 |
|---|
| 3947 | #define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fa |
|---|
| 3948 | #define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 |
|---|
| 3949 | #define regHUBPREQ2_BLANK_OFFSET_0 0x07fb |
|---|
| 3950 | #define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 |
|---|
| 3951 | #define regHUBPREQ2_BLANK_OFFSET_1 0x07fc |
|---|
| 3952 | #define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 |
|---|
| 3953 | #define regHUBPREQ2_DST_DIMENSIONS 0x07fd |
|---|
| 3954 | #define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 |
|---|
| 3955 | #define regHUBPREQ2_DST_AFTER_SCALER 0x07fe |
|---|
| 3956 | #define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 |
|---|
| 3957 | #define regHUBPREQ2_PREFETCH_SETTINGS 0x07ff |
|---|
| 3958 | #define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 |
|---|
| 3959 | #define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0800 |
|---|
| 3960 | #define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 |
|---|
| 3961 | #define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0801 |
|---|
| 3962 | #define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 |
|---|
| 3963 | #define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0802 |
|---|
| 3964 | #define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 |
|---|
| 3965 | #define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0803 |
|---|
| 3966 | #define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 |
|---|
| 3967 | #define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0804 |
|---|
| 3968 | #define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 |
|---|
| 3969 | #define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0805 |
|---|
| 3970 | #define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 |
|---|
| 3971 | #define regHUBPREQ2_FLIP_PARAMETERS_0 0x0806 |
|---|
| 3972 | #define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 |
|---|
| 3973 | #define regHUBPREQ2_FLIP_PARAMETERS_1 0x0807 |
|---|
| 3974 | #define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 |
|---|
| 3975 | #define regHUBPREQ2_FLIP_PARAMETERS_2 0x0808 |
|---|
| 3976 | #define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 |
|---|
| 3977 | #define regHUBPREQ2_NOM_PARAMETERS_0 0x0809 |
|---|
| 3978 | #define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 |
|---|
| 3979 | #define regHUBPREQ2_NOM_PARAMETERS_1 0x080a |
|---|
| 3980 | #define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 |
|---|
| 3981 | #define regHUBPREQ2_NOM_PARAMETERS_2 0x080b |
|---|
| 3982 | #define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 |
|---|
| 3983 | #define regHUBPREQ2_NOM_PARAMETERS_3 0x080c |
|---|
| 3984 | #define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 |
|---|
| 3985 | #define regHUBPREQ2_NOM_PARAMETERS_4 0x080d |
|---|
| 3986 | #define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 |
|---|
| 3987 | #define regHUBPREQ2_NOM_PARAMETERS_5 0x080e |
|---|
| 3988 | #define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 |
|---|
| 3989 | #define regHUBPREQ2_NOM_PARAMETERS_6 0x080f |
|---|
| 3990 | #define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 |
|---|
| 3991 | #define regHUBPREQ2_NOM_PARAMETERS_7 0x0810 |
|---|
| 3992 | #define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 |
|---|
| 3993 | #define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0811 |
|---|
| 3994 | #define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 |
|---|
| 3995 | #define regHUBPREQ2_PER_LINE_DELIVERY 0x0812 |
|---|
| 3996 | #define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 |
|---|
| 3997 | #define regHUBPREQ2_CURSOR_SETTINGS 0x0813 |
|---|
| 3998 | #define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 |
|---|
| 3999 | #define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0814 |
|---|
| 4000 | #define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 |
|---|
| 4001 | #define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0815 |
|---|
| 4002 | #define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 |
|---|
| 4003 | #define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0816 |
|---|
| 4004 | #define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 4005 | #define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0817 |
|---|
| 4006 | #define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 4007 | #define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081a |
|---|
| 4008 | #define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 |
|---|
| 4009 | #define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081b |
|---|
| 4010 | #define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 |
|---|
| 4011 | #define regHUBPREQ2_FLIP_PARAMETERS_3 0x081c |
|---|
| 4012 | #define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 |
|---|
| 4013 | #define regHUBPREQ2_FLIP_PARAMETERS_4 0x081d |
|---|
| 4014 | #define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 |
|---|
| 4015 | #define regHUBPREQ2_FLIP_PARAMETERS_5 0x081e |
|---|
| 4016 | #define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 |
|---|
| 4017 | #define regHUBPREQ2_FLIP_PARAMETERS_6 0x081f |
|---|
| 4018 | #define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 |
|---|
| 4019 | #define regHUBPREQ2_UCLK_PSTATE_FORCE 0x0820 |
|---|
| 4020 | #define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX 2 |
|---|
| 4021 | #define regHUBPREQ2_HUBPREQ_STATUS_REG0 0x0821 |
|---|
| 4022 | #define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX 2 |
|---|
| 4023 | #define regHUBPREQ2_HUBPREQ_STATUS_REG1 0x0822 |
|---|
| 4024 | #define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX 2 |
|---|
| 4025 | #define regHUBPREQ2_HUBPREQ_STATUS_REG2 0x0823 |
|---|
| 4026 | #define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX 2 |
|---|
| 4027 | |
|---|
| 4028 | |
|---|
| 4029 | // addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec |
|---|
| 4030 | // base address: 0x6e0 |
|---|
| 4031 | #define regHUBPRET2_HUBPRET_CONTROL 0x0824 |
|---|
| 4032 | #define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 |
|---|
| 4033 | #define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 |
|---|
| 4034 | #define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 4035 | #define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 |
|---|
| 4036 | #define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 4037 | #define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 |
|---|
| 4038 | #define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 |
|---|
| 4039 | #define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 |
|---|
| 4040 | #define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 |
|---|
| 4041 | #define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 |
|---|
| 4042 | #define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 |
|---|
| 4043 | #define regHUBPRET2_HUBPRET_READ_LINE1 0x082a |
|---|
| 4044 | #define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 |
|---|
| 4045 | #define regHUBPRET2_HUBPRET_INTERRUPT 0x082b |
|---|
| 4046 | #define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 |
|---|
| 4047 | #define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c |
|---|
| 4048 | #define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 |
|---|
| 4049 | #define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d |
|---|
| 4050 | #define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 |
|---|
| 4051 | |
|---|
| 4052 | |
|---|
| 4053 | // addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec |
|---|
| 4054 | // base address: 0x6e0 |
|---|
| 4055 | #define regCURSOR0_2_CURSOR_CONTROL 0x0830 |
|---|
| 4056 | #define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 |
|---|
| 4057 | #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 |
|---|
| 4058 | #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 4059 | #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 |
|---|
| 4060 | #define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 4061 | #define regCURSOR0_2_CURSOR_SIZE 0x0833 |
|---|
| 4062 | #define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 |
|---|
| 4063 | #define regCURSOR0_2_CURSOR_POSITION 0x0834 |
|---|
| 4064 | #define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 |
|---|
| 4065 | #define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 |
|---|
| 4066 | #define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 |
|---|
| 4067 | #define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 |
|---|
| 4068 | #define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 |
|---|
| 4069 | #define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 |
|---|
| 4070 | #define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 |
|---|
| 4071 | #define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 |
|---|
| 4072 | #define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 4073 | #define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 |
|---|
| 4074 | #define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 4075 | #define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a |
|---|
| 4076 | #define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 4077 | #define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b |
|---|
| 4078 | #define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 |
|---|
| 4079 | #define regCURSOR0_2_DMDATA_CNTL 0x083c |
|---|
| 4080 | #define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 |
|---|
| 4081 | #define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d |
|---|
| 4082 | #define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 |
|---|
| 4083 | #define regCURSOR0_2_DMDATA_STATUS 0x083e |
|---|
| 4084 | #define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 |
|---|
| 4085 | #define regCURSOR0_2_DMDATA_SW_CNTL 0x083f |
|---|
| 4086 | #define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 |
|---|
| 4087 | #define regCURSOR0_2_DMDATA_SW_DATA 0x0840 |
|---|
| 4088 | #define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 |
|---|
| 4089 | |
|---|
| 4090 | |
|---|
| 4091 | // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec |
|---|
| 4092 | // base address: 0x2154 |
|---|
| 4093 | #define regDC_PERFMON9_PERFCOUNTER_CNTL 0x0855 |
|---|
| 4094 | #define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 4095 | #define regDC_PERFMON9_PERFCOUNTER_CNTL2 0x0856 |
|---|
| 4096 | #define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 4097 | #define regDC_PERFMON9_PERFCOUNTER_STATE 0x0857 |
|---|
| 4098 | #define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 4099 | #define regDC_PERFMON9_PERFMON_CNTL 0x0858 |
|---|
| 4100 | #define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 4101 | #define regDC_PERFMON9_PERFMON_CNTL2 0x0859 |
|---|
| 4102 | #define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 4103 | #define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x085a |
|---|
| 4104 | #define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 4105 | #define regDC_PERFMON9_PERFMON_CVALUE_LOW 0x085b |
|---|
| 4106 | #define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 4107 | #define regDC_PERFMON9_PERFMON_HI 0x085c |
|---|
| 4108 | #define regDC_PERFMON9_PERFMON_HI_BASE_IDX 2 |
|---|
| 4109 | #define regDC_PERFMON9_PERFMON_LOW 0x085d |
|---|
| 4110 | #define regDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 |
|---|
| 4111 | |
|---|
| 4112 | |
|---|
| 4113 | // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec |
|---|
| 4114 | // base address: 0xa50 |
|---|
| 4115 | #define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 |
|---|
| 4116 | #define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 |
|---|
| 4117 | #define regHUBP3_DCSURF_ADDR_CONFIG 0x087a |
|---|
| 4118 | #define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 |
|---|
| 4119 | #define regHUBP3_DCSURF_TILING_CONFIG 0x087b |
|---|
| 4120 | #define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 |
|---|
| 4121 | #define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d |
|---|
| 4122 | #define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 |
|---|
| 4123 | #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e |
|---|
| 4124 | #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 |
|---|
| 4125 | #define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f |
|---|
| 4126 | #define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 |
|---|
| 4127 | #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 |
|---|
| 4128 | #define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
|---|
| 4129 | #define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 |
|---|
| 4130 | #define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 |
|---|
| 4131 | #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 |
|---|
| 4132 | #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 |
|---|
| 4133 | #define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 |
|---|
| 4134 | #define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 |
|---|
| 4135 | #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 |
|---|
| 4136 | #define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 |
|---|
| 4137 | #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 |
|---|
| 4138 | #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 |
|---|
| 4139 | #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 |
|---|
| 4140 | #define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 |
|---|
| 4141 | #define regHUBP3_DCHUBP_CNTL 0x0887 |
|---|
| 4142 | #define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 |
|---|
| 4143 | #define regHUBP3_HUBP_CLK_CNTL 0x0888 |
|---|
| 4144 | #define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 |
|---|
| 4145 | #define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 |
|---|
| 4146 | #define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 |
|---|
| 4147 | #define regHUBP3_DCHUBP_MALL_CONFIG 0x088a |
|---|
| 4148 | #define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX 2 |
|---|
| 4149 | #define regHUBP3_DCHUBP_MALL_SUB_VP 0x088b |
|---|
| 4150 | #define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX 2 |
|---|
| 4151 | #define regHUBP3_HUBPREQ_DEBUG_DB 0x088c |
|---|
| 4152 | #define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 |
|---|
| 4153 | #define regHUBP3_HUBPREQ_DEBUG 0x088d |
|---|
| 4154 | #define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 |
|---|
| 4155 | #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0891 |
|---|
| 4156 | #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 |
|---|
| 4157 | #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0892 |
|---|
| 4158 | #define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 |
|---|
| 4159 | #define regHUBP3_HUBP_MALL_STATUS 0x0893 |
|---|
| 4160 | #define regHUBP3_HUBP_MALL_STATUS_BASE_IDX 2 |
|---|
| 4161 | |
|---|
| 4162 | |
|---|
| 4163 | // addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec |
|---|
| 4164 | // base address: 0xa50 |
|---|
| 4165 | #define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b |
|---|
| 4166 | #define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 |
|---|
| 4167 | #define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c |
|---|
| 4168 | #define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 |
|---|
| 4169 | #define regHUBPREQ3_VMID_SETTINGS_0 0x089d |
|---|
| 4170 | #define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 |
|---|
| 4171 | #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e |
|---|
| 4172 | #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 4173 | #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f |
|---|
| 4174 | #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 4175 | #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 |
|---|
| 4176 | #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 4177 | #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 |
|---|
| 4178 | #define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 4179 | #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 |
|---|
| 4180 | #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 4181 | #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 |
|---|
| 4182 | #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 4183 | #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 |
|---|
| 4184 | #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 4185 | #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 |
|---|
| 4186 | #define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 4187 | #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 |
|---|
| 4188 | #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 4189 | #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 |
|---|
| 4190 | #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 4191 | #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 |
|---|
| 4192 | #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 4193 | #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 |
|---|
| 4194 | #define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 4195 | #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa |
|---|
| 4196 | #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 4197 | #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab |
|---|
| 4198 | #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 4199 | #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac |
|---|
| 4200 | #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 |
|---|
| 4201 | #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad |
|---|
| 4202 | #define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 |
|---|
| 4203 | #define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae |
|---|
| 4204 | #define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 |
|---|
| 4205 | #define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af |
|---|
| 4206 | #define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 |
|---|
| 4207 | #define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 |
|---|
| 4208 | #define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 |
|---|
| 4209 | #define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b3 |
|---|
| 4210 | #define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 |
|---|
| 4211 | #define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b4 |
|---|
| 4212 | #define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 |
|---|
| 4213 | #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b5 |
|---|
| 4214 | #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 |
|---|
| 4215 | #define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b6 |
|---|
| 4216 | #define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 |
|---|
| 4217 | #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b7 |
|---|
| 4218 | #define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 |
|---|
| 4219 | #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b8 |
|---|
| 4220 | #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 |
|---|
| 4221 | #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08b9 |
|---|
| 4222 | #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 |
|---|
| 4223 | #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08ba |
|---|
| 4224 | #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 |
|---|
| 4225 | #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bb |
|---|
| 4226 | #define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 |
|---|
| 4227 | #define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bc |
|---|
| 4228 | #define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 |
|---|
| 4229 | #define regHUBPREQ3_DCN_TTU_QOS_WM 0x08bd |
|---|
| 4230 | #define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 |
|---|
| 4231 | #define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08be |
|---|
| 4232 | #define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 |
|---|
| 4233 | #define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08bf |
|---|
| 4234 | #define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 |
|---|
| 4235 | #define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c0 |
|---|
| 4236 | #define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 |
|---|
| 4237 | #define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c1 |
|---|
| 4238 | #define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 |
|---|
| 4239 | #define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c2 |
|---|
| 4240 | #define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 |
|---|
| 4241 | #define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c3 |
|---|
| 4242 | #define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 |
|---|
| 4243 | #define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c4 |
|---|
| 4244 | #define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 |
|---|
| 4245 | #define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c5 |
|---|
| 4246 | #define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 |
|---|
| 4247 | #define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c6 |
|---|
| 4248 | #define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 |
|---|
| 4249 | #define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c7 |
|---|
| 4250 | #define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 |
|---|
| 4251 | #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c8 |
|---|
| 4252 | #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 |
|---|
| 4253 | #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08c9 |
|---|
| 4254 | #define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 |
|---|
| 4255 | #define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d6 |
|---|
| 4256 | #define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 |
|---|
| 4257 | #define regHUBPREQ3_BLANK_OFFSET_0 0x08d7 |
|---|
| 4258 | #define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 |
|---|
| 4259 | #define regHUBPREQ3_BLANK_OFFSET_1 0x08d8 |
|---|
| 4260 | #define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 |
|---|
| 4261 | #define regHUBPREQ3_DST_DIMENSIONS 0x08d9 |
|---|
| 4262 | #define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 |
|---|
| 4263 | #define regHUBPREQ3_DST_AFTER_SCALER 0x08da |
|---|
| 4264 | #define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 |
|---|
| 4265 | #define regHUBPREQ3_PREFETCH_SETTINGS 0x08db |
|---|
| 4266 | #define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 |
|---|
| 4267 | #define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dc |
|---|
| 4268 | #define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 |
|---|
| 4269 | #define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08dd |
|---|
| 4270 | #define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 |
|---|
| 4271 | #define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08de |
|---|
| 4272 | #define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 |
|---|
| 4273 | #define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08df |
|---|
| 4274 | #define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 |
|---|
| 4275 | #define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e0 |
|---|
| 4276 | #define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 |
|---|
| 4277 | #define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e1 |
|---|
| 4278 | #define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 |
|---|
| 4279 | #define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e2 |
|---|
| 4280 | #define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 |
|---|
| 4281 | #define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e3 |
|---|
| 4282 | #define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 |
|---|
| 4283 | #define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e4 |
|---|
| 4284 | #define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 |
|---|
| 4285 | #define regHUBPREQ3_NOM_PARAMETERS_0 0x08e5 |
|---|
| 4286 | #define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 |
|---|
| 4287 | #define regHUBPREQ3_NOM_PARAMETERS_1 0x08e6 |
|---|
| 4288 | #define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 |
|---|
| 4289 | #define regHUBPREQ3_NOM_PARAMETERS_2 0x08e7 |
|---|
| 4290 | #define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 |
|---|
| 4291 | #define regHUBPREQ3_NOM_PARAMETERS_3 0x08e8 |
|---|
| 4292 | #define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 |
|---|
| 4293 | #define regHUBPREQ3_NOM_PARAMETERS_4 0x08e9 |
|---|
| 4294 | #define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 |
|---|
| 4295 | #define regHUBPREQ3_NOM_PARAMETERS_5 0x08ea |
|---|
| 4296 | #define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 |
|---|
| 4297 | #define regHUBPREQ3_NOM_PARAMETERS_6 0x08eb |
|---|
| 4298 | #define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 |
|---|
| 4299 | #define regHUBPREQ3_NOM_PARAMETERS_7 0x08ec |
|---|
| 4300 | #define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 |
|---|
| 4301 | #define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ed |
|---|
| 4302 | #define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 |
|---|
| 4303 | #define regHUBPREQ3_PER_LINE_DELIVERY 0x08ee |
|---|
| 4304 | #define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 |
|---|
| 4305 | #define regHUBPREQ3_CURSOR_SETTINGS 0x08ef |
|---|
| 4306 | #define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 |
|---|
| 4307 | #define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f0 |
|---|
| 4308 | #define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 |
|---|
| 4309 | #define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f1 |
|---|
| 4310 | #define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 |
|---|
| 4311 | #define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f2 |
|---|
| 4312 | #define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 4313 | #define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f3 |
|---|
| 4314 | #define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 4315 | #define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f6 |
|---|
| 4316 | #define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 |
|---|
| 4317 | #define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f7 |
|---|
| 4318 | #define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 |
|---|
| 4319 | #define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f8 |
|---|
| 4320 | #define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 |
|---|
| 4321 | #define regHUBPREQ3_FLIP_PARAMETERS_4 0x08f9 |
|---|
| 4322 | #define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 |
|---|
| 4323 | #define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fa |
|---|
| 4324 | #define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 |
|---|
| 4325 | #define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fb |
|---|
| 4326 | #define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 |
|---|
| 4327 | #define regHUBPREQ3_UCLK_PSTATE_FORCE 0x08fc |
|---|
| 4328 | #define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX 2 |
|---|
| 4329 | #define regHUBPREQ3_HUBPREQ_STATUS_REG0 0x08fd |
|---|
| 4330 | #define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX 2 |
|---|
| 4331 | #define regHUBPREQ3_HUBPREQ_STATUS_REG1 0x08fe |
|---|
| 4332 | #define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX 2 |
|---|
| 4333 | #define regHUBPREQ3_HUBPREQ_STATUS_REG2 0x08ff |
|---|
| 4334 | #define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX 2 |
|---|
| 4335 | |
|---|
| 4336 | |
|---|
| 4337 | // addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec |
|---|
| 4338 | // base address: 0xa50 |
|---|
| 4339 | #define regHUBPRET3_HUBPRET_CONTROL 0x0900 |
|---|
| 4340 | #define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 |
|---|
| 4341 | #define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 |
|---|
| 4342 | #define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 4343 | #define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 |
|---|
| 4344 | #define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 4345 | #define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 |
|---|
| 4346 | #define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 |
|---|
| 4347 | #define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 |
|---|
| 4348 | #define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 |
|---|
| 4349 | #define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 |
|---|
| 4350 | #define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 |
|---|
| 4351 | #define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 |
|---|
| 4352 | #define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 |
|---|
| 4353 | #define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 |
|---|
| 4354 | #define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 |
|---|
| 4355 | #define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 |
|---|
| 4356 | #define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 |
|---|
| 4357 | #define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 |
|---|
| 4358 | #define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 |
|---|
| 4359 | |
|---|
| 4360 | |
|---|
| 4361 | // addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec |
|---|
| 4362 | // base address: 0xa50 |
|---|
| 4363 | #define regCURSOR0_3_CURSOR_CONTROL 0x090c |
|---|
| 4364 | #define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 |
|---|
| 4365 | #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d |
|---|
| 4366 | #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 |
|---|
| 4367 | #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e |
|---|
| 4368 | #define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 4369 | #define regCURSOR0_3_CURSOR_SIZE 0x090f |
|---|
| 4370 | #define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 |
|---|
| 4371 | #define regCURSOR0_3_CURSOR_POSITION 0x0910 |
|---|
| 4372 | #define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 |
|---|
| 4373 | #define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 |
|---|
| 4374 | #define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 |
|---|
| 4375 | #define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 |
|---|
| 4376 | #define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 |
|---|
| 4377 | #define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 |
|---|
| 4378 | #define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 |
|---|
| 4379 | #define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 |
|---|
| 4380 | #define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 4381 | #define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 |
|---|
| 4382 | #define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 4383 | #define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 |
|---|
| 4384 | #define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 |
|---|
| 4385 | #define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 |
|---|
| 4386 | #define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 |
|---|
| 4387 | #define regCURSOR0_3_DMDATA_CNTL 0x0918 |
|---|
| 4388 | #define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 |
|---|
| 4389 | #define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 |
|---|
| 4390 | #define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 |
|---|
| 4391 | #define regCURSOR0_3_DMDATA_STATUS 0x091a |
|---|
| 4392 | #define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 |
|---|
| 4393 | #define regCURSOR0_3_DMDATA_SW_CNTL 0x091b |
|---|
| 4394 | #define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 |
|---|
| 4395 | #define regCURSOR0_3_DMDATA_SW_DATA 0x091c |
|---|
| 4396 | #define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 |
|---|
| 4397 | |
|---|
| 4398 | |
|---|
| 4399 | // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec |
|---|
| 4400 | // base address: 0x24c4 |
|---|
| 4401 | #define regDC_PERFMON10_PERFCOUNTER_CNTL 0x0931 |
|---|
| 4402 | #define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 4403 | #define regDC_PERFMON10_PERFCOUNTER_CNTL2 0x0932 |
|---|
| 4404 | #define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 4405 | #define regDC_PERFMON10_PERFCOUNTER_STATE 0x0933 |
|---|
| 4406 | #define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 4407 | #define regDC_PERFMON10_PERFMON_CNTL 0x0934 |
|---|
| 4408 | #define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 4409 | #define regDC_PERFMON10_PERFMON_CNTL2 0x0935 |
|---|
| 4410 | #define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 4411 | #define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0936 |
|---|
| 4412 | #define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 4413 | #define regDC_PERFMON10_PERFMON_CVALUE_LOW 0x0937 |
|---|
| 4414 | #define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 4415 | #define regDC_PERFMON10_PERFMON_HI 0x0938 |
|---|
| 4416 | #define regDC_PERFMON10_PERFMON_HI_BASE_IDX 2 |
|---|
| 4417 | #define regDC_PERFMON10_PERFMON_LOW 0x0939 |
|---|
| 4418 | #define regDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 |
|---|
| 4419 | |
|---|
| 4420 | |
|---|
| 4421 | // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec |
|---|
| 4422 | // base address: 0x0 |
|---|
| 4423 | #define regDPP_TOP0_DPP_CONTROL 0x0cc5 |
|---|
| 4424 | #define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 |
|---|
| 4425 | #define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 |
|---|
| 4426 | #define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 |
|---|
| 4427 | #define regDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7 |
|---|
| 4428 | #define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 |
|---|
| 4429 | #define regDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8 |
|---|
| 4430 | #define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 |
|---|
| 4431 | #define regDPP_TOP0_DPP_CRC_CTRL 0x0cc9 |
|---|
| 4432 | #define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 |
|---|
| 4433 | #define regDPP_TOP0_HOST_READ_CONTROL 0x0cca |
|---|
| 4434 | #define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 |
|---|
| 4435 | |
|---|
| 4436 | |
|---|
| 4437 | // addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec |
|---|
| 4438 | // base address: 0x0 |
|---|
| 4439 | #define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf |
|---|
| 4440 | #define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 |
|---|
| 4441 | #define regCNVC_CFG0_FORMAT_CONTROL 0x0cd0 |
|---|
| 4442 | #define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 |
|---|
| 4443 | #define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1 |
|---|
| 4444 | #define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 |
|---|
| 4445 | #define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2 |
|---|
| 4446 | #define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 |
|---|
| 4447 | #define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3 |
|---|
| 4448 | #define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 |
|---|
| 4449 | #define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4 |
|---|
| 4450 | #define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 |
|---|
| 4451 | #define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5 |
|---|
| 4452 | #define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 |
|---|
| 4453 | #define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6 |
|---|
| 4454 | #define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 |
|---|
| 4455 | #define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7 |
|---|
| 4456 | #define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 |
|---|
| 4457 | #define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8 |
|---|
| 4458 | #define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 |
|---|
| 4459 | #define regCNVC_CFG0_COLOR_KEYER_RED 0x0cd9 |
|---|
| 4460 | #define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 |
|---|
| 4461 | #define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda |
|---|
| 4462 | #define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 |
|---|
| 4463 | #define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb |
|---|
| 4464 | #define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 |
|---|
| 4465 | #define regCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd |
|---|
| 4466 | #define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2 |
|---|
| 4467 | #define regCNVC_CFG0_PRE_DEALPHA 0x0cde |
|---|
| 4468 | #define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 |
|---|
| 4469 | #define regCNVC_CFG0_PRE_CSC_MODE 0x0cdf |
|---|
| 4470 | #define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 |
|---|
| 4471 | #define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0 |
|---|
| 4472 | #define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 |
|---|
| 4473 | #define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1 |
|---|
| 4474 | #define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 |
|---|
| 4475 | #define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2 |
|---|
| 4476 | #define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 |
|---|
| 4477 | #define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3 |
|---|
| 4478 | #define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 |
|---|
| 4479 | #define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4 |
|---|
| 4480 | #define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 |
|---|
| 4481 | #define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5 |
|---|
| 4482 | #define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 |
|---|
| 4483 | #define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6 |
|---|
| 4484 | #define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 |
|---|
| 4485 | #define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7 |
|---|
| 4486 | #define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 |
|---|
| 4487 | #define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8 |
|---|
| 4488 | #define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 |
|---|
| 4489 | #define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9 |
|---|
| 4490 | #define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 |
|---|
| 4491 | #define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea |
|---|
| 4492 | #define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 |
|---|
| 4493 | #define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb |
|---|
| 4494 | #define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 |
|---|
| 4495 | #define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec |
|---|
| 4496 | #define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 |
|---|
| 4497 | #define regCNVC_CFG0_PRE_DEGAM 0x0ced |
|---|
| 4498 | #define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 |
|---|
| 4499 | #define regCNVC_CFG0_PRE_REALPHA 0x0cee |
|---|
| 4500 | #define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 |
|---|
| 4501 | |
|---|
| 4502 | |
|---|
| 4503 | // addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec |
|---|
| 4504 | // base address: 0x0 |
|---|
| 4505 | #define regCNVC_CUR0_CURSOR0_CONTROL 0x0cf1 |
|---|
| 4506 | #define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 |
|---|
| 4507 | #define regCNVC_CUR0_CURSOR0_COLOR0 0x0cf2 |
|---|
| 4508 | #define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 |
|---|
| 4509 | #define regCNVC_CUR0_CURSOR0_COLOR1 0x0cf3 |
|---|
| 4510 | #define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 |
|---|
| 4511 | #define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4 |
|---|
| 4512 | #define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 |
|---|
| 4513 | |
|---|
| 4514 | |
|---|
| 4515 | // addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec |
|---|
| 4516 | // base address: 0x0 |
|---|
| 4517 | #define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9 |
|---|
| 4518 | #define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 |
|---|
| 4519 | #define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa |
|---|
| 4520 | #define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 |
|---|
| 4521 | #define regDSCL0_SCL_MODE 0x0cfb |
|---|
| 4522 | #define regDSCL0_SCL_MODE_BASE_IDX 2 |
|---|
| 4523 | #define regDSCL0_SCL_TAP_CONTROL 0x0cfc |
|---|
| 4524 | #define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 |
|---|
| 4525 | #define regDSCL0_DSCL_CONTROL 0x0cfd |
|---|
| 4526 | #define regDSCL0_DSCL_CONTROL_BASE_IDX 2 |
|---|
| 4527 | #define regDSCL0_DSCL_2TAP_CONTROL 0x0cfe |
|---|
| 4528 | #define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 |
|---|
| 4529 | #define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff |
|---|
| 4530 | #define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 |
|---|
| 4531 | #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00 |
|---|
| 4532 | #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 |
|---|
| 4533 | #define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d01 |
|---|
| 4534 | #define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 |
|---|
| 4535 | #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02 |
|---|
| 4536 | #define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
|---|
| 4537 | #define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03 |
|---|
| 4538 | #define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 |
|---|
| 4539 | #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04 |
|---|
| 4540 | #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 |
|---|
| 4541 | #define regDSCL0_SCL_VERT_FILTER_INIT 0x0d05 |
|---|
| 4542 | #define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 |
|---|
| 4543 | #define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06 |
|---|
| 4544 | #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 |
|---|
| 4545 | #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07 |
|---|
| 4546 | #define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
|---|
| 4547 | #define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08 |
|---|
| 4548 | #define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 |
|---|
| 4549 | #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09 |
|---|
| 4550 | #define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 |
|---|
| 4551 | #define regDSCL0_SCL_BLACK_COLOR 0x0d0a |
|---|
| 4552 | #define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 |
|---|
| 4553 | #define regDSCL0_DSCL_UPDATE 0x0d0b |
|---|
| 4554 | #define regDSCL0_DSCL_UPDATE_BASE_IDX 2 |
|---|
| 4555 | #define regDSCL0_DSCL_AUTOCAL 0x0d0c |
|---|
| 4556 | #define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 |
|---|
| 4557 | #define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d |
|---|
| 4558 | #define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 |
|---|
| 4559 | #define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e |
|---|
| 4560 | #define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 |
|---|
| 4561 | #define regDSCL0_OTG_H_BLANK 0x0d0f |
|---|
| 4562 | #define regDSCL0_OTG_H_BLANK_BASE_IDX 2 |
|---|
| 4563 | #define regDSCL0_OTG_V_BLANK 0x0d10 |
|---|
| 4564 | #define regDSCL0_OTG_V_BLANK_BASE_IDX 2 |
|---|
| 4565 | #define regDSCL0_RECOUT_START 0x0d11 |
|---|
| 4566 | #define regDSCL0_RECOUT_START_BASE_IDX 2 |
|---|
| 4567 | #define regDSCL0_RECOUT_SIZE 0x0d12 |
|---|
| 4568 | #define regDSCL0_RECOUT_SIZE_BASE_IDX 2 |
|---|
| 4569 | #define regDSCL0_MPC_SIZE 0x0d13 |
|---|
| 4570 | #define regDSCL0_MPC_SIZE_BASE_IDX 2 |
|---|
| 4571 | #define regDSCL0_LB_DATA_FORMAT 0x0d14 |
|---|
| 4572 | #define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 |
|---|
| 4573 | #define regDSCL0_LB_MEMORY_CTRL 0x0d15 |
|---|
| 4574 | #define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 |
|---|
| 4575 | #define regDSCL0_LB_V_COUNTER 0x0d16 |
|---|
| 4576 | #define regDSCL0_LB_V_COUNTER_BASE_IDX 2 |
|---|
| 4577 | #define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d17 |
|---|
| 4578 | #define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 4579 | #define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d18 |
|---|
| 4580 | #define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 4581 | #define regDSCL0_OBUF_CONTROL 0x0d19 |
|---|
| 4582 | #define regDSCL0_OBUF_CONTROL_BASE_IDX 2 |
|---|
| 4583 | #define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a |
|---|
| 4584 | #define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 4585 | |
|---|
| 4586 | |
|---|
| 4587 | // addressBlock: dce_dc_dpp0_dispdec_cm_dispdec |
|---|
| 4588 | // base address: 0x0 |
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| 4589 | #define regCM0_CM_CONTROL 0x0d20 |
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| 4590 | #define regCM0_CM_CONTROL_BASE_IDX 2 |
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| 4591 | #define regCM0_CM_POST_CSC_CONTROL 0x0d21 |
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| 4592 | #define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 |
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| 4593 | #define regCM0_CM_POST_CSC_C11_C12 0x0d22 |
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| 4594 | #define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 |
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| 4595 | #define regCM0_CM_POST_CSC_C13_C14 0x0d23 |
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| 4596 | #define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 |
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| 4597 | #define regCM0_CM_POST_CSC_C21_C22 0x0d24 |
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| 4598 | #define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 |
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| 4599 | #define regCM0_CM_POST_CSC_C23_C24 0x0d25 |
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| 4600 | #define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 |
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| 4601 | #define regCM0_CM_POST_CSC_C31_C32 0x0d26 |
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| 4602 | #define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 |
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| 4603 | #define regCM0_CM_POST_CSC_C33_C34 0x0d27 |
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| 4604 | #define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 |
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| 4605 | #define regCM0_CM_POST_CSC_B_C11_C12 0x0d28 |
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| 4606 | #define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 |
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| 4607 | #define regCM0_CM_POST_CSC_B_C13_C14 0x0d29 |
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| 4608 | #define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 |
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| 4609 | #define regCM0_CM_POST_CSC_B_C21_C22 0x0d2a |
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| 4610 | #define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 |
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| 4611 | #define regCM0_CM_POST_CSC_B_C23_C24 0x0d2b |
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| 4612 | #define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 |
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| 4613 | #define regCM0_CM_POST_CSC_B_C31_C32 0x0d2c |
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| 4614 | #define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 |
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| 4615 | #define regCM0_CM_POST_CSC_B_C33_C34 0x0d2d |
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| 4616 | #define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 |
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| 4617 | #define regCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e |
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| 4618 | #define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 |
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| 4619 | #define regCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f |
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| 4620 | #define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 |
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| 4621 | #define regCM0_CM_GAMUT_REMAP_C13_C14 0x0d30 |
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| 4622 | #define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 |
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| 4623 | #define regCM0_CM_GAMUT_REMAP_C21_C22 0x0d31 |
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| 4624 | #define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 |
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| 4625 | #define regCM0_CM_GAMUT_REMAP_C23_C24 0x0d32 |
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| 4626 | #define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 |
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| 4627 | #define regCM0_CM_GAMUT_REMAP_C31_C32 0x0d33 |
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| 4628 | #define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 |
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| 4629 | #define regCM0_CM_GAMUT_REMAP_C33_C34 0x0d34 |
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| 4630 | #define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 |
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| 4631 | #define regCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35 |
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| 4632 | #define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 |
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| 4633 | #define regCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36 |
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| 4634 | #define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 |
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| 4635 | #define regCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37 |
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| 4636 | #define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 |
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| 4637 | #define regCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38 |
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| 4638 | #define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 |
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| 4639 | #define regCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39 |
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| 4640 | #define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 |
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| 4641 | #define regCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a |
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| 4642 | #define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 |
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| 4643 | #define regCM0_CM_BIAS_CR_R 0x0d3b |
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| 4644 | #define regCM0_CM_BIAS_CR_R_BASE_IDX 2 |
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| 4645 | #define regCM0_CM_BIAS_Y_G_CB_B 0x0d3c |
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| 4646 | #define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 |
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| 4647 | #define regCM0_CM_GAMCOR_CONTROL 0x0d3d |
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| 4648 | #define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 |
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| 4649 | #define regCM0_CM_GAMCOR_LUT_INDEX 0x0d3e |
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| 4650 | #define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 |
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| 4651 | #define regCM0_CM_GAMCOR_LUT_DATA 0x0d3f |
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| 4652 | #define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 |
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| 4653 | #define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d40 |
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| 4654 | #define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 |
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| 4655 | #define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41 |
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| 4656 | #define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 |
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| 4657 | #define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42 |
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| 4658 | #define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 |
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| 4659 | #define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43 |
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| 4660 | #define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 |
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| 4661 | #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44 |
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| 4662 | #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 |
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| 4663 | #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45 |
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| 4664 | #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 |
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| 4665 | #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46 |
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| 4666 | #define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 |
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| 4667 | #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47 |
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| 4668 | #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 |
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| 4669 | #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48 |
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| 4670 | #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 |
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| 4671 | #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49 |
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| 4672 | #define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 |
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| 4673 | #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a |
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| 4674 | #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 |
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| 4675 | #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b |
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| 4676 | #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 |
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| 4677 | #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c |
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| 4678 | #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 |
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| 4679 | #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d |
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| 4680 | #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 |
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| 4681 | #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e |
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| 4682 | #define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 |
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| 4683 | #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f |
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| 4684 | #define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 |
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| 4685 | #define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50 |
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| 4686 | #define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 |
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| 4687 | #define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51 |
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| 4688 | #define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 |
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| 4689 | #define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52 |
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| 4690 | #define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 |
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| 4691 | #define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53 |
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| 4692 | #define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 |
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| 4693 | #define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54 |
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| 4694 | #define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 |
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| 4695 | #define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55 |
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| 4696 | #define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 |
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| 4697 | #define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56 |
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| 4698 | #define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 |
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| 4699 | #define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57 |
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| 4700 | #define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 |
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| 4701 | #define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58 |
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| 4702 | #define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 |
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| 4703 | #define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59 |
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| 4704 | #define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 |
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| 4705 | #define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a |
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| 4706 | #define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 |
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| 4707 | #define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b |
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| 4708 | #define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 |
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| 4709 | #define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c |
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| 4710 | #define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 |
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| 4711 | #define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d |
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| 4712 | #define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 |
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| 4713 | #define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e |
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| 4714 | #define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 |
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| 4715 | #define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f |
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| 4716 | #define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 |
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| 4717 | #define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60 |
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| 4718 | #define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 |
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| 4719 | #define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61 |
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| 4720 | #define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 |
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| 4721 | #define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62 |
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| 4722 | #define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 |
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| 4723 | #define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63 |
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| 4724 | #define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 |
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| 4725 | #define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64 |
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| 4726 | #define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 |
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| 4727 | #define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65 |
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| 4728 | #define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 |
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| 4729 | #define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66 |
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| 4730 | #define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 |
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| 4731 | #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67 |
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| 4732 | #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 |
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| 4733 | #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68 |
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| 4734 | #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 |
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| 4735 | #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69 |
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| 4736 | #define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 |
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| 4737 | #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a |
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| 4738 | #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 |
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| 4739 | #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b |
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| 4740 | #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 |
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| 4741 | #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c |
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| 4742 | #define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 |
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| 4743 | #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d |
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| 4744 | #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 |
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| 4745 | #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e |
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| 4746 | #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 |
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| 4747 | #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f |
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| 4748 | #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 |
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| 4749 | #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70 |
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| 4750 | #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 |
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| 4751 | #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71 |
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| 4752 | #define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 |
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| 4753 | #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72 |
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| 4754 | #define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 |
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| 4755 | #define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73 |
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| 4756 | #define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 |
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| 4757 | #define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74 |
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| 4758 | #define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 |
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| 4759 | #define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75 |
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| 4760 | #define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 |
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| 4761 | #define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76 |
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| 4762 | #define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 |
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| 4763 | #define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77 |
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| 4764 | #define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 |
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| 4765 | #define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78 |
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| 4766 | #define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 |
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| 4767 | #define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79 |
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| 4768 | #define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 |
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| 4769 | #define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a |
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| 4770 | #define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 |
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| 4771 | #define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b |
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| 4772 | #define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 |
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| 4773 | #define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c |
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| 4774 | #define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 |
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| 4775 | #define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d |
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| 4776 | #define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 |
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| 4777 | #define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e |
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| 4778 | #define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 |
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| 4779 | #define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f |
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| 4780 | #define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 |
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| 4781 | #define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80 |
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| 4782 | #define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 |
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| 4783 | #define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81 |
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| 4784 | #define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 |
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| 4785 | #define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82 |
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| 4786 | #define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 |
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| 4787 | #define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83 |
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| 4788 | #define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 |
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| 4789 | #define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84 |
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| 4790 | #define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 |
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| 4791 | #define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85 |
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| 4792 | #define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 |
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| 4793 | #define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86 |
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| 4794 | #define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 |
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| 4795 | #define regCM0_CM_HDR_MULT_COEF 0x0d87 |
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| 4796 | #define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 |
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| 4797 | #define regCM0_CM_MEM_PWR_CTRL 0x0d88 |
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| 4798 | #define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 |
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| 4799 | #define regCM0_CM_MEM_PWR_STATUS 0x0d89 |
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| 4800 | #define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 |
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| 4801 | #define regCM0_CM_DEALPHA 0x0d8b |
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| 4802 | #define regCM0_CM_DEALPHA_BASE_IDX 2 |
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| 4803 | #define regCM0_CM_COEF_FORMAT 0x0d8c |
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| 4804 | #define regCM0_CM_COEF_FORMAT_BASE_IDX 2 |
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| 4805 | #define regCM0_CM_TEST_DEBUG_INDEX 0x0d8d |
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| 4806 | #define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 |
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| 4807 | #define regCM0_CM_TEST_DEBUG_DATA 0x0d8e |
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| 4808 | #define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 |
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| 4809 | |
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| 4810 | |
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| 4811 | // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec |
|---|
| 4812 | // base address: 0x3890 |
|---|
| 4813 | #define regDC_PERFMON11_PERFCOUNTER_CNTL 0x0e24 |
|---|
| 4814 | #define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 4815 | #define regDC_PERFMON11_PERFCOUNTER_CNTL2 0x0e25 |
|---|
| 4816 | #define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 4817 | #define regDC_PERFMON11_PERFCOUNTER_STATE 0x0e26 |
|---|
| 4818 | #define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 4819 | #define regDC_PERFMON11_PERFMON_CNTL 0x0e27 |
|---|
| 4820 | #define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 4821 | #define regDC_PERFMON11_PERFMON_CNTL2 0x0e28 |
|---|
| 4822 | #define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 4823 | #define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0e29 |
|---|
| 4824 | #define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 4825 | #define regDC_PERFMON11_PERFMON_CVALUE_LOW 0x0e2a |
|---|
| 4826 | #define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 4827 | #define regDC_PERFMON11_PERFMON_HI 0x0e2b |
|---|
| 4828 | #define regDC_PERFMON11_PERFMON_HI_BASE_IDX 2 |
|---|
| 4829 | #define regDC_PERFMON11_PERFMON_LOW 0x0e2c |
|---|
| 4830 | #define regDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 |
|---|
| 4831 | |
|---|
| 4832 | |
|---|
| 4833 | // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec |
|---|
| 4834 | // base address: 0x5ac |
|---|
| 4835 | #define regDPP_TOP1_DPP_CONTROL 0x0e30 |
|---|
| 4836 | #define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 |
|---|
| 4837 | #define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 |
|---|
| 4838 | #define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 |
|---|
| 4839 | #define regDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32 |
|---|
| 4840 | #define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 |
|---|
| 4841 | #define regDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33 |
|---|
| 4842 | #define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 |
|---|
| 4843 | #define regDPP_TOP1_DPP_CRC_CTRL 0x0e34 |
|---|
| 4844 | #define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 |
|---|
| 4845 | #define regDPP_TOP1_HOST_READ_CONTROL 0x0e35 |
|---|
| 4846 | #define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 |
|---|
| 4847 | |
|---|
| 4848 | |
|---|
| 4849 | // addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec |
|---|
| 4850 | // base address: 0x5ac |
|---|
| 4851 | #define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a |
|---|
| 4852 | #define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 |
|---|
| 4853 | #define regCNVC_CFG1_FORMAT_CONTROL 0x0e3b |
|---|
| 4854 | #define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 |
|---|
| 4855 | #define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c |
|---|
| 4856 | #define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 |
|---|
| 4857 | #define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d |
|---|
| 4858 | #define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 |
|---|
| 4859 | #define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e |
|---|
| 4860 | #define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 |
|---|
| 4861 | #define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f |
|---|
| 4862 | #define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 |
|---|
| 4863 | #define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40 |
|---|
| 4864 | #define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 |
|---|
| 4865 | #define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41 |
|---|
| 4866 | #define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 |
|---|
| 4867 | #define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42 |
|---|
| 4868 | #define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 |
|---|
| 4869 | #define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43 |
|---|
| 4870 | #define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 |
|---|
| 4871 | #define regCNVC_CFG1_COLOR_KEYER_RED 0x0e44 |
|---|
| 4872 | #define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 |
|---|
| 4873 | #define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45 |
|---|
| 4874 | #define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 |
|---|
| 4875 | #define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46 |
|---|
| 4876 | #define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 |
|---|
| 4877 | #define regCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48 |
|---|
| 4878 | #define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2 |
|---|
| 4879 | #define regCNVC_CFG1_PRE_DEALPHA 0x0e49 |
|---|
| 4880 | #define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 |
|---|
| 4881 | #define regCNVC_CFG1_PRE_CSC_MODE 0x0e4a |
|---|
| 4882 | #define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 |
|---|
| 4883 | #define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b |
|---|
| 4884 | #define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 |
|---|
| 4885 | #define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c |
|---|
| 4886 | #define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 |
|---|
| 4887 | #define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d |
|---|
| 4888 | #define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 |
|---|
| 4889 | #define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e |
|---|
| 4890 | #define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 |
|---|
| 4891 | #define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f |
|---|
| 4892 | #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 |
|---|
| 4893 | #define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e50 |
|---|
| 4894 | #define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 |
|---|
| 4895 | #define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51 |
|---|
| 4896 | #define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 |
|---|
| 4897 | #define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52 |
|---|
| 4898 | #define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 |
|---|
| 4899 | #define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53 |
|---|
| 4900 | #define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 |
|---|
| 4901 | #define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54 |
|---|
| 4902 | #define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 |
|---|
| 4903 | #define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55 |
|---|
| 4904 | #define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 |
|---|
| 4905 | #define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56 |
|---|
| 4906 | #define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 |
|---|
| 4907 | #define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57 |
|---|
| 4908 | #define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 |
|---|
| 4909 | #define regCNVC_CFG1_PRE_DEGAM 0x0e58 |
|---|
| 4910 | #define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 |
|---|
| 4911 | #define regCNVC_CFG1_PRE_REALPHA 0x0e59 |
|---|
| 4912 | #define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 |
|---|
| 4913 | |
|---|
| 4914 | |
|---|
| 4915 | // addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec |
|---|
| 4916 | // base address: 0x5ac |
|---|
| 4917 | #define regCNVC_CUR1_CURSOR0_CONTROL 0x0e5c |
|---|
| 4918 | #define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 |
|---|
| 4919 | #define regCNVC_CUR1_CURSOR0_COLOR0 0x0e5d |
|---|
| 4920 | #define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 |
|---|
| 4921 | #define regCNVC_CUR1_CURSOR0_COLOR1 0x0e5e |
|---|
| 4922 | #define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 |
|---|
| 4923 | #define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f |
|---|
| 4924 | #define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 |
|---|
| 4925 | |
|---|
| 4926 | |
|---|
| 4927 | // addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec |
|---|
| 4928 | // base address: 0x5ac |
|---|
| 4929 | #define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64 |
|---|
| 4930 | #define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 |
|---|
| 4931 | #define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65 |
|---|
| 4932 | #define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 |
|---|
| 4933 | #define regDSCL1_SCL_MODE 0x0e66 |
|---|
| 4934 | #define regDSCL1_SCL_MODE_BASE_IDX 2 |
|---|
| 4935 | #define regDSCL1_SCL_TAP_CONTROL 0x0e67 |
|---|
| 4936 | #define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 |
|---|
| 4937 | #define regDSCL1_DSCL_CONTROL 0x0e68 |
|---|
| 4938 | #define regDSCL1_DSCL_CONTROL_BASE_IDX 2 |
|---|
| 4939 | #define regDSCL1_DSCL_2TAP_CONTROL 0x0e69 |
|---|
| 4940 | #define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 |
|---|
| 4941 | #define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a |
|---|
| 4942 | #define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 |
|---|
| 4943 | #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b |
|---|
| 4944 | #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 |
|---|
| 4945 | #define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c |
|---|
| 4946 | #define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 |
|---|
| 4947 | #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d |
|---|
| 4948 | #define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
|---|
| 4949 | #define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e |
|---|
| 4950 | #define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 |
|---|
| 4951 | #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f |
|---|
| 4952 | #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 |
|---|
| 4953 | #define regDSCL1_SCL_VERT_FILTER_INIT 0x0e70 |
|---|
| 4954 | #define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 |
|---|
| 4955 | #define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71 |
|---|
| 4956 | #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 |
|---|
| 4957 | #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72 |
|---|
| 4958 | #define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
|---|
| 4959 | #define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73 |
|---|
| 4960 | #define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 |
|---|
| 4961 | #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74 |
|---|
| 4962 | #define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 |
|---|
| 4963 | #define regDSCL1_SCL_BLACK_COLOR 0x0e75 |
|---|
| 4964 | #define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 |
|---|
| 4965 | #define regDSCL1_DSCL_UPDATE 0x0e76 |
|---|
| 4966 | #define regDSCL1_DSCL_UPDATE_BASE_IDX 2 |
|---|
| 4967 | #define regDSCL1_DSCL_AUTOCAL 0x0e77 |
|---|
| 4968 | #define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 |
|---|
| 4969 | #define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78 |
|---|
| 4970 | #define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 |
|---|
| 4971 | #define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79 |
|---|
| 4972 | #define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 |
|---|
| 4973 | #define regDSCL1_OTG_H_BLANK 0x0e7a |
|---|
| 4974 | #define regDSCL1_OTG_H_BLANK_BASE_IDX 2 |
|---|
| 4975 | #define regDSCL1_OTG_V_BLANK 0x0e7b |
|---|
| 4976 | #define regDSCL1_OTG_V_BLANK_BASE_IDX 2 |
|---|
| 4977 | #define regDSCL1_RECOUT_START 0x0e7c |
|---|
| 4978 | #define regDSCL1_RECOUT_START_BASE_IDX 2 |
|---|
| 4979 | #define regDSCL1_RECOUT_SIZE 0x0e7d |
|---|
| 4980 | #define regDSCL1_RECOUT_SIZE_BASE_IDX 2 |
|---|
| 4981 | #define regDSCL1_MPC_SIZE 0x0e7e |
|---|
| 4982 | #define regDSCL1_MPC_SIZE_BASE_IDX 2 |
|---|
| 4983 | #define regDSCL1_LB_DATA_FORMAT 0x0e7f |
|---|
| 4984 | #define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 |
|---|
| 4985 | #define regDSCL1_LB_MEMORY_CTRL 0x0e80 |
|---|
| 4986 | #define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 |
|---|
| 4987 | #define regDSCL1_LB_V_COUNTER 0x0e81 |
|---|
| 4988 | #define regDSCL1_LB_V_COUNTER_BASE_IDX 2 |
|---|
| 4989 | #define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e82 |
|---|
| 4990 | #define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 4991 | #define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e83 |
|---|
| 4992 | #define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 4993 | #define regDSCL1_OBUF_CONTROL 0x0e84 |
|---|
| 4994 | #define regDSCL1_OBUF_CONTROL_BASE_IDX 2 |
|---|
| 4995 | #define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e85 |
|---|
| 4996 | #define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 4997 | |
|---|
| 4998 | |
|---|
| 4999 | // addressBlock: dce_dc_dpp1_dispdec_cm_dispdec |
|---|
| 5000 | // base address: 0x5ac |
|---|
| 5001 | #define regCM1_CM_CONTROL 0x0e8b |
|---|
| 5002 | #define regCM1_CM_CONTROL_BASE_IDX 2 |
|---|
| 5003 | #define regCM1_CM_POST_CSC_CONTROL 0x0e8c |
|---|
| 5004 | #define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 |
|---|
| 5005 | #define regCM1_CM_POST_CSC_C11_C12 0x0e8d |
|---|
| 5006 | #define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 |
|---|
| 5007 | #define regCM1_CM_POST_CSC_C13_C14 0x0e8e |
|---|
| 5008 | #define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 |
|---|
| 5009 | #define regCM1_CM_POST_CSC_C21_C22 0x0e8f |
|---|
| 5010 | #define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 |
|---|
| 5011 | #define regCM1_CM_POST_CSC_C23_C24 0x0e90 |
|---|
| 5012 | #define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 |
|---|
| 5013 | #define regCM1_CM_POST_CSC_C31_C32 0x0e91 |
|---|
| 5014 | #define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 |
|---|
| 5015 | #define regCM1_CM_POST_CSC_C33_C34 0x0e92 |
|---|
| 5016 | #define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 |
|---|
| 5017 | #define regCM1_CM_POST_CSC_B_C11_C12 0x0e93 |
|---|
| 5018 | #define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 |
|---|
| 5019 | #define regCM1_CM_POST_CSC_B_C13_C14 0x0e94 |
|---|
| 5020 | #define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 |
|---|
| 5021 | #define regCM1_CM_POST_CSC_B_C21_C22 0x0e95 |
|---|
| 5022 | #define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 |
|---|
| 5023 | #define regCM1_CM_POST_CSC_B_C23_C24 0x0e96 |
|---|
| 5024 | #define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 |
|---|
| 5025 | #define regCM1_CM_POST_CSC_B_C31_C32 0x0e97 |
|---|
| 5026 | #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 |
|---|
| 5027 | #define regCM1_CM_POST_CSC_B_C33_C34 0x0e98 |
|---|
| 5028 | #define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 |
|---|
| 5029 | #define regCM1_CM_GAMUT_REMAP_CONTROL 0x0e99 |
|---|
| 5030 | #define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 |
|---|
| 5031 | #define regCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a |
|---|
| 5032 | #define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 |
|---|
| 5033 | #define regCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b |
|---|
| 5034 | #define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 |
|---|
| 5035 | #define regCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c |
|---|
| 5036 | #define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 |
|---|
| 5037 | #define regCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d |
|---|
| 5038 | #define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 |
|---|
| 5039 | #define regCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e |
|---|
| 5040 | #define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 |
|---|
| 5041 | #define regCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f |
|---|
| 5042 | #define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 |
|---|
| 5043 | #define regCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0 |
|---|
| 5044 | #define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 |
|---|
| 5045 | #define regCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1 |
|---|
| 5046 | #define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 |
|---|
| 5047 | #define regCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2 |
|---|
| 5048 | #define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 |
|---|
| 5049 | #define regCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3 |
|---|
| 5050 | #define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 |
|---|
| 5051 | #define regCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4 |
|---|
| 5052 | #define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 |
|---|
| 5053 | #define regCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5 |
|---|
| 5054 | #define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 |
|---|
| 5055 | #define regCM1_CM_BIAS_CR_R 0x0ea6 |
|---|
| 5056 | #define regCM1_CM_BIAS_CR_R_BASE_IDX 2 |
|---|
| 5057 | #define regCM1_CM_BIAS_Y_G_CB_B 0x0ea7 |
|---|
| 5058 | #define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 |
|---|
| 5059 | #define regCM1_CM_GAMCOR_CONTROL 0x0ea8 |
|---|
| 5060 | #define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 |
|---|
| 5061 | #define regCM1_CM_GAMCOR_LUT_INDEX 0x0ea9 |
|---|
| 5062 | #define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 |
|---|
| 5063 | #define regCM1_CM_GAMCOR_LUT_DATA 0x0eaa |
|---|
| 5064 | #define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 |
|---|
| 5065 | #define regCM1_CM_GAMCOR_LUT_CONTROL 0x0eab |
|---|
| 5066 | #define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 |
|---|
| 5067 | #define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac |
|---|
| 5068 | #define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 |
|---|
| 5069 | #define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead |
|---|
| 5070 | #define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 |
|---|
| 5071 | #define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae |
|---|
| 5072 | #define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 |
|---|
| 5073 | #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf |
|---|
| 5074 | #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 |
|---|
| 5075 | #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0 |
|---|
| 5076 | #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 |
|---|
| 5077 | #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1 |
|---|
| 5078 | #define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 |
|---|
| 5079 | #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2 |
|---|
| 5080 | #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 |
|---|
| 5081 | #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3 |
|---|
| 5082 | #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 |
|---|
| 5083 | #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4 |
|---|
| 5084 | #define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 |
|---|
| 5085 | #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5 |
|---|
| 5086 | #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 |
|---|
| 5087 | #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6 |
|---|
| 5088 | #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 |
|---|
| 5089 | #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7 |
|---|
| 5090 | #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 |
|---|
| 5091 | #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8 |
|---|
| 5092 | #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 |
|---|
| 5093 | #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9 |
|---|
| 5094 | #define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 |
|---|
| 5095 | #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba |
|---|
| 5096 | #define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 |
|---|
| 5097 | #define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb |
|---|
| 5098 | #define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 |
|---|
| 5099 | #define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc |
|---|
| 5100 | #define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 |
|---|
| 5101 | #define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd |
|---|
| 5102 | #define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 |
|---|
| 5103 | #define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe |
|---|
| 5104 | #define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 |
|---|
| 5105 | #define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf |
|---|
| 5106 | #define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 |
|---|
| 5107 | #define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0 |
|---|
| 5108 | #define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 |
|---|
| 5109 | #define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1 |
|---|
| 5110 | #define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 |
|---|
| 5111 | #define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2 |
|---|
| 5112 | #define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 |
|---|
| 5113 | #define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3 |
|---|
| 5114 | #define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 |
|---|
| 5115 | #define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4 |
|---|
| 5116 | #define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 |
|---|
| 5117 | #define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5 |
|---|
| 5118 | #define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 |
|---|
| 5119 | #define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6 |
|---|
| 5120 | #define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 |
|---|
| 5121 | #define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7 |
|---|
| 5122 | #define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 |
|---|
| 5123 | #define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8 |
|---|
| 5124 | #define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 |
|---|
| 5125 | #define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9 |
|---|
| 5126 | #define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 |
|---|
| 5127 | #define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca |
|---|
| 5128 | #define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 |
|---|
| 5129 | #define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb |
|---|
| 5130 | #define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 |
|---|
| 5131 | #define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc |
|---|
| 5132 | #define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 |
|---|
| 5133 | #define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd |
|---|
| 5134 | #define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 |
|---|
| 5135 | #define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece |
|---|
| 5136 | #define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 |
|---|
| 5137 | #define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf |
|---|
| 5138 | #define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 |
|---|
| 5139 | #define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0 |
|---|
| 5140 | #define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 |
|---|
| 5141 | #define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1 |
|---|
| 5142 | #define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 |
|---|
| 5143 | #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2 |
|---|
| 5144 | #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 |
|---|
| 5145 | #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3 |
|---|
| 5146 | #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 |
|---|
| 5147 | #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4 |
|---|
| 5148 | #define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 |
|---|
| 5149 | #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5 |
|---|
| 5150 | #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 |
|---|
| 5151 | #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6 |
|---|
| 5152 | #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 |
|---|
| 5153 | #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7 |
|---|
| 5154 | #define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 |
|---|
| 5155 | #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8 |
|---|
| 5156 | #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 |
|---|
| 5157 | #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9 |
|---|
| 5158 | #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 |
|---|
| 5159 | #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda |
|---|
| 5160 | #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 |
|---|
| 5161 | #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb |
|---|
| 5162 | #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 |
|---|
| 5163 | #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc |
|---|
| 5164 | #define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 |
|---|
| 5165 | #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd |
|---|
| 5166 | #define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 |
|---|
| 5167 | #define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede |
|---|
| 5168 | #define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 |
|---|
| 5169 | #define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf |
|---|
| 5170 | #define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 |
|---|
| 5171 | #define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0 |
|---|
| 5172 | #define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 |
|---|
| 5173 | #define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1 |
|---|
| 5174 | #define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 |
|---|
| 5175 | #define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2 |
|---|
| 5176 | #define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 |
|---|
| 5177 | #define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3 |
|---|
| 5178 | #define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 |
|---|
| 5179 | #define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4 |
|---|
| 5180 | #define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 |
|---|
| 5181 | #define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5 |
|---|
| 5182 | #define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 |
|---|
| 5183 | #define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6 |
|---|
| 5184 | #define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 |
|---|
| 5185 | #define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7 |
|---|
| 5186 | #define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 |
|---|
| 5187 | #define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8 |
|---|
| 5188 | #define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 |
|---|
| 5189 | #define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9 |
|---|
| 5190 | #define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 |
|---|
| 5191 | #define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea |
|---|
| 5192 | #define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 |
|---|
| 5193 | #define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb |
|---|
| 5194 | #define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 |
|---|
| 5195 | #define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec |
|---|
| 5196 | #define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 |
|---|
| 5197 | #define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed |
|---|
| 5198 | #define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 |
|---|
| 5199 | #define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee |
|---|
| 5200 | #define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 |
|---|
| 5201 | #define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef |
|---|
| 5202 | #define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 |
|---|
| 5203 | #define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0 |
|---|
| 5204 | #define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 |
|---|
| 5205 | #define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1 |
|---|
| 5206 | #define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 |
|---|
| 5207 | #define regCM1_CM_HDR_MULT_COEF 0x0ef2 |
|---|
| 5208 | #define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 |
|---|
| 5209 | #define regCM1_CM_MEM_PWR_CTRL 0x0ef3 |
|---|
| 5210 | #define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 5211 | #define regCM1_CM_MEM_PWR_STATUS 0x0ef4 |
|---|
| 5212 | #define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 5213 | #define regCM1_CM_DEALPHA 0x0ef6 |
|---|
| 5214 | #define regCM1_CM_DEALPHA_BASE_IDX 2 |
|---|
| 5215 | #define regCM1_CM_COEF_FORMAT 0x0ef7 |
|---|
| 5216 | #define regCM1_CM_COEF_FORMAT_BASE_IDX 2 |
|---|
| 5217 | #define regCM1_CM_TEST_DEBUG_INDEX 0x0ef8 |
|---|
| 5218 | #define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 |
|---|
| 5219 | #define regCM1_CM_TEST_DEBUG_DATA 0x0ef9 |
|---|
| 5220 | #define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 |
|---|
| 5221 | |
|---|
| 5222 | |
|---|
| 5223 | // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec |
|---|
| 5224 | // base address: 0x3e3c |
|---|
| 5225 | #define regDC_PERFMON12_PERFCOUNTER_CNTL 0x0f8f |
|---|
| 5226 | #define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 5227 | #define regDC_PERFMON12_PERFCOUNTER_CNTL2 0x0f90 |
|---|
| 5228 | #define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 5229 | #define regDC_PERFMON12_PERFCOUNTER_STATE 0x0f91 |
|---|
| 5230 | #define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 5231 | #define regDC_PERFMON12_PERFMON_CNTL 0x0f92 |
|---|
| 5232 | #define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 5233 | #define regDC_PERFMON12_PERFMON_CNTL2 0x0f93 |
|---|
| 5234 | #define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 5235 | #define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0f94 |
|---|
| 5236 | #define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 5237 | #define regDC_PERFMON12_PERFMON_CVALUE_LOW 0x0f95 |
|---|
| 5238 | #define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 5239 | #define regDC_PERFMON12_PERFMON_HI 0x0f96 |
|---|
| 5240 | #define regDC_PERFMON12_PERFMON_HI_BASE_IDX 2 |
|---|
| 5241 | #define regDC_PERFMON12_PERFMON_LOW 0x0f97 |
|---|
| 5242 | #define regDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 |
|---|
| 5243 | |
|---|
| 5244 | |
|---|
| 5245 | // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec |
|---|
| 5246 | // base address: 0xb58 |
|---|
| 5247 | #define regDPP_TOP2_DPP_CONTROL 0x0f9b |
|---|
| 5248 | #define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 |
|---|
| 5249 | #define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c |
|---|
| 5250 | #define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 |
|---|
| 5251 | #define regDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d |
|---|
| 5252 | #define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 |
|---|
| 5253 | #define regDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e |
|---|
| 5254 | #define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 |
|---|
| 5255 | #define regDPP_TOP2_DPP_CRC_CTRL 0x0f9f |
|---|
| 5256 | #define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 |
|---|
| 5257 | #define regDPP_TOP2_HOST_READ_CONTROL 0x0fa0 |
|---|
| 5258 | #define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 |
|---|
| 5259 | |
|---|
| 5260 | |
|---|
| 5261 | // addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec |
|---|
| 5262 | // base address: 0xb58 |
|---|
| 5263 | #define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5 |
|---|
| 5264 | #define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 |
|---|
| 5265 | #define regCNVC_CFG2_FORMAT_CONTROL 0x0fa6 |
|---|
| 5266 | #define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 |
|---|
| 5267 | #define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7 |
|---|
| 5268 | #define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 |
|---|
| 5269 | #define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8 |
|---|
| 5270 | #define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 |
|---|
| 5271 | #define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9 |
|---|
| 5272 | #define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 |
|---|
| 5273 | #define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa |
|---|
| 5274 | #define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 |
|---|
| 5275 | #define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab |
|---|
| 5276 | #define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 |
|---|
| 5277 | #define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac |
|---|
| 5278 | #define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 |
|---|
| 5279 | #define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad |
|---|
| 5280 | #define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 |
|---|
| 5281 | #define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae |
|---|
| 5282 | #define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 |
|---|
| 5283 | #define regCNVC_CFG2_COLOR_KEYER_RED 0x0faf |
|---|
| 5284 | #define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 |
|---|
| 5285 | #define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0 |
|---|
| 5286 | #define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 |
|---|
| 5287 | #define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1 |
|---|
| 5288 | #define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 |
|---|
| 5289 | #define regCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3 |
|---|
| 5290 | #define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2 |
|---|
| 5291 | #define regCNVC_CFG2_PRE_DEALPHA 0x0fb4 |
|---|
| 5292 | #define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 |
|---|
| 5293 | #define regCNVC_CFG2_PRE_CSC_MODE 0x0fb5 |
|---|
| 5294 | #define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 |
|---|
| 5295 | #define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6 |
|---|
| 5296 | #define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 |
|---|
| 5297 | #define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7 |
|---|
| 5298 | #define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 |
|---|
| 5299 | #define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8 |
|---|
| 5300 | #define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 |
|---|
| 5301 | #define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9 |
|---|
| 5302 | #define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 |
|---|
| 5303 | #define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fba |
|---|
| 5304 | #define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 |
|---|
| 5305 | #define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb |
|---|
| 5306 | #define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 |
|---|
| 5307 | #define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc |
|---|
| 5308 | #define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 |
|---|
| 5309 | #define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd |
|---|
| 5310 | #define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 |
|---|
| 5311 | #define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe |
|---|
| 5312 | #define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 |
|---|
| 5313 | #define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf |
|---|
| 5314 | #define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 |
|---|
| 5315 | #define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0 |
|---|
| 5316 | #define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 |
|---|
| 5317 | #define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1 |
|---|
| 5318 | #define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 |
|---|
| 5319 | #define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2 |
|---|
| 5320 | #define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 |
|---|
| 5321 | #define regCNVC_CFG2_PRE_DEGAM 0x0fc3 |
|---|
| 5322 | #define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 |
|---|
| 5323 | #define regCNVC_CFG2_PRE_REALPHA 0x0fc4 |
|---|
| 5324 | #define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 |
|---|
| 5325 | |
|---|
| 5326 | |
|---|
| 5327 | // addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec |
|---|
| 5328 | // base address: 0xb58 |
|---|
| 5329 | #define regCNVC_CUR2_CURSOR0_CONTROL 0x0fc7 |
|---|
| 5330 | #define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 |
|---|
| 5331 | #define regCNVC_CUR2_CURSOR0_COLOR0 0x0fc8 |
|---|
| 5332 | #define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 |
|---|
| 5333 | #define regCNVC_CUR2_CURSOR0_COLOR1 0x0fc9 |
|---|
| 5334 | #define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 |
|---|
| 5335 | #define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca |
|---|
| 5336 | #define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 |
|---|
| 5337 | |
|---|
| 5338 | |
|---|
| 5339 | // addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec |
|---|
| 5340 | // base address: 0xb58 |
|---|
| 5341 | #define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf |
|---|
| 5342 | #define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 |
|---|
| 5343 | #define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0 |
|---|
| 5344 | #define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 |
|---|
| 5345 | #define regDSCL2_SCL_MODE 0x0fd1 |
|---|
| 5346 | #define regDSCL2_SCL_MODE_BASE_IDX 2 |
|---|
| 5347 | #define regDSCL2_SCL_TAP_CONTROL 0x0fd2 |
|---|
| 5348 | #define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 |
|---|
| 5349 | #define regDSCL2_DSCL_CONTROL 0x0fd3 |
|---|
| 5350 | #define regDSCL2_DSCL_CONTROL_BASE_IDX 2 |
|---|
| 5351 | #define regDSCL2_DSCL_2TAP_CONTROL 0x0fd4 |
|---|
| 5352 | #define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 |
|---|
| 5353 | #define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5 |
|---|
| 5354 | #define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 |
|---|
| 5355 | #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6 |
|---|
| 5356 | #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 |
|---|
| 5357 | #define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7 |
|---|
| 5358 | #define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 |
|---|
| 5359 | #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8 |
|---|
| 5360 | #define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
|---|
| 5361 | #define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9 |
|---|
| 5362 | #define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 |
|---|
| 5363 | #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda |
|---|
| 5364 | #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 |
|---|
| 5365 | #define regDSCL2_SCL_VERT_FILTER_INIT 0x0fdb |
|---|
| 5366 | #define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 |
|---|
| 5367 | #define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc |
|---|
| 5368 | #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 |
|---|
| 5369 | #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd |
|---|
| 5370 | #define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
|---|
| 5371 | #define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde |
|---|
| 5372 | #define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 |
|---|
| 5373 | #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf |
|---|
| 5374 | #define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 |
|---|
| 5375 | #define regDSCL2_SCL_BLACK_COLOR 0x0fe0 |
|---|
| 5376 | #define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 |
|---|
| 5377 | #define regDSCL2_DSCL_UPDATE 0x0fe1 |
|---|
| 5378 | #define regDSCL2_DSCL_UPDATE_BASE_IDX 2 |
|---|
| 5379 | #define regDSCL2_DSCL_AUTOCAL 0x0fe2 |
|---|
| 5380 | #define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 |
|---|
| 5381 | #define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3 |
|---|
| 5382 | #define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 |
|---|
| 5383 | #define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4 |
|---|
| 5384 | #define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 |
|---|
| 5385 | #define regDSCL2_OTG_H_BLANK 0x0fe5 |
|---|
| 5386 | #define regDSCL2_OTG_H_BLANK_BASE_IDX 2 |
|---|
| 5387 | #define regDSCL2_OTG_V_BLANK 0x0fe6 |
|---|
| 5388 | #define regDSCL2_OTG_V_BLANK_BASE_IDX 2 |
|---|
| 5389 | #define regDSCL2_RECOUT_START 0x0fe7 |
|---|
| 5390 | #define regDSCL2_RECOUT_START_BASE_IDX 2 |
|---|
| 5391 | #define regDSCL2_RECOUT_SIZE 0x0fe8 |
|---|
| 5392 | #define regDSCL2_RECOUT_SIZE_BASE_IDX 2 |
|---|
| 5393 | #define regDSCL2_MPC_SIZE 0x0fe9 |
|---|
| 5394 | #define regDSCL2_MPC_SIZE_BASE_IDX 2 |
|---|
| 5395 | #define regDSCL2_LB_DATA_FORMAT 0x0fea |
|---|
| 5396 | #define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 |
|---|
| 5397 | #define regDSCL2_LB_MEMORY_CTRL 0x0feb |
|---|
| 5398 | #define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 |
|---|
| 5399 | #define regDSCL2_LB_V_COUNTER 0x0fec |
|---|
| 5400 | #define regDSCL2_LB_V_COUNTER_BASE_IDX 2 |
|---|
| 5401 | #define regDSCL2_DSCL_MEM_PWR_CTRL 0x0fed |
|---|
| 5402 | #define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 5403 | #define regDSCL2_DSCL_MEM_PWR_STATUS 0x0fee |
|---|
| 5404 | #define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 5405 | #define regDSCL2_OBUF_CONTROL 0x0fef |
|---|
| 5406 | #define regDSCL2_OBUF_CONTROL_BASE_IDX 2 |
|---|
| 5407 | #define regDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0 |
|---|
| 5408 | #define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 5409 | |
|---|
| 5410 | |
|---|
| 5411 | // addressBlock: dce_dc_dpp2_dispdec_cm_dispdec |
|---|
| 5412 | // base address: 0xb58 |
|---|
| 5413 | #define regCM2_CM_CONTROL 0x0ff6 |
|---|
| 5414 | #define regCM2_CM_CONTROL_BASE_IDX 2 |
|---|
| 5415 | #define regCM2_CM_POST_CSC_CONTROL 0x0ff7 |
|---|
| 5416 | #define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 |
|---|
| 5417 | #define regCM2_CM_POST_CSC_C11_C12 0x0ff8 |
|---|
| 5418 | #define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 |
|---|
| 5419 | #define regCM2_CM_POST_CSC_C13_C14 0x0ff9 |
|---|
| 5420 | #define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 |
|---|
| 5421 | #define regCM2_CM_POST_CSC_C21_C22 0x0ffa |
|---|
| 5422 | #define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 |
|---|
| 5423 | #define regCM2_CM_POST_CSC_C23_C24 0x0ffb |
|---|
| 5424 | #define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 |
|---|
| 5425 | #define regCM2_CM_POST_CSC_C31_C32 0x0ffc |
|---|
| 5426 | #define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 |
|---|
| 5427 | #define regCM2_CM_POST_CSC_C33_C34 0x0ffd |
|---|
| 5428 | #define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 |
|---|
| 5429 | #define regCM2_CM_POST_CSC_B_C11_C12 0x0ffe |
|---|
| 5430 | #define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 |
|---|
| 5431 | #define regCM2_CM_POST_CSC_B_C13_C14 0x0fff |
|---|
| 5432 | #define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 |
|---|
| 5433 | #define regCM2_CM_POST_CSC_B_C21_C22 0x1000 |
|---|
| 5434 | #define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 |
|---|
| 5435 | #define regCM2_CM_POST_CSC_B_C23_C24 0x1001 |
|---|
| 5436 | #define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 |
|---|
| 5437 | #define regCM2_CM_POST_CSC_B_C31_C32 0x1002 |
|---|
| 5438 | #define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 |
|---|
| 5439 | #define regCM2_CM_POST_CSC_B_C33_C34 0x1003 |
|---|
| 5440 | #define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 |
|---|
| 5441 | #define regCM2_CM_GAMUT_REMAP_CONTROL 0x1004 |
|---|
| 5442 | #define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 |
|---|
| 5443 | #define regCM2_CM_GAMUT_REMAP_C11_C12 0x1005 |
|---|
| 5444 | #define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 |
|---|
| 5445 | #define regCM2_CM_GAMUT_REMAP_C13_C14 0x1006 |
|---|
| 5446 | #define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 |
|---|
| 5447 | #define regCM2_CM_GAMUT_REMAP_C21_C22 0x1007 |
|---|
| 5448 | #define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 |
|---|
| 5449 | #define regCM2_CM_GAMUT_REMAP_C23_C24 0x1008 |
|---|
| 5450 | #define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 |
|---|
| 5451 | #define regCM2_CM_GAMUT_REMAP_C31_C32 0x1009 |
|---|
| 5452 | #define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 |
|---|
| 5453 | #define regCM2_CM_GAMUT_REMAP_C33_C34 0x100a |
|---|
| 5454 | #define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 |
|---|
| 5455 | #define regCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b |
|---|
| 5456 | #define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 |
|---|
| 5457 | #define regCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c |
|---|
| 5458 | #define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 |
|---|
| 5459 | #define regCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d |
|---|
| 5460 | #define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 |
|---|
| 5461 | #define regCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e |
|---|
| 5462 | #define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 |
|---|
| 5463 | #define regCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f |
|---|
| 5464 | #define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 |
|---|
| 5465 | #define regCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010 |
|---|
| 5466 | #define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 |
|---|
| 5467 | #define regCM2_CM_BIAS_CR_R 0x1011 |
|---|
| 5468 | #define regCM2_CM_BIAS_CR_R_BASE_IDX 2 |
|---|
| 5469 | #define regCM2_CM_BIAS_Y_G_CB_B 0x1012 |
|---|
| 5470 | #define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 |
|---|
| 5471 | #define regCM2_CM_GAMCOR_CONTROL 0x1013 |
|---|
| 5472 | #define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 |
|---|
| 5473 | #define regCM2_CM_GAMCOR_LUT_INDEX 0x1014 |
|---|
| 5474 | #define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 |
|---|
| 5475 | #define regCM2_CM_GAMCOR_LUT_DATA 0x1015 |
|---|
| 5476 | #define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 |
|---|
| 5477 | #define regCM2_CM_GAMCOR_LUT_CONTROL 0x1016 |
|---|
| 5478 | #define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 |
|---|
| 5479 | #define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017 |
|---|
| 5480 | #define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 |
|---|
| 5481 | #define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018 |
|---|
| 5482 | #define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 |
|---|
| 5483 | #define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019 |
|---|
| 5484 | #define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 |
|---|
| 5485 | #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a |
|---|
| 5486 | #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 |
|---|
| 5487 | #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b |
|---|
| 5488 | #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 |
|---|
| 5489 | #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c |
|---|
| 5490 | #define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 |
|---|
| 5491 | #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d |
|---|
| 5492 | #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 |
|---|
| 5493 | #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e |
|---|
| 5494 | #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 |
|---|
| 5495 | #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f |
|---|
| 5496 | #define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 |
|---|
| 5497 | #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020 |
|---|
| 5498 | #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 |
|---|
| 5499 | #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021 |
|---|
| 5500 | #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 |
|---|
| 5501 | #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022 |
|---|
| 5502 | #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 |
|---|
| 5503 | #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023 |
|---|
| 5504 | #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 |
|---|
| 5505 | #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024 |
|---|
| 5506 | #define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 |
|---|
| 5507 | #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025 |
|---|
| 5508 | #define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 |
|---|
| 5509 | #define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026 |
|---|
| 5510 | #define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 |
|---|
| 5511 | #define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027 |
|---|
| 5512 | #define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 |
|---|
| 5513 | #define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028 |
|---|
| 5514 | #define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 |
|---|
| 5515 | #define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029 |
|---|
| 5516 | #define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 |
|---|
| 5517 | #define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a |
|---|
| 5518 | #define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 |
|---|
| 5519 | #define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b |
|---|
| 5520 | #define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 |
|---|
| 5521 | #define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c |
|---|
| 5522 | #define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 |
|---|
| 5523 | #define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d |
|---|
| 5524 | #define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 |
|---|
| 5525 | #define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e |
|---|
| 5526 | #define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 |
|---|
| 5527 | #define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f |
|---|
| 5528 | #define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 |
|---|
| 5529 | #define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030 |
|---|
| 5530 | #define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 |
|---|
| 5531 | #define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031 |
|---|
| 5532 | #define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 |
|---|
| 5533 | #define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032 |
|---|
| 5534 | #define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 |
|---|
| 5535 | #define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033 |
|---|
| 5536 | #define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 |
|---|
| 5537 | #define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034 |
|---|
| 5538 | #define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 |
|---|
| 5539 | #define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035 |
|---|
| 5540 | #define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 |
|---|
| 5541 | #define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036 |
|---|
| 5542 | #define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 |
|---|
| 5543 | #define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037 |
|---|
| 5544 | #define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 |
|---|
| 5545 | #define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038 |
|---|
| 5546 | #define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 |
|---|
| 5547 | #define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039 |
|---|
| 5548 | #define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 |
|---|
| 5549 | #define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a |
|---|
| 5550 | #define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 |
|---|
| 5551 | #define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b |
|---|
| 5552 | #define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 |
|---|
| 5553 | #define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c |
|---|
| 5554 | #define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 |
|---|
| 5555 | #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d |
|---|
| 5556 | #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 |
|---|
| 5557 | #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e |
|---|
| 5558 | #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 |
|---|
| 5559 | #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f |
|---|
| 5560 | #define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 |
|---|
| 5561 | #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040 |
|---|
| 5562 | #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 |
|---|
| 5563 | #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041 |
|---|
| 5564 | #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 |
|---|
| 5565 | #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042 |
|---|
| 5566 | #define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 |
|---|
| 5567 | #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043 |
|---|
| 5568 | #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 |
|---|
| 5569 | #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044 |
|---|
| 5570 | #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 |
|---|
| 5571 | #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045 |
|---|
| 5572 | #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 |
|---|
| 5573 | #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046 |
|---|
| 5574 | #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 |
|---|
| 5575 | #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047 |
|---|
| 5576 | #define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 |
|---|
| 5577 | #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048 |
|---|
| 5578 | #define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 |
|---|
| 5579 | #define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049 |
|---|
| 5580 | #define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 |
|---|
| 5581 | #define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a |
|---|
| 5582 | #define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 |
|---|
| 5583 | #define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b |
|---|
| 5584 | #define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 |
|---|
| 5585 | #define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c |
|---|
| 5586 | #define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 |
|---|
| 5587 | #define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d |
|---|
| 5588 | #define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 |
|---|
| 5589 | #define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e |
|---|
| 5590 | #define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 |
|---|
| 5591 | #define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f |
|---|
| 5592 | #define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 |
|---|
| 5593 | #define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050 |
|---|
| 5594 | #define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 |
|---|
| 5595 | #define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051 |
|---|
| 5596 | #define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 |
|---|
| 5597 | #define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052 |
|---|
| 5598 | #define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 |
|---|
| 5599 | #define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053 |
|---|
| 5600 | #define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 |
|---|
| 5601 | #define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054 |
|---|
| 5602 | #define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 |
|---|
| 5603 | #define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055 |
|---|
| 5604 | #define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 |
|---|
| 5605 | #define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056 |
|---|
| 5606 | #define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 |
|---|
| 5607 | #define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057 |
|---|
| 5608 | #define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 |
|---|
| 5609 | #define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058 |
|---|
| 5610 | #define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 |
|---|
| 5611 | #define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059 |
|---|
| 5612 | #define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 |
|---|
| 5613 | #define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a |
|---|
| 5614 | #define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 |
|---|
| 5615 | #define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b |
|---|
| 5616 | #define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 |
|---|
| 5617 | #define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c |
|---|
| 5618 | #define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 |
|---|
| 5619 | #define regCM2_CM_HDR_MULT_COEF 0x105d |
|---|
| 5620 | #define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 |
|---|
| 5621 | #define regCM2_CM_MEM_PWR_CTRL 0x105e |
|---|
| 5622 | #define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 5623 | #define regCM2_CM_MEM_PWR_STATUS 0x105f |
|---|
| 5624 | #define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 5625 | #define regCM2_CM_DEALPHA 0x1061 |
|---|
| 5626 | #define regCM2_CM_DEALPHA_BASE_IDX 2 |
|---|
| 5627 | #define regCM2_CM_COEF_FORMAT 0x1062 |
|---|
| 5628 | #define regCM2_CM_COEF_FORMAT_BASE_IDX 2 |
|---|
| 5629 | #define regCM2_CM_TEST_DEBUG_INDEX 0x1063 |
|---|
| 5630 | #define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 |
|---|
| 5631 | #define regCM2_CM_TEST_DEBUG_DATA 0x1064 |
|---|
| 5632 | #define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 |
|---|
| 5633 | |
|---|
| 5634 | |
|---|
| 5635 | // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec |
|---|
| 5636 | // base address: 0x43e8 |
|---|
| 5637 | #define regDC_PERFMON13_PERFCOUNTER_CNTL 0x10fa |
|---|
| 5638 | #define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 5639 | #define regDC_PERFMON13_PERFCOUNTER_CNTL2 0x10fb |
|---|
| 5640 | #define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 5641 | #define regDC_PERFMON13_PERFCOUNTER_STATE 0x10fc |
|---|
| 5642 | #define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 5643 | #define regDC_PERFMON13_PERFMON_CNTL 0x10fd |
|---|
| 5644 | #define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 5645 | #define regDC_PERFMON13_PERFMON_CNTL2 0x10fe |
|---|
| 5646 | #define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 5647 | #define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x10ff |
|---|
| 5648 | #define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 5649 | #define regDC_PERFMON13_PERFMON_CVALUE_LOW 0x1100 |
|---|
| 5650 | #define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 5651 | #define regDC_PERFMON13_PERFMON_HI 0x1101 |
|---|
| 5652 | #define regDC_PERFMON13_PERFMON_HI_BASE_IDX 2 |
|---|
| 5653 | #define regDC_PERFMON13_PERFMON_LOW 0x1102 |
|---|
| 5654 | #define regDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 |
|---|
| 5655 | |
|---|
| 5656 | |
|---|
| 5657 | // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec |
|---|
| 5658 | // base address: 0x1104 |
|---|
| 5659 | #define regDPP_TOP3_DPP_CONTROL 0x1106 |
|---|
| 5660 | #define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 |
|---|
| 5661 | #define regDPP_TOP3_DPP_SOFT_RESET 0x1107 |
|---|
| 5662 | #define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 |
|---|
| 5663 | #define regDPP_TOP3_DPP_CRC_VAL_R_G 0x1108 |
|---|
| 5664 | #define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 |
|---|
| 5665 | #define regDPP_TOP3_DPP_CRC_VAL_B_A 0x1109 |
|---|
| 5666 | #define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 |
|---|
| 5667 | #define regDPP_TOP3_DPP_CRC_CTRL 0x110a |
|---|
| 5668 | #define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 |
|---|
| 5669 | #define regDPP_TOP3_HOST_READ_CONTROL 0x110b |
|---|
| 5670 | #define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 |
|---|
| 5671 | |
|---|
| 5672 | |
|---|
| 5673 | // addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec |
|---|
| 5674 | // base address: 0x1104 |
|---|
| 5675 | #define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110 |
|---|
| 5676 | #define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 |
|---|
| 5677 | #define regCNVC_CFG3_FORMAT_CONTROL 0x1111 |
|---|
| 5678 | #define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 |
|---|
| 5679 | #define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1112 |
|---|
| 5680 | #define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 |
|---|
| 5681 | #define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1113 |
|---|
| 5682 | #define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 |
|---|
| 5683 | #define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1114 |
|---|
| 5684 | #define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 |
|---|
| 5685 | #define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1115 |
|---|
| 5686 | #define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 |
|---|
| 5687 | #define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1116 |
|---|
| 5688 | #define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 |
|---|
| 5689 | #define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1117 |
|---|
| 5690 | #define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 |
|---|
| 5691 | #define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118 |
|---|
| 5692 | #define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 |
|---|
| 5693 | #define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119 |
|---|
| 5694 | #define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 |
|---|
| 5695 | #define regCNVC_CFG3_COLOR_KEYER_RED 0x111a |
|---|
| 5696 | #define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 |
|---|
| 5697 | #define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111b |
|---|
| 5698 | #define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 |
|---|
| 5699 | #define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111c |
|---|
| 5700 | #define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 |
|---|
| 5701 | #define regCNVC_CFG3_ALPHA_2BIT_LUT 0x111e |
|---|
| 5702 | #define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2 |
|---|
| 5703 | #define regCNVC_CFG3_PRE_DEALPHA 0x111f |
|---|
| 5704 | #define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 |
|---|
| 5705 | #define regCNVC_CFG3_PRE_CSC_MODE 0x1120 |
|---|
| 5706 | #define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 |
|---|
| 5707 | #define regCNVC_CFG3_PRE_CSC_C11_C12 0x1121 |
|---|
| 5708 | #define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 |
|---|
| 5709 | #define regCNVC_CFG3_PRE_CSC_C13_C14 0x1122 |
|---|
| 5710 | #define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 |
|---|
| 5711 | #define regCNVC_CFG3_PRE_CSC_C21_C22 0x1123 |
|---|
| 5712 | #define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 |
|---|
| 5713 | #define regCNVC_CFG3_PRE_CSC_C23_C24 0x1124 |
|---|
| 5714 | #define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 |
|---|
| 5715 | #define regCNVC_CFG3_PRE_CSC_C31_C32 0x1125 |
|---|
| 5716 | #define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 |
|---|
| 5717 | #define regCNVC_CFG3_PRE_CSC_C33_C34 0x1126 |
|---|
| 5718 | #define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 |
|---|
| 5719 | #define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127 |
|---|
| 5720 | #define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 |
|---|
| 5721 | #define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128 |
|---|
| 5722 | #define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 |
|---|
| 5723 | #define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129 |
|---|
| 5724 | #define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 |
|---|
| 5725 | #define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a |
|---|
| 5726 | #define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 |
|---|
| 5727 | #define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b |
|---|
| 5728 | #define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 |
|---|
| 5729 | #define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c |
|---|
| 5730 | #define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 |
|---|
| 5731 | #define regCNVC_CFG3_CNVC_COEF_FORMAT 0x112d |
|---|
| 5732 | #define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 |
|---|
| 5733 | #define regCNVC_CFG3_PRE_DEGAM 0x112e |
|---|
| 5734 | #define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 |
|---|
| 5735 | #define regCNVC_CFG3_PRE_REALPHA 0x112f |
|---|
| 5736 | #define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 |
|---|
| 5737 | |
|---|
| 5738 | |
|---|
| 5739 | // addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec |
|---|
| 5740 | // base address: 0x1104 |
|---|
| 5741 | #define regCNVC_CUR3_CURSOR0_CONTROL 0x1132 |
|---|
| 5742 | #define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 |
|---|
| 5743 | #define regCNVC_CUR3_CURSOR0_COLOR0 0x1133 |
|---|
| 5744 | #define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 |
|---|
| 5745 | #define regCNVC_CUR3_CURSOR0_COLOR1 0x1134 |
|---|
| 5746 | #define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 |
|---|
| 5747 | #define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135 |
|---|
| 5748 | #define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 |
|---|
| 5749 | |
|---|
| 5750 | |
|---|
| 5751 | // addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec |
|---|
| 5752 | // base address: 0x1104 |
|---|
| 5753 | #define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a |
|---|
| 5754 | #define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 |
|---|
| 5755 | #define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b |
|---|
| 5756 | #define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 |
|---|
| 5757 | #define regDSCL3_SCL_MODE 0x113c |
|---|
| 5758 | #define regDSCL3_SCL_MODE_BASE_IDX 2 |
|---|
| 5759 | #define regDSCL3_SCL_TAP_CONTROL 0x113d |
|---|
| 5760 | #define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 |
|---|
| 5761 | #define regDSCL3_DSCL_CONTROL 0x113e |
|---|
| 5762 | #define regDSCL3_DSCL_CONTROL_BASE_IDX 2 |
|---|
| 5763 | #define regDSCL3_DSCL_2TAP_CONTROL 0x113f |
|---|
| 5764 | #define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 |
|---|
| 5765 | #define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140 |
|---|
| 5766 | #define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 |
|---|
| 5767 | #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141 |
|---|
| 5768 | #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 |
|---|
| 5769 | #define regDSCL3_SCL_HORZ_FILTER_INIT 0x1142 |
|---|
| 5770 | #define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 |
|---|
| 5771 | #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143 |
|---|
| 5772 | #define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
|---|
| 5773 | #define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144 |
|---|
| 5774 | #define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 |
|---|
| 5775 | #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145 |
|---|
| 5776 | #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 |
|---|
| 5777 | #define regDSCL3_SCL_VERT_FILTER_INIT 0x1146 |
|---|
| 5778 | #define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 |
|---|
| 5779 | #define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147 |
|---|
| 5780 | #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 |
|---|
| 5781 | #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148 |
|---|
| 5782 | #define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 |
|---|
| 5783 | #define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1149 |
|---|
| 5784 | #define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 |
|---|
| 5785 | #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a |
|---|
| 5786 | #define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 |
|---|
| 5787 | #define regDSCL3_SCL_BLACK_COLOR 0x114b |
|---|
| 5788 | #define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 |
|---|
| 5789 | #define regDSCL3_DSCL_UPDATE 0x114c |
|---|
| 5790 | #define regDSCL3_DSCL_UPDATE_BASE_IDX 2 |
|---|
| 5791 | #define regDSCL3_DSCL_AUTOCAL 0x114d |
|---|
| 5792 | #define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 |
|---|
| 5793 | #define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e |
|---|
| 5794 | #define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 |
|---|
| 5795 | #define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f |
|---|
| 5796 | #define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 |
|---|
| 5797 | #define regDSCL3_OTG_H_BLANK 0x1150 |
|---|
| 5798 | #define regDSCL3_OTG_H_BLANK_BASE_IDX 2 |
|---|
| 5799 | #define regDSCL3_OTG_V_BLANK 0x1151 |
|---|
| 5800 | #define regDSCL3_OTG_V_BLANK_BASE_IDX 2 |
|---|
| 5801 | #define regDSCL3_RECOUT_START 0x1152 |
|---|
| 5802 | #define regDSCL3_RECOUT_START_BASE_IDX 2 |
|---|
| 5803 | #define regDSCL3_RECOUT_SIZE 0x1153 |
|---|
| 5804 | #define regDSCL3_RECOUT_SIZE_BASE_IDX 2 |
|---|
| 5805 | #define regDSCL3_MPC_SIZE 0x1154 |
|---|
| 5806 | #define regDSCL3_MPC_SIZE_BASE_IDX 2 |
|---|
| 5807 | #define regDSCL3_LB_DATA_FORMAT 0x1155 |
|---|
| 5808 | #define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 |
|---|
| 5809 | #define regDSCL3_LB_MEMORY_CTRL 0x1156 |
|---|
| 5810 | #define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 |
|---|
| 5811 | #define regDSCL3_LB_V_COUNTER 0x1157 |
|---|
| 5812 | #define regDSCL3_LB_V_COUNTER_BASE_IDX 2 |
|---|
| 5813 | #define regDSCL3_DSCL_MEM_PWR_CTRL 0x1158 |
|---|
| 5814 | #define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 5815 | #define regDSCL3_DSCL_MEM_PWR_STATUS 0x1159 |
|---|
| 5816 | #define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 5817 | #define regDSCL3_OBUF_CONTROL 0x115a |
|---|
| 5818 | #define regDSCL3_OBUF_CONTROL_BASE_IDX 2 |
|---|
| 5819 | #define regDSCL3_OBUF_MEM_PWR_CTRL 0x115b |
|---|
| 5820 | #define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 5821 | |
|---|
| 5822 | |
|---|
| 5823 | // addressBlock: dce_dc_dpp3_dispdec_cm_dispdec |
|---|
| 5824 | // base address: 0x1104 |
|---|
| 5825 | #define regCM3_CM_CONTROL 0x1161 |
|---|
| 5826 | #define regCM3_CM_CONTROL_BASE_IDX 2 |
|---|
| 5827 | #define regCM3_CM_POST_CSC_CONTROL 0x1162 |
|---|
| 5828 | #define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 |
|---|
| 5829 | #define regCM3_CM_POST_CSC_C11_C12 0x1163 |
|---|
| 5830 | #define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 |
|---|
| 5831 | #define regCM3_CM_POST_CSC_C13_C14 0x1164 |
|---|
| 5832 | #define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 |
|---|
| 5833 | #define regCM3_CM_POST_CSC_C21_C22 0x1165 |
|---|
| 5834 | #define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 |
|---|
| 5835 | #define regCM3_CM_POST_CSC_C23_C24 0x1166 |
|---|
| 5836 | #define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 |
|---|
| 5837 | #define regCM3_CM_POST_CSC_C31_C32 0x1167 |
|---|
| 5838 | #define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 |
|---|
| 5839 | #define regCM3_CM_POST_CSC_C33_C34 0x1168 |
|---|
| 5840 | #define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 |
|---|
| 5841 | #define regCM3_CM_POST_CSC_B_C11_C12 0x1169 |
|---|
| 5842 | #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 |
|---|
| 5843 | #define regCM3_CM_POST_CSC_B_C13_C14 0x116a |
|---|
| 5844 | #define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 |
|---|
| 5845 | #define regCM3_CM_POST_CSC_B_C21_C22 0x116b |
|---|
| 5846 | #define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 |
|---|
| 5847 | #define regCM3_CM_POST_CSC_B_C23_C24 0x116c |
|---|
| 5848 | #define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 |
|---|
| 5849 | #define regCM3_CM_POST_CSC_B_C31_C32 0x116d |
|---|
| 5850 | #define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 |
|---|
| 5851 | #define regCM3_CM_POST_CSC_B_C33_C34 0x116e |
|---|
| 5852 | #define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 |
|---|
| 5853 | #define regCM3_CM_GAMUT_REMAP_CONTROL 0x116f |
|---|
| 5854 | #define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 |
|---|
| 5855 | #define regCM3_CM_GAMUT_REMAP_C11_C12 0x1170 |
|---|
| 5856 | #define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 |
|---|
| 5857 | #define regCM3_CM_GAMUT_REMAP_C13_C14 0x1171 |
|---|
| 5858 | #define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 |
|---|
| 5859 | #define regCM3_CM_GAMUT_REMAP_C21_C22 0x1172 |
|---|
| 5860 | #define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 |
|---|
| 5861 | #define regCM3_CM_GAMUT_REMAP_C23_C24 0x1173 |
|---|
| 5862 | #define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 |
|---|
| 5863 | #define regCM3_CM_GAMUT_REMAP_C31_C32 0x1174 |
|---|
| 5864 | #define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 |
|---|
| 5865 | #define regCM3_CM_GAMUT_REMAP_C33_C34 0x1175 |
|---|
| 5866 | #define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 |
|---|
| 5867 | #define regCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176 |
|---|
| 5868 | #define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2 |
|---|
| 5869 | #define regCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177 |
|---|
| 5870 | #define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2 |
|---|
| 5871 | #define regCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178 |
|---|
| 5872 | #define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2 |
|---|
| 5873 | #define regCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179 |
|---|
| 5874 | #define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2 |
|---|
| 5875 | #define regCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a |
|---|
| 5876 | #define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2 |
|---|
| 5877 | #define regCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b |
|---|
| 5878 | #define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2 |
|---|
| 5879 | #define regCM3_CM_BIAS_CR_R 0x117c |
|---|
| 5880 | #define regCM3_CM_BIAS_CR_R_BASE_IDX 2 |
|---|
| 5881 | #define regCM3_CM_BIAS_Y_G_CB_B 0x117d |
|---|
| 5882 | #define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 |
|---|
| 5883 | #define regCM3_CM_GAMCOR_CONTROL 0x117e |
|---|
| 5884 | #define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 |
|---|
| 5885 | #define regCM3_CM_GAMCOR_LUT_INDEX 0x117f |
|---|
| 5886 | #define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 |
|---|
| 5887 | #define regCM3_CM_GAMCOR_LUT_DATA 0x1180 |
|---|
| 5888 | #define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 |
|---|
| 5889 | #define regCM3_CM_GAMCOR_LUT_CONTROL 0x1181 |
|---|
| 5890 | #define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 |
|---|
| 5891 | #define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182 |
|---|
| 5892 | #define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 |
|---|
| 5893 | #define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183 |
|---|
| 5894 | #define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 |
|---|
| 5895 | #define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184 |
|---|
| 5896 | #define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 |
|---|
| 5897 | #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185 |
|---|
| 5898 | #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 |
|---|
| 5899 | #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186 |
|---|
| 5900 | #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 |
|---|
| 5901 | #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187 |
|---|
| 5902 | #define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 |
|---|
| 5903 | #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188 |
|---|
| 5904 | #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 |
|---|
| 5905 | #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189 |
|---|
| 5906 | #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 |
|---|
| 5907 | #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a |
|---|
| 5908 | #define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 |
|---|
| 5909 | #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b |
|---|
| 5910 | #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 |
|---|
| 5911 | #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c |
|---|
| 5912 | #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 |
|---|
| 5913 | #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d |
|---|
| 5914 | #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 |
|---|
| 5915 | #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e |
|---|
| 5916 | #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 |
|---|
| 5917 | #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f |
|---|
| 5918 | #define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 |
|---|
| 5919 | #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190 |
|---|
| 5920 | #define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 |
|---|
| 5921 | #define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191 |
|---|
| 5922 | #define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 |
|---|
| 5923 | #define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192 |
|---|
| 5924 | #define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 |
|---|
| 5925 | #define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193 |
|---|
| 5926 | #define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 |
|---|
| 5927 | #define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194 |
|---|
| 5928 | #define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 |
|---|
| 5929 | #define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195 |
|---|
| 5930 | #define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 |
|---|
| 5931 | #define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196 |
|---|
| 5932 | #define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 |
|---|
| 5933 | #define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197 |
|---|
| 5934 | #define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 |
|---|
| 5935 | #define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198 |
|---|
| 5936 | #define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 |
|---|
| 5937 | #define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199 |
|---|
| 5938 | #define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 |
|---|
| 5939 | #define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a |
|---|
| 5940 | #define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 |
|---|
| 5941 | #define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b |
|---|
| 5942 | #define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 |
|---|
| 5943 | #define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c |
|---|
| 5944 | #define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 |
|---|
| 5945 | #define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d |
|---|
| 5946 | #define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 |
|---|
| 5947 | #define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e |
|---|
| 5948 | #define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 |
|---|
| 5949 | #define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f |
|---|
| 5950 | #define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 |
|---|
| 5951 | #define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0 |
|---|
| 5952 | #define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 |
|---|
| 5953 | #define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1 |
|---|
| 5954 | #define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 |
|---|
| 5955 | #define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2 |
|---|
| 5956 | #define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 |
|---|
| 5957 | #define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3 |
|---|
| 5958 | #define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 |
|---|
| 5959 | #define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4 |
|---|
| 5960 | #define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 |
|---|
| 5961 | #define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5 |
|---|
| 5962 | #define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 |
|---|
| 5963 | #define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6 |
|---|
| 5964 | #define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 |
|---|
| 5965 | #define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7 |
|---|
| 5966 | #define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 |
|---|
| 5967 | #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8 |
|---|
| 5968 | #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 |
|---|
| 5969 | #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9 |
|---|
| 5970 | #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 |
|---|
| 5971 | #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa |
|---|
| 5972 | #define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 |
|---|
| 5973 | #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab |
|---|
| 5974 | #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 |
|---|
| 5975 | #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac |
|---|
| 5976 | #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 |
|---|
| 5977 | #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad |
|---|
| 5978 | #define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 |
|---|
| 5979 | #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae |
|---|
| 5980 | #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 |
|---|
| 5981 | #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af |
|---|
| 5982 | #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 |
|---|
| 5983 | #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0 |
|---|
| 5984 | #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 |
|---|
| 5985 | #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1 |
|---|
| 5986 | #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 |
|---|
| 5987 | #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2 |
|---|
| 5988 | #define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 |
|---|
| 5989 | #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3 |
|---|
| 5990 | #define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 |
|---|
| 5991 | #define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4 |
|---|
| 5992 | #define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 |
|---|
| 5993 | #define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5 |
|---|
| 5994 | #define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 |
|---|
| 5995 | #define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6 |
|---|
| 5996 | #define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 |
|---|
| 5997 | #define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7 |
|---|
| 5998 | #define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 |
|---|
| 5999 | #define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8 |
|---|
| 6000 | #define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 |
|---|
| 6001 | #define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9 |
|---|
| 6002 | #define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 |
|---|
| 6003 | #define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba |
|---|
| 6004 | #define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 |
|---|
| 6005 | #define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb |
|---|
| 6006 | #define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 |
|---|
| 6007 | #define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc |
|---|
| 6008 | #define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 |
|---|
| 6009 | #define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd |
|---|
| 6010 | #define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 |
|---|
| 6011 | #define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be |
|---|
| 6012 | #define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 |
|---|
| 6013 | #define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf |
|---|
| 6014 | #define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 |
|---|
| 6015 | #define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0 |
|---|
| 6016 | #define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 |
|---|
| 6017 | #define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1 |
|---|
| 6018 | #define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 |
|---|
| 6019 | #define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2 |
|---|
| 6020 | #define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 |
|---|
| 6021 | #define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3 |
|---|
| 6022 | #define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 |
|---|
| 6023 | #define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4 |
|---|
| 6024 | #define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 |
|---|
| 6025 | #define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5 |
|---|
| 6026 | #define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 |
|---|
| 6027 | #define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6 |
|---|
| 6028 | #define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 |
|---|
| 6029 | #define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7 |
|---|
| 6030 | #define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 |
|---|
| 6031 | #define regCM3_CM_HDR_MULT_COEF 0x11c8 |
|---|
| 6032 | #define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 |
|---|
| 6033 | #define regCM3_CM_MEM_PWR_CTRL 0x11c9 |
|---|
| 6034 | #define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 6035 | #define regCM3_CM_MEM_PWR_STATUS 0x11ca |
|---|
| 6036 | #define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 6037 | #define regCM3_CM_DEALPHA 0x11cc |
|---|
| 6038 | #define regCM3_CM_DEALPHA_BASE_IDX 2 |
|---|
| 6039 | #define regCM3_CM_COEF_FORMAT 0x11cd |
|---|
| 6040 | #define regCM3_CM_COEF_FORMAT_BASE_IDX 2 |
|---|
| 6041 | #define regCM3_CM_TEST_DEBUG_INDEX 0x11ce |
|---|
| 6042 | #define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 |
|---|
| 6043 | #define regCM3_CM_TEST_DEBUG_DATA 0x11cf |
|---|
| 6044 | #define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 |
|---|
| 6045 | |
|---|
| 6046 | |
|---|
| 6047 | // addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec |
|---|
| 6048 | // base address: 0x4994 |
|---|
| 6049 | #define regDC_PERFMON14_PERFCOUNTER_CNTL 0x1265 |
|---|
| 6050 | #define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 6051 | #define regDC_PERFMON14_PERFCOUNTER_CNTL2 0x1266 |
|---|
| 6052 | #define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 6053 | #define regDC_PERFMON14_PERFCOUNTER_STATE 0x1267 |
|---|
| 6054 | #define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 6055 | #define regDC_PERFMON14_PERFMON_CNTL 0x1268 |
|---|
| 6056 | #define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 6057 | #define regDC_PERFMON14_PERFMON_CNTL2 0x1269 |
|---|
| 6058 | #define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 6059 | #define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x126a |
|---|
| 6060 | #define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 6061 | #define regDC_PERFMON14_PERFMON_CVALUE_LOW 0x126b |
|---|
| 6062 | #define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 6063 | #define regDC_PERFMON14_PERFMON_HI 0x126c |
|---|
| 6064 | #define regDC_PERFMON14_PERFMON_HI_BASE_IDX 2 |
|---|
| 6065 | #define regDC_PERFMON14_PERFMON_LOW 0x126d |
|---|
| 6066 | #define regDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 |
|---|
| 6067 | |
|---|
| 6068 | |
|---|
| 6069 | // addressBlock: dce_dc_opp_fmt0_dispdec |
|---|
| 6070 | // base address: 0x0 |
|---|
| 6071 | #define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c |
|---|
| 6072 | #define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 |
|---|
| 6073 | #define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d |
|---|
| 6074 | #define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 |
|---|
| 6075 | #define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e |
|---|
| 6076 | #define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 |
|---|
| 6077 | #define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f |
|---|
| 6078 | #define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 |
|---|
| 6079 | #define regFMT0_FMT_CONTROL 0x1840 |
|---|
| 6080 | #define regFMT0_FMT_CONTROL_BASE_IDX 2 |
|---|
| 6081 | #define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 |
|---|
| 6082 | #define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 |
|---|
| 6083 | #define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 |
|---|
| 6084 | #define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 |
|---|
| 6085 | #define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 |
|---|
| 6086 | #define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 |
|---|
| 6087 | #define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 |
|---|
| 6088 | #define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 |
|---|
| 6089 | #define regFMT0_FMT_CLAMP_CNTL 0x1845 |
|---|
| 6090 | #define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 |
|---|
| 6091 | #define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 |
|---|
| 6092 | #define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 |
|---|
| 6093 | #define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 |
|---|
| 6094 | #define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 |
|---|
| 6095 | #define regFMT0_FMT_422_CONTROL 0x1849 |
|---|
| 6096 | #define regFMT0_FMT_422_CONTROL_BASE_IDX 2 |
|---|
| 6097 | |
|---|
| 6098 | |
|---|
| 6099 | // addressBlock: dce_dc_opp_dpg0_dispdec |
|---|
| 6100 | // base address: 0x0 |
|---|
| 6101 | #define regDPG0_DPG_CONTROL 0x1854 |
|---|
| 6102 | #define regDPG0_DPG_CONTROL_BASE_IDX 2 |
|---|
| 6103 | #define regDPG0_DPG_RAMP_CONTROL 0x1855 |
|---|
| 6104 | #define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 |
|---|
| 6105 | #define regDPG0_DPG_DIMENSIONS 0x1856 |
|---|
| 6106 | #define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 |
|---|
| 6107 | #define regDPG0_DPG_COLOUR_R_CR 0x1857 |
|---|
| 6108 | #define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 |
|---|
| 6109 | #define regDPG0_DPG_COLOUR_G_Y 0x1858 |
|---|
| 6110 | #define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 |
|---|
| 6111 | #define regDPG0_DPG_COLOUR_B_CB 0x1859 |
|---|
| 6112 | #define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 |
|---|
| 6113 | #define regDPG0_DPG_OFFSET_SEGMENT 0x185a |
|---|
| 6114 | #define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 |
|---|
| 6115 | #define regDPG0_DPG_STATUS 0x185b |
|---|
| 6116 | #define regDPG0_DPG_STATUS_BASE_IDX 2 |
|---|
| 6117 | |
|---|
| 6118 | |
|---|
| 6119 | // addressBlock: dce_dc_opp_oppbuf0_dispdec |
|---|
| 6120 | // base address: 0x0 |
|---|
| 6121 | #define regOPPBUF0_OPPBUF_CONTROL 0x1884 |
|---|
| 6122 | #define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 |
|---|
| 6123 | #define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 |
|---|
| 6124 | #define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 |
|---|
| 6125 | #define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 |
|---|
| 6126 | #define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 |
|---|
| 6127 | #define regOPPBUF0_OPPBUF_CONTROL1 0x1889 |
|---|
| 6128 | #define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 |
|---|
| 6129 | |
|---|
| 6130 | |
|---|
| 6131 | // addressBlock: dce_dc_opp_opp_pipe0_dispdec |
|---|
| 6132 | // base address: 0x0 |
|---|
| 6133 | #define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188c |
|---|
| 6134 | #define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 |
|---|
| 6135 | |
|---|
| 6136 | |
|---|
| 6137 | // addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec |
|---|
| 6138 | // base address: 0x0 |
|---|
| 6139 | #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 |
|---|
| 6140 | #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 |
|---|
| 6141 | #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 |
|---|
| 6142 | #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 |
|---|
| 6143 | #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 |
|---|
| 6144 | #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 |
|---|
| 6145 | #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 |
|---|
| 6146 | #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 |
|---|
| 6147 | #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 |
|---|
| 6148 | #define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 |
|---|
| 6149 | |
|---|
| 6150 | |
|---|
| 6151 | // addressBlock: dce_dc_opp_fmt1_dispdec |
|---|
| 6152 | // base address: 0x168 |
|---|
| 6153 | #define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 |
|---|
| 6154 | #define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 |
|---|
| 6155 | #define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 |
|---|
| 6156 | #define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 |
|---|
| 6157 | #define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 |
|---|
| 6158 | #define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 |
|---|
| 6159 | #define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 |
|---|
| 6160 | #define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 |
|---|
| 6161 | #define regFMT1_FMT_CONTROL 0x189a |
|---|
| 6162 | #define regFMT1_FMT_CONTROL_BASE_IDX 2 |
|---|
| 6163 | #define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b |
|---|
| 6164 | #define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 |
|---|
| 6165 | #define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c |
|---|
| 6166 | #define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 |
|---|
| 6167 | #define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d |
|---|
| 6168 | #define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 |
|---|
| 6169 | #define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e |
|---|
| 6170 | #define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 |
|---|
| 6171 | #define regFMT1_FMT_CLAMP_CNTL 0x189f |
|---|
| 6172 | #define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 |
|---|
| 6173 | #define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 |
|---|
| 6174 | #define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 |
|---|
| 6175 | #define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 |
|---|
| 6176 | #define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 |
|---|
| 6177 | #define regFMT1_FMT_422_CONTROL 0x18a3 |
|---|
| 6178 | #define regFMT1_FMT_422_CONTROL_BASE_IDX 2 |
|---|
| 6179 | |
|---|
| 6180 | |
|---|
| 6181 | // addressBlock: dce_dc_opp_dpg1_dispdec |
|---|
| 6182 | // base address: 0x168 |
|---|
| 6183 | #define regDPG1_DPG_CONTROL 0x18ae |
|---|
| 6184 | #define regDPG1_DPG_CONTROL_BASE_IDX 2 |
|---|
| 6185 | #define regDPG1_DPG_RAMP_CONTROL 0x18af |
|---|
| 6186 | #define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 |
|---|
| 6187 | #define regDPG1_DPG_DIMENSIONS 0x18b0 |
|---|
| 6188 | #define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 |
|---|
| 6189 | #define regDPG1_DPG_COLOUR_R_CR 0x18b1 |
|---|
| 6190 | #define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 |
|---|
| 6191 | #define regDPG1_DPG_COLOUR_G_Y 0x18b2 |
|---|
| 6192 | #define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 |
|---|
| 6193 | #define regDPG1_DPG_COLOUR_B_CB 0x18b3 |
|---|
| 6194 | #define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 |
|---|
| 6195 | #define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 |
|---|
| 6196 | #define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 |
|---|
| 6197 | #define regDPG1_DPG_STATUS 0x18b5 |
|---|
| 6198 | #define regDPG1_DPG_STATUS_BASE_IDX 2 |
|---|
| 6199 | |
|---|
| 6200 | // addressBlock: dce_dc_opp_oppbuf1_dispdec |
|---|
| 6201 | // base address: 0x168 |
|---|
| 6202 | #define regOPPBUF1_OPPBUF_CONTROL 0x18de |
|---|
| 6203 | #define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 |
|---|
| 6204 | #define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df |
|---|
| 6205 | #define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 |
|---|
| 6206 | #define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 |
|---|
| 6207 | #define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 |
|---|
| 6208 | #define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 |
|---|
| 6209 | #define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 |
|---|
| 6210 | |
|---|
| 6211 | |
|---|
| 6212 | // addressBlock: dce_dc_opp_opp_pipe1_dispdec |
|---|
| 6213 | // base address: 0x168 |
|---|
| 6214 | #define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 |
|---|
| 6215 | #define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 |
|---|
| 6216 | |
|---|
| 6217 | |
|---|
| 6218 | // addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec |
|---|
| 6219 | // base address: 0x168 |
|---|
| 6220 | #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb |
|---|
| 6221 | #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 |
|---|
| 6222 | #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec |
|---|
| 6223 | #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 |
|---|
| 6224 | #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed |
|---|
| 6225 | #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 |
|---|
| 6226 | #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee |
|---|
| 6227 | #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 |
|---|
| 6228 | #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef |
|---|
| 6229 | #define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 |
|---|
| 6230 | |
|---|
| 6231 | |
|---|
| 6232 | // addressBlock: dce_dc_opp_fmt2_dispdec |
|---|
| 6233 | // base address: 0x2d0 |
|---|
| 6234 | #define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 |
|---|
| 6235 | #define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 |
|---|
| 6236 | #define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 |
|---|
| 6237 | #define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 |
|---|
| 6238 | #define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 |
|---|
| 6239 | #define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 |
|---|
| 6240 | #define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 |
|---|
| 6241 | #define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 |
|---|
| 6242 | #define regFMT2_FMT_CONTROL 0x18f4 |
|---|
| 6243 | #define regFMT2_FMT_CONTROL_BASE_IDX 2 |
|---|
| 6244 | #define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 |
|---|
| 6245 | #define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 |
|---|
| 6246 | #define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 |
|---|
| 6247 | #define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 |
|---|
| 6248 | #define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 |
|---|
| 6249 | #define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 |
|---|
| 6250 | #define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 |
|---|
| 6251 | #define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 |
|---|
| 6252 | #define regFMT2_FMT_CLAMP_CNTL 0x18f9 |
|---|
| 6253 | #define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 |
|---|
| 6254 | #define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa |
|---|
| 6255 | #define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 |
|---|
| 6256 | #define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb |
|---|
| 6257 | #define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 |
|---|
| 6258 | #define regFMT2_FMT_422_CONTROL 0x18fd |
|---|
| 6259 | #define regFMT2_FMT_422_CONTROL_BASE_IDX 2 |
|---|
| 6260 | |
|---|
| 6261 | |
|---|
| 6262 | // addressBlock: dce_dc_opp_dpg2_dispdec |
|---|
| 6263 | // base address: 0x2d0 |
|---|
| 6264 | #define regDPG2_DPG_CONTROL 0x1908 |
|---|
| 6265 | #define regDPG2_DPG_CONTROL_BASE_IDX 2 |
|---|
| 6266 | #define regDPG2_DPG_RAMP_CONTROL 0x1909 |
|---|
| 6267 | #define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 |
|---|
| 6268 | #define regDPG2_DPG_DIMENSIONS 0x190a |
|---|
| 6269 | #define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 |
|---|
| 6270 | #define regDPG2_DPG_COLOUR_R_CR 0x190b |
|---|
| 6271 | #define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 |
|---|
| 6272 | #define regDPG2_DPG_COLOUR_G_Y 0x190c |
|---|
| 6273 | #define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 |
|---|
| 6274 | #define regDPG2_DPG_COLOUR_B_CB 0x190d |
|---|
| 6275 | #define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 |
|---|
| 6276 | #define regDPG2_DPG_OFFSET_SEGMENT 0x190e |
|---|
| 6277 | #define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 |
|---|
| 6278 | #define regDPG2_DPG_STATUS 0x190f |
|---|
| 6279 | #define regDPG2_DPG_STATUS_BASE_IDX 2 |
|---|
| 6280 | |
|---|
| 6281 | |
|---|
| 6282 | // addressBlock: dce_dc_opp_oppbuf2_dispdec |
|---|
| 6283 | // base address: 0x2d0 |
|---|
| 6284 | #define regOPPBUF2_OPPBUF_CONTROL 0x1938 |
|---|
| 6285 | #define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 |
|---|
| 6286 | #define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 |
|---|
| 6287 | #define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 |
|---|
| 6288 | #define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a |
|---|
| 6289 | #define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 |
|---|
| 6290 | #define regOPPBUF2_OPPBUF_CONTROL1 0x193d |
|---|
| 6291 | #define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 |
|---|
| 6292 | |
|---|
| 6293 | |
|---|
| 6294 | // addressBlock: dce_dc_opp_opp_pipe2_dispdec |
|---|
| 6295 | // base address: 0x2d0 |
|---|
| 6296 | #define regOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 |
|---|
| 6297 | #define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 |
|---|
| 6298 | |
|---|
| 6299 | |
|---|
| 6300 | // addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec |
|---|
| 6301 | // base address: 0x2d0 |
|---|
| 6302 | #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 |
|---|
| 6303 | #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 |
|---|
| 6304 | #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 |
|---|
| 6305 | #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 |
|---|
| 6306 | #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 |
|---|
| 6307 | #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 |
|---|
| 6308 | #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 |
|---|
| 6309 | #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 |
|---|
| 6310 | #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 |
|---|
| 6311 | #define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 |
|---|
| 6312 | |
|---|
| 6313 | |
|---|
| 6314 | // addressBlock: dce_dc_opp_fmt3_dispdec |
|---|
| 6315 | // base address: 0x438 |
|---|
| 6316 | #define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a |
|---|
| 6317 | #define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 |
|---|
| 6318 | #define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b |
|---|
| 6319 | #define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 |
|---|
| 6320 | #define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c |
|---|
| 6321 | #define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 |
|---|
| 6322 | #define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d |
|---|
| 6323 | #define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 |
|---|
| 6324 | #define regFMT3_FMT_CONTROL 0x194e |
|---|
| 6325 | #define regFMT3_FMT_CONTROL_BASE_IDX 2 |
|---|
| 6326 | #define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f |
|---|
| 6327 | #define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 |
|---|
| 6328 | #define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 |
|---|
| 6329 | #define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 |
|---|
| 6330 | #define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 |
|---|
| 6331 | #define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 |
|---|
| 6332 | #define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 |
|---|
| 6333 | #define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 |
|---|
| 6334 | #define regFMT3_FMT_CLAMP_CNTL 0x1953 |
|---|
| 6335 | #define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 |
|---|
| 6336 | #define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 |
|---|
| 6337 | #define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 |
|---|
| 6338 | #define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 |
|---|
| 6339 | #define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 |
|---|
| 6340 | #define regFMT3_FMT_422_CONTROL 0x1957 |
|---|
| 6341 | #define regFMT3_FMT_422_CONTROL_BASE_IDX 2 |
|---|
| 6342 | |
|---|
| 6343 | |
|---|
| 6344 | // addressBlock: dce_dc_opp_dpg3_dispdec |
|---|
| 6345 | // base address: 0x438 |
|---|
| 6346 | #define regDPG3_DPG_CONTROL 0x1962 |
|---|
| 6347 | #define regDPG3_DPG_CONTROL_BASE_IDX 2 |
|---|
| 6348 | #define regDPG3_DPG_RAMP_CONTROL 0x1963 |
|---|
| 6349 | #define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 |
|---|
| 6350 | #define regDPG3_DPG_DIMENSIONS 0x1964 |
|---|
| 6351 | #define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 |
|---|
| 6352 | #define regDPG3_DPG_COLOUR_R_CR 0x1965 |
|---|
| 6353 | #define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 |
|---|
| 6354 | #define regDPG3_DPG_COLOUR_G_Y 0x1966 |
|---|
| 6355 | #define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 |
|---|
| 6356 | #define regDPG3_DPG_COLOUR_B_CB 0x1967 |
|---|
| 6357 | #define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 |
|---|
| 6358 | #define regDPG3_DPG_OFFSET_SEGMENT 0x1968 |
|---|
| 6359 | #define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 |
|---|
| 6360 | #define regDPG3_DPG_STATUS 0x1969 |
|---|
| 6361 | #define regDPG3_DPG_STATUS_BASE_IDX 2 |
|---|
| 6362 | |
|---|
| 6363 | |
|---|
| 6364 | // addressBlock: dce_dc_opp_oppbuf3_dispdec |
|---|
| 6365 | // base address: 0x438 |
|---|
| 6366 | #define regOPPBUF3_OPPBUF_CONTROL 0x1992 |
|---|
| 6367 | #define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 |
|---|
| 6368 | #define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 |
|---|
| 6369 | #define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 |
|---|
| 6370 | #define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 |
|---|
| 6371 | #define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 |
|---|
| 6372 | #define regOPPBUF3_OPPBUF_CONTROL1 0x1997 |
|---|
| 6373 | #define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 |
|---|
| 6374 | |
|---|
| 6375 | |
|---|
| 6376 | // addressBlock: dce_dc_opp_opp_pipe3_dispdec |
|---|
| 6377 | // base address: 0x438 |
|---|
| 6378 | #define regOPP_PIPE3_OPP_PIPE_CONTROL 0x199a |
|---|
| 6379 | #define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 |
|---|
| 6380 | |
|---|
| 6381 | |
|---|
| 6382 | // addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec |
|---|
| 6383 | // base address: 0x438 |
|---|
| 6384 | #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f |
|---|
| 6385 | #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 |
|---|
| 6386 | #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 |
|---|
| 6387 | #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 |
|---|
| 6388 | #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 |
|---|
| 6389 | #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 |
|---|
| 6390 | #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 |
|---|
| 6391 | #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 |
|---|
| 6392 | #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 |
|---|
| 6393 | #define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 |
|---|
| 6394 | |
|---|
| 6395 | |
|---|
| 6396 | // addressBlock: dce_dc_opp_opp_top_dispdec |
|---|
| 6397 | // base address: 0x0 |
|---|
| 6398 | #define regOPP_TOP_CLK_CONTROL 0x1a5e |
|---|
| 6399 | #define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 |
|---|
| 6400 | #define regOPP_ABM_CONTROL 0x1a60 |
|---|
| 6401 | #define regOPP_ABM_CONTROL_BASE_IDX 2 |
|---|
| 6402 | |
|---|
| 6403 | |
|---|
| 6404 | // addressBlock: dce_dc_opp_dscrm0_dispdec |
|---|
| 6405 | // base address: 0x0 |
|---|
| 6406 | #define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 |
|---|
| 6407 | #define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 |
|---|
| 6408 | |
|---|
| 6409 | |
|---|
| 6410 | // addressBlock: dce_dc_opp_dscrm1_dispdec |
|---|
| 6411 | // base address: 0x4 |
|---|
| 6412 | #define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 |
|---|
| 6413 | #define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 |
|---|
| 6414 | |
|---|
| 6415 | |
|---|
| 6416 | // addressBlock: dce_dc_opp_dscrm2_dispdec |
|---|
| 6417 | // base address: 0x8 |
|---|
| 6418 | #define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 |
|---|
| 6419 | #define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 |
|---|
| 6420 | |
|---|
| 6421 | |
|---|
| 6422 | // addressBlock: dce_dc_opp_dscrm3_dispdec |
|---|
| 6423 | // base address: 0xc |
|---|
| 6424 | #define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67 |
|---|
| 6425 | #define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 |
|---|
| 6426 | |
|---|
| 6427 | |
|---|
| 6428 | // addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec |
|---|
| 6429 | // base address: 0x6af8 |
|---|
| 6430 | #define regDC_PERFMON16_PERFCOUNTER_CNTL 0x1abe |
|---|
| 6431 | #define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 6432 | #define regDC_PERFMON16_PERFCOUNTER_CNTL2 0x1abf |
|---|
| 6433 | #define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 6434 | #define regDC_PERFMON16_PERFCOUNTER_STATE 0x1ac0 |
|---|
| 6435 | #define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 6436 | #define regDC_PERFMON16_PERFMON_CNTL 0x1ac1 |
|---|
| 6437 | #define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 6438 | #define regDC_PERFMON16_PERFMON_CNTL2 0x1ac2 |
|---|
| 6439 | #define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 6440 | #define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1ac3 |
|---|
| 6441 | #define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 6442 | #define regDC_PERFMON16_PERFMON_CVALUE_LOW 0x1ac4 |
|---|
| 6443 | #define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 6444 | #define regDC_PERFMON16_PERFMON_HI 0x1ac5 |
|---|
| 6445 | #define regDC_PERFMON16_PERFMON_HI_BASE_IDX 2 |
|---|
| 6446 | #define regDC_PERFMON16_PERFMON_LOW 0x1ac6 |
|---|
| 6447 | #define regDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 |
|---|
| 6448 | |
|---|
| 6449 | |
|---|
| 6450 | // addressBlock: dce_dc_optc_odm0_dispdec |
|---|
| 6451 | // base address: 0x0 |
|---|
| 6452 | #define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca |
|---|
| 6453 | #define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 |
|---|
| 6454 | #define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acb |
|---|
| 6455 | #define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 |
|---|
| 6456 | #define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc |
|---|
| 6457 | #define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 |
|---|
| 6458 | #define regODM0_OPTC_BYTES_PER_PIXEL 0x1acd |
|---|
| 6459 | #define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 |
|---|
| 6460 | #define regODM0_OPTC_WIDTH_CONTROL 0x1ace |
|---|
| 6461 | #define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 |
|---|
| 6462 | #define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf |
|---|
| 6463 | #define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 6464 | #define regODM0_OPTC_MEMORY_CONFIG 0x1ad0 |
|---|
| 6465 | #define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 |
|---|
| 6466 | #define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1 |
|---|
| 6467 | #define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 |
|---|
| 6468 | |
|---|
| 6469 | |
|---|
| 6470 | // addressBlock: dce_dc_optc_odm1_dispdec |
|---|
| 6471 | // base address: 0x40 |
|---|
| 6472 | #define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada |
|---|
| 6473 | #define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 |
|---|
| 6474 | #define regODM1_OPTC_DATA_SOURCE_SELECT 0x1adb |
|---|
| 6475 | #define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 |
|---|
| 6476 | #define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc |
|---|
| 6477 | #define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 |
|---|
| 6478 | #define regODM1_OPTC_BYTES_PER_PIXEL 0x1add |
|---|
| 6479 | #define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 |
|---|
| 6480 | #define regODM1_OPTC_WIDTH_CONTROL 0x1ade |
|---|
| 6481 | #define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 |
|---|
| 6482 | #define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf |
|---|
| 6483 | #define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 6484 | #define regODM1_OPTC_MEMORY_CONFIG 0x1ae0 |
|---|
| 6485 | #define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 |
|---|
| 6486 | #define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1 |
|---|
| 6487 | #define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 |
|---|
| 6488 | |
|---|
| 6489 | |
|---|
| 6490 | // addressBlock: dce_dc_optc_odm2_dispdec |
|---|
| 6491 | // base address: 0x80 |
|---|
| 6492 | #define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea |
|---|
| 6493 | #define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 |
|---|
| 6494 | #define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb |
|---|
| 6495 | #define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 |
|---|
| 6496 | #define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec |
|---|
| 6497 | #define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 |
|---|
| 6498 | #define regODM2_OPTC_BYTES_PER_PIXEL 0x1aed |
|---|
| 6499 | #define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 |
|---|
| 6500 | #define regODM2_OPTC_WIDTH_CONTROL 0x1aee |
|---|
| 6501 | #define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 |
|---|
| 6502 | #define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef |
|---|
| 6503 | #define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 6504 | #define regODM2_OPTC_MEMORY_CONFIG 0x1af0 |
|---|
| 6505 | #define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 |
|---|
| 6506 | #define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1 |
|---|
| 6507 | #define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 |
|---|
| 6508 | |
|---|
| 6509 | |
|---|
| 6510 | // addressBlock: dce_dc_optc_odm3_dispdec |
|---|
| 6511 | // base address: 0xc0 |
|---|
| 6512 | #define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa |
|---|
| 6513 | #define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 |
|---|
| 6514 | #define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afb |
|---|
| 6515 | #define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 |
|---|
| 6516 | #define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc |
|---|
| 6517 | #define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 |
|---|
| 6518 | #define regODM3_OPTC_BYTES_PER_PIXEL 0x1afd |
|---|
| 6519 | #define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 |
|---|
| 6520 | #define regODM3_OPTC_WIDTH_CONTROL 0x1afe |
|---|
| 6521 | #define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 |
|---|
| 6522 | #define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff |
|---|
| 6523 | #define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 6524 | #define regODM3_OPTC_MEMORY_CONFIG 0x1b00 |
|---|
| 6525 | #define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 |
|---|
| 6526 | #define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01 |
|---|
| 6527 | #define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 |
|---|
| 6528 | |
|---|
| 6529 | |
|---|
| 6530 | // addressBlock: dce_dc_optc_otg0_dispdec |
|---|
| 6531 | // base address: 0x0 |
|---|
| 6532 | #define regOTG0_OTG_H_TOTAL 0x1b2a |
|---|
| 6533 | #define regOTG0_OTG_H_TOTAL_BASE_IDX 2 |
|---|
| 6534 | #define regOTG0_OTG_H_BLANK_START_END 0x1b2b |
|---|
| 6535 | #define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 |
|---|
| 6536 | #define regOTG0_OTG_H_SYNC_A 0x1b2c |
|---|
| 6537 | #define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 |
|---|
| 6538 | #define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d |
|---|
| 6539 | #define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 |
|---|
| 6540 | #define regOTG0_OTG_H_TIMING_CNTL 0x1b2e |
|---|
| 6541 | #define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 |
|---|
| 6542 | #define regOTG0_OTG_V_TOTAL 0x1b2f |
|---|
| 6543 | #define regOTG0_OTG_V_TOTAL_BASE_IDX 2 |
|---|
| 6544 | #define regOTG0_OTG_V_TOTAL_MIN 0x1b30 |
|---|
| 6545 | #define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 |
|---|
| 6546 | #define regOTG0_OTG_V_TOTAL_MAX 0x1b31 |
|---|
| 6547 | #define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 |
|---|
| 6548 | #define regOTG0_OTG_V_TOTAL_MID 0x1b32 |
|---|
| 6549 | #define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 |
|---|
| 6550 | #define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 |
|---|
| 6551 | #define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 |
|---|
| 6552 | #define regOTG0_OTG_V_COUNT_STOP_CONTROL 0x1b34 |
|---|
| 6553 | #define regOTG0_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 |
|---|
| 6554 | #define regOTG0_OTG_V_COUNT_STOP_CONTROL2 0x1b35 |
|---|
| 6555 | #define regOTG0_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 |
|---|
| 6556 | #define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b36 |
|---|
| 6557 | #define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 |
|---|
| 6558 | #define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b37 |
|---|
| 6559 | #define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 |
|---|
| 6560 | #define regOTG0_OTG_V_BLANK_START_END 0x1b38 |
|---|
| 6561 | #define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 |
|---|
| 6562 | #define regOTG0_OTG_V_SYNC_A 0x1b39 |
|---|
| 6563 | #define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 |
|---|
| 6564 | #define regOTG0_OTG_V_SYNC_A_CNTL 0x1b3a |
|---|
| 6565 | #define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 |
|---|
| 6566 | #define regOTG0_OTG_TRIGA_CNTL 0x1b3b |
|---|
| 6567 | #define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 |
|---|
| 6568 | #define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3c |
|---|
| 6569 | #define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 |
|---|
| 6570 | #define regOTG0_OTG_TRIGB_CNTL 0x1b3d |
|---|
| 6571 | #define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 |
|---|
| 6572 | #define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3e |
|---|
| 6573 | #define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 |
|---|
| 6574 | #define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3f |
|---|
| 6575 | #define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 |
|---|
| 6576 | #define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b41 |
|---|
| 6577 | #define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 |
|---|
| 6578 | #define regOTG0_OTG_CONTROL 0x1b43 |
|---|
| 6579 | #define regOTG0_OTG_CONTROL_BASE_IDX 2 |
|---|
| 6580 | #define regOTG0_OTG_DLPC_CONTROL 0x1b44 |
|---|
| 6581 | #define regOTG0_OTG_DLPC_CONTROL_BASE_IDX 2 |
|---|
| 6582 | #define regOTG0_OTG_INTERLACE_CONTROL 0x1b45 |
|---|
| 6583 | #define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 |
|---|
| 6584 | #define regOTG0_OTG_INTERLACE_STATUS 0x1b46 |
|---|
| 6585 | #define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 |
|---|
| 6586 | #define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 |
|---|
| 6587 | #define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 |
|---|
| 6588 | #define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 |
|---|
| 6589 | #define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 |
|---|
| 6590 | #define regOTG0_OTG_STATUS 0x1b49 |
|---|
| 6591 | #define regOTG0_OTG_STATUS_BASE_IDX 2 |
|---|
| 6592 | #define regOTG0_OTG_STATUS_POSITION 0x1b4a |
|---|
| 6593 | #define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 |
|---|
| 6594 | #define regOTG0_OTG_LONG_VBLANK_STATUS 0x1b4b |
|---|
| 6595 | #define regOTG0_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 |
|---|
| 6596 | #define regOTG0_OTG_NOM_VERT_POSITION 0x1b4c |
|---|
| 6597 | #define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 |
|---|
| 6598 | #define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4d |
|---|
| 6599 | #define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 |
|---|
| 6600 | #define regOTG0_OTG_STATUS_VF_COUNT 0x1b4e |
|---|
| 6601 | #define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 |
|---|
| 6602 | #define regOTG0_OTG_STATUS_HV_COUNT 0x1b4f |
|---|
| 6603 | #define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 |
|---|
| 6604 | #define regOTG0_OTG_COUNT_CONTROL 0x1b50 |
|---|
| 6605 | #define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 6606 | #define regOTG0_OTG_COUNT_RESET 0x1b51 |
|---|
| 6607 | #define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 |
|---|
| 6608 | #define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b52 |
|---|
| 6609 | #define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 |
|---|
| 6610 | #define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b53 |
|---|
| 6611 | #define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 |
|---|
| 6612 | #define regOTG0_OTG_STEREO_STATUS 0x1b54 |
|---|
| 6613 | #define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 |
|---|
| 6614 | #define regOTG0_OTG_STEREO_CONTROL 0x1b55 |
|---|
| 6615 | #define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 |
|---|
| 6616 | #define regOTG0_OTG_SNAPSHOT_STATUS 0x1b56 |
|---|
| 6617 | #define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 |
|---|
| 6618 | #define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b57 |
|---|
| 6619 | #define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 |
|---|
| 6620 | #define regOTG0_OTG_SNAPSHOT_POSITION 0x1b58 |
|---|
| 6621 | #define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 |
|---|
| 6622 | #define regOTG0_OTG_SNAPSHOT_FRAME 0x1b59 |
|---|
| 6623 | #define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 |
|---|
| 6624 | #define regOTG0_OTG_INTERRUPT_CONTROL 0x1b5a |
|---|
| 6625 | #define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 |
|---|
| 6626 | #define regOTG0_OTG_UPDATE_LOCK 0x1b5b |
|---|
| 6627 | #define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 |
|---|
| 6628 | #define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5c |
|---|
| 6629 | #define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
|---|
| 6630 | #define regOTG0_OTG_MASTER_EN 0x1b5d |
|---|
| 6631 | #define regOTG0_OTG_MASTER_EN_BASE_IDX 2 |
|---|
| 6632 | #define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b5f |
|---|
| 6633 | #define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 |
|---|
| 6634 | #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b60 |
|---|
| 6635 | #define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 |
|---|
| 6636 | #define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b61 |
|---|
| 6637 | #define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 |
|---|
| 6638 | #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b62 |
|---|
| 6639 | #define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 |
|---|
| 6640 | #define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b63 |
|---|
| 6641 | #define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 |
|---|
| 6642 | #define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b64 |
|---|
| 6643 | #define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 |
|---|
| 6644 | #define regOTG0_OTG_CRC_CNTL 0x1b65 |
|---|
| 6645 | #define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 |
|---|
| 6646 | #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b66 |
|---|
| 6647 | #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 |
|---|
| 6648 | #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b67 |
|---|
| 6649 | #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 |
|---|
| 6650 | #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b68 |
|---|
| 6651 | #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 |
|---|
| 6652 | #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b69 |
|---|
| 6653 | #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 |
|---|
| 6654 | #define regOTG0_OTG_CRC0_DATA_RG 0x1b6a |
|---|
| 6655 | #define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 |
|---|
| 6656 | #define regOTG0_OTG_CRC0_DATA_B 0x1b6b |
|---|
| 6657 | #define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 |
|---|
| 6658 | #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b6c |
|---|
| 6659 | #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 |
|---|
| 6660 | #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b6d |
|---|
| 6661 | #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 |
|---|
| 6662 | #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b6e |
|---|
| 6663 | #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 |
|---|
| 6664 | #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b6f |
|---|
| 6665 | #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 |
|---|
| 6666 | #define regOTG0_OTG_CRC1_DATA_RG 0x1b70 |
|---|
| 6667 | #define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 |
|---|
| 6668 | #define regOTG0_OTG_CRC1_DATA_B 0x1b71 |
|---|
| 6669 | #define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 |
|---|
| 6670 | #define regOTG0_OTG_CRC2_DATA_RG 0x1b72 |
|---|
| 6671 | #define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 |
|---|
| 6672 | #define regOTG0_OTG_CRC2_DATA_B 0x1b73 |
|---|
| 6673 | #define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 |
|---|
| 6674 | #define regOTG0_OTG_CRC3_DATA_RG 0x1b74 |
|---|
| 6675 | #define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 |
|---|
| 6676 | #define regOTG0_OTG_CRC3_DATA_B 0x1b75 |
|---|
| 6677 | #define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 |
|---|
| 6678 | #define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b76 |
|---|
| 6679 | #define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 |
|---|
| 6680 | #define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b77 |
|---|
| 6681 | #define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 |
|---|
| 6682 | #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1b78 |
|---|
| 6683 | #define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6684 | #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1b79 |
|---|
| 6685 | #define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6686 | #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1b7a |
|---|
| 6687 | #define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6688 | #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1b7b |
|---|
| 6689 | #define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6690 | #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1b7c |
|---|
| 6691 | #define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6692 | #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1b7d |
|---|
| 6693 | #define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6694 | #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1b7e |
|---|
| 6695 | #define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6696 | #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1b7f |
|---|
| 6697 | #define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6698 | #define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b80 |
|---|
| 6699 | #define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 |
|---|
| 6700 | #define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b81 |
|---|
| 6701 | #define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 |
|---|
| 6702 | #define regOTG0_OTG_GSL_VSYNC_GAP 0x1b82 |
|---|
| 6703 | #define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 |
|---|
| 6704 | #define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b83 |
|---|
| 6705 | #define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 |
|---|
| 6706 | #define regOTG0_OTG_CLOCK_CONTROL 0x1b84 |
|---|
| 6707 | #define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 6708 | #define regOTG0_OTG_VSTARTUP_PARAM 0x1b85 |
|---|
| 6709 | #define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 |
|---|
| 6710 | #define regOTG0_OTG_VUPDATE_PARAM 0x1b86 |
|---|
| 6711 | #define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 |
|---|
| 6712 | #define regOTG0_OTG_VREADY_PARAM 0x1b87 |
|---|
| 6713 | #define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 |
|---|
| 6714 | #define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b88 |
|---|
| 6715 | #define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 |
|---|
| 6716 | #define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b89 |
|---|
| 6717 | #define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 |
|---|
| 6718 | #define regOTG0_OTG_GSL_CONTROL 0x1b8a |
|---|
| 6719 | #define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 |
|---|
| 6720 | #define regOTG0_OTG_GSL_WINDOW_X 0x1b8b |
|---|
| 6721 | #define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 |
|---|
| 6722 | #define regOTG0_OTG_GSL_WINDOW_Y 0x1b8c |
|---|
| 6723 | #define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 |
|---|
| 6724 | #define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b8d |
|---|
| 6725 | #define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 |
|---|
| 6726 | #define regOTG0_OTG_GLOBAL_CONTROL0 0x1b8e |
|---|
| 6727 | #define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 |
|---|
| 6728 | #define regOTG0_OTG_GLOBAL_CONTROL1 0x1b8f |
|---|
| 6729 | #define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 |
|---|
| 6730 | #define regOTG0_OTG_GLOBAL_CONTROL2 0x1b90 |
|---|
| 6731 | #define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 |
|---|
| 6732 | #define regOTG0_OTG_GLOBAL_CONTROL3 0x1b91 |
|---|
| 6733 | #define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 |
|---|
| 6734 | #define regOTG0_OTG_GLOBAL_CONTROL4 0x1b92 |
|---|
| 6735 | #define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 |
|---|
| 6736 | #define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b93 |
|---|
| 6737 | #define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 |
|---|
| 6738 | #define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b95 |
|---|
| 6739 | #define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 |
|---|
| 6740 | #define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b96 |
|---|
| 6741 | #define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 |
|---|
| 6742 | #define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b97 |
|---|
| 6743 | #define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 |
|---|
| 6744 | #define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b98 |
|---|
| 6745 | #define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 |
|---|
| 6746 | #define regOTG0_OTG_DRR_CONTROL 0x1b99 |
|---|
| 6747 | #define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 |
|---|
| 6748 | #define regOTG0_OTG_DRR_CONTOL2 0x1b9a |
|---|
| 6749 | #define regOTG0_OTG_DRR_CONTOL2_BASE_IDX 2 |
|---|
| 6750 | #define regOTG0_OTG_M_CONST_DTO0 0x1b9b |
|---|
| 6751 | #define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 |
|---|
| 6752 | #define regOTG0_OTG_M_CONST_DTO1 0x1b9c |
|---|
| 6753 | #define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 |
|---|
| 6754 | #define regOTG0_OTG_REQUEST_CONTROL 0x1b9d |
|---|
| 6755 | #define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 |
|---|
| 6756 | #define regOTG0_OTG_DSC_START_POSITION 0x1b9e |
|---|
| 6757 | #define regOTG0_OTG_DSC_START_POSITION_BASE_IDX 2 |
|---|
| 6758 | #define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1b9f |
|---|
| 6759 | #define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 |
|---|
| 6760 | #define regOTG0_OTG_SPARE_REGISTER 0x1ba0 |
|---|
| 6761 | #define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 |
|---|
| 6762 | |
|---|
| 6763 | |
|---|
| 6764 | // addressBlock: dce_dc_optc_otg1_dispdec |
|---|
| 6765 | // base address: 0x200 |
|---|
| 6766 | #define regOTG1_OTG_H_TOTAL 0x1baa |
|---|
| 6767 | #define regOTG1_OTG_H_TOTAL_BASE_IDX 2 |
|---|
| 6768 | #define regOTG1_OTG_H_BLANK_START_END 0x1bab |
|---|
| 6769 | #define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 |
|---|
| 6770 | #define regOTG1_OTG_H_SYNC_A 0x1bac |
|---|
| 6771 | #define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 |
|---|
| 6772 | #define regOTG1_OTG_H_SYNC_A_CNTL 0x1bad |
|---|
| 6773 | #define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 |
|---|
| 6774 | #define regOTG1_OTG_H_TIMING_CNTL 0x1bae |
|---|
| 6775 | #define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 |
|---|
| 6776 | #define regOTG1_OTG_V_TOTAL 0x1baf |
|---|
| 6777 | #define regOTG1_OTG_V_TOTAL_BASE_IDX 2 |
|---|
| 6778 | #define regOTG1_OTG_V_TOTAL_MIN 0x1bb0 |
|---|
| 6779 | #define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 |
|---|
| 6780 | #define regOTG1_OTG_V_TOTAL_MAX 0x1bb1 |
|---|
| 6781 | #define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 |
|---|
| 6782 | #define regOTG1_OTG_V_TOTAL_MID 0x1bb2 |
|---|
| 6783 | #define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 |
|---|
| 6784 | #define regOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 |
|---|
| 6785 | #define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 |
|---|
| 6786 | #define regOTG1_OTG_V_COUNT_STOP_CONTROL 0x1bb4 |
|---|
| 6787 | #define regOTG1_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 |
|---|
| 6788 | #define regOTG1_OTG_V_COUNT_STOP_CONTROL2 0x1bb5 |
|---|
| 6789 | #define regOTG1_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 |
|---|
| 6790 | #define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb6 |
|---|
| 6791 | #define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 |
|---|
| 6792 | #define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb7 |
|---|
| 6793 | #define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 |
|---|
| 6794 | #define regOTG1_OTG_V_BLANK_START_END 0x1bb8 |
|---|
| 6795 | #define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 |
|---|
| 6796 | #define regOTG1_OTG_V_SYNC_A 0x1bb9 |
|---|
| 6797 | #define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 |
|---|
| 6798 | #define regOTG1_OTG_V_SYNC_A_CNTL 0x1bba |
|---|
| 6799 | #define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 |
|---|
| 6800 | #define regOTG1_OTG_TRIGA_CNTL 0x1bbb |
|---|
| 6801 | #define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 |
|---|
| 6802 | #define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bbc |
|---|
| 6803 | #define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 |
|---|
| 6804 | #define regOTG1_OTG_TRIGB_CNTL 0x1bbd |
|---|
| 6805 | #define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 |
|---|
| 6806 | #define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbe |
|---|
| 6807 | #define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 |
|---|
| 6808 | #define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbf |
|---|
| 6809 | #define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 |
|---|
| 6810 | #define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bc1 |
|---|
| 6811 | #define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 |
|---|
| 6812 | #define regOTG1_OTG_CONTROL 0x1bc3 |
|---|
| 6813 | #define regOTG1_OTG_CONTROL_BASE_IDX 2 |
|---|
| 6814 | #define regOTG1_OTG_DLPC_CONTROL 0x1bc4 |
|---|
| 6815 | #define regOTG1_OTG_DLPC_CONTROL_BASE_IDX 2 |
|---|
| 6816 | #define regOTG1_OTG_INTERLACE_CONTROL 0x1bc5 |
|---|
| 6817 | #define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 |
|---|
| 6818 | #define regOTG1_OTG_INTERLACE_STATUS 0x1bc6 |
|---|
| 6819 | #define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 |
|---|
| 6820 | #define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 |
|---|
| 6821 | #define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 |
|---|
| 6822 | #define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 |
|---|
| 6823 | #define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 |
|---|
| 6824 | #define regOTG1_OTG_STATUS 0x1bc9 |
|---|
| 6825 | #define regOTG1_OTG_STATUS_BASE_IDX 2 |
|---|
| 6826 | #define regOTG1_OTG_STATUS_POSITION 0x1bca |
|---|
| 6827 | #define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 |
|---|
| 6828 | #define regOTG1_OTG_LONG_VBLANK_STATUS 0x1bcb |
|---|
| 6829 | #define regOTG1_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 |
|---|
| 6830 | #define regOTG1_OTG_NOM_VERT_POSITION 0x1bcc |
|---|
| 6831 | #define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 |
|---|
| 6832 | #define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bcd |
|---|
| 6833 | #define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 |
|---|
| 6834 | #define regOTG1_OTG_STATUS_VF_COUNT 0x1bce |
|---|
| 6835 | #define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 |
|---|
| 6836 | #define regOTG1_OTG_STATUS_HV_COUNT 0x1bcf |
|---|
| 6837 | #define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 |
|---|
| 6838 | #define regOTG1_OTG_COUNT_CONTROL 0x1bd0 |
|---|
| 6839 | #define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 6840 | #define regOTG1_OTG_COUNT_RESET 0x1bd1 |
|---|
| 6841 | #define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 |
|---|
| 6842 | #define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd2 |
|---|
| 6843 | #define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 |
|---|
| 6844 | #define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bd3 |
|---|
| 6845 | #define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 |
|---|
| 6846 | #define regOTG1_OTG_STEREO_STATUS 0x1bd4 |
|---|
| 6847 | #define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 |
|---|
| 6848 | #define regOTG1_OTG_STEREO_CONTROL 0x1bd5 |
|---|
| 6849 | #define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 |
|---|
| 6850 | #define regOTG1_OTG_SNAPSHOT_STATUS 0x1bd6 |
|---|
| 6851 | #define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 |
|---|
| 6852 | #define regOTG1_OTG_SNAPSHOT_CONTROL 0x1bd7 |
|---|
| 6853 | #define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 |
|---|
| 6854 | #define regOTG1_OTG_SNAPSHOT_POSITION 0x1bd8 |
|---|
| 6855 | #define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 |
|---|
| 6856 | #define regOTG1_OTG_SNAPSHOT_FRAME 0x1bd9 |
|---|
| 6857 | #define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 |
|---|
| 6858 | #define regOTG1_OTG_INTERRUPT_CONTROL 0x1bda |
|---|
| 6859 | #define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 |
|---|
| 6860 | #define regOTG1_OTG_UPDATE_LOCK 0x1bdb |
|---|
| 6861 | #define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 |
|---|
| 6862 | #define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdc |
|---|
| 6863 | #define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
|---|
| 6864 | #define regOTG1_OTG_MASTER_EN 0x1bdd |
|---|
| 6865 | #define regOTG1_OTG_MASTER_EN_BASE_IDX 2 |
|---|
| 6866 | #define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1bdf |
|---|
| 6867 | #define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 |
|---|
| 6868 | #define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be0 |
|---|
| 6869 | #define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 |
|---|
| 6870 | #define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be1 |
|---|
| 6871 | #define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 |
|---|
| 6872 | #define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be2 |
|---|
| 6873 | #define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 |
|---|
| 6874 | #define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be3 |
|---|
| 6875 | #define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 |
|---|
| 6876 | #define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be4 |
|---|
| 6877 | #define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 |
|---|
| 6878 | #define regOTG1_OTG_CRC_CNTL 0x1be5 |
|---|
| 6879 | #define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 |
|---|
| 6880 | #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1be6 |
|---|
| 6881 | #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 |
|---|
| 6882 | #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1be7 |
|---|
| 6883 | #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 |
|---|
| 6884 | #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1be8 |
|---|
| 6885 | #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 |
|---|
| 6886 | #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1be9 |
|---|
| 6887 | #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 |
|---|
| 6888 | #define regOTG1_OTG_CRC0_DATA_RG 0x1bea |
|---|
| 6889 | #define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 |
|---|
| 6890 | #define regOTG1_OTG_CRC0_DATA_B 0x1beb |
|---|
| 6891 | #define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 |
|---|
| 6892 | #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bec |
|---|
| 6893 | #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 |
|---|
| 6894 | #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bed |
|---|
| 6895 | #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 |
|---|
| 6896 | #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bee |
|---|
| 6897 | #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 |
|---|
| 6898 | #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bef |
|---|
| 6899 | #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 |
|---|
| 6900 | #define regOTG1_OTG_CRC1_DATA_RG 0x1bf0 |
|---|
| 6901 | #define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 |
|---|
| 6902 | #define regOTG1_OTG_CRC1_DATA_B 0x1bf1 |
|---|
| 6903 | #define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 |
|---|
| 6904 | #define regOTG1_OTG_CRC2_DATA_RG 0x1bf2 |
|---|
| 6905 | #define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 |
|---|
| 6906 | #define regOTG1_OTG_CRC2_DATA_B 0x1bf3 |
|---|
| 6907 | #define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 |
|---|
| 6908 | #define regOTG1_OTG_CRC3_DATA_RG 0x1bf4 |
|---|
| 6909 | #define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 |
|---|
| 6910 | #define regOTG1_OTG_CRC3_DATA_B 0x1bf5 |
|---|
| 6911 | #define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 |
|---|
| 6912 | #define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bf6 |
|---|
| 6913 | #define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 |
|---|
| 6914 | #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bf7 |
|---|
| 6915 | #define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 |
|---|
| 6916 | #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1bf8 |
|---|
| 6917 | #define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6918 | #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1bf9 |
|---|
| 6919 | #define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6920 | #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1bfa |
|---|
| 6921 | #define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6922 | #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1bfb |
|---|
| 6923 | #define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6924 | #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1bfc |
|---|
| 6925 | #define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6926 | #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1bfd |
|---|
| 6927 | #define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6928 | #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1bfe |
|---|
| 6929 | #define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6930 | #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1bff |
|---|
| 6931 | #define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 6932 | #define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c00 |
|---|
| 6933 | #define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 |
|---|
| 6934 | #define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c01 |
|---|
| 6935 | #define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 |
|---|
| 6936 | #define regOTG1_OTG_GSL_VSYNC_GAP 0x1c02 |
|---|
| 6937 | #define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 |
|---|
| 6938 | #define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c03 |
|---|
| 6939 | #define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 |
|---|
| 6940 | #define regOTG1_OTG_CLOCK_CONTROL 0x1c04 |
|---|
| 6941 | #define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 6942 | #define regOTG1_OTG_VSTARTUP_PARAM 0x1c05 |
|---|
| 6943 | #define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 |
|---|
| 6944 | #define regOTG1_OTG_VUPDATE_PARAM 0x1c06 |
|---|
| 6945 | #define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 |
|---|
| 6946 | #define regOTG1_OTG_VREADY_PARAM 0x1c07 |
|---|
| 6947 | #define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 |
|---|
| 6948 | #define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c08 |
|---|
| 6949 | #define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 |
|---|
| 6950 | #define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c09 |
|---|
| 6951 | #define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 |
|---|
| 6952 | #define regOTG1_OTG_GSL_CONTROL 0x1c0a |
|---|
| 6953 | #define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 |
|---|
| 6954 | #define regOTG1_OTG_GSL_WINDOW_X 0x1c0b |
|---|
| 6955 | #define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 |
|---|
| 6956 | #define regOTG1_OTG_GSL_WINDOW_Y 0x1c0c |
|---|
| 6957 | #define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 |
|---|
| 6958 | #define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c0d |
|---|
| 6959 | #define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 |
|---|
| 6960 | #define regOTG1_OTG_GLOBAL_CONTROL0 0x1c0e |
|---|
| 6961 | #define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 |
|---|
| 6962 | #define regOTG1_OTG_GLOBAL_CONTROL1 0x1c0f |
|---|
| 6963 | #define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 |
|---|
| 6964 | #define regOTG1_OTG_GLOBAL_CONTROL2 0x1c10 |
|---|
| 6965 | #define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 |
|---|
| 6966 | #define regOTG1_OTG_GLOBAL_CONTROL3 0x1c11 |
|---|
| 6967 | #define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 |
|---|
| 6968 | #define regOTG1_OTG_GLOBAL_CONTROL4 0x1c12 |
|---|
| 6969 | #define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 |
|---|
| 6970 | #define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c13 |
|---|
| 6971 | #define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 |
|---|
| 6972 | #define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c15 |
|---|
| 6973 | #define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 |
|---|
| 6974 | #define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c16 |
|---|
| 6975 | #define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 |
|---|
| 6976 | #define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c17 |
|---|
| 6977 | #define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 |
|---|
| 6978 | #define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c18 |
|---|
| 6979 | #define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 |
|---|
| 6980 | #define regOTG1_OTG_DRR_CONTROL 0x1c19 |
|---|
| 6981 | #define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 |
|---|
| 6982 | #define regOTG1_OTG_DRR_CONTOL2 0x1c1a |
|---|
| 6983 | #define regOTG1_OTG_DRR_CONTOL2_BASE_IDX 2 |
|---|
| 6984 | #define regOTG1_OTG_M_CONST_DTO0 0x1c1b |
|---|
| 6985 | #define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 |
|---|
| 6986 | #define regOTG1_OTG_M_CONST_DTO1 0x1c1c |
|---|
| 6987 | #define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 |
|---|
| 6988 | #define regOTG1_OTG_REQUEST_CONTROL 0x1c1d |
|---|
| 6989 | #define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 |
|---|
| 6990 | #define regOTG1_OTG_DSC_START_POSITION 0x1c1e |
|---|
| 6991 | #define regOTG1_OTG_DSC_START_POSITION_BASE_IDX 2 |
|---|
| 6992 | #define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c1f |
|---|
| 6993 | #define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 |
|---|
| 6994 | #define regOTG1_OTG_SPARE_REGISTER 0x1c20 |
|---|
| 6995 | #define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 |
|---|
| 6996 | |
|---|
| 6997 | |
|---|
| 6998 | // addressBlock: dce_dc_optc_otg2_dispdec |
|---|
| 6999 | // base address: 0x400 |
|---|
| 7000 | #define regOTG2_OTG_H_TOTAL 0x1c2a |
|---|
| 7001 | #define regOTG2_OTG_H_TOTAL_BASE_IDX 2 |
|---|
| 7002 | #define regOTG2_OTG_H_BLANK_START_END 0x1c2b |
|---|
| 7003 | #define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 |
|---|
| 7004 | #define regOTG2_OTG_H_SYNC_A 0x1c2c |
|---|
| 7005 | #define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 |
|---|
| 7006 | #define regOTG2_OTG_H_SYNC_A_CNTL 0x1c2d |
|---|
| 7007 | #define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 |
|---|
| 7008 | #define regOTG2_OTG_H_TIMING_CNTL 0x1c2e |
|---|
| 7009 | #define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 |
|---|
| 7010 | #define regOTG2_OTG_V_TOTAL 0x1c2f |
|---|
| 7011 | #define regOTG2_OTG_V_TOTAL_BASE_IDX 2 |
|---|
| 7012 | #define regOTG2_OTG_V_TOTAL_MIN 0x1c30 |
|---|
| 7013 | #define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 |
|---|
| 7014 | #define regOTG2_OTG_V_TOTAL_MAX 0x1c31 |
|---|
| 7015 | #define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 |
|---|
| 7016 | #define regOTG2_OTG_V_TOTAL_MID 0x1c32 |
|---|
| 7017 | #define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 |
|---|
| 7018 | #define regOTG2_OTG_V_TOTAL_CONTROL 0x1c33 |
|---|
| 7019 | #define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 |
|---|
| 7020 | #define regOTG2_OTG_V_COUNT_STOP_CONTROL 0x1c34 |
|---|
| 7021 | #define regOTG2_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 |
|---|
| 7022 | #define regOTG2_OTG_V_COUNT_STOP_CONTROL2 0x1c35 |
|---|
| 7023 | #define regOTG2_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 |
|---|
| 7024 | #define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c36 |
|---|
| 7025 | #define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 |
|---|
| 7026 | #define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c37 |
|---|
| 7027 | #define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 |
|---|
| 7028 | #define regOTG2_OTG_V_BLANK_START_END 0x1c38 |
|---|
| 7029 | #define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 |
|---|
| 7030 | #define regOTG2_OTG_V_SYNC_A 0x1c39 |
|---|
| 7031 | #define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 |
|---|
| 7032 | #define regOTG2_OTG_V_SYNC_A_CNTL 0x1c3a |
|---|
| 7033 | #define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 |
|---|
| 7034 | #define regOTG2_OTG_TRIGA_CNTL 0x1c3b |
|---|
| 7035 | #define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 |
|---|
| 7036 | #define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3c |
|---|
| 7037 | #define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 |
|---|
| 7038 | #define regOTG2_OTG_TRIGB_CNTL 0x1c3d |
|---|
| 7039 | #define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 |
|---|
| 7040 | #define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3e |
|---|
| 7041 | #define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 |
|---|
| 7042 | #define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3f |
|---|
| 7043 | #define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 |
|---|
| 7044 | #define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c41 |
|---|
| 7045 | #define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 |
|---|
| 7046 | #define regOTG2_OTG_CONTROL 0x1c43 |
|---|
| 7047 | #define regOTG2_OTG_CONTROL_BASE_IDX 2 |
|---|
| 7048 | #define regOTG2_OTG_DLPC_CONTROL 0x1c44 |
|---|
| 7049 | #define regOTG2_OTG_DLPC_CONTROL_BASE_IDX 2 |
|---|
| 7050 | #define regOTG2_OTG_INTERLACE_CONTROL 0x1c45 |
|---|
| 7051 | #define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 |
|---|
| 7052 | #define regOTG2_OTG_INTERLACE_STATUS 0x1c46 |
|---|
| 7053 | #define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 |
|---|
| 7054 | #define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 |
|---|
| 7055 | #define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 |
|---|
| 7056 | #define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 |
|---|
| 7057 | #define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 |
|---|
| 7058 | #define regOTG2_OTG_STATUS 0x1c49 |
|---|
| 7059 | #define regOTG2_OTG_STATUS_BASE_IDX 2 |
|---|
| 7060 | #define regOTG2_OTG_STATUS_POSITION 0x1c4a |
|---|
| 7061 | #define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 |
|---|
| 7062 | #define regOTG2_OTG_LONG_VBLANK_STATUS 0x1c4b |
|---|
| 7063 | #define regOTG2_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 |
|---|
| 7064 | #define regOTG2_OTG_NOM_VERT_POSITION 0x1c4c |
|---|
| 7065 | #define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 |
|---|
| 7066 | #define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c4d |
|---|
| 7067 | #define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 |
|---|
| 7068 | #define regOTG2_OTG_STATUS_VF_COUNT 0x1c4e |
|---|
| 7069 | #define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 |
|---|
| 7070 | #define regOTG2_OTG_STATUS_HV_COUNT 0x1c4f |
|---|
| 7071 | #define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 |
|---|
| 7072 | #define regOTG2_OTG_COUNT_CONTROL 0x1c50 |
|---|
| 7073 | #define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 7074 | #define regOTG2_OTG_COUNT_RESET 0x1c51 |
|---|
| 7075 | #define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 |
|---|
| 7076 | #define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c52 |
|---|
| 7077 | #define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 |
|---|
| 7078 | #define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c53 |
|---|
| 7079 | #define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 |
|---|
| 7080 | #define regOTG2_OTG_STEREO_STATUS 0x1c54 |
|---|
| 7081 | #define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 |
|---|
| 7082 | #define regOTG2_OTG_STEREO_CONTROL 0x1c55 |
|---|
| 7083 | #define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 |
|---|
| 7084 | #define regOTG2_OTG_SNAPSHOT_STATUS 0x1c56 |
|---|
| 7085 | #define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 |
|---|
| 7086 | #define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c57 |
|---|
| 7087 | #define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 |
|---|
| 7088 | #define regOTG2_OTG_SNAPSHOT_POSITION 0x1c58 |
|---|
| 7089 | #define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 |
|---|
| 7090 | #define regOTG2_OTG_SNAPSHOT_FRAME 0x1c59 |
|---|
| 7091 | #define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 |
|---|
| 7092 | #define regOTG2_OTG_INTERRUPT_CONTROL 0x1c5a |
|---|
| 7093 | #define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 |
|---|
| 7094 | #define regOTG2_OTG_UPDATE_LOCK 0x1c5b |
|---|
| 7095 | #define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 |
|---|
| 7096 | #define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5c |
|---|
| 7097 | #define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
|---|
| 7098 | #define regOTG2_OTG_MASTER_EN 0x1c5d |
|---|
| 7099 | #define regOTG2_OTG_MASTER_EN_BASE_IDX 2 |
|---|
| 7100 | #define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c5f |
|---|
| 7101 | #define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 |
|---|
| 7102 | #define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c60 |
|---|
| 7103 | #define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 |
|---|
| 7104 | #define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c61 |
|---|
| 7105 | #define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 |
|---|
| 7106 | #define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c62 |
|---|
| 7107 | #define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 |
|---|
| 7108 | #define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c63 |
|---|
| 7109 | #define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 |
|---|
| 7110 | #define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c64 |
|---|
| 7111 | #define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 |
|---|
| 7112 | #define regOTG2_OTG_CRC_CNTL 0x1c65 |
|---|
| 7113 | #define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 |
|---|
| 7114 | #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c66 |
|---|
| 7115 | #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 |
|---|
| 7116 | #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c67 |
|---|
| 7117 | #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 |
|---|
| 7118 | #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c68 |
|---|
| 7119 | #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 |
|---|
| 7120 | #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c69 |
|---|
| 7121 | #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 |
|---|
| 7122 | #define regOTG2_OTG_CRC0_DATA_RG 0x1c6a |
|---|
| 7123 | #define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 |
|---|
| 7124 | #define regOTG2_OTG_CRC0_DATA_B 0x1c6b |
|---|
| 7125 | #define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 |
|---|
| 7126 | #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c6c |
|---|
| 7127 | #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 |
|---|
| 7128 | #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c6d |
|---|
| 7129 | #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 |
|---|
| 7130 | #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c6e |
|---|
| 7131 | #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 |
|---|
| 7132 | #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c6f |
|---|
| 7133 | #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 |
|---|
| 7134 | #define regOTG2_OTG_CRC1_DATA_RG 0x1c70 |
|---|
| 7135 | #define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 |
|---|
| 7136 | #define regOTG2_OTG_CRC1_DATA_B 0x1c71 |
|---|
| 7137 | #define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 |
|---|
| 7138 | #define regOTG2_OTG_CRC2_DATA_RG 0x1c72 |
|---|
| 7139 | #define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 |
|---|
| 7140 | #define regOTG2_OTG_CRC2_DATA_B 0x1c73 |
|---|
| 7141 | #define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 |
|---|
| 7142 | #define regOTG2_OTG_CRC3_DATA_RG 0x1c74 |
|---|
| 7143 | #define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 |
|---|
| 7144 | #define regOTG2_OTG_CRC3_DATA_B 0x1c75 |
|---|
| 7145 | #define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 |
|---|
| 7146 | #define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c76 |
|---|
| 7147 | #define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 |
|---|
| 7148 | #define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c77 |
|---|
| 7149 | #define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 |
|---|
| 7150 | #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1c78 |
|---|
| 7151 | #define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7152 | #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1c79 |
|---|
| 7153 | #define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7154 | #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1c7a |
|---|
| 7155 | #define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7156 | #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1c7b |
|---|
| 7157 | #define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7158 | #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1c7c |
|---|
| 7159 | #define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7160 | #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1c7d |
|---|
| 7161 | #define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7162 | #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1c7e |
|---|
| 7163 | #define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7164 | #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1c7f |
|---|
| 7165 | #define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7166 | #define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c80 |
|---|
| 7167 | #define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 |
|---|
| 7168 | #define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c81 |
|---|
| 7169 | #define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 |
|---|
| 7170 | #define regOTG2_OTG_GSL_VSYNC_GAP 0x1c82 |
|---|
| 7171 | #define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 |
|---|
| 7172 | #define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c83 |
|---|
| 7173 | #define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 |
|---|
| 7174 | #define regOTG2_OTG_CLOCK_CONTROL 0x1c84 |
|---|
| 7175 | #define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 7176 | #define regOTG2_OTG_VSTARTUP_PARAM 0x1c85 |
|---|
| 7177 | #define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 |
|---|
| 7178 | #define regOTG2_OTG_VUPDATE_PARAM 0x1c86 |
|---|
| 7179 | #define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 |
|---|
| 7180 | #define regOTG2_OTG_VREADY_PARAM 0x1c87 |
|---|
| 7181 | #define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 |
|---|
| 7182 | #define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c88 |
|---|
| 7183 | #define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 |
|---|
| 7184 | #define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1c89 |
|---|
| 7185 | #define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 |
|---|
| 7186 | #define regOTG2_OTG_GSL_CONTROL 0x1c8a |
|---|
| 7187 | #define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 |
|---|
| 7188 | #define regOTG2_OTG_GSL_WINDOW_X 0x1c8b |
|---|
| 7189 | #define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 |
|---|
| 7190 | #define regOTG2_OTG_GSL_WINDOW_Y 0x1c8c |
|---|
| 7191 | #define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 |
|---|
| 7192 | #define regOTG2_OTG_VUPDATE_KEEPOUT 0x1c8d |
|---|
| 7193 | #define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 |
|---|
| 7194 | #define regOTG2_OTG_GLOBAL_CONTROL0 0x1c8e |
|---|
| 7195 | #define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 |
|---|
| 7196 | #define regOTG2_OTG_GLOBAL_CONTROL1 0x1c8f |
|---|
| 7197 | #define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 |
|---|
| 7198 | #define regOTG2_OTG_GLOBAL_CONTROL2 0x1c90 |
|---|
| 7199 | #define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 |
|---|
| 7200 | #define regOTG2_OTG_GLOBAL_CONTROL3 0x1c91 |
|---|
| 7201 | #define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 |
|---|
| 7202 | #define regOTG2_OTG_GLOBAL_CONTROL4 0x1c92 |
|---|
| 7203 | #define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 |
|---|
| 7204 | #define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c93 |
|---|
| 7205 | #define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 |
|---|
| 7206 | #define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c95 |
|---|
| 7207 | #define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 |
|---|
| 7208 | #define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c96 |
|---|
| 7209 | #define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 |
|---|
| 7210 | #define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c97 |
|---|
| 7211 | #define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 |
|---|
| 7212 | #define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c98 |
|---|
| 7213 | #define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 |
|---|
| 7214 | #define regOTG2_OTG_DRR_CONTROL 0x1c99 |
|---|
| 7215 | #define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 |
|---|
| 7216 | #define regOTG2_OTG_DRR_CONTOL2 0x1c9a |
|---|
| 7217 | #define regOTG2_OTG_DRR_CONTOL2_BASE_IDX 2 |
|---|
| 7218 | #define regOTG2_OTG_M_CONST_DTO0 0x1c9b |
|---|
| 7219 | #define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 |
|---|
| 7220 | #define regOTG2_OTG_M_CONST_DTO1 0x1c9c |
|---|
| 7221 | #define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 |
|---|
| 7222 | #define regOTG2_OTG_REQUEST_CONTROL 0x1c9d |
|---|
| 7223 | #define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 |
|---|
| 7224 | #define regOTG2_OTG_DSC_START_POSITION 0x1c9e |
|---|
| 7225 | #define regOTG2_OTG_DSC_START_POSITION_BASE_IDX 2 |
|---|
| 7226 | #define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1c9f |
|---|
| 7227 | #define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 |
|---|
| 7228 | #define regOTG2_OTG_SPARE_REGISTER 0x1ca0 |
|---|
| 7229 | #define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 |
|---|
| 7230 | |
|---|
| 7231 | |
|---|
| 7232 | // addressBlock: dce_dc_optc_otg3_dispdec |
|---|
| 7233 | // base address: 0x600 |
|---|
| 7234 | #define regOTG3_OTG_H_TOTAL 0x1caa |
|---|
| 7235 | #define regOTG3_OTG_H_TOTAL_BASE_IDX 2 |
|---|
| 7236 | #define regOTG3_OTG_H_BLANK_START_END 0x1cab |
|---|
| 7237 | #define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 |
|---|
| 7238 | #define regOTG3_OTG_H_SYNC_A 0x1cac |
|---|
| 7239 | #define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 |
|---|
| 7240 | #define regOTG3_OTG_H_SYNC_A_CNTL 0x1cad |
|---|
| 7241 | #define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 |
|---|
| 7242 | #define regOTG3_OTG_H_TIMING_CNTL 0x1cae |
|---|
| 7243 | #define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 |
|---|
| 7244 | #define regOTG3_OTG_V_TOTAL 0x1caf |
|---|
| 7245 | #define regOTG3_OTG_V_TOTAL_BASE_IDX 2 |
|---|
| 7246 | #define regOTG3_OTG_V_TOTAL_MIN 0x1cb0 |
|---|
| 7247 | #define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 |
|---|
| 7248 | #define regOTG3_OTG_V_TOTAL_MAX 0x1cb1 |
|---|
| 7249 | #define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 |
|---|
| 7250 | #define regOTG3_OTG_V_TOTAL_MID 0x1cb2 |
|---|
| 7251 | #define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 |
|---|
| 7252 | #define regOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 |
|---|
| 7253 | #define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 |
|---|
| 7254 | #define regOTG3_OTG_V_COUNT_STOP_CONTROL 0x1cb4 |
|---|
| 7255 | #define regOTG3_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 |
|---|
| 7256 | #define regOTG3_OTG_V_COUNT_STOP_CONTROL2 0x1cb5 |
|---|
| 7257 | #define regOTG3_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 |
|---|
| 7258 | #define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb6 |
|---|
| 7259 | #define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 |
|---|
| 7260 | #define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb7 |
|---|
| 7261 | #define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 |
|---|
| 7262 | #define regOTG3_OTG_V_BLANK_START_END 0x1cb8 |
|---|
| 7263 | #define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 |
|---|
| 7264 | #define regOTG3_OTG_V_SYNC_A 0x1cb9 |
|---|
| 7265 | #define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 |
|---|
| 7266 | #define regOTG3_OTG_V_SYNC_A_CNTL 0x1cba |
|---|
| 7267 | #define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 |
|---|
| 7268 | #define regOTG3_OTG_TRIGA_CNTL 0x1cbb |
|---|
| 7269 | #define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 |
|---|
| 7270 | #define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cbc |
|---|
| 7271 | #define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 |
|---|
| 7272 | #define regOTG3_OTG_TRIGB_CNTL 0x1cbd |
|---|
| 7273 | #define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 |
|---|
| 7274 | #define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbe |
|---|
| 7275 | #define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 |
|---|
| 7276 | #define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbf |
|---|
| 7277 | #define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 |
|---|
| 7278 | #define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cc1 |
|---|
| 7279 | #define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 |
|---|
| 7280 | #define regOTG3_OTG_CONTROL 0x1cc3 |
|---|
| 7281 | #define regOTG3_OTG_CONTROL_BASE_IDX 2 |
|---|
| 7282 | #define regOTG3_OTG_DLPC_CONTROL 0x1cc4 |
|---|
| 7283 | #define regOTG3_OTG_DLPC_CONTROL_BASE_IDX 2 |
|---|
| 7284 | #define regOTG3_OTG_INTERLACE_CONTROL 0x1cc5 |
|---|
| 7285 | #define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 |
|---|
| 7286 | #define regOTG3_OTG_INTERLACE_STATUS 0x1cc6 |
|---|
| 7287 | #define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 |
|---|
| 7288 | #define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 |
|---|
| 7289 | #define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 |
|---|
| 7290 | #define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 |
|---|
| 7291 | #define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 |
|---|
| 7292 | #define regOTG3_OTG_STATUS 0x1cc9 |
|---|
| 7293 | #define regOTG3_OTG_STATUS_BASE_IDX 2 |
|---|
| 7294 | #define regOTG3_OTG_STATUS_POSITION 0x1cca |
|---|
| 7295 | #define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 |
|---|
| 7296 | #define regOTG3_OTG_LONG_VBLANK_STATUS 0x1ccb |
|---|
| 7297 | #define regOTG3_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 |
|---|
| 7298 | #define regOTG3_OTG_NOM_VERT_POSITION 0x1ccc |
|---|
| 7299 | #define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 |
|---|
| 7300 | #define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ccd |
|---|
| 7301 | #define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 |
|---|
| 7302 | #define regOTG3_OTG_STATUS_VF_COUNT 0x1cce |
|---|
| 7303 | #define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 |
|---|
| 7304 | #define regOTG3_OTG_STATUS_HV_COUNT 0x1ccf |
|---|
| 7305 | #define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 |
|---|
| 7306 | #define regOTG3_OTG_COUNT_CONTROL 0x1cd0 |
|---|
| 7307 | #define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 7308 | #define regOTG3_OTG_COUNT_RESET 0x1cd1 |
|---|
| 7309 | #define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 |
|---|
| 7310 | #define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd2 |
|---|
| 7311 | #define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 |
|---|
| 7312 | #define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cd3 |
|---|
| 7313 | #define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 |
|---|
| 7314 | #define regOTG3_OTG_STEREO_STATUS 0x1cd4 |
|---|
| 7315 | #define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 |
|---|
| 7316 | #define regOTG3_OTG_STEREO_CONTROL 0x1cd5 |
|---|
| 7317 | #define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 |
|---|
| 7318 | #define regOTG3_OTG_SNAPSHOT_STATUS 0x1cd6 |
|---|
| 7319 | #define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 |
|---|
| 7320 | #define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cd7 |
|---|
| 7321 | #define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 |
|---|
| 7322 | #define regOTG3_OTG_SNAPSHOT_POSITION 0x1cd8 |
|---|
| 7323 | #define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 |
|---|
| 7324 | #define regOTG3_OTG_SNAPSHOT_FRAME 0x1cd9 |
|---|
| 7325 | #define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 |
|---|
| 7326 | #define regOTG3_OTG_INTERRUPT_CONTROL 0x1cda |
|---|
| 7327 | #define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 |
|---|
| 7328 | #define regOTG3_OTG_UPDATE_LOCK 0x1cdb |
|---|
| 7329 | #define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 |
|---|
| 7330 | #define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdc |
|---|
| 7331 | #define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
|---|
| 7332 | #define regOTG3_OTG_MASTER_EN 0x1cdd |
|---|
| 7333 | #define regOTG3_OTG_MASTER_EN_BASE_IDX 2 |
|---|
| 7334 | #define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1cdf |
|---|
| 7335 | #define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 |
|---|
| 7336 | #define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce0 |
|---|
| 7337 | #define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 |
|---|
| 7338 | #define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce1 |
|---|
| 7339 | #define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 |
|---|
| 7340 | #define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce2 |
|---|
| 7341 | #define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 |
|---|
| 7342 | #define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce3 |
|---|
| 7343 | #define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 |
|---|
| 7344 | #define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce4 |
|---|
| 7345 | #define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 |
|---|
| 7346 | #define regOTG3_OTG_CRC_CNTL 0x1ce5 |
|---|
| 7347 | #define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 |
|---|
| 7348 | #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1ce6 |
|---|
| 7349 | #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 |
|---|
| 7350 | #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ce7 |
|---|
| 7351 | #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 |
|---|
| 7352 | #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1ce8 |
|---|
| 7353 | #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 |
|---|
| 7354 | #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ce9 |
|---|
| 7355 | #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 |
|---|
| 7356 | #define regOTG3_OTG_CRC0_DATA_RG 0x1cea |
|---|
| 7357 | #define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 |
|---|
| 7358 | #define regOTG3_OTG_CRC0_DATA_B 0x1ceb |
|---|
| 7359 | #define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 |
|---|
| 7360 | #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cec |
|---|
| 7361 | #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 |
|---|
| 7362 | #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1ced |
|---|
| 7363 | #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 |
|---|
| 7364 | #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cee |
|---|
| 7365 | #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 |
|---|
| 7366 | #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cef |
|---|
| 7367 | #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 |
|---|
| 7368 | #define regOTG3_OTG_CRC1_DATA_RG 0x1cf0 |
|---|
| 7369 | #define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 |
|---|
| 7370 | #define regOTG3_OTG_CRC1_DATA_B 0x1cf1 |
|---|
| 7371 | #define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 |
|---|
| 7372 | #define regOTG3_OTG_CRC2_DATA_RG 0x1cf2 |
|---|
| 7373 | #define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 |
|---|
| 7374 | #define regOTG3_OTG_CRC2_DATA_B 0x1cf3 |
|---|
| 7375 | #define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 |
|---|
| 7376 | #define regOTG3_OTG_CRC3_DATA_RG 0x1cf4 |
|---|
| 7377 | #define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 |
|---|
| 7378 | #define regOTG3_OTG_CRC3_DATA_B 0x1cf5 |
|---|
| 7379 | #define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 |
|---|
| 7380 | #define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cf6 |
|---|
| 7381 | #define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 |
|---|
| 7382 | #define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cf7 |
|---|
| 7383 | #define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 |
|---|
| 7384 | #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1cf8 |
|---|
| 7385 | #define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7386 | #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1cf9 |
|---|
| 7387 | #define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7388 | #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1cfa |
|---|
| 7389 | #define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7390 | #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1cfb |
|---|
| 7391 | #define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7392 | #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1cfc |
|---|
| 7393 | #define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7394 | #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1cfd |
|---|
| 7395 | #define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7396 | #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1cfe |
|---|
| 7397 | #define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7398 | #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1cff |
|---|
| 7399 | #define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 |
|---|
| 7400 | #define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d00 |
|---|
| 7401 | #define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 |
|---|
| 7402 | #define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d01 |
|---|
| 7403 | #define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 |
|---|
| 7404 | #define regOTG3_OTG_GSL_VSYNC_GAP 0x1d02 |
|---|
| 7405 | #define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 |
|---|
| 7406 | #define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d03 |
|---|
| 7407 | #define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 |
|---|
| 7408 | #define regOTG3_OTG_CLOCK_CONTROL 0x1d04 |
|---|
| 7409 | #define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 7410 | #define regOTG3_OTG_VSTARTUP_PARAM 0x1d05 |
|---|
| 7411 | #define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 |
|---|
| 7412 | #define regOTG3_OTG_VUPDATE_PARAM 0x1d06 |
|---|
| 7413 | #define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 |
|---|
| 7414 | #define regOTG3_OTG_VREADY_PARAM 0x1d07 |
|---|
| 7415 | #define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 |
|---|
| 7416 | #define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d08 |
|---|
| 7417 | #define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 |
|---|
| 7418 | #define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d09 |
|---|
| 7419 | #define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 |
|---|
| 7420 | #define regOTG3_OTG_GSL_CONTROL 0x1d0a |
|---|
| 7421 | #define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 |
|---|
| 7422 | #define regOTG3_OTG_GSL_WINDOW_X 0x1d0b |
|---|
| 7423 | #define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 |
|---|
| 7424 | #define regOTG3_OTG_GSL_WINDOW_Y 0x1d0c |
|---|
| 7425 | #define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 |
|---|
| 7426 | #define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d0d |
|---|
| 7427 | #define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 |
|---|
| 7428 | #define regOTG3_OTG_GLOBAL_CONTROL0 0x1d0e |
|---|
| 7429 | #define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 |
|---|
| 7430 | #define regOTG3_OTG_GLOBAL_CONTROL1 0x1d0f |
|---|
| 7431 | #define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 |
|---|
| 7432 | #define regOTG3_OTG_GLOBAL_CONTROL2 0x1d10 |
|---|
| 7433 | #define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 |
|---|
| 7434 | #define regOTG3_OTG_GLOBAL_CONTROL3 0x1d11 |
|---|
| 7435 | #define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 |
|---|
| 7436 | #define regOTG3_OTG_GLOBAL_CONTROL4 0x1d12 |
|---|
| 7437 | #define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 |
|---|
| 7438 | #define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d13 |
|---|
| 7439 | #define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 |
|---|
| 7440 | #define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d15 |
|---|
| 7441 | #define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 |
|---|
| 7442 | #define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d16 |
|---|
| 7443 | #define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 |
|---|
| 7444 | #define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d17 |
|---|
| 7445 | #define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 |
|---|
| 7446 | #define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d18 |
|---|
| 7447 | #define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 |
|---|
| 7448 | #define regOTG3_OTG_DRR_CONTROL 0x1d19 |
|---|
| 7449 | #define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 |
|---|
| 7450 | #define regOTG3_OTG_DRR_CONTOL2 0x1d1a |
|---|
| 7451 | #define regOTG3_OTG_DRR_CONTOL2_BASE_IDX 2 |
|---|
| 7452 | #define regOTG3_OTG_M_CONST_DTO0 0x1d1b |
|---|
| 7453 | #define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 |
|---|
| 7454 | #define regOTG3_OTG_M_CONST_DTO1 0x1d1c |
|---|
| 7455 | #define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 |
|---|
| 7456 | #define regOTG3_OTG_REQUEST_CONTROL 0x1d1d |
|---|
| 7457 | #define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 |
|---|
| 7458 | #define regOTG3_OTG_DSC_START_POSITION 0x1d1e |
|---|
| 7459 | #define regOTG3_OTG_DSC_START_POSITION_BASE_IDX 2 |
|---|
| 7460 | #define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d1f |
|---|
| 7461 | #define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 |
|---|
| 7462 | #define regOTG3_OTG_SPARE_REGISTER 0x1d20 |
|---|
| 7463 | #define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 |
|---|
| 7464 | |
|---|
| 7465 | |
|---|
| 7466 | // addressBlock: dce_dc_optc_optc_misc_dispdec |
|---|
| 7467 | // base address: 0x0 |
|---|
| 7468 | #define regGSL_SOURCE_SELECT 0x1e2b |
|---|
| 7469 | #define regGSL_SOURCE_SELECT_BASE_IDX 2 |
|---|
| 7470 | #define regOPTC_DLPC_CONTROL 0x1e2c |
|---|
| 7471 | #define regOPTC_DLPC_CONTROL_BASE_IDX 2 |
|---|
| 7472 | #define regOPTC_CLOCK_CONTROL 0x1e2d |
|---|
| 7473 | #define regOPTC_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 7474 | #define regODM_MEM_PWR_CTRL 0x1e2e |
|---|
| 7475 | #define regODM_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 7476 | #define regODM_MEM_PWR_CTRL3 0x1e30 |
|---|
| 7477 | #define regODM_MEM_PWR_CTRL3_BASE_IDX 2 |
|---|
| 7478 | #define regODM_MEM_PWR_STATUS 0x1e31 |
|---|
| 7479 | #define regODM_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 7480 | #define regOPTC_MISC_SPARE_REGISTER 0x1e32 |
|---|
| 7481 | #define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 |
|---|
| 7482 | |
|---|
| 7483 | |
|---|
| 7484 | // addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec |
|---|
| 7485 | // base address: 0x79a8 |
|---|
| 7486 | #define regDC_PERFMON17_PERFCOUNTER_CNTL 0x1e6a |
|---|
| 7487 | #define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 7488 | #define regDC_PERFMON17_PERFCOUNTER_CNTL2 0x1e6b |
|---|
| 7489 | #define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 7490 | #define regDC_PERFMON17_PERFCOUNTER_STATE 0x1e6c |
|---|
| 7491 | #define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 7492 | #define regDC_PERFMON17_PERFMON_CNTL 0x1e6d |
|---|
| 7493 | #define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 7494 | #define regDC_PERFMON17_PERFMON_CNTL2 0x1e6e |
|---|
| 7495 | #define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 7496 | #define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1e6f |
|---|
| 7497 | #define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 7498 | #define regDC_PERFMON17_PERFMON_CVALUE_LOW 0x1e70 |
|---|
| 7499 | #define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 7500 | #define regDC_PERFMON17_PERFMON_HI 0x1e71 |
|---|
| 7501 | #define regDC_PERFMON17_PERFMON_HI_BASE_IDX 2 |
|---|
| 7502 | #define regDC_PERFMON17_PERFMON_LOW 0x1e72 |
|---|
| 7503 | #define regDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 |
|---|
| 7504 | |
|---|
| 7505 | |
|---|
| 7506 | // addressBlock: dce_dc_dio_dout_i2c_dispdec |
|---|
| 7507 | // base address: 0x0 |
|---|
| 7508 | #define regDC_I2C_CONTROL 0x1e98 |
|---|
| 7509 | #define regDC_I2C_CONTROL_BASE_IDX 2 |
|---|
| 7510 | #define regDC_I2C_ARBITRATION 0x1e99 |
|---|
| 7511 | #define regDC_I2C_ARBITRATION_BASE_IDX 2 |
|---|
| 7512 | #define regDC_I2C_INTERRUPT_CONTROL 0x1e9a |
|---|
| 7513 | #define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 |
|---|
| 7514 | #define regDC_I2C_SW_STATUS 0x1e9b |
|---|
| 7515 | #define regDC_I2C_SW_STATUS_BASE_IDX 2 |
|---|
| 7516 | #define regDC_I2C_DDC1_HW_STATUS 0x1e9c |
|---|
| 7517 | #define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 |
|---|
| 7518 | #define regDC_I2C_DDC2_HW_STATUS 0x1e9d |
|---|
| 7519 | #define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 |
|---|
| 7520 | #define regDC_I2C_DDC3_HW_STATUS 0x1e9e |
|---|
| 7521 | #define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 |
|---|
| 7522 | #define regDC_I2C_DDC4_HW_STATUS 0x1e9f |
|---|
| 7523 | #define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 |
|---|
| 7524 | #define regDC_I2C_DDC5_HW_STATUS 0x1ea0 |
|---|
| 7525 | #define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 |
|---|
| 7526 | #define regDC_I2C_DDC1_SPEED 0x1ea2 |
|---|
| 7527 | #define regDC_I2C_DDC1_SPEED_BASE_IDX 2 |
|---|
| 7528 | #define regDC_I2C_DDC1_SETUP 0x1ea3 |
|---|
| 7529 | #define regDC_I2C_DDC1_SETUP_BASE_IDX 2 |
|---|
| 7530 | #define regDC_I2C_DDC2_SPEED 0x1ea4 |
|---|
| 7531 | #define regDC_I2C_DDC2_SPEED_BASE_IDX 2 |
|---|
| 7532 | #define regDC_I2C_DDC2_SETUP 0x1ea5 |
|---|
| 7533 | #define regDC_I2C_DDC2_SETUP_BASE_IDX 2 |
|---|
| 7534 | #define regDC_I2C_DDC3_SPEED 0x1ea6 |
|---|
| 7535 | #define regDC_I2C_DDC3_SPEED_BASE_IDX 2 |
|---|
| 7536 | #define regDC_I2C_DDC3_SETUP 0x1ea7 |
|---|
| 7537 | #define regDC_I2C_DDC3_SETUP_BASE_IDX 2 |
|---|
| 7538 | #define regDC_I2C_DDC4_SPEED 0x1ea8 |
|---|
| 7539 | #define regDC_I2C_DDC4_SPEED_BASE_IDX 2 |
|---|
| 7540 | #define regDC_I2C_DDC4_SETUP 0x1ea9 |
|---|
| 7541 | #define regDC_I2C_DDC4_SETUP_BASE_IDX 2 |
|---|
| 7542 | #define regDC_I2C_DDC5_SPEED 0x1eaa |
|---|
| 7543 | #define regDC_I2C_DDC5_SPEED_BASE_IDX 2 |
|---|
| 7544 | #define regDC_I2C_DDC5_SETUP 0x1eab |
|---|
| 7545 | #define regDC_I2C_DDC5_SETUP_BASE_IDX 2 |
|---|
| 7546 | #define regDC_I2C_TRANSACTION0 0x1eae |
|---|
| 7547 | #define regDC_I2C_TRANSACTION0_BASE_IDX 2 |
|---|
| 7548 | #define regDC_I2C_TRANSACTION1 0x1eaf |
|---|
| 7549 | #define regDC_I2C_TRANSACTION1_BASE_IDX 2 |
|---|
| 7550 | #define regDC_I2C_TRANSACTION2 0x1eb0 |
|---|
| 7551 | #define regDC_I2C_TRANSACTION2_BASE_IDX 2 |
|---|
| 7552 | #define regDC_I2C_TRANSACTION3 0x1eb1 |
|---|
| 7553 | #define regDC_I2C_TRANSACTION3_BASE_IDX 2 |
|---|
| 7554 | #define regDC_I2C_DATA 0x1eb2 |
|---|
| 7555 | #define regDC_I2C_DATA_BASE_IDX 2 |
|---|
| 7556 | #define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 |
|---|
| 7557 | #define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 |
|---|
| 7558 | #define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 |
|---|
| 7559 | #define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 |
|---|
| 7560 | |
|---|
| 7561 | |
|---|
| 7562 | // addressBlock: dce_dc_dio_dio_misc_dispdec |
|---|
| 7563 | // base address: 0x0 |
|---|
| 7564 | #define regDIO_DCN_STATUS 0x1ec3 |
|---|
| 7565 | #define regDIO_DCN_STATUS_BASE_IDX 2 |
|---|
| 7566 | #define regDIO_SCRATCH0 0x1eca |
|---|
| 7567 | #define regDIO_SCRATCH0_BASE_IDX 2 |
|---|
| 7568 | #define regDIO_SCRATCH1 0x1ecb |
|---|
| 7569 | #define regDIO_SCRATCH1_BASE_IDX 2 |
|---|
| 7570 | #define regDIO_SCRATCH2 0x1ecc |
|---|
| 7571 | #define regDIO_SCRATCH2_BASE_IDX 2 |
|---|
| 7572 | #define regDIO_SCRATCH3 0x1ecd |
|---|
| 7573 | #define regDIO_SCRATCH3_BASE_IDX 2 |
|---|
| 7574 | #define regDIO_SCRATCH4 0x1ece |
|---|
| 7575 | #define regDIO_SCRATCH4_BASE_IDX 2 |
|---|
| 7576 | #define regDIO_SCRATCH5 0x1ecf |
|---|
| 7577 | #define regDIO_SCRATCH5_BASE_IDX 2 |
|---|
| 7578 | #define regDIO_SCRATCH6 0x1ed0 |
|---|
| 7579 | #define regDIO_SCRATCH6_BASE_IDX 2 |
|---|
| 7580 | #define regDIO_SCRATCH7 0x1ed1 |
|---|
| 7581 | #define regDIO_SCRATCH7_BASE_IDX 2 |
|---|
| 7582 | #define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS 0x1ed3 |
|---|
| 7583 | #define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX 2 |
|---|
| 7584 | #define regDIO_MEM_PWR_STATUS 0x1edd |
|---|
| 7585 | #define regDIO_MEM_PWR_STATUS_BASE_IDX 2 |
|---|
| 7586 | #define regDIO_MEM_PWR_CTRL 0x1ede |
|---|
| 7587 | #define regDIO_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 7588 | #define regDIO_MEM_PWR_CTRL2 0x1edf |
|---|
| 7589 | #define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 |
|---|
| 7590 | #define regDIO_CLK_CNTL 0x1ee0 |
|---|
| 7591 | #define regDIO_CLK_CNTL_BASE_IDX 2 |
|---|
| 7592 | #define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 |
|---|
| 7593 | #define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 |
|---|
| 7594 | #define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff |
|---|
| 7595 | #define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 |
|---|
| 7596 | #define regDIO_PSP_INTERRUPT_STATUS 0x1f00 |
|---|
| 7597 | #define regDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2 |
|---|
| 7598 | #define regDIO_PSP_INTERRUPT_CLEAR 0x1f01 |
|---|
| 7599 | #define regDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2 |
|---|
| 7600 | #define regDIO_STATUS 0x1f02 |
|---|
| 7601 | #define regDIO_STATUS_BASE_IDX 2 |
|---|
| 7602 | #define regDIO_LINKA_CNTL 0x1f04 |
|---|
| 7603 | #define regDIO_LINKA_CNTL_BASE_IDX 2 |
|---|
| 7604 | #define regDIO_LINKB_CNTL 0x1f05 |
|---|
| 7605 | #define regDIO_LINKB_CNTL_BASE_IDX 2 |
|---|
| 7606 | #define regDIO_LINKC_CNTL 0x1f06 |
|---|
| 7607 | #define regDIO_LINKC_CNTL_BASE_IDX 2 |
|---|
| 7608 | #define regDIO_LINKD_CNTL 0x1f07 |
|---|
| 7609 | #define regDIO_LINKD_CNTL_BASE_IDX 2 |
|---|
| 7610 | #define regDIO_LINKE_CNTL 0x1f08 |
|---|
| 7611 | #define regDIO_LINKE_CNTL_BASE_IDX 2 |
|---|
| 7612 | #define regDIO_LINKF_CNTL 0x1f09 |
|---|
| 7613 | #define regDIO_LINKF_CNTL_BASE_IDX 2 |
|---|
| 7614 | |
|---|
| 7615 | |
|---|
| 7616 | // addressBlock: dce_dc_dio_hpd0_dispdec |
|---|
| 7617 | // base address: 0x0 |
|---|
| 7618 | #define regHPD0_DC_HPD_INT_STATUS 0x1f14 |
|---|
| 7619 | #define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 |
|---|
| 7620 | #define regHPD0_DC_HPD_INT_CONTROL 0x1f15 |
|---|
| 7621 | #define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 |
|---|
| 7622 | #define regHPD0_DC_HPD_CONTROL 0x1f16 |
|---|
| 7623 | #define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 |
|---|
| 7624 | #define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 |
|---|
| 7625 | #define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 |
|---|
| 7626 | #define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 |
|---|
| 7627 | #define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 |
|---|
| 7628 | |
|---|
| 7629 | |
|---|
| 7630 | // addressBlock: dce_dc_dio_hpd1_dispdec |
|---|
| 7631 | // base address: 0x20 |
|---|
| 7632 | #define regHPD1_DC_HPD_INT_STATUS 0x1f1c |
|---|
| 7633 | #define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 |
|---|
| 7634 | #define regHPD1_DC_HPD_INT_CONTROL 0x1f1d |
|---|
| 7635 | #define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 |
|---|
| 7636 | #define regHPD1_DC_HPD_CONTROL 0x1f1e |
|---|
| 7637 | #define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 |
|---|
| 7638 | #define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f |
|---|
| 7639 | #define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 |
|---|
| 7640 | #define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 |
|---|
| 7641 | #define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 |
|---|
| 7642 | |
|---|
| 7643 | |
|---|
| 7644 | // addressBlock: dce_dc_dio_hpd2_dispdec |
|---|
| 7645 | // base address: 0x40 |
|---|
| 7646 | #define regHPD2_DC_HPD_INT_STATUS 0x1f24 |
|---|
| 7647 | #define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 |
|---|
| 7648 | #define regHPD2_DC_HPD_INT_CONTROL 0x1f25 |
|---|
| 7649 | #define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 |
|---|
| 7650 | #define regHPD2_DC_HPD_CONTROL 0x1f26 |
|---|
| 7651 | #define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 |
|---|
| 7652 | #define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 |
|---|
| 7653 | #define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 |
|---|
| 7654 | #define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 |
|---|
| 7655 | #define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 |
|---|
| 7656 | |
|---|
| 7657 | |
|---|
| 7658 | // addressBlock: dce_dc_dio_hpd3_dispdec |
|---|
| 7659 | // base address: 0x60 |
|---|
| 7660 | #define regHPD3_DC_HPD_INT_STATUS 0x1f2c |
|---|
| 7661 | #define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 |
|---|
| 7662 | #define regHPD3_DC_HPD_INT_CONTROL 0x1f2d |
|---|
| 7663 | #define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 |
|---|
| 7664 | #define regHPD3_DC_HPD_CONTROL 0x1f2e |
|---|
| 7665 | #define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 |
|---|
| 7666 | #define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f |
|---|
| 7667 | #define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 |
|---|
| 7668 | #define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 |
|---|
| 7669 | #define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 |
|---|
| 7670 | |
|---|
| 7671 | |
|---|
| 7672 | // addressBlock: dce_dc_dio_hpd4_dispdec |
|---|
| 7673 | // base address: 0x80 |
|---|
| 7674 | #define regHPD4_DC_HPD_INT_STATUS 0x1f34 |
|---|
| 7675 | #define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 |
|---|
| 7676 | #define regHPD4_DC_HPD_INT_CONTROL 0x1f35 |
|---|
| 7677 | #define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 |
|---|
| 7678 | #define regHPD4_DC_HPD_CONTROL 0x1f36 |
|---|
| 7679 | #define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 |
|---|
| 7680 | #define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 |
|---|
| 7681 | #define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 |
|---|
| 7682 | #define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 |
|---|
| 7683 | #define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 |
|---|
| 7684 | |
|---|
| 7685 | |
|---|
| 7686 | // addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec |
|---|
| 7687 | // base address: 0x7d10 |
|---|
| 7688 | #define regDC_PERFMON18_PERFCOUNTER_CNTL 0x1f44 |
|---|
| 7689 | #define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 7690 | #define regDC_PERFMON18_PERFCOUNTER_CNTL2 0x1f45 |
|---|
| 7691 | #define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 7692 | #define regDC_PERFMON18_PERFCOUNTER_STATE 0x1f46 |
|---|
| 7693 | #define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 7694 | #define regDC_PERFMON18_PERFMON_CNTL 0x1f47 |
|---|
| 7695 | #define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 7696 | #define regDC_PERFMON18_PERFMON_CNTL2 0x1f48 |
|---|
| 7697 | #define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 7698 | #define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1f49 |
|---|
| 7699 | #define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 7700 | #define regDC_PERFMON18_PERFMON_CVALUE_LOW 0x1f4a |
|---|
| 7701 | #define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 7702 | #define regDC_PERFMON18_PERFMON_HI 0x1f4b |
|---|
| 7703 | #define regDC_PERFMON18_PERFMON_HI_BASE_IDX 2 |
|---|
| 7704 | #define regDC_PERFMON18_PERFMON_LOW 0x1f4c |
|---|
| 7705 | #define regDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 |
|---|
| 7706 | |
|---|
| 7707 | |
|---|
| 7708 | // addressBlock: dce_dc_dio_dp_aux0_dispdec |
|---|
| 7709 | // base address: 0x0 |
|---|
| 7710 | #define regDP_AUX0_AUX_CONTROL 0x1f50 |
|---|
| 7711 | #define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 |
|---|
| 7712 | #define regDP_AUX0_AUX_SW_CONTROL 0x1f51 |
|---|
| 7713 | #define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 |
|---|
| 7714 | #define regDP_AUX0_AUX_ARB_CONTROL 0x1f52 |
|---|
| 7715 | #define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 |
|---|
| 7716 | #define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 |
|---|
| 7717 | #define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 |
|---|
| 7718 | #define regDP_AUX0_AUX_SW_STATUS 0x1f54 |
|---|
| 7719 | #define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 |
|---|
| 7720 | #define regDP_AUX0_AUX_LS_STATUS 0x1f55 |
|---|
| 7721 | #define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 |
|---|
| 7722 | #define regDP_AUX0_AUX_SW_DATA 0x1f56 |
|---|
| 7723 | #define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 |
|---|
| 7724 | #define regDP_AUX0_AUX_LS_DATA 0x1f57 |
|---|
| 7725 | #define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 |
|---|
| 7726 | #define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 |
|---|
| 7727 | #define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 |
|---|
| 7728 | #define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 |
|---|
| 7729 | #define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 |
|---|
| 7730 | #define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a |
|---|
| 7731 | #define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 |
|---|
| 7732 | #define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b |
|---|
| 7733 | #define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 |
|---|
| 7734 | #define regDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c |
|---|
| 7735 | #define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 |
|---|
| 7736 | #define regDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d |
|---|
| 7737 | #define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 |
|---|
| 7738 | #define regDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e |
|---|
| 7739 | #define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 |
|---|
| 7740 | #define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f |
|---|
| 7741 | #define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 |
|---|
| 7742 | #define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 |
|---|
| 7743 | #define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 |
|---|
| 7744 | #define regDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 |
|---|
| 7745 | #define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 |
|---|
| 7746 | #define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66 |
|---|
| 7747 | #define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 |
|---|
| 7748 | |
|---|
| 7749 | |
|---|
| 7750 | // addressBlock: dce_dc_dio_dp_aux1_dispdec |
|---|
| 7751 | // base address: 0x70 |
|---|
| 7752 | #define regDP_AUX1_AUX_CONTROL 0x1f6c |
|---|
| 7753 | #define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 |
|---|
| 7754 | #define regDP_AUX1_AUX_SW_CONTROL 0x1f6d |
|---|
| 7755 | #define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 |
|---|
| 7756 | #define regDP_AUX1_AUX_ARB_CONTROL 0x1f6e |
|---|
| 7757 | #define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 |
|---|
| 7758 | #define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f |
|---|
| 7759 | #define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 |
|---|
| 7760 | #define regDP_AUX1_AUX_SW_STATUS 0x1f70 |
|---|
| 7761 | #define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 |
|---|
| 7762 | #define regDP_AUX1_AUX_LS_STATUS 0x1f71 |
|---|
| 7763 | #define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 |
|---|
| 7764 | #define regDP_AUX1_AUX_SW_DATA 0x1f72 |
|---|
| 7765 | #define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 |
|---|
| 7766 | #define regDP_AUX1_AUX_LS_DATA 0x1f73 |
|---|
| 7767 | #define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 |
|---|
| 7768 | #define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 |
|---|
| 7769 | #define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 |
|---|
| 7770 | #define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 |
|---|
| 7771 | #define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 |
|---|
| 7772 | #define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 |
|---|
| 7773 | #define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 |
|---|
| 7774 | #define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 |
|---|
| 7775 | #define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 |
|---|
| 7776 | #define regDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 |
|---|
| 7777 | #define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 |
|---|
| 7778 | #define regDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 |
|---|
| 7779 | #define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 |
|---|
| 7780 | #define regDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a |
|---|
| 7781 | #define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 |
|---|
| 7782 | #define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b |
|---|
| 7783 | #define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 |
|---|
| 7784 | #define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c |
|---|
| 7785 | #define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 |
|---|
| 7786 | #define regDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d |
|---|
| 7787 | #define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 |
|---|
| 7788 | #define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82 |
|---|
| 7789 | #define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 |
|---|
| 7790 | |
|---|
| 7791 | |
|---|
| 7792 | // addressBlock: dce_dc_dio_dp_aux2_dispdec |
|---|
| 7793 | // base address: 0xe0 |
|---|
| 7794 | #define regDP_AUX2_AUX_CONTROL 0x1f88 |
|---|
| 7795 | #define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 |
|---|
| 7796 | #define regDP_AUX2_AUX_SW_CONTROL 0x1f89 |
|---|
| 7797 | #define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 |
|---|
| 7798 | #define regDP_AUX2_AUX_ARB_CONTROL 0x1f8a |
|---|
| 7799 | #define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 |
|---|
| 7800 | #define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b |
|---|
| 7801 | #define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 |
|---|
| 7802 | #define regDP_AUX2_AUX_SW_STATUS 0x1f8c |
|---|
| 7803 | #define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 |
|---|
| 7804 | #define regDP_AUX2_AUX_LS_STATUS 0x1f8d |
|---|
| 7805 | #define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 |
|---|
| 7806 | #define regDP_AUX2_AUX_SW_DATA 0x1f8e |
|---|
| 7807 | #define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 |
|---|
| 7808 | #define regDP_AUX2_AUX_LS_DATA 0x1f8f |
|---|
| 7809 | #define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 |
|---|
| 7810 | #define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 |
|---|
| 7811 | #define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 |
|---|
| 7812 | #define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 |
|---|
| 7813 | #define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 |
|---|
| 7814 | #define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 |
|---|
| 7815 | #define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 |
|---|
| 7816 | #define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 |
|---|
| 7817 | #define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 |
|---|
| 7818 | #define regDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 |
|---|
| 7819 | #define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 |
|---|
| 7820 | #define regDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 |
|---|
| 7821 | #define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 |
|---|
| 7822 | #define regDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96 |
|---|
| 7823 | #define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 |
|---|
| 7824 | #define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 |
|---|
| 7825 | #define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 |
|---|
| 7826 | #define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 |
|---|
| 7827 | #define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 |
|---|
| 7828 | #define regDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 |
|---|
| 7829 | #define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 |
|---|
| 7830 | #define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e |
|---|
| 7831 | #define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 |
|---|
| 7832 | |
|---|
| 7833 | |
|---|
| 7834 | // addressBlock: dce_dc_dio_dp_aux3_dispdec |
|---|
| 7835 | // base address: 0x150 |
|---|
| 7836 | #define regDP_AUX3_AUX_CONTROL 0x1fa4 |
|---|
| 7837 | #define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 |
|---|
| 7838 | #define regDP_AUX3_AUX_SW_CONTROL 0x1fa5 |
|---|
| 7839 | #define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 |
|---|
| 7840 | #define regDP_AUX3_AUX_ARB_CONTROL 0x1fa6 |
|---|
| 7841 | #define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 |
|---|
| 7842 | #define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 |
|---|
| 7843 | #define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 |
|---|
| 7844 | #define regDP_AUX3_AUX_SW_STATUS 0x1fa8 |
|---|
| 7845 | #define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 |
|---|
| 7846 | #define regDP_AUX3_AUX_LS_STATUS 0x1fa9 |
|---|
| 7847 | #define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 |
|---|
| 7848 | #define regDP_AUX3_AUX_SW_DATA 0x1faa |
|---|
| 7849 | #define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 |
|---|
| 7850 | #define regDP_AUX3_AUX_LS_DATA 0x1fab |
|---|
| 7851 | #define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 |
|---|
| 7852 | #define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac |
|---|
| 7853 | #define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 |
|---|
| 7854 | #define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad |
|---|
| 7855 | #define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 |
|---|
| 7856 | #define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae |
|---|
| 7857 | #define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 |
|---|
| 7858 | #define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf |
|---|
| 7859 | #define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 |
|---|
| 7860 | #define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 |
|---|
| 7861 | #define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 |
|---|
| 7862 | #define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 |
|---|
| 7863 | #define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 |
|---|
| 7864 | #define regDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2 |
|---|
| 7865 | #define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 |
|---|
| 7866 | #define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 |
|---|
| 7867 | #define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 |
|---|
| 7868 | #define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 |
|---|
| 7869 | #define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 |
|---|
| 7870 | #define regDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 |
|---|
| 7871 | #define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 |
|---|
| 7872 | #define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba |
|---|
| 7873 | #define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 |
|---|
| 7874 | |
|---|
| 7875 | |
|---|
| 7876 | // addressBlock: dce_dc_dio_dp_aux4_dispdec |
|---|
| 7877 | // base address: 0x1c0 |
|---|
| 7878 | #define regDP_AUX4_AUX_CONTROL 0x1fc0 |
|---|
| 7879 | #define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 |
|---|
| 7880 | #define regDP_AUX4_AUX_SW_CONTROL 0x1fc1 |
|---|
| 7881 | #define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 |
|---|
| 7882 | #define regDP_AUX4_AUX_ARB_CONTROL 0x1fc2 |
|---|
| 7883 | #define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 |
|---|
| 7884 | #define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 |
|---|
| 7885 | #define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 |
|---|
| 7886 | #define regDP_AUX4_AUX_SW_STATUS 0x1fc4 |
|---|
| 7887 | #define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 |
|---|
| 7888 | #define regDP_AUX4_AUX_LS_STATUS 0x1fc5 |
|---|
| 7889 | #define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 |
|---|
| 7890 | #define regDP_AUX4_AUX_SW_DATA 0x1fc6 |
|---|
| 7891 | #define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 |
|---|
| 7892 | #define regDP_AUX4_AUX_LS_DATA 0x1fc7 |
|---|
| 7893 | #define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 |
|---|
| 7894 | #define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 |
|---|
| 7895 | #define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 |
|---|
| 7896 | #define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 |
|---|
| 7897 | #define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 |
|---|
| 7898 | #define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca |
|---|
| 7899 | #define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 |
|---|
| 7900 | #define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb |
|---|
| 7901 | #define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 |
|---|
| 7902 | #define regDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc |
|---|
| 7903 | #define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 |
|---|
| 7904 | #define regDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd |
|---|
| 7905 | #define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 |
|---|
| 7906 | #define regDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce |
|---|
| 7907 | #define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2 |
|---|
| 7908 | #define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf |
|---|
| 7909 | #define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 |
|---|
| 7910 | #define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 |
|---|
| 7911 | #define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 |
|---|
| 7912 | #define regDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 |
|---|
| 7913 | #define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 |
|---|
| 7914 | #define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6 |
|---|
| 7915 | #define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 |
|---|
| 7916 | |
|---|
| 7917 | |
|---|
| 7918 | // addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec |
|---|
| 7919 | // base address: 0x154a0 |
|---|
| 7920 | #define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 |
|---|
| 7921 | #define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 7922 | #define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 |
|---|
| 7923 | #define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
|---|
| 7924 | #define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a |
|---|
| 7925 | #define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 7926 | #define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b |
|---|
| 7927 | #define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 7928 | #define regVPG0_VPG_GENERIC_STATUS 0x206c |
|---|
| 7929 | #define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 |
|---|
| 7930 | #define regVPG0_VPG_MEM_PWR 0x206d |
|---|
| 7931 | #define regVPG0_VPG_MEM_PWR_BASE_IDX 2 |
|---|
| 7932 | #define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e |
|---|
| 7933 | #define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 7934 | #define regVPG0_VPG_ISRC1_2_DATA 0x206f |
|---|
| 7935 | #define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 |
|---|
| 7936 | #define regVPG0_VPG_MPEG_INFO0 0x2070 |
|---|
| 7937 | #define regVPG0_VPG_MPEG_INFO0_BASE_IDX 2 |
|---|
| 7938 | #define regVPG0_VPG_MPEG_INFO1 0x2071 |
|---|
| 7939 | #define regVPG0_VPG_MPEG_INFO1_BASE_IDX 2 |
|---|
| 7940 | |
|---|
| 7941 | |
|---|
| 7942 | // addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec |
|---|
| 7943 | // base address: 0x154cc |
|---|
| 7944 | #define regAFMT0_AFMT_ACP 0x2073 |
|---|
| 7945 | #define regAFMT0_AFMT_ACP_BASE_IDX 2 |
|---|
| 7946 | #define regAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074 |
|---|
| 7947 | #define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 7948 | #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075 |
|---|
| 7949 | #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 |
|---|
| 7950 | #define regAFMT0_AFMT_AUDIO_INFO0 0x2076 |
|---|
| 7951 | #define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2 |
|---|
| 7952 | #define regAFMT0_AFMT_AUDIO_INFO1 0x2077 |
|---|
| 7953 | #define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2 |
|---|
| 7954 | #define regAFMT0_AFMT_60958_0 0x2078 |
|---|
| 7955 | #define regAFMT0_AFMT_60958_0_BASE_IDX 2 |
|---|
| 7956 | #define regAFMT0_AFMT_60958_1 0x2079 |
|---|
| 7957 | #define regAFMT0_AFMT_60958_1_BASE_IDX 2 |
|---|
| 7958 | #define regAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a |
|---|
| 7959 | #define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 |
|---|
| 7960 | #define regAFMT0_AFMT_RAMP_CONTROL0 0x207b |
|---|
| 7961 | #define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2 |
|---|
| 7962 | #define regAFMT0_AFMT_RAMP_CONTROL1 0x207c |
|---|
| 7963 | #define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2 |
|---|
| 7964 | #define regAFMT0_AFMT_RAMP_CONTROL2 0x207d |
|---|
| 7965 | #define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2 |
|---|
| 7966 | #define regAFMT0_AFMT_RAMP_CONTROL3 0x207e |
|---|
| 7967 | #define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2 |
|---|
| 7968 | #define regAFMT0_AFMT_60958_2 0x207f |
|---|
| 7969 | #define regAFMT0_AFMT_60958_2_BASE_IDX 2 |
|---|
| 7970 | #define regAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080 |
|---|
| 7971 | #define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 |
|---|
| 7972 | #define regAFMT0_AFMT_STATUS 0x2081 |
|---|
| 7973 | #define regAFMT0_AFMT_STATUS_BASE_IDX 2 |
|---|
| 7974 | #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082 |
|---|
| 7975 | #define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 7976 | #define regAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083 |
|---|
| 7977 | #define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 |
|---|
| 7978 | #define regAFMT0_AFMT_INTERRUPT_STATUS 0x2084 |
|---|
| 7979 | #define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 |
|---|
| 7980 | #define regAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085 |
|---|
| 7981 | #define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 |
|---|
| 7982 | #define regAFMT0_AFMT_MEM_PWR 0x2087 |
|---|
| 7983 | #define regAFMT0_AFMT_MEM_PWR_BASE_IDX 2 |
|---|
| 7984 | |
|---|
| 7985 | |
|---|
| 7986 | // addressBlock: dce_dc_dio_dig0_dme_dme_dispdec |
|---|
| 7987 | // base address: 0x15544 |
|---|
| 7988 | #define regDME0_DME_CONTROL 0x2091 |
|---|
| 7989 | #define regDME0_DME_CONTROL_BASE_IDX 2 |
|---|
| 7990 | #define regDME0_DME_MEMORY_CONTROL 0x2092 |
|---|
| 7991 | #define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 |
|---|
| 7992 | |
|---|
| 7993 | |
|---|
| 7994 | |
|---|
| 7995 | // addressBlock: dce_dc_dio_dig0_dispdec |
|---|
| 7996 | // base address: 0x0 |
|---|
| 7997 | #define regDIG0_DIG_FE_CNTL 0x2093 |
|---|
| 7998 | #define regDIG0_DIG_FE_CNTL_BASE_IDX 2 |
|---|
| 7999 | #define regDIG0_DIG_FE_CLK_CNTL 0x2094 |
|---|
| 8000 | #define regDIG0_DIG_FE_CLK_CNTL_BASE_IDX 2 |
|---|
| 8001 | #define regDIG0_DIG_FE_EN_CNTL 0x2095 |
|---|
| 8002 | #define regDIG0_DIG_FE_EN_CNTL_BASE_IDX 2 |
|---|
| 8003 | #define regDIG0_DIG_OUTPUT_CRC_CNTL 0x2096 |
|---|
| 8004 | #define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 |
|---|
| 8005 | #define regDIG0_DIG_OUTPUT_CRC_RESULT 0x2097 |
|---|
| 8006 | #define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 |
|---|
| 8007 | #define regDIG0_DIG_CLOCK_PATTERN 0x2098 |
|---|
| 8008 | #define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 |
|---|
| 8009 | #define regDIG0_DIG_TEST_PATTERN 0x2099 |
|---|
| 8010 | #define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 |
|---|
| 8011 | #define regDIG0_DIG_RANDOM_PATTERN_SEED 0x209a |
|---|
| 8012 | #define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 |
|---|
| 8013 | #define regDIG0_DIG_FIFO_CTRL0 0x209b |
|---|
| 8014 | #define regDIG0_DIG_FIFO_CTRL0_BASE_IDX 2 |
|---|
| 8015 | #define regDIG0_DIG_FIFO_CTRL1 0x209c |
|---|
| 8016 | #define regDIG0_DIG_FIFO_CTRL1_BASE_IDX 2 |
|---|
| 8017 | #define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x209d |
|---|
| 8018 | #define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8019 | #define regDIG0_HDMI_CONTROL 0x209e |
|---|
| 8020 | #define regDIG0_HDMI_CONTROL_BASE_IDX 2 |
|---|
| 8021 | #define regDIG0_HDMI_STATUS 0x209f |
|---|
| 8022 | #define regDIG0_HDMI_STATUS_BASE_IDX 2 |
|---|
| 8023 | #define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x20a0 |
|---|
| 8024 | #define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8025 | #define regDIG0_HDMI_ACR_PACKET_CONTROL 0x20a1 |
|---|
| 8026 | #define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8027 | #define regDIG0_HDMI_VBI_PACKET_CONTROL 0x20a2 |
|---|
| 8028 | #define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8029 | #define regDIG0_HDMI_INFOFRAME_CONTROL0 0x20a3 |
|---|
| 8030 | #define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 |
|---|
| 8031 | #define regDIG0_HDMI_INFOFRAME_CONTROL1 0x20a4 |
|---|
| 8032 | #define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 |
|---|
| 8033 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x20a5 |
|---|
| 8034 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 |
|---|
| 8035 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x20a6 |
|---|
| 8036 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 |
|---|
| 8037 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x20a7 |
|---|
| 8038 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 |
|---|
| 8039 | #define regDIG0_HDMI_GC 0x20a8 |
|---|
| 8040 | #define regDIG0_HDMI_GC_BASE_IDX 2 |
|---|
| 8041 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x20a9 |
|---|
| 8042 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 |
|---|
| 8043 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x20aa |
|---|
| 8044 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 |
|---|
| 8045 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20ab |
|---|
| 8046 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 |
|---|
| 8047 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20ac |
|---|
| 8048 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 |
|---|
| 8049 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20ad |
|---|
| 8050 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 |
|---|
| 8051 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20ae |
|---|
| 8052 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 |
|---|
| 8053 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20af |
|---|
| 8054 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 |
|---|
| 8055 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20b0 |
|---|
| 8056 | #define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 |
|---|
| 8057 | #define regDIG0_HDMI_DB_CONTROL 0x20b1 |
|---|
| 8058 | #define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 |
|---|
| 8059 | #define regDIG0_HDMI_ACR_32_0 0x20b2 |
|---|
| 8060 | #define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 |
|---|
| 8061 | #define regDIG0_HDMI_ACR_32_1 0x20b3 |
|---|
| 8062 | #define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 |
|---|
| 8063 | #define regDIG0_HDMI_ACR_44_0 0x20b4 |
|---|
| 8064 | #define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 |
|---|
| 8065 | #define regDIG0_HDMI_ACR_44_1 0x20b5 |
|---|
| 8066 | #define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 |
|---|
| 8067 | #define regDIG0_HDMI_ACR_48_0 0x20b6 |
|---|
| 8068 | #define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 |
|---|
| 8069 | #define regDIG0_HDMI_ACR_48_1 0x20b7 |
|---|
| 8070 | #define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 |
|---|
| 8071 | #define regDIG0_HDMI_ACR_STATUS_0 0x20b8 |
|---|
| 8072 | #define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 |
|---|
| 8073 | #define regDIG0_HDMI_ACR_STATUS_1 0x20b9 |
|---|
| 8074 | #define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 |
|---|
| 8075 | #define regDIG0_AFMT_CNTL 0x20ba |
|---|
| 8076 | #define regDIG0_AFMT_CNTL_BASE_IDX 2 |
|---|
| 8077 | #define regDIG0_DIG_BE_CLK_CNTL 0x20bb |
|---|
| 8078 | #define regDIG0_DIG_BE_CLK_CNTL_BASE_IDX 2 |
|---|
| 8079 | #define regDIG0_DIG_BE_CNTL 0x20bc |
|---|
| 8080 | #define regDIG0_DIG_BE_CNTL_BASE_IDX 2 |
|---|
| 8081 | #define regDIG0_DIG_BE_EN_CNTL 0x20bd |
|---|
| 8082 | #define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 |
|---|
| 8083 | #define regDIG0_TMDS_CNTL 0x20e4 |
|---|
| 8084 | #define regDIG0_TMDS_CNTL_BASE_IDX 2 |
|---|
| 8085 | #define regDIG0_TMDS_CONTROL_CHAR 0x20e5 |
|---|
| 8086 | #define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 |
|---|
| 8087 | #define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20e6 |
|---|
| 8088 | #define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 |
|---|
| 8089 | #define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20e7 |
|---|
| 8090 | #define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 |
|---|
| 8091 | #define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20e8 |
|---|
| 8092 | #define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 |
|---|
| 8093 | #define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20e9 |
|---|
| 8094 | #define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 |
|---|
| 8095 | #define regDIG0_TMDS_CTL_BITS 0x20eb |
|---|
| 8096 | #define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 |
|---|
| 8097 | #define regDIG0_TMDS_DCBALANCER_CONTROL 0x20ec |
|---|
| 8098 | #define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 |
|---|
| 8099 | #define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20ed |
|---|
| 8100 | #define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 |
|---|
| 8101 | #define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20ee |
|---|
| 8102 | #define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 |
|---|
| 8103 | #define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20ef |
|---|
| 8104 | #define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 |
|---|
| 8105 | #define regDIG0_DIG_VERSION 0x20f1 |
|---|
| 8106 | #define regDIG0_DIG_VERSION_BASE_IDX 2 |
|---|
| 8107 | |
|---|
| 8108 | |
|---|
| 8109 | // addressBlock: dce_dc_dio_dp0_dispdec |
|---|
| 8110 | // base address: 0x0 |
|---|
| 8111 | #define regDP0_DP_LINK_CNTL 0x211e |
|---|
| 8112 | #define regDP0_DP_LINK_CNTL_BASE_IDX 2 |
|---|
| 8113 | #define regDP0_DP_PIXEL_FORMAT 0x211f |
|---|
| 8114 | #define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 |
|---|
| 8115 | #define regDP0_DP_MSA_COLORIMETRY 0x2120 |
|---|
| 8116 | #define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 |
|---|
| 8117 | #define regDP0_DP_CONFIG 0x2121 |
|---|
| 8118 | #define regDP0_DP_CONFIG_BASE_IDX 2 |
|---|
| 8119 | #define regDP0_DP_VID_STREAM_CNTL 0x2122 |
|---|
| 8120 | #define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 |
|---|
| 8121 | #define regDP0_DP_STEER_FIFO 0x2123 |
|---|
| 8122 | #define regDP0_DP_STEER_FIFO_BASE_IDX 2 |
|---|
| 8123 | #define regDP0_DP_MSA_MISC 0x2124 |
|---|
| 8124 | #define regDP0_DP_MSA_MISC_BASE_IDX 2 |
|---|
| 8125 | #define regDP0_DP_DPHY_INTERNAL_CTRL 0x2125 |
|---|
| 8126 | #define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
|---|
| 8127 | #define regDP0_DP_VID_TIMING 0x2126 |
|---|
| 8128 | #define regDP0_DP_VID_TIMING_BASE_IDX 2 |
|---|
| 8129 | #define regDP0_DP_VID_N 0x2127 |
|---|
| 8130 | #define regDP0_DP_VID_N_BASE_IDX 2 |
|---|
| 8131 | #define regDP0_DP_VID_M 0x2128 |
|---|
| 8132 | #define regDP0_DP_VID_M_BASE_IDX 2 |
|---|
| 8133 | #define regDP0_DP_LINK_FRAMING_CNTL 0x2129 |
|---|
| 8134 | #define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 |
|---|
| 8135 | #define regDP0_DP_HBR2_EYE_PATTERN 0x212a |
|---|
| 8136 | #define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 |
|---|
| 8137 | #define regDP0_DP_VID_MSA_VBID 0x212b |
|---|
| 8138 | #define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 |
|---|
| 8139 | #define regDP0_DP_VID_INTERRUPT_CNTL 0x212c |
|---|
| 8140 | #define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 |
|---|
| 8141 | #define regDP0_DP_DPHY_CNTL 0x212d |
|---|
| 8142 | #define regDP0_DP_DPHY_CNTL_BASE_IDX 2 |
|---|
| 8143 | #define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x212e |
|---|
| 8144 | #define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 |
|---|
| 8145 | #define regDP0_DP_DPHY_SYM0 0x212f |
|---|
| 8146 | #define regDP0_DP_DPHY_SYM0_BASE_IDX 2 |
|---|
| 8147 | #define regDP0_DP_DPHY_SYM1 0x2130 |
|---|
| 8148 | #define regDP0_DP_DPHY_SYM1_BASE_IDX 2 |
|---|
| 8149 | #define regDP0_DP_DPHY_SYM2 0x2131 |
|---|
| 8150 | #define regDP0_DP_DPHY_SYM2_BASE_IDX 2 |
|---|
| 8151 | #define regDP0_DP_DPHY_8B10B_CNTL 0x2132 |
|---|
| 8152 | #define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 |
|---|
| 8153 | #define regDP0_DP_DPHY_PRBS_CNTL 0x2133 |
|---|
| 8154 | #define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 |
|---|
| 8155 | #define regDP0_DP_DPHY_SCRAM_CNTL 0x2134 |
|---|
| 8156 | #define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 |
|---|
| 8157 | #define regDP0_DP_DPHY_CRC_EN 0x2135 |
|---|
| 8158 | #define regDP0_DP_DPHY_CRC_EN_BASE_IDX 2 |
|---|
| 8159 | #define regDP0_DP_DPHY_CRC_CNTL 0x2136 |
|---|
| 8160 | #define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 |
|---|
| 8161 | #define regDP0_DP_DPHY_CRC_RESULT 0x2137 |
|---|
| 8162 | #define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 |
|---|
| 8163 | #define regDP0_DP_DPHY_CRC_MST_CNTL 0x2138 |
|---|
| 8164 | #define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 |
|---|
| 8165 | #define regDP0_DP_DPHY_CRC_MST_STATUS 0x2139 |
|---|
| 8166 | #define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 |
|---|
| 8167 | #define regDP0_DP_DPHY_FAST_TRAINING 0x213a |
|---|
| 8168 | #define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 |
|---|
| 8169 | #define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x213b |
|---|
| 8170 | #define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 |
|---|
| 8171 | #define regDP0_DP_SEC_CNTL 0x2141 |
|---|
| 8172 | #define regDP0_DP_SEC_CNTL_BASE_IDX 2 |
|---|
| 8173 | #define regDP0_DP_SEC_CNTL1 0x2142 |
|---|
| 8174 | #define regDP0_DP_SEC_CNTL1_BASE_IDX 2 |
|---|
| 8175 | #define regDP0_DP_SEC_FRAMING1 0x2143 |
|---|
| 8176 | #define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 |
|---|
| 8177 | #define regDP0_DP_SEC_FRAMING2 0x2144 |
|---|
| 8178 | #define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 |
|---|
| 8179 | #define regDP0_DP_SEC_FRAMING3 0x2145 |
|---|
| 8180 | #define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 |
|---|
| 8181 | #define regDP0_DP_SEC_FRAMING4 0x2146 |
|---|
| 8182 | #define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 |
|---|
| 8183 | #define regDP0_DP_SEC_AUD_N 0x2147 |
|---|
| 8184 | #define regDP0_DP_SEC_AUD_N_BASE_IDX 2 |
|---|
| 8185 | #define regDP0_DP_SEC_AUD_N_READBACK 0x2148 |
|---|
| 8186 | #define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 |
|---|
| 8187 | #define regDP0_DP_SEC_AUD_M 0x2149 |
|---|
| 8188 | #define regDP0_DP_SEC_AUD_M_BASE_IDX 2 |
|---|
| 8189 | #define regDP0_DP_SEC_AUD_M_READBACK 0x214a |
|---|
| 8190 | #define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 |
|---|
| 8191 | #define regDP0_DP_SEC_TIMESTAMP 0x214b |
|---|
| 8192 | #define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 |
|---|
| 8193 | #define regDP0_DP_SEC_PACKET_CNTL 0x214c |
|---|
| 8194 | #define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 |
|---|
| 8195 | #define regDP0_DP_MSE_RATE_CNTL 0x214d |
|---|
| 8196 | #define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 |
|---|
| 8197 | #define regDP0_DP_MSE_RATE_UPDATE 0x214f |
|---|
| 8198 | #define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 |
|---|
| 8199 | #define regDP0_DP_MSE_SAT0 0x2150 |
|---|
| 8200 | #define regDP0_DP_MSE_SAT0_BASE_IDX 2 |
|---|
| 8201 | #define regDP0_DP_MSE_SAT1 0x2151 |
|---|
| 8202 | #define regDP0_DP_MSE_SAT1_BASE_IDX 2 |
|---|
| 8203 | #define regDP0_DP_MSE_SAT2 0x2152 |
|---|
| 8204 | #define regDP0_DP_MSE_SAT2_BASE_IDX 2 |
|---|
| 8205 | #define regDP0_DP_MSE_SAT_UPDATE 0x2153 |
|---|
| 8206 | #define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 |
|---|
| 8207 | #define regDP0_DP_MSE_LINK_TIMING 0x2154 |
|---|
| 8208 | #define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 |
|---|
| 8209 | #define regDP0_DP_MSE_MISC_CNTL 0x2155 |
|---|
| 8210 | #define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 |
|---|
| 8211 | #define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x215a |
|---|
| 8212 | #define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 |
|---|
| 8213 | #define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x215b |
|---|
| 8214 | #define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 |
|---|
| 8215 | #define regDP0_DP_MSE_SAT0_STATUS 0x215d |
|---|
| 8216 | #define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 |
|---|
| 8217 | #define regDP0_DP_MSE_SAT1_STATUS 0x215e |
|---|
| 8218 | #define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 |
|---|
| 8219 | #define regDP0_DP_MSE_SAT2_STATUS 0x215f |
|---|
| 8220 | #define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 |
|---|
| 8221 | #define regDP0_DP_DPIA_SPARE 0x2160 |
|---|
| 8222 | #define regDP0_DP_DPIA_SPARE_BASE_IDX 2 |
|---|
| 8223 | #define regDP0_DP_MSA_TIMING_PARAM1 0x2162 |
|---|
| 8224 | #define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 |
|---|
| 8225 | #define regDP0_DP_MSA_TIMING_PARAM2 0x2163 |
|---|
| 8226 | #define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 |
|---|
| 8227 | #define regDP0_DP_MSA_TIMING_PARAM3 0x2164 |
|---|
| 8228 | #define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 |
|---|
| 8229 | #define regDP0_DP_MSA_TIMING_PARAM4 0x2165 |
|---|
| 8230 | #define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 |
|---|
| 8231 | #define regDP0_DP_MSO_CNTL 0x2166 |
|---|
| 8232 | #define regDP0_DP_MSO_CNTL_BASE_IDX 2 |
|---|
| 8233 | #define regDP0_DP_MSO_CNTL1 0x2167 |
|---|
| 8234 | #define regDP0_DP_MSO_CNTL1_BASE_IDX 2 |
|---|
| 8235 | #define regDP0_DP_DSC_CNTL 0x2168 |
|---|
| 8236 | #define regDP0_DP_DSC_CNTL_BASE_IDX 2 |
|---|
| 8237 | #define regDP0_DP_SEC_CNTL2 0x2169 |
|---|
| 8238 | #define regDP0_DP_SEC_CNTL2_BASE_IDX 2 |
|---|
| 8239 | #define regDP0_DP_SEC_CNTL3 0x216a |
|---|
| 8240 | #define regDP0_DP_SEC_CNTL3_BASE_IDX 2 |
|---|
| 8241 | #define regDP0_DP_SEC_CNTL4 0x216b |
|---|
| 8242 | #define regDP0_DP_SEC_CNTL4_BASE_IDX 2 |
|---|
| 8243 | #define regDP0_DP_SEC_CNTL5 0x216c |
|---|
| 8244 | #define regDP0_DP_SEC_CNTL5_BASE_IDX 2 |
|---|
| 8245 | #define regDP0_DP_SEC_CNTL6 0x216d |
|---|
| 8246 | #define regDP0_DP_SEC_CNTL6_BASE_IDX 2 |
|---|
| 8247 | #define regDP0_DP_SEC_CNTL7 0x216e |
|---|
| 8248 | #define regDP0_DP_SEC_CNTL7_BASE_IDX 2 |
|---|
| 8249 | #define regDP0_DP_DB_CNTL 0x216f |
|---|
| 8250 | #define regDP0_DP_DB_CNTL_BASE_IDX 2 |
|---|
| 8251 | #define regDP0_DP_MSA_VBID_MISC 0x2170 |
|---|
| 8252 | #define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 |
|---|
| 8253 | #define regDP0_DP_SEC_METADATA_TRANSMISSION 0x2171 |
|---|
| 8254 | #define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 |
|---|
| 8255 | #define regDP0_DP_ALPM_CNTL 0x2173 |
|---|
| 8256 | #define regDP0_DP_ALPM_CNTL_BASE_IDX 2 |
|---|
| 8257 | #define regDP0_DP_GSP8_CNTL 0x2174 |
|---|
| 8258 | #define regDP0_DP_GSP8_CNTL_BASE_IDX 2 |
|---|
| 8259 | #define regDP0_DP_GSP9_CNTL 0x2175 |
|---|
| 8260 | #define regDP0_DP_GSP9_CNTL_BASE_IDX 2 |
|---|
| 8261 | #define regDP0_DP_GSP10_CNTL 0x2176 |
|---|
| 8262 | #define regDP0_DP_GSP10_CNTL_BASE_IDX 2 |
|---|
| 8263 | #define regDP0_DP_GSP11_CNTL 0x2177 |
|---|
| 8264 | #define regDP0_DP_GSP11_CNTL_BASE_IDX 2 |
|---|
| 8265 | #define regDP0_DP_GSP_EN_DB_STATUS 0x2178 |
|---|
| 8266 | #define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 |
|---|
| 8267 | #define regDP0_DP_AUXLESS_ALPM_CNTL1 0x2179 |
|---|
| 8268 | #define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 |
|---|
| 8269 | #define regDP0_DP_AUXLESS_ALPM_CNTL2 0x217a |
|---|
| 8270 | #define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 |
|---|
| 8271 | #define regDP0_DP_AUXLESS_ALPM_CNTL3 0x217b |
|---|
| 8272 | #define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 |
|---|
| 8273 | #define regDP0_DP_AUXLESS_ALPM_CNTL4 0x217c |
|---|
| 8274 | #define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 |
|---|
| 8275 | #define regDP0_DP_AUXLESS_ALPM_CNTL5 0x217d |
|---|
| 8276 | #define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 |
|---|
| 8277 | #define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS 0x217e |
|---|
| 8278 | #define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 |
|---|
| 8279 | #define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL 0x217f |
|---|
| 8280 | #define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 8281 | #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0 0x2180 |
|---|
| 8282 | #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 |
|---|
| 8283 | #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1 0x2181 |
|---|
| 8284 | #define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 |
|---|
| 8285 | #define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL 0x2182 |
|---|
| 8286 | #define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 8287 | |
|---|
| 8288 | |
|---|
| 8289 | // addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec |
|---|
| 8290 | // base address: 0x15930 |
|---|
| 8291 | #define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x218c |
|---|
| 8292 | #define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 8293 | #define regVPG1_VPG_GENERIC_PACKET_DATA 0x218d |
|---|
| 8294 | #define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
|---|
| 8295 | #define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x218e |
|---|
| 8296 | #define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 8297 | #define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x218f |
|---|
| 8298 | #define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 8299 | #define regVPG1_VPG_GENERIC_STATUS 0x2190 |
|---|
| 8300 | #define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 |
|---|
| 8301 | #define regVPG1_VPG_MEM_PWR 0x2191 |
|---|
| 8302 | #define regVPG1_VPG_MEM_PWR_BASE_IDX 2 |
|---|
| 8303 | #define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x2192 |
|---|
| 8304 | #define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 8305 | #define regVPG1_VPG_ISRC1_2_DATA 0x2193 |
|---|
| 8306 | #define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 |
|---|
| 8307 | #define regVPG1_VPG_MPEG_INFO0 0x2194 |
|---|
| 8308 | #define regVPG1_VPG_MPEG_INFO0_BASE_IDX 2 |
|---|
| 8309 | #define regVPG1_VPG_MPEG_INFO1 0x2195 |
|---|
| 8310 | #define regVPG1_VPG_MPEG_INFO1_BASE_IDX 2 |
|---|
| 8311 | |
|---|
| 8312 | |
|---|
| 8313 | // addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec |
|---|
| 8314 | // base address: 0x1595c |
|---|
| 8315 | #define regAFMT1_AFMT_ACP 0x2197 |
|---|
| 8316 | #define regAFMT1_AFMT_ACP_BASE_IDX 2 |
|---|
| 8317 | #define regAFMT1_AFMT_VBI_PACKET_CONTROL 0x2198 |
|---|
| 8318 | #define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8319 | #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2199 |
|---|
| 8320 | #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 |
|---|
| 8321 | #define regAFMT1_AFMT_AUDIO_INFO0 0x219a |
|---|
| 8322 | #define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2 |
|---|
| 8323 | #define regAFMT1_AFMT_AUDIO_INFO1 0x219b |
|---|
| 8324 | #define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2 |
|---|
| 8325 | #define regAFMT1_AFMT_60958_0 0x219c |
|---|
| 8326 | #define regAFMT1_AFMT_60958_0_BASE_IDX 2 |
|---|
| 8327 | #define regAFMT1_AFMT_60958_1 0x219d |
|---|
| 8328 | #define regAFMT1_AFMT_60958_1_BASE_IDX 2 |
|---|
| 8329 | #define regAFMT1_AFMT_AUDIO_CRC_CONTROL 0x219e |
|---|
| 8330 | #define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 |
|---|
| 8331 | #define regAFMT1_AFMT_RAMP_CONTROL0 0x219f |
|---|
| 8332 | #define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2 |
|---|
| 8333 | #define regAFMT1_AFMT_RAMP_CONTROL1 0x21a0 |
|---|
| 8334 | #define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2 |
|---|
| 8335 | #define regAFMT1_AFMT_RAMP_CONTROL2 0x21a1 |
|---|
| 8336 | #define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2 |
|---|
| 8337 | #define regAFMT1_AFMT_RAMP_CONTROL3 0x21a2 |
|---|
| 8338 | #define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2 |
|---|
| 8339 | #define regAFMT1_AFMT_60958_2 0x21a3 |
|---|
| 8340 | #define regAFMT1_AFMT_60958_2_BASE_IDX 2 |
|---|
| 8341 | #define regAFMT1_AFMT_AUDIO_CRC_RESULT 0x21a4 |
|---|
| 8342 | #define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 |
|---|
| 8343 | #define regAFMT1_AFMT_STATUS 0x21a5 |
|---|
| 8344 | #define regAFMT1_AFMT_STATUS_BASE_IDX 2 |
|---|
| 8345 | #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x21a6 |
|---|
| 8346 | #define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8347 | #define regAFMT1_AFMT_INFOFRAME_CONTROL0 0x21a7 |
|---|
| 8348 | #define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 |
|---|
| 8349 | #define regAFMT1_AFMT_INTERRUPT_STATUS 0x21a8 |
|---|
| 8350 | #define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 |
|---|
| 8351 | #define regAFMT1_AFMT_AUDIO_SRC_CONTROL 0x21a9 |
|---|
| 8352 | #define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 |
|---|
| 8353 | #define regAFMT1_AFMT_MEM_PWR 0x21ab |
|---|
| 8354 | #define regAFMT1_AFMT_MEM_PWR_BASE_IDX 2 |
|---|
| 8355 | |
|---|
| 8356 | |
|---|
| 8357 | // addressBlock: dce_dc_dio_dig1_dme_dme_dispdec |
|---|
| 8358 | // base address: 0x159d4 |
|---|
| 8359 | #define regDME1_DME_CONTROL 0x21b5 |
|---|
| 8360 | #define regDME1_DME_CONTROL_BASE_IDX 2 |
|---|
| 8361 | #define regDME1_DME_MEMORY_CONTROL 0x21b6 |
|---|
| 8362 | #define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 |
|---|
| 8363 | |
|---|
| 8364 | |
|---|
| 8365 | // addressBlock: dce_dc_dio_dig1_dispdec |
|---|
| 8366 | // base address: 0x490 |
|---|
| 8367 | #define regDIG1_DIG_FE_CNTL 0x21b7 |
|---|
| 8368 | #define regDIG1_DIG_FE_CNTL_BASE_IDX 2 |
|---|
| 8369 | #define regDIG1_DIG_FE_CLK_CNTL 0x21b8 |
|---|
| 8370 | #define regDIG1_DIG_FE_CLK_CNTL_BASE_IDX 2 |
|---|
| 8371 | #define regDIG1_DIG_FE_EN_CNTL 0x21b9 |
|---|
| 8372 | #define regDIG1_DIG_FE_EN_CNTL_BASE_IDX 2 |
|---|
| 8373 | #define regDIG1_DIG_OUTPUT_CRC_CNTL 0x21ba |
|---|
| 8374 | #define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 |
|---|
| 8375 | #define regDIG1_DIG_OUTPUT_CRC_RESULT 0x21bb |
|---|
| 8376 | #define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 |
|---|
| 8377 | #define regDIG1_DIG_CLOCK_PATTERN 0x21bc |
|---|
| 8378 | #define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 |
|---|
| 8379 | #define regDIG1_DIG_TEST_PATTERN 0x21bd |
|---|
| 8380 | #define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 |
|---|
| 8381 | #define regDIG1_DIG_RANDOM_PATTERN_SEED 0x21be |
|---|
| 8382 | #define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 |
|---|
| 8383 | #define regDIG1_DIG_FIFO_CTRL0 0x21bf |
|---|
| 8384 | #define regDIG1_DIG_FIFO_CTRL0_BASE_IDX 2 |
|---|
| 8385 | #define regDIG1_DIG_FIFO_CTRL1 0x21c0 |
|---|
| 8386 | #define regDIG1_DIG_FIFO_CTRL1_BASE_IDX 2 |
|---|
| 8387 | #define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x21c1 |
|---|
| 8388 | #define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8389 | #define regDIG1_HDMI_CONTROL 0x21c2 |
|---|
| 8390 | #define regDIG1_HDMI_CONTROL_BASE_IDX 2 |
|---|
| 8391 | #define regDIG1_HDMI_STATUS 0x21c3 |
|---|
| 8392 | #define regDIG1_HDMI_STATUS_BASE_IDX 2 |
|---|
| 8393 | #define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x21c4 |
|---|
| 8394 | #define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8395 | #define regDIG1_HDMI_ACR_PACKET_CONTROL 0x21c5 |
|---|
| 8396 | #define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8397 | #define regDIG1_HDMI_VBI_PACKET_CONTROL 0x21c6 |
|---|
| 8398 | #define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8399 | #define regDIG1_HDMI_INFOFRAME_CONTROL0 0x21c7 |
|---|
| 8400 | #define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 |
|---|
| 8401 | #define regDIG1_HDMI_INFOFRAME_CONTROL1 0x21c8 |
|---|
| 8402 | #define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 |
|---|
| 8403 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x21c9 |
|---|
| 8404 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 |
|---|
| 8405 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x21ca |
|---|
| 8406 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 |
|---|
| 8407 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x21cb |
|---|
| 8408 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 |
|---|
| 8409 | #define regDIG1_HDMI_GC 0x21cc |
|---|
| 8410 | #define regDIG1_HDMI_GC_BASE_IDX 2 |
|---|
| 8411 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x21cd |
|---|
| 8412 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 |
|---|
| 8413 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x21ce |
|---|
| 8414 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 |
|---|
| 8415 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21cf |
|---|
| 8416 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 |
|---|
| 8417 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21d0 |
|---|
| 8418 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 |
|---|
| 8419 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21d1 |
|---|
| 8420 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 |
|---|
| 8421 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21d2 |
|---|
| 8422 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 |
|---|
| 8423 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21d3 |
|---|
| 8424 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 |
|---|
| 8425 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21d4 |
|---|
| 8426 | #define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 |
|---|
| 8427 | #define regDIG1_HDMI_DB_CONTROL 0x21d5 |
|---|
| 8428 | #define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 |
|---|
| 8429 | #define regDIG1_HDMI_ACR_32_0 0x21d6 |
|---|
| 8430 | #define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 |
|---|
| 8431 | #define regDIG1_HDMI_ACR_32_1 0x21d7 |
|---|
| 8432 | #define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 |
|---|
| 8433 | #define regDIG1_HDMI_ACR_44_0 0x21d8 |
|---|
| 8434 | #define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 |
|---|
| 8435 | #define regDIG1_HDMI_ACR_44_1 0x21d9 |
|---|
| 8436 | #define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 |
|---|
| 8437 | #define regDIG1_HDMI_ACR_48_0 0x21da |
|---|
| 8438 | #define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 |
|---|
| 8439 | #define regDIG1_HDMI_ACR_48_1 0x21db |
|---|
| 8440 | #define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 |
|---|
| 8441 | #define regDIG1_HDMI_ACR_STATUS_0 0x21dc |
|---|
| 8442 | #define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 |
|---|
| 8443 | #define regDIG1_HDMI_ACR_STATUS_1 0x21dd |
|---|
| 8444 | #define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 |
|---|
| 8445 | #define regDIG1_AFMT_CNTL 0x21de |
|---|
| 8446 | #define regDIG1_AFMT_CNTL_BASE_IDX 2 |
|---|
| 8447 | #define regDIG1_DIG_BE_CLK_CNTL 0x21df |
|---|
| 8448 | #define regDIG1_DIG_BE_CLK_CNTL_BASE_IDX 2 |
|---|
| 8449 | #define regDIG1_DIG_BE_CNTL 0x21e0 |
|---|
| 8450 | #define regDIG1_DIG_BE_CNTL_BASE_IDX 2 |
|---|
| 8451 | #define regDIG1_DIG_BE_EN_CNTL 0x21e1 |
|---|
| 8452 | #define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 |
|---|
| 8453 | #define regDIG1_TMDS_CNTL 0x2208 |
|---|
| 8454 | #define regDIG1_TMDS_CNTL_BASE_IDX 2 |
|---|
| 8455 | #define regDIG1_TMDS_CONTROL_CHAR 0x2209 |
|---|
| 8456 | #define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 |
|---|
| 8457 | #define regDIG1_TMDS_CONTROL0_FEEDBACK 0x220a |
|---|
| 8458 | #define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 |
|---|
| 8459 | #define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x220b |
|---|
| 8460 | #define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 |
|---|
| 8461 | #define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x220c |
|---|
| 8462 | #define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 |
|---|
| 8463 | #define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x220d |
|---|
| 8464 | #define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 |
|---|
| 8465 | #define regDIG1_TMDS_CTL_BITS 0x220f |
|---|
| 8466 | #define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 |
|---|
| 8467 | #define regDIG1_TMDS_DCBALANCER_CONTROL 0x2210 |
|---|
| 8468 | #define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 |
|---|
| 8469 | #define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x2211 |
|---|
| 8470 | #define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 |
|---|
| 8471 | #define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x2212 |
|---|
| 8472 | #define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 |
|---|
| 8473 | #define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x2213 |
|---|
| 8474 | #define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 |
|---|
| 8475 | #define regDIG1_DIG_VERSION 0x2215 |
|---|
| 8476 | #define regDIG1_DIG_VERSION_BASE_IDX 2 |
|---|
| 8477 | |
|---|
| 8478 | |
|---|
| 8479 | // addressBlock: dce_dc_dio_dp1_dispdec |
|---|
| 8480 | // base address: 0x490 |
|---|
| 8481 | #define regDP1_DP_LINK_CNTL 0x2242 |
|---|
| 8482 | #define regDP1_DP_LINK_CNTL_BASE_IDX 2 |
|---|
| 8483 | #define regDP1_DP_PIXEL_FORMAT 0x2243 |
|---|
| 8484 | #define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 |
|---|
| 8485 | #define regDP1_DP_MSA_COLORIMETRY 0x2244 |
|---|
| 8486 | #define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 |
|---|
| 8487 | #define regDP1_DP_CONFIG 0x2245 |
|---|
| 8488 | #define regDP1_DP_CONFIG_BASE_IDX 2 |
|---|
| 8489 | #define regDP1_DP_VID_STREAM_CNTL 0x2246 |
|---|
| 8490 | #define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 |
|---|
| 8491 | #define regDP1_DP_STEER_FIFO 0x2247 |
|---|
| 8492 | #define regDP1_DP_STEER_FIFO_BASE_IDX 2 |
|---|
| 8493 | #define regDP1_DP_MSA_MISC 0x2248 |
|---|
| 8494 | #define regDP1_DP_MSA_MISC_BASE_IDX 2 |
|---|
| 8495 | #define regDP1_DP_DPHY_INTERNAL_CTRL 0x2249 |
|---|
| 8496 | #define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
|---|
| 8497 | #define regDP1_DP_VID_TIMING 0x224a |
|---|
| 8498 | #define regDP1_DP_VID_TIMING_BASE_IDX 2 |
|---|
| 8499 | #define regDP1_DP_VID_N 0x224b |
|---|
| 8500 | #define regDP1_DP_VID_N_BASE_IDX 2 |
|---|
| 8501 | #define regDP1_DP_VID_M 0x224c |
|---|
| 8502 | #define regDP1_DP_VID_M_BASE_IDX 2 |
|---|
| 8503 | #define regDP1_DP_LINK_FRAMING_CNTL 0x224d |
|---|
| 8504 | #define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 |
|---|
| 8505 | #define regDP1_DP_HBR2_EYE_PATTERN 0x224e |
|---|
| 8506 | #define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 |
|---|
| 8507 | #define regDP1_DP_VID_MSA_VBID 0x224f |
|---|
| 8508 | #define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 |
|---|
| 8509 | #define regDP1_DP_VID_INTERRUPT_CNTL 0x2250 |
|---|
| 8510 | #define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 |
|---|
| 8511 | #define regDP1_DP_DPHY_CNTL 0x2251 |
|---|
| 8512 | #define regDP1_DP_DPHY_CNTL_BASE_IDX 2 |
|---|
| 8513 | #define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2252 |
|---|
| 8514 | #define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 |
|---|
| 8515 | #define regDP1_DP_DPHY_SYM0 0x2253 |
|---|
| 8516 | #define regDP1_DP_DPHY_SYM0_BASE_IDX 2 |
|---|
| 8517 | #define regDP1_DP_DPHY_SYM1 0x2254 |
|---|
| 8518 | #define regDP1_DP_DPHY_SYM1_BASE_IDX 2 |
|---|
| 8519 | #define regDP1_DP_DPHY_SYM2 0x2255 |
|---|
| 8520 | #define regDP1_DP_DPHY_SYM2_BASE_IDX 2 |
|---|
| 8521 | #define regDP1_DP_DPHY_8B10B_CNTL 0x2256 |
|---|
| 8522 | #define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 |
|---|
| 8523 | #define regDP1_DP_DPHY_PRBS_CNTL 0x2257 |
|---|
| 8524 | #define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 |
|---|
| 8525 | #define regDP1_DP_DPHY_SCRAM_CNTL 0x2258 |
|---|
| 8526 | #define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 |
|---|
| 8527 | #define regDP1_DP_DPHY_CRC_EN 0x2259 |
|---|
| 8528 | #define regDP1_DP_DPHY_CRC_EN_BASE_IDX 2 |
|---|
| 8529 | #define regDP1_DP_DPHY_CRC_CNTL 0x225a |
|---|
| 8530 | #define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 |
|---|
| 8531 | #define regDP1_DP_DPHY_CRC_RESULT 0x225b |
|---|
| 8532 | #define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 |
|---|
| 8533 | #define regDP1_DP_DPHY_CRC_MST_CNTL 0x225c |
|---|
| 8534 | #define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 |
|---|
| 8535 | #define regDP1_DP_DPHY_CRC_MST_STATUS 0x225d |
|---|
| 8536 | #define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 |
|---|
| 8537 | #define regDP1_DP_DPHY_FAST_TRAINING 0x225e |
|---|
| 8538 | #define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 |
|---|
| 8539 | #define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x225f |
|---|
| 8540 | #define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 |
|---|
| 8541 | #define regDP1_DP_SEC_CNTL 0x2265 |
|---|
| 8542 | #define regDP1_DP_SEC_CNTL_BASE_IDX 2 |
|---|
| 8543 | #define regDP1_DP_SEC_CNTL1 0x2266 |
|---|
| 8544 | #define regDP1_DP_SEC_CNTL1_BASE_IDX 2 |
|---|
| 8545 | #define regDP1_DP_SEC_FRAMING1 0x2267 |
|---|
| 8546 | #define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 |
|---|
| 8547 | #define regDP1_DP_SEC_FRAMING2 0x2268 |
|---|
| 8548 | #define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 |
|---|
| 8549 | #define regDP1_DP_SEC_FRAMING3 0x2269 |
|---|
| 8550 | #define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 |
|---|
| 8551 | #define regDP1_DP_SEC_FRAMING4 0x226a |
|---|
| 8552 | #define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 |
|---|
| 8553 | #define regDP1_DP_SEC_AUD_N 0x226b |
|---|
| 8554 | #define regDP1_DP_SEC_AUD_N_BASE_IDX 2 |
|---|
| 8555 | #define regDP1_DP_SEC_AUD_N_READBACK 0x226c |
|---|
| 8556 | #define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 |
|---|
| 8557 | #define regDP1_DP_SEC_AUD_M 0x226d |
|---|
| 8558 | #define regDP1_DP_SEC_AUD_M_BASE_IDX 2 |
|---|
| 8559 | #define regDP1_DP_SEC_AUD_M_READBACK 0x226e |
|---|
| 8560 | #define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 |
|---|
| 8561 | #define regDP1_DP_SEC_TIMESTAMP 0x226f |
|---|
| 8562 | #define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 |
|---|
| 8563 | #define regDP1_DP_SEC_PACKET_CNTL 0x2270 |
|---|
| 8564 | #define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 |
|---|
| 8565 | #define regDP1_DP_MSE_RATE_CNTL 0x2271 |
|---|
| 8566 | #define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 |
|---|
| 8567 | #define regDP1_DP_MSE_RATE_UPDATE 0x2273 |
|---|
| 8568 | #define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 |
|---|
| 8569 | #define regDP1_DP_MSE_SAT0 0x2274 |
|---|
| 8570 | #define regDP1_DP_MSE_SAT0_BASE_IDX 2 |
|---|
| 8571 | #define regDP1_DP_MSE_SAT1 0x2275 |
|---|
| 8572 | #define regDP1_DP_MSE_SAT1_BASE_IDX 2 |
|---|
| 8573 | #define regDP1_DP_MSE_SAT2 0x2276 |
|---|
| 8574 | #define regDP1_DP_MSE_SAT2_BASE_IDX 2 |
|---|
| 8575 | #define regDP1_DP_MSE_SAT_UPDATE 0x2277 |
|---|
| 8576 | #define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 |
|---|
| 8577 | #define regDP1_DP_MSE_LINK_TIMING 0x2278 |
|---|
| 8578 | #define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 |
|---|
| 8579 | #define regDP1_DP_MSE_MISC_CNTL 0x2279 |
|---|
| 8580 | #define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 |
|---|
| 8581 | #define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x227e |
|---|
| 8582 | #define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 |
|---|
| 8583 | #define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x227f |
|---|
| 8584 | #define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 |
|---|
| 8585 | #define regDP1_DP_MSE_SAT0_STATUS 0x2281 |
|---|
| 8586 | #define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 |
|---|
| 8587 | #define regDP1_DP_MSE_SAT1_STATUS 0x2282 |
|---|
| 8588 | #define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 |
|---|
| 8589 | #define regDP1_DP_MSE_SAT2_STATUS 0x2283 |
|---|
| 8590 | #define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 |
|---|
| 8591 | #define regDP1_DP_DPIA_SPARE 0x2284 |
|---|
| 8592 | #define regDP1_DP_DPIA_SPARE_BASE_IDX 2 |
|---|
| 8593 | #define regDP1_DP_MSA_TIMING_PARAM1 0x2286 |
|---|
| 8594 | #define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 |
|---|
| 8595 | #define regDP1_DP_MSA_TIMING_PARAM2 0x2287 |
|---|
| 8596 | #define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 |
|---|
| 8597 | #define regDP1_DP_MSA_TIMING_PARAM3 0x2288 |
|---|
| 8598 | #define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 |
|---|
| 8599 | #define regDP1_DP_MSA_TIMING_PARAM4 0x2289 |
|---|
| 8600 | #define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 |
|---|
| 8601 | #define regDP1_DP_MSO_CNTL 0x228a |
|---|
| 8602 | #define regDP1_DP_MSO_CNTL_BASE_IDX 2 |
|---|
| 8603 | #define regDP1_DP_MSO_CNTL1 0x228b |
|---|
| 8604 | #define regDP1_DP_MSO_CNTL1_BASE_IDX 2 |
|---|
| 8605 | #define regDP1_DP_DSC_CNTL 0x228c |
|---|
| 8606 | #define regDP1_DP_DSC_CNTL_BASE_IDX 2 |
|---|
| 8607 | #define regDP1_DP_SEC_CNTL2 0x228d |
|---|
| 8608 | #define regDP1_DP_SEC_CNTL2_BASE_IDX 2 |
|---|
| 8609 | #define regDP1_DP_SEC_CNTL3 0x228e |
|---|
| 8610 | #define regDP1_DP_SEC_CNTL3_BASE_IDX 2 |
|---|
| 8611 | #define regDP1_DP_SEC_CNTL4 0x228f |
|---|
| 8612 | #define regDP1_DP_SEC_CNTL4_BASE_IDX 2 |
|---|
| 8613 | #define regDP1_DP_SEC_CNTL5 0x2290 |
|---|
| 8614 | #define regDP1_DP_SEC_CNTL5_BASE_IDX 2 |
|---|
| 8615 | #define regDP1_DP_SEC_CNTL6 0x2291 |
|---|
| 8616 | #define regDP1_DP_SEC_CNTL6_BASE_IDX 2 |
|---|
| 8617 | #define regDP1_DP_SEC_CNTL7 0x2292 |
|---|
| 8618 | #define regDP1_DP_SEC_CNTL7_BASE_IDX 2 |
|---|
| 8619 | #define regDP1_DP_DB_CNTL 0x2293 |
|---|
| 8620 | #define regDP1_DP_DB_CNTL_BASE_IDX 2 |
|---|
| 8621 | #define regDP1_DP_MSA_VBID_MISC 0x2294 |
|---|
| 8622 | #define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 |
|---|
| 8623 | #define regDP1_DP_SEC_METADATA_TRANSMISSION 0x2295 |
|---|
| 8624 | #define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 |
|---|
| 8625 | #define regDP1_DP_ALPM_CNTL 0x2297 |
|---|
| 8626 | #define regDP1_DP_ALPM_CNTL_BASE_IDX 2 |
|---|
| 8627 | #define regDP1_DP_GSP8_CNTL 0x2298 |
|---|
| 8628 | #define regDP1_DP_GSP8_CNTL_BASE_IDX 2 |
|---|
| 8629 | #define regDP1_DP_GSP9_CNTL 0x2299 |
|---|
| 8630 | #define regDP1_DP_GSP9_CNTL_BASE_IDX 2 |
|---|
| 8631 | #define regDP1_DP_GSP10_CNTL 0x229a |
|---|
| 8632 | #define regDP1_DP_GSP10_CNTL_BASE_IDX 2 |
|---|
| 8633 | #define regDP1_DP_GSP11_CNTL 0x229b |
|---|
| 8634 | #define regDP1_DP_GSP11_CNTL_BASE_IDX 2 |
|---|
| 8635 | #define regDP1_DP_GSP_EN_DB_STATUS 0x229c |
|---|
| 8636 | #define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 |
|---|
| 8637 | #define regDP1_DP_AUXLESS_ALPM_CNTL1 0x229d |
|---|
| 8638 | #define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 |
|---|
| 8639 | #define regDP1_DP_AUXLESS_ALPM_CNTL2 0x229e |
|---|
| 8640 | #define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 |
|---|
| 8641 | #define regDP1_DP_AUXLESS_ALPM_CNTL3 0x229f |
|---|
| 8642 | #define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 |
|---|
| 8643 | #define regDP1_DP_AUXLESS_ALPM_CNTL4 0x22a0 |
|---|
| 8644 | #define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 |
|---|
| 8645 | #define regDP1_DP_AUXLESS_ALPM_CNTL5 0x22a1 |
|---|
| 8646 | #define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 |
|---|
| 8647 | #define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS 0x22a2 |
|---|
| 8648 | #define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 |
|---|
| 8649 | #define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL 0x22a3 |
|---|
| 8650 | #define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 8651 | #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0 0x22a4 |
|---|
| 8652 | #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 |
|---|
| 8653 | #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1 0x22a5 |
|---|
| 8654 | #define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 |
|---|
| 8655 | #define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL 0x22a6 |
|---|
| 8656 | #define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 8657 | |
|---|
| 8658 | |
|---|
| 8659 | // addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec |
|---|
| 8660 | // base address: 0x15dc0 |
|---|
| 8661 | #define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x22b0 |
|---|
| 8662 | #define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 8663 | #define regVPG2_VPG_GENERIC_PACKET_DATA 0x22b1 |
|---|
| 8664 | #define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
|---|
| 8665 | #define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x22b2 |
|---|
| 8666 | #define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 8667 | #define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x22b3 |
|---|
| 8668 | #define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 8669 | #define regVPG2_VPG_GENERIC_STATUS 0x22b4 |
|---|
| 8670 | #define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 |
|---|
| 8671 | #define regVPG2_VPG_MEM_PWR 0x22b5 |
|---|
| 8672 | #define regVPG2_VPG_MEM_PWR_BASE_IDX 2 |
|---|
| 8673 | #define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x22b6 |
|---|
| 8674 | #define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 8675 | #define regVPG2_VPG_ISRC1_2_DATA 0x22b7 |
|---|
| 8676 | #define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 |
|---|
| 8677 | #define regVPG2_VPG_MPEG_INFO0 0x22b8 |
|---|
| 8678 | #define regVPG2_VPG_MPEG_INFO0_BASE_IDX 2 |
|---|
| 8679 | #define regVPG2_VPG_MPEG_INFO1 0x22b9 |
|---|
| 8680 | #define regVPG2_VPG_MPEG_INFO1_BASE_IDX 2 |
|---|
| 8681 | |
|---|
| 8682 | |
|---|
| 8683 | // addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec |
|---|
| 8684 | // base address: 0x15dec |
|---|
| 8685 | #define regAFMT2_AFMT_ACP 0x22bb |
|---|
| 8686 | #define regAFMT2_AFMT_ACP_BASE_IDX 2 |
|---|
| 8687 | #define regAFMT2_AFMT_VBI_PACKET_CONTROL 0x22bc |
|---|
| 8688 | #define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8689 | #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x22bd |
|---|
| 8690 | #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 |
|---|
| 8691 | #define regAFMT2_AFMT_AUDIO_INFO0 0x22be |
|---|
| 8692 | #define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2 |
|---|
| 8693 | #define regAFMT2_AFMT_AUDIO_INFO1 0x22bf |
|---|
| 8694 | #define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2 |
|---|
| 8695 | #define regAFMT2_AFMT_60958_0 0x22c0 |
|---|
| 8696 | #define regAFMT2_AFMT_60958_0_BASE_IDX 2 |
|---|
| 8697 | #define regAFMT2_AFMT_60958_1 0x22c1 |
|---|
| 8698 | #define regAFMT2_AFMT_60958_1_BASE_IDX 2 |
|---|
| 8699 | #define regAFMT2_AFMT_AUDIO_CRC_CONTROL 0x22c2 |
|---|
| 8700 | #define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 |
|---|
| 8701 | #define regAFMT2_AFMT_RAMP_CONTROL0 0x22c3 |
|---|
| 8702 | #define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2 |
|---|
| 8703 | #define regAFMT2_AFMT_RAMP_CONTROL1 0x22c4 |
|---|
| 8704 | #define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2 |
|---|
| 8705 | #define regAFMT2_AFMT_RAMP_CONTROL2 0x22c5 |
|---|
| 8706 | #define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2 |
|---|
| 8707 | #define regAFMT2_AFMT_RAMP_CONTROL3 0x22c6 |
|---|
| 8708 | #define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2 |
|---|
| 8709 | #define regAFMT2_AFMT_60958_2 0x22c7 |
|---|
| 8710 | #define regAFMT2_AFMT_60958_2_BASE_IDX 2 |
|---|
| 8711 | #define regAFMT2_AFMT_AUDIO_CRC_RESULT 0x22c8 |
|---|
| 8712 | #define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 |
|---|
| 8713 | #define regAFMT2_AFMT_STATUS 0x22c9 |
|---|
| 8714 | #define regAFMT2_AFMT_STATUS_BASE_IDX 2 |
|---|
| 8715 | #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x22ca |
|---|
| 8716 | #define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8717 | #define regAFMT2_AFMT_INFOFRAME_CONTROL0 0x22cb |
|---|
| 8718 | #define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 |
|---|
| 8719 | #define regAFMT2_AFMT_INTERRUPT_STATUS 0x22cc |
|---|
| 8720 | #define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 |
|---|
| 8721 | #define regAFMT2_AFMT_AUDIO_SRC_CONTROL 0x22cd |
|---|
| 8722 | #define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 |
|---|
| 8723 | #define regAFMT2_AFMT_MEM_PWR 0x22cf |
|---|
| 8724 | #define regAFMT2_AFMT_MEM_PWR_BASE_IDX 2 |
|---|
| 8725 | |
|---|
| 8726 | |
|---|
| 8727 | // addressBlock: dce_dc_dio_dig2_dme_dme_dispdec |
|---|
| 8728 | // base address: 0x15e64 |
|---|
| 8729 | #define regDME2_DME_CONTROL 0x22d9 |
|---|
| 8730 | #define regDME2_DME_CONTROL_BASE_IDX 2 |
|---|
| 8731 | #define regDME2_DME_MEMORY_CONTROL 0x22da |
|---|
| 8732 | #define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 |
|---|
| 8733 | |
|---|
| 8734 | |
|---|
| 8735 | // addressBlock: dce_dc_dio_dig2_dispdec |
|---|
| 8736 | // base address: 0x920 |
|---|
| 8737 | #define regDIG2_DIG_FE_CNTL 0x22db |
|---|
| 8738 | #define regDIG2_DIG_FE_CNTL_BASE_IDX 2 |
|---|
| 8739 | #define regDIG2_DIG_FE_CLK_CNTL 0x22dc |
|---|
| 8740 | #define regDIG2_DIG_FE_CLK_CNTL_BASE_IDX 2 |
|---|
| 8741 | #define regDIG2_DIG_FE_EN_CNTL 0x22dd |
|---|
| 8742 | #define regDIG2_DIG_FE_EN_CNTL_BASE_IDX 2 |
|---|
| 8743 | #define regDIG2_DIG_OUTPUT_CRC_CNTL 0x22de |
|---|
| 8744 | #define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 |
|---|
| 8745 | #define regDIG2_DIG_OUTPUT_CRC_RESULT 0x22df |
|---|
| 8746 | #define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 |
|---|
| 8747 | #define regDIG2_DIG_CLOCK_PATTERN 0x22e0 |
|---|
| 8748 | #define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 |
|---|
| 8749 | #define regDIG2_DIG_TEST_PATTERN 0x22e1 |
|---|
| 8750 | #define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 |
|---|
| 8751 | #define regDIG2_DIG_RANDOM_PATTERN_SEED 0x22e2 |
|---|
| 8752 | #define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 |
|---|
| 8753 | #define regDIG2_DIG_FIFO_CTRL0 0x22e3 |
|---|
| 8754 | #define regDIG2_DIG_FIFO_CTRL0_BASE_IDX 2 |
|---|
| 8755 | #define regDIG2_DIG_FIFO_CTRL1 0x22e4 |
|---|
| 8756 | #define regDIG2_DIG_FIFO_CTRL1_BASE_IDX 2 |
|---|
| 8757 | #define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x22e5 |
|---|
| 8758 | #define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8759 | #define regDIG2_HDMI_CONTROL 0x22e6 |
|---|
| 8760 | #define regDIG2_HDMI_CONTROL_BASE_IDX 2 |
|---|
| 8761 | #define regDIG2_HDMI_STATUS 0x22e7 |
|---|
| 8762 | #define regDIG2_HDMI_STATUS_BASE_IDX 2 |
|---|
| 8763 | #define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x22e8 |
|---|
| 8764 | #define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8765 | #define regDIG2_HDMI_ACR_PACKET_CONTROL 0x22e9 |
|---|
| 8766 | #define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8767 | #define regDIG2_HDMI_VBI_PACKET_CONTROL 0x22ea |
|---|
| 8768 | #define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 8769 | #define regDIG2_HDMI_INFOFRAME_CONTROL0 0x22eb |
|---|
| 8770 | #define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 |
|---|
| 8771 | #define regDIG2_HDMI_INFOFRAME_CONTROL1 0x22ec |
|---|
| 8772 | #define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 |
|---|
| 8773 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x22ed |
|---|
| 8774 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 |
|---|
| 8775 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x22ee |
|---|
| 8776 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 |
|---|
| 8777 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x22ef |
|---|
| 8778 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 |
|---|
| 8779 | #define regDIG2_HDMI_GC 0x22f0 |
|---|
| 8780 | #define regDIG2_HDMI_GC_BASE_IDX 2 |
|---|
| 8781 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x22f1 |
|---|
| 8782 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 |
|---|
| 8783 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x22f2 |
|---|
| 8784 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 |
|---|
| 8785 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22f3 |
|---|
| 8786 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 |
|---|
| 8787 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22f4 |
|---|
| 8788 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 |
|---|
| 8789 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22f5 |
|---|
| 8790 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 |
|---|
| 8791 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22f6 |
|---|
| 8792 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 |
|---|
| 8793 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22f7 |
|---|
| 8794 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 |
|---|
| 8795 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22f8 |
|---|
| 8796 | #define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 |
|---|
| 8797 | #define regDIG2_HDMI_DB_CONTROL 0x22f9 |
|---|
| 8798 | #define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 |
|---|
| 8799 | #define regDIG2_HDMI_ACR_32_0 0x22fa |
|---|
| 8800 | #define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 |
|---|
| 8801 | #define regDIG2_HDMI_ACR_32_1 0x22fb |
|---|
| 8802 | #define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 |
|---|
| 8803 | #define regDIG2_HDMI_ACR_44_0 0x22fc |
|---|
| 8804 | #define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 |
|---|
| 8805 | #define regDIG2_HDMI_ACR_44_1 0x22fd |
|---|
| 8806 | #define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 |
|---|
| 8807 | #define regDIG2_HDMI_ACR_48_0 0x22fe |
|---|
| 8808 | #define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 |
|---|
| 8809 | #define regDIG2_HDMI_ACR_48_1 0x22ff |
|---|
| 8810 | #define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 |
|---|
| 8811 | #define regDIG2_HDMI_ACR_STATUS_0 0x2300 |
|---|
| 8812 | #define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 |
|---|
| 8813 | #define regDIG2_HDMI_ACR_STATUS_1 0x2301 |
|---|
| 8814 | #define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 |
|---|
| 8815 | #define regDIG2_AFMT_CNTL 0x2302 |
|---|
| 8816 | #define regDIG2_AFMT_CNTL_BASE_IDX 2 |
|---|
| 8817 | #define regDIG2_DIG_BE_CLK_CNTL 0x2303 |
|---|
| 8818 | #define regDIG2_DIG_BE_CLK_CNTL_BASE_IDX 2 |
|---|
| 8819 | #define regDIG2_DIG_BE_CNTL 0x2304 |
|---|
| 8820 | #define regDIG2_DIG_BE_CNTL_BASE_IDX 2 |
|---|
| 8821 | #define regDIG2_DIG_BE_EN_CNTL 0x2305 |
|---|
| 8822 | #define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 |
|---|
| 8823 | #define regDIG2_TMDS_CNTL 0x232c |
|---|
| 8824 | #define regDIG2_TMDS_CNTL_BASE_IDX 2 |
|---|
| 8825 | #define regDIG2_TMDS_CONTROL_CHAR 0x232d |
|---|
| 8826 | #define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 |
|---|
| 8827 | #define regDIG2_TMDS_CONTROL0_FEEDBACK 0x232e |
|---|
| 8828 | #define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 |
|---|
| 8829 | #define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x232f |
|---|
| 8830 | #define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 |
|---|
| 8831 | #define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x2330 |
|---|
| 8832 | #define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 |
|---|
| 8833 | #define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x2331 |
|---|
| 8834 | #define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 |
|---|
| 8835 | #define regDIG2_TMDS_CTL_BITS 0x2333 |
|---|
| 8836 | #define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 |
|---|
| 8837 | #define regDIG2_TMDS_DCBALANCER_CONTROL 0x2334 |
|---|
| 8838 | #define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 |
|---|
| 8839 | #define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x2335 |
|---|
| 8840 | #define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 |
|---|
| 8841 | #define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x2336 |
|---|
| 8842 | #define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 |
|---|
| 8843 | #define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x2337 |
|---|
| 8844 | #define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 |
|---|
| 8845 | #define regDIG2_DIG_VERSION 0x2339 |
|---|
| 8846 | #define regDIG2_DIG_VERSION_BASE_IDX 2 |
|---|
| 8847 | |
|---|
| 8848 | |
|---|
| 8849 | // addressBlock: dce_dc_dio_dp2_dispdec |
|---|
| 8850 | // base address: 0x920 |
|---|
| 8851 | #define regDP2_DP_LINK_CNTL 0x2366 |
|---|
| 8852 | #define regDP2_DP_LINK_CNTL_BASE_IDX 2 |
|---|
| 8853 | #define regDP2_DP_PIXEL_FORMAT 0x2367 |
|---|
| 8854 | #define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 |
|---|
| 8855 | #define regDP2_DP_MSA_COLORIMETRY 0x2368 |
|---|
| 8856 | #define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 |
|---|
| 8857 | #define regDP2_DP_CONFIG 0x2369 |
|---|
| 8858 | #define regDP2_DP_CONFIG_BASE_IDX 2 |
|---|
| 8859 | #define regDP2_DP_VID_STREAM_CNTL 0x236a |
|---|
| 8860 | #define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 |
|---|
| 8861 | #define regDP2_DP_STEER_FIFO 0x236b |
|---|
| 8862 | #define regDP2_DP_STEER_FIFO_BASE_IDX 2 |
|---|
| 8863 | #define regDP2_DP_MSA_MISC 0x236c |
|---|
| 8864 | #define regDP2_DP_MSA_MISC_BASE_IDX 2 |
|---|
| 8865 | #define regDP2_DP_DPHY_INTERNAL_CTRL 0x236d |
|---|
| 8866 | #define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
|---|
| 8867 | #define regDP2_DP_VID_TIMING 0x236e |
|---|
| 8868 | #define regDP2_DP_VID_TIMING_BASE_IDX 2 |
|---|
| 8869 | #define regDP2_DP_VID_N 0x236f |
|---|
| 8870 | #define regDP2_DP_VID_N_BASE_IDX 2 |
|---|
| 8871 | #define regDP2_DP_VID_M 0x2370 |
|---|
| 8872 | #define regDP2_DP_VID_M_BASE_IDX 2 |
|---|
| 8873 | #define regDP2_DP_LINK_FRAMING_CNTL 0x2371 |
|---|
| 8874 | #define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 |
|---|
| 8875 | #define regDP2_DP_HBR2_EYE_PATTERN 0x2372 |
|---|
| 8876 | #define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 |
|---|
| 8877 | #define regDP2_DP_VID_MSA_VBID 0x2373 |
|---|
| 8878 | #define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 |
|---|
| 8879 | #define regDP2_DP_VID_INTERRUPT_CNTL 0x2374 |
|---|
| 8880 | #define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 |
|---|
| 8881 | #define regDP2_DP_DPHY_CNTL 0x2375 |
|---|
| 8882 | #define regDP2_DP_DPHY_CNTL_BASE_IDX 2 |
|---|
| 8883 | #define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2376 |
|---|
| 8884 | #define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 |
|---|
| 8885 | #define regDP2_DP_DPHY_SYM0 0x2377 |
|---|
| 8886 | #define regDP2_DP_DPHY_SYM0_BASE_IDX 2 |
|---|
| 8887 | #define regDP2_DP_DPHY_SYM1 0x2378 |
|---|
| 8888 | #define regDP2_DP_DPHY_SYM1_BASE_IDX 2 |
|---|
| 8889 | #define regDP2_DP_DPHY_SYM2 0x2379 |
|---|
| 8890 | #define regDP2_DP_DPHY_SYM2_BASE_IDX 2 |
|---|
| 8891 | #define regDP2_DP_DPHY_8B10B_CNTL 0x237a |
|---|
| 8892 | #define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 |
|---|
| 8893 | #define regDP2_DP_DPHY_PRBS_CNTL 0x237b |
|---|
| 8894 | #define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 |
|---|
| 8895 | #define regDP2_DP_DPHY_SCRAM_CNTL 0x237c |
|---|
| 8896 | #define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 |
|---|
| 8897 | #define regDP2_DP_DPHY_CRC_EN 0x237d |
|---|
| 8898 | #define regDP2_DP_DPHY_CRC_EN_BASE_IDX 2 |
|---|
| 8899 | #define regDP2_DP_DPHY_CRC_CNTL 0x237e |
|---|
| 8900 | #define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 |
|---|
| 8901 | #define regDP2_DP_DPHY_CRC_RESULT 0x237f |
|---|
| 8902 | #define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 |
|---|
| 8903 | #define regDP2_DP_DPHY_CRC_MST_CNTL 0x2380 |
|---|
| 8904 | #define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 |
|---|
| 8905 | #define regDP2_DP_DPHY_CRC_MST_STATUS 0x2381 |
|---|
| 8906 | #define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 |
|---|
| 8907 | #define regDP2_DP_DPHY_FAST_TRAINING 0x2382 |
|---|
| 8908 | #define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 |
|---|
| 8909 | #define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2383 |
|---|
| 8910 | #define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 |
|---|
| 8911 | #define regDP2_DP_SEC_CNTL 0x2389 |
|---|
| 8912 | #define regDP2_DP_SEC_CNTL_BASE_IDX 2 |
|---|
| 8913 | #define regDP2_DP_SEC_CNTL1 0x238a |
|---|
| 8914 | #define regDP2_DP_SEC_CNTL1_BASE_IDX 2 |
|---|
| 8915 | #define regDP2_DP_SEC_FRAMING1 0x238b |
|---|
| 8916 | #define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 |
|---|
| 8917 | #define regDP2_DP_SEC_FRAMING2 0x238c |
|---|
| 8918 | #define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 |
|---|
| 8919 | #define regDP2_DP_SEC_FRAMING3 0x238d |
|---|
| 8920 | #define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 |
|---|
| 8921 | #define regDP2_DP_SEC_FRAMING4 0x238e |
|---|
| 8922 | #define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 |
|---|
| 8923 | #define regDP2_DP_SEC_AUD_N 0x238f |
|---|
| 8924 | #define regDP2_DP_SEC_AUD_N_BASE_IDX 2 |
|---|
| 8925 | #define regDP2_DP_SEC_AUD_N_READBACK 0x2390 |
|---|
| 8926 | #define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 |
|---|
| 8927 | #define regDP2_DP_SEC_AUD_M 0x2391 |
|---|
| 8928 | #define regDP2_DP_SEC_AUD_M_BASE_IDX 2 |
|---|
| 8929 | #define regDP2_DP_SEC_AUD_M_READBACK 0x2392 |
|---|
| 8930 | #define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 |
|---|
| 8931 | #define regDP2_DP_SEC_TIMESTAMP 0x2393 |
|---|
| 8932 | #define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 |
|---|
| 8933 | #define regDP2_DP_SEC_PACKET_CNTL 0x2394 |
|---|
| 8934 | #define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 |
|---|
| 8935 | #define regDP2_DP_MSE_RATE_CNTL 0x2395 |
|---|
| 8936 | #define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 |
|---|
| 8937 | #define regDP2_DP_MSE_RATE_UPDATE 0x2397 |
|---|
| 8938 | #define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 |
|---|
| 8939 | #define regDP2_DP_MSE_SAT0 0x2398 |
|---|
| 8940 | #define regDP2_DP_MSE_SAT0_BASE_IDX 2 |
|---|
| 8941 | #define regDP2_DP_MSE_SAT1 0x2399 |
|---|
| 8942 | #define regDP2_DP_MSE_SAT1_BASE_IDX 2 |
|---|
| 8943 | #define regDP2_DP_MSE_SAT2 0x239a |
|---|
| 8944 | #define regDP2_DP_MSE_SAT2_BASE_IDX 2 |
|---|
| 8945 | #define regDP2_DP_MSE_SAT_UPDATE 0x239b |
|---|
| 8946 | #define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 |
|---|
| 8947 | #define regDP2_DP_MSE_LINK_TIMING 0x239c |
|---|
| 8948 | #define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 |
|---|
| 8949 | #define regDP2_DP_MSE_MISC_CNTL 0x239d |
|---|
| 8950 | #define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 |
|---|
| 8951 | #define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x23a2 |
|---|
| 8952 | #define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 |
|---|
| 8953 | #define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x23a3 |
|---|
| 8954 | #define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 |
|---|
| 8955 | #define regDP2_DP_MSE_SAT0_STATUS 0x23a5 |
|---|
| 8956 | #define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 |
|---|
| 8957 | #define regDP2_DP_MSE_SAT1_STATUS 0x23a6 |
|---|
| 8958 | #define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 |
|---|
| 8959 | #define regDP2_DP_MSE_SAT2_STATUS 0x23a7 |
|---|
| 8960 | #define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 |
|---|
| 8961 | #define regDP2_DP_DPIA_SPARE 0x23a8 |
|---|
| 8962 | #define regDP2_DP_DPIA_SPARE_BASE_IDX 2 |
|---|
| 8963 | #define regDP2_DP_MSA_TIMING_PARAM1 0x23aa |
|---|
| 8964 | #define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 |
|---|
| 8965 | #define regDP2_DP_MSA_TIMING_PARAM2 0x23ab |
|---|
| 8966 | #define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 |
|---|
| 8967 | #define regDP2_DP_MSA_TIMING_PARAM3 0x23ac |
|---|
| 8968 | #define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 |
|---|
| 8969 | #define regDP2_DP_MSA_TIMING_PARAM4 0x23ad |
|---|
| 8970 | #define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 |
|---|
| 8971 | #define regDP2_DP_MSO_CNTL 0x23ae |
|---|
| 8972 | #define regDP2_DP_MSO_CNTL_BASE_IDX 2 |
|---|
| 8973 | #define regDP2_DP_MSO_CNTL1 0x23af |
|---|
| 8974 | #define regDP2_DP_MSO_CNTL1_BASE_IDX 2 |
|---|
| 8975 | #define regDP2_DP_DSC_CNTL 0x23b0 |
|---|
| 8976 | #define regDP2_DP_DSC_CNTL_BASE_IDX 2 |
|---|
| 8977 | #define regDP2_DP_SEC_CNTL2 0x23b1 |
|---|
| 8978 | #define regDP2_DP_SEC_CNTL2_BASE_IDX 2 |
|---|
| 8979 | #define regDP2_DP_SEC_CNTL3 0x23b2 |
|---|
| 8980 | #define regDP2_DP_SEC_CNTL3_BASE_IDX 2 |
|---|
| 8981 | #define regDP2_DP_SEC_CNTL4 0x23b3 |
|---|
| 8982 | #define regDP2_DP_SEC_CNTL4_BASE_IDX 2 |
|---|
| 8983 | #define regDP2_DP_SEC_CNTL5 0x23b4 |
|---|
| 8984 | #define regDP2_DP_SEC_CNTL5_BASE_IDX 2 |
|---|
| 8985 | #define regDP2_DP_SEC_CNTL6 0x23b5 |
|---|
| 8986 | #define regDP2_DP_SEC_CNTL6_BASE_IDX 2 |
|---|
| 8987 | #define regDP2_DP_SEC_CNTL7 0x23b6 |
|---|
| 8988 | #define regDP2_DP_SEC_CNTL7_BASE_IDX 2 |
|---|
| 8989 | #define regDP2_DP_DB_CNTL 0x23b7 |
|---|
| 8990 | #define regDP2_DP_DB_CNTL_BASE_IDX 2 |
|---|
| 8991 | #define regDP2_DP_MSA_VBID_MISC 0x23b8 |
|---|
| 8992 | #define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 |
|---|
| 8993 | #define regDP2_DP_SEC_METADATA_TRANSMISSION 0x23b9 |
|---|
| 8994 | #define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 |
|---|
| 8995 | #define regDP2_DP_ALPM_CNTL 0x23bb |
|---|
| 8996 | #define regDP2_DP_ALPM_CNTL_BASE_IDX 2 |
|---|
| 8997 | #define regDP2_DP_GSP8_CNTL 0x23bc |
|---|
| 8998 | #define regDP2_DP_GSP8_CNTL_BASE_IDX 2 |
|---|
| 8999 | #define regDP2_DP_GSP9_CNTL 0x23bd |
|---|
| 9000 | #define regDP2_DP_GSP9_CNTL_BASE_IDX 2 |
|---|
| 9001 | #define regDP2_DP_GSP10_CNTL 0x23be |
|---|
| 9002 | #define regDP2_DP_GSP10_CNTL_BASE_IDX 2 |
|---|
| 9003 | #define regDP2_DP_GSP11_CNTL 0x23bf |
|---|
| 9004 | #define regDP2_DP_GSP11_CNTL_BASE_IDX 2 |
|---|
| 9005 | #define regDP2_DP_GSP_EN_DB_STATUS 0x23c0 |
|---|
| 9006 | #define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 |
|---|
| 9007 | #define regDP2_DP_AUXLESS_ALPM_CNTL1 0x23c1 |
|---|
| 9008 | #define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 |
|---|
| 9009 | #define regDP2_DP_AUXLESS_ALPM_CNTL2 0x23c2 |
|---|
| 9010 | #define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 |
|---|
| 9011 | #define regDP2_DP_AUXLESS_ALPM_CNTL3 0x23c3 |
|---|
| 9012 | #define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 |
|---|
| 9013 | #define regDP2_DP_AUXLESS_ALPM_CNTL4 0x23c4 |
|---|
| 9014 | #define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 |
|---|
| 9015 | #define regDP2_DP_AUXLESS_ALPM_CNTL5 0x23c5 |
|---|
| 9016 | #define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 |
|---|
| 9017 | #define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS 0x23c6 |
|---|
| 9018 | #define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 |
|---|
| 9019 | #define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL 0x23c7 |
|---|
| 9020 | #define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 9021 | #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0 0x23c8 |
|---|
| 9022 | #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 |
|---|
| 9023 | #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1 0x23c9 |
|---|
| 9024 | #define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 |
|---|
| 9025 | #define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL 0x23ca |
|---|
| 9026 | #define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 9027 | |
|---|
| 9028 | |
|---|
| 9029 | // addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec |
|---|
| 9030 | // base address: 0x16250 |
|---|
| 9031 | #define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x23d4 |
|---|
| 9032 | #define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 9033 | #define regVPG3_VPG_GENERIC_PACKET_DATA 0x23d5 |
|---|
| 9034 | #define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
|---|
| 9035 | #define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x23d6 |
|---|
| 9036 | #define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 9037 | #define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x23d7 |
|---|
| 9038 | #define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 9039 | #define regVPG3_VPG_GENERIC_STATUS 0x23d8 |
|---|
| 9040 | #define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 |
|---|
| 9041 | #define regVPG3_VPG_MEM_PWR 0x23d9 |
|---|
| 9042 | #define regVPG3_VPG_MEM_PWR_BASE_IDX 2 |
|---|
| 9043 | #define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x23da |
|---|
| 9044 | #define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 9045 | #define regVPG3_VPG_ISRC1_2_DATA 0x23db |
|---|
| 9046 | #define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 |
|---|
| 9047 | #define regVPG3_VPG_MPEG_INFO0 0x23dc |
|---|
| 9048 | #define regVPG3_VPG_MPEG_INFO0_BASE_IDX 2 |
|---|
| 9049 | #define regVPG3_VPG_MPEG_INFO1 0x23dd |
|---|
| 9050 | #define regVPG3_VPG_MPEG_INFO1_BASE_IDX 2 |
|---|
| 9051 | |
|---|
| 9052 | |
|---|
| 9053 | // addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec |
|---|
| 9054 | // base address: 0x1627c |
|---|
| 9055 | #define regAFMT3_AFMT_ACP 0x23df |
|---|
| 9056 | #define regAFMT3_AFMT_ACP_BASE_IDX 2 |
|---|
| 9057 | #define regAFMT3_AFMT_VBI_PACKET_CONTROL 0x23e0 |
|---|
| 9058 | #define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 9059 | #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x23e1 |
|---|
| 9060 | #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 |
|---|
| 9061 | #define regAFMT3_AFMT_AUDIO_INFO0 0x23e2 |
|---|
| 9062 | #define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2 |
|---|
| 9063 | #define regAFMT3_AFMT_AUDIO_INFO1 0x23e3 |
|---|
| 9064 | #define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2 |
|---|
| 9065 | #define regAFMT3_AFMT_60958_0 0x23e4 |
|---|
| 9066 | #define regAFMT3_AFMT_60958_0_BASE_IDX 2 |
|---|
| 9067 | #define regAFMT3_AFMT_60958_1 0x23e5 |
|---|
| 9068 | #define regAFMT3_AFMT_60958_1_BASE_IDX 2 |
|---|
| 9069 | #define regAFMT3_AFMT_AUDIO_CRC_CONTROL 0x23e6 |
|---|
| 9070 | #define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 |
|---|
| 9071 | #define regAFMT3_AFMT_RAMP_CONTROL0 0x23e7 |
|---|
| 9072 | #define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2 |
|---|
| 9073 | #define regAFMT3_AFMT_RAMP_CONTROL1 0x23e8 |
|---|
| 9074 | #define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2 |
|---|
| 9075 | #define regAFMT3_AFMT_RAMP_CONTROL2 0x23e9 |
|---|
| 9076 | #define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2 |
|---|
| 9077 | #define regAFMT3_AFMT_RAMP_CONTROL3 0x23ea |
|---|
| 9078 | #define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2 |
|---|
| 9079 | #define regAFMT3_AFMT_60958_2 0x23eb |
|---|
| 9080 | #define regAFMT3_AFMT_60958_2_BASE_IDX 2 |
|---|
| 9081 | #define regAFMT3_AFMT_AUDIO_CRC_RESULT 0x23ec |
|---|
| 9082 | #define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 |
|---|
| 9083 | #define regAFMT3_AFMT_STATUS 0x23ed |
|---|
| 9084 | #define regAFMT3_AFMT_STATUS_BASE_IDX 2 |
|---|
| 9085 | #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x23ee |
|---|
| 9086 | #define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 9087 | #define regAFMT3_AFMT_INFOFRAME_CONTROL0 0x23ef |
|---|
| 9088 | #define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 |
|---|
| 9089 | #define regAFMT3_AFMT_INTERRUPT_STATUS 0x23f0 |
|---|
| 9090 | #define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 |
|---|
| 9091 | #define regAFMT3_AFMT_AUDIO_SRC_CONTROL 0x23f1 |
|---|
| 9092 | #define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 |
|---|
| 9093 | #define regAFMT3_AFMT_MEM_PWR 0x23f3 |
|---|
| 9094 | #define regAFMT3_AFMT_MEM_PWR_BASE_IDX 2 |
|---|
| 9095 | |
|---|
| 9096 | |
|---|
| 9097 | // addressBlock: dce_dc_dio_dig3_dme_dme_dispdec |
|---|
| 9098 | // base address: 0x162f4 |
|---|
| 9099 | #define regDME3_DME_CONTROL 0x23fd |
|---|
| 9100 | #define regDME3_DME_CONTROL_BASE_IDX 2 |
|---|
| 9101 | #define regDME3_DME_MEMORY_CONTROL 0x23fe |
|---|
| 9102 | #define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 |
|---|
| 9103 | |
|---|
| 9104 | |
|---|
| 9105 | // addressBlock: dce_dc_dio_dig3_dispdec |
|---|
| 9106 | // base address: 0xdb0 |
|---|
| 9107 | #define regDIG3_DIG_FE_CNTL 0x23ff |
|---|
| 9108 | #define regDIG3_DIG_FE_CNTL_BASE_IDX 2 |
|---|
| 9109 | #define regDIG3_DIG_FE_CLK_CNTL 0x2400 |
|---|
| 9110 | #define regDIG3_DIG_FE_CLK_CNTL_BASE_IDX 2 |
|---|
| 9111 | #define regDIG3_DIG_FE_EN_CNTL 0x2401 |
|---|
| 9112 | #define regDIG3_DIG_FE_EN_CNTL_BASE_IDX 2 |
|---|
| 9113 | #define regDIG3_DIG_OUTPUT_CRC_CNTL 0x2402 |
|---|
| 9114 | #define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 |
|---|
| 9115 | #define regDIG3_DIG_OUTPUT_CRC_RESULT 0x2403 |
|---|
| 9116 | #define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 |
|---|
| 9117 | #define regDIG3_DIG_CLOCK_PATTERN 0x2404 |
|---|
| 9118 | #define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 |
|---|
| 9119 | #define regDIG3_DIG_TEST_PATTERN 0x2405 |
|---|
| 9120 | #define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 |
|---|
| 9121 | #define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2406 |
|---|
| 9122 | #define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 |
|---|
| 9123 | #define regDIG3_DIG_FIFO_CTRL0 0x2407 |
|---|
| 9124 | #define regDIG3_DIG_FIFO_CTRL0_BASE_IDX 2 |
|---|
| 9125 | #define regDIG3_DIG_FIFO_CTRL1 0x2408 |
|---|
| 9126 | #define regDIG3_DIG_FIFO_CTRL1_BASE_IDX 2 |
|---|
| 9127 | #define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2409 |
|---|
| 9128 | #define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 9129 | #define regDIG3_HDMI_CONTROL 0x240a |
|---|
| 9130 | #define regDIG3_HDMI_CONTROL_BASE_IDX 2 |
|---|
| 9131 | #define regDIG3_HDMI_STATUS 0x240b |
|---|
| 9132 | #define regDIG3_HDMI_STATUS_BASE_IDX 2 |
|---|
| 9133 | #define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x240c |
|---|
| 9134 | #define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 9135 | #define regDIG3_HDMI_ACR_PACKET_CONTROL 0x240d |
|---|
| 9136 | #define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 9137 | #define regDIG3_HDMI_VBI_PACKET_CONTROL 0x240e |
|---|
| 9138 | #define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 9139 | #define regDIG3_HDMI_INFOFRAME_CONTROL0 0x240f |
|---|
| 9140 | #define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 |
|---|
| 9141 | #define regDIG3_HDMI_INFOFRAME_CONTROL1 0x2410 |
|---|
| 9142 | #define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 |
|---|
| 9143 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2411 |
|---|
| 9144 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 |
|---|
| 9145 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x2412 |
|---|
| 9146 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 |
|---|
| 9147 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x2413 |
|---|
| 9148 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 |
|---|
| 9149 | #define regDIG3_HDMI_GC 0x2414 |
|---|
| 9150 | #define regDIG3_HDMI_GC_BASE_IDX 2 |
|---|
| 9151 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2415 |
|---|
| 9152 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 |
|---|
| 9153 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2416 |
|---|
| 9154 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 |
|---|
| 9155 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2417 |
|---|
| 9156 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 |
|---|
| 9157 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x2418 |
|---|
| 9158 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 |
|---|
| 9159 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x2419 |
|---|
| 9160 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 |
|---|
| 9161 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x241a |
|---|
| 9162 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 |
|---|
| 9163 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x241b |
|---|
| 9164 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 |
|---|
| 9165 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x241c |
|---|
| 9166 | #define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 |
|---|
| 9167 | #define regDIG3_HDMI_DB_CONTROL 0x241d |
|---|
| 9168 | #define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 |
|---|
| 9169 | #define regDIG3_HDMI_ACR_32_0 0x241e |
|---|
| 9170 | #define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 |
|---|
| 9171 | #define regDIG3_HDMI_ACR_32_1 0x241f |
|---|
| 9172 | #define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 |
|---|
| 9173 | #define regDIG3_HDMI_ACR_44_0 0x2420 |
|---|
| 9174 | #define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 |
|---|
| 9175 | #define regDIG3_HDMI_ACR_44_1 0x2421 |
|---|
| 9176 | #define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 |
|---|
| 9177 | #define regDIG3_HDMI_ACR_48_0 0x2422 |
|---|
| 9178 | #define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 |
|---|
| 9179 | #define regDIG3_HDMI_ACR_48_1 0x2423 |
|---|
| 9180 | #define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 |
|---|
| 9181 | #define regDIG3_HDMI_ACR_STATUS_0 0x2424 |
|---|
| 9182 | #define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 |
|---|
| 9183 | #define regDIG3_HDMI_ACR_STATUS_1 0x2425 |
|---|
| 9184 | #define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 |
|---|
| 9185 | #define regDIG3_AFMT_CNTL 0x2426 |
|---|
| 9186 | #define regDIG3_AFMT_CNTL_BASE_IDX 2 |
|---|
| 9187 | #define regDIG3_DIG_BE_CLK_CNTL 0x2427 |
|---|
| 9188 | #define regDIG3_DIG_BE_CLK_CNTL_BASE_IDX 2 |
|---|
| 9189 | #define regDIG3_DIG_BE_CNTL 0x2428 |
|---|
| 9190 | #define regDIG3_DIG_BE_CNTL_BASE_IDX 2 |
|---|
| 9191 | #define regDIG3_DIG_BE_EN_CNTL 0x2429 |
|---|
| 9192 | #define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 |
|---|
| 9193 | #define regDIG3_TMDS_CNTL 0x2450 |
|---|
| 9194 | #define regDIG3_TMDS_CNTL_BASE_IDX 2 |
|---|
| 9195 | #define regDIG3_TMDS_CONTROL_CHAR 0x2451 |
|---|
| 9196 | #define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 |
|---|
| 9197 | #define regDIG3_TMDS_CONTROL0_FEEDBACK 0x2452 |
|---|
| 9198 | #define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 |
|---|
| 9199 | #define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x2453 |
|---|
| 9200 | #define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 |
|---|
| 9201 | #define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x2454 |
|---|
| 9202 | #define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 |
|---|
| 9203 | #define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x2455 |
|---|
| 9204 | #define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 |
|---|
| 9205 | #define regDIG3_TMDS_CTL_BITS 0x2457 |
|---|
| 9206 | #define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 |
|---|
| 9207 | #define regDIG3_TMDS_DCBALANCER_CONTROL 0x2458 |
|---|
| 9208 | #define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 |
|---|
| 9209 | #define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x2459 |
|---|
| 9210 | #define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 |
|---|
| 9211 | #define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x245a |
|---|
| 9212 | #define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 |
|---|
| 9213 | #define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x245b |
|---|
| 9214 | #define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 |
|---|
| 9215 | #define regDIG3_DIG_VERSION 0x245d |
|---|
| 9216 | #define regDIG3_DIG_VERSION_BASE_IDX 2 |
|---|
| 9217 | |
|---|
| 9218 | |
|---|
| 9219 | // addressBlock: dce_dc_dio_dp3_dispdec |
|---|
| 9220 | // base address: 0xdb0 |
|---|
| 9221 | #define regDP3_DP_LINK_CNTL 0x248a |
|---|
| 9222 | #define regDP3_DP_LINK_CNTL_BASE_IDX 2 |
|---|
| 9223 | #define regDP3_DP_PIXEL_FORMAT 0x248b |
|---|
| 9224 | #define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 |
|---|
| 9225 | #define regDP3_DP_MSA_COLORIMETRY 0x248c |
|---|
| 9226 | #define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 |
|---|
| 9227 | #define regDP3_DP_CONFIG 0x248d |
|---|
| 9228 | #define regDP3_DP_CONFIG_BASE_IDX 2 |
|---|
| 9229 | #define regDP3_DP_VID_STREAM_CNTL 0x248e |
|---|
| 9230 | #define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 |
|---|
| 9231 | #define regDP3_DP_STEER_FIFO 0x248f |
|---|
| 9232 | #define regDP3_DP_STEER_FIFO_BASE_IDX 2 |
|---|
| 9233 | #define regDP3_DP_MSA_MISC 0x2490 |
|---|
| 9234 | #define regDP3_DP_MSA_MISC_BASE_IDX 2 |
|---|
| 9235 | #define regDP3_DP_DPHY_INTERNAL_CTRL 0x2491 |
|---|
| 9236 | #define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
|---|
| 9237 | #define regDP3_DP_VID_TIMING 0x2492 |
|---|
| 9238 | #define regDP3_DP_VID_TIMING_BASE_IDX 2 |
|---|
| 9239 | #define regDP3_DP_VID_N 0x2493 |
|---|
| 9240 | #define regDP3_DP_VID_N_BASE_IDX 2 |
|---|
| 9241 | #define regDP3_DP_VID_M 0x2494 |
|---|
| 9242 | #define regDP3_DP_VID_M_BASE_IDX 2 |
|---|
| 9243 | #define regDP3_DP_LINK_FRAMING_CNTL 0x2495 |
|---|
| 9244 | #define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 |
|---|
| 9245 | #define regDP3_DP_HBR2_EYE_PATTERN 0x2496 |
|---|
| 9246 | #define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 |
|---|
| 9247 | #define regDP3_DP_VID_MSA_VBID 0x2497 |
|---|
| 9248 | #define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 |
|---|
| 9249 | #define regDP3_DP_VID_INTERRUPT_CNTL 0x2498 |
|---|
| 9250 | #define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 |
|---|
| 9251 | #define regDP3_DP_DPHY_CNTL 0x2499 |
|---|
| 9252 | #define regDP3_DP_DPHY_CNTL_BASE_IDX 2 |
|---|
| 9253 | #define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x249a |
|---|
| 9254 | #define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 |
|---|
| 9255 | #define regDP3_DP_DPHY_SYM0 0x249b |
|---|
| 9256 | #define regDP3_DP_DPHY_SYM0_BASE_IDX 2 |
|---|
| 9257 | #define regDP3_DP_DPHY_SYM1 0x249c |
|---|
| 9258 | #define regDP3_DP_DPHY_SYM1_BASE_IDX 2 |
|---|
| 9259 | #define regDP3_DP_DPHY_SYM2 0x249d |
|---|
| 9260 | #define regDP3_DP_DPHY_SYM2_BASE_IDX 2 |
|---|
| 9261 | #define regDP3_DP_DPHY_8B10B_CNTL 0x249e |
|---|
| 9262 | #define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 |
|---|
| 9263 | #define regDP3_DP_DPHY_PRBS_CNTL 0x249f |
|---|
| 9264 | #define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 |
|---|
| 9265 | #define regDP3_DP_DPHY_SCRAM_CNTL 0x24a0 |
|---|
| 9266 | #define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 |
|---|
| 9267 | #define regDP3_DP_DPHY_CRC_EN 0x24a1 |
|---|
| 9268 | #define regDP3_DP_DPHY_CRC_EN_BASE_IDX 2 |
|---|
| 9269 | #define regDP3_DP_DPHY_CRC_CNTL 0x24a2 |
|---|
| 9270 | #define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 |
|---|
| 9271 | #define regDP3_DP_DPHY_CRC_RESULT 0x24a3 |
|---|
| 9272 | #define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 |
|---|
| 9273 | #define regDP3_DP_DPHY_CRC_MST_CNTL 0x24a4 |
|---|
| 9274 | #define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 |
|---|
| 9275 | #define regDP3_DP_DPHY_CRC_MST_STATUS 0x24a5 |
|---|
| 9276 | #define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 |
|---|
| 9277 | #define regDP3_DP_DPHY_FAST_TRAINING 0x24a6 |
|---|
| 9278 | #define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 |
|---|
| 9279 | #define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x24a7 |
|---|
| 9280 | #define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 |
|---|
| 9281 | #define regDP3_DP_SEC_CNTL 0x24ad |
|---|
| 9282 | #define regDP3_DP_SEC_CNTL_BASE_IDX 2 |
|---|
| 9283 | #define regDP3_DP_SEC_CNTL1 0x24ae |
|---|
| 9284 | #define regDP3_DP_SEC_CNTL1_BASE_IDX 2 |
|---|
| 9285 | #define regDP3_DP_SEC_FRAMING1 0x24af |
|---|
| 9286 | #define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 |
|---|
| 9287 | #define regDP3_DP_SEC_FRAMING2 0x24b0 |
|---|
| 9288 | #define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 |
|---|
| 9289 | #define regDP3_DP_SEC_FRAMING3 0x24b1 |
|---|
| 9290 | #define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 |
|---|
| 9291 | #define regDP3_DP_SEC_FRAMING4 0x24b2 |
|---|
| 9292 | #define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 |
|---|
| 9293 | #define regDP3_DP_SEC_AUD_N 0x24b3 |
|---|
| 9294 | #define regDP3_DP_SEC_AUD_N_BASE_IDX 2 |
|---|
| 9295 | #define regDP3_DP_SEC_AUD_N_READBACK 0x24b4 |
|---|
| 9296 | #define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 |
|---|
| 9297 | #define regDP3_DP_SEC_AUD_M 0x24b5 |
|---|
| 9298 | #define regDP3_DP_SEC_AUD_M_BASE_IDX 2 |
|---|
| 9299 | #define regDP3_DP_SEC_AUD_M_READBACK 0x24b6 |
|---|
| 9300 | #define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 |
|---|
| 9301 | #define regDP3_DP_SEC_TIMESTAMP 0x24b7 |
|---|
| 9302 | #define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 |
|---|
| 9303 | #define regDP3_DP_SEC_PACKET_CNTL 0x24b8 |
|---|
| 9304 | #define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 |
|---|
| 9305 | #define regDP3_DP_MSE_RATE_CNTL 0x24b9 |
|---|
| 9306 | #define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 |
|---|
| 9307 | #define regDP3_DP_MSE_RATE_UPDATE 0x24bb |
|---|
| 9308 | #define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 |
|---|
| 9309 | #define regDP3_DP_MSE_SAT0 0x24bc |
|---|
| 9310 | #define regDP3_DP_MSE_SAT0_BASE_IDX 2 |
|---|
| 9311 | #define regDP3_DP_MSE_SAT1 0x24bd |
|---|
| 9312 | #define regDP3_DP_MSE_SAT1_BASE_IDX 2 |
|---|
| 9313 | #define regDP3_DP_MSE_SAT2 0x24be |
|---|
| 9314 | #define regDP3_DP_MSE_SAT2_BASE_IDX 2 |
|---|
| 9315 | #define regDP3_DP_MSE_SAT_UPDATE 0x24bf |
|---|
| 9316 | #define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 |
|---|
| 9317 | #define regDP3_DP_MSE_LINK_TIMING 0x24c0 |
|---|
| 9318 | #define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 |
|---|
| 9319 | #define regDP3_DP_MSE_MISC_CNTL 0x24c1 |
|---|
| 9320 | #define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 |
|---|
| 9321 | #define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x24c6 |
|---|
| 9322 | #define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 |
|---|
| 9323 | #define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x24c7 |
|---|
| 9324 | #define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 |
|---|
| 9325 | #define regDP3_DP_MSE_SAT0_STATUS 0x24c9 |
|---|
| 9326 | #define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 |
|---|
| 9327 | #define regDP3_DP_MSE_SAT1_STATUS 0x24ca |
|---|
| 9328 | #define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 |
|---|
| 9329 | #define regDP3_DP_MSE_SAT2_STATUS 0x24cb |
|---|
| 9330 | #define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 |
|---|
| 9331 | #define regDP3_DP_DPIA_SPARE 0x24cc |
|---|
| 9332 | #define regDP3_DP_DPIA_SPARE_BASE_IDX 2 |
|---|
| 9333 | #define regDP3_DP_MSA_TIMING_PARAM1 0x24ce |
|---|
| 9334 | #define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 |
|---|
| 9335 | #define regDP3_DP_MSA_TIMING_PARAM2 0x24cf |
|---|
| 9336 | #define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 |
|---|
| 9337 | #define regDP3_DP_MSA_TIMING_PARAM3 0x24d0 |
|---|
| 9338 | #define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 |
|---|
| 9339 | #define regDP3_DP_MSA_TIMING_PARAM4 0x24d1 |
|---|
| 9340 | #define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 |
|---|
| 9341 | #define regDP3_DP_MSO_CNTL 0x24d2 |
|---|
| 9342 | #define regDP3_DP_MSO_CNTL_BASE_IDX 2 |
|---|
| 9343 | #define regDP3_DP_MSO_CNTL1 0x24d3 |
|---|
| 9344 | #define regDP3_DP_MSO_CNTL1_BASE_IDX 2 |
|---|
| 9345 | #define regDP3_DP_DSC_CNTL 0x24d4 |
|---|
| 9346 | #define regDP3_DP_DSC_CNTL_BASE_IDX 2 |
|---|
| 9347 | #define regDP3_DP_SEC_CNTL2 0x24d5 |
|---|
| 9348 | #define regDP3_DP_SEC_CNTL2_BASE_IDX 2 |
|---|
| 9349 | #define regDP3_DP_SEC_CNTL3 0x24d6 |
|---|
| 9350 | #define regDP3_DP_SEC_CNTL3_BASE_IDX 2 |
|---|
| 9351 | #define regDP3_DP_SEC_CNTL4 0x24d7 |
|---|
| 9352 | #define regDP3_DP_SEC_CNTL4_BASE_IDX 2 |
|---|
| 9353 | #define regDP3_DP_SEC_CNTL5 0x24d8 |
|---|
| 9354 | #define regDP3_DP_SEC_CNTL5_BASE_IDX 2 |
|---|
| 9355 | #define regDP3_DP_SEC_CNTL6 0x24d9 |
|---|
| 9356 | #define regDP3_DP_SEC_CNTL6_BASE_IDX 2 |
|---|
| 9357 | #define regDP3_DP_SEC_CNTL7 0x24da |
|---|
| 9358 | #define regDP3_DP_SEC_CNTL7_BASE_IDX 2 |
|---|
| 9359 | #define regDP3_DP_DB_CNTL 0x24db |
|---|
| 9360 | #define regDP3_DP_DB_CNTL_BASE_IDX 2 |
|---|
| 9361 | #define regDP3_DP_MSA_VBID_MISC 0x24dc |
|---|
| 9362 | #define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 |
|---|
| 9363 | #define regDP3_DP_SEC_METADATA_TRANSMISSION 0x24dd |
|---|
| 9364 | #define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 |
|---|
| 9365 | #define regDP3_DP_ALPM_CNTL 0x24df |
|---|
| 9366 | #define regDP3_DP_ALPM_CNTL_BASE_IDX 2 |
|---|
| 9367 | #define regDP3_DP_GSP8_CNTL 0x24e0 |
|---|
| 9368 | #define regDP3_DP_GSP8_CNTL_BASE_IDX 2 |
|---|
| 9369 | #define regDP3_DP_GSP9_CNTL 0x24e1 |
|---|
| 9370 | #define regDP3_DP_GSP9_CNTL_BASE_IDX 2 |
|---|
| 9371 | #define regDP3_DP_GSP10_CNTL 0x24e2 |
|---|
| 9372 | #define regDP3_DP_GSP10_CNTL_BASE_IDX 2 |
|---|
| 9373 | #define regDP3_DP_GSP11_CNTL 0x24e3 |
|---|
| 9374 | #define regDP3_DP_GSP11_CNTL_BASE_IDX 2 |
|---|
| 9375 | #define regDP3_DP_GSP_EN_DB_STATUS 0x24e4 |
|---|
| 9376 | #define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 |
|---|
| 9377 | #define regDP3_DP_AUXLESS_ALPM_CNTL1 0x24e5 |
|---|
| 9378 | #define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 |
|---|
| 9379 | #define regDP3_DP_AUXLESS_ALPM_CNTL2 0x24e6 |
|---|
| 9380 | #define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 |
|---|
| 9381 | #define regDP3_DP_AUXLESS_ALPM_CNTL3 0x24e7 |
|---|
| 9382 | #define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 |
|---|
| 9383 | #define regDP3_DP_AUXLESS_ALPM_CNTL4 0x24e8 |
|---|
| 9384 | #define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 |
|---|
| 9385 | #define regDP3_DP_AUXLESS_ALPM_CNTL5 0x24e9 |
|---|
| 9386 | #define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 |
|---|
| 9387 | #define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS 0x24ea |
|---|
| 9388 | #define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 |
|---|
| 9389 | #define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL 0x24eb |
|---|
| 9390 | #define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 9391 | #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0 0x24ec |
|---|
| 9392 | #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 |
|---|
| 9393 | #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1 0x24ed |
|---|
| 9394 | #define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 |
|---|
| 9395 | #define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL 0x24ee |
|---|
| 9396 | #define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 9397 | |
|---|
| 9398 | |
|---|
| 9399 | // addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec |
|---|
| 9400 | // base address: 0x166e0 |
|---|
| 9401 | #define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x24f8 |
|---|
| 9402 | #define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 9403 | #define regVPG4_VPG_GENERIC_PACKET_DATA 0x24f9 |
|---|
| 9404 | #define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
|---|
| 9405 | #define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x24fa |
|---|
| 9406 | #define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 9407 | #define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x24fb |
|---|
| 9408 | #define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 9409 | #define regVPG4_VPG_GENERIC_STATUS 0x24fc |
|---|
| 9410 | #define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 |
|---|
| 9411 | #define regVPG4_VPG_MEM_PWR 0x24fd |
|---|
| 9412 | #define regVPG4_VPG_MEM_PWR_BASE_IDX 2 |
|---|
| 9413 | #define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x24fe |
|---|
| 9414 | #define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 9415 | #define regVPG4_VPG_ISRC1_2_DATA 0x24ff |
|---|
| 9416 | #define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 |
|---|
| 9417 | #define regVPG4_VPG_MPEG_INFO0 0x2500 |
|---|
| 9418 | #define regVPG4_VPG_MPEG_INFO0_BASE_IDX 2 |
|---|
| 9419 | #define regVPG4_VPG_MPEG_INFO1 0x2501 |
|---|
| 9420 | #define regVPG4_VPG_MPEG_INFO1_BASE_IDX 2 |
|---|
| 9421 | |
|---|
| 9422 | |
|---|
| 9423 | // addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec |
|---|
| 9424 | // base address: 0x1670c |
|---|
| 9425 | #define regAFMT4_AFMT_ACP 0x2503 |
|---|
| 9426 | #define regAFMT4_AFMT_ACP_BASE_IDX 2 |
|---|
| 9427 | #define regAFMT4_AFMT_VBI_PACKET_CONTROL 0x2504 |
|---|
| 9428 | #define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 9429 | #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2505 |
|---|
| 9430 | #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 |
|---|
| 9431 | #define regAFMT4_AFMT_AUDIO_INFO0 0x2506 |
|---|
| 9432 | #define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2 |
|---|
| 9433 | #define regAFMT4_AFMT_AUDIO_INFO1 0x2507 |
|---|
| 9434 | #define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2 |
|---|
| 9435 | #define regAFMT4_AFMT_60958_0 0x2508 |
|---|
| 9436 | #define regAFMT4_AFMT_60958_0_BASE_IDX 2 |
|---|
| 9437 | #define regAFMT4_AFMT_60958_1 0x2509 |
|---|
| 9438 | #define regAFMT4_AFMT_60958_1_BASE_IDX 2 |
|---|
| 9439 | #define regAFMT4_AFMT_AUDIO_CRC_CONTROL 0x250a |
|---|
| 9440 | #define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 |
|---|
| 9441 | #define regAFMT4_AFMT_RAMP_CONTROL0 0x250b |
|---|
| 9442 | #define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2 |
|---|
| 9443 | #define regAFMT4_AFMT_RAMP_CONTROL1 0x250c |
|---|
| 9444 | #define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2 |
|---|
| 9445 | #define regAFMT4_AFMT_RAMP_CONTROL2 0x250d |
|---|
| 9446 | #define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2 |
|---|
| 9447 | #define regAFMT4_AFMT_RAMP_CONTROL3 0x250e |
|---|
| 9448 | #define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2 |
|---|
| 9449 | #define regAFMT4_AFMT_60958_2 0x250f |
|---|
| 9450 | #define regAFMT4_AFMT_60958_2_BASE_IDX 2 |
|---|
| 9451 | #define regAFMT4_AFMT_AUDIO_CRC_RESULT 0x2510 |
|---|
| 9452 | #define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 |
|---|
| 9453 | #define regAFMT4_AFMT_STATUS 0x2511 |
|---|
| 9454 | #define regAFMT4_AFMT_STATUS_BASE_IDX 2 |
|---|
| 9455 | #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2512 |
|---|
| 9456 | #define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 9457 | #define regAFMT4_AFMT_INFOFRAME_CONTROL0 0x2513 |
|---|
| 9458 | #define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 |
|---|
| 9459 | #define regAFMT4_AFMT_INTERRUPT_STATUS 0x2514 |
|---|
| 9460 | #define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 |
|---|
| 9461 | #define regAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2515 |
|---|
| 9462 | #define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 |
|---|
| 9463 | #define regAFMT4_AFMT_MEM_PWR 0x2517 |
|---|
| 9464 | #define regAFMT4_AFMT_MEM_PWR_BASE_IDX 2 |
|---|
| 9465 | |
|---|
| 9466 | |
|---|
| 9467 | // addressBlock: dce_dc_dio_dig4_dme_dme_dispdec |
|---|
| 9468 | // base address: 0x16784 |
|---|
| 9469 | #define regDME4_DME_CONTROL 0x2521 |
|---|
| 9470 | #define regDME4_DME_CONTROL_BASE_IDX 2 |
|---|
| 9471 | #define regDME4_DME_MEMORY_CONTROL 0x2522 |
|---|
| 9472 | #define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 |
|---|
| 9473 | |
|---|
| 9474 | |
|---|
| 9475 | // addressBlock: dce_dc_dio_dig4_dispdec |
|---|
| 9476 | // base address: 0x1240 |
|---|
| 9477 | #define regDIG4_DIG_FE_CNTL 0x2523 |
|---|
| 9478 | #define regDIG4_DIG_FE_CNTL_BASE_IDX 2 |
|---|
| 9479 | #define regDIG4_DIG_FE_CLK_CNTL 0x2524 |
|---|
| 9480 | #define regDIG4_DIG_FE_CLK_CNTL_BASE_IDX 2 |
|---|
| 9481 | #define regDIG4_DIG_FE_EN_CNTL 0x2525 |
|---|
| 9482 | #define regDIG4_DIG_FE_EN_CNTL_BASE_IDX 2 |
|---|
| 9483 | #define regDIG4_DIG_OUTPUT_CRC_CNTL 0x2526 |
|---|
| 9484 | #define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 |
|---|
| 9485 | #define regDIG4_DIG_OUTPUT_CRC_RESULT 0x2527 |
|---|
| 9486 | #define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 |
|---|
| 9487 | #define regDIG4_DIG_CLOCK_PATTERN 0x2528 |
|---|
| 9488 | #define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 |
|---|
| 9489 | #define regDIG4_DIG_TEST_PATTERN 0x2529 |
|---|
| 9490 | #define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 |
|---|
| 9491 | #define regDIG4_DIG_RANDOM_PATTERN_SEED 0x252a |
|---|
| 9492 | #define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 |
|---|
| 9493 | #define regDIG4_DIG_FIFO_CTRL0 0x252b |
|---|
| 9494 | #define regDIG4_DIG_FIFO_CTRL0_BASE_IDX 2 |
|---|
| 9495 | #define regDIG4_DIG_FIFO_CTRL1 0x252c |
|---|
| 9496 | #define regDIG4_DIG_FIFO_CTRL1_BASE_IDX 2 |
|---|
| 9497 | #define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x252d |
|---|
| 9498 | #define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 9499 | #define regDIG4_HDMI_CONTROL 0x252e |
|---|
| 9500 | #define regDIG4_HDMI_CONTROL_BASE_IDX 2 |
|---|
| 9501 | #define regDIG4_HDMI_STATUS 0x252f |
|---|
| 9502 | #define regDIG4_HDMI_STATUS_BASE_IDX 2 |
|---|
| 9503 | #define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2530 |
|---|
| 9504 | #define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 9505 | #define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2531 |
|---|
| 9506 | #define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 9507 | #define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2532 |
|---|
| 9508 | #define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 9509 | #define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2533 |
|---|
| 9510 | #define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 |
|---|
| 9511 | #define regDIG4_HDMI_INFOFRAME_CONTROL1 0x2534 |
|---|
| 9512 | #define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 |
|---|
| 9513 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2535 |
|---|
| 9514 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 |
|---|
| 9515 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x2536 |
|---|
| 9516 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 |
|---|
| 9517 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x2537 |
|---|
| 9518 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 |
|---|
| 9519 | #define regDIG4_HDMI_GC 0x2538 |
|---|
| 9520 | #define regDIG4_HDMI_GC_BASE_IDX 2 |
|---|
| 9521 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2539 |
|---|
| 9522 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 |
|---|
| 9523 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x253a |
|---|
| 9524 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 |
|---|
| 9525 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x253b |
|---|
| 9526 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 |
|---|
| 9527 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x253c |
|---|
| 9528 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 |
|---|
| 9529 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x253d |
|---|
| 9530 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 |
|---|
| 9531 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x253e |
|---|
| 9532 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 |
|---|
| 9533 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x253f |
|---|
| 9534 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 |
|---|
| 9535 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x2540 |
|---|
| 9536 | #define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 |
|---|
| 9537 | #define regDIG4_HDMI_DB_CONTROL 0x2541 |
|---|
| 9538 | #define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 |
|---|
| 9539 | #define regDIG4_HDMI_ACR_32_0 0x2542 |
|---|
| 9540 | #define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 |
|---|
| 9541 | #define regDIG4_HDMI_ACR_32_1 0x2543 |
|---|
| 9542 | #define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 |
|---|
| 9543 | #define regDIG4_HDMI_ACR_44_0 0x2544 |
|---|
| 9544 | #define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 |
|---|
| 9545 | #define regDIG4_HDMI_ACR_44_1 0x2545 |
|---|
| 9546 | #define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 |
|---|
| 9547 | #define regDIG4_HDMI_ACR_48_0 0x2546 |
|---|
| 9548 | #define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 |
|---|
| 9549 | #define regDIG4_HDMI_ACR_48_1 0x2547 |
|---|
| 9550 | #define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 |
|---|
| 9551 | #define regDIG4_HDMI_ACR_STATUS_0 0x2548 |
|---|
| 9552 | #define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 |
|---|
| 9553 | #define regDIG4_HDMI_ACR_STATUS_1 0x2549 |
|---|
| 9554 | #define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 |
|---|
| 9555 | #define regDIG4_AFMT_CNTL 0x254a |
|---|
| 9556 | #define regDIG4_AFMT_CNTL_BASE_IDX 2 |
|---|
| 9557 | #define regDIG4_DIG_BE_CLK_CNTL 0x254b |
|---|
| 9558 | #define regDIG4_DIG_BE_CLK_CNTL_BASE_IDX 2 |
|---|
| 9559 | #define regDIG4_DIG_BE_CNTL 0x254c |
|---|
| 9560 | #define regDIG4_DIG_BE_CNTL_BASE_IDX 2 |
|---|
| 9561 | #define regDIG4_DIG_BE_EN_CNTL 0x254d |
|---|
| 9562 | #define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 |
|---|
| 9563 | #define regDIG4_TMDS_CNTL 0x2574 |
|---|
| 9564 | #define regDIG4_TMDS_CNTL_BASE_IDX 2 |
|---|
| 9565 | #define regDIG4_TMDS_CONTROL_CHAR 0x2575 |
|---|
| 9566 | #define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 |
|---|
| 9567 | #define regDIG4_TMDS_CONTROL0_FEEDBACK 0x2576 |
|---|
| 9568 | #define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 |
|---|
| 9569 | #define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x2577 |
|---|
| 9570 | #define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 |
|---|
| 9571 | #define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x2578 |
|---|
| 9572 | #define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 |
|---|
| 9573 | #define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x2579 |
|---|
| 9574 | #define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 |
|---|
| 9575 | #define regDIG4_TMDS_CTL_BITS 0x257b |
|---|
| 9576 | #define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 |
|---|
| 9577 | #define regDIG4_TMDS_DCBALANCER_CONTROL 0x257c |
|---|
| 9578 | #define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 |
|---|
| 9579 | #define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x257d |
|---|
| 9580 | #define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 |
|---|
| 9581 | #define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x257e |
|---|
| 9582 | #define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 |
|---|
| 9583 | #define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x257f |
|---|
| 9584 | #define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 |
|---|
| 9585 | #define regDIG4_DIG_VERSION 0x2581 |
|---|
| 9586 | #define regDIG4_DIG_VERSION_BASE_IDX 2 |
|---|
| 9587 | |
|---|
| 9588 | |
|---|
| 9589 | // addressBlock: dce_dc_dio_dp4_dispdec |
|---|
| 9590 | // base address: 0x1240 |
|---|
| 9591 | #define regDP4_DP_LINK_CNTL 0x25ae |
|---|
| 9592 | #define regDP4_DP_LINK_CNTL_BASE_IDX 2 |
|---|
| 9593 | #define regDP4_DP_PIXEL_FORMAT 0x25af |
|---|
| 9594 | #define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 |
|---|
| 9595 | #define regDP4_DP_MSA_COLORIMETRY 0x25b0 |
|---|
| 9596 | #define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 |
|---|
| 9597 | #define regDP4_DP_CONFIG 0x25b1 |
|---|
| 9598 | #define regDP4_DP_CONFIG_BASE_IDX 2 |
|---|
| 9599 | #define regDP4_DP_VID_STREAM_CNTL 0x25b2 |
|---|
| 9600 | #define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 |
|---|
| 9601 | #define regDP4_DP_STEER_FIFO 0x25b3 |
|---|
| 9602 | #define regDP4_DP_STEER_FIFO_BASE_IDX 2 |
|---|
| 9603 | #define regDP4_DP_MSA_MISC 0x25b4 |
|---|
| 9604 | #define regDP4_DP_MSA_MISC_BASE_IDX 2 |
|---|
| 9605 | #define regDP4_DP_DPHY_INTERNAL_CTRL 0x25b5 |
|---|
| 9606 | #define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
|---|
| 9607 | #define regDP4_DP_VID_TIMING 0x25b6 |
|---|
| 9608 | #define regDP4_DP_VID_TIMING_BASE_IDX 2 |
|---|
| 9609 | #define regDP4_DP_VID_N 0x25b7 |
|---|
| 9610 | #define regDP4_DP_VID_N_BASE_IDX 2 |
|---|
| 9611 | #define regDP4_DP_VID_M 0x25b8 |
|---|
| 9612 | #define regDP4_DP_VID_M_BASE_IDX 2 |
|---|
| 9613 | #define regDP4_DP_LINK_FRAMING_CNTL 0x25b9 |
|---|
| 9614 | #define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 |
|---|
| 9615 | #define regDP4_DP_HBR2_EYE_PATTERN 0x25ba |
|---|
| 9616 | #define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 |
|---|
| 9617 | #define regDP4_DP_VID_MSA_VBID 0x25bb |
|---|
| 9618 | #define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 |
|---|
| 9619 | #define regDP4_DP_VID_INTERRUPT_CNTL 0x25bc |
|---|
| 9620 | #define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 |
|---|
| 9621 | #define regDP4_DP_DPHY_CNTL 0x25bd |
|---|
| 9622 | #define regDP4_DP_DPHY_CNTL_BASE_IDX 2 |
|---|
| 9623 | #define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x25be |
|---|
| 9624 | #define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 |
|---|
| 9625 | #define regDP4_DP_DPHY_SYM0 0x25bf |
|---|
| 9626 | #define regDP4_DP_DPHY_SYM0_BASE_IDX 2 |
|---|
| 9627 | #define regDP4_DP_DPHY_SYM1 0x25c0 |
|---|
| 9628 | #define regDP4_DP_DPHY_SYM1_BASE_IDX 2 |
|---|
| 9629 | #define regDP4_DP_DPHY_SYM2 0x25c1 |
|---|
| 9630 | #define regDP4_DP_DPHY_SYM2_BASE_IDX 2 |
|---|
| 9631 | #define regDP4_DP_DPHY_8B10B_CNTL 0x25c2 |
|---|
| 9632 | #define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 |
|---|
| 9633 | #define regDP4_DP_DPHY_PRBS_CNTL 0x25c3 |
|---|
| 9634 | #define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 |
|---|
| 9635 | #define regDP4_DP_DPHY_SCRAM_CNTL 0x25c4 |
|---|
| 9636 | #define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 |
|---|
| 9637 | #define regDP4_DP_DPHY_CRC_EN 0x25c5 |
|---|
| 9638 | #define regDP4_DP_DPHY_CRC_EN_BASE_IDX 2 |
|---|
| 9639 | #define regDP4_DP_DPHY_CRC_CNTL 0x25c6 |
|---|
| 9640 | #define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 |
|---|
| 9641 | #define regDP4_DP_DPHY_CRC_RESULT 0x25c7 |
|---|
| 9642 | #define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 |
|---|
| 9643 | #define regDP4_DP_DPHY_CRC_MST_CNTL 0x25c8 |
|---|
| 9644 | #define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 |
|---|
| 9645 | #define regDP4_DP_DPHY_CRC_MST_STATUS 0x25c9 |
|---|
| 9646 | #define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 |
|---|
| 9647 | #define regDP4_DP_DPHY_FAST_TRAINING 0x25ca |
|---|
| 9648 | #define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 |
|---|
| 9649 | #define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x25cb |
|---|
| 9650 | #define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 |
|---|
| 9651 | #define regDP4_DP_SEC_CNTL 0x25d1 |
|---|
| 9652 | #define regDP4_DP_SEC_CNTL_BASE_IDX 2 |
|---|
| 9653 | #define regDP4_DP_SEC_CNTL1 0x25d2 |
|---|
| 9654 | #define regDP4_DP_SEC_CNTL1_BASE_IDX 2 |
|---|
| 9655 | #define regDP4_DP_SEC_FRAMING1 0x25d3 |
|---|
| 9656 | #define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 |
|---|
| 9657 | #define regDP4_DP_SEC_FRAMING2 0x25d4 |
|---|
| 9658 | #define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 |
|---|
| 9659 | #define regDP4_DP_SEC_FRAMING3 0x25d5 |
|---|
| 9660 | #define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 |
|---|
| 9661 | #define regDP4_DP_SEC_FRAMING4 0x25d6 |
|---|
| 9662 | #define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 |
|---|
| 9663 | #define regDP4_DP_SEC_AUD_N 0x25d7 |
|---|
| 9664 | #define regDP4_DP_SEC_AUD_N_BASE_IDX 2 |
|---|
| 9665 | #define regDP4_DP_SEC_AUD_N_READBACK 0x25d8 |
|---|
| 9666 | #define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 |
|---|
| 9667 | #define regDP4_DP_SEC_AUD_M 0x25d9 |
|---|
| 9668 | #define regDP4_DP_SEC_AUD_M_BASE_IDX 2 |
|---|
| 9669 | #define regDP4_DP_SEC_AUD_M_READBACK 0x25da |
|---|
| 9670 | #define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 |
|---|
| 9671 | #define regDP4_DP_SEC_TIMESTAMP 0x25db |
|---|
| 9672 | #define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 |
|---|
| 9673 | #define regDP4_DP_SEC_PACKET_CNTL 0x25dc |
|---|
| 9674 | #define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 |
|---|
| 9675 | #define regDP4_DP_MSE_RATE_CNTL 0x25dd |
|---|
| 9676 | #define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 |
|---|
| 9677 | #define regDP4_DP_MSE_RATE_UPDATE 0x25df |
|---|
| 9678 | #define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 |
|---|
| 9679 | #define regDP4_DP_MSE_SAT0 0x25e0 |
|---|
| 9680 | #define regDP4_DP_MSE_SAT0_BASE_IDX 2 |
|---|
| 9681 | #define regDP4_DP_MSE_SAT1 0x25e1 |
|---|
| 9682 | #define regDP4_DP_MSE_SAT1_BASE_IDX 2 |
|---|
| 9683 | #define regDP4_DP_MSE_SAT2 0x25e2 |
|---|
| 9684 | #define regDP4_DP_MSE_SAT2_BASE_IDX 2 |
|---|
| 9685 | #define regDP4_DP_MSE_SAT_UPDATE 0x25e3 |
|---|
| 9686 | #define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 |
|---|
| 9687 | #define regDP4_DP_MSE_LINK_TIMING 0x25e4 |
|---|
| 9688 | #define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 |
|---|
| 9689 | #define regDP4_DP_MSE_MISC_CNTL 0x25e5 |
|---|
| 9690 | #define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 |
|---|
| 9691 | #define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x25ea |
|---|
| 9692 | #define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 |
|---|
| 9693 | #define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x25eb |
|---|
| 9694 | #define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 |
|---|
| 9695 | #define regDP4_DP_MSE_SAT0_STATUS 0x25ed |
|---|
| 9696 | #define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 |
|---|
| 9697 | #define regDP4_DP_MSE_SAT1_STATUS 0x25ee |
|---|
| 9698 | #define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 |
|---|
| 9699 | #define regDP4_DP_MSE_SAT2_STATUS 0x25ef |
|---|
| 9700 | #define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 |
|---|
| 9701 | #define regDP4_DP_DPIA_SPARE 0x25f0 |
|---|
| 9702 | #define regDP4_DP_DPIA_SPARE_BASE_IDX 2 |
|---|
| 9703 | #define regDP4_DP_MSA_TIMING_PARAM1 0x25f2 |
|---|
| 9704 | #define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 |
|---|
| 9705 | #define regDP4_DP_MSA_TIMING_PARAM2 0x25f3 |
|---|
| 9706 | #define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 |
|---|
| 9707 | #define regDP4_DP_MSA_TIMING_PARAM3 0x25f4 |
|---|
| 9708 | #define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 |
|---|
| 9709 | #define regDP4_DP_MSA_TIMING_PARAM4 0x25f5 |
|---|
| 9710 | #define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 |
|---|
| 9711 | #define regDP4_DP_MSO_CNTL 0x25f6 |
|---|
| 9712 | #define regDP4_DP_MSO_CNTL_BASE_IDX 2 |
|---|
| 9713 | #define regDP4_DP_MSO_CNTL1 0x25f7 |
|---|
| 9714 | #define regDP4_DP_MSO_CNTL1_BASE_IDX 2 |
|---|
| 9715 | #define regDP4_DP_DSC_CNTL 0x25f8 |
|---|
| 9716 | #define regDP4_DP_DSC_CNTL_BASE_IDX 2 |
|---|
| 9717 | #define regDP4_DP_SEC_CNTL2 0x25f9 |
|---|
| 9718 | #define regDP4_DP_SEC_CNTL2_BASE_IDX 2 |
|---|
| 9719 | #define regDP4_DP_SEC_CNTL3 0x25fa |
|---|
| 9720 | #define regDP4_DP_SEC_CNTL3_BASE_IDX 2 |
|---|
| 9721 | #define regDP4_DP_SEC_CNTL4 0x25fb |
|---|
| 9722 | #define regDP4_DP_SEC_CNTL4_BASE_IDX 2 |
|---|
| 9723 | #define regDP4_DP_SEC_CNTL5 0x25fc |
|---|
| 9724 | #define regDP4_DP_SEC_CNTL5_BASE_IDX 2 |
|---|
| 9725 | #define regDP4_DP_SEC_CNTL6 0x25fd |
|---|
| 9726 | #define regDP4_DP_SEC_CNTL6_BASE_IDX 2 |
|---|
| 9727 | #define regDP4_DP_SEC_CNTL7 0x25fe |
|---|
| 9728 | #define regDP4_DP_SEC_CNTL7_BASE_IDX 2 |
|---|
| 9729 | #define regDP4_DP_DB_CNTL 0x25ff |
|---|
| 9730 | #define regDP4_DP_DB_CNTL_BASE_IDX 2 |
|---|
| 9731 | #define regDP4_DP_MSA_VBID_MISC 0x2600 |
|---|
| 9732 | #define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 |
|---|
| 9733 | #define regDP4_DP_SEC_METADATA_TRANSMISSION 0x2601 |
|---|
| 9734 | #define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 |
|---|
| 9735 | #define regDP4_DP_ALPM_CNTL 0x2603 |
|---|
| 9736 | #define regDP4_DP_ALPM_CNTL_BASE_IDX 2 |
|---|
| 9737 | #define regDP4_DP_GSP8_CNTL 0x2604 |
|---|
| 9738 | #define regDP4_DP_GSP8_CNTL_BASE_IDX 2 |
|---|
| 9739 | #define regDP4_DP_GSP9_CNTL 0x2605 |
|---|
| 9740 | #define regDP4_DP_GSP9_CNTL_BASE_IDX 2 |
|---|
| 9741 | #define regDP4_DP_GSP10_CNTL 0x2606 |
|---|
| 9742 | #define regDP4_DP_GSP10_CNTL_BASE_IDX 2 |
|---|
| 9743 | #define regDP4_DP_GSP11_CNTL 0x2607 |
|---|
| 9744 | #define regDP4_DP_GSP11_CNTL_BASE_IDX 2 |
|---|
| 9745 | #define regDP4_DP_GSP_EN_DB_STATUS 0x2608 |
|---|
| 9746 | #define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 |
|---|
| 9747 | #define regDP4_DP_AUXLESS_ALPM_CNTL1 0x2609 |
|---|
| 9748 | #define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 |
|---|
| 9749 | #define regDP4_DP_AUXLESS_ALPM_CNTL2 0x260a |
|---|
| 9750 | #define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 |
|---|
| 9751 | #define regDP4_DP_AUXLESS_ALPM_CNTL3 0x260b |
|---|
| 9752 | #define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 |
|---|
| 9753 | #define regDP4_DP_AUXLESS_ALPM_CNTL4 0x260c |
|---|
| 9754 | #define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 |
|---|
| 9755 | #define regDP4_DP_AUXLESS_ALPM_CNTL5 0x260d |
|---|
| 9756 | #define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 |
|---|
| 9757 | #define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS 0x260e |
|---|
| 9758 | #define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 |
|---|
| 9759 | #define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL 0x260f |
|---|
| 9760 | #define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 9761 | #define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0 0x2610 |
|---|
| 9762 | #define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 |
|---|
| 9763 | #define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1 0x2611 |
|---|
| 9764 | #define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 |
|---|
| 9765 | #define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL 0x2612 |
|---|
| 9766 | #define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 9767 | |
|---|
| 9768 | |
|---|
| 9769 | // addressBlock: dce_dc_dcio_dcio_dispdec |
|---|
| 9770 | // base address: 0x0 |
|---|
| 9771 | #define regDC_GENERICA 0x2868 |
|---|
| 9772 | #define regDC_GENERICA_BASE_IDX 2 |
|---|
| 9773 | #define regDC_GENERICB 0x2869 |
|---|
| 9774 | #define regDC_GENERICB_BASE_IDX 2 |
|---|
| 9775 | #define regDCIO_CLOCK_CNTL 0x286a |
|---|
| 9776 | #define regDCIO_CLOCK_CNTL_BASE_IDX 2 |
|---|
| 9777 | #define regDC_REF_CLK_CNTL 0x286b |
|---|
| 9778 | #define regDC_REF_CLK_CNTL_BASE_IDX 2 |
|---|
| 9779 | #define regUNIPHYA_LINK_CNTL 0x286d |
|---|
| 9780 | #define regUNIPHYA_LINK_CNTL_BASE_IDX 2 |
|---|
| 9781 | #define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e |
|---|
| 9782 | #define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
|---|
| 9783 | #define regUNIPHYB_LINK_CNTL 0x286f |
|---|
| 9784 | #define regUNIPHYB_LINK_CNTL_BASE_IDX 2 |
|---|
| 9785 | #define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 |
|---|
| 9786 | #define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
|---|
| 9787 | #define regUNIPHYC_LINK_CNTL 0x2871 |
|---|
| 9788 | #define regUNIPHYC_LINK_CNTL_BASE_IDX 2 |
|---|
| 9789 | #define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 |
|---|
| 9790 | #define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
|---|
| 9791 | #define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 |
|---|
| 9792 | #define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
|---|
| 9793 | #define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 |
|---|
| 9794 | #define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 |
|---|
| 9795 | #define regDCIO_WRCMD_DELAY 0x287e |
|---|
| 9796 | #define regDCIO_WRCMD_DELAY_BASE_IDX 2 |
|---|
| 9797 | #define regDC_PINSTRAPS 0x2880 |
|---|
| 9798 | #define regDC_PINSTRAPS_BASE_IDX 2 |
|---|
| 9799 | #define regDCIO_SPARE 0x2882 |
|---|
| 9800 | #define regDCIO_SPARE_BASE_IDX 2 |
|---|
| 9801 | #define regINTERCEPT_STATE 0x2884 |
|---|
| 9802 | #define regINTERCEPT_STATE_BASE_IDX 2 |
|---|
| 9803 | #define regDCIO_PATTERN_GEN_PAT 0x2886 |
|---|
| 9804 | #define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2 |
|---|
| 9805 | #define regDCIO_PATTERN_GEN_EN 0x2887 |
|---|
| 9806 | #define regDCIO_PATTERN_GEN_EN_BASE_IDX 2 |
|---|
| 9807 | #define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b |
|---|
| 9808 | #define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 |
|---|
| 9809 | #define regDCIO_GSL_GENLK_PAD_CNTL 0x288c |
|---|
| 9810 | #define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 |
|---|
| 9811 | #define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d |
|---|
| 9812 | #define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 |
|---|
| 9813 | #define regDCIO_SOFT_RESET 0x289e |
|---|
| 9814 | #define regDCIO_SOFT_RESET_BASE_IDX 2 |
|---|
| 9815 | |
|---|
| 9816 | |
|---|
| 9817 | // addressBlock: dce_dc_dcio_dcio_chip_dispdec |
|---|
| 9818 | // base address: 0x0 |
|---|
| 9819 | #define regDC_GPIO_GENERIC_MASK 0x28c8 |
|---|
| 9820 | #define regDC_GPIO_GENERIC_MASK_BASE_IDX 2 |
|---|
| 9821 | #define regDC_GPIO_GENERIC_A 0x28c9 |
|---|
| 9822 | #define regDC_GPIO_GENERIC_A_BASE_IDX 2 |
|---|
| 9823 | #define regDC_GPIO_GENERIC_EN 0x28ca |
|---|
| 9824 | #define regDC_GPIO_GENERIC_EN_BASE_IDX 2 |
|---|
| 9825 | #define regDC_GPIO_GENERIC_Y 0x28cb |
|---|
| 9826 | #define regDC_GPIO_GENERIC_Y_BASE_IDX 2 |
|---|
| 9827 | #define regDC_GPIO_DDC1_MASK 0x28d0 |
|---|
| 9828 | #define regDC_GPIO_DDC1_MASK_BASE_IDX 2 |
|---|
| 9829 | #define regDC_GPIO_DDC1_A 0x28d1 |
|---|
| 9830 | #define regDC_GPIO_DDC1_A_BASE_IDX 2 |
|---|
| 9831 | #define regDC_GPIO_DDC1_EN 0x28d2 |
|---|
| 9832 | #define regDC_GPIO_DDC1_EN_BASE_IDX 2 |
|---|
| 9833 | #define regDC_GPIO_DDC1_Y 0x28d3 |
|---|
| 9834 | #define regDC_GPIO_DDC1_Y_BASE_IDX 2 |
|---|
| 9835 | #define regDC_GPIO_DDC2_MASK 0x28d4 |
|---|
| 9836 | #define regDC_GPIO_DDC2_MASK_BASE_IDX 2 |
|---|
| 9837 | #define regDC_GPIO_DDC2_A 0x28d5 |
|---|
| 9838 | #define regDC_GPIO_DDC2_A_BASE_IDX 2 |
|---|
| 9839 | #define regDC_GPIO_DDC2_EN 0x28d6 |
|---|
| 9840 | #define regDC_GPIO_DDC2_EN_BASE_IDX 2 |
|---|
| 9841 | #define regDC_GPIO_DDC2_Y 0x28d7 |
|---|
| 9842 | #define regDC_GPIO_DDC2_Y_BASE_IDX 2 |
|---|
| 9843 | #define regDC_GPIO_DDC3_MASK 0x28d8 |
|---|
| 9844 | #define regDC_GPIO_DDC3_MASK_BASE_IDX 2 |
|---|
| 9845 | #define regDC_GPIO_DDC3_A 0x28d9 |
|---|
| 9846 | #define regDC_GPIO_DDC3_A_BASE_IDX 2 |
|---|
| 9847 | #define regDC_GPIO_DDC3_EN 0x28da |
|---|
| 9848 | #define regDC_GPIO_DDC3_EN_BASE_IDX 2 |
|---|
| 9849 | #define regDC_GPIO_DDC3_Y 0x28db |
|---|
| 9850 | #define regDC_GPIO_DDC3_Y_BASE_IDX 2 |
|---|
| 9851 | #define regDC_GPIO_DDC4_MASK 0x28dc |
|---|
| 9852 | #define regDC_GPIO_DDC4_MASK_BASE_IDX 2 |
|---|
| 9853 | #define regDC_GPIO_DDC4_A 0x28dd |
|---|
| 9854 | #define regDC_GPIO_DDC4_A_BASE_IDX 2 |
|---|
| 9855 | #define regDC_GPIO_DDC4_EN 0x28de |
|---|
| 9856 | #define regDC_GPIO_DDC4_EN_BASE_IDX 2 |
|---|
| 9857 | #define regDC_GPIO_DDC4_Y 0x28df |
|---|
| 9858 | #define regDC_GPIO_DDC4_Y_BASE_IDX 2 |
|---|
| 9859 | #define regDC_GPIO_DDC5_MASK 0x28e0 |
|---|
| 9860 | #define regDC_GPIO_DDC5_MASK_BASE_IDX 2 |
|---|
| 9861 | #define regDC_GPIO_DDC5_A 0x28e1 |
|---|
| 9862 | #define regDC_GPIO_DDC5_A_BASE_IDX 2 |
|---|
| 9863 | #define regDC_GPIO_DDC5_EN 0x28e2 |
|---|
| 9864 | #define regDC_GPIO_DDC5_EN_BASE_IDX 2 |
|---|
| 9865 | #define regDC_GPIO_DDC5_Y 0x28e3 |
|---|
| 9866 | #define regDC_GPIO_DDC5_Y_BASE_IDX 2 |
|---|
| 9867 | #define regDC_GPIO_DDCVGA_MASK 0x28e8 |
|---|
| 9868 | #define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 |
|---|
| 9869 | #define regDC_GPIO_DDCVGA_A 0x28e9 |
|---|
| 9870 | #define regDC_GPIO_DDCVGA_A_BASE_IDX 2 |
|---|
| 9871 | #define regDC_GPIO_DDCVGA_EN 0x28ea |
|---|
| 9872 | #define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 |
|---|
| 9873 | #define regDC_GPIO_DDCVGA_Y 0x28eb |
|---|
| 9874 | #define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 |
|---|
| 9875 | #define regDC_GPIO_GENLK_MASK 0x28f0 |
|---|
| 9876 | #define regDC_GPIO_GENLK_MASK_BASE_IDX 2 |
|---|
| 9877 | #define regDC_GPIO_GENLK_A 0x28f1 |
|---|
| 9878 | #define regDC_GPIO_GENLK_A_BASE_IDX 2 |
|---|
| 9879 | #define regDC_GPIO_GENLK_EN 0x28f2 |
|---|
| 9880 | #define regDC_GPIO_GENLK_EN_BASE_IDX 2 |
|---|
| 9881 | #define regDC_GPIO_GENLK_Y 0x28f3 |
|---|
| 9882 | #define regDC_GPIO_GENLK_Y_BASE_IDX 2 |
|---|
| 9883 | #define regDC_GPIO_HPD_MASK 0x28f4 |
|---|
| 9884 | #define regDC_GPIO_HPD_MASK_BASE_IDX 2 |
|---|
| 9885 | #define regDC_GPIO_HPD_A 0x28f5 |
|---|
| 9886 | #define regDC_GPIO_HPD_A_BASE_IDX 2 |
|---|
| 9887 | #define regDC_GPIO_HPD_EN 0x28f6 |
|---|
| 9888 | #define regDC_GPIO_HPD_EN_BASE_IDX 2 |
|---|
| 9889 | #define regDC_GPIO_HPD_Y 0x28f7 |
|---|
| 9890 | #define regDC_GPIO_HPD_Y_BASE_IDX 2 |
|---|
| 9891 | #define regDC_GPIO_DRIVE_STRENGTH_S0 0x28f8 |
|---|
| 9892 | #define regDC_GPIO_DRIVE_STRENGTH_S0_BASE_IDX 2 |
|---|
| 9893 | #define regDC_GPIO_DRIVE_STRENGTH_S1 0x28f9 |
|---|
| 9894 | #define regDC_GPIO_DRIVE_STRENGTH_S1_BASE_IDX 2 |
|---|
| 9895 | #define regDC_GPIO_PWRSEQ0_EN 0x28fa |
|---|
| 9896 | #define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 |
|---|
| 9897 | #define regDC_GPIO_PAD_STRENGTH_1 0x28fc |
|---|
| 9898 | #define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 |
|---|
| 9899 | #define regDC_GPIO_PAD_STRENGTH_2 0x28fd |
|---|
| 9900 | #define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 |
|---|
| 9901 | #define regPHY_AUX_CNTL 0x28ff |
|---|
| 9902 | #define regPHY_AUX_CNTL_BASE_IDX 2 |
|---|
| 9903 | #define regDC_GPIO_DRIVE_TXIMPSEL 0x2900 |
|---|
| 9904 | #define regDC_GPIO_DRIVE_TXIMPSEL_BASE_IDX 2 |
|---|
| 9905 | #define regDC_GPIO_PWRSEQ1_EN 0x2902 |
|---|
| 9906 | #define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 |
|---|
| 9907 | #define regDC_GPIO_TX12_EN 0x2915 |
|---|
| 9908 | #define regDC_GPIO_TX12_EN_BASE_IDX 2 |
|---|
| 9909 | #define regDC_GPIO_AUX_CTRL_0 0x2916 |
|---|
| 9910 | #define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 |
|---|
| 9911 | #define regDC_GPIO_AUX_CTRL_1 0x2917 |
|---|
| 9912 | #define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 |
|---|
| 9913 | #define regDC_GPIO_AUX_CTRL_2 0x2918 |
|---|
| 9914 | #define regDC_GPIO_AUX_CTRL_2_BASE_IDX 2 |
|---|
| 9915 | #define regDC_GPIO_RXEN 0x2919 |
|---|
| 9916 | #define regDC_GPIO_RXEN_BASE_IDX 2 |
|---|
| 9917 | #define regDC_GPIO_PULLUPEN 0x291a |
|---|
| 9918 | #define regDC_GPIO_PULLUPEN_BASE_IDX 2 |
|---|
| 9919 | #define regDC_GPIO_AUX_CTRL_3 0x291b |
|---|
| 9920 | #define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 |
|---|
| 9921 | #define regDC_GPIO_AUX_CTRL_4 0x291c |
|---|
| 9922 | #define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 |
|---|
| 9923 | #define regDC_GPIO_AUX_CTRL_5 0x291d |
|---|
| 9924 | #define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 |
|---|
| 9925 | #define regAUXI2C_PAD_ALL_PWR_OK 0x291e |
|---|
| 9926 | #define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 |
|---|
| 9927 | |
|---|
| 9928 | |
|---|
| 9929 | // addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec |
|---|
| 9930 | // base address: 0x0 |
|---|
| 9931 | |
|---|
| 9932 | |
|---|
| 9933 | // addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec |
|---|
| 9934 | // base address: 0x360 |
|---|
| 9935 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 |
|---|
| 9936 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 |
|---|
| 9937 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 |
|---|
| 9938 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 |
|---|
| 9939 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 |
|---|
| 9940 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 |
|---|
| 9941 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 |
|---|
| 9942 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 |
|---|
| 9943 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 |
|---|
| 9944 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 |
|---|
| 9945 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 |
|---|
| 9946 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 |
|---|
| 9947 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 |
|---|
| 9948 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 |
|---|
| 9949 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 |
|---|
| 9950 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 |
|---|
| 9951 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 |
|---|
| 9952 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 |
|---|
| 9953 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 |
|---|
| 9954 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 |
|---|
| 9955 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a |
|---|
| 9956 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 |
|---|
| 9957 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b |
|---|
| 9958 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 |
|---|
| 9959 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c |
|---|
| 9960 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 |
|---|
| 9961 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d |
|---|
| 9962 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 |
|---|
| 9963 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e |
|---|
| 9964 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 |
|---|
| 9965 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f |
|---|
| 9966 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 |
|---|
| 9967 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 |
|---|
| 9968 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 |
|---|
| 9969 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 |
|---|
| 9970 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 |
|---|
| 9971 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 |
|---|
| 9972 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 |
|---|
| 9973 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 |
|---|
| 9974 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 |
|---|
| 9975 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 |
|---|
| 9976 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 |
|---|
| 9977 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 |
|---|
| 9978 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 |
|---|
| 9979 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 |
|---|
| 9980 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 |
|---|
| 9981 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 |
|---|
| 9982 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 |
|---|
| 9983 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 |
|---|
| 9984 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 |
|---|
| 9985 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 |
|---|
| 9986 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 |
|---|
| 9987 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a |
|---|
| 9988 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 |
|---|
| 9989 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b |
|---|
| 9990 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 |
|---|
| 9991 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c |
|---|
| 9992 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 |
|---|
| 9993 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d |
|---|
| 9994 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 |
|---|
| 9995 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e |
|---|
| 9996 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 |
|---|
| 9997 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f |
|---|
| 9998 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 |
|---|
| 9999 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 |
|---|
| 10000 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 |
|---|
| 10001 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 |
|---|
| 10002 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 |
|---|
| 10003 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 |
|---|
| 10004 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 |
|---|
| 10005 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 |
|---|
| 10006 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 |
|---|
| 10007 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 |
|---|
| 10008 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 |
|---|
| 10009 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 |
|---|
| 10010 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 |
|---|
| 10011 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 |
|---|
| 10012 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 |
|---|
| 10013 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 |
|---|
| 10014 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 |
|---|
| 10015 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 |
|---|
| 10016 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 |
|---|
| 10017 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 |
|---|
| 10018 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 |
|---|
| 10019 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a |
|---|
| 10020 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 |
|---|
| 10021 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b |
|---|
| 10022 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 |
|---|
| 10023 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c |
|---|
| 10024 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 |
|---|
| 10025 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d |
|---|
| 10026 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 |
|---|
| 10027 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e |
|---|
| 10028 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 |
|---|
| 10029 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f |
|---|
| 10030 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 |
|---|
| 10031 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 |
|---|
| 10032 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 |
|---|
| 10033 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 |
|---|
| 10034 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 |
|---|
| 10035 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 |
|---|
| 10036 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 |
|---|
| 10037 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 |
|---|
| 10038 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 |
|---|
| 10039 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 |
|---|
| 10040 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 |
|---|
| 10041 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 |
|---|
| 10042 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 |
|---|
| 10043 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 |
|---|
| 10044 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 |
|---|
| 10045 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 |
|---|
| 10046 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 |
|---|
| 10047 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 |
|---|
| 10048 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 |
|---|
| 10049 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 |
|---|
| 10050 | #define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 |
|---|
| 10051 | |
|---|
| 10052 | |
|---|
| 10053 | // addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec |
|---|
| 10054 | // base address: 0x6c0 |
|---|
| 10055 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 |
|---|
| 10056 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 |
|---|
| 10057 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 |
|---|
| 10058 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 |
|---|
| 10059 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada |
|---|
| 10060 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 |
|---|
| 10061 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb |
|---|
| 10062 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 |
|---|
| 10063 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc |
|---|
| 10064 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 |
|---|
| 10065 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add |
|---|
| 10066 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 |
|---|
| 10067 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade |
|---|
| 10068 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 |
|---|
| 10069 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf |
|---|
| 10070 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 |
|---|
| 10071 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 |
|---|
| 10072 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 |
|---|
| 10073 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 |
|---|
| 10074 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 |
|---|
| 10075 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 |
|---|
| 10076 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 |
|---|
| 10077 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 |
|---|
| 10078 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 |
|---|
| 10079 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 |
|---|
| 10080 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 |
|---|
| 10081 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 |
|---|
| 10082 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 |
|---|
| 10083 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 |
|---|
| 10084 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 |
|---|
| 10085 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 |
|---|
| 10086 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 |
|---|
| 10087 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 |
|---|
| 10088 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 |
|---|
| 10089 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 |
|---|
| 10090 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 |
|---|
| 10091 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea |
|---|
| 10092 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 |
|---|
| 10093 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb |
|---|
| 10094 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 |
|---|
| 10095 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec |
|---|
| 10096 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 |
|---|
| 10097 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed |
|---|
| 10098 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 |
|---|
| 10099 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee |
|---|
| 10100 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 |
|---|
| 10101 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef |
|---|
| 10102 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 |
|---|
| 10103 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 |
|---|
| 10104 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 |
|---|
| 10105 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 |
|---|
| 10106 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 |
|---|
| 10107 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 |
|---|
| 10108 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 |
|---|
| 10109 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 |
|---|
| 10110 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 |
|---|
| 10111 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 |
|---|
| 10112 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 |
|---|
| 10113 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 |
|---|
| 10114 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 |
|---|
| 10115 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 |
|---|
| 10116 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 |
|---|
| 10117 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 |
|---|
| 10118 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 |
|---|
| 10119 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 |
|---|
| 10120 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 |
|---|
| 10121 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 |
|---|
| 10122 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 |
|---|
| 10123 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa |
|---|
| 10124 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 |
|---|
| 10125 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb |
|---|
| 10126 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 |
|---|
| 10127 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc |
|---|
| 10128 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 |
|---|
| 10129 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd |
|---|
| 10130 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 |
|---|
| 10131 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe |
|---|
| 10132 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 |
|---|
| 10133 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff |
|---|
| 10134 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 |
|---|
| 10135 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 |
|---|
| 10136 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 |
|---|
| 10137 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 |
|---|
| 10138 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 |
|---|
| 10139 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 |
|---|
| 10140 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 |
|---|
| 10141 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 |
|---|
| 10142 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 |
|---|
| 10143 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 |
|---|
| 10144 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 |
|---|
| 10145 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 |
|---|
| 10146 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 |
|---|
| 10147 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 |
|---|
| 10148 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 |
|---|
| 10149 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 |
|---|
| 10150 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 |
|---|
| 10151 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 |
|---|
| 10152 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 |
|---|
| 10153 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 |
|---|
| 10154 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 |
|---|
| 10155 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a |
|---|
| 10156 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 |
|---|
| 10157 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b |
|---|
| 10158 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 |
|---|
| 10159 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c |
|---|
| 10160 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 |
|---|
| 10161 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d |
|---|
| 10162 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 |
|---|
| 10163 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e |
|---|
| 10164 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 |
|---|
| 10165 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f |
|---|
| 10166 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 |
|---|
| 10167 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 |
|---|
| 10168 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 |
|---|
| 10169 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 |
|---|
| 10170 | #define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 |
|---|
| 10171 | |
|---|
| 10172 | |
|---|
| 10173 | // addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec |
|---|
| 10174 | // base address: 0xa20 |
|---|
| 10175 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 |
|---|
| 10176 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 |
|---|
| 10177 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 |
|---|
| 10178 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 |
|---|
| 10179 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 |
|---|
| 10180 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 |
|---|
| 10181 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 |
|---|
| 10182 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 |
|---|
| 10183 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 |
|---|
| 10184 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 |
|---|
| 10185 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 |
|---|
| 10186 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 |
|---|
| 10187 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 |
|---|
| 10188 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 |
|---|
| 10189 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 |
|---|
| 10190 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 |
|---|
| 10191 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 |
|---|
| 10192 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 |
|---|
| 10193 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 |
|---|
| 10194 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 |
|---|
| 10195 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba |
|---|
| 10196 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 |
|---|
| 10197 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb |
|---|
| 10198 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 |
|---|
| 10199 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc |
|---|
| 10200 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 |
|---|
| 10201 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd |
|---|
| 10202 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 |
|---|
| 10203 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe |
|---|
| 10204 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 |
|---|
| 10205 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf |
|---|
| 10206 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 |
|---|
| 10207 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 |
|---|
| 10208 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 |
|---|
| 10209 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 |
|---|
| 10210 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 |
|---|
| 10211 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 |
|---|
| 10212 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 |
|---|
| 10213 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 |
|---|
| 10214 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 |
|---|
| 10215 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 |
|---|
| 10216 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 |
|---|
| 10217 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 |
|---|
| 10218 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 |
|---|
| 10219 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 |
|---|
| 10220 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 |
|---|
| 10221 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 |
|---|
| 10222 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 |
|---|
| 10223 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 |
|---|
| 10224 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 |
|---|
| 10225 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 |
|---|
| 10226 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 |
|---|
| 10227 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca |
|---|
| 10228 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 |
|---|
| 10229 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb |
|---|
| 10230 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 |
|---|
| 10231 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc |
|---|
| 10232 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 |
|---|
| 10233 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd |
|---|
| 10234 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 |
|---|
| 10235 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce |
|---|
| 10236 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 |
|---|
| 10237 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf |
|---|
| 10238 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 |
|---|
| 10239 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 |
|---|
| 10240 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 |
|---|
| 10241 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 |
|---|
| 10242 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 |
|---|
| 10243 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 |
|---|
| 10244 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 |
|---|
| 10245 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 |
|---|
| 10246 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 |
|---|
| 10247 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 |
|---|
| 10248 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 |
|---|
| 10249 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 |
|---|
| 10250 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 |
|---|
| 10251 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 |
|---|
| 10252 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 |
|---|
| 10253 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 |
|---|
| 10254 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 |
|---|
| 10255 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 |
|---|
| 10256 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 |
|---|
| 10257 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 |
|---|
| 10258 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 |
|---|
| 10259 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda |
|---|
| 10260 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 |
|---|
| 10261 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb |
|---|
| 10262 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 |
|---|
| 10263 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc |
|---|
| 10264 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 |
|---|
| 10265 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd |
|---|
| 10266 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 |
|---|
| 10267 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde |
|---|
| 10268 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 |
|---|
| 10269 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf |
|---|
| 10270 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 |
|---|
| 10271 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 |
|---|
| 10272 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 |
|---|
| 10273 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 |
|---|
| 10274 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 |
|---|
| 10275 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 |
|---|
| 10276 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 |
|---|
| 10277 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 |
|---|
| 10278 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 |
|---|
| 10279 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 |
|---|
| 10280 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 |
|---|
| 10281 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 |
|---|
| 10282 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 |
|---|
| 10283 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 |
|---|
| 10284 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 |
|---|
| 10285 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 |
|---|
| 10286 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 |
|---|
| 10287 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 |
|---|
| 10288 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 |
|---|
| 10289 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 |
|---|
| 10290 | #define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 |
|---|
| 10291 | |
|---|
| 10292 | |
|---|
| 10293 | // addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec |
|---|
| 10294 | // base address: 0xd80 |
|---|
| 10295 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88 |
|---|
| 10296 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 |
|---|
| 10297 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89 |
|---|
| 10298 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 |
|---|
| 10299 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a |
|---|
| 10300 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 |
|---|
| 10301 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b |
|---|
| 10302 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 |
|---|
| 10303 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c |
|---|
| 10304 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 |
|---|
| 10305 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d |
|---|
| 10306 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 |
|---|
| 10307 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e |
|---|
| 10308 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 |
|---|
| 10309 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f |
|---|
| 10310 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 |
|---|
| 10311 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90 |
|---|
| 10312 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 |
|---|
| 10313 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91 |
|---|
| 10314 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 |
|---|
| 10315 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92 |
|---|
| 10316 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 |
|---|
| 10317 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93 |
|---|
| 10318 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 |
|---|
| 10319 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94 |
|---|
| 10320 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 |
|---|
| 10321 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95 |
|---|
| 10322 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 |
|---|
| 10323 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96 |
|---|
| 10324 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 |
|---|
| 10325 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97 |
|---|
| 10326 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 |
|---|
| 10327 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98 |
|---|
| 10328 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 |
|---|
| 10329 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99 |
|---|
| 10330 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 |
|---|
| 10331 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a |
|---|
| 10332 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 |
|---|
| 10333 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b |
|---|
| 10334 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 |
|---|
| 10335 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c |
|---|
| 10336 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 |
|---|
| 10337 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d |
|---|
| 10338 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 |
|---|
| 10339 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e |
|---|
| 10340 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 |
|---|
| 10341 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f |
|---|
| 10342 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 |
|---|
| 10343 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0 |
|---|
| 10344 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 |
|---|
| 10345 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1 |
|---|
| 10346 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 |
|---|
| 10347 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2 |
|---|
| 10348 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 |
|---|
| 10349 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3 |
|---|
| 10350 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 |
|---|
| 10351 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4 |
|---|
| 10352 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 |
|---|
| 10353 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5 |
|---|
| 10354 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 |
|---|
| 10355 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6 |
|---|
| 10356 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 |
|---|
| 10357 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7 |
|---|
| 10358 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 |
|---|
| 10359 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8 |
|---|
| 10360 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 |
|---|
| 10361 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9 |
|---|
| 10362 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 |
|---|
| 10363 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa |
|---|
| 10364 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 |
|---|
| 10365 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab |
|---|
| 10366 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 |
|---|
| 10367 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac |
|---|
| 10368 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 |
|---|
| 10369 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad |
|---|
| 10370 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 |
|---|
| 10371 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae |
|---|
| 10372 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 |
|---|
| 10373 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf |
|---|
| 10374 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 |
|---|
| 10375 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0 |
|---|
| 10376 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 |
|---|
| 10377 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1 |
|---|
| 10378 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 |
|---|
| 10379 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2 |
|---|
| 10380 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 |
|---|
| 10381 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3 |
|---|
| 10382 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 |
|---|
| 10383 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4 |
|---|
| 10384 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 |
|---|
| 10385 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5 |
|---|
| 10386 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 |
|---|
| 10387 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6 |
|---|
| 10388 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 |
|---|
| 10389 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7 |
|---|
| 10390 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 |
|---|
| 10391 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48 0x2cb8 |
|---|
| 10392 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 |
|---|
| 10393 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49 0x2cb9 |
|---|
| 10394 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 |
|---|
| 10395 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50 0x2cba |
|---|
| 10396 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 |
|---|
| 10397 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51 0x2cbb |
|---|
| 10398 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 |
|---|
| 10399 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52 0x2cbc |
|---|
| 10400 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 |
|---|
| 10401 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53 0x2cbd |
|---|
| 10402 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 |
|---|
| 10403 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54 0x2cbe |
|---|
| 10404 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 |
|---|
| 10405 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55 0x2cbf |
|---|
| 10406 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 |
|---|
| 10407 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56 0x2cc0 |
|---|
| 10408 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 |
|---|
| 10409 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57 0x2cc1 |
|---|
| 10410 | #define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 |
|---|
| 10411 | |
|---|
| 10412 | |
|---|
| 10413 | // addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec |
|---|
| 10414 | // base address: 0x0 |
|---|
| 10415 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0x2f10 |
|---|
| 10416 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 |
|---|
| 10417 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0x2f11 |
|---|
| 10418 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 |
|---|
| 10419 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0x2f12 |
|---|
| 10420 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 |
|---|
| 10421 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0x2f13 |
|---|
| 10422 | #define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 |
|---|
| 10423 | #define regPWRSEQ0_PANEL_PWRSEQ_CNTL 0x2f14 |
|---|
| 10424 | #define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX 2 |
|---|
| 10425 | #define regPWRSEQ0_PANEL_PWRSEQ_STATE 0x2f15 |
|---|
| 10426 | #define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX 2 |
|---|
| 10427 | #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0x2f16 |
|---|
| 10428 | #define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 |
|---|
| 10429 | #define regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0x2f17 |
|---|
| 10430 | #define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 |
|---|
| 10431 | #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0x2f18 |
|---|
| 10432 | #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 |
|---|
| 10433 | #define regPWRSEQ0_BL_PWM_CNTL 0x2f19 |
|---|
| 10434 | #define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2 |
|---|
| 10435 | #define regPWRSEQ0_BL_PWM_CNTL2 0x2f1a |
|---|
| 10436 | #define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX 2 |
|---|
| 10437 | #define regPWRSEQ0_BL_PWM_PERIOD_CNTL 0x2f1b |
|---|
| 10438 | #define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX 2 |
|---|
| 10439 | #define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0x2f1c |
|---|
| 10440 | #define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 |
|---|
| 10441 | #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0x2f1d |
|---|
| 10442 | #define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 |
|---|
| 10443 | #define regPWRSEQ0_PWRSEQ_SPARE 0x2f21 |
|---|
| 10444 | #define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX 2 |
|---|
| 10445 | |
|---|
| 10446 | |
|---|
| 10447 | // addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec |
|---|
| 10448 | // base address: 0x1b0 |
|---|
| 10449 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0x2f7c |
|---|
| 10450 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX 2 |
|---|
| 10451 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0x2f7d |
|---|
| 10452 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2 |
|---|
| 10453 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0x2f7e |
|---|
| 10454 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2 |
|---|
| 10455 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0x2f7f |
|---|
| 10456 | #define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2 |
|---|
| 10457 | #define regPWRSEQ1_PANEL_PWRSEQ_CNTL 0x2f80 |
|---|
| 10458 | #define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX 2 |
|---|
| 10459 | #define regPWRSEQ1_PANEL_PWRSEQ_STATE 0x2f81 |
|---|
| 10460 | #define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX 2 |
|---|
| 10461 | #define regPWRSEQ1_PANEL_PWRSEQ_DELAY1 0x2f82 |
|---|
| 10462 | #define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX 2 |
|---|
| 10463 | #define regPWRSEQ1_PANEL_PWRSEQ_DELAY2 0x2f83 |
|---|
| 10464 | #define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX 2 |
|---|
| 10465 | #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1 0x2f84 |
|---|
| 10466 | #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2 |
|---|
| 10467 | #define regPWRSEQ1_BL_PWM_CNTL 0x2f85 |
|---|
| 10468 | #define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX 2 |
|---|
| 10469 | #define regPWRSEQ1_BL_PWM_CNTL2 0x2f86 |
|---|
| 10470 | #define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX 2 |
|---|
| 10471 | #define regPWRSEQ1_BL_PWM_PERIOD_CNTL 0x2f87 |
|---|
| 10472 | #define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX 2 |
|---|
| 10473 | #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK 0x2f88 |
|---|
| 10474 | #define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2 |
|---|
| 10475 | #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2 0x2f89 |
|---|
| 10476 | #define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2 |
|---|
| 10477 | #define regPWRSEQ1_PWRSEQ_SPARE 0x2f8d |
|---|
| 10478 | #define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX 2 |
|---|
| 10479 | |
|---|
| 10480 | |
|---|
| 10481 | // addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec |
|---|
| 10482 | // base address: 0x0 |
|---|
| 10483 | #define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 |
|---|
| 10484 | #define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 |
|---|
| 10485 | #define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 |
|---|
| 10486 | #define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 |
|---|
| 10487 | |
|---|
| 10488 | |
|---|
| 10489 | // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec |
|---|
| 10490 | // base address: 0x0 |
|---|
| 10491 | #define regDSCCIF0_DSCCIF_CONFIG0 0x3005 |
|---|
| 10492 | #define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 |
|---|
| 10493 | #define regDSCCIF0_DSCCIF_CONFIG1 0x3006 |
|---|
| 10494 | #define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2 |
|---|
| 10495 | |
|---|
| 10496 | |
|---|
| 10497 | // addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec |
|---|
| 10498 | // base address: 0x0 |
|---|
| 10499 | #define regDSCC0_DSCC_CONFIG0 0x300a |
|---|
| 10500 | #define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 |
|---|
| 10501 | #define regDSCC0_DSCC_CONFIG1 0x300b |
|---|
| 10502 | #define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 |
|---|
| 10503 | #define regDSCC0_DSCC_STATUS 0x300c |
|---|
| 10504 | #define regDSCC0_DSCC_STATUS_BASE_IDX 2 |
|---|
| 10505 | #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d |
|---|
| 10506 | #define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 |
|---|
| 10507 | #define regDSCC0_DSCC_PPS_CONFIG0 0x300e |
|---|
| 10508 | #define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 |
|---|
| 10509 | #define regDSCC0_DSCC_PPS_CONFIG1 0x300f |
|---|
| 10510 | #define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 |
|---|
| 10511 | #define regDSCC0_DSCC_PPS_CONFIG2 0x3010 |
|---|
| 10512 | #define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 |
|---|
| 10513 | #define regDSCC0_DSCC_PPS_CONFIG3 0x3011 |
|---|
| 10514 | #define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 |
|---|
| 10515 | #define regDSCC0_DSCC_PPS_CONFIG4 0x3012 |
|---|
| 10516 | #define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 |
|---|
| 10517 | #define regDSCC0_DSCC_PPS_CONFIG5 0x3013 |
|---|
| 10518 | #define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 |
|---|
| 10519 | #define regDSCC0_DSCC_PPS_CONFIG6 0x3014 |
|---|
| 10520 | #define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 |
|---|
| 10521 | #define regDSCC0_DSCC_PPS_CONFIG7 0x3015 |
|---|
| 10522 | #define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 |
|---|
| 10523 | #define regDSCC0_DSCC_PPS_CONFIG8 0x3016 |
|---|
| 10524 | #define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 |
|---|
| 10525 | #define regDSCC0_DSCC_PPS_CONFIG9 0x3017 |
|---|
| 10526 | #define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 |
|---|
| 10527 | #define regDSCC0_DSCC_PPS_CONFIG10 0x3018 |
|---|
| 10528 | #define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 |
|---|
| 10529 | #define regDSCC0_DSCC_PPS_CONFIG11 0x3019 |
|---|
| 10530 | #define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 |
|---|
| 10531 | #define regDSCC0_DSCC_PPS_CONFIG12 0x301a |
|---|
| 10532 | #define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 |
|---|
| 10533 | #define regDSCC0_DSCC_PPS_CONFIG13 0x301b |
|---|
| 10534 | #define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 |
|---|
| 10535 | #define regDSCC0_DSCC_PPS_CONFIG14 0x301c |
|---|
| 10536 | #define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 |
|---|
| 10537 | #define regDSCC0_DSCC_PPS_CONFIG15 0x301d |
|---|
| 10538 | #define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 |
|---|
| 10539 | #define regDSCC0_DSCC_PPS_CONFIG16 0x301e |
|---|
| 10540 | #define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 |
|---|
| 10541 | #define regDSCC0_DSCC_PPS_CONFIG17 0x301f |
|---|
| 10542 | #define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 |
|---|
| 10543 | #define regDSCC0_DSCC_PPS_CONFIG18 0x3020 |
|---|
| 10544 | #define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 |
|---|
| 10545 | #define regDSCC0_DSCC_PPS_CONFIG19 0x3021 |
|---|
| 10546 | #define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 |
|---|
| 10547 | #define regDSCC0_DSCC_PPS_CONFIG20 0x3022 |
|---|
| 10548 | #define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 |
|---|
| 10549 | #define regDSCC0_DSCC_PPS_CONFIG21 0x3023 |
|---|
| 10550 | #define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 |
|---|
| 10551 | #define regDSCC0_DSCC_PPS_CONFIG22 0x3024 |
|---|
| 10552 | #define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 |
|---|
| 10553 | #define regDSCC0_DSCC_MEM_POWER_CONTROL 0x3025 |
|---|
| 10554 | #define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 |
|---|
| 10555 | #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026 |
|---|
| 10556 | #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 |
|---|
| 10557 | #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027 |
|---|
| 10558 | #define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 |
|---|
| 10559 | #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028 |
|---|
| 10560 | #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 |
|---|
| 10561 | #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029 |
|---|
| 10562 | #define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 |
|---|
| 10563 | #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a |
|---|
| 10564 | #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 |
|---|
| 10565 | #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b |
|---|
| 10566 | #define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 |
|---|
| 10567 | #define regDSCC0_DSCC_MAX_ABS_ERROR0 0x302c |
|---|
| 10568 | #define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 |
|---|
| 10569 | #define regDSCC0_DSCC_MAX_ABS_ERROR1 0x302d |
|---|
| 10570 | #define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 |
|---|
| 10571 | #define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e |
|---|
| 10572 | #define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10573 | #define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f |
|---|
| 10574 | #define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10575 | #define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030 |
|---|
| 10576 | #define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10577 | #define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031 |
|---|
| 10578 | #define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10579 | #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032 |
|---|
| 10580 | #define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10581 | #define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033 |
|---|
| 10582 | #define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10583 | #define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034 |
|---|
| 10584 | #define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10585 | #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035 |
|---|
| 10586 | #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10587 | #define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a |
|---|
| 10588 | #define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 |
|---|
| 10589 | |
|---|
| 10590 | |
|---|
| 10591 | // addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec |
|---|
| 10592 | // base address: 0xc140 |
|---|
| 10593 | #define regDC_PERFMON19_PERFCOUNTER_CNTL 0x3050 |
|---|
| 10594 | #define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 10595 | #define regDC_PERFMON19_PERFCOUNTER_CNTL2 0x3051 |
|---|
| 10596 | #define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 10597 | #define regDC_PERFMON19_PERFCOUNTER_STATE 0x3052 |
|---|
| 10598 | #define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 10599 | #define regDC_PERFMON19_PERFMON_CNTL 0x3053 |
|---|
| 10600 | #define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 10601 | #define regDC_PERFMON19_PERFMON_CNTL2 0x3054 |
|---|
| 10602 | #define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 10603 | #define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x3055 |
|---|
| 10604 | #define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 10605 | #define regDC_PERFMON19_PERFMON_CVALUE_LOW 0x3056 |
|---|
| 10606 | #define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 10607 | #define regDC_PERFMON19_PERFMON_HI 0x3057 |
|---|
| 10608 | #define regDC_PERFMON19_PERFMON_HI_BASE_IDX 2 |
|---|
| 10609 | #define regDC_PERFMON19_PERFMON_LOW 0x3058 |
|---|
| 10610 | #define regDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 |
|---|
| 10611 | |
|---|
| 10612 | |
|---|
| 10613 | // addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec |
|---|
| 10614 | // base address: 0x170 |
|---|
| 10615 | #define regDSC_TOP1_DSC_TOP_CONTROL 0x305c |
|---|
| 10616 | #define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 |
|---|
| 10617 | #define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d |
|---|
| 10618 | #define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 |
|---|
| 10619 | |
|---|
| 10620 | // addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec |
|---|
| 10621 | // base address: 0x170 |
|---|
| 10622 | #define regDSCCIF1_DSCCIF_CONFIG0 0x3061 |
|---|
| 10623 | #define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 |
|---|
| 10624 | #define regDSCCIF1_DSCCIF_CONFIG1 0x3062 |
|---|
| 10625 | #define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2 |
|---|
| 10626 | |
|---|
| 10627 | |
|---|
| 10628 | // addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec |
|---|
| 10629 | // base address: 0x170 |
|---|
| 10630 | #define regDSCC1_DSCC_CONFIG0 0x3066 |
|---|
| 10631 | #define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 |
|---|
| 10632 | #define regDSCC1_DSCC_CONFIG1 0x3067 |
|---|
| 10633 | #define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 |
|---|
| 10634 | #define regDSCC1_DSCC_STATUS 0x3068 |
|---|
| 10635 | #define regDSCC1_DSCC_STATUS_BASE_IDX 2 |
|---|
| 10636 | #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069 |
|---|
| 10637 | #define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 |
|---|
| 10638 | #define regDSCC1_DSCC_PPS_CONFIG0 0x306a |
|---|
| 10639 | #define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 |
|---|
| 10640 | #define regDSCC1_DSCC_PPS_CONFIG1 0x306b |
|---|
| 10641 | #define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 |
|---|
| 10642 | #define regDSCC1_DSCC_PPS_CONFIG2 0x306c |
|---|
| 10643 | #define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 |
|---|
| 10644 | #define regDSCC1_DSCC_PPS_CONFIG3 0x306d |
|---|
| 10645 | #define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 |
|---|
| 10646 | #define regDSCC1_DSCC_PPS_CONFIG4 0x306e |
|---|
| 10647 | #define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 |
|---|
| 10648 | #define regDSCC1_DSCC_PPS_CONFIG5 0x306f |
|---|
| 10649 | #define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 |
|---|
| 10650 | #define regDSCC1_DSCC_PPS_CONFIG6 0x3070 |
|---|
| 10651 | #define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 |
|---|
| 10652 | #define regDSCC1_DSCC_PPS_CONFIG7 0x3071 |
|---|
| 10653 | #define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 |
|---|
| 10654 | #define regDSCC1_DSCC_PPS_CONFIG8 0x3072 |
|---|
| 10655 | #define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 |
|---|
| 10656 | #define regDSCC1_DSCC_PPS_CONFIG9 0x3073 |
|---|
| 10657 | #define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 |
|---|
| 10658 | #define regDSCC1_DSCC_PPS_CONFIG10 0x3074 |
|---|
| 10659 | #define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 |
|---|
| 10660 | #define regDSCC1_DSCC_PPS_CONFIG11 0x3075 |
|---|
| 10661 | #define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 |
|---|
| 10662 | #define regDSCC1_DSCC_PPS_CONFIG12 0x3076 |
|---|
| 10663 | #define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 |
|---|
| 10664 | #define regDSCC1_DSCC_PPS_CONFIG13 0x3077 |
|---|
| 10665 | #define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 |
|---|
| 10666 | #define regDSCC1_DSCC_PPS_CONFIG14 0x3078 |
|---|
| 10667 | #define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 |
|---|
| 10668 | #define regDSCC1_DSCC_PPS_CONFIG15 0x3079 |
|---|
| 10669 | #define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 |
|---|
| 10670 | #define regDSCC1_DSCC_PPS_CONFIG16 0x307a |
|---|
| 10671 | #define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 |
|---|
| 10672 | #define regDSCC1_DSCC_PPS_CONFIG17 0x307b |
|---|
| 10673 | #define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 |
|---|
| 10674 | #define regDSCC1_DSCC_PPS_CONFIG18 0x307c |
|---|
| 10675 | #define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 |
|---|
| 10676 | #define regDSCC1_DSCC_PPS_CONFIG19 0x307d |
|---|
| 10677 | #define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 |
|---|
| 10678 | #define regDSCC1_DSCC_PPS_CONFIG20 0x307e |
|---|
| 10679 | #define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 |
|---|
| 10680 | #define regDSCC1_DSCC_PPS_CONFIG21 0x307f |
|---|
| 10681 | #define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 |
|---|
| 10682 | #define regDSCC1_DSCC_PPS_CONFIG22 0x3080 |
|---|
| 10683 | #define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 |
|---|
| 10684 | #define regDSCC1_DSCC_MEM_POWER_CONTROL 0x3081 |
|---|
| 10685 | #define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 |
|---|
| 10686 | #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082 |
|---|
| 10687 | #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 |
|---|
| 10688 | #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083 |
|---|
| 10689 | #define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 |
|---|
| 10690 | #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084 |
|---|
| 10691 | #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 |
|---|
| 10692 | #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085 |
|---|
| 10693 | #define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 |
|---|
| 10694 | #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086 |
|---|
| 10695 | #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 |
|---|
| 10696 | #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087 |
|---|
| 10697 | #define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 |
|---|
| 10698 | #define regDSCC1_DSCC_MAX_ABS_ERROR0 0x3088 |
|---|
| 10699 | #define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 |
|---|
| 10700 | #define regDSCC1_DSCC_MAX_ABS_ERROR1 0x3089 |
|---|
| 10701 | #define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 |
|---|
| 10702 | #define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a |
|---|
| 10703 | #define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10704 | #define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b |
|---|
| 10705 | #define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10706 | #define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c |
|---|
| 10707 | #define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10708 | #define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d |
|---|
| 10709 | #define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10710 | #define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e |
|---|
| 10711 | #define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10712 | #define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f |
|---|
| 10713 | #define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10714 | #define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090 |
|---|
| 10715 | #define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10716 | #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091 |
|---|
| 10717 | #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10718 | #define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096 |
|---|
| 10719 | #define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 |
|---|
| 10720 | |
|---|
| 10721 | |
|---|
| 10722 | // addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec |
|---|
| 10723 | // base address: 0xc2b0 |
|---|
| 10724 | #define regDC_PERFMON20_PERFCOUNTER_CNTL 0x30ac |
|---|
| 10725 | #define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 10726 | #define regDC_PERFMON20_PERFCOUNTER_CNTL2 0x30ad |
|---|
| 10727 | #define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 10728 | #define regDC_PERFMON20_PERFCOUNTER_STATE 0x30ae |
|---|
| 10729 | #define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 10730 | #define regDC_PERFMON20_PERFMON_CNTL 0x30af |
|---|
| 10731 | #define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 10732 | #define regDC_PERFMON20_PERFMON_CNTL2 0x30b0 |
|---|
| 10733 | #define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 10734 | #define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x30b1 |
|---|
| 10735 | #define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 10736 | #define regDC_PERFMON20_PERFMON_CVALUE_LOW 0x30b2 |
|---|
| 10737 | #define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 10738 | #define regDC_PERFMON20_PERFMON_HI 0x30b3 |
|---|
| 10739 | #define regDC_PERFMON20_PERFMON_HI_BASE_IDX 2 |
|---|
| 10740 | #define regDC_PERFMON20_PERFMON_LOW 0x30b4 |
|---|
| 10741 | #define regDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 |
|---|
| 10742 | |
|---|
| 10743 | |
|---|
| 10744 | // addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec |
|---|
| 10745 | // base address: 0x2e0 |
|---|
| 10746 | #define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 |
|---|
| 10747 | #define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 |
|---|
| 10748 | #define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 |
|---|
| 10749 | #define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 |
|---|
| 10750 | |
|---|
| 10751 | |
|---|
| 10752 | // addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec |
|---|
| 10753 | // base address: 0x2e0 |
|---|
| 10754 | #define regDSCCIF2_DSCCIF_CONFIG0 0x30bd |
|---|
| 10755 | #define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 |
|---|
| 10756 | #define regDSCCIF2_DSCCIF_CONFIG1 0x30be |
|---|
| 10757 | #define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2 |
|---|
| 10758 | |
|---|
| 10759 | |
|---|
| 10760 | // addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec |
|---|
| 10761 | // base address: 0x2e0 |
|---|
| 10762 | #define regDSCC2_DSCC_CONFIG0 0x30c2 |
|---|
| 10763 | #define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 |
|---|
| 10764 | #define regDSCC2_DSCC_CONFIG1 0x30c3 |
|---|
| 10765 | #define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 |
|---|
| 10766 | #define regDSCC2_DSCC_STATUS 0x30c4 |
|---|
| 10767 | #define regDSCC2_DSCC_STATUS_BASE_IDX 2 |
|---|
| 10768 | #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5 |
|---|
| 10769 | #define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 |
|---|
| 10770 | #define regDSCC2_DSCC_PPS_CONFIG0 0x30c6 |
|---|
| 10771 | #define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 |
|---|
| 10772 | #define regDSCC2_DSCC_PPS_CONFIG1 0x30c7 |
|---|
| 10773 | #define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 |
|---|
| 10774 | #define regDSCC2_DSCC_PPS_CONFIG2 0x30c8 |
|---|
| 10775 | #define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 |
|---|
| 10776 | #define regDSCC2_DSCC_PPS_CONFIG3 0x30c9 |
|---|
| 10777 | #define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 |
|---|
| 10778 | #define regDSCC2_DSCC_PPS_CONFIG4 0x30ca |
|---|
| 10779 | #define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 |
|---|
| 10780 | #define regDSCC2_DSCC_PPS_CONFIG5 0x30cb |
|---|
| 10781 | #define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 |
|---|
| 10782 | #define regDSCC2_DSCC_PPS_CONFIG6 0x30cc |
|---|
| 10783 | #define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 |
|---|
| 10784 | #define regDSCC2_DSCC_PPS_CONFIG7 0x30cd |
|---|
| 10785 | #define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 |
|---|
| 10786 | #define regDSCC2_DSCC_PPS_CONFIG8 0x30ce |
|---|
| 10787 | #define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 |
|---|
| 10788 | #define regDSCC2_DSCC_PPS_CONFIG9 0x30cf |
|---|
| 10789 | #define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 |
|---|
| 10790 | #define regDSCC2_DSCC_PPS_CONFIG10 0x30d0 |
|---|
| 10791 | #define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 |
|---|
| 10792 | #define regDSCC2_DSCC_PPS_CONFIG11 0x30d1 |
|---|
| 10793 | #define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 |
|---|
| 10794 | #define regDSCC2_DSCC_PPS_CONFIG12 0x30d2 |
|---|
| 10795 | #define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 |
|---|
| 10796 | #define regDSCC2_DSCC_PPS_CONFIG13 0x30d3 |
|---|
| 10797 | #define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 |
|---|
| 10798 | #define regDSCC2_DSCC_PPS_CONFIG14 0x30d4 |
|---|
| 10799 | #define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 |
|---|
| 10800 | #define regDSCC2_DSCC_PPS_CONFIG15 0x30d5 |
|---|
| 10801 | #define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 |
|---|
| 10802 | #define regDSCC2_DSCC_PPS_CONFIG16 0x30d6 |
|---|
| 10803 | #define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 |
|---|
| 10804 | #define regDSCC2_DSCC_PPS_CONFIG17 0x30d7 |
|---|
| 10805 | #define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 |
|---|
| 10806 | #define regDSCC2_DSCC_PPS_CONFIG18 0x30d8 |
|---|
| 10807 | #define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 |
|---|
| 10808 | #define regDSCC2_DSCC_PPS_CONFIG19 0x30d9 |
|---|
| 10809 | #define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 |
|---|
| 10810 | #define regDSCC2_DSCC_PPS_CONFIG20 0x30da |
|---|
| 10811 | #define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 |
|---|
| 10812 | #define regDSCC2_DSCC_PPS_CONFIG21 0x30db |
|---|
| 10813 | #define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 |
|---|
| 10814 | #define regDSCC2_DSCC_PPS_CONFIG22 0x30dc |
|---|
| 10815 | #define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 |
|---|
| 10816 | #define regDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd |
|---|
| 10817 | #define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 |
|---|
| 10818 | #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de |
|---|
| 10819 | #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 |
|---|
| 10820 | #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df |
|---|
| 10821 | #define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 |
|---|
| 10822 | #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0 |
|---|
| 10823 | #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 |
|---|
| 10824 | #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1 |
|---|
| 10825 | #define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 |
|---|
| 10826 | #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2 |
|---|
| 10827 | #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 |
|---|
| 10828 | #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3 |
|---|
| 10829 | #define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 |
|---|
| 10830 | #define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4 |
|---|
| 10831 | #define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 |
|---|
| 10832 | #define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5 |
|---|
| 10833 | #define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 |
|---|
| 10834 | #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6 |
|---|
| 10835 | #define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10836 | #define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7 |
|---|
| 10837 | #define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10838 | #define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8 |
|---|
| 10839 | #define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10840 | #define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9 |
|---|
| 10841 | #define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10842 | #define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea |
|---|
| 10843 | #define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10844 | #define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb |
|---|
| 10845 | #define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10846 | #define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec |
|---|
| 10847 | #define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10848 | #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed |
|---|
| 10849 | #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10850 | #define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2 |
|---|
| 10851 | #define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 |
|---|
| 10852 | |
|---|
| 10853 | |
|---|
| 10854 | // addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec |
|---|
| 10855 | // base address: 0xc420 |
|---|
| 10856 | #define regDC_PERFMON21_PERFCOUNTER_CNTL 0x3108 |
|---|
| 10857 | #define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 10858 | #define regDC_PERFMON21_PERFCOUNTER_CNTL2 0x3109 |
|---|
| 10859 | #define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 10860 | #define regDC_PERFMON21_PERFCOUNTER_STATE 0x310a |
|---|
| 10861 | #define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 10862 | #define regDC_PERFMON21_PERFMON_CNTL 0x310b |
|---|
| 10863 | #define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 10864 | #define regDC_PERFMON21_PERFMON_CNTL2 0x310c |
|---|
| 10865 | #define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 10866 | #define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x310d |
|---|
| 10867 | #define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 10868 | #define regDC_PERFMON21_PERFMON_CVALUE_LOW 0x310e |
|---|
| 10869 | #define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 10870 | #define regDC_PERFMON21_PERFMON_HI 0x310f |
|---|
| 10871 | #define regDC_PERFMON21_PERFMON_HI_BASE_IDX 2 |
|---|
| 10872 | #define regDC_PERFMON21_PERFMON_LOW 0x3110 |
|---|
| 10873 | #define regDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 |
|---|
| 10874 | |
|---|
| 10875 | |
|---|
| 10876 | // addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec |
|---|
| 10877 | // base address: 0x450 |
|---|
| 10878 | #define regDSC_TOP3_DSC_TOP_CONTROL 0x3114 |
|---|
| 10879 | #define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2 |
|---|
| 10880 | #define regDSC_TOP3_DSC_DEBUG_CONTROL 0x3115 |
|---|
| 10881 | #define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2 |
|---|
| 10882 | |
|---|
| 10883 | |
|---|
| 10884 | // addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec |
|---|
| 10885 | // base address: 0x450 |
|---|
| 10886 | #define regDSCCIF3_DSCCIF_CONFIG0 0x3119 |
|---|
| 10887 | #define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2 |
|---|
| 10888 | #define regDSCCIF3_DSCCIF_CONFIG1 0x311a |
|---|
| 10889 | #define regDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2 |
|---|
| 10890 | |
|---|
| 10891 | |
|---|
| 10892 | // addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec |
|---|
| 10893 | // base address: 0x450 |
|---|
| 10894 | #define regDSCC3_DSCC_CONFIG0 0x311e |
|---|
| 10895 | #define regDSCC3_DSCC_CONFIG0_BASE_IDX 2 |
|---|
| 10896 | #define regDSCC3_DSCC_CONFIG1 0x311f |
|---|
| 10897 | #define regDSCC3_DSCC_CONFIG1_BASE_IDX 2 |
|---|
| 10898 | #define regDSCC3_DSCC_STATUS 0x3120 |
|---|
| 10899 | #define regDSCC3_DSCC_STATUS_BASE_IDX 2 |
|---|
| 10900 | #define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121 |
|---|
| 10901 | #define regDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 |
|---|
| 10902 | #define regDSCC3_DSCC_PPS_CONFIG0 0x3122 |
|---|
| 10903 | #define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2 |
|---|
| 10904 | #define regDSCC3_DSCC_PPS_CONFIG1 0x3123 |
|---|
| 10905 | #define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2 |
|---|
| 10906 | #define regDSCC3_DSCC_PPS_CONFIG2 0x3124 |
|---|
| 10907 | #define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2 |
|---|
| 10908 | #define regDSCC3_DSCC_PPS_CONFIG3 0x3125 |
|---|
| 10909 | #define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2 |
|---|
| 10910 | #define regDSCC3_DSCC_PPS_CONFIG4 0x3126 |
|---|
| 10911 | #define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2 |
|---|
| 10912 | #define regDSCC3_DSCC_PPS_CONFIG5 0x3127 |
|---|
| 10913 | #define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2 |
|---|
| 10914 | #define regDSCC3_DSCC_PPS_CONFIG6 0x3128 |
|---|
| 10915 | #define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2 |
|---|
| 10916 | #define regDSCC3_DSCC_PPS_CONFIG7 0x3129 |
|---|
| 10917 | #define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2 |
|---|
| 10918 | #define regDSCC3_DSCC_PPS_CONFIG8 0x312a |
|---|
| 10919 | #define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2 |
|---|
| 10920 | #define regDSCC3_DSCC_PPS_CONFIG9 0x312b |
|---|
| 10921 | #define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2 |
|---|
| 10922 | #define regDSCC3_DSCC_PPS_CONFIG10 0x312c |
|---|
| 10923 | #define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2 |
|---|
| 10924 | #define regDSCC3_DSCC_PPS_CONFIG11 0x312d |
|---|
| 10925 | #define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2 |
|---|
| 10926 | #define regDSCC3_DSCC_PPS_CONFIG12 0x312e |
|---|
| 10927 | #define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2 |
|---|
| 10928 | #define regDSCC3_DSCC_PPS_CONFIG13 0x312f |
|---|
| 10929 | #define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2 |
|---|
| 10930 | #define regDSCC3_DSCC_PPS_CONFIG14 0x3130 |
|---|
| 10931 | #define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2 |
|---|
| 10932 | #define regDSCC3_DSCC_PPS_CONFIG15 0x3131 |
|---|
| 10933 | #define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2 |
|---|
| 10934 | #define regDSCC3_DSCC_PPS_CONFIG16 0x3132 |
|---|
| 10935 | #define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2 |
|---|
| 10936 | #define regDSCC3_DSCC_PPS_CONFIG17 0x3133 |
|---|
| 10937 | #define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2 |
|---|
| 10938 | #define regDSCC3_DSCC_PPS_CONFIG18 0x3134 |
|---|
| 10939 | #define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2 |
|---|
| 10940 | #define regDSCC3_DSCC_PPS_CONFIG19 0x3135 |
|---|
| 10941 | #define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2 |
|---|
| 10942 | #define regDSCC3_DSCC_PPS_CONFIG20 0x3136 |
|---|
| 10943 | #define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2 |
|---|
| 10944 | #define regDSCC3_DSCC_PPS_CONFIG21 0x3137 |
|---|
| 10945 | #define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2 |
|---|
| 10946 | #define regDSCC3_DSCC_PPS_CONFIG22 0x3138 |
|---|
| 10947 | #define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2 |
|---|
| 10948 | #define regDSCC3_DSCC_MEM_POWER_CONTROL 0x3139 |
|---|
| 10949 | #define regDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2 |
|---|
| 10950 | #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a |
|---|
| 10951 | #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 |
|---|
| 10952 | #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b |
|---|
| 10953 | #define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 |
|---|
| 10954 | #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c |
|---|
| 10955 | #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 |
|---|
| 10956 | #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d |
|---|
| 10957 | #define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 |
|---|
| 10958 | #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e |
|---|
| 10959 | #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 |
|---|
| 10960 | #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f |
|---|
| 10961 | #define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 |
|---|
| 10962 | #define regDSCC3_DSCC_MAX_ABS_ERROR0 0x3140 |
|---|
| 10963 | #define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 |
|---|
| 10964 | #define regDSCC3_DSCC_MAX_ABS_ERROR1 0x3141 |
|---|
| 10965 | #define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 |
|---|
| 10966 | #define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142 |
|---|
| 10967 | #define regDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10968 | #define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143 |
|---|
| 10969 | #define regDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10970 | #define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144 |
|---|
| 10971 | #define regDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10972 | #define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145 |
|---|
| 10973 | #define regDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10974 | #define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146 |
|---|
| 10975 | #define regDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10976 | #define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147 |
|---|
| 10977 | #define regDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10978 | #define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148 |
|---|
| 10979 | #define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10980 | #define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149 |
|---|
| 10981 | #define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2 |
|---|
| 10982 | #define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x314e |
|---|
| 10983 | #define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 |
|---|
| 10984 | |
|---|
| 10985 | |
|---|
| 10986 | // addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec |
|---|
| 10987 | // base address: 0xc590 |
|---|
| 10988 | #define regDC_PERFMON22_PERFCOUNTER_CNTL 0x3164 |
|---|
| 10989 | #define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 10990 | #define regDC_PERFMON22_PERFCOUNTER_CNTL2 0x3165 |
|---|
| 10991 | #define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 10992 | #define regDC_PERFMON22_PERFCOUNTER_STATE 0x3166 |
|---|
| 10993 | #define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 10994 | #define regDC_PERFMON22_PERFMON_CNTL 0x3167 |
|---|
| 10995 | #define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 10996 | #define regDC_PERFMON22_PERFMON_CNTL2 0x3168 |
|---|
| 10997 | #define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 10998 | #define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x3169 |
|---|
| 10999 | #define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 11000 | #define regDC_PERFMON22_PERFMON_CVALUE_LOW 0x316a |
|---|
| 11001 | #define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 11002 | #define regDC_PERFMON22_PERFMON_HI 0x316b |
|---|
| 11003 | #define regDC_PERFMON22_PERFMON_HI_BASE_IDX 2 |
|---|
| 11004 | #define regDC_PERFMON22_PERFMON_LOW 0x316c |
|---|
| 11005 | #define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 2 |
|---|
| 11006 | |
|---|
| 11007 | |
|---|
| 11008 | // addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec |
|---|
| 11009 | // base address: 0x0 |
|---|
| 11010 | #define regDWB_ENABLE_CLK_CTRL 0x3228 |
|---|
| 11011 | #define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 |
|---|
| 11012 | #define regDWB_MEM_PWR_CTRL 0x3229 |
|---|
| 11013 | #define regDWB_MEM_PWR_CTRL_BASE_IDX 2 |
|---|
| 11014 | #define regFC_MODE_CTRL 0x322a |
|---|
| 11015 | #define regFC_MODE_CTRL_BASE_IDX 2 |
|---|
| 11016 | #define regFC_FLOW_CTRL 0x322b |
|---|
| 11017 | #define regFC_FLOW_CTRL_BASE_IDX 2 |
|---|
| 11018 | #define regFC_WINDOW_START 0x322c |
|---|
| 11019 | #define regFC_WINDOW_START_BASE_IDX 2 |
|---|
| 11020 | #define regFC_WINDOW_SIZE 0x322d |
|---|
| 11021 | #define regFC_WINDOW_SIZE_BASE_IDX 2 |
|---|
| 11022 | #define regFC_SOURCE_SIZE 0x322e |
|---|
| 11023 | #define regFC_SOURCE_SIZE_BASE_IDX 2 |
|---|
| 11024 | #define regDWB_UPDATE_CTRL 0x322f |
|---|
| 11025 | #define regDWB_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 11026 | #define regDWB_CRC_CTRL 0x3230 |
|---|
| 11027 | #define regDWB_CRC_CTRL_BASE_IDX 2 |
|---|
| 11028 | #define regDWB_CRC_MASK_R_G 0x3231 |
|---|
| 11029 | #define regDWB_CRC_MASK_R_G_BASE_IDX 2 |
|---|
| 11030 | #define regDWB_CRC_MASK_B_A 0x3232 |
|---|
| 11031 | #define regDWB_CRC_MASK_B_A_BASE_IDX 2 |
|---|
| 11032 | #define regDWB_CRC_VAL_R_G 0x3233 |
|---|
| 11033 | #define regDWB_CRC_VAL_R_G_BASE_IDX 2 |
|---|
| 11034 | #define regDWB_CRC_VAL_B_A 0x3234 |
|---|
| 11035 | #define regDWB_CRC_VAL_B_A_BASE_IDX 2 |
|---|
| 11036 | #define regDWB_OUT_CTRL 0x3235 |
|---|
| 11037 | #define regDWB_OUT_CTRL_BASE_IDX 2 |
|---|
| 11038 | #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 |
|---|
| 11039 | #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 |
|---|
| 11040 | #define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 |
|---|
| 11041 | #define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 |
|---|
| 11042 | #define regDWB_HOST_READ_CONTROL 0x3238 |
|---|
| 11043 | #define regDWB_HOST_READ_CONTROL_BASE_IDX 2 |
|---|
| 11044 | #define regDWB_OVERFLOW_STATUS 0x3239 |
|---|
| 11045 | #define regDWB_OVERFLOW_STATUS_BASE_IDX 2 |
|---|
| 11046 | #define regDWB_OVERFLOW_COUNTER 0x323a |
|---|
| 11047 | #define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 |
|---|
| 11048 | #define regDWB_SOFT_RESET 0x323b |
|---|
| 11049 | #define regDWB_SOFT_RESET_BASE_IDX 2 |
|---|
| 11050 | |
|---|
| 11051 | |
|---|
| 11052 | // addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec |
|---|
| 11053 | // base address: 0xca20 |
|---|
| 11054 | #define regDC_PERFMON3_PERFCOUNTER_CNTL 0x3288 |
|---|
| 11055 | #define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 |
|---|
| 11056 | #define regDC_PERFMON3_PERFCOUNTER_CNTL2 0x3289 |
|---|
| 11057 | #define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 |
|---|
| 11058 | #define regDC_PERFMON3_PERFCOUNTER_STATE 0x328a |
|---|
| 11059 | #define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 |
|---|
| 11060 | #define regDC_PERFMON3_PERFMON_CNTL 0x328b |
|---|
| 11061 | #define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 |
|---|
| 11062 | #define regDC_PERFMON3_PERFMON_CNTL2 0x328c |
|---|
| 11063 | #define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 |
|---|
| 11064 | #define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x328d |
|---|
| 11065 | #define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 |
|---|
| 11066 | #define regDC_PERFMON3_PERFMON_CVALUE_LOW 0x328e |
|---|
| 11067 | #define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 |
|---|
| 11068 | #define regDC_PERFMON3_PERFMON_HI 0x328f |
|---|
| 11069 | #define regDC_PERFMON3_PERFMON_HI_BASE_IDX 2 |
|---|
| 11070 | #define regDC_PERFMON3_PERFMON_LOW 0x3290 |
|---|
| 11071 | #define regDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 |
|---|
| 11072 | |
|---|
| 11073 | |
|---|
| 11074 | // addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec |
|---|
| 11075 | // base address: 0x0 |
|---|
| 11076 | #define regDWB_HDR_MULT_COEF 0x3294 |
|---|
| 11077 | #define regDWB_HDR_MULT_COEF_BASE_IDX 2 |
|---|
| 11078 | #define regDWB_GAMUT_REMAP_MODE 0x3295 |
|---|
| 11079 | #define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 |
|---|
| 11080 | #define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 |
|---|
| 11081 | #define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 |
|---|
| 11082 | #define regDWB_GAMUT_REMAPA_C11_C12 0x3297 |
|---|
| 11083 | #define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 |
|---|
| 11084 | #define regDWB_GAMUT_REMAPA_C13_C14 0x3298 |
|---|
| 11085 | #define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 |
|---|
| 11086 | #define regDWB_GAMUT_REMAPA_C21_C22 0x3299 |
|---|
| 11087 | #define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 |
|---|
| 11088 | #define regDWB_GAMUT_REMAPA_C23_C24 0x329a |
|---|
| 11089 | #define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 |
|---|
| 11090 | #define regDWB_GAMUT_REMAPA_C31_C32 0x329b |
|---|
| 11091 | #define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 |
|---|
| 11092 | #define regDWB_GAMUT_REMAPA_C33_C34 0x329c |
|---|
| 11093 | #define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 |
|---|
| 11094 | #define regDWB_GAMUT_REMAPB_C11_C12 0x329d |
|---|
| 11095 | #define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 |
|---|
| 11096 | #define regDWB_GAMUT_REMAPB_C13_C14 0x329e |
|---|
| 11097 | #define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 |
|---|
| 11098 | #define regDWB_GAMUT_REMAPB_C21_C22 0x329f |
|---|
| 11099 | #define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 |
|---|
| 11100 | #define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 |
|---|
| 11101 | #define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 |
|---|
| 11102 | #define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 |
|---|
| 11103 | #define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 |
|---|
| 11104 | #define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 |
|---|
| 11105 | #define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 |
|---|
| 11106 | #define regDWB_OGAM_CONTROL 0x32a3 |
|---|
| 11107 | #define regDWB_OGAM_CONTROL_BASE_IDX 2 |
|---|
| 11108 | #define regDWB_OGAM_LUT_INDEX 0x32a4 |
|---|
| 11109 | #define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 |
|---|
| 11110 | #define regDWB_OGAM_LUT_DATA 0x32a5 |
|---|
| 11111 | #define regDWB_OGAM_LUT_DATA_BASE_IDX 2 |
|---|
| 11112 | #define regDWB_OGAM_LUT_CONTROL 0x32a6 |
|---|
| 11113 | #define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 |
|---|
| 11114 | #define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 |
|---|
| 11115 | #define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 |
|---|
| 11116 | #define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 |
|---|
| 11117 | #define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 |
|---|
| 11118 | #define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 |
|---|
| 11119 | #define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 |
|---|
| 11120 | #define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa |
|---|
| 11121 | #define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 |
|---|
| 11122 | #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab |
|---|
| 11123 | #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 |
|---|
| 11124 | #define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac |
|---|
| 11125 | #define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 |
|---|
| 11126 | #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad |
|---|
| 11127 | #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 |
|---|
| 11128 | #define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae |
|---|
| 11129 | #define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 |
|---|
| 11130 | #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af |
|---|
| 11131 | #define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 |
|---|
| 11132 | #define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 |
|---|
| 11133 | #define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 |
|---|
| 11134 | #define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 |
|---|
| 11135 | #define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 |
|---|
| 11136 | #define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 |
|---|
| 11137 | #define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 |
|---|
| 11138 | #define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 |
|---|
| 11139 | #define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 |
|---|
| 11140 | #define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 |
|---|
| 11141 | #define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 |
|---|
| 11142 | #define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 |
|---|
| 11143 | #define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 |
|---|
| 11144 | #define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 |
|---|
| 11145 | #define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 |
|---|
| 11146 | #define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 |
|---|
| 11147 | #define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 |
|---|
| 11148 | #define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 |
|---|
| 11149 | #define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 |
|---|
| 11150 | #define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 |
|---|
| 11151 | #define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 |
|---|
| 11152 | #define regDWB_OGAM_RAMA_REGION_2_3 0x32ba |
|---|
| 11153 | #define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 |
|---|
| 11154 | #define regDWB_OGAM_RAMA_REGION_4_5 0x32bb |
|---|
| 11155 | #define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 |
|---|
| 11156 | #define regDWB_OGAM_RAMA_REGION_6_7 0x32bc |
|---|
| 11157 | #define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 |
|---|
| 11158 | #define regDWB_OGAM_RAMA_REGION_8_9 0x32bd |
|---|
| 11159 | #define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 |
|---|
| 11160 | #define regDWB_OGAM_RAMA_REGION_10_11 0x32be |
|---|
| 11161 | #define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 |
|---|
| 11162 | #define regDWB_OGAM_RAMA_REGION_12_13 0x32bf |
|---|
| 11163 | #define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 |
|---|
| 11164 | #define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 |
|---|
| 11165 | #define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 |
|---|
| 11166 | #define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 |
|---|
| 11167 | #define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 |
|---|
| 11168 | #define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 |
|---|
| 11169 | #define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 |
|---|
| 11170 | #define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 |
|---|
| 11171 | #define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 |
|---|
| 11172 | #define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 |
|---|
| 11173 | #define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 |
|---|
| 11174 | #define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 |
|---|
| 11175 | #define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 |
|---|
| 11176 | #define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 |
|---|
| 11177 | #define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 |
|---|
| 11178 | #define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 |
|---|
| 11179 | #define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 |
|---|
| 11180 | #define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 |
|---|
| 11181 | #define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 |
|---|
| 11182 | #define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 |
|---|
| 11183 | #define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 |
|---|
| 11184 | #define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca |
|---|
| 11185 | #define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 |
|---|
| 11186 | #define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb |
|---|
| 11187 | #define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 |
|---|
| 11188 | #define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc |
|---|
| 11189 | #define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 |
|---|
| 11190 | #define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd |
|---|
| 11191 | #define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 |
|---|
| 11192 | #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce |
|---|
| 11193 | #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 |
|---|
| 11194 | #define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf |
|---|
| 11195 | #define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 |
|---|
| 11196 | #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 |
|---|
| 11197 | #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 |
|---|
| 11198 | #define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 |
|---|
| 11199 | #define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 |
|---|
| 11200 | #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 |
|---|
| 11201 | #define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 |
|---|
| 11202 | #define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 |
|---|
| 11203 | #define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 |
|---|
| 11204 | #define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 |
|---|
| 11205 | #define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 |
|---|
| 11206 | #define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 |
|---|
| 11207 | #define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 |
|---|
| 11208 | #define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 |
|---|
| 11209 | #define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 |
|---|
| 11210 | #define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 |
|---|
| 11211 | #define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 |
|---|
| 11212 | #define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 |
|---|
| 11213 | #define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 |
|---|
| 11214 | #define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 |
|---|
| 11215 | #define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 |
|---|
| 11216 | #define regDWB_OGAM_RAMB_OFFSET_G 0x32da |
|---|
| 11217 | #define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 |
|---|
| 11218 | #define regDWB_OGAM_RAMB_OFFSET_R 0x32db |
|---|
| 11219 | #define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 |
|---|
| 11220 | #define regDWB_OGAM_RAMB_REGION_0_1 0x32dc |
|---|
| 11221 | #define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 |
|---|
| 11222 | #define regDWB_OGAM_RAMB_REGION_2_3 0x32dd |
|---|
| 11223 | #define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 |
|---|
| 11224 | #define regDWB_OGAM_RAMB_REGION_4_5 0x32de |
|---|
| 11225 | #define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 |
|---|
| 11226 | #define regDWB_OGAM_RAMB_REGION_6_7 0x32df |
|---|
| 11227 | #define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 |
|---|
| 11228 | #define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 |
|---|
| 11229 | #define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 |
|---|
| 11230 | #define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 |
|---|
| 11231 | #define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 |
|---|
| 11232 | #define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 |
|---|
| 11233 | #define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 |
|---|
| 11234 | #define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 |
|---|
| 11235 | #define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 |
|---|
| 11236 | #define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 |
|---|
| 11237 | #define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 |
|---|
| 11238 | #define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 |
|---|
| 11239 | #define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 |
|---|
| 11240 | #define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 |
|---|
| 11241 | #define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 |
|---|
| 11242 | #define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 |
|---|
| 11243 | #define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 |
|---|
| 11244 | #define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 |
|---|
| 11245 | #define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 |
|---|
| 11246 | #define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 |
|---|
| 11247 | #define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 |
|---|
| 11248 | #define regDWB_OGAM_RAMB_REGION_28_29 0x32ea |
|---|
| 11249 | #define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 |
|---|
| 11250 | #define regDWB_OGAM_RAMB_REGION_30_31 0x32eb |
|---|
| 11251 | #define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 |
|---|
| 11252 | #define regDWB_OGAM_RAMB_REGION_32_33 0x32ec |
|---|
| 11253 | #define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 |
|---|
| 11254 | |
|---|
| 11255 | |
|---|
| 11256 | // addressBlock: dce_dc_dchvm_hvm_dispdec |
|---|
| 11257 | // base address: 0x0 |
|---|
| 11258 | #define regDCHVM_CTRL0 0x3603 |
|---|
| 11259 | #define regDCHVM_CTRL0_BASE_IDX 2 |
|---|
| 11260 | #define regDCHVM_CTRL1 0x3604 |
|---|
| 11261 | #define regDCHVM_CTRL1_BASE_IDX 2 |
|---|
| 11262 | #define regDCHVM_CLK_CTRL 0x3605 |
|---|
| 11263 | #define regDCHVM_CLK_CTRL_BASE_IDX 2 |
|---|
| 11264 | #define regDCHVM_MEM_CTRL 0x3606 |
|---|
| 11265 | #define regDCHVM_MEM_CTRL_BASE_IDX 2 |
|---|
| 11266 | #define regDCHVM_RIOMMU_CTRL0 0x3607 |
|---|
| 11267 | #define regDCHVM_RIOMMU_CTRL0_BASE_IDX 2 |
|---|
| 11268 | #define regDCHVM_RIOMMU_STAT0 0x3608 |
|---|
| 11269 | #define regDCHVM_RIOMMU_STAT0_BASE_IDX 2 |
|---|
| 11270 | |
|---|
| 11271 | |
|---|
| 11272 | // addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec |
|---|
| 11273 | // base address: 0x1ab8c |
|---|
| 11274 | #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 |
|---|
| 11275 | #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 11276 | #define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 |
|---|
| 11277 | #define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 |
|---|
| 11278 | #define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 |
|---|
| 11279 | #define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 |
|---|
| 11280 | #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 |
|---|
| 11281 | #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 |
|---|
| 11282 | #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 |
|---|
| 11283 | #define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 |
|---|
| 11284 | #define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 |
|---|
| 11285 | #define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 |
|---|
| 11286 | |
|---|
| 11287 | |
|---|
| 11288 | // addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec |
|---|
| 11289 | // base address: 0x1abc0 |
|---|
| 11290 | #define regAPG0_APG_CONTROL 0x3630 |
|---|
| 11291 | #define regAPG0_APG_CONTROL_BASE_IDX 2 |
|---|
| 11292 | #define regAPG0_APG_CONTROL2 0x3631 |
|---|
| 11293 | #define regAPG0_APG_CONTROL2_BASE_IDX 2 |
|---|
| 11294 | #define regAPG0_APG_DBG_GEN_CONTROL 0x3632 |
|---|
| 11295 | #define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 |
|---|
| 11296 | #define regAPG0_APG_PACKET_CONTROL 0x3633 |
|---|
| 11297 | #define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 11298 | #define regAPG0_APG_AUDIO_CRC_CONTROL 0x363a |
|---|
| 11299 | #define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 |
|---|
| 11300 | #define regAPG0_APG_AUDIO_CRC_CONTROL2 0x363b |
|---|
| 11301 | #define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 |
|---|
| 11302 | #define regAPG0_APG_AUDIO_CRC_RESULT 0x363c |
|---|
| 11303 | #define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 |
|---|
| 11304 | #define regAPG0_APG_STATUS 0x3641 |
|---|
| 11305 | #define regAPG0_APG_STATUS_BASE_IDX 2 |
|---|
| 11306 | #define regAPG0_APG_STATUS2 0x3642 |
|---|
| 11307 | #define regAPG0_APG_STATUS2_BASE_IDX 2 |
|---|
| 11308 | #define regAPG0_APG_MEM_PWR 0x3644 |
|---|
| 11309 | #define regAPG0_APG_MEM_PWR_BASE_IDX 2 |
|---|
| 11310 | #define regAPG0_APG_SPARE 0x3646 |
|---|
| 11311 | #define regAPG0_APG_SPARE_BASE_IDX 2 |
|---|
| 11312 | |
|---|
| 11313 | |
|---|
| 11314 | // addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec |
|---|
| 11315 | // base address: 0x1ac38 |
|---|
| 11316 | #define regDME6_DME_CONTROL 0x364e |
|---|
| 11317 | #define regDME6_DME_CONTROL_BASE_IDX 2 |
|---|
| 11318 | #define regDME6_DME_MEMORY_CONTROL 0x364f |
|---|
| 11319 | #define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 |
|---|
| 11320 | |
|---|
| 11321 | |
|---|
| 11322 | // addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec |
|---|
| 11323 | // base address: 0x1ac44 |
|---|
| 11324 | #define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 |
|---|
| 11325 | #define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 11326 | #define regVPG6_VPG_GENERIC_PACKET_DATA 0x3652 |
|---|
| 11327 | #define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
|---|
| 11328 | #define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 |
|---|
| 11329 | #define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 11330 | #define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 |
|---|
| 11331 | #define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 11332 | #define regVPG6_VPG_GENERIC_STATUS 0x3655 |
|---|
| 11333 | #define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 |
|---|
| 11334 | #define regVPG6_VPG_MEM_PWR 0x3656 |
|---|
| 11335 | #define regVPG6_VPG_MEM_PWR_BASE_IDX 2 |
|---|
| 11336 | #define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x3657 |
|---|
| 11337 | #define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 11338 | #define regVPG6_VPG_ISRC1_2_DATA 0x3658 |
|---|
| 11339 | #define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 |
|---|
| 11340 | #define regVPG6_VPG_MPEG_INFO0 0x3659 |
|---|
| 11341 | #define regVPG6_VPG_MPEG_INFO0_BASE_IDX 2 |
|---|
| 11342 | #define regVPG6_VPG_MPEG_INFO1 0x365a |
|---|
| 11343 | #define regVPG6_VPG_MPEG_INFO1_BASE_IDX 2 |
|---|
| 11344 | |
|---|
| 11345 | |
|---|
| 11346 | // addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec |
|---|
| 11347 | // base address: 0x1ac74 |
|---|
| 11348 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d |
|---|
| 11349 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 |
|---|
| 11350 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e |
|---|
| 11351 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 |
|---|
| 11352 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f |
|---|
| 11353 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
|---|
| 11354 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 |
|---|
| 11355 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
|---|
| 11356 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 |
|---|
| 11357 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 |
|---|
| 11358 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 |
|---|
| 11359 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 |
|---|
| 11360 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 |
|---|
| 11361 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 |
|---|
| 11362 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 |
|---|
| 11363 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 |
|---|
| 11364 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 |
|---|
| 11365 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 |
|---|
| 11366 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 |
|---|
| 11367 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 |
|---|
| 11368 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 |
|---|
| 11369 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 |
|---|
| 11370 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 |
|---|
| 11371 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 |
|---|
| 11372 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 |
|---|
| 11373 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 |
|---|
| 11374 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a |
|---|
| 11375 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 |
|---|
| 11376 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b |
|---|
| 11377 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 |
|---|
| 11378 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c |
|---|
| 11379 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 |
|---|
| 11380 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d |
|---|
| 11381 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 |
|---|
| 11382 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e |
|---|
| 11383 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 |
|---|
| 11384 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f |
|---|
| 11385 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 |
|---|
| 11386 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 |
|---|
| 11387 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 |
|---|
| 11388 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 |
|---|
| 11389 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 |
|---|
| 11390 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 |
|---|
| 11391 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 |
|---|
| 11392 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 |
|---|
| 11393 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 |
|---|
| 11394 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 |
|---|
| 11395 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 |
|---|
| 11396 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 |
|---|
| 11397 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 |
|---|
| 11398 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 |
|---|
| 11399 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 |
|---|
| 11400 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 |
|---|
| 11401 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 |
|---|
| 11402 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 |
|---|
| 11403 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 |
|---|
| 11404 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 |
|---|
| 11405 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 |
|---|
| 11406 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a |
|---|
| 11407 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 |
|---|
| 11408 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b |
|---|
| 11409 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 |
|---|
| 11410 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c |
|---|
| 11411 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 |
|---|
| 11412 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d |
|---|
| 11413 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 |
|---|
| 11414 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e |
|---|
| 11415 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 11416 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 |
|---|
| 11417 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 |
|---|
| 11418 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 |
|---|
| 11419 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 |
|---|
| 11420 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 |
|---|
| 11421 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 |
|---|
| 11422 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 |
|---|
| 11423 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 |
|---|
| 11424 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 |
|---|
| 11425 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 |
|---|
| 11426 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 |
|---|
| 11427 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 |
|---|
| 11428 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 |
|---|
| 11429 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 |
|---|
| 11430 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368a |
|---|
| 11431 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 |
|---|
| 11432 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x368b |
|---|
| 11433 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 |
|---|
| 11434 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x368c |
|---|
| 11435 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 11436 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x368d |
|---|
| 11437 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 |
|---|
| 11438 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x368e |
|---|
| 11439 | #define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 |
|---|
| 11440 | |
|---|
| 11441 | |
|---|
| 11442 | // addressBlock: dce_dc_hpo_dp_link_enc0_dispdec |
|---|
| 11443 | // base address: 0x1ad5c |
|---|
| 11444 | #define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x3697 |
|---|
| 11445 | #define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 11446 | #define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x3698 |
|---|
| 11447 | #define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 |
|---|
| 11448 | |
|---|
| 11449 | |
|---|
| 11450 | // addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec |
|---|
| 11451 | // base address: 0x1ae00 |
|---|
| 11452 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36c0 |
|---|
| 11453 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 |
|---|
| 11454 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36c1 |
|---|
| 11455 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 |
|---|
| 11456 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36c4 |
|---|
| 11457 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 |
|---|
| 11458 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36c5 |
|---|
| 11459 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 |
|---|
| 11460 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36c6 |
|---|
| 11461 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 |
|---|
| 11462 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36c7 |
|---|
| 11463 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 |
|---|
| 11464 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36c8 |
|---|
| 11465 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 |
|---|
| 11466 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36cb |
|---|
| 11467 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 |
|---|
| 11468 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36cc |
|---|
| 11469 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 |
|---|
| 11470 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36cd |
|---|
| 11471 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 |
|---|
| 11472 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36ce |
|---|
| 11473 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 |
|---|
| 11474 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36d1 |
|---|
| 11475 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 |
|---|
| 11476 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36d2 |
|---|
| 11477 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 |
|---|
| 11478 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36d3 |
|---|
| 11479 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 |
|---|
| 11480 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36d4 |
|---|
| 11481 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 |
|---|
| 11482 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d7 |
|---|
| 11483 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 |
|---|
| 11484 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d8 |
|---|
| 11485 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 |
|---|
| 11486 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d9 |
|---|
| 11487 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 |
|---|
| 11488 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36da |
|---|
| 11489 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 |
|---|
| 11490 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36db |
|---|
| 11491 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 |
|---|
| 11492 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36dc |
|---|
| 11493 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 |
|---|
| 11494 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36dd |
|---|
| 11495 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 |
|---|
| 11496 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36de |
|---|
| 11497 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 |
|---|
| 11498 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36df |
|---|
| 11499 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 |
|---|
| 11500 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36e0 |
|---|
| 11501 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 |
|---|
| 11502 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36e1 |
|---|
| 11503 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 |
|---|
| 11504 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36e2 |
|---|
| 11505 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 |
|---|
| 11506 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e3 |
|---|
| 11507 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 |
|---|
| 11508 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e4 |
|---|
| 11509 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 |
|---|
| 11510 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e5 |
|---|
| 11511 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 |
|---|
| 11512 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e6 |
|---|
| 11513 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 |
|---|
| 11514 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e7 |
|---|
| 11515 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 |
|---|
| 11516 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e8 |
|---|
| 11517 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 |
|---|
| 11518 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x36ea |
|---|
| 11519 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 |
|---|
| 11520 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x36eb |
|---|
| 11521 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 |
|---|
| 11522 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x36ec |
|---|
| 11523 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 |
|---|
| 11524 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x36ed |
|---|
| 11525 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 11526 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0 0x36ee |
|---|
| 11527 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 |
|---|
| 11528 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1 0x36ef |
|---|
| 11529 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 |
|---|
| 11530 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS 0x36f0 |
|---|
| 11531 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 |
|---|
| 11532 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT 0x36f1 |
|---|
| 11533 | #define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 |
|---|
| 11534 | |
|---|
| 11535 | |
|---|
| 11536 | // addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec |
|---|
| 11537 | // base address: 0x1aedc |
|---|
| 11538 | #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 |
|---|
| 11539 | #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 11540 | #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 |
|---|
| 11541 | #define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 |
|---|
| 11542 | #define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 |
|---|
| 11543 | #define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 |
|---|
| 11544 | #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa |
|---|
| 11545 | #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 |
|---|
| 11546 | #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb |
|---|
| 11547 | #define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 |
|---|
| 11548 | #define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc |
|---|
| 11549 | #define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 |
|---|
| 11550 | |
|---|
| 11551 | |
|---|
| 11552 | // addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec |
|---|
| 11553 | // base address: 0x1af10 |
|---|
| 11554 | #define regAPG1_APG_CONTROL 0x3704 |
|---|
| 11555 | #define regAPG1_APG_CONTROL_BASE_IDX 2 |
|---|
| 11556 | #define regAPG1_APG_CONTROL2 0x3705 |
|---|
| 11557 | #define regAPG1_APG_CONTROL2_BASE_IDX 2 |
|---|
| 11558 | #define regAPG1_APG_DBG_GEN_CONTROL 0x3706 |
|---|
| 11559 | #define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 |
|---|
| 11560 | #define regAPG1_APG_PACKET_CONTROL 0x3707 |
|---|
| 11561 | #define regAPG1_APG_PACKET_CONTROL 0x3707 |
|---|
| 11562 | #define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 11563 | #define regAPG1_APG_AUDIO_CRC_CONTROL 0x370e |
|---|
| 11564 | #define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 |
|---|
| 11565 | #define regAPG1_APG_AUDIO_CRC_CONTROL2 0x370f |
|---|
| 11566 | #define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 |
|---|
| 11567 | #define regAPG1_APG_AUDIO_CRC_RESULT 0x3710 |
|---|
| 11568 | #define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 |
|---|
| 11569 | #define regAPG1_APG_STATUS 0x3715 |
|---|
| 11570 | #define regAPG1_APG_STATUS_BASE_IDX 2 |
|---|
| 11571 | #define regAPG1_APG_STATUS2 0x3716 |
|---|
| 11572 | #define regAPG1_APG_STATUS2_BASE_IDX 2 |
|---|
| 11573 | #define regAPG1_APG_MEM_PWR 0x3718 |
|---|
| 11574 | #define regAPG1_APG_MEM_PWR_BASE_IDX 2 |
|---|
| 11575 | #define regAPG1_APG_SPARE 0x371a |
|---|
| 11576 | #define regAPG1_APG_SPARE_BASE_IDX 2 |
|---|
| 11577 | |
|---|
| 11578 | |
|---|
| 11579 | // addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec |
|---|
| 11580 | // base address: 0x1af88 |
|---|
| 11581 | #define regDME7_DME_CONTROL 0x3722 |
|---|
| 11582 | #define regDME7_DME_CONTROL_BASE_IDX 2 |
|---|
| 11583 | #define regDME7_DME_MEMORY_CONTROL 0x3723 |
|---|
| 11584 | #define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 |
|---|
| 11585 | |
|---|
| 11586 | |
|---|
| 11587 | // addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec |
|---|
| 11588 | // base address: 0x1af94 |
|---|
| 11589 | #define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 |
|---|
| 11590 | #define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 11591 | #define regVPG7_VPG_GENERIC_PACKET_DATA 0x3726 |
|---|
| 11592 | #define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
|---|
| 11593 | #define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 |
|---|
| 11594 | #define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 11595 | #define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 |
|---|
| 11596 | #define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 11597 | #define regVPG7_VPG_GENERIC_STATUS 0x3729 |
|---|
| 11598 | #define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 |
|---|
| 11599 | #define regVPG7_VPG_MEM_PWR 0x372a |
|---|
| 11600 | #define regVPG7_VPG_MEM_PWR_BASE_IDX 2 |
|---|
| 11601 | #define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x372b |
|---|
| 11602 | #define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 11603 | #define regVPG7_VPG_ISRC1_2_DATA 0x372c |
|---|
| 11604 | #define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 |
|---|
| 11605 | #define regVPG7_VPG_MPEG_INFO0 0x372d |
|---|
| 11606 | #define regVPG7_VPG_MPEG_INFO0_BASE_IDX 2 |
|---|
| 11607 | #define regVPG7_VPG_MPEG_INFO1 0x372e |
|---|
| 11608 | #define regVPG7_VPG_MPEG_INFO1_BASE_IDX 2 |
|---|
| 11609 | |
|---|
| 11610 | |
|---|
| 11611 | // addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec |
|---|
| 11612 | // base address: 0x1afc4 |
|---|
| 11613 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 |
|---|
| 11614 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 |
|---|
| 11615 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 |
|---|
| 11616 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 |
|---|
| 11617 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 |
|---|
| 11618 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
|---|
| 11619 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 |
|---|
| 11620 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
|---|
| 11621 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 |
|---|
| 11622 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 |
|---|
| 11623 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 |
|---|
| 11624 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 |
|---|
| 11625 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 |
|---|
| 11626 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 |
|---|
| 11627 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 |
|---|
| 11628 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 |
|---|
| 11629 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 |
|---|
| 11630 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 |
|---|
| 11631 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a |
|---|
| 11632 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 |
|---|
| 11633 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b |
|---|
| 11634 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 |
|---|
| 11635 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c |
|---|
| 11636 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 |
|---|
| 11637 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d |
|---|
| 11638 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 |
|---|
| 11639 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e |
|---|
| 11640 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 |
|---|
| 11641 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f |
|---|
| 11642 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 |
|---|
| 11643 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 |
|---|
| 11644 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 |
|---|
| 11645 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 |
|---|
| 11646 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 |
|---|
| 11647 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 |
|---|
| 11648 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 |
|---|
| 11649 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 |
|---|
| 11650 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 |
|---|
| 11651 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 |
|---|
| 11652 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 |
|---|
| 11653 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 |
|---|
| 11654 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 |
|---|
| 11655 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 |
|---|
| 11656 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 |
|---|
| 11657 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 |
|---|
| 11658 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 |
|---|
| 11659 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 |
|---|
| 11660 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 |
|---|
| 11661 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 |
|---|
| 11662 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 |
|---|
| 11663 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a |
|---|
| 11664 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 |
|---|
| 11665 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b |
|---|
| 11666 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 |
|---|
| 11667 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c |
|---|
| 11668 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 |
|---|
| 11669 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d |
|---|
| 11670 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 |
|---|
| 11671 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e |
|---|
| 11672 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 |
|---|
| 11673 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f |
|---|
| 11674 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 |
|---|
| 11675 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 |
|---|
| 11676 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 |
|---|
| 11677 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 |
|---|
| 11678 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 |
|---|
| 11679 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 |
|---|
| 11680 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 11681 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 |
|---|
| 11682 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 |
|---|
| 11683 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 |
|---|
| 11684 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 |
|---|
| 11685 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 |
|---|
| 11686 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 |
|---|
| 11687 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a |
|---|
| 11688 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 |
|---|
| 11689 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b |
|---|
| 11690 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 |
|---|
| 11691 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c |
|---|
| 11692 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 |
|---|
| 11693 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d |
|---|
| 11694 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 |
|---|
| 11695 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x375e |
|---|
| 11696 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 |
|---|
| 11697 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x375f |
|---|
| 11698 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 |
|---|
| 11699 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3760 |
|---|
| 11700 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 11701 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3761 |
|---|
| 11702 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 |
|---|
| 11703 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x3762 |
|---|
| 11704 | #define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 |
|---|
| 11705 | |
|---|
| 11706 | |
|---|
| 11707 | // addressBlock: dce_dc_hpo_dp_link_enc1_dispdec |
|---|
| 11708 | // base address: 0x1b0ac |
|---|
| 11709 | #define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x376b |
|---|
| 11710 | #define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 11711 | #define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x376c |
|---|
| 11712 | #define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 |
|---|
| 11713 | |
|---|
| 11714 | |
|---|
| 11715 | // addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec |
|---|
| 11716 | // base address: 0x1b150 |
|---|
| 11717 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3794 |
|---|
| 11718 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 |
|---|
| 11719 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3795 |
|---|
| 11720 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 |
|---|
| 11721 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x3798 |
|---|
| 11722 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 |
|---|
| 11723 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3799 |
|---|
| 11724 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 |
|---|
| 11725 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x379a |
|---|
| 11726 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 |
|---|
| 11727 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x379b |
|---|
| 11728 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 |
|---|
| 11729 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x379c |
|---|
| 11730 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 |
|---|
| 11731 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x379f |
|---|
| 11732 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 |
|---|
| 11733 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x37a0 |
|---|
| 11734 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 |
|---|
| 11735 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x37a1 |
|---|
| 11736 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 |
|---|
| 11737 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x37a2 |
|---|
| 11738 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 |
|---|
| 11739 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x37a5 |
|---|
| 11740 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 |
|---|
| 11741 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x37a6 |
|---|
| 11742 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 |
|---|
| 11743 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x37a7 |
|---|
| 11744 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 |
|---|
| 11745 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x37a8 |
|---|
| 11746 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 |
|---|
| 11747 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37ab |
|---|
| 11748 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 |
|---|
| 11749 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37ac |
|---|
| 11750 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 |
|---|
| 11751 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37ad |
|---|
| 11752 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 |
|---|
| 11753 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ae |
|---|
| 11754 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 |
|---|
| 11755 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37af |
|---|
| 11756 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 |
|---|
| 11757 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37b0 |
|---|
| 11758 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 |
|---|
| 11759 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37b1 |
|---|
| 11760 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 |
|---|
| 11761 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37b2 |
|---|
| 11762 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 |
|---|
| 11763 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b3 |
|---|
| 11764 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 |
|---|
| 11765 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b4 |
|---|
| 11766 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 |
|---|
| 11767 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b5 |
|---|
| 11768 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 |
|---|
| 11769 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b6 |
|---|
| 11770 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 |
|---|
| 11771 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b7 |
|---|
| 11772 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 |
|---|
| 11773 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b8 |
|---|
| 11774 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 |
|---|
| 11775 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b9 |
|---|
| 11776 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 |
|---|
| 11777 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37ba |
|---|
| 11778 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 |
|---|
| 11779 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37bb |
|---|
| 11780 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 |
|---|
| 11781 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37bc |
|---|
| 11782 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 |
|---|
| 11783 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE 0x37be |
|---|
| 11784 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX 2 |
|---|
| 11785 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x37bf |
|---|
| 11786 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 |
|---|
| 11787 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x37c0 |
|---|
| 11788 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 |
|---|
| 11789 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x37c1 |
|---|
| 11790 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 11791 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0 0x37c2 |
|---|
| 11792 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX 2 |
|---|
| 11793 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1 0x37c3 |
|---|
| 11794 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX 2 |
|---|
| 11795 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS 0x37c4 |
|---|
| 11796 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX 2 |
|---|
| 11797 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT 0x37c5 |
|---|
| 11798 | #define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX 2 |
|---|
| 11799 | |
|---|
| 11800 | |
|---|
| 11801 | // addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec |
|---|
| 11802 | // base address: 0x1b22c |
|---|
| 11803 | #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb |
|---|
| 11804 | #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 11805 | #define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc |
|---|
| 11806 | #define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 |
|---|
| 11807 | #define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd |
|---|
| 11808 | #define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 |
|---|
| 11809 | #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce |
|---|
| 11810 | #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 |
|---|
| 11811 | #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf |
|---|
| 11812 | #define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 |
|---|
| 11813 | #define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 |
|---|
| 11814 | #define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 |
|---|
| 11815 | |
|---|
| 11816 | |
|---|
| 11817 | // addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec |
|---|
| 11818 | // base address: 0x1b260 |
|---|
| 11819 | #define regAPG2_APG_CONTROL 0x37d8 |
|---|
| 11820 | #define regAPG2_APG_CONTROL_BASE_IDX 2 |
|---|
| 11821 | #define regAPG2_APG_CONTROL2 0x37d9 |
|---|
| 11822 | #define regAPG2_APG_CONTROL2_BASE_IDX 2 |
|---|
| 11823 | #define regAPG2_APG_DBG_GEN_CONTROL 0x37da |
|---|
| 11824 | #define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 |
|---|
| 11825 | #define regAPG2_APG_PACKET_CONTROL 0x37db |
|---|
| 11826 | #define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 11827 | #define regAPG2_APG_AUDIO_CRC_CONTROL 0x37e2 |
|---|
| 11828 | #define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 |
|---|
| 11829 | #define regAPG2_APG_AUDIO_CRC_CONTROL2 0x37e3 |
|---|
| 11830 | #define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 |
|---|
| 11831 | #define regAPG2_APG_AUDIO_CRC_RESULT 0x37e4 |
|---|
| 11832 | #define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 |
|---|
| 11833 | #define regAPG2_APG_STATUS 0x37e9 |
|---|
| 11834 | #define regAPG2_APG_STATUS_BASE_IDX 2 |
|---|
| 11835 | #define regAPG2_APG_STATUS2 0x37ea |
|---|
| 11836 | #define regAPG2_APG_STATUS2_BASE_IDX 2 |
|---|
| 11837 | #define regAPG2_APG_MEM_PWR 0x37ec |
|---|
| 11838 | #define regAPG2_APG_MEM_PWR_BASE_IDX 2 |
|---|
| 11839 | #define regAPG2_APG_SPARE 0x37ee |
|---|
| 11840 | #define regAPG2_APG_SPARE_BASE_IDX 2 |
|---|
| 11841 | |
|---|
| 11842 | |
|---|
| 11843 | // addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec |
|---|
| 11844 | // base address: 0x1b2d8 |
|---|
| 11845 | #define regDME8_DME_CONTROL 0x37f6 |
|---|
| 11846 | #define regDME8_DME_CONTROL_BASE_IDX 2 |
|---|
| 11847 | #define regDME8_DME_MEMORY_CONTROL 0x37f7 |
|---|
| 11848 | #define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 |
|---|
| 11849 | |
|---|
| 11850 | |
|---|
| 11851 | // addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec |
|---|
| 11852 | // base address: 0x1b2e4 |
|---|
| 11853 | #define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 |
|---|
| 11854 | #define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 11855 | #define regVPG8_VPG_GENERIC_PACKET_DATA 0x37fa |
|---|
| 11856 | #define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
|---|
| 11857 | #define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb |
|---|
| 11858 | #define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 11859 | #define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc |
|---|
| 11860 | #define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 11861 | #define regVPG8_VPG_GENERIC_STATUS 0x37fd |
|---|
| 11862 | #define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 |
|---|
| 11863 | #define regVPG8_VPG_MEM_PWR 0x37fe |
|---|
| 11864 | #define regVPG8_VPG_MEM_PWR_BASE_IDX 2 |
|---|
| 11865 | #define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x37ff |
|---|
| 11866 | #define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 11867 | #define regVPG8_VPG_ISRC1_2_DATA 0x3800 |
|---|
| 11868 | #define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 |
|---|
| 11869 | #define regVPG8_VPG_MPEG_INFO0 0x3801 |
|---|
| 11870 | #define regVPG8_VPG_MPEG_INFO0_BASE_IDX 2 |
|---|
| 11871 | #define regVPG8_VPG_MPEG_INFO1 0x3802 |
|---|
| 11872 | #define regVPG8_VPG_MPEG_INFO1_BASE_IDX 2 |
|---|
| 11873 | |
|---|
| 11874 | |
|---|
| 11875 | // addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec |
|---|
| 11876 | // base address: 0x1b314 |
|---|
| 11877 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 |
|---|
| 11878 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 |
|---|
| 11879 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 |
|---|
| 11880 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 |
|---|
| 11881 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 |
|---|
| 11882 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
|---|
| 11883 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 |
|---|
| 11884 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
|---|
| 11885 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 |
|---|
| 11886 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 |
|---|
| 11887 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a |
|---|
| 11888 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 |
|---|
| 11889 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b |
|---|
| 11890 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 |
|---|
| 11891 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c |
|---|
| 11892 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 |
|---|
| 11893 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d |
|---|
| 11894 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 |
|---|
| 11895 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e |
|---|
| 11896 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 |
|---|
| 11897 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f |
|---|
| 11898 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 |
|---|
| 11899 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 |
|---|
| 11900 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 |
|---|
| 11901 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 |
|---|
| 11902 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 |
|---|
| 11903 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 |
|---|
| 11904 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 |
|---|
| 11905 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 |
|---|
| 11906 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 |
|---|
| 11907 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 |
|---|
| 11908 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 |
|---|
| 11909 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 |
|---|
| 11910 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 |
|---|
| 11911 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 |
|---|
| 11912 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 |
|---|
| 11913 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 |
|---|
| 11914 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 |
|---|
| 11915 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 |
|---|
| 11916 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 |
|---|
| 11917 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 |
|---|
| 11918 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 |
|---|
| 11919 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a |
|---|
| 11920 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 |
|---|
| 11921 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b |
|---|
| 11922 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 |
|---|
| 11923 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c |
|---|
| 11924 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 |
|---|
| 11925 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d |
|---|
| 11926 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 |
|---|
| 11927 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e |
|---|
| 11928 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 |
|---|
| 11929 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f |
|---|
| 11930 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 |
|---|
| 11931 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 |
|---|
| 11932 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 |
|---|
| 11933 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 |
|---|
| 11934 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 |
|---|
| 11935 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 |
|---|
| 11936 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 |
|---|
| 11937 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 |
|---|
| 11938 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 |
|---|
| 11939 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 |
|---|
| 11940 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 |
|---|
| 11941 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 |
|---|
| 11942 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 |
|---|
| 11943 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 |
|---|
| 11944 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 11945 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b |
|---|
| 11946 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 |
|---|
| 11947 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c |
|---|
| 11948 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 |
|---|
| 11949 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d |
|---|
| 11950 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 |
|---|
| 11951 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e |
|---|
| 11952 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 |
|---|
| 11953 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f |
|---|
| 11954 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 |
|---|
| 11955 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 |
|---|
| 11956 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 |
|---|
| 11957 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 |
|---|
| 11958 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 |
|---|
| 11959 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3832 |
|---|
| 11960 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 |
|---|
| 11961 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3833 |
|---|
| 11962 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 |
|---|
| 11963 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3834 |
|---|
| 11964 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 11965 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3835 |
|---|
| 11966 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 |
|---|
| 11967 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3836 |
|---|
| 11968 | #define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 |
|---|
| 11969 | |
|---|
| 11970 | |
|---|
| 11971 | // addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec |
|---|
| 11972 | // base address: 0x1b57c |
|---|
| 11973 | #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f |
|---|
| 11974 | #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 |
|---|
| 11975 | #define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 |
|---|
| 11976 | #define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 |
|---|
| 11977 | #define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 |
|---|
| 11978 | #define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 |
|---|
| 11979 | #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 |
|---|
| 11980 | #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 |
|---|
| 11981 | #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 |
|---|
| 11982 | #define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 |
|---|
| 11983 | #define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 |
|---|
| 11984 | #define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 |
|---|
| 11985 | |
|---|
| 11986 | |
|---|
| 11987 | // addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec |
|---|
| 11988 | // base address: 0x1b5b0 |
|---|
| 11989 | #define regAPG3_APG_CONTROL 0x38ac |
|---|
| 11990 | #define regAPG3_APG_CONTROL_BASE_IDX 2 |
|---|
| 11991 | #define regAPG3_APG_CONTROL2 0x38ad |
|---|
| 11992 | #define regAPG3_APG_CONTROL2_BASE_IDX 2 |
|---|
| 11993 | #define regAPG3_APG_DBG_GEN_CONTROL 0x38ae |
|---|
| 11994 | #define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 |
|---|
| 11995 | #define regAPG3_APG_PACKET_CONTROL 0x38af |
|---|
| 11996 | #define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 11997 | #define regAPG3_APG_AUDIO_CRC_CONTROL 0x38b6 |
|---|
| 11998 | #define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 |
|---|
| 11999 | #define regAPG3_APG_AUDIO_CRC_CONTROL2 0x38b7 |
|---|
| 12000 | #define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 |
|---|
| 12001 | #define regAPG3_APG_AUDIO_CRC_RESULT 0x38b8 |
|---|
| 12002 | #define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 |
|---|
| 12003 | #define regAPG3_APG_STATUS 0x38bd |
|---|
| 12004 | #define regAPG3_APG_STATUS_BASE_IDX 2 |
|---|
| 12005 | #define regAPG3_APG_STATUS2 0x38be |
|---|
| 12006 | #define regAPG3_APG_STATUS2_BASE_IDX 2 |
|---|
| 12007 | #define regAPG3_APG_MEM_PWR 0x38c0 |
|---|
| 12008 | #define regAPG3_APG_MEM_PWR_BASE_IDX 2 |
|---|
| 12009 | #define regAPG3_APG_SPARE 0x38c2 |
|---|
| 12010 | #define regAPG3_APG_SPARE_BASE_IDX 2 |
|---|
| 12011 | |
|---|
| 12012 | |
|---|
| 12013 | // addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec |
|---|
| 12014 | // base address: 0x1b628 |
|---|
| 12015 | #define regDME9_DME_CONTROL 0x38ca |
|---|
| 12016 | #define regDME9_DME_CONTROL_BASE_IDX 2 |
|---|
| 12017 | #define regDME9_DME_MEMORY_CONTROL 0x38cb |
|---|
| 12018 | #define regDME9_DME_MEMORY_CONTROL_BASE_IDX 2 |
|---|
| 12019 | |
|---|
| 12020 | |
|---|
| 12021 | // addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec |
|---|
| 12022 | // base address: 0x1b634 |
|---|
| 12023 | #define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd |
|---|
| 12024 | #define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 12025 | #define regVPG9_VPG_GENERIC_PACKET_DATA 0x38ce |
|---|
| 12026 | #define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 |
|---|
| 12027 | #define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf |
|---|
| 12028 | #define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 12029 | #define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 |
|---|
| 12030 | #define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 |
|---|
| 12031 | #define regVPG9_VPG_GENERIC_STATUS 0x38d1 |
|---|
| 12032 | #define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 2 |
|---|
| 12033 | #define regVPG9_VPG_MEM_PWR 0x38d2 |
|---|
| 12034 | #define regVPG9_VPG_MEM_PWR_BASE_IDX 2 |
|---|
| 12035 | #define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 |
|---|
| 12036 | #define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 |
|---|
| 12037 | #define regVPG9_VPG_ISRC1_2_DATA 0x38d4 |
|---|
| 12038 | #define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 2 |
|---|
| 12039 | #define regVPG9_VPG_MPEG_INFO0 0x38d5 |
|---|
| 12040 | #define regVPG9_VPG_MPEG_INFO0_BASE_IDX 2 |
|---|
| 12041 | #define regVPG9_VPG_MPEG_INFO1 0x38d6 |
|---|
| 12042 | #define regVPG9_VPG_MPEG_INFO1_BASE_IDX 2 |
|---|
| 12043 | |
|---|
| 12044 | |
|---|
| 12045 | // addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec |
|---|
| 12046 | // base address: 0x1b664 |
|---|
| 12047 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 |
|---|
| 12048 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 |
|---|
| 12049 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da |
|---|
| 12050 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 |
|---|
| 12051 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db |
|---|
| 12052 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
|---|
| 12053 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc |
|---|
| 12054 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 |
|---|
| 12055 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd |
|---|
| 12056 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 |
|---|
| 12057 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de |
|---|
| 12058 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 |
|---|
| 12059 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df |
|---|
| 12060 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 |
|---|
| 12061 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 |
|---|
| 12062 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 |
|---|
| 12063 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 |
|---|
| 12064 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 |
|---|
| 12065 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 |
|---|
| 12066 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 |
|---|
| 12067 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 |
|---|
| 12068 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 |
|---|
| 12069 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 |
|---|
| 12070 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 |
|---|
| 12071 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 |
|---|
| 12072 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 |
|---|
| 12073 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 |
|---|
| 12074 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 |
|---|
| 12075 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 |
|---|
| 12076 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 |
|---|
| 12077 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 |
|---|
| 12078 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 |
|---|
| 12079 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 |
|---|
| 12080 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 |
|---|
| 12081 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea |
|---|
| 12082 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 |
|---|
| 12083 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb |
|---|
| 12084 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 |
|---|
| 12085 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec |
|---|
| 12086 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 |
|---|
| 12087 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed |
|---|
| 12088 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 |
|---|
| 12089 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee |
|---|
| 12090 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 |
|---|
| 12091 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef |
|---|
| 12092 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 |
|---|
| 12093 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 |
|---|
| 12094 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 |
|---|
| 12095 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 |
|---|
| 12096 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 |
|---|
| 12097 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 |
|---|
| 12098 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 |
|---|
| 12099 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 |
|---|
| 12100 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 |
|---|
| 12101 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 |
|---|
| 12102 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 |
|---|
| 12103 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 |
|---|
| 12104 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 |
|---|
| 12105 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 |
|---|
| 12106 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 |
|---|
| 12107 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 |
|---|
| 12108 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 |
|---|
| 12109 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 |
|---|
| 12110 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 |
|---|
| 12111 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 |
|---|
| 12112 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 |
|---|
| 12113 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa |
|---|
| 12114 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 |
|---|
| 12115 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff |
|---|
| 12116 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 |
|---|
| 12117 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 |
|---|
| 12118 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 |
|---|
| 12119 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 |
|---|
| 12120 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 |
|---|
| 12121 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 |
|---|
| 12122 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 |
|---|
| 12123 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 |
|---|
| 12124 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 |
|---|
| 12125 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 |
|---|
| 12126 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 |
|---|
| 12127 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 |
|---|
| 12128 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 |
|---|
| 12129 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3906 |
|---|
| 12130 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 |
|---|
| 12131 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3907 |
|---|
| 12132 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 |
|---|
| 12133 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3908 |
|---|
| 12134 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 |
|---|
| 12135 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3909 |
|---|
| 12136 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 |
|---|
| 12137 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x390a |
|---|
| 12138 | #define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 |
|---|
| 12139 | |
|---|
| 12140 | |
|---|
| 12141 | // addressBlock: dce_dc_mpc_mpcc0_dispdec |
|---|
| 12142 | // base address: 0x0 |
|---|
| 12143 | #define regMPCC0_MPCC_TOP_SEL 0x0000 |
|---|
| 12144 | #define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 |
|---|
| 12145 | #define regMPCC0_MPCC_BOT_SEL 0x0001 |
|---|
| 12146 | #define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 |
|---|
| 12147 | #define regMPCC0_MPCC_OPP_ID 0x0002 |
|---|
| 12148 | #define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 |
|---|
| 12149 | #define regMPCC0_MPCC_CONTROL 0x0003 |
|---|
| 12150 | #define regMPCC0_MPCC_CONTROL_BASE_IDX 3 |
|---|
| 12151 | #define regMPCC0_MPCC_SM_CONTROL 0x0004 |
|---|
| 12152 | #define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 |
|---|
| 12153 | #define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005 |
|---|
| 12154 | #define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 |
|---|
| 12155 | #define regMPCC0_MPCC_TOP_GAIN 0x0006 |
|---|
| 12156 | #define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 |
|---|
| 12157 | #define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007 |
|---|
| 12158 | #define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 |
|---|
| 12159 | #define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008 |
|---|
| 12160 | #define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 |
|---|
| 12161 | #define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0009 |
|---|
| 12162 | #define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 |
|---|
| 12163 | #define regMPCC0_MPCC_BG_R_CR 0x000a |
|---|
| 12164 | #define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 |
|---|
| 12165 | #define regMPCC0_MPCC_BG_G_Y 0x000b |
|---|
| 12166 | #define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 |
|---|
| 12167 | #define regMPCC0_MPCC_BG_B_CB 0x000c |
|---|
| 12168 | #define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 |
|---|
| 12169 | #define regMPCC0_MPCC_MEM_PWR_CTRL 0x000d |
|---|
| 12170 | #define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 |
|---|
| 12171 | #define regMPCC0_MPCC_STATUS 0x000e |
|---|
| 12172 | #define regMPCC0_MPCC_STATUS_BASE_IDX 3 |
|---|
| 12173 | |
|---|
| 12174 | |
|---|
| 12175 | // addressBlock: dce_dc_mpc_mpcc1_dispdec |
|---|
| 12176 | // base address: 0x54 |
|---|
| 12177 | #define regMPCC1_MPCC_TOP_SEL 0x0015 |
|---|
| 12178 | #define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 |
|---|
| 12179 | #define regMPCC1_MPCC_BOT_SEL 0x0016 |
|---|
| 12180 | #define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 |
|---|
| 12181 | #define regMPCC1_MPCC_OPP_ID 0x0017 |
|---|
| 12182 | #define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 |
|---|
| 12183 | #define regMPCC1_MPCC_CONTROL 0x0018 |
|---|
| 12184 | #define regMPCC1_MPCC_CONTROL_BASE_IDX 3 |
|---|
| 12185 | #define regMPCC1_MPCC_SM_CONTROL 0x0019 |
|---|
| 12186 | #define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 |
|---|
| 12187 | #define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x001a |
|---|
| 12188 | #define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 |
|---|
| 12189 | #define regMPCC1_MPCC_TOP_GAIN 0x001b |
|---|
| 12190 | #define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 |
|---|
| 12191 | #define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x001c |
|---|
| 12192 | #define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 |
|---|
| 12193 | #define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x001d |
|---|
| 12194 | #define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 |
|---|
| 12195 | #define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x001e |
|---|
| 12196 | #define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 |
|---|
| 12197 | #define regMPCC1_MPCC_BG_R_CR 0x001f |
|---|
| 12198 | #define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 |
|---|
| 12199 | #define regMPCC1_MPCC_BG_G_Y 0x0020 |
|---|
| 12200 | #define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 |
|---|
| 12201 | #define regMPCC1_MPCC_BG_B_CB 0x0021 |
|---|
| 12202 | #define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 |
|---|
| 12203 | #define regMPCC1_MPCC_MEM_PWR_CTRL 0x0022 |
|---|
| 12204 | #define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 |
|---|
| 12205 | #define regMPCC1_MPCC_STATUS 0x0023 |
|---|
| 12206 | #define regMPCC1_MPCC_STATUS_BASE_IDX 3 |
|---|
| 12207 | |
|---|
| 12208 | |
|---|
| 12209 | // addressBlock: dce_dc_mpc_mpcc2_dispdec |
|---|
| 12210 | // base address: 0xa8 |
|---|
| 12211 | #define regMPCC2_MPCC_TOP_SEL 0x002a |
|---|
| 12212 | #define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 |
|---|
| 12213 | #define regMPCC2_MPCC_BOT_SEL 0x002b |
|---|
| 12214 | #define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 |
|---|
| 12215 | #define regMPCC2_MPCC_OPP_ID 0x002c |
|---|
| 12216 | #define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 |
|---|
| 12217 | #define regMPCC2_MPCC_CONTROL 0x002d |
|---|
| 12218 | #define regMPCC2_MPCC_CONTROL_BASE_IDX 3 |
|---|
| 12219 | #define regMPCC2_MPCC_SM_CONTROL 0x002e |
|---|
| 12220 | #define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 |
|---|
| 12221 | #define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x002f |
|---|
| 12222 | #define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 |
|---|
| 12223 | #define regMPCC2_MPCC_TOP_GAIN 0x0030 |
|---|
| 12224 | #define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 |
|---|
| 12225 | #define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0031 |
|---|
| 12226 | #define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 |
|---|
| 12227 | #define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0032 |
|---|
| 12228 | #define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 |
|---|
| 12229 | #define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0033 |
|---|
| 12230 | #define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 |
|---|
| 12231 | #define regMPCC2_MPCC_BG_R_CR 0x0034 |
|---|
| 12232 | #define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 |
|---|
| 12233 | #define regMPCC2_MPCC_BG_G_Y 0x0035 |
|---|
| 12234 | #define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 |
|---|
| 12235 | #define regMPCC2_MPCC_BG_B_CB 0x0036 |
|---|
| 12236 | #define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 |
|---|
| 12237 | #define regMPCC2_MPCC_MEM_PWR_CTRL 0x0037 |
|---|
| 12238 | #define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 |
|---|
| 12239 | #define regMPCC2_MPCC_STATUS 0x0038 |
|---|
| 12240 | #define regMPCC2_MPCC_STATUS_BASE_IDX 3 |
|---|
| 12241 | |
|---|
| 12242 | |
|---|
| 12243 | // addressBlock: dce_dc_mpc_mpcc3_dispdec |
|---|
| 12244 | // base address: 0xfc |
|---|
| 12245 | #define regMPCC3_MPCC_TOP_SEL 0x003f |
|---|
| 12246 | #define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 |
|---|
| 12247 | #define regMPCC3_MPCC_BOT_SEL 0x0040 |
|---|
| 12248 | #define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 |
|---|
| 12249 | #define regMPCC3_MPCC_OPP_ID 0x0041 |
|---|
| 12250 | #define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 |
|---|
| 12251 | #define regMPCC3_MPCC_CONTROL 0x0042 |
|---|
| 12252 | #define regMPCC3_MPCC_CONTROL_BASE_IDX 3 |
|---|
| 12253 | #define regMPCC3_MPCC_SM_CONTROL 0x0043 |
|---|
| 12254 | #define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 |
|---|
| 12255 | #define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0044 |
|---|
| 12256 | #define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 |
|---|
| 12257 | #define regMPCC3_MPCC_TOP_GAIN 0x0045 |
|---|
| 12258 | #define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 |
|---|
| 12259 | #define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0046 |
|---|
| 12260 | #define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 |
|---|
| 12261 | #define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0047 |
|---|
| 12262 | #define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 |
|---|
| 12263 | #define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0048 |
|---|
| 12264 | #define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 |
|---|
| 12265 | #define regMPCC3_MPCC_BG_R_CR 0x0049 |
|---|
| 12266 | #define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 |
|---|
| 12267 | #define regMPCC3_MPCC_BG_G_Y 0x004a |
|---|
| 12268 | #define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 |
|---|
| 12269 | #define regMPCC3_MPCC_BG_B_CB 0x004b |
|---|
| 12270 | #define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 |
|---|
| 12271 | #define regMPCC3_MPCC_MEM_PWR_CTRL 0x004c |
|---|
| 12272 | #define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 |
|---|
| 12273 | #define regMPCC3_MPCC_STATUS 0x004d |
|---|
| 12274 | #define regMPCC3_MPCC_STATUS_BASE_IDX 3 |
|---|
| 12275 | |
|---|
| 12276 | |
|---|
| 12277 | |
|---|
| 12278 | // addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec |
|---|
| 12279 | // base address: 0x0 |
|---|
| 12280 | #define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x00a8 |
|---|
| 12281 | #define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 |
|---|
| 12282 | #define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x00a9 |
|---|
| 12283 | #define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 |
|---|
| 12284 | #define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x00aa |
|---|
| 12285 | #define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 |
|---|
| 12286 | #define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x00ab |
|---|
| 12287 | #define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 |
|---|
| 12288 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x00ac |
|---|
| 12289 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 |
|---|
| 12290 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x00ad |
|---|
| 12291 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 |
|---|
| 12292 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x00ae |
|---|
| 12293 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 |
|---|
| 12294 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x00af |
|---|
| 12295 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 12296 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x00b0 |
|---|
| 12297 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 12298 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x00b1 |
|---|
| 12299 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 12300 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x00b2 |
|---|
| 12301 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 12302 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x00b3 |
|---|
| 12303 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 12304 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x00b4 |
|---|
| 12305 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 12306 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x00b5 |
|---|
| 12307 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 |
|---|
| 12308 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x00b6 |
|---|
| 12309 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 |
|---|
| 12310 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x00b7 |
|---|
| 12311 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 |
|---|
| 12312 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x00b8 |
|---|
| 12313 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 |
|---|
| 12314 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x00b9 |
|---|
| 12315 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 |
|---|
| 12316 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x00ba |
|---|
| 12317 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 |
|---|
| 12318 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x00bb |
|---|
| 12319 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 |
|---|
| 12320 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x00bc |
|---|
| 12321 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 |
|---|
| 12322 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x00bd |
|---|
| 12323 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 |
|---|
| 12324 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x00be |
|---|
| 12325 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 |
|---|
| 12326 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x00bf |
|---|
| 12327 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 |
|---|
| 12328 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x00c0 |
|---|
| 12329 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 |
|---|
| 12330 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x00c1 |
|---|
| 12331 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 |
|---|
| 12332 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x00c2 |
|---|
| 12333 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 |
|---|
| 12334 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x00c3 |
|---|
| 12335 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 |
|---|
| 12336 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x00c4 |
|---|
| 12337 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 |
|---|
| 12338 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x00c5 |
|---|
| 12339 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 |
|---|
| 12340 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x00c6 |
|---|
| 12341 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 |
|---|
| 12342 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x00c7 |
|---|
| 12343 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 |
|---|
| 12344 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x00c8 |
|---|
| 12345 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 |
|---|
| 12346 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x00c9 |
|---|
| 12347 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 |
|---|
| 12348 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x00ca |
|---|
| 12349 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 |
|---|
| 12350 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x00cb |
|---|
| 12351 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 |
|---|
| 12352 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x00cc |
|---|
| 12353 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 |
|---|
| 12354 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x00cd |
|---|
| 12355 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 |
|---|
| 12356 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x00ce |
|---|
| 12357 | #define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 |
|---|
| 12358 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x00cf |
|---|
| 12359 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 |
|---|
| 12360 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x00d0 |
|---|
| 12361 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 |
|---|
| 12362 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x00d1 |
|---|
| 12363 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 |
|---|
| 12364 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x00d2 |
|---|
| 12365 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 12366 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x00d3 |
|---|
| 12367 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 12368 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x00d4 |
|---|
| 12369 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 12370 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x00d5 |
|---|
| 12371 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 12372 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x00d6 |
|---|
| 12373 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 12374 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x00d7 |
|---|
| 12375 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 12376 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x00d8 |
|---|
| 12377 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 |
|---|
| 12378 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x00d9 |
|---|
| 12379 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 |
|---|
| 12380 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x00da |
|---|
| 12381 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 |
|---|
| 12382 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x00db |
|---|
| 12383 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 |
|---|
| 12384 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x00dc |
|---|
| 12385 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 |
|---|
| 12386 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x00dd |
|---|
| 12387 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 |
|---|
| 12388 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x00de |
|---|
| 12389 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 |
|---|
| 12390 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x00df |
|---|
| 12391 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 |
|---|
| 12392 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x00e0 |
|---|
| 12393 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 |
|---|
| 12394 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x00e1 |
|---|
| 12395 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 |
|---|
| 12396 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x00e2 |
|---|
| 12397 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 |
|---|
| 12398 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x00e3 |
|---|
| 12399 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 |
|---|
| 12400 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x00e4 |
|---|
| 12401 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 |
|---|
| 12402 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x00e5 |
|---|
| 12403 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 |
|---|
| 12404 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x00e6 |
|---|
| 12405 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 |
|---|
| 12406 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x00e7 |
|---|
| 12407 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 |
|---|
| 12408 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x00e8 |
|---|
| 12409 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 |
|---|
| 12410 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x00e9 |
|---|
| 12411 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 |
|---|
| 12412 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x00ea |
|---|
| 12413 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 |
|---|
| 12414 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x00eb |
|---|
| 12415 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 |
|---|
| 12416 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x00ec |
|---|
| 12417 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 |
|---|
| 12418 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x00ed |
|---|
| 12419 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 |
|---|
| 12420 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x00ee |
|---|
| 12421 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 |
|---|
| 12422 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x00ef |
|---|
| 12423 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 |
|---|
| 12424 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x00f0 |
|---|
| 12425 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 |
|---|
| 12426 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x00f1 |
|---|
| 12427 | #define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 |
|---|
| 12428 | #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x00f2 |
|---|
| 12429 | #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 |
|---|
| 12430 | #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x00f3 |
|---|
| 12431 | #define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 |
|---|
| 12432 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x00f4 |
|---|
| 12433 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 |
|---|
| 12434 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x00f5 |
|---|
| 12435 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 |
|---|
| 12436 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x00f6 |
|---|
| 12437 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 |
|---|
| 12438 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x00f7 |
|---|
| 12439 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 |
|---|
| 12440 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x00f8 |
|---|
| 12441 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 |
|---|
| 12442 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x00f9 |
|---|
| 12443 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 |
|---|
| 12444 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x00fa |
|---|
| 12445 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 |
|---|
| 12446 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x00fb |
|---|
| 12447 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 |
|---|
| 12448 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x00fc |
|---|
| 12449 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 |
|---|
| 12450 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x00fd |
|---|
| 12451 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 |
|---|
| 12452 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x00fe |
|---|
| 12453 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 |
|---|
| 12454 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x00ff |
|---|
| 12455 | #define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 |
|---|
| 12456 | |
|---|
| 12457 | |
|---|
| 12458 | // addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec |
|---|
| 12459 | // base address: 0x178 |
|---|
| 12460 | #define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0106 |
|---|
| 12461 | #define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 |
|---|
| 12462 | #define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0107 |
|---|
| 12463 | #define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 |
|---|
| 12464 | #define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0108 |
|---|
| 12465 | #define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 |
|---|
| 12466 | #define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0109 |
|---|
| 12467 | #define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 |
|---|
| 12468 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x010a |
|---|
| 12469 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 |
|---|
| 12470 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x010b |
|---|
| 12471 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 |
|---|
| 12472 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x010c |
|---|
| 12473 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 |
|---|
| 12474 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x010d |
|---|
| 12475 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 12476 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x010e |
|---|
| 12477 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 12478 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x010f |
|---|
| 12479 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 12480 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0110 |
|---|
| 12481 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 12482 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0111 |
|---|
| 12483 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 12484 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0112 |
|---|
| 12485 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 12486 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x0113 |
|---|
| 12487 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 |
|---|
| 12488 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x0114 |
|---|
| 12489 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 |
|---|
| 12490 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x0115 |
|---|
| 12491 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 |
|---|
| 12492 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0116 |
|---|
| 12493 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 |
|---|
| 12494 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0117 |
|---|
| 12495 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 |
|---|
| 12496 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0118 |
|---|
| 12497 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 |
|---|
| 12498 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0119 |
|---|
| 12499 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 |
|---|
| 12500 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x011a |
|---|
| 12501 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 |
|---|
| 12502 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x011b |
|---|
| 12503 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 |
|---|
| 12504 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x011c |
|---|
| 12505 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 |
|---|
| 12506 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x011d |
|---|
| 12507 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 |
|---|
| 12508 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x011e |
|---|
| 12509 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 |
|---|
| 12510 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x011f |
|---|
| 12511 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 |
|---|
| 12512 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x0120 |
|---|
| 12513 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 |
|---|
| 12514 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x0121 |
|---|
| 12515 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 |
|---|
| 12516 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x0122 |
|---|
| 12517 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 |
|---|
| 12518 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x0123 |
|---|
| 12519 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 |
|---|
| 12520 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x0124 |
|---|
| 12521 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 |
|---|
| 12522 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x0125 |
|---|
| 12523 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 |
|---|
| 12524 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x0126 |
|---|
| 12525 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 |
|---|
| 12526 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x0127 |
|---|
| 12527 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 |
|---|
| 12528 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x0128 |
|---|
| 12529 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 |
|---|
| 12530 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x0129 |
|---|
| 12531 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 |
|---|
| 12532 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x012a |
|---|
| 12533 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 |
|---|
| 12534 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x012b |
|---|
| 12535 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 |
|---|
| 12536 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x012c |
|---|
| 12537 | #define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 |
|---|
| 12538 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x012d |
|---|
| 12539 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 |
|---|
| 12540 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x012e |
|---|
| 12541 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 |
|---|
| 12542 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x012f |
|---|
| 12543 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 |
|---|
| 12544 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x0130 |
|---|
| 12545 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 12546 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x0131 |
|---|
| 12547 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 12548 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0132 |
|---|
| 12549 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 12550 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0133 |
|---|
| 12551 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 12552 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0134 |
|---|
| 12553 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 12554 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0135 |
|---|
| 12555 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 12556 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x0136 |
|---|
| 12557 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 |
|---|
| 12558 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x0137 |
|---|
| 12559 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 |
|---|
| 12560 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x0138 |
|---|
| 12561 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 |
|---|
| 12562 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x0139 |
|---|
| 12563 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 |
|---|
| 12564 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x013a |
|---|
| 12565 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 |
|---|
| 12566 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x013b |
|---|
| 12567 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 |
|---|
| 12568 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x013c |
|---|
| 12569 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 |
|---|
| 12570 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x013d |
|---|
| 12571 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 |
|---|
| 12572 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x013e |
|---|
| 12573 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 |
|---|
| 12574 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x013f |
|---|
| 12575 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 |
|---|
| 12576 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x0140 |
|---|
| 12577 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 |
|---|
| 12578 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x0141 |
|---|
| 12579 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 |
|---|
| 12580 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x0142 |
|---|
| 12581 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 |
|---|
| 12582 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x0143 |
|---|
| 12583 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 |
|---|
| 12584 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x0144 |
|---|
| 12585 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 |
|---|
| 12586 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x0145 |
|---|
| 12587 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 |
|---|
| 12588 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x0146 |
|---|
| 12589 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 |
|---|
| 12590 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x0147 |
|---|
| 12591 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 |
|---|
| 12592 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x0148 |
|---|
| 12593 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 |
|---|
| 12594 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x0149 |
|---|
| 12595 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 |
|---|
| 12596 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x014a |
|---|
| 12597 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 |
|---|
| 12598 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x014b |
|---|
| 12599 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 |
|---|
| 12600 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x014c |
|---|
| 12601 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 |
|---|
| 12602 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x014d |
|---|
| 12603 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 |
|---|
| 12604 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x014e |
|---|
| 12605 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 |
|---|
| 12606 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x014f |
|---|
| 12607 | #define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 |
|---|
| 12608 | #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x0150 |
|---|
| 12609 | #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 |
|---|
| 12610 | #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x0151 |
|---|
| 12611 | #define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 |
|---|
| 12612 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x0152 |
|---|
| 12613 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 |
|---|
| 12614 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x0153 |
|---|
| 12615 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 |
|---|
| 12616 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x0154 |
|---|
| 12617 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 |
|---|
| 12618 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x0155 |
|---|
| 12619 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 |
|---|
| 12620 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x0156 |
|---|
| 12621 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 |
|---|
| 12622 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x0157 |
|---|
| 12623 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 |
|---|
| 12624 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x0158 |
|---|
| 12625 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 |
|---|
| 12626 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x0159 |
|---|
| 12627 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 |
|---|
| 12628 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x015a |
|---|
| 12629 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 |
|---|
| 12630 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x015b |
|---|
| 12631 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 |
|---|
| 12632 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x015c |
|---|
| 12633 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 |
|---|
| 12634 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x015d |
|---|
| 12635 | #define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 |
|---|
| 12636 | |
|---|
| 12637 | |
|---|
| 12638 | // addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec |
|---|
| 12639 | // base address: 0x2f0 |
|---|
| 12640 | #define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0164 |
|---|
| 12641 | #define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 |
|---|
| 12642 | #define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0165 |
|---|
| 12643 | #define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 |
|---|
| 12644 | #define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0166 |
|---|
| 12645 | #define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 |
|---|
| 12646 | #define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0167 |
|---|
| 12647 | #define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 |
|---|
| 12648 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0168 |
|---|
| 12649 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 |
|---|
| 12650 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0169 |
|---|
| 12651 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 |
|---|
| 12652 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x016a |
|---|
| 12653 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 |
|---|
| 12654 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x016b |
|---|
| 12655 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 12656 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x016c |
|---|
| 12657 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 12658 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x016d |
|---|
| 12659 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 12660 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x016e |
|---|
| 12661 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 12662 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x016f |
|---|
| 12663 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 12664 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0170 |
|---|
| 12665 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 12666 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x0171 |
|---|
| 12667 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 |
|---|
| 12668 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x0172 |
|---|
| 12669 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 |
|---|
| 12670 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x0173 |
|---|
| 12671 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 |
|---|
| 12672 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0174 |
|---|
| 12673 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 |
|---|
| 12674 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0175 |
|---|
| 12675 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 |
|---|
| 12676 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0176 |
|---|
| 12677 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 |
|---|
| 12678 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0177 |
|---|
| 12679 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 |
|---|
| 12680 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0178 |
|---|
| 12681 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 |
|---|
| 12682 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0179 |
|---|
| 12683 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 |
|---|
| 12684 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x017a |
|---|
| 12685 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 |
|---|
| 12686 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x017b |
|---|
| 12687 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 |
|---|
| 12688 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x017c |
|---|
| 12689 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 |
|---|
| 12690 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x017d |
|---|
| 12691 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 |
|---|
| 12692 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x017e |
|---|
| 12693 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 |
|---|
| 12694 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x017f |
|---|
| 12695 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 |
|---|
| 12696 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x0180 |
|---|
| 12697 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 |
|---|
| 12698 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x0181 |
|---|
| 12699 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 |
|---|
| 12700 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x0182 |
|---|
| 12701 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 |
|---|
| 12702 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x0183 |
|---|
| 12703 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 |
|---|
| 12704 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0184 |
|---|
| 12705 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 |
|---|
| 12706 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0185 |
|---|
| 12707 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 |
|---|
| 12708 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0186 |
|---|
| 12709 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 |
|---|
| 12710 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0187 |
|---|
| 12711 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 |
|---|
| 12712 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0188 |
|---|
| 12713 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 |
|---|
| 12714 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0189 |
|---|
| 12715 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 |
|---|
| 12716 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x018a |
|---|
| 12717 | #define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 |
|---|
| 12718 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x018b |
|---|
| 12719 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 |
|---|
| 12720 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x018c |
|---|
| 12721 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 |
|---|
| 12722 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x018d |
|---|
| 12723 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 |
|---|
| 12724 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x018e |
|---|
| 12725 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 12726 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x018f |
|---|
| 12727 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 12728 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0190 |
|---|
| 12729 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 12730 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0191 |
|---|
| 12731 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 12732 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0192 |
|---|
| 12733 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 12734 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0193 |
|---|
| 12735 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 12736 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0194 |
|---|
| 12737 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 |
|---|
| 12738 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0195 |
|---|
| 12739 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 |
|---|
| 12740 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0196 |
|---|
| 12741 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 |
|---|
| 12742 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0197 |
|---|
| 12743 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 |
|---|
| 12744 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0198 |
|---|
| 12745 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 |
|---|
| 12746 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0199 |
|---|
| 12747 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 |
|---|
| 12748 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x019a |
|---|
| 12749 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 |
|---|
| 12750 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x019b |
|---|
| 12751 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 |
|---|
| 12752 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x019c |
|---|
| 12753 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 |
|---|
| 12754 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x019d |
|---|
| 12755 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 |
|---|
| 12756 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x019e |
|---|
| 12757 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 |
|---|
| 12758 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x019f |
|---|
| 12759 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 |
|---|
| 12760 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x01a0 |
|---|
| 12761 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 |
|---|
| 12762 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x01a1 |
|---|
| 12763 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 |
|---|
| 12764 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x01a2 |
|---|
| 12765 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 |
|---|
| 12766 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x01a3 |
|---|
| 12767 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 |
|---|
| 12768 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x01a4 |
|---|
| 12769 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 |
|---|
| 12770 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x01a5 |
|---|
| 12771 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 |
|---|
| 12772 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x01a6 |
|---|
| 12773 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 |
|---|
| 12774 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x01a7 |
|---|
| 12775 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 |
|---|
| 12776 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x01a8 |
|---|
| 12777 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 |
|---|
| 12778 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x01a9 |
|---|
| 12779 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 |
|---|
| 12780 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x01aa |
|---|
| 12781 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 |
|---|
| 12782 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x01ab |
|---|
| 12783 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 |
|---|
| 12784 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x01ac |
|---|
| 12785 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 |
|---|
| 12786 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x01ad |
|---|
| 12787 | #define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 |
|---|
| 12788 | #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ae |
|---|
| 12789 | #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 |
|---|
| 12790 | #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x01af |
|---|
| 12791 | #define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 |
|---|
| 12792 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x01b0 |
|---|
| 12793 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 |
|---|
| 12794 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x01b1 |
|---|
| 12795 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 |
|---|
| 12796 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x01b2 |
|---|
| 12797 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 |
|---|
| 12798 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x01b3 |
|---|
| 12799 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 |
|---|
| 12800 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x01b4 |
|---|
| 12801 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 |
|---|
| 12802 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x01b5 |
|---|
| 12803 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 |
|---|
| 12804 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x01b6 |
|---|
| 12805 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 |
|---|
| 12806 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x01b7 |
|---|
| 12807 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 |
|---|
| 12808 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x01b8 |
|---|
| 12809 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 |
|---|
| 12810 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x01b9 |
|---|
| 12811 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 |
|---|
| 12812 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x01ba |
|---|
| 12813 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 |
|---|
| 12814 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x01bb |
|---|
| 12815 | #define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 |
|---|
| 12816 | |
|---|
| 12817 | |
|---|
| 12818 | // addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec |
|---|
| 12819 | // base address: 0x468 |
|---|
| 12820 | #define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x01c2 |
|---|
| 12821 | #define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 |
|---|
| 12822 | #define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x01c3 |
|---|
| 12823 | #define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 |
|---|
| 12824 | #define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x01c4 |
|---|
| 12825 | #define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 |
|---|
| 12826 | #define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x01c5 |
|---|
| 12827 | #define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 |
|---|
| 12828 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x01c6 |
|---|
| 12829 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 |
|---|
| 12830 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x01c7 |
|---|
| 12831 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 |
|---|
| 12832 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x01c8 |
|---|
| 12833 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 |
|---|
| 12834 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x01c9 |
|---|
| 12835 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 12836 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x01ca |
|---|
| 12837 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 12838 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x01cb |
|---|
| 12839 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 12840 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x01cc |
|---|
| 12841 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 12842 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x01cd |
|---|
| 12843 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 12844 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x01ce |
|---|
| 12845 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 12846 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x01cf |
|---|
| 12847 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 |
|---|
| 12848 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x01d0 |
|---|
| 12849 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 |
|---|
| 12850 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x01d1 |
|---|
| 12851 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 |
|---|
| 12852 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x01d2 |
|---|
| 12853 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 |
|---|
| 12854 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x01d3 |
|---|
| 12855 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 |
|---|
| 12856 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x01d4 |
|---|
| 12857 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 |
|---|
| 12858 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x01d5 |
|---|
| 12859 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 |
|---|
| 12860 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x01d6 |
|---|
| 12861 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 |
|---|
| 12862 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x01d7 |
|---|
| 12863 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 |
|---|
| 12864 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x01d8 |
|---|
| 12865 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 |
|---|
| 12866 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x01d9 |
|---|
| 12867 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 |
|---|
| 12868 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x01da |
|---|
| 12869 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 |
|---|
| 12870 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x01db |
|---|
| 12871 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 |
|---|
| 12872 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x01dc |
|---|
| 12873 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 |
|---|
| 12874 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x01dd |
|---|
| 12875 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 |
|---|
| 12876 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x01de |
|---|
| 12877 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 |
|---|
| 12878 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x01df |
|---|
| 12879 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 |
|---|
| 12880 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x01e0 |
|---|
| 12881 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 |
|---|
| 12882 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x01e1 |
|---|
| 12883 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 |
|---|
| 12884 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x01e2 |
|---|
| 12885 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 |
|---|
| 12886 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x01e3 |
|---|
| 12887 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 |
|---|
| 12888 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x01e4 |
|---|
| 12889 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 |
|---|
| 12890 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x01e5 |
|---|
| 12891 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 |
|---|
| 12892 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x01e6 |
|---|
| 12893 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 |
|---|
| 12894 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x01e7 |
|---|
| 12895 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 |
|---|
| 12896 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x01e8 |
|---|
| 12897 | #define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 |
|---|
| 12898 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x01e9 |
|---|
| 12899 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 |
|---|
| 12900 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x01ea |
|---|
| 12901 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 |
|---|
| 12902 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x01eb |
|---|
| 12903 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 |
|---|
| 12904 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01ec |
|---|
| 12905 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 12906 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ed |
|---|
| 12907 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 12908 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ee |
|---|
| 12909 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 12910 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ef |
|---|
| 12911 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 12912 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01f0 |
|---|
| 12913 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 12914 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01f1 |
|---|
| 12915 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 12916 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x01f2 |
|---|
| 12917 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 |
|---|
| 12918 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x01f3 |
|---|
| 12919 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 |
|---|
| 12920 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x01f4 |
|---|
| 12921 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 |
|---|
| 12922 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x01f5 |
|---|
| 12923 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 |
|---|
| 12924 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x01f6 |
|---|
| 12925 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 |
|---|
| 12926 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x01f7 |
|---|
| 12927 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 |
|---|
| 12928 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x01f8 |
|---|
| 12929 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 |
|---|
| 12930 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x01f9 |
|---|
| 12931 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 |
|---|
| 12932 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x01fa |
|---|
| 12933 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 |
|---|
| 12934 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x01fb |
|---|
| 12935 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 |
|---|
| 12936 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x01fc |
|---|
| 12937 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 |
|---|
| 12938 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x01fd |
|---|
| 12939 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 |
|---|
| 12940 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x01fe |
|---|
| 12941 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 |
|---|
| 12942 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x01ff |
|---|
| 12943 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 |
|---|
| 12944 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x0200 |
|---|
| 12945 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 |
|---|
| 12946 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x0201 |
|---|
| 12947 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 |
|---|
| 12948 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x0202 |
|---|
| 12949 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 |
|---|
| 12950 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x0203 |
|---|
| 12951 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 |
|---|
| 12952 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x0204 |
|---|
| 12953 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 |
|---|
| 12954 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x0205 |
|---|
| 12955 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 |
|---|
| 12956 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x0206 |
|---|
| 12957 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 |
|---|
| 12958 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x0207 |
|---|
| 12959 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 |
|---|
| 12960 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x0208 |
|---|
| 12961 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 |
|---|
| 12962 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x0209 |
|---|
| 12963 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 |
|---|
| 12964 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x020a |
|---|
| 12965 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 |
|---|
| 12966 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x020b |
|---|
| 12967 | #define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 |
|---|
| 12968 | #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x020c |
|---|
| 12969 | #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 |
|---|
| 12970 | #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x020d |
|---|
| 12971 | #define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 |
|---|
| 12972 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x020e |
|---|
| 12973 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 |
|---|
| 12974 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x020f |
|---|
| 12975 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 |
|---|
| 12976 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x0210 |
|---|
| 12977 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 |
|---|
| 12978 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x0211 |
|---|
| 12979 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 |
|---|
| 12980 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x0212 |
|---|
| 12981 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 |
|---|
| 12982 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x0213 |
|---|
| 12983 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 |
|---|
| 12984 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x0214 |
|---|
| 12985 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 |
|---|
| 12986 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x0215 |
|---|
| 12987 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 |
|---|
| 12988 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x0216 |
|---|
| 12989 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 |
|---|
| 12990 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x0217 |
|---|
| 12991 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 |
|---|
| 12992 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x0218 |
|---|
| 12993 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 |
|---|
| 12994 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x0219 |
|---|
| 12995 | #define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 |
|---|
| 12996 | |
|---|
| 12997 | |
|---|
| 12998 | // addressBlock: dce_dc_mpc_mpc_cfg_dispdec |
|---|
| 12999 | // base address: 0x0 |
|---|
| 13000 | #define regMPC_CLOCK_CONTROL 0x0398 |
|---|
| 13001 | #define regMPC_CLOCK_CONTROL_BASE_IDX 3 |
|---|
| 13002 | #define regMPC_SOFT_RESET 0x0399 |
|---|
| 13003 | #define regMPC_SOFT_RESET_BASE_IDX 3 |
|---|
| 13004 | #define regMPC_CRC_CTRL 0x039a |
|---|
| 13005 | #define regMPC_CRC_CTRL_BASE_IDX 3 |
|---|
| 13006 | #define regMPC_CRC_SEL_CONTROL 0x039b |
|---|
| 13007 | #define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 |
|---|
| 13008 | #define regMPC_CRC_RESULT_AR 0x039c |
|---|
| 13009 | #define regMPC_CRC_RESULT_AR_BASE_IDX 3 |
|---|
| 13010 | #define regMPC_CRC_RESULT_GB 0x039d |
|---|
| 13011 | #define regMPC_CRC_RESULT_GB_BASE_IDX 3 |
|---|
| 13012 | #define regMPC_CRC_RESULT_C 0x039e |
|---|
| 13013 | #define regMPC_CRC_RESULT_C_BASE_IDX 3 |
|---|
| 13014 | #define regMPC_PERFMON_EVENT_CTRL 0x03a1 |
|---|
| 13015 | #define regMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 |
|---|
| 13016 | #define regMPC_BYPASS_BG_AR 0x03a2 |
|---|
| 13017 | #define regMPC_BYPASS_BG_AR_BASE_IDX 3 |
|---|
| 13018 | #define regMPC_BYPASS_BG_GB 0x03a3 |
|---|
| 13019 | #define regMPC_BYPASS_BG_GB_BASE_IDX 3 |
|---|
| 13020 | #define regMPC_HOST_READ_CONTROL 0x03a4 |
|---|
| 13021 | #define regMPC_HOST_READ_CONTROL_BASE_IDX 3 |
|---|
| 13022 | #define regMPC_DPP_PENDING_STATUS 0x03a5 |
|---|
| 13023 | #define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 |
|---|
| 13024 | #define regMPC_PENDING_STATUS_MISC 0x03a6 |
|---|
| 13025 | #define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 |
|---|
| 13026 | #define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x03a7 |
|---|
| 13027 | #define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 |
|---|
| 13028 | #define regADR_CFG_VUPDATE_LOCK_SET0 0x03a8 |
|---|
| 13029 | #define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 |
|---|
| 13030 | #define regADR_VUPDATE_LOCK_SET0 0x03a9 |
|---|
| 13031 | #define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 |
|---|
| 13032 | #define regCFG_VUPDATE_LOCK_SET0 0x03aa |
|---|
| 13033 | #define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 |
|---|
| 13034 | #define regCUR_VUPDATE_LOCK_SET0 0x03ab |
|---|
| 13035 | #define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 |
|---|
| 13036 | #define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x03ac |
|---|
| 13037 | #define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 |
|---|
| 13038 | #define regADR_CFG_VUPDATE_LOCK_SET1 0x03ad |
|---|
| 13039 | #define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 |
|---|
| 13040 | #define regADR_VUPDATE_LOCK_SET1 0x03ae |
|---|
| 13041 | #define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 |
|---|
| 13042 | #define regCFG_VUPDATE_LOCK_SET1 0x03af |
|---|
| 13043 | #define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 |
|---|
| 13044 | #define regCUR_VUPDATE_LOCK_SET1 0x03b0 |
|---|
| 13045 | #define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 |
|---|
| 13046 | #define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x03b1 |
|---|
| 13047 | #define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 |
|---|
| 13048 | #define regADR_CFG_VUPDATE_LOCK_SET2 0x03b2 |
|---|
| 13049 | #define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 |
|---|
| 13050 | #define regADR_VUPDATE_LOCK_SET2 0x03b3 |
|---|
| 13051 | #define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 |
|---|
| 13052 | #define regCFG_VUPDATE_LOCK_SET2 0x03b4 |
|---|
| 13053 | #define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 |
|---|
| 13054 | #define regCUR_VUPDATE_LOCK_SET2 0x03b5 |
|---|
| 13055 | #define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 |
|---|
| 13056 | #define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x03b6 |
|---|
| 13057 | #define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 |
|---|
| 13058 | #define regADR_CFG_VUPDATE_LOCK_SET3 0x03b7 |
|---|
| 13059 | #define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 |
|---|
| 13060 | #define regADR_VUPDATE_LOCK_SET3 0x03b8 |
|---|
| 13061 | #define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 |
|---|
| 13062 | #define regCFG_VUPDATE_LOCK_SET3 0x03b9 |
|---|
| 13063 | #define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 |
|---|
| 13064 | #define regCUR_VUPDATE_LOCK_SET3 0x03ba |
|---|
| 13065 | #define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 |
|---|
| 13066 | #define regMPC_DWB0_MUX 0x03c6 |
|---|
| 13067 | #define regMPC_DWB0_MUX_BASE_IDX 3 |
|---|
| 13068 | |
|---|
| 13069 | |
|---|
| 13070 | // addressBlock: dce_dc_mpc_mpc_ocsc_dispdec |
|---|
| 13071 | // base address: 0x0 |
|---|
| 13072 | #define regMPC_OUT0_MUX 0x03d8 |
|---|
| 13073 | #define regMPC_OUT0_MUX_BASE_IDX 3 |
|---|
| 13074 | #define regMPC_OUT0_DENORM_CONTROL 0x03d9 |
|---|
| 13075 | #define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 |
|---|
| 13076 | #define regMPC_OUT0_DENORM_CLAMP_G_Y 0x03da |
|---|
| 13077 | #define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 |
|---|
| 13078 | #define regMPC_OUT0_DENORM_CLAMP_B_CB 0x03db |
|---|
| 13079 | #define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 |
|---|
| 13080 | #define regMPC_OUT1_MUX 0x03dc |
|---|
| 13081 | #define regMPC_OUT1_MUX_BASE_IDX 3 |
|---|
| 13082 | #define regMPC_OUT1_DENORM_CONTROL 0x03dd |
|---|
| 13083 | #define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 |
|---|
| 13084 | #define regMPC_OUT1_DENORM_CLAMP_G_Y 0x03de |
|---|
| 13085 | #define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 |
|---|
| 13086 | #define regMPC_OUT1_DENORM_CLAMP_B_CB 0x03df |
|---|
| 13087 | #define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 |
|---|
| 13088 | #define regMPC_OUT2_MUX 0x03e0 |
|---|
| 13089 | #define regMPC_OUT2_MUX_BASE_IDX 3 |
|---|
| 13090 | #define regMPC_OUT2_DENORM_CONTROL 0x03e1 |
|---|
| 13091 | #define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 |
|---|
| 13092 | #define regMPC_OUT2_DENORM_CLAMP_G_Y 0x03e2 |
|---|
| 13093 | #define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 |
|---|
| 13094 | #define regMPC_OUT2_DENORM_CLAMP_B_CB 0x03e3 |
|---|
| 13095 | #define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 |
|---|
| 13096 | #define regMPC_OUT3_MUX 0x03e4 |
|---|
| 13097 | #define regMPC_OUT3_MUX_BASE_IDX 3 |
|---|
| 13098 | #define regMPC_OUT3_DENORM_CONTROL 0x03e5 |
|---|
| 13099 | #define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 |
|---|
| 13100 | #define regMPC_OUT3_DENORM_CLAMP_G_Y 0x03e6 |
|---|
| 13101 | #define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 |
|---|
| 13102 | #define regMPC_OUT3_DENORM_CLAMP_B_CB 0x03e7 |
|---|
| 13103 | #define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 |
|---|
| 13104 | #define regMPC_OUT_CSC_COEF_FORMAT 0x03f0 |
|---|
| 13105 | #define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 |
|---|
| 13106 | #define regMPC_OUT0_CSC_MODE 0x03f1 |
|---|
| 13107 | #define regMPC_OUT0_CSC_MODE_BASE_IDX 3 |
|---|
| 13108 | #define regMPC_OUT0_CSC_C11_C12_A 0x03f2 |
|---|
| 13109 | #define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 |
|---|
| 13110 | #define regMPC_OUT0_CSC_C13_C14_A 0x03f3 |
|---|
| 13111 | #define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 |
|---|
| 13112 | #define regMPC_OUT0_CSC_C21_C22_A 0x03f4 |
|---|
| 13113 | #define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 |
|---|
| 13114 | #define regMPC_OUT0_CSC_C23_C24_A 0x03f5 |
|---|
| 13115 | #define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 |
|---|
| 13116 | #define regMPC_OUT0_CSC_C31_C32_A 0x03f6 |
|---|
| 13117 | #define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 |
|---|
| 13118 | #define regMPC_OUT0_CSC_C33_C34_A 0x03f7 |
|---|
| 13119 | #define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 |
|---|
| 13120 | #define regMPC_OUT0_CSC_C11_C12_B 0x03f8 |
|---|
| 13121 | #define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 |
|---|
| 13122 | #define regMPC_OUT0_CSC_C13_C14_B 0x03f9 |
|---|
| 13123 | #define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 |
|---|
| 13124 | #define regMPC_OUT0_CSC_C21_C22_B 0x03fa |
|---|
| 13125 | #define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 |
|---|
| 13126 | #define regMPC_OUT0_CSC_C23_C24_B 0x03fb |
|---|
| 13127 | #define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 |
|---|
| 13128 | #define regMPC_OUT0_CSC_C31_C32_B 0x03fc |
|---|
| 13129 | #define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 |
|---|
| 13130 | #define regMPC_OUT0_CSC_C33_C34_B 0x03fd |
|---|
| 13131 | #define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 |
|---|
| 13132 | #define regMPC_OUT1_CSC_MODE 0x03fe |
|---|
| 13133 | #define regMPC_OUT1_CSC_MODE_BASE_IDX 3 |
|---|
| 13134 | #define regMPC_OUT1_CSC_C11_C12_A 0x03ff |
|---|
| 13135 | #define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 |
|---|
| 13136 | #define regMPC_OUT1_CSC_C13_C14_A 0x0400 |
|---|
| 13137 | #define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 |
|---|
| 13138 | #define regMPC_OUT1_CSC_C21_C22_A 0x0401 |
|---|
| 13139 | #define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 |
|---|
| 13140 | #define regMPC_OUT1_CSC_C23_C24_A 0x0402 |
|---|
| 13141 | #define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 |
|---|
| 13142 | #define regMPC_OUT1_CSC_C31_C32_A 0x0403 |
|---|
| 13143 | #define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 |
|---|
| 13144 | #define regMPC_OUT1_CSC_C33_C34_A 0x0404 |
|---|
| 13145 | #define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 |
|---|
| 13146 | #define regMPC_OUT1_CSC_C11_C12_B 0x0405 |
|---|
| 13147 | #define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 |
|---|
| 13148 | #define regMPC_OUT1_CSC_C13_C14_B 0x0406 |
|---|
| 13149 | #define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 |
|---|
| 13150 | #define regMPC_OUT1_CSC_C21_C22_B 0x0407 |
|---|
| 13151 | #define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 |
|---|
| 13152 | #define regMPC_OUT1_CSC_C23_C24_B 0x0408 |
|---|
| 13153 | #define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 |
|---|
| 13154 | #define regMPC_OUT1_CSC_C31_C32_B 0x0409 |
|---|
| 13155 | #define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 |
|---|
| 13156 | #define regMPC_OUT1_CSC_C33_C34_B 0x040a |
|---|
| 13157 | #define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 |
|---|
| 13158 | #define regMPC_OUT2_CSC_MODE 0x040b |
|---|
| 13159 | #define regMPC_OUT2_CSC_MODE_BASE_IDX 3 |
|---|
| 13160 | #define regMPC_OUT2_CSC_C11_C12_A 0x040c |
|---|
| 13161 | #define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 |
|---|
| 13162 | #define regMPC_OUT2_CSC_C13_C14_A 0x040d |
|---|
| 13163 | #define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 |
|---|
| 13164 | #define regMPC_OUT2_CSC_C21_C22_A 0x040e |
|---|
| 13165 | #define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 |
|---|
| 13166 | #define regMPC_OUT2_CSC_C23_C24_A 0x040f |
|---|
| 13167 | #define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 |
|---|
| 13168 | #define regMPC_OUT2_CSC_C31_C32_A 0x0410 |
|---|
| 13169 | #define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 |
|---|
| 13170 | #define regMPC_OUT2_CSC_C33_C34_A 0x0411 |
|---|
| 13171 | #define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 |
|---|
| 13172 | #define regMPC_OUT2_CSC_C11_C12_B 0x0412 |
|---|
| 13173 | #define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 |
|---|
| 13174 | #define regMPC_OUT2_CSC_C13_C14_B 0x0413 |
|---|
| 13175 | #define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 |
|---|
| 13176 | #define regMPC_OUT2_CSC_C21_C22_B 0x0414 |
|---|
| 13177 | #define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 |
|---|
| 13178 | #define regMPC_OUT2_CSC_C23_C24_B 0x0415 |
|---|
| 13179 | #define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 |
|---|
| 13180 | #define regMPC_OUT2_CSC_C31_C32_B 0x0416 |
|---|
| 13181 | #define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 |
|---|
| 13182 | #define regMPC_OUT2_CSC_C33_C34_B 0x0417 |
|---|
| 13183 | #define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 |
|---|
| 13184 | #define regMPC_OUT3_CSC_MODE 0x0418 |
|---|
| 13185 | #define regMPC_OUT3_CSC_MODE_BASE_IDX 3 |
|---|
| 13186 | #define regMPC_OUT3_CSC_C11_C12_A 0x0419 |
|---|
| 13187 | #define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 |
|---|
| 13188 | #define regMPC_OUT3_CSC_C13_C14_A 0x041a |
|---|
| 13189 | #define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 |
|---|
| 13190 | #define regMPC_OUT3_CSC_C21_C22_A 0x041b |
|---|
| 13191 | #define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 |
|---|
| 13192 | #define regMPC_OUT3_CSC_C23_C24_A 0x041c |
|---|
| 13193 | #define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 |
|---|
| 13194 | #define regMPC_OUT3_CSC_C31_C32_A 0x041d |
|---|
| 13195 | #define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 |
|---|
| 13196 | #define regMPC_OUT3_CSC_C33_C34_A 0x041e |
|---|
| 13197 | #define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 |
|---|
| 13198 | #define regMPC_OUT3_CSC_C11_C12_B 0x041f |
|---|
| 13199 | #define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 |
|---|
| 13200 | #define regMPC_OUT3_CSC_C13_C14_B 0x0420 |
|---|
| 13201 | #define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 |
|---|
| 13202 | #define regMPC_OUT3_CSC_C21_C22_B 0x0421 |
|---|
| 13203 | #define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 |
|---|
| 13204 | #define regMPC_OUT3_CSC_C23_C24_B 0x0422 |
|---|
| 13205 | #define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 |
|---|
| 13206 | #define regMPC_OUT3_CSC_C31_C32_B 0x0423 |
|---|
| 13207 | #define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 |
|---|
| 13208 | #define regMPC_OUT3_CSC_C33_C34_B 0x0424 |
|---|
| 13209 | #define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 |
|---|
| 13210 | |
|---|
| 13211 | |
|---|
| 13212 | // addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec |
|---|
| 13213 | // base address: 0x17e1c |
|---|
| 13214 | #define regDC_PERFMON15_PERFCOUNTER_CNTL 0x0447 |
|---|
| 13215 | #define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 3 |
|---|
| 13216 | #define regDC_PERFMON15_PERFCOUNTER_CNTL2 0x0448 |
|---|
| 13217 | #define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 3 |
|---|
| 13218 | #define regDC_PERFMON15_PERFCOUNTER_STATE 0x0449 |
|---|
| 13219 | #define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 3 |
|---|
| 13220 | #define regDC_PERFMON15_PERFMON_CNTL 0x044a |
|---|
| 13221 | #define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX 3 |
|---|
| 13222 | #define regDC_PERFMON15_PERFMON_CNTL2 0x044b |
|---|
| 13223 | #define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 3 |
|---|
| 13224 | #define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x044c |
|---|
| 13225 | #define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 |
|---|
| 13226 | #define regDC_PERFMON15_PERFMON_CVALUE_LOW 0x044d |
|---|
| 13227 | #define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 3 |
|---|
| 13228 | #define regDC_PERFMON15_PERFMON_HI 0x044e |
|---|
| 13229 | #define regDC_PERFMON15_PERFMON_HI_BASE_IDX 3 |
|---|
| 13230 | #define regDC_PERFMON15_PERFMON_LOW 0x044f |
|---|
| 13231 | #define regDC_PERFMON15_PERFMON_LOW_BASE_IDX 3 |
|---|
| 13232 | |
|---|
| 13233 | |
|---|
| 13234 | // addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec |
|---|
| 13235 | // base address: 0x2646c |
|---|
| 13236 | #define regAFMT5_AFMT_ACP 0x091b |
|---|
| 13237 | #define regAFMT5_AFMT_ACP_BASE_IDX 3 |
|---|
| 13238 | #define regAFMT5_AFMT_VBI_PACKET_CONTROL 0x091c |
|---|
| 13239 | #define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3 |
|---|
| 13240 | #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x091d |
|---|
| 13241 | #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3 |
|---|
| 13242 | #define regAFMT5_AFMT_AUDIO_INFO0 0x091e |
|---|
| 13243 | #define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 3 |
|---|
| 13244 | #define regAFMT5_AFMT_AUDIO_INFO1 0x091f |
|---|
| 13245 | #define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 3 |
|---|
| 13246 | #define regAFMT5_AFMT_60958_0 0x0920 |
|---|
| 13247 | #define regAFMT5_AFMT_60958_0_BASE_IDX 3 |
|---|
| 13248 | #define regAFMT5_AFMT_60958_1 0x0921 |
|---|
| 13249 | #define regAFMT5_AFMT_60958_1_BASE_IDX 3 |
|---|
| 13250 | #define regAFMT5_AFMT_AUDIO_CRC_CONTROL 0x0922 |
|---|
| 13251 | #define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3 |
|---|
| 13252 | #define regAFMT5_AFMT_RAMP_CONTROL0 0x0923 |
|---|
| 13253 | #define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 3 |
|---|
| 13254 | #define regAFMT5_AFMT_RAMP_CONTROL1 0x0924 |
|---|
| 13255 | #define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 3 |
|---|
| 13256 | #define regAFMT5_AFMT_RAMP_CONTROL2 0x0925 |
|---|
| 13257 | #define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 3 |
|---|
| 13258 | #define regAFMT5_AFMT_RAMP_CONTROL3 0x0926 |
|---|
| 13259 | #define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 3 |
|---|
| 13260 | #define regAFMT5_AFMT_60958_2 0x0927 |
|---|
| 13261 | #define regAFMT5_AFMT_60958_2_BASE_IDX 3 |
|---|
| 13262 | #define regAFMT5_AFMT_AUDIO_CRC_RESULT 0x0928 |
|---|
| 13263 | #define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3 |
|---|
| 13264 | #define regAFMT5_AFMT_STATUS 0x0929 |
|---|
| 13265 | #define regAFMT5_AFMT_STATUS_BASE_IDX 3 |
|---|
| 13266 | #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x092a |
|---|
| 13267 | #define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3 |
|---|
| 13268 | #define regAFMT5_AFMT_INFOFRAME_CONTROL0 0x092b |
|---|
| 13269 | #define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3 |
|---|
| 13270 | #define regAFMT5_AFMT_INTERRUPT_STATUS 0x092c |
|---|
| 13271 | #define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 3 |
|---|
| 13272 | #define regAFMT5_AFMT_AUDIO_SRC_CONTROL 0x092d |
|---|
| 13273 | #define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3 |
|---|
| 13274 | #define regAFMT5_AFMT_MEM_PWR 0x092f |
|---|
| 13275 | #define regAFMT5_AFMT_MEM_PWR_BASE_IDX 3 |
|---|
| 13276 | |
|---|
| 13277 | |
|---|
| 13278 | // addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec |
|---|
| 13279 | // base address: 0x264c4 |
|---|
| 13280 | #define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 |
|---|
| 13281 | #define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 |
|---|
| 13282 | #define regVPG5_VPG_GENERIC_PACKET_DATA 0x0932 |
|---|
| 13283 | #define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 |
|---|
| 13284 | #define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 |
|---|
| 13285 | #define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 |
|---|
| 13286 | #define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 |
|---|
| 13287 | #define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 |
|---|
| 13288 | #define regVPG5_VPG_GENERIC_STATUS 0x0935 |
|---|
| 13289 | #define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 3 |
|---|
| 13290 | #define regVPG5_VPG_MEM_PWR 0x0936 |
|---|
| 13291 | #define regVPG5_VPG_MEM_PWR_BASE_IDX 3 |
|---|
| 13292 | #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x0937 |
|---|
| 13293 | #define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 |
|---|
| 13294 | #define regVPG5_VPG_ISRC1_2_DATA 0x0938 |
|---|
| 13295 | #define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 3 |
|---|
| 13296 | #define regVPG5_VPG_MPEG_INFO0 0x0939 |
|---|
| 13297 | #define regVPG5_VPG_MPEG_INFO0_BASE_IDX 3 |
|---|
| 13298 | #define regVPG5_VPG_MPEG_INFO1 0x093a |
|---|
| 13299 | #define regVPG5_VPG_MPEG_INFO1_BASE_IDX 3 |
|---|
| 13300 | |
|---|
| 13301 | |
|---|
| 13302 | // addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec |
|---|
| 13303 | // base address: 0x264f0 |
|---|
| 13304 | #define regDME5_DME_CONTROL 0x093c |
|---|
| 13305 | #define regDME5_DME_CONTROL_BASE_IDX 3 |
|---|
| 13306 | #define regDME5_DME_MEMORY_CONTROL 0x093d |
|---|
| 13307 | #define regDME5_DME_MEMORY_CONTROL_BASE_IDX 3 |
|---|
| 13308 | |
|---|
| 13309 | |
|---|
| 13310 | // addressBlock: dce_dc_hpo_hpo_top_dispdec |
|---|
| 13311 | // base address: 0x2790c |
|---|
| 13312 | #define regHPO_TOP_CLOCK_CONTROL 0x0e43 |
|---|
| 13313 | #define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 |
|---|
| 13314 | #define regHPO_TOP_HW_CONTROL 0x0e4a |
|---|
| 13315 | #define regHPO_TOP_HW_CONTROL_BASE_IDX 3 |
|---|
| 13316 | |
|---|
| 13317 | |
|---|
| 13318 | // addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec |
|---|
| 13319 | // base address: 0x27958 |
|---|
| 13320 | #define regDP_STREAM_MAPPER_CONTROL0 0x0e56 |
|---|
| 13321 | #define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 |
|---|
| 13322 | #define regDP_STREAM_MAPPER_CONTROL1 0x0e57 |
|---|
| 13323 | #define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 |
|---|
| 13324 | #define regDP_STREAM_MAPPER_CONTROL2 0x0e58 |
|---|
| 13325 | #define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 |
|---|
| 13326 | #define regDP_STREAM_MAPPER_CONTROL3 0x0e59 |
|---|
| 13327 | #define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 |
|---|
| 13328 | |
|---|
| 13329 | |
|---|
| 13330 | // addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec |
|---|
| 13331 | // base address: 0x1a698 |
|---|
| 13332 | #define regDC_PERFMON23_PERFCOUNTER_CNTL 0x0e66 |
|---|
| 13333 | #define regDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 3 |
|---|
| 13334 | #define regDC_PERFMON23_PERFCOUNTER_CNTL2 0x0e67 |
|---|
| 13335 | #define regDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 3 |
|---|
| 13336 | #define regDC_PERFMON23_PERFCOUNTER_STATE 0x0e68 |
|---|
| 13337 | #define regDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 3 |
|---|
| 13338 | #define regDC_PERFMON23_PERFMON_CNTL 0x0e69 |
|---|
| 13339 | #define regDC_PERFMON23_PERFMON_CNTL_BASE_IDX 3 |
|---|
| 13340 | #define regDC_PERFMON23_PERFMON_CNTL2 0x0e6a |
|---|
| 13341 | #define regDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 3 |
|---|
| 13342 | #define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x0e6b |
|---|
| 13343 | #define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 |
|---|
| 13344 | #define regDC_PERFMON23_PERFMON_CVALUE_LOW 0x0e6c |
|---|
| 13345 | #define regDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 3 |
|---|
| 13346 | #define regDC_PERFMON23_PERFMON_HI 0x0e6d |
|---|
| 13347 | #define regDC_PERFMON23_PERFMON_HI_BASE_IDX 3 |
|---|
| 13348 | #define regDC_PERFMON23_PERFMON_LOW 0x0e6e |
|---|
| 13349 | #define regDC_PERFMON23_PERFMON_LOW_BASE_IDX 3 |
|---|
| 13350 | |
|---|
| 13351 | |
|---|
| 13352 | |
|---|
| 13353 | // addressBlock: dce_dc_opp_abm0_dispdec |
|---|
| 13354 | // base address: 0x0 |
|---|
| 13355 | #define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a |
|---|
| 13356 | #define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 |
|---|
| 13357 | #define regABM0_BL1_PWM_USER_LEVEL 0x0e7b |
|---|
| 13358 | #define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 |
|---|
| 13359 | #define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c |
|---|
| 13360 | #define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 |
|---|
| 13361 | #define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d |
|---|
| 13362 | #define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 |
|---|
| 13363 | #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e |
|---|
| 13364 | #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 |
|---|
| 13365 | #define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f |
|---|
| 13366 | #define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 |
|---|
| 13367 | #define regABM0_BL1_PWM_ABM_CNTL 0x0e80 |
|---|
| 13368 | #define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 |
|---|
| 13369 | #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 |
|---|
| 13370 | #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 |
|---|
| 13371 | #define regABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82 |
|---|
| 13372 | #define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 |
|---|
| 13373 | #define regABM0_DC_ABM1_CNTL 0x0e83 |
|---|
| 13374 | #define regABM0_DC_ABM1_CNTL_BASE_IDX 3 |
|---|
| 13375 | #define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84 |
|---|
| 13376 | #define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 |
|---|
| 13377 | #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85 |
|---|
| 13378 | #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 |
|---|
| 13379 | #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86 |
|---|
| 13380 | #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 |
|---|
| 13381 | #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87 |
|---|
| 13382 | #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 |
|---|
| 13383 | #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88 |
|---|
| 13384 | #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 |
|---|
| 13385 | #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89 |
|---|
| 13386 | #define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 |
|---|
| 13387 | #define regABM0_DC_ABM1_ACE_THRES_12 0x0e8a |
|---|
| 13388 | #define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3 |
|---|
| 13389 | #define regABM0_DC_ABM1_ACE_THRES_34 0x0e8b |
|---|
| 13390 | #define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3 |
|---|
| 13391 | #define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c |
|---|
| 13392 | #define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 |
|---|
| 13393 | #define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e |
|---|
| 13394 | #define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 |
|---|
| 13395 | #define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f |
|---|
| 13396 | #define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 |
|---|
| 13397 | #define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90 |
|---|
| 13398 | #define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 |
|---|
| 13399 | #define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91 |
|---|
| 13400 | #define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 |
|---|
| 13401 | #define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92 |
|---|
| 13402 | #define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 |
|---|
| 13403 | #define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93 |
|---|
| 13404 | #define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 |
|---|
| 13405 | #define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94 |
|---|
| 13406 | #define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 |
|---|
| 13407 | #define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95 |
|---|
| 13408 | #define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 |
|---|
| 13409 | #define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96 |
|---|
| 13410 | #define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 |
|---|
| 13411 | #define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97 |
|---|
| 13412 | #define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 |
|---|
| 13413 | #define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98 |
|---|
| 13414 | #define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 |
|---|
| 13415 | #define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99 |
|---|
| 13416 | #define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 |
|---|
| 13417 | #define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a |
|---|
| 13418 | #define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13419 | #define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b |
|---|
| 13420 | #define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13421 | #define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c |
|---|
| 13422 | #define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13423 | #define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d |
|---|
| 13424 | #define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13425 | #define regABM0_DC_ABM1_HG_RESULT_1 0x0e9e |
|---|
| 13426 | #define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3 |
|---|
| 13427 | #define regABM0_DC_ABM1_HG_RESULT_2 0x0e9f |
|---|
| 13428 | #define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3 |
|---|
| 13429 | #define regABM0_DC_ABM1_HG_RESULT_3 0x0ea0 |
|---|
| 13430 | #define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3 |
|---|
| 13431 | #define regABM0_DC_ABM1_HG_RESULT_4 0x0ea1 |
|---|
| 13432 | #define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3 |
|---|
| 13433 | #define regABM0_DC_ABM1_HG_RESULT_5 0x0ea2 |
|---|
| 13434 | #define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3 |
|---|
| 13435 | #define regABM0_DC_ABM1_HG_RESULT_6 0x0ea3 |
|---|
| 13436 | #define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3 |
|---|
| 13437 | #define regABM0_DC_ABM1_HG_RESULT_7 0x0ea4 |
|---|
| 13438 | #define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3 |
|---|
| 13439 | #define regABM0_DC_ABM1_HG_RESULT_8 0x0ea5 |
|---|
| 13440 | #define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3 |
|---|
| 13441 | #define regABM0_DC_ABM1_HG_RESULT_9 0x0ea6 |
|---|
| 13442 | #define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3 |
|---|
| 13443 | #define regABM0_DC_ABM1_HG_RESULT_10 0x0ea7 |
|---|
| 13444 | #define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3 |
|---|
| 13445 | #define regABM0_DC_ABM1_HG_RESULT_11 0x0ea8 |
|---|
| 13446 | #define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3 |
|---|
| 13447 | #define regABM0_DC_ABM1_HG_RESULT_12 0x0ea9 |
|---|
| 13448 | #define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3 |
|---|
| 13449 | #define regABM0_DC_ABM1_HG_RESULT_13 0x0eaa |
|---|
| 13450 | #define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3 |
|---|
| 13451 | #define regABM0_DC_ABM1_HG_RESULT_14 0x0eab |
|---|
| 13452 | #define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3 |
|---|
| 13453 | #define regABM0_DC_ABM1_HG_RESULT_15 0x0eac |
|---|
| 13454 | #define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3 |
|---|
| 13455 | #define regABM0_DC_ABM1_HG_RESULT_16 0x0ead |
|---|
| 13456 | #define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3 |
|---|
| 13457 | #define regABM0_DC_ABM1_HG_RESULT_17 0x0eae |
|---|
| 13458 | #define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3 |
|---|
| 13459 | #define regABM0_DC_ABM1_HG_RESULT_18 0x0eaf |
|---|
| 13460 | #define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3 |
|---|
| 13461 | #define regABM0_DC_ABM1_HG_RESULT_19 0x0eb0 |
|---|
| 13462 | #define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3 |
|---|
| 13463 | #define regABM0_DC_ABM1_HG_RESULT_20 0x0eb1 |
|---|
| 13464 | #define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3 |
|---|
| 13465 | #define regABM0_DC_ABM1_HG_RESULT_21 0x0eb2 |
|---|
| 13466 | #define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3 |
|---|
| 13467 | #define regABM0_DC_ABM1_HG_RESULT_22 0x0eb3 |
|---|
| 13468 | #define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3 |
|---|
| 13469 | #define regABM0_DC_ABM1_HG_RESULT_23 0x0eb4 |
|---|
| 13470 | #define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3 |
|---|
| 13471 | #define regABM0_DC_ABM1_HG_RESULT_24 0x0eb5 |
|---|
| 13472 | #define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3 |
|---|
| 13473 | #define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6 |
|---|
| 13474 | #define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 |
|---|
| 13475 | |
|---|
| 13476 | |
|---|
| 13477 | // addressBlock: dce_dc_opp_abm1_dispdec |
|---|
| 13478 | // base address: 0x104 |
|---|
| 13479 | #define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb |
|---|
| 13480 | #define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 |
|---|
| 13481 | #define regABM1_BL1_PWM_USER_LEVEL 0x0ebc |
|---|
| 13482 | #define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 |
|---|
| 13483 | #define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd |
|---|
| 13484 | #define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 |
|---|
| 13485 | #define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe |
|---|
| 13486 | #define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 |
|---|
| 13487 | #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf |
|---|
| 13488 | #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 |
|---|
| 13489 | #define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 |
|---|
| 13490 | #define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 |
|---|
| 13491 | #define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 |
|---|
| 13492 | #define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 |
|---|
| 13493 | #define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 |
|---|
| 13494 | #define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 |
|---|
| 13495 | #define regABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3 |
|---|
| 13496 | #define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 |
|---|
| 13497 | #define regABM1_DC_ABM1_CNTL 0x0ec4 |
|---|
| 13498 | #define regABM1_DC_ABM1_CNTL_BASE_IDX 3 |
|---|
| 13499 | #define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5 |
|---|
| 13500 | #define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 |
|---|
| 13501 | #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6 |
|---|
| 13502 | #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 |
|---|
| 13503 | #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7 |
|---|
| 13504 | #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 |
|---|
| 13505 | #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8 |
|---|
| 13506 | #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 |
|---|
| 13507 | #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9 |
|---|
| 13508 | #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 |
|---|
| 13509 | #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca |
|---|
| 13510 | #define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 |
|---|
| 13511 | #define regABM1_DC_ABM1_ACE_THRES_12 0x0ecb |
|---|
| 13512 | #define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3 |
|---|
| 13513 | #define regABM1_DC_ABM1_ACE_THRES_34 0x0ecc |
|---|
| 13514 | #define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3 |
|---|
| 13515 | #define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd |
|---|
| 13516 | #define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 |
|---|
| 13517 | #define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf |
|---|
| 13518 | #define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 |
|---|
| 13519 | #define regABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0 |
|---|
| 13520 | #define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 |
|---|
| 13521 | #define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1 |
|---|
| 13522 | #define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 |
|---|
| 13523 | #define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2 |
|---|
| 13524 | #define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 |
|---|
| 13525 | #define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3 |
|---|
| 13526 | #define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 |
|---|
| 13527 | #define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4 |
|---|
| 13528 | #define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 |
|---|
| 13529 | #define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5 |
|---|
| 13530 | #define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 |
|---|
| 13531 | #define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6 |
|---|
| 13532 | #define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 |
|---|
| 13533 | #define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7 |
|---|
| 13534 | #define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 |
|---|
| 13535 | #define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8 |
|---|
| 13536 | #define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 |
|---|
| 13537 | #define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9 |
|---|
| 13538 | #define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 |
|---|
| 13539 | #define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda |
|---|
| 13540 | #define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 |
|---|
| 13541 | #define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb |
|---|
| 13542 | #define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13543 | #define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc |
|---|
| 13544 | #define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13545 | #define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd |
|---|
| 13546 | #define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13547 | #define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede |
|---|
| 13548 | #define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13549 | #define regABM1_DC_ABM1_HG_RESULT_1 0x0edf |
|---|
| 13550 | #define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3 |
|---|
| 13551 | #define regABM1_DC_ABM1_HG_RESULT_2 0x0ee0 |
|---|
| 13552 | #define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3 |
|---|
| 13553 | #define regABM1_DC_ABM1_HG_RESULT_3 0x0ee1 |
|---|
| 13554 | #define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3 |
|---|
| 13555 | #define regABM1_DC_ABM1_HG_RESULT_4 0x0ee2 |
|---|
| 13556 | #define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3 |
|---|
| 13557 | #define regABM1_DC_ABM1_HG_RESULT_5 0x0ee3 |
|---|
| 13558 | #define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3 |
|---|
| 13559 | #define regABM1_DC_ABM1_HG_RESULT_6 0x0ee4 |
|---|
| 13560 | #define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3 |
|---|
| 13561 | #define regABM1_DC_ABM1_HG_RESULT_7 0x0ee5 |
|---|
| 13562 | #define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3 |
|---|
| 13563 | #define regABM1_DC_ABM1_HG_RESULT_8 0x0ee6 |
|---|
| 13564 | #define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3 |
|---|
| 13565 | #define regABM1_DC_ABM1_HG_RESULT_9 0x0ee7 |
|---|
| 13566 | #define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3 |
|---|
| 13567 | #define regABM1_DC_ABM1_HG_RESULT_10 0x0ee8 |
|---|
| 13568 | #define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3 |
|---|
| 13569 | #define regABM1_DC_ABM1_HG_RESULT_11 0x0ee9 |
|---|
| 13570 | #define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3 |
|---|
| 13571 | #define regABM1_DC_ABM1_HG_RESULT_12 0x0eea |
|---|
| 13572 | #define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3 |
|---|
| 13573 | #define regABM1_DC_ABM1_HG_RESULT_13 0x0eeb |
|---|
| 13574 | #define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3 |
|---|
| 13575 | #define regABM1_DC_ABM1_HG_RESULT_14 0x0eec |
|---|
| 13576 | #define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3 |
|---|
| 13577 | #define regABM1_DC_ABM1_HG_RESULT_15 0x0eed |
|---|
| 13578 | #define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3 |
|---|
| 13579 | #define regABM1_DC_ABM1_HG_RESULT_16 0x0eee |
|---|
| 13580 | #define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3 |
|---|
| 13581 | #define regABM1_DC_ABM1_HG_RESULT_17 0x0eef |
|---|
| 13582 | #define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3 |
|---|
| 13583 | #define regABM1_DC_ABM1_HG_RESULT_18 0x0ef0 |
|---|
| 13584 | #define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3 |
|---|
| 13585 | #define regABM1_DC_ABM1_HG_RESULT_19 0x0ef1 |
|---|
| 13586 | #define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3 |
|---|
| 13587 | #define regABM1_DC_ABM1_HG_RESULT_20 0x0ef2 |
|---|
| 13588 | #define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3 |
|---|
| 13589 | #define regABM1_DC_ABM1_HG_RESULT_21 0x0ef3 |
|---|
| 13590 | #define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3 |
|---|
| 13591 | #define regABM1_DC_ABM1_HG_RESULT_22 0x0ef4 |
|---|
| 13592 | #define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3 |
|---|
| 13593 | #define regABM1_DC_ABM1_HG_RESULT_23 0x0ef5 |
|---|
| 13594 | #define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3 |
|---|
| 13595 | #define regABM1_DC_ABM1_HG_RESULT_24 0x0ef6 |
|---|
| 13596 | #define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3 |
|---|
| 13597 | #define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7 |
|---|
| 13598 | #define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 |
|---|
| 13599 | |
|---|
| 13600 | |
|---|
| 13601 | // addressBlock: dce_dc_opp_abm2_dispdec |
|---|
| 13602 | // base address: 0x208 |
|---|
| 13603 | #define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc |
|---|
| 13604 | #define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 |
|---|
| 13605 | #define regABM2_BL1_PWM_USER_LEVEL 0x0efd |
|---|
| 13606 | #define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 |
|---|
| 13607 | #define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe |
|---|
| 13608 | #define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 |
|---|
| 13609 | #define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff |
|---|
| 13610 | #define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 |
|---|
| 13611 | #define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 |
|---|
| 13612 | #define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 |
|---|
| 13613 | #define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 |
|---|
| 13614 | #define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 |
|---|
| 13615 | #define regABM2_BL1_PWM_ABM_CNTL 0x0f02 |
|---|
| 13616 | #define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 |
|---|
| 13617 | #define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 |
|---|
| 13618 | #define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 |
|---|
| 13619 | #define regABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04 |
|---|
| 13620 | #define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 |
|---|
| 13621 | #define regABM2_DC_ABM1_CNTL 0x0f05 |
|---|
| 13622 | #define regABM2_DC_ABM1_CNTL_BASE_IDX 3 |
|---|
| 13623 | #define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06 |
|---|
| 13624 | #define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 |
|---|
| 13625 | #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07 |
|---|
| 13626 | #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 |
|---|
| 13627 | #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08 |
|---|
| 13628 | #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 |
|---|
| 13629 | #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09 |
|---|
| 13630 | #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 |
|---|
| 13631 | #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a |
|---|
| 13632 | #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 |
|---|
| 13633 | #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b |
|---|
| 13634 | #define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 |
|---|
| 13635 | #define regABM2_DC_ABM1_ACE_THRES_12 0x0f0c |
|---|
| 13636 | #define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3 |
|---|
| 13637 | #define regABM2_DC_ABM1_ACE_THRES_34 0x0f0d |
|---|
| 13638 | #define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3 |
|---|
| 13639 | #define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e |
|---|
| 13640 | #define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 |
|---|
| 13641 | #define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10 |
|---|
| 13642 | #define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 |
|---|
| 13643 | #define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f11 |
|---|
| 13644 | #define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 |
|---|
| 13645 | #define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12 |
|---|
| 13646 | #define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 |
|---|
| 13647 | #define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13 |
|---|
| 13648 | #define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 |
|---|
| 13649 | #define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14 |
|---|
| 13650 | #define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 |
|---|
| 13651 | #define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15 |
|---|
| 13652 | #define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 |
|---|
| 13653 | #define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16 |
|---|
| 13654 | #define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 |
|---|
| 13655 | #define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17 |
|---|
| 13656 | #define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 |
|---|
| 13657 | #define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18 |
|---|
| 13658 | #define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 |
|---|
| 13659 | #define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19 |
|---|
| 13660 | #define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 |
|---|
| 13661 | #define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a |
|---|
| 13662 | #define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 |
|---|
| 13663 | #define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b |
|---|
| 13664 | #define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 |
|---|
| 13665 | #define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c |
|---|
| 13666 | #define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13667 | #define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d |
|---|
| 13668 | #define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13669 | #define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e |
|---|
| 13670 | #define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13671 | #define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f |
|---|
| 13672 | #define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13673 | #define regABM2_DC_ABM1_HG_RESULT_1 0x0f20 |
|---|
| 13674 | #define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3 |
|---|
| 13675 | #define regABM2_DC_ABM1_HG_RESULT_2 0x0f21 |
|---|
| 13676 | #define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3 |
|---|
| 13677 | #define regABM2_DC_ABM1_HG_RESULT_3 0x0f22 |
|---|
| 13678 | #define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3 |
|---|
| 13679 | #define regABM2_DC_ABM1_HG_RESULT_4 0x0f23 |
|---|
| 13680 | #define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3 |
|---|
| 13681 | #define regABM2_DC_ABM1_HG_RESULT_5 0x0f24 |
|---|
| 13682 | #define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3 |
|---|
| 13683 | #define regABM2_DC_ABM1_HG_RESULT_6 0x0f25 |
|---|
| 13684 | #define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3 |
|---|
| 13685 | #define regABM2_DC_ABM1_HG_RESULT_7 0x0f26 |
|---|
| 13686 | #define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3 |
|---|
| 13687 | #define regABM2_DC_ABM1_HG_RESULT_8 0x0f27 |
|---|
| 13688 | #define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3 |
|---|
| 13689 | #define regABM2_DC_ABM1_HG_RESULT_9 0x0f28 |
|---|
| 13690 | #define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3 |
|---|
| 13691 | #define regABM2_DC_ABM1_HG_RESULT_10 0x0f29 |
|---|
| 13692 | #define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3 |
|---|
| 13693 | #define regABM2_DC_ABM1_HG_RESULT_11 0x0f2a |
|---|
| 13694 | #define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3 |
|---|
| 13695 | #define regABM2_DC_ABM1_HG_RESULT_12 0x0f2b |
|---|
| 13696 | #define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3 |
|---|
| 13697 | #define regABM2_DC_ABM1_HG_RESULT_13 0x0f2c |
|---|
| 13698 | #define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3 |
|---|
| 13699 | #define regABM2_DC_ABM1_HG_RESULT_14 0x0f2d |
|---|
| 13700 | #define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3 |
|---|
| 13701 | #define regABM2_DC_ABM1_HG_RESULT_15 0x0f2e |
|---|
| 13702 | #define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3 |
|---|
| 13703 | #define regABM2_DC_ABM1_HG_RESULT_16 0x0f2f |
|---|
| 13704 | #define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3 |
|---|
| 13705 | #define regABM2_DC_ABM1_HG_RESULT_17 0x0f30 |
|---|
| 13706 | #define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3 |
|---|
| 13707 | #define regABM2_DC_ABM1_HG_RESULT_18 0x0f31 |
|---|
| 13708 | #define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3 |
|---|
| 13709 | #define regABM2_DC_ABM1_HG_RESULT_19 0x0f32 |
|---|
| 13710 | #define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3 |
|---|
| 13711 | #define regABM2_DC_ABM1_HG_RESULT_20 0x0f33 |
|---|
| 13712 | #define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3 |
|---|
| 13713 | #define regABM2_DC_ABM1_HG_RESULT_21 0x0f34 |
|---|
| 13714 | #define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3 |
|---|
| 13715 | #define regABM2_DC_ABM1_HG_RESULT_22 0x0f35 |
|---|
| 13716 | #define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3 |
|---|
| 13717 | #define regABM2_DC_ABM1_HG_RESULT_23 0x0f36 |
|---|
| 13718 | #define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3 |
|---|
| 13719 | #define regABM2_DC_ABM1_HG_RESULT_24 0x0f37 |
|---|
| 13720 | #define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3 |
|---|
| 13721 | #define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38 |
|---|
| 13722 | #define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 |
|---|
| 13723 | |
|---|
| 13724 | |
|---|
| 13725 | // addressBlock: dce_dc_opp_abm3_dispdec |
|---|
| 13726 | // base address: 0x30c |
|---|
| 13727 | #define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d |
|---|
| 13728 | #define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 |
|---|
| 13729 | #define regABM3_BL1_PWM_USER_LEVEL 0x0f3e |
|---|
| 13730 | #define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 |
|---|
| 13731 | #define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f |
|---|
| 13732 | #define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 |
|---|
| 13733 | #define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 |
|---|
| 13734 | #define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 |
|---|
| 13735 | #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 |
|---|
| 13736 | #define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 |
|---|
| 13737 | #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 |
|---|
| 13738 | #define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 |
|---|
| 13739 | #define regABM3_BL1_PWM_ABM_CNTL 0x0f43 |
|---|
| 13740 | #define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 |
|---|
| 13741 | #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 |
|---|
| 13742 | #define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 |
|---|
| 13743 | #define regABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45 |
|---|
| 13744 | #define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3 |
|---|
| 13745 | #define regABM3_DC_ABM1_CNTL 0x0f46 |
|---|
| 13746 | #define regABM3_DC_ABM1_CNTL_BASE_IDX 3 |
|---|
| 13747 | #define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47 |
|---|
| 13748 | #define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 |
|---|
| 13749 | #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48 |
|---|
| 13750 | #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3 |
|---|
| 13751 | #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49 |
|---|
| 13752 | #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3 |
|---|
| 13753 | #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a |
|---|
| 13754 | #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3 |
|---|
| 13755 | #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b |
|---|
| 13756 | #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3 |
|---|
| 13757 | #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c |
|---|
| 13758 | #define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3 |
|---|
| 13759 | #define regABM3_DC_ABM1_ACE_THRES_12 0x0f4d |
|---|
| 13760 | #define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3 |
|---|
| 13761 | #define regABM3_DC_ABM1_ACE_THRES_34 0x0f4e |
|---|
| 13762 | #define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3 |
|---|
| 13763 | #define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f |
|---|
| 13764 | #define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 |
|---|
| 13765 | #define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51 |
|---|
| 13766 | #define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 |
|---|
| 13767 | #define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f52 |
|---|
| 13768 | #define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 |
|---|
| 13769 | #define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53 |
|---|
| 13770 | #define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 |
|---|
| 13771 | #define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54 |
|---|
| 13772 | #define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 |
|---|
| 13773 | #define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55 |
|---|
| 13774 | #define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 |
|---|
| 13775 | #define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56 |
|---|
| 13776 | #define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 |
|---|
| 13777 | #define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57 |
|---|
| 13778 | #define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 |
|---|
| 13779 | #define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58 |
|---|
| 13780 | #define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 |
|---|
| 13781 | #define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59 |
|---|
| 13782 | #define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 |
|---|
| 13783 | #define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a |
|---|
| 13784 | #define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 |
|---|
| 13785 | #define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b |
|---|
| 13786 | #define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 |
|---|
| 13787 | #define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c |
|---|
| 13788 | #define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 |
|---|
| 13789 | #define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d |
|---|
| 13790 | #define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13791 | #define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e |
|---|
| 13792 | #define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13793 | #define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f |
|---|
| 13794 | #define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13795 | #define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60 |
|---|
| 13796 | #define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 |
|---|
| 13797 | #define regABM3_DC_ABM1_HG_RESULT_1 0x0f61 |
|---|
| 13798 | #define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3 |
|---|
| 13799 | #define regABM3_DC_ABM1_HG_RESULT_2 0x0f62 |
|---|
| 13800 | #define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3 |
|---|
| 13801 | #define regABM3_DC_ABM1_HG_RESULT_3 0x0f63 |
|---|
| 13802 | #define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3 |
|---|
| 13803 | #define regABM3_DC_ABM1_HG_RESULT_4 0x0f64 |
|---|
| 13804 | #define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3 |
|---|
| 13805 | #define regABM3_DC_ABM1_HG_RESULT_5 0x0f65 |
|---|
| 13806 | #define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3 |
|---|
| 13807 | #define regABM3_DC_ABM1_HG_RESULT_6 0x0f66 |
|---|
| 13808 | #define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3 |
|---|
| 13809 | #define regABM3_DC_ABM1_HG_RESULT_7 0x0f67 |
|---|
| 13810 | #define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3 |
|---|
| 13811 | #define regABM3_DC_ABM1_HG_RESULT_8 0x0f68 |
|---|
| 13812 | #define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3 |
|---|
| 13813 | #define regABM3_DC_ABM1_HG_RESULT_9 0x0f69 |
|---|
| 13814 | #define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3 |
|---|
| 13815 | #define regABM3_DC_ABM1_HG_RESULT_10 0x0f6a |
|---|
| 13816 | #define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3 |
|---|
| 13817 | #define regABM3_DC_ABM1_HG_RESULT_11 0x0f6b |
|---|
| 13818 | #define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3 |
|---|
| 13819 | #define regABM3_DC_ABM1_HG_RESULT_12 0x0f6c |
|---|
| 13820 | #define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3 |
|---|
| 13821 | #define regABM3_DC_ABM1_HG_RESULT_13 0x0f6d |
|---|
| 13822 | #define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3 |
|---|
| 13823 | #define regABM3_DC_ABM1_HG_RESULT_14 0x0f6e |
|---|
| 13824 | #define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3 |
|---|
| 13825 | #define regABM3_DC_ABM1_HG_RESULT_15 0x0f6f |
|---|
| 13826 | #define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3 |
|---|
| 13827 | #define regABM3_DC_ABM1_HG_RESULT_16 0x0f70 |
|---|
| 13828 | #define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3 |
|---|
| 13829 | #define regABM3_DC_ABM1_HG_RESULT_17 0x0f71 |
|---|
| 13830 | #define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3 |
|---|
| 13831 | #define regABM3_DC_ABM1_HG_RESULT_18 0x0f72 |
|---|
| 13832 | #define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3 |
|---|
| 13833 | #define regABM3_DC_ABM1_HG_RESULT_19 0x0f73 |
|---|
| 13834 | #define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3 |
|---|
| 13835 | #define regABM3_DC_ABM1_HG_RESULT_20 0x0f74 |
|---|
| 13836 | #define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3 |
|---|
| 13837 | #define regABM3_DC_ABM1_HG_RESULT_21 0x0f75 |
|---|
| 13838 | #define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3 |
|---|
| 13839 | #define regABM3_DC_ABM1_HG_RESULT_22 0x0f76 |
|---|
| 13840 | #define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3 |
|---|
| 13841 | #define regABM3_DC_ABM1_HG_RESULT_23 0x0f77 |
|---|
| 13842 | #define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3 |
|---|
| 13843 | #define regABM3_DC_ABM1_HG_RESULT_24 0x0f78 |
|---|
| 13844 | #define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3 |
|---|
| 13845 | #define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79 |
|---|
| 13846 | #define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 |
|---|
| 13847 | |
|---|
| 13848 | |
|---|
| 13849 | // addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec |
|---|
| 13850 | // base address: 0x2656c |
|---|
| 13851 | #define regHDMI_LINK_ENC_CONTROL 0x095b |
|---|
| 13852 | #define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 |
|---|
| 13853 | #define regHDMI_LINK_ENC_CLK_CTRL 0x095c |
|---|
| 13854 | #define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 |
|---|
| 13855 | |
|---|
| 13856 | |
|---|
| 13857 | // addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec |
|---|
| 13858 | // base address: 0x26594 |
|---|
| 13859 | #define regHDMI_FRL_ENC_CONFIG 0x0965 |
|---|
| 13860 | #define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 |
|---|
| 13861 | #define regHDMI_FRL_ENC_CONFIG2 0x0966 |
|---|
| 13862 | #define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 |
|---|
| 13863 | #define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 |
|---|
| 13864 | #define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 |
|---|
| 13865 | #define regHDMI_FRL_ENC_MEM_CTRL 0x0968 |
|---|
| 13866 | #define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 |
|---|
| 13867 | |
|---|
| 13868 | |
|---|
| 13869 | // addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec |
|---|
| 13870 | // base address: 0x2634c |
|---|
| 13871 | #define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 |
|---|
| 13872 | #define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 |
|---|
| 13873 | #define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d5 |
|---|
| 13874 | #define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 |
|---|
| 13875 | #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d6 |
|---|
| 13876 | #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 |
|---|
| 13877 | #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d7 |
|---|
| 13878 | #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 |
|---|
| 13879 | #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d8 |
|---|
| 13880 | #define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 |
|---|
| 13881 | |
|---|
| 13882 | |
|---|
| 13883 | // addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec |
|---|
| 13884 | // base address: 0x2637c |
|---|
| 13885 | #define regHDMI_TB_ENC_CONTROL 0x08df |
|---|
| 13886 | #define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 |
|---|
| 13887 | #define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 |
|---|
| 13888 | #define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 |
|---|
| 13889 | #define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 |
|---|
| 13890 | #define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 |
|---|
| 13891 | #define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 |
|---|
| 13892 | #define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 |
|---|
| 13893 | #define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 |
|---|
| 13894 | #define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 |
|---|
| 13895 | #define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 |
|---|
| 13896 | #define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 |
|---|
| 13897 | #define regHDMI_TB_ENC_GC_CONTROL 0x08e5 |
|---|
| 13898 | #define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 |
|---|
| 13899 | #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 |
|---|
| 13900 | #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 |
|---|
| 13901 | #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 |
|---|
| 13902 | #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 |
|---|
| 13903 | #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 |
|---|
| 13904 | #define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 |
|---|
| 13905 | #define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 |
|---|
| 13906 | #define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 |
|---|
| 13907 | #define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea |
|---|
| 13908 | #define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 |
|---|
| 13909 | #define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb |
|---|
| 13910 | #define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 |
|---|
| 13911 | #define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec |
|---|
| 13912 | #define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 |
|---|
| 13913 | #define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed |
|---|
| 13914 | #define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 |
|---|
| 13915 | #define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee |
|---|
| 13916 | #define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 |
|---|
| 13917 | #define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef |
|---|
| 13918 | #define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 |
|---|
| 13919 | #define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 |
|---|
| 13920 | #define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 |
|---|
| 13921 | #define regHDMI_TB_ENC_DB_CONTROL 0x08f1 |
|---|
| 13922 | #define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 |
|---|
| 13923 | #define regHDMI_TB_ENC_ACR_32_0 0x08f2 |
|---|
| 13924 | #define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 |
|---|
| 13925 | #define regHDMI_TB_ENC_ACR_32_1 0x08f3 |
|---|
| 13926 | #define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 |
|---|
| 13927 | #define regHDMI_TB_ENC_ACR_44_0 0x08f4 |
|---|
| 13928 | #define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 |
|---|
| 13929 | #define regHDMI_TB_ENC_ACR_44_1 0x08f5 |
|---|
| 13930 | #define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 |
|---|
| 13931 | #define regHDMI_TB_ENC_ACR_48_0 0x08f6 |
|---|
| 13932 | #define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 |
|---|
| 13933 | #define regHDMI_TB_ENC_ACR_48_1 0x08f7 |
|---|
| 13934 | #define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 |
|---|
| 13935 | #define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 |
|---|
| 13936 | #define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 |
|---|
| 13937 | #define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 |
|---|
| 13938 | #define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 |
|---|
| 13939 | #define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb |
|---|
| 13940 | #define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 |
|---|
| 13941 | #define regHDMI_TB_ENC_MEM_CTRL 0x08fe |
|---|
| 13942 | #define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 |
|---|
| 13943 | #define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff |
|---|
| 13944 | #define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 |
|---|
| 13945 | #define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 |
|---|
| 13946 | #define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 |
|---|
| 13947 | #define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 |
|---|
| 13948 | #define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 |
|---|
| 13949 | #define regHDMI_TB_ENC_CRC_CNTL 0x0903 |
|---|
| 13950 | #define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 |
|---|
| 13951 | #define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 |
|---|
| 13952 | #define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 |
|---|
| 13953 | #define regHDMI_TB_ENC_ENCRYPTION_CONTROL 0x0907 |
|---|
| 13954 | #define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX 3 |
|---|
| 13955 | #define regHDMI_TB_ENC_MODE 0x0908 |
|---|
| 13956 | #define regHDMI_TB_ENC_MODE_BASE_IDX 3 |
|---|
| 13957 | #define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 |
|---|
| 13958 | #define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 |
|---|
| 13959 | #define regHDMI_TB_ENC_CRC_RESULT_1 0x090a |
|---|
| 13960 | #define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 |
|---|
| 13961 | |
|---|
| 13962 | |
|---|
| 13963 | // addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec |
|---|
| 13964 | // base address: 0x0 |
|---|
| 13965 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL 0x0453 |
|---|
| 13966 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 |
|---|
| 13967 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R 0x0454 |
|---|
| 13968 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 |
|---|
| 13969 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G 0x0455 |
|---|
| 13970 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 |
|---|
| 13971 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B 0x0456 |
|---|
| 13972 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 |
|---|
| 13973 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R 0x0457 |
|---|
| 13974 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 |
|---|
| 13975 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B 0x0458 |
|---|
| 13976 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 |
|---|
| 13977 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX 0x0459 |
|---|
| 13978 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 |
|---|
| 13979 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA 0x045a |
|---|
| 13980 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 |
|---|
| 13981 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x045b |
|---|
| 13982 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 |
|---|
| 13983 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x045c |
|---|
| 13984 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 |
|---|
| 13985 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x045d |
|---|
| 13986 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 |
|---|
| 13987 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x045e |
|---|
| 13988 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 |
|---|
| 13989 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x045f |
|---|
| 13990 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 |
|---|
| 13991 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0460 |
|---|
| 13992 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 |
|---|
| 13993 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0461 |
|---|
| 13994 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 |
|---|
| 13995 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0462 |
|---|
| 13996 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 |
|---|
| 13997 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0463 |
|---|
| 13998 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 |
|---|
| 13999 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0464 |
|---|
| 14000 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 |
|---|
| 14001 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0465 |
|---|
| 14002 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 |
|---|
| 14003 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0466 |
|---|
| 14004 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 |
|---|
| 14005 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0467 |
|---|
| 14006 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 |
|---|
| 14007 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0468 |
|---|
| 14008 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 |
|---|
| 14009 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0469 |
|---|
| 14010 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 |
|---|
| 14011 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x046a |
|---|
| 14012 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 |
|---|
| 14013 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x046b |
|---|
| 14014 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 |
|---|
| 14015 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x046c |
|---|
| 14016 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 |
|---|
| 14017 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x046d |
|---|
| 14018 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 |
|---|
| 14019 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x046e |
|---|
| 14020 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 |
|---|
| 14021 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x046f |
|---|
| 14022 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 |
|---|
| 14023 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0470 |
|---|
| 14024 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 |
|---|
| 14025 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0471 |
|---|
| 14026 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 |
|---|
| 14027 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0472 |
|---|
| 14028 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 |
|---|
| 14029 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0473 |
|---|
| 14030 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 |
|---|
| 14031 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0474 |
|---|
| 14032 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 |
|---|
| 14033 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0475 |
|---|
| 14034 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 |
|---|
| 14035 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0476 |
|---|
| 14036 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 |
|---|
| 14037 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0477 |
|---|
| 14038 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 |
|---|
| 14039 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0478 |
|---|
| 14040 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 |
|---|
| 14041 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0479 |
|---|
| 14042 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 |
|---|
| 14043 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x047a |
|---|
| 14044 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 |
|---|
| 14045 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x047b |
|---|
| 14046 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 |
|---|
| 14047 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x047c |
|---|
| 14048 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 |
|---|
| 14049 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x047d |
|---|
| 14050 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 |
|---|
| 14051 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x047e |
|---|
| 14052 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 |
|---|
| 14053 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x047f |
|---|
| 14054 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 |
|---|
| 14055 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0480 |
|---|
| 14056 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 |
|---|
| 14057 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0481 |
|---|
| 14058 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 |
|---|
| 14059 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0482 |
|---|
| 14060 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 |
|---|
| 14061 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0483 |
|---|
| 14062 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 |
|---|
| 14063 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0484 |
|---|
| 14064 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 |
|---|
| 14065 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0485 |
|---|
| 14066 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 |
|---|
| 14067 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0486 |
|---|
| 14068 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 |
|---|
| 14069 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0487 |
|---|
| 14070 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 |
|---|
| 14071 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0488 |
|---|
| 14072 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 |
|---|
| 14073 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0489 |
|---|
| 14074 | #define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 |
|---|
| 14075 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE 0x048a |
|---|
| 14076 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 |
|---|
| 14077 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX 0x048b |
|---|
| 14078 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 |
|---|
| 14079 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA 0x048c |
|---|
| 14080 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 |
|---|
| 14081 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT 0x048d |
|---|
| 14082 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 |
|---|
| 14083 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x048e |
|---|
| 14084 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 |
|---|
| 14085 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x048f |
|---|
| 14086 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 |
|---|
| 14087 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0490 |
|---|
| 14088 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 |
|---|
| 14089 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0491 |
|---|
| 14090 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 |
|---|
| 14091 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0492 |
|---|
| 14092 | #define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 |
|---|
| 14093 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL 0x0493 |
|---|
| 14094 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 |
|---|
| 14095 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX 0x0494 |
|---|
| 14096 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 |
|---|
| 14097 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA 0x0495 |
|---|
| 14098 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 |
|---|
| 14099 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL 0x0496 |
|---|
| 14100 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 |
|---|
| 14101 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0497 |
|---|
| 14102 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 |
|---|
| 14103 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0498 |
|---|
| 14104 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 |
|---|
| 14105 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0499 |
|---|
| 14106 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 |
|---|
| 14107 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x049a |
|---|
| 14108 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 14109 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x049b |
|---|
| 14110 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 14111 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x049c |
|---|
| 14112 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 14113 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x049d |
|---|
| 14114 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 14115 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x049e |
|---|
| 14116 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 14117 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x049f |
|---|
| 14118 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 14119 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x04a0 |
|---|
| 14120 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 |
|---|
| 14121 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x04a1 |
|---|
| 14122 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 |
|---|
| 14123 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x04a2 |
|---|
| 14124 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 |
|---|
| 14125 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x04a3 |
|---|
| 14126 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 |
|---|
| 14127 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x04a4 |
|---|
| 14128 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 |
|---|
| 14129 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x04a5 |
|---|
| 14130 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 |
|---|
| 14131 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x04a6 |
|---|
| 14132 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 |
|---|
| 14133 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x04a7 |
|---|
| 14134 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 |
|---|
| 14135 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x04a8 |
|---|
| 14136 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 |
|---|
| 14137 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x04a9 |
|---|
| 14138 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 |
|---|
| 14139 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x04aa |
|---|
| 14140 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 |
|---|
| 14141 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x04ab |
|---|
| 14142 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 |
|---|
| 14143 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x04ac |
|---|
| 14144 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 |
|---|
| 14145 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x04ad |
|---|
| 14146 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 |
|---|
| 14147 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x04ae |
|---|
| 14148 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 |
|---|
| 14149 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x04af |
|---|
| 14150 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 |
|---|
| 14151 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x04b0 |
|---|
| 14152 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 |
|---|
| 14153 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x04b1 |
|---|
| 14154 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 |
|---|
| 14155 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x04b2 |
|---|
| 14156 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 |
|---|
| 14157 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x04b3 |
|---|
| 14158 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 |
|---|
| 14159 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x04b4 |
|---|
| 14160 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 |
|---|
| 14161 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x04b5 |
|---|
| 14162 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 |
|---|
| 14163 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x04b6 |
|---|
| 14164 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 |
|---|
| 14165 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x04b7 |
|---|
| 14166 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 |
|---|
| 14167 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x04b8 |
|---|
| 14168 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 |
|---|
| 14169 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x04b9 |
|---|
| 14170 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 |
|---|
| 14171 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x04ba |
|---|
| 14172 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 |
|---|
| 14173 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x04bb |
|---|
| 14174 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 |
|---|
| 14175 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x04bc |
|---|
| 14176 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 |
|---|
| 14177 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x04bd |
|---|
| 14178 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 14179 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x04be |
|---|
| 14180 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 14181 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x04bf |
|---|
| 14182 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 14183 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x04c0 |
|---|
| 14184 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 14185 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x04c1 |
|---|
| 14186 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 14187 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x04c2 |
|---|
| 14188 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 14189 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x04c3 |
|---|
| 14190 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 |
|---|
| 14191 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x04c4 |
|---|
| 14192 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 |
|---|
| 14193 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x04c5 |
|---|
| 14194 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 |
|---|
| 14195 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x04c6 |
|---|
| 14196 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 |
|---|
| 14197 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x04c7 |
|---|
| 14198 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 |
|---|
| 14199 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x04c8 |
|---|
| 14200 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 |
|---|
| 14201 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x04c9 |
|---|
| 14202 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 |
|---|
| 14203 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x04ca |
|---|
| 14204 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 |
|---|
| 14205 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x04cb |
|---|
| 14206 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 |
|---|
| 14207 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x04cc |
|---|
| 14208 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 |
|---|
| 14209 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x04cd |
|---|
| 14210 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 |
|---|
| 14211 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x04ce |
|---|
| 14212 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 |
|---|
| 14213 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x04cf |
|---|
| 14214 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 |
|---|
| 14215 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x04d0 |
|---|
| 14216 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 |
|---|
| 14217 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x04d1 |
|---|
| 14218 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 |
|---|
| 14219 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x04d2 |
|---|
| 14220 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 |
|---|
| 14221 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x04d3 |
|---|
| 14222 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 |
|---|
| 14223 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x04d4 |
|---|
| 14224 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 |
|---|
| 14225 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x04d5 |
|---|
| 14226 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 |
|---|
| 14227 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x04d6 |
|---|
| 14228 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 |
|---|
| 14229 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x04d7 |
|---|
| 14230 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 |
|---|
| 14231 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x04d8 |
|---|
| 14232 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 |
|---|
| 14233 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x04d9 |
|---|
| 14234 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 |
|---|
| 14235 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x04da |
|---|
| 14236 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 |
|---|
| 14237 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x04db |
|---|
| 14238 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 |
|---|
| 14239 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x04dc |
|---|
| 14240 | #define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 |
|---|
| 14241 | #define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL 0x04dd |
|---|
| 14242 | #define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 |
|---|
| 14243 | |
|---|
| 14244 | |
|---|
| 14245 | // addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec |
|---|
| 14246 | // base address: 0x240 |
|---|
| 14247 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL 0x04e3 |
|---|
| 14248 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 |
|---|
| 14249 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R 0x04e4 |
|---|
| 14250 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 |
|---|
| 14251 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G 0x04e5 |
|---|
| 14252 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 |
|---|
| 14253 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B 0x04e6 |
|---|
| 14254 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 |
|---|
| 14255 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R 0x04e7 |
|---|
| 14256 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 |
|---|
| 14257 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B 0x04e8 |
|---|
| 14258 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 |
|---|
| 14259 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX 0x04e9 |
|---|
| 14260 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 |
|---|
| 14261 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA 0x04ea |
|---|
| 14262 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 |
|---|
| 14263 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x04eb |
|---|
| 14264 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 |
|---|
| 14265 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x04ec |
|---|
| 14266 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 |
|---|
| 14267 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x04ed |
|---|
| 14268 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 |
|---|
| 14269 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x04ee |
|---|
| 14270 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 |
|---|
| 14271 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x04ef |
|---|
| 14272 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 |
|---|
| 14273 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x04f0 |
|---|
| 14274 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 |
|---|
| 14275 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x04f1 |
|---|
| 14276 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 |
|---|
| 14277 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x04f2 |
|---|
| 14278 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 |
|---|
| 14279 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x04f3 |
|---|
| 14280 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 |
|---|
| 14281 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x04f4 |
|---|
| 14282 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 |
|---|
| 14283 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x04f5 |
|---|
| 14284 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 |
|---|
| 14285 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x04f6 |
|---|
| 14286 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 |
|---|
| 14287 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x04f7 |
|---|
| 14288 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 |
|---|
| 14289 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x04f8 |
|---|
| 14290 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 |
|---|
| 14291 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x04f9 |
|---|
| 14292 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 |
|---|
| 14293 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x04fa |
|---|
| 14294 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 |
|---|
| 14295 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x04fb |
|---|
| 14296 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 |
|---|
| 14297 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x04fc |
|---|
| 14298 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 |
|---|
| 14299 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x04fd |
|---|
| 14300 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 |
|---|
| 14301 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x04fe |
|---|
| 14302 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 |
|---|
| 14303 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x04ff |
|---|
| 14304 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 |
|---|
| 14305 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0500 |
|---|
| 14306 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 |
|---|
| 14307 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0501 |
|---|
| 14308 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 |
|---|
| 14309 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0502 |
|---|
| 14310 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 |
|---|
| 14311 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0503 |
|---|
| 14312 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 |
|---|
| 14313 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0504 |
|---|
| 14314 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 |
|---|
| 14315 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0505 |
|---|
| 14316 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 |
|---|
| 14317 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0506 |
|---|
| 14318 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 |
|---|
| 14319 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0507 |
|---|
| 14320 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 |
|---|
| 14321 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0508 |
|---|
| 14322 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 |
|---|
| 14323 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0509 |
|---|
| 14324 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 |
|---|
| 14325 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x050a |
|---|
| 14326 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 |
|---|
| 14327 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x050b |
|---|
| 14328 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 |
|---|
| 14329 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x050c |
|---|
| 14330 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 |
|---|
| 14331 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x050d |
|---|
| 14332 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 |
|---|
| 14333 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x050e |
|---|
| 14334 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 |
|---|
| 14335 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x050f |
|---|
| 14336 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 |
|---|
| 14337 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0510 |
|---|
| 14338 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 |
|---|
| 14339 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0511 |
|---|
| 14340 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 |
|---|
| 14341 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0512 |
|---|
| 14342 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 |
|---|
| 14343 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0513 |
|---|
| 14344 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 |
|---|
| 14345 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0514 |
|---|
| 14346 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 |
|---|
| 14347 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0515 |
|---|
| 14348 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 |
|---|
| 14349 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0516 |
|---|
| 14350 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 |
|---|
| 14351 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0517 |
|---|
| 14352 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 |
|---|
| 14353 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0518 |
|---|
| 14354 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 |
|---|
| 14355 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0519 |
|---|
| 14356 | #define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 |
|---|
| 14357 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE 0x051a |
|---|
| 14358 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 |
|---|
| 14359 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX 0x051b |
|---|
| 14360 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 |
|---|
| 14361 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA 0x051c |
|---|
| 14362 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 |
|---|
| 14363 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT 0x051d |
|---|
| 14364 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 |
|---|
| 14365 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x051e |
|---|
| 14366 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 |
|---|
| 14367 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x051f |
|---|
| 14368 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 |
|---|
| 14369 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0520 |
|---|
| 14370 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 |
|---|
| 14371 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0521 |
|---|
| 14372 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 |
|---|
| 14373 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0522 |
|---|
| 14374 | #define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 |
|---|
| 14375 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL 0x0523 |
|---|
| 14376 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 |
|---|
| 14377 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX 0x0524 |
|---|
| 14378 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 |
|---|
| 14379 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA 0x0525 |
|---|
| 14380 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 |
|---|
| 14381 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL 0x0526 |
|---|
| 14382 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 |
|---|
| 14383 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0527 |
|---|
| 14384 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 |
|---|
| 14385 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0528 |
|---|
| 14386 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 |
|---|
| 14387 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0529 |
|---|
| 14388 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 |
|---|
| 14389 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x052a |
|---|
| 14390 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 14391 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x052b |
|---|
| 14392 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 14393 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x052c |
|---|
| 14394 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 14395 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x052d |
|---|
| 14396 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 14397 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x052e |
|---|
| 14398 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 14399 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x052f |
|---|
| 14400 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 14401 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0530 |
|---|
| 14402 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 |
|---|
| 14403 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0531 |
|---|
| 14404 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 |
|---|
| 14405 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0532 |
|---|
| 14406 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 |
|---|
| 14407 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0533 |
|---|
| 14408 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 |
|---|
| 14409 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0534 |
|---|
| 14410 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 |
|---|
| 14411 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0535 |
|---|
| 14412 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 |
|---|
| 14413 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0536 |
|---|
| 14414 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 |
|---|
| 14415 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0537 |
|---|
| 14416 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 |
|---|
| 14417 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0538 |
|---|
| 14418 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 |
|---|
| 14419 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0539 |
|---|
| 14420 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 |
|---|
| 14421 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x053a |
|---|
| 14422 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 |
|---|
| 14423 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x053b |
|---|
| 14424 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 |
|---|
| 14425 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x053c |
|---|
| 14426 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 |
|---|
| 14427 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x053d |
|---|
| 14428 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 |
|---|
| 14429 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x053e |
|---|
| 14430 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 |
|---|
| 14431 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x053f |
|---|
| 14432 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 |
|---|
| 14433 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0540 |
|---|
| 14434 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 |
|---|
| 14435 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0541 |
|---|
| 14436 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 |
|---|
| 14437 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0542 |
|---|
| 14438 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 |
|---|
| 14439 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0543 |
|---|
| 14440 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 |
|---|
| 14441 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0544 |
|---|
| 14442 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 |
|---|
| 14443 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0545 |
|---|
| 14444 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 |
|---|
| 14445 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0546 |
|---|
| 14446 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 |
|---|
| 14447 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0547 |
|---|
| 14448 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 |
|---|
| 14449 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0548 |
|---|
| 14450 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 |
|---|
| 14451 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0549 |
|---|
| 14452 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 |
|---|
| 14453 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x054a |
|---|
| 14454 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 |
|---|
| 14455 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x054b |
|---|
| 14456 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 |
|---|
| 14457 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x054c |
|---|
| 14458 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 |
|---|
| 14459 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x054d |
|---|
| 14460 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 14461 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x054e |
|---|
| 14462 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 14463 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x054f |
|---|
| 14464 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 14465 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0550 |
|---|
| 14466 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 14467 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0551 |
|---|
| 14468 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 14469 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0552 |
|---|
| 14470 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 14471 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0553 |
|---|
| 14472 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 |
|---|
| 14473 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0554 |
|---|
| 14474 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 |
|---|
| 14475 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0555 |
|---|
| 14476 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 |
|---|
| 14477 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0556 |
|---|
| 14478 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 |
|---|
| 14479 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0557 |
|---|
| 14480 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 |
|---|
| 14481 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0558 |
|---|
| 14482 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 |
|---|
| 14483 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0559 |
|---|
| 14484 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 |
|---|
| 14485 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x055a |
|---|
| 14486 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 |
|---|
| 14487 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x055b |
|---|
| 14488 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 |
|---|
| 14489 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x055c |
|---|
| 14490 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 |
|---|
| 14491 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x055d |
|---|
| 14492 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 |
|---|
| 14493 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x055e |
|---|
| 14494 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 |
|---|
| 14495 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x055f |
|---|
| 14496 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 |
|---|
| 14497 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0560 |
|---|
| 14498 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 |
|---|
| 14499 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0561 |
|---|
| 14500 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 |
|---|
| 14501 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0562 |
|---|
| 14502 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 |
|---|
| 14503 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0563 |
|---|
| 14504 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 |
|---|
| 14505 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0564 |
|---|
| 14506 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 |
|---|
| 14507 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0565 |
|---|
| 14508 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 |
|---|
| 14509 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0566 |
|---|
| 14510 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 |
|---|
| 14511 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0567 |
|---|
| 14512 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 |
|---|
| 14513 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0568 |
|---|
| 14514 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 |
|---|
| 14515 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0569 |
|---|
| 14516 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 |
|---|
| 14517 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x056a |
|---|
| 14518 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 |
|---|
| 14519 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x056b |
|---|
| 14520 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 |
|---|
| 14521 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x056c |
|---|
| 14522 | #define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 |
|---|
| 14523 | #define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL 0x056d |
|---|
| 14524 | #define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 |
|---|
| 14525 | |
|---|
| 14526 | |
|---|
| 14527 | // addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec |
|---|
| 14528 | // base address: 0x480 |
|---|
| 14529 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL 0x0573 |
|---|
| 14530 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 |
|---|
| 14531 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R 0x0574 |
|---|
| 14532 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 |
|---|
| 14533 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G 0x0575 |
|---|
| 14534 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 |
|---|
| 14535 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B 0x0576 |
|---|
| 14536 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 |
|---|
| 14537 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R 0x0577 |
|---|
| 14538 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 |
|---|
| 14539 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B 0x0578 |
|---|
| 14540 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 |
|---|
| 14541 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX 0x0579 |
|---|
| 14542 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 |
|---|
| 14543 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA 0x057a |
|---|
| 14544 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 |
|---|
| 14545 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x057b |
|---|
| 14546 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 |
|---|
| 14547 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x057c |
|---|
| 14548 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 |
|---|
| 14549 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x057d |
|---|
| 14550 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 |
|---|
| 14551 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x057e |
|---|
| 14552 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 |
|---|
| 14553 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x057f |
|---|
| 14554 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 |
|---|
| 14555 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0580 |
|---|
| 14556 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 |
|---|
| 14557 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0581 |
|---|
| 14558 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 |
|---|
| 14559 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0582 |
|---|
| 14560 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 |
|---|
| 14561 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0583 |
|---|
| 14562 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 |
|---|
| 14563 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0584 |
|---|
| 14564 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 |
|---|
| 14565 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0585 |
|---|
| 14566 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 |
|---|
| 14567 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0586 |
|---|
| 14568 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 |
|---|
| 14569 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0587 |
|---|
| 14570 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 |
|---|
| 14571 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0588 |
|---|
| 14572 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 |
|---|
| 14573 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0589 |
|---|
| 14574 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 |
|---|
| 14575 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x058a |
|---|
| 14576 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 |
|---|
| 14577 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x058b |
|---|
| 14578 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 |
|---|
| 14579 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x058c |
|---|
| 14580 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 |
|---|
| 14581 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x058d |
|---|
| 14582 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 |
|---|
| 14583 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x058e |
|---|
| 14584 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 |
|---|
| 14585 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x058f |
|---|
| 14586 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 |
|---|
| 14587 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0590 |
|---|
| 14588 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 |
|---|
| 14589 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0591 |
|---|
| 14590 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 |
|---|
| 14591 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0592 |
|---|
| 14592 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 |
|---|
| 14593 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0593 |
|---|
| 14594 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 |
|---|
| 14595 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0594 |
|---|
| 14596 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 |
|---|
| 14597 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0595 |
|---|
| 14598 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 |
|---|
| 14599 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0596 |
|---|
| 14600 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 |
|---|
| 14601 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0597 |
|---|
| 14602 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 |
|---|
| 14603 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0598 |
|---|
| 14604 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 |
|---|
| 14605 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0599 |
|---|
| 14606 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 |
|---|
| 14607 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x059a |
|---|
| 14608 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 |
|---|
| 14609 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x059b |
|---|
| 14610 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 |
|---|
| 14611 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x059c |
|---|
| 14612 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 |
|---|
| 14613 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x059d |
|---|
| 14614 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 |
|---|
| 14615 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x059e |
|---|
| 14616 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 |
|---|
| 14617 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x059f |
|---|
| 14618 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 |
|---|
| 14619 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x05a0 |
|---|
| 14620 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 |
|---|
| 14621 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x05a1 |
|---|
| 14622 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 |
|---|
| 14623 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x05a2 |
|---|
| 14624 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 |
|---|
| 14625 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x05a3 |
|---|
| 14626 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 |
|---|
| 14627 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x05a4 |
|---|
| 14628 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 |
|---|
| 14629 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x05a5 |
|---|
| 14630 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 |
|---|
| 14631 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x05a6 |
|---|
| 14632 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 |
|---|
| 14633 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x05a7 |
|---|
| 14634 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 |
|---|
| 14635 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x05a8 |
|---|
| 14636 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 |
|---|
| 14637 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x05a9 |
|---|
| 14638 | #define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 |
|---|
| 14639 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE 0x05aa |
|---|
| 14640 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 |
|---|
| 14641 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX 0x05ab |
|---|
| 14642 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 |
|---|
| 14643 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA 0x05ac |
|---|
| 14644 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 |
|---|
| 14645 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT 0x05ad |
|---|
| 14646 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 |
|---|
| 14647 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x05ae |
|---|
| 14648 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 |
|---|
| 14649 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x05af |
|---|
| 14650 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 |
|---|
| 14651 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x05b0 |
|---|
| 14652 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 |
|---|
| 14653 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x05b1 |
|---|
| 14654 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 |
|---|
| 14655 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x05b2 |
|---|
| 14656 | #define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 |
|---|
| 14657 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL 0x05b3 |
|---|
| 14658 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 |
|---|
| 14659 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX 0x05b4 |
|---|
| 14660 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 |
|---|
| 14661 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA 0x05b5 |
|---|
| 14662 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 |
|---|
| 14663 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL 0x05b6 |
|---|
| 14664 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 |
|---|
| 14665 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x05b7 |
|---|
| 14666 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 |
|---|
| 14667 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x05b8 |
|---|
| 14668 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 |
|---|
| 14669 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x05b9 |
|---|
| 14670 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 |
|---|
| 14671 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x05ba |
|---|
| 14672 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 14673 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x05bb |
|---|
| 14674 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 14675 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x05bc |
|---|
| 14676 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 14677 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x05bd |
|---|
| 14678 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 14679 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x05be |
|---|
| 14680 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 14681 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x05bf |
|---|
| 14682 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 14683 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x05c0 |
|---|
| 14684 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 |
|---|
| 14685 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x05c1 |
|---|
| 14686 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 |
|---|
| 14687 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x05c2 |
|---|
| 14688 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 |
|---|
| 14689 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x05c3 |
|---|
| 14690 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 |
|---|
| 14691 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x05c4 |
|---|
| 14692 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 |
|---|
| 14693 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x05c5 |
|---|
| 14694 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 |
|---|
| 14695 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x05c6 |
|---|
| 14696 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 |
|---|
| 14697 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x05c7 |
|---|
| 14698 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 |
|---|
| 14699 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x05c8 |
|---|
| 14700 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 |
|---|
| 14701 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x05c9 |
|---|
| 14702 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 |
|---|
| 14703 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x05ca |
|---|
| 14704 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 |
|---|
| 14705 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x05cb |
|---|
| 14706 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 |
|---|
| 14707 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x05cc |
|---|
| 14708 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 |
|---|
| 14709 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x05cd |
|---|
| 14710 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 |
|---|
| 14711 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x05ce |
|---|
| 14712 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 |
|---|
| 14713 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x05cf |
|---|
| 14714 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 |
|---|
| 14715 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x05d0 |
|---|
| 14716 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 |
|---|
| 14717 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x05d1 |
|---|
| 14718 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 |
|---|
| 14719 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x05d2 |
|---|
| 14720 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 |
|---|
| 14721 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x05d3 |
|---|
| 14722 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 |
|---|
| 14723 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x05d4 |
|---|
| 14724 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 |
|---|
| 14725 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x05d5 |
|---|
| 14726 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 |
|---|
| 14727 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x05d6 |
|---|
| 14728 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 |
|---|
| 14729 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x05d7 |
|---|
| 14730 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 |
|---|
| 14731 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x05d8 |
|---|
| 14732 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 |
|---|
| 14733 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x05d9 |
|---|
| 14734 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 |
|---|
| 14735 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x05da |
|---|
| 14736 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 |
|---|
| 14737 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x05db |
|---|
| 14738 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 |
|---|
| 14739 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x05dc |
|---|
| 14740 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 |
|---|
| 14741 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x05dd |
|---|
| 14742 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 14743 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x05de |
|---|
| 14744 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 14745 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x05df |
|---|
| 14746 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 14747 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x05e0 |
|---|
| 14748 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 14749 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x05e1 |
|---|
| 14750 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 14751 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x05e2 |
|---|
| 14752 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 14753 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x05e3 |
|---|
| 14754 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 |
|---|
| 14755 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x05e4 |
|---|
| 14756 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 |
|---|
| 14757 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x05e5 |
|---|
| 14758 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 |
|---|
| 14759 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x05e6 |
|---|
| 14760 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 |
|---|
| 14761 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x05e7 |
|---|
| 14762 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 |
|---|
| 14763 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x05e8 |
|---|
| 14764 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 |
|---|
| 14765 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x05e9 |
|---|
| 14766 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 |
|---|
| 14767 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x05ea |
|---|
| 14768 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 |
|---|
| 14769 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x05eb |
|---|
| 14770 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 |
|---|
| 14771 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x05ec |
|---|
| 14772 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 |
|---|
| 14773 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x05ed |
|---|
| 14774 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 |
|---|
| 14775 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x05ee |
|---|
| 14776 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 |
|---|
| 14777 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x05ef |
|---|
| 14778 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 |
|---|
| 14779 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x05f0 |
|---|
| 14780 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 |
|---|
| 14781 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x05f1 |
|---|
| 14782 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 |
|---|
| 14783 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x05f2 |
|---|
| 14784 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 |
|---|
| 14785 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x05f3 |
|---|
| 14786 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 |
|---|
| 14787 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x05f4 |
|---|
| 14788 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 |
|---|
| 14789 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x05f5 |
|---|
| 14790 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 |
|---|
| 14791 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x05f6 |
|---|
| 14792 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 |
|---|
| 14793 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x05f7 |
|---|
| 14794 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 |
|---|
| 14795 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x05f8 |
|---|
| 14796 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 |
|---|
| 14797 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x05f9 |
|---|
| 14798 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 |
|---|
| 14799 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x05fa |
|---|
| 14800 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 |
|---|
| 14801 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x05fb |
|---|
| 14802 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 |
|---|
| 14803 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x05fc |
|---|
| 14804 | #define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 |
|---|
| 14805 | #define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL 0x05fd |
|---|
| 14806 | #define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 |
|---|
| 14807 | |
|---|
| 14808 | |
|---|
| 14809 | // addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec |
|---|
| 14810 | // base address: 0x6c0 |
|---|
| 14811 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL 0x0603 |
|---|
| 14812 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 |
|---|
| 14813 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R 0x0604 |
|---|
| 14814 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 |
|---|
| 14815 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G 0x0605 |
|---|
| 14816 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 |
|---|
| 14817 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B 0x0606 |
|---|
| 14818 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 |
|---|
| 14819 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R 0x0607 |
|---|
| 14820 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 |
|---|
| 14821 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B 0x0608 |
|---|
| 14822 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 |
|---|
| 14823 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX 0x0609 |
|---|
| 14824 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 |
|---|
| 14825 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA 0x060a |
|---|
| 14826 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 |
|---|
| 14827 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x060b |
|---|
| 14828 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 |
|---|
| 14829 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x060c |
|---|
| 14830 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 |
|---|
| 14831 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x060d |
|---|
| 14832 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 |
|---|
| 14833 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x060e |
|---|
| 14834 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 |
|---|
| 14835 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x060f |
|---|
| 14836 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 |
|---|
| 14837 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0610 |
|---|
| 14838 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 |
|---|
| 14839 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0611 |
|---|
| 14840 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 |
|---|
| 14841 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0612 |
|---|
| 14842 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 |
|---|
| 14843 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0613 |
|---|
| 14844 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 |
|---|
| 14845 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0614 |
|---|
| 14846 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 |
|---|
| 14847 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0615 |
|---|
| 14848 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 |
|---|
| 14849 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0616 |
|---|
| 14850 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 |
|---|
| 14851 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0617 |
|---|
| 14852 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 |
|---|
| 14853 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0618 |
|---|
| 14854 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 |
|---|
| 14855 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0619 |
|---|
| 14856 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 |
|---|
| 14857 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x061a |
|---|
| 14858 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 |
|---|
| 14859 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x061b |
|---|
| 14860 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 |
|---|
| 14861 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x061c |
|---|
| 14862 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 |
|---|
| 14863 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x061d |
|---|
| 14864 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 |
|---|
| 14865 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x061e |
|---|
| 14866 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 |
|---|
| 14867 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x061f |
|---|
| 14868 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 |
|---|
| 14869 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0620 |
|---|
| 14870 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 |
|---|
| 14871 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0621 |
|---|
| 14872 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 |
|---|
| 14873 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0622 |
|---|
| 14874 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 |
|---|
| 14875 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0623 |
|---|
| 14876 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 |
|---|
| 14877 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0624 |
|---|
| 14878 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 |
|---|
| 14879 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0625 |
|---|
| 14880 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 |
|---|
| 14881 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0626 |
|---|
| 14882 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 |
|---|
| 14883 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0627 |
|---|
| 14884 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 |
|---|
| 14885 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0628 |
|---|
| 14886 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 |
|---|
| 14887 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0629 |
|---|
| 14888 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 |
|---|
| 14889 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x062a |
|---|
| 14890 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 |
|---|
| 14891 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x062b |
|---|
| 14892 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 |
|---|
| 14893 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x062c |
|---|
| 14894 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 |
|---|
| 14895 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x062d |
|---|
| 14896 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 |
|---|
| 14897 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x062e |
|---|
| 14898 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 |
|---|
| 14899 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x062f |
|---|
| 14900 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 |
|---|
| 14901 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0630 |
|---|
| 14902 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 |
|---|
| 14903 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0631 |
|---|
| 14904 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 |
|---|
| 14905 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0632 |
|---|
| 14906 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 |
|---|
| 14907 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0633 |
|---|
| 14908 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 |
|---|
| 14909 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0634 |
|---|
| 14910 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 |
|---|
| 14911 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0635 |
|---|
| 14912 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 |
|---|
| 14913 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0636 |
|---|
| 14914 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 |
|---|
| 14915 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0637 |
|---|
| 14916 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 |
|---|
| 14917 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0638 |
|---|
| 14918 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 |
|---|
| 14919 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0639 |
|---|
| 14920 | #define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 |
|---|
| 14921 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE 0x063a |
|---|
| 14922 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 |
|---|
| 14923 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX 0x063b |
|---|
| 14924 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 |
|---|
| 14925 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA 0x063c |
|---|
| 14926 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 |
|---|
| 14927 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT 0x063d |
|---|
| 14928 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 |
|---|
| 14929 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x063e |
|---|
| 14930 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 |
|---|
| 14931 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x063f |
|---|
| 14932 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 |
|---|
| 14933 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0640 |
|---|
| 14934 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 |
|---|
| 14935 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0641 |
|---|
| 14936 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 |
|---|
| 14937 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0642 |
|---|
| 14938 | #define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 |
|---|
| 14939 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL 0x0643 |
|---|
| 14940 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 |
|---|
| 14941 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX 0x0644 |
|---|
| 14942 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 |
|---|
| 14943 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA 0x0645 |
|---|
| 14944 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 |
|---|
| 14945 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL 0x0646 |
|---|
| 14946 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 |
|---|
| 14947 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0647 |
|---|
| 14948 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 |
|---|
| 14949 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0648 |
|---|
| 14950 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 |
|---|
| 14951 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0649 |
|---|
| 14952 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 |
|---|
| 14953 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x064a |
|---|
| 14954 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 14955 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x064b |
|---|
| 14956 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 14957 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x064c |
|---|
| 14958 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 14959 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x064d |
|---|
| 14960 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 14961 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x064e |
|---|
| 14962 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 14963 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x064f |
|---|
| 14964 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 14965 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0650 |
|---|
| 14966 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 |
|---|
| 14967 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0651 |
|---|
| 14968 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 |
|---|
| 14969 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0652 |
|---|
| 14970 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 |
|---|
| 14971 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0653 |
|---|
| 14972 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 |
|---|
| 14973 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0654 |
|---|
| 14974 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 |
|---|
| 14975 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0655 |
|---|
| 14976 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 |
|---|
| 14977 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0656 |
|---|
| 14978 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 |
|---|
| 14979 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0657 |
|---|
| 14980 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 |
|---|
| 14981 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0658 |
|---|
| 14982 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 |
|---|
| 14983 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0659 |
|---|
| 14984 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 |
|---|
| 14985 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x065a |
|---|
| 14986 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 |
|---|
| 14987 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x065b |
|---|
| 14988 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 |
|---|
| 14989 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x065c |
|---|
| 14990 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 |
|---|
| 14991 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x065d |
|---|
| 14992 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 |
|---|
| 14993 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x065e |
|---|
| 14994 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 |
|---|
| 14995 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x065f |
|---|
| 14996 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 |
|---|
| 14997 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0660 |
|---|
| 14998 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 |
|---|
| 14999 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0661 |
|---|
| 15000 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 |
|---|
| 15001 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0662 |
|---|
| 15002 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 |
|---|
| 15003 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0663 |
|---|
| 15004 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 |
|---|
| 15005 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0664 |
|---|
| 15006 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 |
|---|
| 15007 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0665 |
|---|
| 15008 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 |
|---|
| 15009 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0666 |
|---|
| 15010 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 |
|---|
| 15011 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0667 |
|---|
| 15012 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 |
|---|
| 15013 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0668 |
|---|
| 15014 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 |
|---|
| 15015 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0669 |
|---|
| 15016 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 |
|---|
| 15017 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x066a |
|---|
| 15018 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 |
|---|
| 15019 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x066b |
|---|
| 15020 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 |
|---|
| 15021 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x066c |
|---|
| 15022 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 |
|---|
| 15023 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x066d |
|---|
| 15024 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 |
|---|
| 15025 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x066e |
|---|
| 15026 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 |
|---|
| 15027 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x066f |
|---|
| 15028 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 |
|---|
| 15029 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0670 |
|---|
| 15030 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 |
|---|
| 15031 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0671 |
|---|
| 15032 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 |
|---|
| 15033 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0672 |
|---|
| 15034 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 |
|---|
| 15035 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0673 |
|---|
| 15036 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 |
|---|
| 15037 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0674 |
|---|
| 15038 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 |
|---|
| 15039 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0675 |
|---|
| 15040 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 |
|---|
| 15041 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0676 |
|---|
| 15042 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 |
|---|
| 15043 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0677 |
|---|
| 15044 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 |
|---|
| 15045 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0678 |
|---|
| 15046 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 |
|---|
| 15047 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0679 |
|---|
| 15048 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 |
|---|
| 15049 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x067a |
|---|
| 15050 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 |
|---|
| 15051 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x067b |
|---|
| 15052 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 |
|---|
| 15053 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x067c |
|---|
| 15054 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 |
|---|
| 15055 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x067d |
|---|
| 15056 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 |
|---|
| 15057 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x067e |
|---|
| 15058 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 |
|---|
| 15059 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x067f |
|---|
| 15060 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 |
|---|
| 15061 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0680 |
|---|
| 15062 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 |
|---|
| 15063 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0681 |
|---|
| 15064 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 |
|---|
| 15065 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0682 |
|---|
| 15066 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 |
|---|
| 15067 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0683 |
|---|
| 15068 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 |
|---|
| 15069 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0684 |
|---|
| 15070 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 |
|---|
| 15071 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0685 |
|---|
| 15072 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 |
|---|
| 15073 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0686 |
|---|
| 15074 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 |
|---|
| 15075 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0687 |
|---|
| 15076 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 |
|---|
| 15077 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0688 |
|---|
| 15078 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 |
|---|
| 15079 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0689 |
|---|
| 15080 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 |
|---|
| 15081 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x068a |
|---|
| 15082 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 |
|---|
| 15083 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x068b |
|---|
| 15084 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 |
|---|
| 15085 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x068c |
|---|
| 15086 | #define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 |
|---|
| 15087 | #define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL 0x068d |
|---|
| 15088 | #define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 |
|---|
| 15089 | |
|---|
| 15090 | |
|---|
| 15091 | // addressBlock: dce_dc_dlpc_dlpc_dispdec |
|---|
| 15092 | // base address: 0x0 |
|---|
| 15093 | #define regDLPC_ENABLE 0x2fe8 |
|---|
| 15094 | #define regDLPC_ENABLE_BASE_IDX 2 |
|---|
| 15095 | #define regDLPC_CURRENT_COUNT 0x2fe9 |
|---|
| 15096 | #define regDLPC_CURRENT_COUNT_BASE_IDX 2 |
|---|
| 15097 | #define regDLPC_OPTC_SNAPSHOT 0x2fea |
|---|
| 15098 | #define regDLPC_OPTC_SNAPSHOT_BASE_IDX 2 |
|---|
| 15099 | #define regDLPC_PWRUP 0x2feb |
|---|
| 15100 | #define regDLPC_PWRUP_BASE_IDX 2 |
|---|
| 15101 | #define regDLPC_OTG_RESYNC 0x2fec |
|---|
| 15102 | #define regDLPC_OTG_RESYNC_BASE_IDX 2 |
|---|
| 15103 | #define regDLPC_DCN_ZSC_LONO_PWRUP 0x2fed |
|---|
| 15104 | #define regDLPC_DCN_ZSC_LONO_PWRUP_BASE_IDX 2 |
|---|
| 15105 | #define regDLPC_SPARE 0x2fee |
|---|
| 15106 | #define regDLPC_SPARE_BASE_IDX 2 |
|---|
| 15107 | #define regDLPC_COUNTER_INIT_VALUE 0x2fef |
|---|
| 15108 | #define regDLPC_COUNTER_INIT_VALUE_BASE_IDX 2 |
|---|
| 15109 | |
|---|
| 15110 | |
|---|
| 15111 | // addressBlock: dce_dpia_dpia_mu0_dpiadec |
|---|
| 15112 | // base address: 0x72000 |
|---|
| 15113 | #define regDPIA_MU_CLOCK_CTRL 0x13800 |
|---|
| 15114 | #define regDPIA_MU_CLOCK_CTRL_BASE_IDX 3 |
|---|
| 15115 | #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0 0x13801 |
|---|
| 15116 | #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0_BASE_IDX 3 |
|---|
| 15117 | #define regDPIA_MU_RESET_CTRL_DPIA_PORT0 0x13802 |
|---|
| 15118 | #define regDPIA_MU_RESET_CTRL_DPIA_PORT0_BASE_IDX 3 |
|---|
| 15119 | #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1 0x13803 |
|---|
| 15120 | #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1_BASE_IDX 3 |
|---|
| 15121 | #define regDPIA_MU_RESET_CTRL_DPIA_PORT1 0x13804 |
|---|
| 15122 | #define regDPIA_MU_RESET_CTRL_DPIA_PORT1_BASE_IDX 3 |
|---|
| 15123 | #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2 0x13805 |
|---|
| 15124 | #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2_BASE_IDX 3 |
|---|
| 15125 | #define regDPIA_MU_RESET_CTRL_DPIA_PORT2 0x13806 |
|---|
| 15126 | #define regDPIA_MU_RESET_CTRL_DPIA_PORT2_BASE_IDX 3 |
|---|
| 15127 | #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3 0x13807 |
|---|
| 15128 | #define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3_BASE_IDX 3 |
|---|
| 15129 | #define regDPIA_MU_RESET_CTRL_DPIA_PORT3 0x13808 |
|---|
| 15130 | #define regDPIA_MU_RESET_CTRL_DPIA_PORT3_BASE_IDX 3 |
|---|
| 15131 | #define regDPIA_MU_TPI_STATUS_DPIA_PORT0 0x13811 |
|---|
| 15132 | #define regDPIA_MU_TPI_STATUS_DPIA_PORT0_BASE_IDX 3 |
|---|
| 15133 | #define regDPIA_MU_TPI_STATUS_DPIA_PORT1 0x13812 |
|---|
| 15134 | #define regDPIA_MU_TPI_STATUS_DPIA_PORT1_BASE_IDX 3 |
|---|
| 15135 | #define regDPIA_MU_TPI_STATUS_DPIA_PORT2 0x13813 |
|---|
| 15136 | #define regDPIA_MU_TPI_STATUS_DPIA_PORT2_BASE_IDX 3 |
|---|
| 15137 | #define regDPIA_MU_TPI_STATUS_DPIA_PORT3 0x13814 |
|---|
| 15138 | #define regDPIA_MU_TPI_STATUS_DPIA_PORT3_BASE_IDX 3 |
|---|
| 15139 | #define regDPIA_MU_TPI_MAX_CREDIT_COUNT 0x13819 |
|---|
| 15140 | #define regDPIA_MU_TPI_MAX_CREDIT_COUNT_BASE_IDX 3 |
|---|
| 15141 | #define regDPIA_MU_INTERRUPT_STATUS 0x1381a |
|---|
| 15142 | #define regDPIA_MU_INTERRUPT_STATUS_BASE_IDX 3 |
|---|
| 15143 | #define regDPIA_MU_INTERRUPT_CTRL 0x1381b |
|---|
| 15144 | #define regDPIA_MU_INTERRUPT_CTRL_BASE_IDX 3 |
|---|
| 15145 | #define regDPIA_MU_LOCAL_INTERRUPT_CTRL 0x1381c |
|---|
| 15146 | #define regDPIA_MU_LOCAL_INTERRUPT_CTRL_BASE_IDX 3 |
|---|
| 15147 | #define regDPIA_MU_LOCAL_INTERRUPT_ACK 0x1381d |
|---|
| 15148 | #define regDPIA_MU_LOCAL_INTERRUPT_ACK_BASE_IDX 3 |
|---|
| 15149 | #define regDPIA_MU_RBBMIF_TIMEOUT_CTRL 0x1381e |
|---|
| 15150 | #define regDPIA_MU_RBBMIF_TIMEOUT_CTRL_BASE_IDX 3 |
|---|
| 15151 | #define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2 0x1381f |
|---|
| 15152 | #define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2_BASE_IDX 3 |
|---|
| 15153 | #define regDPIA_MU_RBBMIF_STATUS 0x13820 |
|---|
| 15154 | #define regDPIA_MU_RBBMIF_STATUS_BASE_IDX 3 |
|---|
| 15155 | #define regDPIA_MU_MICROSECOND_REF_CTRL 0x13821 |
|---|
| 15156 | #define regDPIA_MU_MICROSECOND_REF_CTRL_BASE_IDX 3 |
|---|
| 15157 | #define regDPIA_MU_PORT_ADP_STATUS 0x13822 |
|---|
| 15158 | #define regDPIA_MU_PORT_ADP_STATUS_BASE_IDX 3 |
|---|
| 15159 | #define regDPIA_GLUE_CTRL 0x13823 |
|---|
| 15160 | #define regDPIA_GLUE_CTRL_BASE_IDX 3 |
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| 15161 | #define regDPIA_PERF_COUNT_CONTROL0 0x13825 |
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| 15162 | #define regDPIA_PERF_COUNT_CONTROL0_BASE_IDX 3 |
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| 15163 | #define regDPIA_PERF_COUNT_CONTROL1 0x13826 |
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| 15164 | #define regDPIA_PERF_COUNT_CONTROL1_BASE_IDX 3 |
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| 15165 | #define regDPIA_PERF_COUNT_CONTROL2 0x13827 |
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| 15166 | #define regDPIA_PERF_COUNT_CONTROL2_BASE_IDX 3 |
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| 15167 | #define regDPIA_PERF_COUNT_CONTROL3 0x13828 |
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| 15168 | #define regDPIA_PERF_COUNT_CONTROL3_BASE_IDX 3 |
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| 15169 | #define regDPIA_PERF_COUNT_CONTROL4 0x13829 |
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| 15170 | #define regDPIA_PERF_COUNT_CONTROL4_BASE_IDX 3 |
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| 15171 | #define regDPIA_PERF_COUNT_CONTROL5 0x1382a |
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| 15172 | #define regDPIA_PERF_COUNT_CONTROL5_BASE_IDX 3 |
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| 15173 | #define regDPIA_PERF_COUNT_INDEX 0x1382b |
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| 15174 | #define regDPIA_PERF_COUNT_INDEX_BASE_IDX 3 |
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| 15175 | #define regDPIA_PERF_COUNT_DATA_LO 0x1382c |
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| 15176 | #define regDPIA_PERF_COUNT_DATA_LO_BASE_IDX 3 |
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| 15177 | #define regDPIA_MU_SPARE 0x1382d |
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| 15178 | #define regDPIA_MU_SPARE_BASE_IDX 3 |
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| 15179 | |
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| 15180 | |
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| 15181 | // addressBlock: dce_dc_hda_azcontroller_azdec |
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| 15182 | // base address: 0x0 |
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| 15183 | #define regAZCONTROLLER1_CORB_WRITE_POINTER 0x0000 |
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| 15184 | #define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX 0 |
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| 15185 | #define regAZCONTROLLER1_CORB_READ_POINTER 0x0000 |
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| 15186 | #define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX 0 |
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| 15187 | #define regAZCONTROLLER1_CORB_CONTROL 0x0001 |
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| 15188 | #define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX 0 |
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| 15189 | #define regAZCONTROLLER1_CORB_STATUS 0x0001 |
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| 15190 | #define regAZCONTROLLER1_CORB_STATUS_BASE_IDX 0 |
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| 15191 | #define regAZCONTROLLER1_CORB_SIZE 0x0001 |
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| 15192 | #define regAZCONTROLLER1_CORB_SIZE_BASE_IDX 0 |
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| 15193 | #define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS 0x0002 |
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| 15194 | #define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 |
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| 15195 | #define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS 0x0003 |
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| 15196 | #define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 |
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| 15197 | #define regAZCONTROLLER1_RIRB_WRITE_POINTER 0x0004 |
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| 15198 | #define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX 0 |
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| 15199 | #define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT 0x0004 |
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| 15200 | #define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0 |
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| 15201 | #define regAZCONTROLLER1_RIRB_CONTROL 0x0005 |
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| 15202 | #define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX 0 |
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| 15203 | #define regAZCONTROLLER1_RIRB_STATUS 0x0005 |
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| 15204 | #define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX 0 |
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| 15205 | #define regAZCONTROLLER1_RIRB_SIZE 0x0005 |
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| 15206 | #define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX 0 |
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| 15207 | #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 |
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| 15208 | #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 |
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| 15209 | #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 |
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| 15210 | #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 |
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| 15211 | #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 |
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| 15212 | #define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 |
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| 15213 | #define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 |
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| 15214 | #define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 |
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| 15215 | #define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS 0x0008 |
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| 15216 | #define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0 |
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| 15217 | #define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a |
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| 15218 | #define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 |
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| 15219 | #define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b |
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| 15220 | #define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 |
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| 15221 | #define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS 0x074c |
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| 15222 | #define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 |
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| 15223 | |
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| 15224 | |
|---|
| 15225 | // addressBlock: dce_dc_hda_azendpoint_azdec |
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| 15226 | // base address: 0x0 |
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| 15227 | #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 |
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| 15228 | #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 |
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| 15229 | #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 |
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| 15230 | #define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 |
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| 15231 | |
|---|
| 15232 | |
|---|
| 15233 | // addressBlock: dce_dc_hda_azinputendpoint_azdec |
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| 15234 | // base address: 0x0 |
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| 15235 | #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 |
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| 15236 | #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 |
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| 15237 | #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 |
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| 15238 | #define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 |
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| 15239 | |
|---|
| 15240 | |
|---|
| 15241 | // addressBlock: dce_dc_dio_dio_dpia_mux0_dispdec |
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| 15242 | // base address: 0x14de0 |
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| 15243 | #define regDIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL 0x1eb8 |
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| 15244 | #define regDIO_DPIA_MUX0_DIO_DPIA_MUX_CONTROL_BASE_IDX 2 |
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| 15245 | |
|---|
| 15246 | |
|---|
| 15247 | // addressBlock: dce_dc_dio_dio_dpia_mux1_dispdec |
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| 15248 | // base address: 0x14de4 |
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| 15249 | #define regDIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL 0x1eb9 |
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| 15250 | #define regDIO_DPIA_MUX1_DIO_DPIA_MUX_CONTROL_BASE_IDX 2 |
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| 15251 | |
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| 15252 | |
|---|
| 15253 | // addressBlock: dce_dc_dio_dio_dpia_mux2_dispdec |
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| 15254 | // base address: 0x14de8 |
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| 15255 | #define regDIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL 0x1eba |
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| 15256 | #define regDIO_DPIA_MUX2_DIO_DPIA_MUX_CONTROL_BASE_IDX 2 |
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| 15257 | |
|---|
| 15258 | |
|---|
| 15259 | // addressBlock: dce_dc_dio_dio_dpia_mux3_dispdec |
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| 15260 | // base address: 0x14dec |
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| 15261 | #define regDIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL 0x1ebb |
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| 15262 | #define regDIO_DPIA_MUX3_DIO_DPIA_MUX_CONTROL_BASE_IDX 2 |
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| 15263 | |
|---|
| 15264 | |
|---|
| 15265 | // addressBlock: dce_dc_dio_dig_stream_mapper_dispdec |
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| 15266 | // base address: 0x0 |
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| 15267 | #define regDIG0_STREAM_MAPPER_CONTROL 0x1f0d |
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| 15268 | #define regDIG0_STREAM_MAPPER_CONTROL_BASE_IDX 2 |
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| 15269 | #define regDIG1_STREAM_MAPPER_CONTROL 0x1f0e |
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| 15270 | #define regDIG1_STREAM_MAPPER_CONTROL_BASE_IDX 2 |
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| 15271 | #define regDIG2_STREAM_MAPPER_CONTROL 0x1f0f |
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| 15272 | #define regDIG2_STREAM_MAPPER_CONTROL_BASE_IDX 2 |
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| 15273 | #define regDIG3_STREAM_MAPPER_CONTROL 0x1f10 |
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| 15274 | #define regDIG3_STREAM_MAPPER_CONTROL_BASE_IDX 2 |
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| 15275 | #define regDIG4_STREAM_MAPPER_CONTROL 0x1f11 |
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| 15276 | #define regDIG4_STREAM_MAPPER_CONTROL_BASE_IDX 2 |
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| 15277 | |
|---|
| 15278 | |
|---|
| 15279 | #endif |
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| 15280 | |
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