1 | /* |
2 | * Copyright (C) 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | */ |
21 | #ifndef _gc_10_1_0_SH_MASK_HEADER |
22 | #define |
23 | |
24 | |
25 | // addressBlock: gc_sdma0_sdma0dec |
26 | //SDMA0_DEC_START |
27 | #define SDMA0_DEC_START__START__SHIFT 0x0 |
28 | #define SDMA0_DEC_START__START_MASK 0xFFFFFFFFL |
29 | //SDMA0_PG_CNTL |
30 | #define SDMA0_PG_CNTL__CMD__SHIFT 0x0 |
31 | #define SDMA0_PG_CNTL__STATUS__SHIFT 0x10 |
32 | #define SDMA0_PG_CNTL__CMD_MASK 0x0000000FL |
33 | #define SDMA0_PG_CNTL__STATUS_MASK 0x000F0000L |
34 | //SDMA0_PG_CTX_LO |
35 | #define SDMA0_PG_CTX_LO__ADDR__SHIFT 0x0 |
36 | #define SDMA0_PG_CTX_LO__ADDR_MASK 0xFFFFFFFFL |
37 | //SDMA0_PG_CTX_HI |
38 | #define SDMA0_PG_CTX_HI__ADDR__SHIFT 0x0 |
39 | #define SDMA0_PG_CTX_HI__ADDR_MASK 0xFFFFFFFFL |
40 | //SDMA0_PG_CTX_CNTL |
41 | #define SDMA0_PG_CTX_CNTL__VMID__SHIFT 0x0 |
42 | #define SDMA0_PG_CTX_CNTL__VMID_MASK 0x0000000FL |
43 | //SDMA0_POWER_CNTL |
44 | #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 |
45 | #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 |
46 | #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 |
47 | #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 |
48 | #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 |
49 | #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 |
50 | #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa |
51 | #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb |
52 | #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc |
53 | #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a |
54 | #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L |
55 | #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L |
56 | #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L |
57 | #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L |
58 | #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L |
59 | #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L |
60 | #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L |
61 | #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L |
62 | #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L |
63 | #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L |
64 | //SDMA0_CLK_CTRL |
65 | #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
66 | #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
67 | #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc |
68 | #define SDMA0_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT 0x17 |
69 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
70 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
71 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
72 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
73 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
74 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
75 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
76 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
77 | #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
78 | #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
79 | #define SDMA0_CLK_CTRL__RESERVED_MASK 0x007FF000L |
80 | #define SDMA0_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK 0x00800000L |
81 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
82 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
83 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
84 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
85 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
86 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
87 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
88 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
89 | //SDMA0_CNTL |
90 | #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 |
91 | #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 |
92 | #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 |
93 | #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 |
94 | #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 |
95 | #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 |
96 | #define SDMA0_CNTL__PAGE_INT_ENABLE__SHIFT 0x7 |
97 | #define SDMA0_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10 |
98 | #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 |
99 | #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 |
100 | #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c |
101 | #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d |
102 | #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e |
103 | #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L |
104 | #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L |
105 | #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L |
106 | #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L |
107 | #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L |
108 | #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L |
109 | #define SDMA0_CNTL__PAGE_INT_ENABLE_MASK 0x00000080L |
110 | #define SDMA0_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L |
111 | #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L |
112 | #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L |
113 | #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L |
114 | #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L |
115 | #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L |
116 | //SDMA0_CHICKEN_BITS |
117 | #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 |
118 | #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 |
119 | #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 |
120 | #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 |
121 | #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa |
122 | #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 |
123 | #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 |
124 | #define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 |
125 | #define SDMA0_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT 0x13 |
126 | #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 |
127 | #define SDMA0_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT 0x15 |
128 | #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 |
129 | #define SDMA0_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT 0x18 |
130 | #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 |
131 | #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a |
132 | #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c |
133 | #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e |
134 | #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L |
135 | #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L |
136 | #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L |
137 | #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L |
138 | #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L |
139 | #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L |
140 | #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L |
141 | #define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L |
142 | #define SDMA0_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK 0x00080000L |
143 | #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L |
144 | #define SDMA0_CHICKEN_BITS__CH_FGCG_ENABLE_MASK 0x00200000L |
145 | #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L |
146 | #define SDMA0_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK 0x01000000L |
147 | #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L |
148 | #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L |
149 | #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L |
150 | #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L |
151 | //SDMA0_GB_ADDR_CONFIG |
152 | #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
153 | #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
154 | #define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
155 | #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 |
156 | #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc |
157 | #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
158 | #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
159 | #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
160 | #define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
161 | #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L |
162 | #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L |
163 | #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
164 | //SDMA0_GB_ADDR_CONFIG_READ |
165 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 |
166 | #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
167 | #define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
168 | #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 |
169 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc |
170 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 |
171 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L |
172 | #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
173 | #define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
174 | #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L |
175 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L |
176 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L |
177 | //SDMA0_RB_RPTR_FETCH_HI |
178 | #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 |
179 | #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL |
180 | //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL |
181 | #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 |
182 | #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL |
183 | //SDMA0_RB_RPTR_FETCH |
184 | #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 |
185 | #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL |
186 | //SDMA0_IB_OFFSET_FETCH |
187 | #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 |
188 | #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL |
189 | //SDMA0_PROGRAM |
190 | #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 |
191 | #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL |
192 | //SDMA0_STATUS_REG |
193 | #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 |
194 | #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 |
195 | #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 |
196 | #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 |
197 | #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 |
198 | #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 |
199 | #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 |
200 | #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 |
201 | #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 |
202 | #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 |
203 | #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa |
204 | #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb |
205 | #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc |
206 | #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd |
207 | #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe |
208 | #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf |
209 | #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 |
210 | #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 |
211 | #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 |
212 | #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 |
213 | #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 |
214 | #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 |
215 | #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 |
216 | #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 |
217 | #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a |
218 | #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b |
219 | #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c |
220 | #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e |
221 | #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f |
222 | #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L |
223 | #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L |
224 | #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L |
225 | #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L |
226 | #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L |
227 | #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L |
228 | #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L |
229 | #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L |
230 | #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L |
231 | #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L |
232 | #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L |
233 | #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L |
234 | #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L |
235 | #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L |
236 | #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L |
237 | #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L |
238 | #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L |
239 | #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L |
240 | #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L |
241 | #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L |
242 | #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L |
243 | #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L |
244 | #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L |
245 | #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L |
246 | #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L |
247 | #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L |
248 | #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L |
249 | #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L |
250 | #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L |
251 | //SDMA0_STATUS1_REG |
252 | #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 |
253 | #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 |
254 | #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 |
255 | #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 |
256 | #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 |
257 | #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 |
258 | #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 |
259 | #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 |
260 | #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa |
261 | #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd |
262 | #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe |
263 | #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf |
264 | #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 |
265 | #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 |
266 | #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L |
267 | #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L |
268 | #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L |
269 | #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L |
270 | #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L |
271 | #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L |
272 | #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L |
273 | #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L |
274 | #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L |
275 | #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L |
276 | #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L |
277 | #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L |
278 | #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L |
279 | #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L |
280 | //SDMA0_RD_BURST_CNTL |
281 | #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 |
282 | #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L |
283 | //SDMA0_HBM_PAGE_CONFIG |
284 | #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 |
285 | #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L |
286 | //SDMA0_UCODE_CHECKSUM |
287 | #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 |
288 | #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL |
289 | //SDMA0_F32_CNTL |
290 | #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 |
291 | #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 |
292 | #define SDMA0_F32_CNTL__CHECKSUM_CLR__SHIFT 0x8 |
293 | #define SDMA0_F32_CNTL__RESET__SHIFT 0x9 |
294 | #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L |
295 | #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L |
296 | #define SDMA0_F32_CNTL__CHECKSUM_CLR_MASK 0x00000100L |
297 | #define SDMA0_F32_CNTL__RESET_MASK 0x00000200L |
298 | //SDMA0_FREEZE |
299 | #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 |
300 | #define SDMA0_FREEZE__FORCE_PREEMPT__SHIFT 0x1 |
301 | #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 |
302 | #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 |
303 | #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 |
304 | #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L |
305 | #define SDMA0_FREEZE__FORCE_PREEMPT_MASK 0x00000002L |
306 | #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L |
307 | #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L |
308 | #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L |
309 | //SDMA0_PHASE0_QUANTUM |
310 | #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 |
311 | #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 |
312 | #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e |
313 | #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL |
314 | #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L |
315 | #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L |
316 | //SDMA0_PHASE1_QUANTUM |
317 | #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 |
318 | #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 |
319 | #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e |
320 | #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL |
321 | #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L |
322 | #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L |
323 | //SDMA_POWER_GATING |
324 | #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 |
325 | #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 |
326 | #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 |
327 | #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 |
328 | #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 |
329 | #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L |
330 | #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L |
331 | #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L |
332 | #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L |
333 | #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L |
334 | //SDMA_PGFSM_CONFIG |
335 | #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 |
336 | #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 |
337 | #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 |
338 | #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa |
339 | #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb |
340 | #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc |
341 | #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd |
342 | #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b |
343 | #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c |
344 | #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL |
345 | #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L |
346 | #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L |
347 | #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L |
348 | #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L |
349 | #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L |
350 | #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L |
351 | #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L |
352 | #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L |
353 | //SDMA_PGFSM_WRITE |
354 | #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 |
355 | #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL |
356 | //SDMA_PGFSM_READ |
357 | #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 |
358 | #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL |
359 | //SDMA0_EDC_CONFIG |
360 | #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 |
361 | #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 |
362 | #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L |
363 | #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L |
364 | //SDMA0_BA_THRESHOLD |
365 | #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 |
366 | #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 |
367 | #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL |
368 | #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L |
369 | //SDMA0_ID |
370 | #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 |
371 | #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL |
372 | //SDMA0_VERSION |
373 | #define SDMA0_VERSION__MINVER__SHIFT 0x0 |
374 | #define SDMA0_VERSION__MAJVER__SHIFT 0x8 |
375 | #define SDMA0_VERSION__REV__SHIFT 0x10 |
376 | #define SDMA0_VERSION__MINVER_MASK 0x0000007FL |
377 | #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L |
378 | #define SDMA0_VERSION__REV_MASK 0x003F0000L |
379 | //SDMA0_EDC_COUNTER |
380 | #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 |
381 | #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 |
382 | #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 |
383 | #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 |
384 | #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 |
385 | #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 |
386 | #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 |
387 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 |
388 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 |
389 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 |
390 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa |
391 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb |
392 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc |
393 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd |
394 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe |
395 | #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf |
396 | #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 |
397 | #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L |
398 | #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L |
399 | #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L |
400 | #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L |
401 | #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L |
402 | #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L |
403 | #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L |
404 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L |
405 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L |
406 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L |
407 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L |
408 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L |
409 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L |
410 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L |
411 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L |
412 | #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L |
413 | #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L |
414 | //SDMA0_EDC_COUNTER_CLEAR |
415 | #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 |
416 | #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L |
417 | //SDMA0_STATUS2_REG |
418 | #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 |
419 | #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 |
420 | #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 |
421 | #define SDMA0_STATUS2_REG__ID_MASK 0x00000003L |
422 | #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL |
423 | #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L |
424 | //SDMA0_ATOMIC_CNTL |
425 | #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 |
426 | #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f |
427 | #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL |
428 | #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L |
429 | //SDMA0_ATOMIC_PREOP_LO |
430 | #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 |
431 | #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL |
432 | //SDMA0_ATOMIC_PREOP_HI |
433 | #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 |
434 | #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL |
435 | //SDMA0_UTCL1_CNTL |
436 | #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 |
437 | #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 |
438 | #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0x6 |
439 | #define SDMA0_UTCL1_CNTL__RESP_MODE__SHIFT 0x9 |
440 | #define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe |
441 | #define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xf |
442 | #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x10 |
443 | #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 |
444 | #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d |
445 | #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L |
446 | #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x0000003EL |
447 | #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x000001C0L |
448 | #define SDMA0_UTCL1_CNTL__RESP_MODE_MASK 0x00000E00L |
449 | #define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00004000L |
450 | #define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00008000L |
451 | #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FF0000L |
452 | #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L |
453 | #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L |
454 | //SDMA0_UTCL1_WATERMK |
455 | #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 |
456 | #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa |
457 | #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 |
458 | #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a |
459 | #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL |
460 | #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L |
461 | #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L |
462 | #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L |
463 | //SDMA0_UTCL1_RD_STATUS |
464 | #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 |
465 | #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1 |
466 | #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2 |
467 | #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3 |
468 | #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4 |
469 | #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5 |
470 | #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6 |
471 | #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7 |
472 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8 |
473 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9 |
474 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa |
475 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb |
476 | #define SDMA0_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT 0xc |
477 | #define SDMA0_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT 0xd |
478 | #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0xe |
479 | #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0xf |
480 | #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x10 |
481 | #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x11 |
482 | #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x15 |
483 | #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x18 |
484 | #define SDMA0_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT 0x19 |
485 | #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT 0x1a |
486 | #define SDMA0_UTCL1_RD_STATUS__HIT_CACHE__SHIFT 0x1b |
487 | #define SDMA0_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT 0x1c |
488 | #define SDMA0_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT 0x1d |
489 | #define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT 0x1e |
490 | #define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT 0x1f |
491 | #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L |
492 | #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L |
493 | #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L |
494 | #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L |
495 | #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L |
496 | #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L |
497 | #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L |
498 | #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L |
499 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L |
500 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L |
501 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L |
502 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L |
503 | #define SDMA0_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L |
504 | #define SDMA0_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK 0x00002000L |
505 | #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00004000L |
506 | #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00008000L |
507 | #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00010000L |
508 | #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x001E0000L |
509 | #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x00E00000L |
510 | #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x01000000L |
511 | #define SDMA0_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK 0x02000000L |
512 | #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK 0x04000000L |
513 | #define SDMA0_UTCL1_RD_STATUS__HIT_CACHE_MASK 0x08000000L |
514 | #define SDMA0_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK 0x10000000L |
515 | #define SDMA0_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK 0x20000000L |
516 | #define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK 0x40000000L |
517 | #define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK 0x80000000L |
518 | //SDMA0_UTCL1_WR_STATUS |
519 | #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 |
520 | #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1 |
521 | #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2 |
522 | #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3 |
523 | #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4 |
524 | #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5 |
525 | #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6 |
526 | #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7 |
527 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8 |
528 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9 |
529 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa |
530 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb |
531 | #define SDMA0_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT 0xc |
532 | #define SDMA0_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT 0xd |
533 | #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0xe |
534 | #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0xf |
535 | #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x10 |
536 | #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x11 |
537 | #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x15 |
538 | #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x18 |
539 | #define SDMA0_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT 0x19 |
540 | #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT 0x1a |
541 | #define SDMA0_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT 0x1b |
542 | #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c |
543 | #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d |
544 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e |
545 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f |
546 | #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L |
547 | #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L |
548 | #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L |
549 | #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L |
550 | #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L |
551 | #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L |
552 | #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L |
553 | #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L |
554 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L |
555 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L |
556 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L |
557 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L |
558 | #define SDMA0_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L |
559 | #define SDMA0_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK 0x00002000L |
560 | #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00004000L |
561 | #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00008000L |
562 | #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00010000L |
563 | #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x001E0000L |
564 | #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x00E00000L |
565 | #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x01000000L |
566 | #define SDMA0_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK 0x02000000L |
567 | #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK 0x04000000L |
568 | #define SDMA0_UTCL1_WR_STATUS__ATOMIC_OP_MASK 0x08000000L |
569 | #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L |
570 | #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L |
571 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L |
572 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L |
573 | //SDMA0_UTCL1_INV0 |
574 | #define SDMA0_UTCL1_INV0__CPF_INVREQ_EN__SHIFT 0x0 |
575 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT 0x1 |
576 | #define SDMA0_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT 0x2 |
577 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT 0x3 |
578 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT 0x4 |
579 | #define SDMA0_UTCL1_INV0__INVREQ_SIZE__SHIFT 0x5 |
580 | #define SDMA0_UTCL1_INV0__INVREQ_IDLE__SHIFT 0xb |
581 | #define SDMA0_UTCL1_INV0__VMINV_PEND_CNT__SHIFT 0xc |
582 | #define SDMA0_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT 0x10 |
583 | #define SDMA0_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT 0x14 |
584 | #define SDMA0_UTCL1_INV0__GPUVM_INV_MODE__SHIFT 0x18 |
585 | #define SDMA0_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT 0x1a |
586 | #define SDMA0_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT 0x1b |
587 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT 0x1c |
588 | #define SDMA0_UTCL1_INV0__CPF_INVREQ_EN_MASK 0x00000001L |
589 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_EN_MASK 0x00000002L |
590 | #define SDMA0_UTCL1_INV0__CPF_GPA_INVREQ_MASK 0x00000004L |
591 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK 0x00000008L |
592 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK 0x00000010L |
593 | #define SDMA0_UTCL1_INV0__INVREQ_SIZE_MASK 0x000007E0L |
594 | #define SDMA0_UTCL1_INV0__INVREQ_IDLE_MASK 0x00000800L |
595 | #define SDMA0_UTCL1_INV0__VMINV_PEND_CNT_MASK 0x0000F000L |
596 | #define SDMA0_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK 0x000F0000L |
597 | #define SDMA0_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK 0x00F00000L |
598 | #define SDMA0_UTCL1_INV0__GPUVM_INV_MODE_MASK 0x03000000L |
599 | #define SDMA0_UTCL1_INV0__INVREQ_IS_HEAVY_MASK 0x04000000L |
600 | #define SDMA0_UTCL1_INV0__INVREQ_FROM_CPF_MASK 0x08000000L |
601 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK 0xF0000000L |
602 | //SDMA0_UTCL1_INV1 |
603 | #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 |
604 | #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL |
605 | //SDMA0_UTCL1_INV2 |
606 | #define SDMA0_UTCL1_INV2__INV_VMID_VEC__SHIFT 0x0 |
607 | #define SDMA0_UTCL1_INV2__RESERVED__SHIFT 0x10 |
608 | #define SDMA0_UTCL1_INV2__INV_VMID_VEC_MASK 0x0000FFFFL |
609 | #define SDMA0_UTCL1_INV2__RESERVED_MASK 0xFFFF0000L |
610 | //SDMA0_UTCL1_RD_XNACK0 |
611 | #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 |
612 | #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL |
613 | //SDMA0_UTCL1_RD_XNACK1 |
614 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 |
615 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 |
616 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 |
617 | #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a |
618 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL |
619 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L |
620 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L |
621 | #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L |
622 | //SDMA0_UTCL1_WR_XNACK0 |
623 | #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 |
624 | #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL |
625 | //SDMA0_UTCL1_WR_XNACK1 |
626 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 |
627 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 |
628 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 |
629 | #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a |
630 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL |
631 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L |
632 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L |
633 | #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L |
634 | //SDMA0_UTCL1_TIMEOUT |
635 | #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 |
636 | #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 |
637 | #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL |
638 | #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L |
639 | //SDMA0_UTCL1_PAGE |
640 | #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 |
641 | #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 |
642 | #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 |
643 | #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa |
644 | #define SDMA0_UTCL1_PAGE__USE_IO__SHIFT 0xb |
645 | #define SDMA0_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc |
646 | #define SDMA0_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe |
647 | #define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT 0x10 |
648 | #define SDMA0_UTCL1_PAGE__USE_BC__SHIFT 0x16 |
649 | #define SDMA0_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17 |
650 | #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L |
651 | #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL |
652 | #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000003C0L |
653 | #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L |
654 | #define SDMA0_UTCL1_PAGE__USE_IO_MASK 0x00000800L |
655 | #define SDMA0_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L |
656 | #define SDMA0_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L |
657 | #define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE_MASK 0x003F0000L |
658 | #define SDMA0_UTCL1_PAGE__USE_BC_MASK 0x00400000L |
659 | #define SDMA0_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L |
660 | //SDMA0_POWER_CNTL_IDLE |
661 | #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 |
662 | #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 |
663 | #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 |
664 | #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL |
665 | #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L |
666 | #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L |
667 | //SDMA0_RELAX_ORDERING_LUT |
668 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 |
669 | #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 |
670 | #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 |
671 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 |
672 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 |
673 | #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 |
674 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 |
675 | #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 |
676 | #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 |
677 | #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa |
678 | #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb |
679 | #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc |
680 | #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd |
681 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe |
682 | #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b |
683 | #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c |
684 | #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d |
685 | #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e |
686 | #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f |
687 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L |
688 | #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L |
689 | #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L |
690 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L |
691 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L |
692 | #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L |
693 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L |
694 | #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L |
695 | #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L |
696 | #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L |
697 | #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L |
698 | #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L |
699 | #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L |
700 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L |
701 | #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L |
702 | #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L |
703 | #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L |
704 | #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L |
705 | #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L |
706 | //SDMA0_CHICKEN_BITS_2 |
707 | #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 |
708 | #define SDMA0_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT 0x4 |
709 | #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL |
710 | #define SDMA0_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK 0x00000010L |
711 | //SDMA0_STATUS3_REG |
712 | #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 |
713 | #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 |
714 | #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 |
715 | #define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15 |
716 | #define SDMA0_STATUS3_REG__TLBI_IDLE__SHIFT 0x16 |
717 | #define SDMA0_STATUS3_REG__GCR_IDLE__SHIFT 0x17 |
718 | #define SDMA0_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18 |
719 | #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19 |
720 | #define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a |
721 | #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL |
722 | #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L |
723 | #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L |
724 | #define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L |
725 | #define SDMA0_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L |
726 | #define SDMA0_STATUS3_REG__GCR_IDLE_MASK 0x00800000L |
727 | #define SDMA0_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L |
728 | #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L |
729 | #define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L |
730 | //SDMA0_PHYSICAL_ADDR_LO |
731 | #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 |
732 | #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 |
733 | #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 |
734 | #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc |
735 | #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L |
736 | #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L |
737 | #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L |
738 | #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L |
739 | //SDMA0_PHYSICAL_ADDR_HI |
740 | #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 |
741 | #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL |
742 | //SDMA0_PHASE2_QUANTUM |
743 | #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 |
744 | #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 |
745 | #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e |
746 | #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL |
747 | #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L |
748 | #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L |
749 | //SDMA0_F32_COUNTER |
750 | #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 |
751 | #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL |
752 | //SDMA0_PERFMON_CNTL |
753 | #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 |
754 | #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 |
755 | #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 |
756 | #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa |
757 | #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb |
758 | #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc |
759 | #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L |
760 | #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L |
761 | #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL |
762 | #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L |
763 | #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L |
764 | #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L |
765 | //SDMA0_PERFCOUNTER0_RESULT |
766 | #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 |
767 | #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL |
768 | //SDMA0_PERFCOUNTER1_RESULT |
769 | #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 |
770 | #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL |
771 | //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE |
772 | #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 |
773 | #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe |
774 | #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c |
775 | #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL |
776 | #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L |
777 | #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L |
778 | //SDMA0_CRD_CNTL |
779 | #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 |
780 | #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd |
781 | #define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13 |
782 | #define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19 |
783 | #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L |
784 | #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L |
785 | #define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L |
786 | #define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L |
787 | //SDMA0_GPU_IOV_VIOLATION_LOG |
788 | //SDMA0_AQL_STATUS |
789 | #define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0 |
790 | #define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1 |
791 | #define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L |
792 | #define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L |
793 | //SDMA0_EA_DBIT_ADDR_DATA |
794 | #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 |
795 | #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL |
796 | //SDMA0_EA_DBIT_ADDR_INDEX |
797 | #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 |
798 | #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L |
799 | //SDMA0_TLBI_GCR_CNTL |
800 | #define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0 |
801 | #define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4 |
802 | #define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT 0x8 |
803 | #define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10 |
804 | #define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18 |
805 | #define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL |
806 | #define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L |
807 | #define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK 0x00000F00L |
808 | #define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L |
809 | #define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L |
810 | //SDMA0_TILING_CONFIG |
811 | #define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
812 | #define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L |
813 | //SDMA0_HASH |
814 | #define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0 |
815 | #define SDMA0_HASH__BANK_BITS__SHIFT 0x4 |
816 | #define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 |
817 | #define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc |
818 | #define SDMA0_HASH__CHANNEL_BITS_MASK 0x00000007L |
819 | #define SDMA0_HASH__BANK_BITS_MASK 0x00000070L |
820 | #define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x00000700L |
821 | #define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x00007000L |
822 | //SDMA0_PERFCOUNTER0_SELECT |
823 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
824 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
825 | #define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
826 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
827 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
828 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
829 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
830 | #define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
831 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
832 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
833 | //SDMA0_PERFCOUNTER0_SELECT1 |
834 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
835 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
836 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
837 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
838 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
839 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
840 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
841 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
842 | //SDMA0_PERFCOUNTER0_LO |
843 | #define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
844 | #define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
845 | //SDMA0_PERFCOUNTER0_HI |
846 | #define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
847 | #define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
848 | //SDMA0_PERFCOUNTER1_SELECT |
849 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
850 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
851 | #define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
852 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
853 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
854 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
855 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
856 | #define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
857 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
858 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
859 | //SDMA0_PERFCOUNTER1_SELECT1 |
860 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
861 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
862 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
863 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
864 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
865 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
866 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
867 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
868 | //SDMA0_PERFCOUNTER1_LO |
869 | #define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
870 | #define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
871 | //SDMA0_PERFCOUNTER1_HI |
872 | #define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
873 | #define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
874 | //SDMA0_INT_STATUS |
875 | #define SDMA0_INT_STATUS__DATA__SHIFT 0x0 |
876 | #define SDMA0_INT_STATUS__DATA_MASK 0xFFFFFFFFL |
877 | //SDMA0_GPU_IOV_VIOLATION_LOG2 |
878 | #define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 |
879 | #define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL |
880 | //SDMA0_HOLE_ADDR_LO |
881 | #define SDMA0_HOLE_ADDR_LO__VALUE__SHIFT 0x0 |
882 | #define SDMA0_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL |
883 | //SDMA0_HOLE_ADDR_HI |
884 | #define SDMA0_HOLE_ADDR_HI__VALUE__SHIFT 0x0 |
885 | #define SDMA0_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL |
886 | //SDMA0_GFX_RB_CNTL |
887 | #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
888 | #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 |
889 | #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
890 | #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
891 | #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
892 | #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
893 | #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 |
894 | #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 |
895 | #define SDMA0_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
896 | #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
897 | #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
898 | #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
899 | #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
900 | #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
901 | #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
902 | #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L |
903 | #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L |
904 | #define SDMA0_GFX_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
905 | //SDMA0_GFX_RB_BASE |
906 | #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 |
907 | #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
908 | //SDMA0_GFX_RB_BASE_HI |
909 | #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 |
910 | #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
911 | //SDMA0_GFX_RB_RPTR |
912 | #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 |
913 | #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
914 | //SDMA0_GFX_RB_RPTR_HI |
915 | #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
916 | #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
917 | //SDMA0_GFX_RB_WPTR |
918 | #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 |
919 | #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
920 | //SDMA0_GFX_RB_WPTR_HI |
921 | #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
922 | #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
923 | //SDMA0_GFX_RB_WPTR_POLL_CNTL |
924 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
925 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
926 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
927 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
928 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
929 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
930 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
931 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
932 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
933 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
934 | //SDMA0_GFX_RB_RPTR_ADDR_HI |
935 | #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
936 | #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
937 | //SDMA0_GFX_RB_RPTR_ADDR_LO |
938 | #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
939 | #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
940 | //SDMA0_GFX_IB_CNTL |
941 | #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
942 | #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
943 | #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
944 | #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 |
945 | #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
946 | #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
947 | #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
948 | #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
949 | //SDMA0_GFX_IB_RPTR |
950 | #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 |
951 | #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
952 | //SDMA0_GFX_IB_OFFSET |
953 | #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 |
954 | #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
955 | //SDMA0_GFX_IB_BASE_LO |
956 | #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 |
957 | #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
958 | //SDMA0_GFX_IB_BASE_HI |
959 | #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 |
960 | #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
961 | //SDMA0_GFX_IB_SIZE |
962 | #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 |
963 | #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL |
964 | //SDMA0_GFX_SKIP_CNTL |
965 | #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
966 | #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
967 | //SDMA0_GFX_CONTEXT_STATUS |
968 | #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
969 | #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
970 | #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
971 | #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
972 | #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
973 | #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
974 | #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
975 | #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
976 | #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
977 | #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
978 | #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
979 | #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
980 | #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
981 | #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
982 | #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
983 | #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
984 | //SDMA0_GFX_DOORBELL |
985 | #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c |
986 | #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e |
987 | #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L |
988 | #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L |
989 | //SDMA0_GFX_CONTEXT_CNTL |
990 | #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 |
991 | #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L |
992 | //SDMA0_GFX_STATUS |
993 | #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
994 | #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
995 | #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
996 | #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
997 | //SDMA0_GFX_DOORBELL_LOG |
998 | //SDMA0_GFX_WATERMARK |
999 | #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
1000 | #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
1001 | #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
1002 | #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
1003 | //SDMA0_GFX_DOORBELL_OFFSET |
1004 | #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1005 | #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1006 | //SDMA0_GFX_CSA_ADDR_LO |
1007 | #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1008 | #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1009 | //SDMA0_GFX_CSA_ADDR_HI |
1010 | #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1011 | #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1012 | //SDMA0_GFX_IB_SUB_REMAIN |
1013 | #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1014 | #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1015 | //SDMA0_GFX_PREEMPT |
1016 | #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1017 | #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1018 | //SDMA0_GFX_DUMMY_REG |
1019 | #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 |
1020 | #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1021 | //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI |
1022 | #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1023 | #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1024 | //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO |
1025 | #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1026 | #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1027 | //SDMA0_GFX_RB_AQL_CNTL |
1028 | #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1029 | #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1030 | #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1031 | #define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1032 | #define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1033 | #define SDMA0_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1034 | #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1035 | #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1036 | #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1037 | #define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1038 | #define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1039 | #define SDMA0_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1040 | //SDMA0_GFX_MINOR_PTR_UPDATE |
1041 | #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1042 | #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1043 | //SDMA0_GFX_MIDCMD_DATA0 |
1044 | #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1045 | #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1046 | //SDMA0_GFX_MIDCMD_DATA1 |
1047 | #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1048 | #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1049 | //SDMA0_GFX_MIDCMD_DATA2 |
1050 | #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1051 | #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1052 | //SDMA0_GFX_MIDCMD_DATA3 |
1053 | #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1054 | #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1055 | //SDMA0_GFX_MIDCMD_DATA4 |
1056 | #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1057 | #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1058 | //SDMA0_GFX_MIDCMD_DATA5 |
1059 | #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1060 | #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1061 | //SDMA0_GFX_MIDCMD_DATA6 |
1062 | #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1063 | #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1064 | //SDMA0_GFX_MIDCMD_DATA7 |
1065 | #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
1066 | #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
1067 | //SDMA0_GFX_MIDCMD_DATA8 |
1068 | #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
1069 | #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
1070 | //SDMA0_GFX_MIDCMD_CNTL |
1071 | #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
1072 | #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
1073 | #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
1074 | #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
1075 | #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
1076 | #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
1077 | #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
1078 | #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
1079 | //SDMA0_PAGE_RB_CNTL |
1080 | #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1081 | #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1082 | #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1083 | #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1084 | #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1085 | #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1086 | #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1087 | #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 |
1088 | #define SDMA0_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
1089 | #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1090 | #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1091 | #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1092 | #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1093 | #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1094 | #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1095 | #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1096 | #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1097 | #define SDMA0_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
1098 | //SDMA0_PAGE_RB_BASE |
1099 | #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 |
1100 | #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1101 | //SDMA0_PAGE_RB_BASE_HI |
1102 | #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 |
1103 | #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1104 | //SDMA0_PAGE_RB_RPTR |
1105 | #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 |
1106 | #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1107 | //SDMA0_PAGE_RB_RPTR_HI |
1108 | #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1109 | #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1110 | //SDMA0_PAGE_RB_WPTR |
1111 | #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 |
1112 | #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1113 | //SDMA0_PAGE_RB_WPTR_HI |
1114 | #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1115 | #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1116 | //SDMA0_PAGE_RB_WPTR_POLL_CNTL |
1117 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
1118 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
1119 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
1120 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
1121 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
1122 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
1123 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
1124 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
1125 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
1126 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
1127 | //SDMA0_PAGE_RB_RPTR_ADDR_HI |
1128 | #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1129 | #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1130 | //SDMA0_PAGE_RB_RPTR_ADDR_LO |
1131 | #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1132 | #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1133 | //SDMA0_PAGE_IB_CNTL |
1134 | #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1135 | #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1136 | #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1137 | #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1138 | #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1139 | #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1140 | #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1141 | #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1142 | //SDMA0_PAGE_IB_RPTR |
1143 | #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 |
1144 | #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1145 | //SDMA0_PAGE_IB_OFFSET |
1146 | #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 |
1147 | #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1148 | //SDMA0_PAGE_IB_BASE_LO |
1149 | #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 |
1150 | #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1151 | //SDMA0_PAGE_IB_BASE_HI |
1152 | #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 |
1153 | #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1154 | //SDMA0_PAGE_IB_SIZE |
1155 | #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 |
1156 | #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1157 | //SDMA0_PAGE_SKIP_CNTL |
1158 | #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1159 | #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1160 | //SDMA0_PAGE_CONTEXT_STATUS |
1161 | #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1162 | #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1163 | #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1164 | #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1165 | #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1166 | #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
1167 | #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
1168 | #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1169 | #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1170 | #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1171 | #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1172 | #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1173 | #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1174 | #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
1175 | #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
1176 | #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1177 | //SDMA0_PAGE_DOORBELL |
1178 | #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c |
1179 | #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e |
1180 | #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L |
1181 | #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L |
1182 | //SDMA0_PAGE_STATUS |
1183 | #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
1184 | #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
1185 | #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
1186 | #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
1187 | //SDMA0_PAGE_DOORBELL_LOG |
1188 | //SDMA0_PAGE_WATERMARK |
1189 | #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
1190 | #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
1191 | #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
1192 | #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
1193 | //SDMA0_PAGE_DOORBELL_OFFSET |
1194 | #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1195 | #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1196 | //SDMA0_PAGE_CSA_ADDR_LO |
1197 | #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1198 | #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1199 | //SDMA0_PAGE_CSA_ADDR_HI |
1200 | #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1201 | #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1202 | //SDMA0_PAGE_IB_SUB_REMAIN |
1203 | #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1204 | #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1205 | //SDMA0_PAGE_PREEMPT |
1206 | #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1207 | #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1208 | //SDMA0_PAGE_DUMMY_REG |
1209 | #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 |
1210 | #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1211 | //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI |
1212 | #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1213 | #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1214 | //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO |
1215 | #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1216 | #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1217 | //SDMA0_PAGE_RB_AQL_CNTL |
1218 | #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1219 | #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1220 | #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1221 | #define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1222 | #define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1223 | #define SDMA0_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1224 | #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1225 | #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1226 | #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1227 | #define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1228 | #define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1229 | #define SDMA0_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1230 | //SDMA0_PAGE_MINOR_PTR_UPDATE |
1231 | #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1232 | #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1233 | //SDMA0_PAGE_MIDCMD_DATA0 |
1234 | #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1235 | #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1236 | //SDMA0_PAGE_MIDCMD_DATA1 |
1237 | #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1238 | #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1239 | //SDMA0_PAGE_MIDCMD_DATA2 |
1240 | #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1241 | #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1242 | //SDMA0_PAGE_MIDCMD_DATA3 |
1243 | #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1244 | #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1245 | //SDMA0_PAGE_MIDCMD_DATA4 |
1246 | #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1247 | #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1248 | //SDMA0_PAGE_MIDCMD_DATA5 |
1249 | #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1250 | #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1251 | //SDMA0_PAGE_MIDCMD_DATA6 |
1252 | #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1253 | #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1254 | //SDMA0_PAGE_MIDCMD_DATA7 |
1255 | #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
1256 | #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
1257 | //SDMA0_PAGE_MIDCMD_DATA8 |
1258 | #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
1259 | #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
1260 | //SDMA0_PAGE_MIDCMD_CNTL |
1261 | #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
1262 | #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
1263 | #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
1264 | #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
1265 | #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
1266 | #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
1267 | #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
1268 | #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
1269 | //SDMA0_RLC0_RB_CNTL |
1270 | #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1271 | #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1272 | #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1273 | #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1274 | #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1275 | #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1276 | #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1277 | #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 |
1278 | #define SDMA0_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
1279 | #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1280 | #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1281 | #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1282 | #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1283 | #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1284 | #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1285 | #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1286 | #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1287 | #define SDMA0_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
1288 | //SDMA0_RLC0_RB_BASE |
1289 | #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 |
1290 | #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1291 | //SDMA0_RLC0_RB_BASE_HI |
1292 | #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 |
1293 | #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1294 | //SDMA0_RLC0_RB_RPTR |
1295 | #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 |
1296 | #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1297 | //SDMA0_RLC0_RB_RPTR_HI |
1298 | #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1299 | #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1300 | //SDMA0_RLC0_RB_WPTR |
1301 | #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 |
1302 | #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1303 | //SDMA0_RLC0_RB_WPTR_HI |
1304 | #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1305 | #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1306 | //SDMA0_RLC0_RB_WPTR_POLL_CNTL |
1307 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
1308 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
1309 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
1310 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
1311 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
1312 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
1313 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
1314 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
1315 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
1316 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
1317 | //SDMA0_RLC0_RB_RPTR_ADDR_HI |
1318 | #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1319 | #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1320 | //SDMA0_RLC0_RB_RPTR_ADDR_LO |
1321 | #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1322 | #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1323 | //SDMA0_RLC0_IB_CNTL |
1324 | #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1325 | #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1326 | #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1327 | #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1328 | #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1329 | #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1330 | #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1331 | #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1332 | //SDMA0_RLC0_IB_RPTR |
1333 | #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 |
1334 | #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1335 | //SDMA0_RLC0_IB_OFFSET |
1336 | #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 |
1337 | #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1338 | //SDMA0_RLC0_IB_BASE_LO |
1339 | #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 |
1340 | #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1341 | //SDMA0_RLC0_IB_BASE_HI |
1342 | #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 |
1343 | #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1344 | //SDMA0_RLC0_IB_SIZE |
1345 | #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 |
1346 | #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1347 | //SDMA0_RLC0_SKIP_CNTL |
1348 | #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1349 | #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1350 | //SDMA0_RLC0_CONTEXT_STATUS |
1351 | #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1352 | #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1353 | #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1354 | #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1355 | #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1356 | #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
1357 | #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
1358 | #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1359 | #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1360 | #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1361 | #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1362 | #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1363 | #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1364 | #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
1365 | #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
1366 | #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1367 | //SDMA0_RLC0_DOORBELL |
1368 | #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c |
1369 | #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e |
1370 | #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L |
1371 | #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L |
1372 | //SDMA0_RLC0_STATUS |
1373 | #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
1374 | #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
1375 | #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
1376 | #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
1377 | //SDMA0_RLC0_DOORBELL_LOG |
1378 | //SDMA0_RLC0_WATERMARK |
1379 | #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
1380 | #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
1381 | #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
1382 | #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
1383 | //SDMA0_RLC0_DOORBELL_OFFSET |
1384 | #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1385 | #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1386 | //SDMA0_RLC0_CSA_ADDR_LO |
1387 | #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1388 | #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1389 | //SDMA0_RLC0_CSA_ADDR_HI |
1390 | #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1391 | #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1392 | //SDMA0_RLC0_IB_SUB_REMAIN |
1393 | #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1394 | #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1395 | //SDMA0_RLC0_PREEMPT |
1396 | #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1397 | #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1398 | //SDMA0_RLC0_DUMMY_REG |
1399 | #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 |
1400 | #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1401 | //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI |
1402 | #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1403 | #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1404 | //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO |
1405 | #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1406 | #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1407 | //SDMA0_RLC0_RB_AQL_CNTL |
1408 | #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1409 | #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1410 | #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1411 | #define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1412 | #define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1413 | #define SDMA0_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1414 | #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1415 | #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1416 | #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1417 | #define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1418 | #define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1419 | #define SDMA0_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1420 | //SDMA0_RLC0_MINOR_PTR_UPDATE |
1421 | #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1422 | #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1423 | //SDMA0_RLC0_MIDCMD_DATA0 |
1424 | #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1425 | #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1426 | //SDMA0_RLC0_MIDCMD_DATA1 |
1427 | #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1428 | #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1429 | //SDMA0_RLC0_MIDCMD_DATA2 |
1430 | #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1431 | #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1432 | //SDMA0_RLC0_MIDCMD_DATA3 |
1433 | #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1434 | #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1435 | //SDMA0_RLC0_MIDCMD_DATA4 |
1436 | #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1437 | #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1438 | //SDMA0_RLC0_MIDCMD_DATA5 |
1439 | #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1440 | #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1441 | //SDMA0_RLC0_MIDCMD_DATA6 |
1442 | #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1443 | #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1444 | //SDMA0_RLC0_MIDCMD_DATA7 |
1445 | #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
1446 | #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
1447 | //SDMA0_RLC0_MIDCMD_DATA8 |
1448 | #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
1449 | #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
1450 | //SDMA0_RLC0_MIDCMD_CNTL |
1451 | #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
1452 | #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
1453 | #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
1454 | #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
1455 | #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
1456 | #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
1457 | #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
1458 | #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
1459 | //SDMA0_RLC1_RB_CNTL |
1460 | #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1461 | #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1462 | #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1463 | #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1464 | #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1465 | #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1466 | #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1467 | #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 |
1468 | #define SDMA0_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
1469 | #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1470 | #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1471 | #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1472 | #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1473 | #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1474 | #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1475 | #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1476 | #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1477 | #define SDMA0_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
1478 | //SDMA0_RLC1_RB_BASE |
1479 | #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 |
1480 | #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1481 | //SDMA0_RLC1_RB_BASE_HI |
1482 | #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 |
1483 | #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1484 | //SDMA0_RLC1_RB_RPTR |
1485 | #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 |
1486 | #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1487 | //SDMA0_RLC1_RB_RPTR_HI |
1488 | #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1489 | #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1490 | //SDMA0_RLC1_RB_WPTR |
1491 | #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 |
1492 | #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1493 | //SDMA0_RLC1_RB_WPTR_HI |
1494 | #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1495 | #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1496 | //SDMA0_RLC1_RB_WPTR_POLL_CNTL |
1497 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
1498 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
1499 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
1500 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
1501 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
1502 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
1503 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
1504 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
1505 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
1506 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
1507 | //SDMA0_RLC1_RB_RPTR_ADDR_HI |
1508 | #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1509 | #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1510 | //SDMA0_RLC1_RB_RPTR_ADDR_LO |
1511 | #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1512 | #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1513 | //SDMA0_RLC1_IB_CNTL |
1514 | #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1515 | #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1516 | #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1517 | #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1518 | #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1519 | #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1520 | #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1521 | #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1522 | //SDMA0_RLC1_IB_RPTR |
1523 | #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 |
1524 | #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1525 | //SDMA0_RLC1_IB_OFFSET |
1526 | #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 |
1527 | #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1528 | //SDMA0_RLC1_IB_BASE_LO |
1529 | #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 |
1530 | #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1531 | //SDMA0_RLC1_IB_BASE_HI |
1532 | #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 |
1533 | #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1534 | //SDMA0_RLC1_IB_SIZE |
1535 | #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 |
1536 | #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1537 | //SDMA0_RLC1_SKIP_CNTL |
1538 | #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1539 | #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1540 | //SDMA0_RLC1_CONTEXT_STATUS |
1541 | #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1542 | #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1543 | #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1544 | #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1545 | #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1546 | #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
1547 | #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
1548 | #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1549 | #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1550 | #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1551 | #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1552 | #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1553 | #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1554 | #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
1555 | #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
1556 | #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1557 | //SDMA0_RLC1_DOORBELL |
1558 | #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c |
1559 | #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e |
1560 | #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L |
1561 | #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L |
1562 | //SDMA0_RLC1_STATUS |
1563 | #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
1564 | #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
1565 | #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
1566 | #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
1567 | //SDMA0_RLC1_DOORBELL_LOG |
1568 | //SDMA0_RLC1_WATERMARK |
1569 | #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
1570 | #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
1571 | #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
1572 | #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
1573 | //SDMA0_RLC1_DOORBELL_OFFSET |
1574 | #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1575 | #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1576 | //SDMA0_RLC1_CSA_ADDR_LO |
1577 | #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1578 | #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1579 | //SDMA0_RLC1_CSA_ADDR_HI |
1580 | #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1581 | #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1582 | //SDMA0_RLC1_IB_SUB_REMAIN |
1583 | #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1584 | #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1585 | //SDMA0_RLC1_PREEMPT |
1586 | #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1587 | #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1588 | //SDMA0_RLC1_DUMMY_REG |
1589 | #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 |
1590 | #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1591 | //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI |
1592 | #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1593 | #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1594 | //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO |
1595 | #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1596 | #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1597 | //SDMA0_RLC1_RB_AQL_CNTL |
1598 | #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1599 | #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1600 | #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1601 | #define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1602 | #define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1603 | #define SDMA0_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1604 | #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1605 | #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1606 | #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1607 | #define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1608 | #define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1609 | #define SDMA0_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1610 | //SDMA0_RLC1_MINOR_PTR_UPDATE |
1611 | #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1612 | #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1613 | //SDMA0_RLC1_MIDCMD_DATA0 |
1614 | #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1615 | #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1616 | //SDMA0_RLC1_MIDCMD_DATA1 |
1617 | #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1618 | #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1619 | //SDMA0_RLC1_MIDCMD_DATA2 |
1620 | #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1621 | #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1622 | //SDMA0_RLC1_MIDCMD_DATA3 |
1623 | #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1624 | #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1625 | //SDMA0_RLC1_MIDCMD_DATA4 |
1626 | #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1627 | #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1628 | //SDMA0_RLC1_MIDCMD_DATA5 |
1629 | #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1630 | #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1631 | //SDMA0_RLC1_MIDCMD_DATA6 |
1632 | #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1633 | #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1634 | //SDMA0_RLC1_MIDCMD_DATA7 |
1635 | #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
1636 | #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
1637 | //SDMA0_RLC1_MIDCMD_DATA8 |
1638 | #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
1639 | #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
1640 | //SDMA0_RLC1_MIDCMD_CNTL |
1641 | #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
1642 | #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
1643 | #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
1644 | #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
1645 | #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
1646 | #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
1647 | #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
1648 | #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
1649 | //SDMA0_RLC2_RB_CNTL |
1650 | #define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1651 | #define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1652 | #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1653 | #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1654 | #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1655 | #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1656 | #define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1657 | #define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 |
1658 | #define SDMA0_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
1659 | #define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1660 | #define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1661 | #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1662 | #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1663 | #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1664 | #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1665 | #define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1666 | #define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1667 | #define SDMA0_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
1668 | //SDMA0_RLC2_RB_BASE |
1669 | #define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0 |
1670 | #define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1671 | //SDMA0_RLC2_RB_BASE_HI |
1672 | #define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 |
1673 | #define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1674 | //SDMA0_RLC2_RB_RPTR |
1675 | #define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 |
1676 | #define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1677 | //SDMA0_RLC2_RB_RPTR_HI |
1678 | #define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1679 | #define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1680 | //SDMA0_RLC2_RB_WPTR |
1681 | #define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 |
1682 | #define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1683 | //SDMA0_RLC2_RB_WPTR_HI |
1684 | #define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1685 | #define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1686 | //SDMA0_RLC2_RB_WPTR_POLL_CNTL |
1687 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
1688 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
1689 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
1690 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
1691 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
1692 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
1693 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
1694 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
1695 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
1696 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
1697 | //SDMA0_RLC2_RB_RPTR_ADDR_HI |
1698 | #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1699 | #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1700 | //SDMA0_RLC2_RB_RPTR_ADDR_LO |
1701 | #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1702 | #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1703 | //SDMA0_RLC2_IB_CNTL |
1704 | #define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1705 | #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1706 | #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1707 | #define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1708 | #define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1709 | #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1710 | #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1711 | #define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1712 | //SDMA0_RLC2_IB_RPTR |
1713 | #define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 |
1714 | #define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1715 | //SDMA0_RLC2_IB_OFFSET |
1716 | #define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 |
1717 | #define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1718 | //SDMA0_RLC2_IB_BASE_LO |
1719 | #define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 |
1720 | #define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1721 | //SDMA0_RLC2_IB_BASE_HI |
1722 | #define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 |
1723 | #define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1724 | //SDMA0_RLC2_IB_SIZE |
1725 | #define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0 |
1726 | #define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1727 | //SDMA0_RLC2_SKIP_CNTL |
1728 | #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1729 | #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1730 | //SDMA0_RLC2_CONTEXT_STATUS |
1731 | #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1732 | #define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1733 | #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1734 | #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1735 | #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1736 | #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
1737 | #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
1738 | #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1739 | #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1740 | #define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1741 | #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1742 | #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1743 | #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1744 | #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
1745 | #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
1746 | #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1747 | //SDMA0_RLC2_DOORBELL |
1748 | #define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c |
1749 | #define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e |
1750 | #define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L |
1751 | #define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L |
1752 | //SDMA0_RLC2_STATUS |
1753 | #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
1754 | #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
1755 | #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
1756 | #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
1757 | //SDMA0_RLC2_DOORBELL_LOG |
1758 | //SDMA0_RLC2_WATERMARK |
1759 | #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
1760 | #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
1761 | #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
1762 | #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
1763 | //SDMA0_RLC2_DOORBELL_OFFSET |
1764 | #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1765 | #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1766 | //SDMA0_RLC2_CSA_ADDR_LO |
1767 | #define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1768 | #define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1769 | //SDMA0_RLC2_CSA_ADDR_HI |
1770 | #define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1771 | #define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1772 | //SDMA0_RLC2_IB_SUB_REMAIN |
1773 | #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1774 | #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1775 | //SDMA0_RLC2_PREEMPT |
1776 | #define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1777 | #define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1778 | //SDMA0_RLC2_DUMMY_REG |
1779 | #define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 |
1780 | #define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1781 | //SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI |
1782 | #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1783 | #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1784 | //SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO |
1785 | #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1786 | #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1787 | //SDMA0_RLC2_RB_AQL_CNTL |
1788 | #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1789 | #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1790 | #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1791 | #define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1792 | #define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1793 | #define SDMA0_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1794 | #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1795 | #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1796 | #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1797 | #define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1798 | #define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1799 | #define SDMA0_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1800 | //SDMA0_RLC2_MINOR_PTR_UPDATE |
1801 | #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1802 | #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1803 | //SDMA0_RLC2_MIDCMD_DATA0 |
1804 | #define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1805 | #define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1806 | //SDMA0_RLC2_MIDCMD_DATA1 |
1807 | #define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1808 | #define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1809 | //SDMA0_RLC2_MIDCMD_DATA2 |
1810 | #define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1811 | #define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1812 | //SDMA0_RLC2_MIDCMD_DATA3 |
1813 | #define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1814 | #define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1815 | //SDMA0_RLC2_MIDCMD_DATA4 |
1816 | #define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1817 | #define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1818 | //SDMA0_RLC2_MIDCMD_DATA5 |
1819 | #define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1820 | #define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1821 | //SDMA0_RLC2_MIDCMD_DATA6 |
1822 | #define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1823 | #define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1824 | //SDMA0_RLC2_MIDCMD_DATA7 |
1825 | #define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
1826 | #define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
1827 | //SDMA0_RLC2_MIDCMD_DATA8 |
1828 | #define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
1829 | #define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
1830 | //SDMA0_RLC2_MIDCMD_CNTL |
1831 | #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
1832 | #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
1833 | #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
1834 | #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
1835 | #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
1836 | #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
1837 | #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
1838 | #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
1839 | //SDMA0_RLC3_RB_CNTL |
1840 | #define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1841 | #define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1842 | #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1843 | #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1844 | #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1845 | #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1846 | #define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1847 | #define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 |
1848 | #define SDMA0_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
1849 | #define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1850 | #define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1851 | #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1852 | #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1853 | #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1854 | #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1855 | #define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1856 | #define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1857 | #define SDMA0_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
1858 | //SDMA0_RLC3_RB_BASE |
1859 | #define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0 |
1860 | #define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1861 | //SDMA0_RLC3_RB_BASE_HI |
1862 | #define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 |
1863 | #define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1864 | //SDMA0_RLC3_RB_RPTR |
1865 | #define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 |
1866 | #define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1867 | //SDMA0_RLC3_RB_RPTR_HI |
1868 | #define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1869 | #define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1870 | //SDMA0_RLC3_RB_WPTR |
1871 | #define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 |
1872 | #define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1873 | //SDMA0_RLC3_RB_WPTR_HI |
1874 | #define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1875 | #define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1876 | //SDMA0_RLC3_RB_WPTR_POLL_CNTL |
1877 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
1878 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
1879 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
1880 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
1881 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
1882 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
1883 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
1884 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
1885 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
1886 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
1887 | //SDMA0_RLC3_RB_RPTR_ADDR_HI |
1888 | #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1889 | #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1890 | //SDMA0_RLC3_RB_RPTR_ADDR_LO |
1891 | #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1892 | #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1893 | //SDMA0_RLC3_IB_CNTL |
1894 | #define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1895 | #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1896 | #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1897 | #define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1898 | #define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1899 | #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1900 | #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1901 | #define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1902 | //SDMA0_RLC3_IB_RPTR |
1903 | #define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 |
1904 | #define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1905 | //SDMA0_RLC3_IB_OFFSET |
1906 | #define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 |
1907 | #define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1908 | //SDMA0_RLC3_IB_BASE_LO |
1909 | #define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 |
1910 | #define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1911 | //SDMA0_RLC3_IB_BASE_HI |
1912 | #define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 |
1913 | #define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1914 | //SDMA0_RLC3_IB_SIZE |
1915 | #define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0 |
1916 | #define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1917 | //SDMA0_RLC3_SKIP_CNTL |
1918 | #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1919 | #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1920 | //SDMA0_RLC3_CONTEXT_STATUS |
1921 | #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1922 | #define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1923 | #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1924 | #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1925 | #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1926 | #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
1927 | #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
1928 | #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1929 | #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1930 | #define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1931 | #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1932 | #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1933 | #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1934 | #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
1935 | #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
1936 | #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1937 | //SDMA0_RLC3_DOORBELL |
1938 | #define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c |
1939 | #define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e |
1940 | #define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L |
1941 | #define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L |
1942 | //SDMA0_RLC3_STATUS |
1943 | #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
1944 | #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
1945 | #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
1946 | #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
1947 | //SDMA0_RLC3_DOORBELL_LOG |
1948 | //SDMA0_RLC3_WATERMARK |
1949 | #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
1950 | #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
1951 | #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
1952 | #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
1953 | //SDMA0_RLC3_DOORBELL_OFFSET |
1954 | #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1955 | #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1956 | //SDMA0_RLC3_CSA_ADDR_LO |
1957 | #define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1958 | #define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1959 | //SDMA0_RLC3_CSA_ADDR_HI |
1960 | #define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1961 | #define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1962 | //SDMA0_RLC3_IB_SUB_REMAIN |
1963 | #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1964 | #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1965 | //SDMA0_RLC3_PREEMPT |
1966 | #define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1967 | #define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1968 | //SDMA0_RLC3_DUMMY_REG |
1969 | #define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 |
1970 | #define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1971 | //SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI |
1972 | #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1973 | #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1974 | //SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO |
1975 | #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1976 | #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1977 | //SDMA0_RLC3_RB_AQL_CNTL |
1978 | #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1979 | #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1980 | #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1981 | #define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1982 | #define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1983 | #define SDMA0_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1984 | #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1985 | #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1986 | #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1987 | #define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1988 | #define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1989 | #define SDMA0_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1990 | //SDMA0_RLC3_MINOR_PTR_UPDATE |
1991 | #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1992 | #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1993 | //SDMA0_RLC3_MIDCMD_DATA0 |
1994 | #define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1995 | #define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1996 | //SDMA0_RLC3_MIDCMD_DATA1 |
1997 | #define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1998 | #define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1999 | //SDMA0_RLC3_MIDCMD_DATA2 |
2000 | #define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
2001 | #define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
2002 | //SDMA0_RLC3_MIDCMD_DATA3 |
2003 | #define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
2004 | #define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
2005 | //SDMA0_RLC3_MIDCMD_DATA4 |
2006 | #define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
2007 | #define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
2008 | //SDMA0_RLC3_MIDCMD_DATA5 |
2009 | #define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
2010 | #define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
2011 | //SDMA0_RLC3_MIDCMD_DATA6 |
2012 | #define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
2013 | #define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
2014 | //SDMA0_RLC3_MIDCMD_DATA7 |
2015 | #define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
2016 | #define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
2017 | //SDMA0_RLC3_MIDCMD_DATA8 |
2018 | #define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
2019 | #define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
2020 | //SDMA0_RLC3_MIDCMD_CNTL |
2021 | #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
2022 | #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
2023 | #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
2024 | #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
2025 | #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
2026 | #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
2027 | #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
2028 | #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
2029 | //SDMA0_RLC4_RB_CNTL |
2030 | #define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
2031 | #define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 |
2032 | #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
2033 | #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
2034 | #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
2035 | #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
2036 | #define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 |
2037 | #define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 |
2038 | #define SDMA0_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
2039 | #define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
2040 | #define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
2041 | #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
2042 | #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
2043 | #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
2044 | #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
2045 | #define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L |
2046 | #define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L |
2047 | #define SDMA0_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
2048 | //SDMA0_RLC4_RB_BASE |
2049 | #define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0 |
2050 | #define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
2051 | //SDMA0_RLC4_RB_BASE_HI |
2052 | #define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 |
2053 | #define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
2054 | //SDMA0_RLC4_RB_RPTR |
2055 | #define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 |
2056 | #define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
2057 | //SDMA0_RLC4_RB_RPTR_HI |
2058 | #define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
2059 | #define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2060 | //SDMA0_RLC4_RB_WPTR |
2061 | #define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 |
2062 | #define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
2063 | //SDMA0_RLC4_RB_WPTR_HI |
2064 | #define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
2065 | #define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2066 | //SDMA0_RLC4_RB_WPTR_POLL_CNTL |
2067 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
2068 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
2069 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
2070 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
2071 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
2072 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
2073 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
2074 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
2075 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
2076 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
2077 | //SDMA0_RLC4_RB_RPTR_ADDR_HI |
2078 | #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
2079 | #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2080 | //SDMA0_RLC4_RB_RPTR_ADDR_LO |
2081 | #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
2082 | #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2083 | //SDMA0_RLC4_IB_CNTL |
2084 | #define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
2085 | #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
2086 | #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
2087 | #define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 |
2088 | #define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
2089 | #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
2090 | #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
2091 | #define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
2092 | //SDMA0_RLC4_IB_RPTR |
2093 | #define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 |
2094 | #define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
2095 | //SDMA0_RLC4_IB_OFFSET |
2096 | #define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 |
2097 | #define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
2098 | //SDMA0_RLC4_IB_BASE_LO |
2099 | #define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 |
2100 | #define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
2101 | //SDMA0_RLC4_IB_BASE_HI |
2102 | #define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 |
2103 | #define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
2104 | //SDMA0_RLC4_IB_SIZE |
2105 | #define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0 |
2106 | #define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL |
2107 | //SDMA0_RLC4_SKIP_CNTL |
2108 | #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
2109 | #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
2110 | //SDMA0_RLC4_CONTEXT_STATUS |
2111 | #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
2112 | #define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
2113 | #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
2114 | #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
2115 | #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
2116 | #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
2117 | #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
2118 | #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
2119 | #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
2120 | #define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
2121 | #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
2122 | #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
2123 | #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
2124 | #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
2125 | #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
2126 | #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
2127 | //SDMA0_RLC4_DOORBELL |
2128 | #define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c |
2129 | #define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e |
2130 | #define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L |
2131 | #define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L |
2132 | //SDMA0_RLC4_STATUS |
2133 | #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
2134 | #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
2135 | #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
2136 | #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
2137 | //SDMA0_RLC4_DOORBELL_LOG |
2138 | //SDMA0_RLC4_WATERMARK |
2139 | #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
2140 | #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
2141 | #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
2142 | #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
2143 | //SDMA0_RLC4_DOORBELL_OFFSET |
2144 | #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
2145 | #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
2146 | //SDMA0_RLC4_CSA_ADDR_LO |
2147 | #define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
2148 | #define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2149 | //SDMA0_RLC4_CSA_ADDR_HI |
2150 | #define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
2151 | #define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2152 | //SDMA0_RLC4_IB_SUB_REMAIN |
2153 | #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
2154 | #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
2155 | //SDMA0_RLC4_PREEMPT |
2156 | #define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
2157 | #define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
2158 | //SDMA0_RLC4_DUMMY_REG |
2159 | #define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 |
2160 | #define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
2161 | //SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI |
2162 | #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
2163 | #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2164 | //SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO |
2165 | #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
2166 | #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2167 | //SDMA0_RLC4_RB_AQL_CNTL |
2168 | #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
2169 | #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
2170 | #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
2171 | #define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
2172 | #define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
2173 | #define SDMA0_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
2174 | #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
2175 | #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
2176 | #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
2177 | #define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
2178 | #define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
2179 | #define SDMA0_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
2180 | //SDMA0_RLC4_MINOR_PTR_UPDATE |
2181 | #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
2182 | #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
2183 | //SDMA0_RLC4_MIDCMD_DATA0 |
2184 | #define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
2185 | #define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
2186 | //SDMA0_RLC4_MIDCMD_DATA1 |
2187 | #define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
2188 | #define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
2189 | //SDMA0_RLC4_MIDCMD_DATA2 |
2190 | #define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
2191 | #define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
2192 | //SDMA0_RLC4_MIDCMD_DATA3 |
2193 | #define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
2194 | #define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
2195 | //SDMA0_RLC4_MIDCMD_DATA4 |
2196 | #define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
2197 | #define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
2198 | //SDMA0_RLC4_MIDCMD_DATA5 |
2199 | #define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
2200 | #define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
2201 | //SDMA0_RLC4_MIDCMD_DATA6 |
2202 | #define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
2203 | #define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
2204 | //SDMA0_RLC4_MIDCMD_DATA7 |
2205 | #define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
2206 | #define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
2207 | //SDMA0_RLC4_MIDCMD_DATA8 |
2208 | #define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
2209 | #define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
2210 | //SDMA0_RLC4_MIDCMD_CNTL |
2211 | #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
2212 | #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
2213 | #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
2214 | #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
2215 | #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
2216 | #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
2217 | #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
2218 | #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
2219 | //SDMA0_RLC5_RB_CNTL |
2220 | #define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
2221 | #define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 |
2222 | #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
2223 | #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
2224 | #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
2225 | #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
2226 | #define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 |
2227 | #define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 |
2228 | #define SDMA0_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
2229 | #define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
2230 | #define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
2231 | #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
2232 | #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
2233 | #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
2234 | #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
2235 | #define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L |
2236 | #define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L |
2237 | #define SDMA0_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
2238 | //SDMA0_RLC5_RB_BASE |
2239 | #define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0 |
2240 | #define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
2241 | //SDMA0_RLC5_RB_BASE_HI |
2242 | #define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 |
2243 | #define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
2244 | //SDMA0_RLC5_RB_RPTR |
2245 | #define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 |
2246 | #define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
2247 | //SDMA0_RLC5_RB_RPTR_HI |
2248 | #define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
2249 | #define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2250 | //SDMA0_RLC5_RB_WPTR |
2251 | #define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 |
2252 | #define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
2253 | //SDMA0_RLC5_RB_WPTR_HI |
2254 | #define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
2255 | #define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2256 | //SDMA0_RLC5_RB_WPTR_POLL_CNTL |
2257 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
2258 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
2259 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
2260 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
2261 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
2262 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
2263 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
2264 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
2265 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
2266 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
2267 | //SDMA0_RLC5_RB_RPTR_ADDR_HI |
2268 | #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
2269 | #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2270 | //SDMA0_RLC5_RB_RPTR_ADDR_LO |
2271 | #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
2272 | #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2273 | //SDMA0_RLC5_IB_CNTL |
2274 | #define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
2275 | #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
2276 | #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
2277 | #define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 |
2278 | #define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
2279 | #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
2280 | #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
2281 | #define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
2282 | //SDMA0_RLC5_IB_RPTR |
2283 | #define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 |
2284 | #define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
2285 | //SDMA0_RLC5_IB_OFFSET |
2286 | #define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 |
2287 | #define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
2288 | //SDMA0_RLC5_IB_BASE_LO |
2289 | #define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 |
2290 | #define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
2291 | //SDMA0_RLC5_IB_BASE_HI |
2292 | #define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 |
2293 | #define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
2294 | //SDMA0_RLC5_IB_SIZE |
2295 | #define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0 |
2296 | #define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL |
2297 | //SDMA0_RLC5_SKIP_CNTL |
2298 | #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
2299 | #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
2300 | //SDMA0_RLC5_CONTEXT_STATUS |
2301 | #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
2302 | #define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
2303 | #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
2304 | #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
2305 | #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
2306 | #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
2307 | #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
2308 | #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
2309 | #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
2310 | #define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
2311 | #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
2312 | #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
2313 | #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
2314 | #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
2315 | #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
2316 | #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
2317 | //SDMA0_RLC5_DOORBELL |
2318 | #define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c |
2319 | #define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e |
2320 | #define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L |
2321 | #define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L |
2322 | //SDMA0_RLC5_STATUS |
2323 | #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
2324 | #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
2325 | #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
2326 | #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
2327 | //SDMA0_RLC5_DOORBELL_LOG |
2328 | //SDMA0_RLC5_WATERMARK |
2329 | #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
2330 | #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
2331 | #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
2332 | #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
2333 | //SDMA0_RLC5_DOORBELL_OFFSET |
2334 | #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
2335 | #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
2336 | //SDMA0_RLC5_CSA_ADDR_LO |
2337 | #define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
2338 | #define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2339 | //SDMA0_RLC5_CSA_ADDR_HI |
2340 | #define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
2341 | #define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2342 | //SDMA0_RLC5_IB_SUB_REMAIN |
2343 | #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
2344 | #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
2345 | //SDMA0_RLC5_PREEMPT |
2346 | #define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
2347 | #define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
2348 | //SDMA0_RLC5_DUMMY_REG |
2349 | #define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 |
2350 | #define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
2351 | //SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI |
2352 | #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
2353 | #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2354 | //SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO |
2355 | #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
2356 | #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2357 | //SDMA0_RLC5_RB_AQL_CNTL |
2358 | #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
2359 | #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
2360 | #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
2361 | #define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
2362 | #define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
2363 | #define SDMA0_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
2364 | #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
2365 | #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
2366 | #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
2367 | #define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
2368 | #define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
2369 | #define SDMA0_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
2370 | //SDMA0_RLC5_MINOR_PTR_UPDATE |
2371 | #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
2372 | #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
2373 | //SDMA0_RLC5_MIDCMD_DATA0 |
2374 | #define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
2375 | #define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
2376 | //SDMA0_RLC5_MIDCMD_DATA1 |
2377 | #define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
2378 | #define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
2379 | //SDMA0_RLC5_MIDCMD_DATA2 |
2380 | #define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
2381 | #define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
2382 | //SDMA0_RLC5_MIDCMD_DATA3 |
2383 | #define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
2384 | #define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
2385 | //SDMA0_RLC5_MIDCMD_DATA4 |
2386 | #define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
2387 | #define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
2388 | //SDMA0_RLC5_MIDCMD_DATA5 |
2389 | #define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
2390 | #define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
2391 | //SDMA0_RLC5_MIDCMD_DATA6 |
2392 | #define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
2393 | #define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
2394 | //SDMA0_RLC5_MIDCMD_DATA7 |
2395 | #define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
2396 | #define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
2397 | //SDMA0_RLC5_MIDCMD_DATA8 |
2398 | #define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
2399 | #define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
2400 | //SDMA0_RLC5_MIDCMD_CNTL |
2401 | #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
2402 | #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
2403 | #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
2404 | #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
2405 | #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
2406 | #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
2407 | #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
2408 | #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
2409 | //SDMA0_RLC6_RB_CNTL |
2410 | #define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
2411 | #define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 |
2412 | #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
2413 | #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
2414 | #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
2415 | #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
2416 | #define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 |
2417 | #define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 |
2418 | #define SDMA0_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
2419 | #define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
2420 | #define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
2421 | #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
2422 | #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
2423 | #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
2424 | #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
2425 | #define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L |
2426 | #define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L |
2427 | #define SDMA0_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
2428 | //SDMA0_RLC6_RB_BASE |
2429 | #define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0 |
2430 | #define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
2431 | //SDMA0_RLC6_RB_BASE_HI |
2432 | #define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 |
2433 | #define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
2434 | //SDMA0_RLC6_RB_RPTR |
2435 | #define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 |
2436 | #define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
2437 | //SDMA0_RLC6_RB_RPTR_HI |
2438 | #define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
2439 | #define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2440 | //SDMA0_RLC6_RB_WPTR |
2441 | #define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 |
2442 | #define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
2443 | //SDMA0_RLC6_RB_WPTR_HI |
2444 | #define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
2445 | #define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2446 | //SDMA0_RLC6_RB_WPTR_POLL_CNTL |
2447 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
2448 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
2449 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
2450 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
2451 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
2452 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
2453 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
2454 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
2455 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
2456 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
2457 | //SDMA0_RLC6_RB_RPTR_ADDR_HI |
2458 | #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
2459 | #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2460 | //SDMA0_RLC6_RB_RPTR_ADDR_LO |
2461 | #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
2462 | #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2463 | //SDMA0_RLC6_IB_CNTL |
2464 | #define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
2465 | #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
2466 | #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
2467 | #define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 |
2468 | #define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
2469 | #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
2470 | #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
2471 | #define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
2472 | //SDMA0_RLC6_IB_RPTR |
2473 | #define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 |
2474 | #define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
2475 | //SDMA0_RLC6_IB_OFFSET |
2476 | #define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 |
2477 | #define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
2478 | //SDMA0_RLC6_IB_BASE_LO |
2479 | #define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 |
2480 | #define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
2481 | //SDMA0_RLC6_IB_BASE_HI |
2482 | #define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 |
2483 | #define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
2484 | //SDMA0_RLC6_IB_SIZE |
2485 | #define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0 |
2486 | #define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL |
2487 | //SDMA0_RLC6_SKIP_CNTL |
2488 | #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
2489 | #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
2490 | //SDMA0_RLC6_CONTEXT_STATUS |
2491 | #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
2492 | #define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
2493 | #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
2494 | #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
2495 | #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
2496 | #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
2497 | #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
2498 | #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
2499 | #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
2500 | #define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
2501 | #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
2502 | #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
2503 | #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
2504 | #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
2505 | #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
2506 | #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
2507 | //SDMA0_RLC6_DOORBELL |
2508 | #define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c |
2509 | #define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e |
2510 | #define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L |
2511 | #define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L |
2512 | //SDMA0_RLC6_STATUS |
2513 | #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
2514 | #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
2515 | #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
2516 | #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
2517 | //SDMA0_RLC6_DOORBELL_LOG |
2518 | //SDMA0_RLC6_WATERMARK |
2519 | #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
2520 | #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
2521 | #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
2522 | #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
2523 | //SDMA0_RLC6_DOORBELL_OFFSET |
2524 | #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
2525 | #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
2526 | //SDMA0_RLC6_CSA_ADDR_LO |
2527 | #define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
2528 | #define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2529 | //SDMA0_RLC6_CSA_ADDR_HI |
2530 | #define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
2531 | #define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2532 | //SDMA0_RLC6_IB_SUB_REMAIN |
2533 | #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
2534 | #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
2535 | //SDMA0_RLC6_PREEMPT |
2536 | #define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
2537 | #define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
2538 | //SDMA0_RLC6_DUMMY_REG |
2539 | #define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 |
2540 | #define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
2541 | //SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI |
2542 | #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
2543 | #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2544 | //SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO |
2545 | #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
2546 | #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2547 | //SDMA0_RLC6_RB_AQL_CNTL |
2548 | #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
2549 | #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
2550 | #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
2551 | #define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
2552 | #define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
2553 | #define SDMA0_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
2554 | #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
2555 | #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
2556 | #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
2557 | #define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
2558 | #define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
2559 | #define SDMA0_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
2560 | //SDMA0_RLC6_MINOR_PTR_UPDATE |
2561 | #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
2562 | #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
2563 | //SDMA0_RLC6_MIDCMD_DATA0 |
2564 | #define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
2565 | #define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
2566 | //SDMA0_RLC6_MIDCMD_DATA1 |
2567 | #define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
2568 | #define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
2569 | //SDMA0_RLC6_MIDCMD_DATA2 |
2570 | #define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
2571 | #define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
2572 | //SDMA0_RLC6_MIDCMD_DATA3 |
2573 | #define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
2574 | #define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
2575 | //SDMA0_RLC6_MIDCMD_DATA4 |
2576 | #define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
2577 | #define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
2578 | //SDMA0_RLC6_MIDCMD_DATA5 |
2579 | #define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
2580 | #define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
2581 | //SDMA0_RLC6_MIDCMD_DATA6 |
2582 | #define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
2583 | #define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
2584 | //SDMA0_RLC6_MIDCMD_DATA7 |
2585 | #define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
2586 | #define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
2587 | //SDMA0_RLC6_MIDCMD_DATA8 |
2588 | #define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
2589 | #define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
2590 | //SDMA0_RLC6_MIDCMD_CNTL |
2591 | #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
2592 | #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
2593 | #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
2594 | #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
2595 | #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
2596 | #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
2597 | #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
2598 | #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
2599 | //SDMA0_RLC7_RB_CNTL |
2600 | #define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
2601 | #define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 |
2602 | #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
2603 | #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
2604 | #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
2605 | #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
2606 | #define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 |
2607 | #define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 |
2608 | #define SDMA0_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
2609 | #define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
2610 | #define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
2611 | #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
2612 | #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
2613 | #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
2614 | #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
2615 | #define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L |
2616 | #define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L |
2617 | #define SDMA0_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
2618 | //SDMA0_RLC7_RB_BASE |
2619 | #define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0 |
2620 | #define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
2621 | //SDMA0_RLC7_RB_BASE_HI |
2622 | #define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 |
2623 | #define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
2624 | //SDMA0_RLC7_RB_RPTR |
2625 | #define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 |
2626 | #define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
2627 | //SDMA0_RLC7_RB_RPTR_HI |
2628 | #define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
2629 | #define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2630 | //SDMA0_RLC7_RB_WPTR |
2631 | #define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 |
2632 | #define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
2633 | //SDMA0_RLC7_RB_WPTR_HI |
2634 | #define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
2635 | #define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2636 | //SDMA0_RLC7_RB_WPTR_POLL_CNTL |
2637 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
2638 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
2639 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
2640 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
2641 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
2642 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
2643 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
2644 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
2645 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
2646 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
2647 | //SDMA0_RLC7_RB_RPTR_ADDR_HI |
2648 | #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
2649 | #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2650 | //SDMA0_RLC7_RB_RPTR_ADDR_LO |
2651 | #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
2652 | #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2653 | //SDMA0_RLC7_IB_CNTL |
2654 | #define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
2655 | #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
2656 | #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
2657 | #define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 |
2658 | #define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
2659 | #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
2660 | #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
2661 | #define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
2662 | //SDMA0_RLC7_IB_RPTR |
2663 | #define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 |
2664 | #define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
2665 | //SDMA0_RLC7_IB_OFFSET |
2666 | #define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 |
2667 | #define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
2668 | //SDMA0_RLC7_IB_BASE_LO |
2669 | #define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 |
2670 | #define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
2671 | //SDMA0_RLC7_IB_BASE_HI |
2672 | #define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 |
2673 | #define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
2674 | //SDMA0_RLC7_IB_SIZE |
2675 | #define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0 |
2676 | #define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL |
2677 | //SDMA0_RLC7_SKIP_CNTL |
2678 | #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
2679 | #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
2680 | //SDMA0_RLC7_CONTEXT_STATUS |
2681 | #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
2682 | #define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
2683 | #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
2684 | #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
2685 | #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
2686 | #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
2687 | #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
2688 | #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
2689 | #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
2690 | #define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
2691 | #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
2692 | #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
2693 | #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
2694 | #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
2695 | #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
2696 | #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
2697 | //SDMA0_RLC7_DOORBELL |
2698 | #define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c |
2699 | #define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e |
2700 | #define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L |
2701 | #define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L |
2702 | //SDMA0_RLC7_STATUS |
2703 | #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
2704 | #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
2705 | #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
2706 | #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
2707 | //SDMA0_RLC7_DOORBELL_LOG |
2708 | //SDMA0_RLC7_WATERMARK |
2709 | #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
2710 | #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
2711 | #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
2712 | #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
2713 | //SDMA0_RLC7_DOORBELL_OFFSET |
2714 | #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
2715 | #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
2716 | //SDMA0_RLC7_CSA_ADDR_LO |
2717 | #define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
2718 | #define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2719 | //SDMA0_RLC7_CSA_ADDR_HI |
2720 | #define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
2721 | #define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2722 | //SDMA0_RLC7_IB_SUB_REMAIN |
2723 | #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
2724 | #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
2725 | //SDMA0_RLC7_PREEMPT |
2726 | #define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
2727 | #define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
2728 | //SDMA0_RLC7_DUMMY_REG |
2729 | #define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 |
2730 | #define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
2731 | //SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI |
2732 | #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
2733 | #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2734 | //SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO |
2735 | #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
2736 | #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2737 | //SDMA0_RLC7_RB_AQL_CNTL |
2738 | #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
2739 | #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
2740 | #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
2741 | #define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
2742 | #define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
2743 | #define SDMA0_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
2744 | #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
2745 | #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
2746 | #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
2747 | #define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
2748 | #define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
2749 | #define SDMA0_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
2750 | //SDMA0_RLC7_MINOR_PTR_UPDATE |
2751 | #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
2752 | #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
2753 | //SDMA0_RLC7_MIDCMD_DATA0 |
2754 | #define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
2755 | #define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
2756 | //SDMA0_RLC7_MIDCMD_DATA1 |
2757 | #define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
2758 | #define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
2759 | //SDMA0_RLC7_MIDCMD_DATA2 |
2760 | #define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
2761 | #define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
2762 | //SDMA0_RLC7_MIDCMD_DATA3 |
2763 | #define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
2764 | #define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
2765 | //SDMA0_RLC7_MIDCMD_DATA4 |
2766 | #define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
2767 | #define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
2768 | //SDMA0_RLC7_MIDCMD_DATA5 |
2769 | #define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
2770 | #define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
2771 | //SDMA0_RLC7_MIDCMD_DATA6 |
2772 | #define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
2773 | #define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
2774 | //SDMA0_RLC7_MIDCMD_DATA7 |
2775 | #define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
2776 | #define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
2777 | //SDMA0_RLC7_MIDCMD_DATA8 |
2778 | #define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
2779 | #define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
2780 | //SDMA0_RLC7_MIDCMD_CNTL |
2781 | #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
2782 | #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
2783 | #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
2784 | #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
2785 | #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
2786 | #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
2787 | #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
2788 | #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
2789 | |
2790 | |
2791 | // addressBlock: gc_sdma1_sdma1dec |
2792 | //SDMA1_DEC_START |
2793 | #define SDMA1_DEC_START__START__SHIFT 0x0 |
2794 | #define SDMA1_DEC_START__START_MASK 0xFFFFFFFFL |
2795 | //SDMA1_PG_CNTL |
2796 | #define SDMA1_PG_CNTL__CMD__SHIFT 0x0 |
2797 | #define SDMA1_PG_CNTL__STATUS__SHIFT 0x10 |
2798 | #define SDMA1_PG_CNTL__CMD_MASK 0x0000000FL |
2799 | #define SDMA1_PG_CNTL__STATUS_MASK 0x000F0000L |
2800 | //SDMA1_PG_CTX_LO |
2801 | #define SDMA1_PG_CTX_LO__ADDR__SHIFT 0x0 |
2802 | #define SDMA1_PG_CTX_LO__ADDR_MASK 0xFFFFFFFFL |
2803 | //SDMA1_PG_CTX_HI |
2804 | #define SDMA1_PG_CTX_HI__ADDR__SHIFT 0x0 |
2805 | #define SDMA1_PG_CTX_HI__ADDR_MASK 0xFFFFFFFFL |
2806 | //SDMA1_PG_CTX_CNTL |
2807 | #define SDMA1_PG_CTX_CNTL__VMID__SHIFT 0x4 |
2808 | #define SDMA1_PG_CTX_CNTL__VMID_MASK 0x000000F0L |
2809 | //SDMA1_POWER_CNTL |
2810 | #define SDMA1_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 |
2811 | #define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 |
2812 | #define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 |
2813 | #define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 |
2814 | #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 |
2815 | #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 |
2816 | #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa |
2817 | #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb |
2818 | #define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc |
2819 | #define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a |
2820 | #define SDMA1_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L |
2821 | #define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L |
2822 | #define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L |
2823 | #define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L |
2824 | #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L |
2825 | #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L |
2826 | #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L |
2827 | #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L |
2828 | #define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L |
2829 | #define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L |
2830 | //SDMA1_CLK_CTRL |
2831 | #define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
2832 | #define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
2833 | #define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc |
2834 | #define SDMA1_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT 0x17 |
2835 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
2836 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
2837 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
2838 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
2839 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
2840 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
2841 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
2842 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
2843 | #define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
2844 | #define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
2845 | #define SDMA1_CLK_CTRL__RESERVED_MASK 0x007FF000L |
2846 | #define SDMA1_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK 0x00800000L |
2847 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
2848 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
2849 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
2850 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
2851 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
2852 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
2853 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
2854 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
2855 | //SDMA1_CNTL |
2856 | #define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 |
2857 | #define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 |
2858 | #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 |
2859 | #define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 |
2860 | #define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 |
2861 | #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 |
2862 | #define SDMA1_CNTL__PAGE_INT_ENABLE__SHIFT 0x7 |
2863 | #define SDMA1_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10 |
2864 | #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 |
2865 | #define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 |
2866 | #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c |
2867 | #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d |
2868 | #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e |
2869 | #define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L |
2870 | #define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L |
2871 | #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L |
2872 | #define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L |
2873 | #define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L |
2874 | #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L |
2875 | #define SDMA1_CNTL__PAGE_INT_ENABLE_MASK 0x00000080L |
2876 | #define SDMA1_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L |
2877 | #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L |
2878 | #define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L |
2879 | #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L |
2880 | #define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L |
2881 | #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L |
2882 | //SDMA1_CHICKEN_BITS |
2883 | #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 |
2884 | #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 |
2885 | #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 |
2886 | #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 |
2887 | #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa |
2888 | #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 |
2889 | #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 |
2890 | #define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 |
2891 | #define SDMA1_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT 0x13 |
2892 | #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 |
2893 | #define SDMA1_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT 0x15 |
2894 | #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 |
2895 | #define SDMA1_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT 0x18 |
2896 | #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 |
2897 | #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a |
2898 | #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c |
2899 | #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e |
2900 | #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L |
2901 | #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L |
2902 | #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L |
2903 | #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L |
2904 | #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L |
2905 | #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L |
2906 | #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L |
2907 | #define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L |
2908 | #define SDMA1_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK 0x00080000L |
2909 | #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L |
2910 | #define SDMA1_CHICKEN_BITS__CH_FGCG_ENABLE_MASK 0x00200000L |
2911 | #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L |
2912 | #define SDMA1_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK 0x01000000L |
2913 | #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L |
2914 | #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L |
2915 | #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L |
2916 | #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L |
2917 | //SDMA1_GB_ADDR_CONFIG |
2918 | #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
2919 | #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
2920 | #define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
2921 | #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 |
2922 | #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc |
2923 | #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
2924 | #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
2925 | #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
2926 | #define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
2927 | #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L |
2928 | #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L |
2929 | #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
2930 | //SDMA1_GB_ADDR_CONFIG_READ |
2931 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 |
2932 | #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
2933 | #define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
2934 | #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 |
2935 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc |
2936 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 |
2937 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L |
2938 | #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
2939 | #define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
2940 | #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L |
2941 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L |
2942 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L |
2943 | //SDMA1_RB_RPTR_FETCH_HI |
2944 | #define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 |
2945 | #define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL |
2946 | //SDMA1_SEM_WAIT_FAIL_TIMER_CNTL |
2947 | #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 |
2948 | #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL |
2949 | //SDMA1_RB_RPTR_FETCH |
2950 | #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 |
2951 | #define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL |
2952 | //SDMA1_IB_OFFSET_FETCH |
2953 | #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 |
2954 | #define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL |
2955 | //SDMA1_PROGRAM |
2956 | #define SDMA1_PROGRAM__STREAM__SHIFT 0x0 |
2957 | #define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL |
2958 | //SDMA1_STATUS_REG |
2959 | #define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 |
2960 | #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 |
2961 | #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 |
2962 | #define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 |
2963 | #define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 |
2964 | #define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 |
2965 | #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 |
2966 | #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 |
2967 | #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 |
2968 | #define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 |
2969 | #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa |
2970 | #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb |
2971 | #define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc |
2972 | #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd |
2973 | #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe |
2974 | #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf |
2975 | #define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 |
2976 | #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 |
2977 | #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 |
2978 | #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 |
2979 | #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 |
2980 | #define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 |
2981 | #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 |
2982 | #define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 |
2983 | #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a |
2984 | #define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b |
2985 | #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c |
2986 | #define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e |
2987 | #define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f |
2988 | #define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L |
2989 | #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L |
2990 | #define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L |
2991 | #define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L |
2992 | #define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L |
2993 | #define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L |
2994 | #define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L |
2995 | #define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L |
2996 | #define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L |
2997 | #define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L |
2998 | #define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L |
2999 | #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L |
3000 | #define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L |
3001 | #define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L |
3002 | #define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L |
3003 | #define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L |
3004 | #define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L |
3005 | #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L |
3006 | #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L |
3007 | #define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L |
3008 | #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L |
3009 | #define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L |
3010 | #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L |
3011 | #define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L |
3012 | #define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L |
3013 | #define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L |
3014 | #define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L |
3015 | #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L |
3016 | #define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L |
3017 | //SDMA1_STATUS1_REG |
3018 | #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 |
3019 | #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 |
3020 | #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 |
3021 | #define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 |
3022 | #define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 |
3023 | #define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 |
3024 | #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 |
3025 | #define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 |
3026 | #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa |
3027 | #define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd |
3028 | #define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe |
3029 | #define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf |
3030 | #define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 |
3031 | #define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 |
3032 | #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L |
3033 | #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L |
3034 | #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L |
3035 | #define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L |
3036 | #define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L |
3037 | #define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L |
3038 | #define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L |
3039 | #define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L |
3040 | #define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L |
3041 | #define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L |
3042 | #define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L |
3043 | #define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L |
3044 | #define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L |
3045 | #define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L |
3046 | //SDMA1_RD_BURST_CNTL |
3047 | #define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 |
3048 | #define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L |
3049 | //SDMA1_HBM_PAGE_CONFIG |
3050 | #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 |
3051 | #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L |
3052 | //SDMA1_UCODE_CHECKSUM |
3053 | #define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 |
3054 | #define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL |
3055 | //SDMA1_F32_CNTL |
3056 | #define SDMA1_F32_CNTL__HALT__SHIFT 0x0 |
3057 | #define SDMA1_F32_CNTL__STEP__SHIFT 0x1 |
3058 | #define SDMA1_F32_CNTL__CHECKSUM_CLR__SHIFT 0x8 |
3059 | #define SDMA1_F32_CNTL__RESET__SHIFT 0x9 |
3060 | #define SDMA1_F32_CNTL__HALT_MASK 0x00000001L |
3061 | #define SDMA1_F32_CNTL__STEP_MASK 0x00000002L |
3062 | #define SDMA1_F32_CNTL__CHECKSUM_CLR_MASK 0x00000100L |
3063 | #define SDMA1_F32_CNTL__RESET_MASK 0x00000200L |
3064 | //SDMA1_FREEZE |
3065 | #define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 |
3066 | #define SDMA1_FREEZE__FORCE_PREEMPT__SHIFT 0x1 |
3067 | #define SDMA1_FREEZE__FREEZE__SHIFT 0x4 |
3068 | #define SDMA1_FREEZE__FROZEN__SHIFT 0x5 |
3069 | #define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 |
3070 | #define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L |
3071 | #define SDMA1_FREEZE__FORCE_PREEMPT_MASK 0x00000002L |
3072 | #define SDMA1_FREEZE__FREEZE_MASK 0x00000010L |
3073 | #define SDMA1_FREEZE__FROZEN_MASK 0x00000020L |
3074 | #define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L |
3075 | //SDMA1_PHASE0_QUANTUM |
3076 | #define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 |
3077 | #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 |
3078 | #define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e |
3079 | #define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL |
3080 | #define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L |
3081 | #define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L |
3082 | //SDMA1_PHASE1_QUANTUM |
3083 | #define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 |
3084 | #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 |
3085 | #define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e |
3086 | #define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL |
3087 | #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L |
3088 | #define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L |
3089 | //SDMA1_EDC_CONFIG |
3090 | #define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 |
3091 | #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 |
3092 | #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L |
3093 | #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L |
3094 | //SDMA1_BA_THRESHOLD |
3095 | #define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 |
3096 | #define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 |
3097 | #define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL |
3098 | #define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L |
3099 | //SDMA1_ID |
3100 | #define SDMA1_ID__DEVICE_ID__SHIFT 0x0 |
3101 | #define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL |
3102 | //SDMA1_VERSION |
3103 | #define SDMA1_VERSION__MINVER__SHIFT 0x0 |
3104 | #define SDMA1_VERSION__MAJVER__SHIFT 0x8 |
3105 | #define SDMA1_VERSION__REV__SHIFT 0x10 |
3106 | #define SDMA1_VERSION__MINVER_MASK 0x0000007FL |
3107 | #define SDMA1_VERSION__MAJVER_MASK 0x00007F00L |
3108 | #define SDMA1_VERSION__REV_MASK 0x003F0000L |
3109 | //SDMA1_EDC_COUNTER |
3110 | #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 |
3111 | #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 |
3112 | #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 |
3113 | #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 |
3114 | #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 |
3115 | #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 |
3116 | #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 |
3117 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 |
3118 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 |
3119 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 |
3120 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa |
3121 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb |
3122 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc |
3123 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd |
3124 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe |
3125 | #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf |
3126 | #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 |
3127 | #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L |
3128 | #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L |
3129 | #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L |
3130 | #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L |
3131 | #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L |
3132 | #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L |
3133 | #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L |
3134 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L |
3135 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L |
3136 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L |
3137 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L |
3138 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L |
3139 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L |
3140 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L |
3141 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L |
3142 | #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L |
3143 | #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L |
3144 | //SDMA1_EDC_COUNTER_CLEAR |
3145 | #define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 |
3146 | #define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L |
3147 | //SDMA1_STATUS2_REG |
3148 | #define SDMA1_STATUS2_REG__ID__SHIFT 0x0 |
3149 | #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 |
3150 | #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 |
3151 | #define SDMA1_STATUS2_REG__ID_MASK 0x00000003L |
3152 | #define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL |
3153 | #define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L |
3154 | //SDMA1_ATOMIC_CNTL |
3155 | #define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 |
3156 | #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f |
3157 | #define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL |
3158 | #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L |
3159 | //SDMA1_ATOMIC_PREOP_LO |
3160 | #define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 |
3161 | #define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL |
3162 | //SDMA1_ATOMIC_PREOP_HI |
3163 | #define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 |
3164 | #define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL |
3165 | //SDMA1_UTCL1_CNTL |
3166 | #define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 |
3167 | #define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 |
3168 | #define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0x6 |
3169 | #define SDMA1_UTCL1_CNTL__RESP_MODE__SHIFT 0x9 |
3170 | #define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe |
3171 | #define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xf |
3172 | #define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x10 |
3173 | #define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 |
3174 | #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d |
3175 | #define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L |
3176 | #define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x0000003EL |
3177 | #define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x000001C0L |
3178 | #define SDMA1_UTCL1_CNTL__RESP_MODE_MASK 0x00000E00L |
3179 | #define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00004000L |
3180 | #define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00008000L |
3181 | #define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FF0000L |
3182 | #define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L |
3183 | #define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L |
3184 | //SDMA1_UTCL1_WATERMK |
3185 | #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 |
3186 | #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa |
3187 | #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 |
3188 | #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a |
3189 | #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL |
3190 | #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L |
3191 | #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L |
3192 | #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L |
3193 | //SDMA1_UTCL1_RD_STATUS |
3194 | #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 |
3195 | #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1 |
3196 | #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2 |
3197 | #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3 |
3198 | #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4 |
3199 | #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5 |
3200 | #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6 |
3201 | #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7 |
3202 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8 |
3203 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9 |
3204 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa |
3205 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb |
3206 | #define SDMA1_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT 0xc |
3207 | #define SDMA1_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT 0xd |
3208 | #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0xe |
3209 | #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0xf |
3210 | #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x10 |
3211 | #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x11 |
3212 | #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x15 |
3213 | #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x18 |
3214 | #define SDMA1_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT 0x19 |
3215 | #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT 0x1a |
3216 | #define SDMA1_UTCL1_RD_STATUS__HIT_CACHE__SHIFT 0x1b |
3217 | #define SDMA1_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT 0x1c |
3218 | #define SDMA1_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT 0x1d |
3219 | #define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT 0x1e |
3220 | #define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT 0x1f |
3221 | #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L |
3222 | #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L |
3223 | #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L |
3224 | #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L |
3225 | #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L |
3226 | #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L |
3227 | #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L |
3228 | #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L |
3229 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L |
3230 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L |
3231 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L |
3232 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L |
3233 | #define SDMA1_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L |
3234 | #define SDMA1_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK 0x00002000L |
3235 | #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00004000L |
3236 | #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00008000L |
3237 | #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00010000L |
3238 | #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x001E0000L |
3239 | #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x00E00000L |
3240 | #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x01000000L |
3241 | #define SDMA1_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK 0x02000000L |
3242 | #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK 0x04000000L |
3243 | #define SDMA1_UTCL1_RD_STATUS__HIT_CACHE_MASK 0x08000000L |
3244 | #define SDMA1_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK 0x10000000L |
3245 | #define SDMA1_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK 0x20000000L |
3246 | #define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK 0x40000000L |
3247 | #define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK 0x80000000L |
3248 | //SDMA1_UTCL1_WR_STATUS |
3249 | #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 |
3250 | #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1 |
3251 | #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2 |
3252 | #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3 |
3253 | #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4 |
3254 | #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5 |
3255 | #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6 |
3256 | #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7 |
3257 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8 |
3258 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9 |
3259 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa |
3260 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb |
3261 | #define SDMA1_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT 0xc |
3262 | #define SDMA1_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT 0xd |
3263 | #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0xe |
3264 | #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0xf |
3265 | #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x10 |
3266 | #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x11 |
3267 | #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x15 |
3268 | #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x18 |
3269 | #define SDMA1_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT 0x19 |
3270 | #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT 0x1a |
3271 | #define SDMA1_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT 0x1b |
3272 | #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c |
3273 | #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d |
3274 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e |
3275 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f |
3276 | #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L |
3277 | #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L |
3278 | #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L |
3279 | #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L |
3280 | #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L |
3281 | #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L |
3282 | #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L |
3283 | #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L |
3284 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L |
3285 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L |
3286 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L |
3287 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L |
3288 | #define SDMA1_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L |
3289 | #define SDMA1_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK 0x00002000L |
3290 | #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00004000L |
3291 | #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00008000L |
3292 | #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00010000L |
3293 | #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x001E0000L |
3294 | #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x00E00000L |
3295 | #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x01000000L |
3296 | #define SDMA1_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK 0x02000000L |
3297 | #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK 0x04000000L |
3298 | #define SDMA1_UTCL1_WR_STATUS__ATOMIC_OP_MASK 0x08000000L |
3299 | #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L |
3300 | #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L |
3301 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L |
3302 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L |
3303 | //SDMA1_UTCL1_INV0 |
3304 | #define SDMA1_UTCL1_INV0__CPF_INVREQ_EN__SHIFT 0x0 |
3305 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT 0x1 |
3306 | #define SDMA1_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT 0x2 |
3307 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT 0x3 |
3308 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT 0x4 |
3309 | #define SDMA1_UTCL1_INV0__INVREQ_SIZE__SHIFT 0x5 |
3310 | #define SDMA1_UTCL1_INV0__INVREQ_IDLE__SHIFT 0xb |
3311 | #define SDMA1_UTCL1_INV0__VMINV_PEND_CNT__SHIFT 0xc |
3312 | #define SDMA1_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT 0x10 |
3313 | #define SDMA1_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT 0x14 |
3314 | #define SDMA1_UTCL1_INV0__GPUVM_INV_MODE__SHIFT 0x18 |
3315 | #define SDMA1_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT 0x1a |
3316 | #define SDMA1_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT 0x1b |
3317 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT 0x1c |
3318 | #define SDMA1_UTCL1_INV0__CPF_INVREQ_EN_MASK 0x00000001L |
3319 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_EN_MASK 0x00000002L |
3320 | #define SDMA1_UTCL1_INV0__CPF_GPA_INVREQ_MASK 0x00000004L |
3321 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK 0x00000008L |
3322 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK 0x00000010L |
3323 | #define SDMA1_UTCL1_INV0__INVREQ_SIZE_MASK 0x000007E0L |
3324 | #define SDMA1_UTCL1_INV0__INVREQ_IDLE_MASK 0x00000800L |
3325 | #define SDMA1_UTCL1_INV0__VMINV_PEND_CNT_MASK 0x0000F000L |
3326 | #define SDMA1_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK 0x000F0000L |
3327 | #define SDMA1_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK 0x00F00000L |
3328 | #define SDMA1_UTCL1_INV0__GPUVM_INV_MODE_MASK 0x03000000L |
3329 | #define SDMA1_UTCL1_INV0__INVREQ_IS_HEAVY_MASK 0x04000000L |
3330 | #define SDMA1_UTCL1_INV0__INVREQ_FROM_CPF_MASK 0x08000000L |
3331 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK 0xF0000000L |
3332 | //SDMA1_UTCL1_INV1 |
3333 | #define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 |
3334 | #define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL |
3335 | //SDMA1_UTCL1_INV2 |
3336 | #define SDMA1_UTCL1_INV2__INV_VMID_VEC__SHIFT 0x0 |
3337 | #define SDMA1_UTCL1_INV2__RESERVED__SHIFT 0x10 |
3338 | #define SDMA1_UTCL1_INV2__INV_VMID_VEC_MASK 0x0000FFFFL |
3339 | #define SDMA1_UTCL1_INV2__RESERVED_MASK 0xFFFF0000L |
3340 | //SDMA1_UTCL1_RD_XNACK0 |
3341 | #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 |
3342 | #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL |
3343 | //SDMA1_UTCL1_RD_XNACK1 |
3344 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 |
3345 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 |
3346 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 |
3347 | #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a |
3348 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL |
3349 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L |
3350 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L |
3351 | #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L |
3352 | //SDMA1_UTCL1_WR_XNACK0 |
3353 | #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 |
3354 | #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL |
3355 | //SDMA1_UTCL1_WR_XNACK1 |
3356 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 |
3357 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 |
3358 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 |
3359 | #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a |
3360 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL |
3361 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L |
3362 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L |
3363 | #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L |
3364 | //SDMA1_UTCL1_TIMEOUT |
3365 | #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 |
3366 | #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 |
3367 | #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL |
3368 | #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L |
3369 | //SDMA1_UTCL1_PAGE |
3370 | #define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 |
3371 | #define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 |
3372 | #define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 |
3373 | #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa |
3374 | #define SDMA1_UTCL1_PAGE__USE_IO__SHIFT 0xb |
3375 | #define SDMA1_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc |
3376 | #define SDMA1_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe |
3377 | #define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT 0x10 |
3378 | #define SDMA1_UTCL1_PAGE__USE_BC__SHIFT 0x16 |
3379 | #define SDMA1_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17 |
3380 | #define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L |
3381 | #define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL |
3382 | #define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000003C0L |
3383 | #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L |
3384 | #define SDMA1_UTCL1_PAGE__USE_IO_MASK 0x00000800L |
3385 | #define SDMA1_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L |
3386 | #define SDMA1_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L |
3387 | #define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE_MASK 0x003F0000L |
3388 | #define SDMA1_UTCL1_PAGE__USE_BC_MASK 0x00400000L |
3389 | #define SDMA1_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L |
3390 | //SDMA1_POWER_CNTL_IDLE |
3391 | #define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 |
3392 | #define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 |
3393 | #define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 |
3394 | #define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL |
3395 | #define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L |
3396 | #define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L |
3397 | //SDMA1_RELAX_ORDERING_LUT |
3398 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 |
3399 | #define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 |
3400 | #define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 |
3401 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 |
3402 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 |
3403 | #define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 |
3404 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 |
3405 | #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 |
3406 | #define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 |
3407 | #define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa |
3408 | #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb |
3409 | #define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc |
3410 | #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd |
3411 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe |
3412 | #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b |
3413 | #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c |
3414 | #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d |
3415 | #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e |
3416 | #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f |
3417 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L |
3418 | #define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L |
3419 | #define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L |
3420 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L |
3421 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L |
3422 | #define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L |
3423 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L |
3424 | #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L |
3425 | #define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L |
3426 | #define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L |
3427 | #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L |
3428 | #define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L |
3429 | #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L |
3430 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L |
3431 | #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L |
3432 | #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L |
3433 | #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L |
3434 | #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L |
3435 | #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L |
3436 | //SDMA1_CHICKEN_BITS_2 |
3437 | #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 |
3438 | #define SDMA1_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT 0x4 |
3439 | #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL |
3440 | #define SDMA1_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK 0x00000010L |
3441 | //SDMA1_STATUS3_REG |
3442 | #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 |
3443 | #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 |
3444 | #define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 |
3445 | #define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15 |
3446 | #define SDMA1_STATUS3_REG__TLBI_IDLE__SHIFT 0x16 |
3447 | #define SDMA1_STATUS3_REG__GCR_IDLE__SHIFT 0x17 |
3448 | #define SDMA1_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18 |
3449 | #define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19 |
3450 | #define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a |
3451 | #define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL |
3452 | #define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L |
3453 | #define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L |
3454 | #define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L |
3455 | #define SDMA1_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L |
3456 | #define SDMA1_STATUS3_REG__GCR_IDLE_MASK 0x00800000L |
3457 | #define SDMA1_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L |
3458 | #define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L |
3459 | #define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L |
3460 | //SDMA1_PHYSICAL_ADDR_LO |
3461 | #define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 |
3462 | #define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 |
3463 | #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 |
3464 | #define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc |
3465 | #define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L |
3466 | #define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L |
3467 | #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L |
3468 | #define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L |
3469 | //SDMA1_PHYSICAL_ADDR_HI |
3470 | #define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 |
3471 | #define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL |
3472 | //SDMA1_PHASE2_QUANTUM |
3473 | #define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 |
3474 | #define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 |
3475 | #define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e |
3476 | #define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL |
3477 | #define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L |
3478 | #define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L |
3479 | //SDMA1_F32_COUNTER |
3480 | #define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 |
3481 | #define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL |
3482 | //SDMA1_PERFMON_CNTL |
3483 | #define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 |
3484 | #define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 |
3485 | #define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 |
3486 | #define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa |
3487 | #define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb |
3488 | #define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc |
3489 | #define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L |
3490 | #define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L |
3491 | #define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL |
3492 | #define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L |
3493 | #define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L |
3494 | #define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L |
3495 | //SDMA1_PERFCOUNTER0_RESULT |
3496 | #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 |
3497 | #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL |
3498 | //SDMA1_PERFCOUNTER1_RESULT |
3499 | #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 |
3500 | #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL |
3501 | //SDMA1_PERFCOUNTER_TAG_DELAY_RANGE |
3502 | #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 |
3503 | #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe |
3504 | #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c |
3505 | #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL |
3506 | #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L |
3507 | #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L |
3508 | //SDMA1_CRD_CNTL |
3509 | #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 |
3510 | #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd |
3511 | #define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13 |
3512 | #define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19 |
3513 | #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L |
3514 | #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L |
3515 | #define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L |
3516 | #define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L |
3517 | //SDMA1_GPU_IOV_VIOLATION_LOG |
3518 | //SDMA1_AQL_STATUS |
3519 | #define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0 |
3520 | #define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1 |
3521 | #define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L |
3522 | #define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L |
3523 | //SDMA1_EA_DBIT_ADDR_DATA |
3524 | #define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 |
3525 | #define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL |
3526 | //SDMA1_EA_DBIT_ADDR_INDEX |
3527 | #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 |
3528 | #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L |
3529 | //SDMA1_TLBI_GCR_CNTL |
3530 | #define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0 |
3531 | #define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4 |
3532 | #define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT 0x8 |
3533 | #define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10 |
3534 | #define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18 |
3535 | #define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL |
3536 | #define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L |
3537 | #define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK 0x00000F00L |
3538 | #define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L |
3539 | #define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L |
3540 | //SDMA1_TILING_CONFIG |
3541 | #define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
3542 | #define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L |
3543 | //SDMA1_HASH |
3544 | #define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0 |
3545 | #define SDMA1_HASH__BANK_BITS__SHIFT 0x4 |
3546 | #define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 |
3547 | #define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc |
3548 | #define SDMA1_HASH__CHANNEL_BITS_MASK 0x00000007L |
3549 | #define SDMA1_HASH__BANK_BITS_MASK 0x00000070L |
3550 | #define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x00000700L |
3551 | #define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x00007000L |
3552 | //SDMA1_PERFCOUNTER0_SELECT |
3553 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
3554 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
3555 | #define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
3556 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
3557 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
3558 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
3559 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
3560 | #define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
3561 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
3562 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
3563 | //SDMA1_PERFCOUNTER0_SELECT1 |
3564 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
3565 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
3566 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
3567 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
3568 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
3569 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
3570 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
3571 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
3572 | //SDMA1_PERFCOUNTER0_LO |
3573 | #define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
3574 | #define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
3575 | //SDMA1_PERFCOUNTER0_HI |
3576 | #define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
3577 | #define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
3578 | //SDMA1_PERFCOUNTER1_SELECT |
3579 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
3580 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
3581 | #define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
3582 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
3583 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
3584 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
3585 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
3586 | #define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
3587 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
3588 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
3589 | //SDMA1_PERFCOUNTER1_SELECT1 |
3590 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
3591 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
3592 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
3593 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
3594 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
3595 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
3596 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
3597 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
3598 | //SDMA1_PERFCOUNTER1_LO |
3599 | #define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
3600 | #define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
3601 | //SDMA1_PERFCOUNTER1_HI |
3602 | #define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
3603 | #define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
3604 | //SDMA1_INT_STATUS |
3605 | #define SDMA1_INT_STATUS__DATA__SHIFT 0x0 |
3606 | #define SDMA1_INT_STATUS__DATA_MASK 0xFFFFFFFFL |
3607 | //SDMA1_GPU_IOV_VIOLATION_LOG2 |
3608 | #define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 |
3609 | #define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL |
3610 | //SDMA1_HOLE_ADDR_LO |
3611 | #define SDMA1_HOLE_ADDR_LO__VALUE__SHIFT 0x0 |
3612 | #define SDMA1_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL |
3613 | //SDMA1_HOLE_ADDR_HI |
3614 | #define SDMA1_HOLE_ADDR_HI__VALUE__SHIFT 0x0 |
3615 | #define SDMA1_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL |
3616 | //SDMA1_GFX_RB_CNTL |
3617 | #define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
3618 | #define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 |
3619 | #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
3620 | #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
3621 | #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
3622 | #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
3623 | #define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 |
3624 | #define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 |
3625 | #define SDMA1_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
3626 | #define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
3627 | #define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
3628 | #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
3629 | #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
3630 | #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
3631 | #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
3632 | #define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L |
3633 | #define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L |
3634 | #define SDMA1_GFX_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
3635 | //SDMA1_GFX_RB_BASE |
3636 | #define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 |
3637 | #define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
3638 | //SDMA1_GFX_RB_BASE_HI |
3639 | #define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 |
3640 | #define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
3641 | //SDMA1_GFX_RB_RPTR |
3642 | #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 |
3643 | #define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
3644 | //SDMA1_GFX_RB_RPTR_HI |
3645 | #define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
3646 | #define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
3647 | //SDMA1_GFX_RB_WPTR |
3648 | #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 |
3649 | #define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
3650 | //SDMA1_GFX_RB_WPTR_HI |
3651 | #define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
3652 | #define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
3653 | //SDMA1_GFX_RB_WPTR_POLL_CNTL |
3654 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
3655 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
3656 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
3657 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
3658 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
3659 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
3660 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
3661 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
3662 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
3663 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
3664 | //SDMA1_GFX_RB_RPTR_ADDR_HI |
3665 | #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
3666 | #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3667 | //SDMA1_GFX_RB_RPTR_ADDR_LO |
3668 | #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
3669 | #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3670 | //SDMA1_GFX_IB_CNTL |
3671 | #define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
3672 | #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
3673 | #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
3674 | #define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 |
3675 | #define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
3676 | #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
3677 | #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
3678 | #define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
3679 | //SDMA1_GFX_IB_RPTR |
3680 | #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 |
3681 | #define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
3682 | //SDMA1_GFX_IB_OFFSET |
3683 | #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 |
3684 | #define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
3685 | //SDMA1_GFX_IB_BASE_LO |
3686 | #define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 |
3687 | #define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
3688 | //SDMA1_GFX_IB_BASE_HI |
3689 | #define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 |
3690 | #define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
3691 | //SDMA1_GFX_IB_SIZE |
3692 | #define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 |
3693 | #define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL |
3694 | //SDMA1_GFX_SKIP_CNTL |
3695 | #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
3696 | #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
3697 | //SDMA1_GFX_CONTEXT_STATUS |
3698 | #define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
3699 | #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
3700 | #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
3701 | #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
3702 | #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
3703 | #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
3704 | #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
3705 | #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
3706 | #define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
3707 | #define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
3708 | #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
3709 | #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
3710 | #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
3711 | #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
3712 | #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
3713 | #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
3714 | //SDMA1_GFX_DOORBELL |
3715 | #define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c |
3716 | #define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e |
3717 | #define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L |
3718 | #define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L |
3719 | //SDMA1_GFX_CONTEXT_CNTL |
3720 | #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 |
3721 | #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L |
3722 | //SDMA1_GFX_STATUS |
3723 | #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
3724 | #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
3725 | #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
3726 | #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
3727 | //SDMA1_GFX_DOORBELL_LOG |
3728 | //SDMA1_GFX_WATERMARK |
3729 | #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
3730 | #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
3731 | #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
3732 | #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
3733 | //SDMA1_GFX_DOORBELL_OFFSET |
3734 | #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
3735 | #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
3736 | //SDMA1_GFX_CSA_ADDR_LO |
3737 | #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
3738 | #define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3739 | //SDMA1_GFX_CSA_ADDR_HI |
3740 | #define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
3741 | #define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3742 | //SDMA1_GFX_IB_SUB_REMAIN |
3743 | #define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
3744 | #define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
3745 | //SDMA1_GFX_PREEMPT |
3746 | #define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
3747 | #define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
3748 | //SDMA1_GFX_DUMMY_REG |
3749 | #define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 |
3750 | #define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
3751 | //SDMA1_GFX_RB_WPTR_POLL_ADDR_HI |
3752 | #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
3753 | #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3754 | //SDMA1_GFX_RB_WPTR_POLL_ADDR_LO |
3755 | #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
3756 | #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3757 | //SDMA1_GFX_RB_AQL_CNTL |
3758 | #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
3759 | #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
3760 | #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
3761 | #define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
3762 | #define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
3763 | #define SDMA1_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
3764 | #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
3765 | #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
3766 | #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
3767 | #define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
3768 | #define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
3769 | #define SDMA1_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
3770 | //SDMA1_GFX_MINOR_PTR_UPDATE |
3771 | #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
3772 | #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
3773 | //SDMA1_GFX_MIDCMD_DATA0 |
3774 | #define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
3775 | #define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
3776 | //SDMA1_GFX_MIDCMD_DATA1 |
3777 | #define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
3778 | #define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
3779 | //SDMA1_GFX_MIDCMD_DATA2 |
3780 | #define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
3781 | #define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
3782 | //SDMA1_GFX_MIDCMD_DATA3 |
3783 | #define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
3784 | #define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
3785 | //SDMA1_GFX_MIDCMD_DATA4 |
3786 | #define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
3787 | #define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
3788 | //SDMA1_GFX_MIDCMD_DATA5 |
3789 | #define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
3790 | #define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
3791 | //SDMA1_GFX_MIDCMD_DATA6 |
3792 | #define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
3793 | #define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
3794 | //SDMA1_GFX_MIDCMD_DATA7 |
3795 | #define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
3796 | #define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
3797 | //SDMA1_GFX_MIDCMD_DATA8 |
3798 | #define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
3799 | #define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
3800 | //SDMA1_GFX_MIDCMD_CNTL |
3801 | #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
3802 | #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
3803 | #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
3804 | #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
3805 | #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
3806 | #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
3807 | #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
3808 | #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
3809 | //SDMA1_PAGE_RB_CNTL |
3810 | #define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
3811 | #define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 |
3812 | #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
3813 | #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
3814 | #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
3815 | #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
3816 | #define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 |
3817 | #define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 |
3818 | #define SDMA1_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
3819 | #define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
3820 | #define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
3821 | #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
3822 | #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
3823 | #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
3824 | #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
3825 | #define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L |
3826 | #define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L |
3827 | #define SDMA1_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
3828 | //SDMA1_PAGE_RB_BASE |
3829 | #define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 |
3830 | #define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
3831 | //SDMA1_PAGE_RB_BASE_HI |
3832 | #define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 |
3833 | #define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
3834 | //SDMA1_PAGE_RB_RPTR |
3835 | #define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 |
3836 | #define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
3837 | //SDMA1_PAGE_RB_RPTR_HI |
3838 | #define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
3839 | #define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
3840 | //SDMA1_PAGE_RB_WPTR |
3841 | #define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 |
3842 | #define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
3843 | //SDMA1_PAGE_RB_WPTR_HI |
3844 | #define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
3845 | #define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
3846 | //SDMA1_PAGE_RB_WPTR_POLL_CNTL |
3847 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
3848 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
3849 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
3850 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
3851 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
3852 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
3853 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
3854 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
3855 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
3856 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
3857 | //SDMA1_PAGE_RB_RPTR_ADDR_HI |
3858 | #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
3859 | #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3860 | //SDMA1_PAGE_RB_RPTR_ADDR_LO |
3861 | #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
3862 | #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3863 | //SDMA1_PAGE_IB_CNTL |
3864 | #define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
3865 | #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
3866 | #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
3867 | #define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 |
3868 | #define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
3869 | #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
3870 | #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
3871 | #define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
3872 | //SDMA1_PAGE_IB_RPTR |
3873 | #define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 |
3874 | #define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
3875 | //SDMA1_PAGE_IB_OFFSET |
3876 | #define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 |
3877 | #define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
3878 | //SDMA1_PAGE_IB_BASE_LO |
3879 | #define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 |
3880 | #define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
3881 | //SDMA1_PAGE_IB_BASE_HI |
3882 | #define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 |
3883 | #define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
3884 | //SDMA1_PAGE_IB_SIZE |
3885 | #define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 |
3886 | #define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL |
3887 | //SDMA1_PAGE_SKIP_CNTL |
3888 | #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
3889 | #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
3890 | //SDMA1_PAGE_CONTEXT_STATUS |
3891 | #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
3892 | #define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
3893 | #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
3894 | #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
3895 | #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
3896 | #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
3897 | #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
3898 | #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
3899 | #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
3900 | #define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
3901 | #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
3902 | #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
3903 | #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
3904 | #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
3905 | #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
3906 | #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
3907 | //SDMA1_PAGE_DOORBELL |
3908 | #define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c |
3909 | #define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e |
3910 | #define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L |
3911 | #define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L |
3912 | //SDMA1_PAGE_STATUS |
3913 | #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
3914 | #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
3915 | #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
3916 | #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
3917 | //SDMA1_PAGE_DOORBELL_LOG |
3918 | //SDMA1_PAGE_WATERMARK |
3919 | #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
3920 | #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
3921 | #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
3922 | #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
3923 | //SDMA1_PAGE_DOORBELL_OFFSET |
3924 | #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
3925 | #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
3926 | //SDMA1_PAGE_CSA_ADDR_LO |
3927 | #define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
3928 | #define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3929 | //SDMA1_PAGE_CSA_ADDR_HI |
3930 | #define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
3931 | #define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3932 | //SDMA1_PAGE_IB_SUB_REMAIN |
3933 | #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
3934 | #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
3935 | //SDMA1_PAGE_PREEMPT |
3936 | #define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
3937 | #define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
3938 | //SDMA1_PAGE_DUMMY_REG |
3939 | #define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 |
3940 | #define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
3941 | //SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI |
3942 | #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
3943 | #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3944 | //SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO |
3945 | #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
3946 | #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3947 | //SDMA1_PAGE_RB_AQL_CNTL |
3948 | #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
3949 | #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
3950 | #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
3951 | #define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
3952 | #define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
3953 | #define SDMA1_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
3954 | #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
3955 | #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
3956 | #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
3957 | #define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
3958 | #define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
3959 | #define SDMA1_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
3960 | //SDMA1_PAGE_MINOR_PTR_UPDATE |
3961 | #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
3962 | #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
3963 | //SDMA1_PAGE_MIDCMD_DATA0 |
3964 | #define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
3965 | #define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
3966 | //SDMA1_PAGE_MIDCMD_DATA1 |
3967 | #define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
3968 | #define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
3969 | //SDMA1_PAGE_MIDCMD_DATA2 |
3970 | #define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
3971 | #define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
3972 | //SDMA1_PAGE_MIDCMD_DATA3 |
3973 | #define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
3974 | #define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
3975 | //SDMA1_PAGE_MIDCMD_DATA4 |
3976 | #define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
3977 | #define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
3978 | //SDMA1_PAGE_MIDCMD_DATA5 |
3979 | #define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
3980 | #define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
3981 | //SDMA1_PAGE_MIDCMD_DATA6 |
3982 | #define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
3983 | #define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
3984 | //SDMA1_PAGE_MIDCMD_DATA7 |
3985 | #define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
3986 | #define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
3987 | //SDMA1_PAGE_MIDCMD_DATA8 |
3988 | #define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
3989 | #define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
3990 | //SDMA1_PAGE_MIDCMD_CNTL |
3991 | #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
3992 | #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
3993 | #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
3994 | #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
3995 | #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
3996 | #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
3997 | #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
3998 | #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
3999 | //SDMA1_RLC0_RB_CNTL |
4000 | #define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4001 | #define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4002 | #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4003 | #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4004 | #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4005 | #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4006 | #define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4007 | #define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 |
4008 | #define SDMA1_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
4009 | #define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4010 | #define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4011 | #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4012 | #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4013 | #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4014 | #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4015 | #define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4016 | #define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4017 | #define SDMA1_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
4018 | //SDMA1_RLC0_RB_BASE |
4019 | #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 |
4020 | #define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4021 | //SDMA1_RLC0_RB_BASE_HI |
4022 | #define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 |
4023 | #define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4024 | //SDMA1_RLC0_RB_RPTR |
4025 | #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 |
4026 | #define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4027 | //SDMA1_RLC0_RB_RPTR_HI |
4028 | #define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4029 | #define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4030 | //SDMA1_RLC0_RB_WPTR |
4031 | #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 |
4032 | #define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4033 | //SDMA1_RLC0_RB_WPTR_HI |
4034 | #define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4035 | #define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4036 | //SDMA1_RLC0_RB_WPTR_POLL_CNTL |
4037 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
4038 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
4039 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
4040 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
4041 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
4042 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
4043 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
4044 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
4045 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
4046 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
4047 | //SDMA1_RLC0_RB_RPTR_ADDR_HI |
4048 | #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4049 | #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4050 | //SDMA1_RLC0_RB_RPTR_ADDR_LO |
4051 | #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4052 | #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4053 | //SDMA1_RLC0_IB_CNTL |
4054 | #define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4055 | #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4056 | #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4057 | #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4058 | #define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4059 | #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4060 | #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4061 | #define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4062 | //SDMA1_RLC0_IB_RPTR |
4063 | #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 |
4064 | #define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4065 | //SDMA1_RLC0_IB_OFFSET |
4066 | #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 |
4067 | #define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4068 | //SDMA1_RLC0_IB_BASE_LO |
4069 | #define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 |
4070 | #define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4071 | //SDMA1_RLC0_IB_BASE_HI |
4072 | #define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 |
4073 | #define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4074 | //SDMA1_RLC0_IB_SIZE |
4075 | #define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 |
4076 | #define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4077 | //SDMA1_RLC0_SKIP_CNTL |
4078 | #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4079 | #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4080 | //SDMA1_RLC0_CONTEXT_STATUS |
4081 | #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4082 | #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4083 | #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4084 | #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4085 | #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4086 | #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
4087 | #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
4088 | #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4089 | #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4090 | #define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4091 | #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4092 | #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4093 | #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4094 | #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
4095 | #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
4096 | #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4097 | //SDMA1_RLC0_DOORBELL |
4098 | #define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c |
4099 | #define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e |
4100 | #define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L |
4101 | #define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L |
4102 | //SDMA1_RLC0_STATUS |
4103 | #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
4104 | #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
4105 | #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
4106 | #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
4107 | //SDMA1_RLC0_DOORBELL_LOG |
4108 | //SDMA1_RLC0_WATERMARK |
4109 | #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
4110 | #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
4111 | #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
4112 | #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
4113 | //SDMA1_RLC0_DOORBELL_OFFSET |
4114 | #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4115 | #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4116 | //SDMA1_RLC0_CSA_ADDR_LO |
4117 | #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4118 | #define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4119 | //SDMA1_RLC0_CSA_ADDR_HI |
4120 | #define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4121 | #define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4122 | //SDMA1_RLC0_IB_SUB_REMAIN |
4123 | #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4124 | #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4125 | //SDMA1_RLC0_PREEMPT |
4126 | #define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4127 | #define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4128 | //SDMA1_RLC0_DUMMY_REG |
4129 | #define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 |
4130 | #define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4131 | //SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI |
4132 | #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4133 | #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4134 | //SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO |
4135 | #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4136 | #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4137 | //SDMA1_RLC0_RB_AQL_CNTL |
4138 | #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4139 | #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4140 | #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4141 | #define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4142 | #define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4143 | #define SDMA1_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4144 | #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4145 | #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4146 | #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4147 | #define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4148 | #define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4149 | #define SDMA1_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4150 | //SDMA1_RLC0_MINOR_PTR_UPDATE |
4151 | #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4152 | #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4153 | //SDMA1_RLC0_MIDCMD_DATA0 |
4154 | #define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4155 | #define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4156 | //SDMA1_RLC0_MIDCMD_DATA1 |
4157 | #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4158 | #define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4159 | //SDMA1_RLC0_MIDCMD_DATA2 |
4160 | #define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4161 | #define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4162 | //SDMA1_RLC0_MIDCMD_DATA3 |
4163 | #define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4164 | #define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4165 | //SDMA1_RLC0_MIDCMD_DATA4 |
4166 | #define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4167 | #define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4168 | //SDMA1_RLC0_MIDCMD_DATA5 |
4169 | #define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4170 | #define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4171 | //SDMA1_RLC0_MIDCMD_DATA6 |
4172 | #define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4173 | #define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4174 | //SDMA1_RLC0_MIDCMD_DATA7 |
4175 | #define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4176 | #define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4177 | //SDMA1_RLC0_MIDCMD_DATA8 |
4178 | #define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4179 | #define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4180 | //SDMA1_RLC0_MIDCMD_CNTL |
4181 | #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4182 | #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4183 | #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4184 | #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4185 | #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4186 | #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4187 | #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4188 | #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4189 | //SDMA1_RLC1_RB_CNTL |
4190 | #define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4191 | #define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4192 | #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4193 | #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4194 | #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4195 | #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4196 | #define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4197 | #define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 |
4198 | #define SDMA1_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
4199 | #define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4200 | #define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4201 | #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4202 | #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4203 | #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4204 | #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4205 | #define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4206 | #define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4207 | #define SDMA1_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
4208 | //SDMA1_RLC1_RB_BASE |
4209 | #define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 |
4210 | #define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4211 | //SDMA1_RLC1_RB_BASE_HI |
4212 | #define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 |
4213 | #define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4214 | //SDMA1_RLC1_RB_RPTR |
4215 | #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 |
4216 | #define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4217 | //SDMA1_RLC1_RB_RPTR_HI |
4218 | #define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4219 | #define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4220 | //SDMA1_RLC1_RB_WPTR |
4221 | #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 |
4222 | #define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4223 | //SDMA1_RLC1_RB_WPTR_HI |
4224 | #define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4225 | #define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4226 | //SDMA1_RLC1_RB_WPTR_POLL_CNTL |
4227 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
4228 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
4229 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
4230 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
4231 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
4232 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
4233 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
4234 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
4235 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
4236 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
4237 | //SDMA1_RLC1_RB_RPTR_ADDR_HI |
4238 | #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4239 | #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4240 | //SDMA1_RLC1_RB_RPTR_ADDR_LO |
4241 | #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4242 | #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4243 | //SDMA1_RLC1_IB_CNTL |
4244 | #define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4245 | #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4246 | #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4247 | #define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4248 | #define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4249 | #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4250 | #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4251 | #define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4252 | //SDMA1_RLC1_IB_RPTR |
4253 | #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 |
4254 | #define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4255 | //SDMA1_RLC1_IB_OFFSET |
4256 | #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 |
4257 | #define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4258 | //SDMA1_RLC1_IB_BASE_LO |
4259 | #define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 |
4260 | #define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4261 | //SDMA1_RLC1_IB_BASE_HI |
4262 | #define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 |
4263 | #define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4264 | //SDMA1_RLC1_IB_SIZE |
4265 | #define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 |
4266 | #define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4267 | //SDMA1_RLC1_SKIP_CNTL |
4268 | #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4269 | #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4270 | //SDMA1_RLC1_CONTEXT_STATUS |
4271 | #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4272 | #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4273 | #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4274 | #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4275 | #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4276 | #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
4277 | #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
4278 | #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4279 | #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4280 | #define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4281 | #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4282 | #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4283 | #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4284 | #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
4285 | #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
4286 | #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4287 | //SDMA1_RLC1_DOORBELL |
4288 | #define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c |
4289 | #define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e |
4290 | #define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L |
4291 | #define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L |
4292 | //SDMA1_RLC1_STATUS |
4293 | #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
4294 | #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
4295 | #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
4296 | #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
4297 | //SDMA1_RLC1_DOORBELL_LOG |
4298 | //SDMA1_RLC1_WATERMARK |
4299 | #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
4300 | #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
4301 | #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
4302 | #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
4303 | //SDMA1_RLC1_DOORBELL_OFFSET |
4304 | #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4305 | #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4306 | //SDMA1_RLC1_CSA_ADDR_LO |
4307 | #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4308 | #define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4309 | //SDMA1_RLC1_CSA_ADDR_HI |
4310 | #define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4311 | #define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4312 | //SDMA1_RLC1_IB_SUB_REMAIN |
4313 | #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4314 | #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4315 | //SDMA1_RLC1_PREEMPT |
4316 | #define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4317 | #define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4318 | //SDMA1_RLC1_DUMMY_REG |
4319 | #define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 |
4320 | #define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4321 | //SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI |
4322 | #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4323 | #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4324 | //SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO |
4325 | #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4326 | #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4327 | //SDMA1_RLC1_RB_AQL_CNTL |
4328 | #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4329 | #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4330 | #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4331 | #define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4332 | #define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4333 | #define SDMA1_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4334 | #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4335 | #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4336 | #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4337 | #define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4338 | #define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4339 | #define SDMA1_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4340 | //SDMA1_RLC1_MINOR_PTR_UPDATE |
4341 | #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4342 | #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4343 | //SDMA1_RLC1_MIDCMD_DATA0 |
4344 | #define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4345 | #define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4346 | //SDMA1_RLC1_MIDCMD_DATA1 |
4347 | #define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4348 | #define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4349 | //SDMA1_RLC1_MIDCMD_DATA2 |
4350 | #define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4351 | #define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4352 | //SDMA1_RLC1_MIDCMD_DATA3 |
4353 | #define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4354 | #define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4355 | //SDMA1_RLC1_MIDCMD_DATA4 |
4356 | #define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4357 | #define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4358 | //SDMA1_RLC1_MIDCMD_DATA5 |
4359 | #define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4360 | #define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4361 | //SDMA1_RLC1_MIDCMD_DATA6 |
4362 | #define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4363 | #define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4364 | //SDMA1_RLC1_MIDCMD_DATA7 |
4365 | #define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4366 | #define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4367 | //SDMA1_RLC1_MIDCMD_DATA8 |
4368 | #define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4369 | #define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4370 | //SDMA1_RLC1_MIDCMD_CNTL |
4371 | #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4372 | #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4373 | #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4374 | #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4375 | #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4376 | #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4377 | #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4378 | #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4379 | //SDMA1_RLC2_RB_CNTL |
4380 | #define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4381 | #define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4382 | #define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4383 | #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4384 | #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4385 | #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4386 | #define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4387 | #define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 |
4388 | #define SDMA1_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
4389 | #define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4390 | #define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4391 | #define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4392 | #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4393 | #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4394 | #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4395 | #define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4396 | #define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4397 | #define SDMA1_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
4398 | //SDMA1_RLC2_RB_BASE |
4399 | #define SDMA1_RLC2_RB_BASE__ADDR__SHIFT 0x0 |
4400 | #define SDMA1_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4401 | //SDMA1_RLC2_RB_BASE_HI |
4402 | #define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 |
4403 | #define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4404 | //SDMA1_RLC2_RB_RPTR |
4405 | #define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 |
4406 | #define SDMA1_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4407 | //SDMA1_RLC2_RB_RPTR_HI |
4408 | #define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4409 | #define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4410 | //SDMA1_RLC2_RB_WPTR |
4411 | #define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 |
4412 | #define SDMA1_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4413 | //SDMA1_RLC2_RB_WPTR_HI |
4414 | #define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4415 | #define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4416 | //SDMA1_RLC2_RB_WPTR_POLL_CNTL |
4417 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
4418 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
4419 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
4420 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
4421 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
4422 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
4423 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
4424 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
4425 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
4426 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
4427 | //SDMA1_RLC2_RB_RPTR_ADDR_HI |
4428 | #define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4429 | #define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4430 | //SDMA1_RLC2_RB_RPTR_ADDR_LO |
4431 | #define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4432 | #define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4433 | //SDMA1_RLC2_IB_CNTL |
4434 | #define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4435 | #define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4436 | #define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4437 | #define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4438 | #define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4439 | #define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4440 | #define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4441 | #define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4442 | //SDMA1_RLC2_IB_RPTR |
4443 | #define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 |
4444 | #define SDMA1_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4445 | //SDMA1_RLC2_IB_OFFSET |
4446 | #define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 |
4447 | #define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4448 | //SDMA1_RLC2_IB_BASE_LO |
4449 | #define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 |
4450 | #define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4451 | //SDMA1_RLC2_IB_BASE_HI |
4452 | #define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 |
4453 | #define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4454 | //SDMA1_RLC2_IB_SIZE |
4455 | #define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT 0x0 |
4456 | #define SDMA1_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4457 | //SDMA1_RLC2_SKIP_CNTL |
4458 | #define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4459 | #define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4460 | //SDMA1_RLC2_CONTEXT_STATUS |
4461 | #define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4462 | #define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4463 | #define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4464 | #define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4465 | #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4466 | #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
4467 | #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
4468 | #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4469 | #define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4470 | #define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4471 | #define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4472 | #define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4473 | #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4474 | #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
4475 | #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
4476 | #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4477 | //SDMA1_RLC2_DOORBELL |
4478 | #define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT 0x1c |
4479 | #define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e |
4480 | #define SDMA1_RLC2_DOORBELL__ENABLE_MASK 0x10000000L |
4481 | #define SDMA1_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L |
4482 | //SDMA1_RLC2_STATUS |
4483 | #define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
4484 | #define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
4485 | #define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
4486 | #define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
4487 | //SDMA1_RLC2_DOORBELL_LOG |
4488 | //SDMA1_RLC2_WATERMARK |
4489 | #define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
4490 | #define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
4491 | #define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
4492 | #define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
4493 | //SDMA1_RLC2_DOORBELL_OFFSET |
4494 | #define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4495 | #define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4496 | //SDMA1_RLC2_CSA_ADDR_LO |
4497 | #define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4498 | #define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4499 | //SDMA1_RLC2_CSA_ADDR_HI |
4500 | #define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4501 | #define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4502 | //SDMA1_RLC2_IB_SUB_REMAIN |
4503 | #define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4504 | #define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4505 | //SDMA1_RLC2_PREEMPT |
4506 | #define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4507 | #define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4508 | //SDMA1_RLC2_DUMMY_REG |
4509 | #define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 |
4510 | #define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4511 | //SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI |
4512 | #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4513 | #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4514 | //SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO |
4515 | #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4516 | #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4517 | //SDMA1_RLC2_RB_AQL_CNTL |
4518 | #define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4519 | #define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4520 | #define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4521 | #define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4522 | #define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4523 | #define SDMA1_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4524 | #define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4525 | #define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4526 | #define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4527 | #define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4528 | #define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4529 | #define SDMA1_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4530 | //SDMA1_RLC2_MINOR_PTR_UPDATE |
4531 | #define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4532 | #define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4533 | //SDMA1_RLC2_MIDCMD_DATA0 |
4534 | #define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4535 | #define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4536 | //SDMA1_RLC2_MIDCMD_DATA1 |
4537 | #define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4538 | #define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4539 | //SDMA1_RLC2_MIDCMD_DATA2 |
4540 | #define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4541 | #define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4542 | //SDMA1_RLC2_MIDCMD_DATA3 |
4543 | #define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4544 | #define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4545 | //SDMA1_RLC2_MIDCMD_DATA4 |
4546 | #define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4547 | #define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4548 | //SDMA1_RLC2_MIDCMD_DATA5 |
4549 | #define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4550 | #define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4551 | //SDMA1_RLC2_MIDCMD_DATA6 |
4552 | #define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4553 | #define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4554 | //SDMA1_RLC2_MIDCMD_DATA7 |
4555 | #define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4556 | #define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4557 | //SDMA1_RLC2_MIDCMD_DATA8 |
4558 | #define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4559 | #define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4560 | //SDMA1_RLC2_MIDCMD_CNTL |
4561 | #define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4562 | #define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4563 | #define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4564 | #define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4565 | #define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4566 | #define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4567 | #define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4568 | #define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4569 | //SDMA1_RLC3_RB_CNTL |
4570 | #define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4571 | #define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4572 | #define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4573 | #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4574 | #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4575 | #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4576 | #define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4577 | #define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 |
4578 | #define SDMA1_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
4579 | #define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4580 | #define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4581 | #define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4582 | #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4583 | #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4584 | #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4585 | #define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4586 | #define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4587 | #define SDMA1_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
4588 | //SDMA1_RLC3_RB_BASE |
4589 | #define SDMA1_RLC3_RB_BASE__ADDR__SHIFT 0x0 |
4590 | #define SDMA1_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4591 | //SDMA1_RLC3_RB_BASE_HI |
4592 | #define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 |
4593 | #define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4594 | //SDMA1_RLC3_RB_RPTR |
4595 | #define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 |
4596 | #define SDMA1_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4597 | //SDMA1_RLC3_RB_RPTR_HI |
4598 | #define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4599 | #define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4600 | //SDMA1_RLC3_RB_WPTR |
4601 | #define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 |
4602 | #define SDMA1_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4603 | //SDMA1_RLC3_RB_WPTR_HI |
4604 | #define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4605 | #define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4606 | //SDMA1_RLC3_RB_WPTR_POLL_CNTL |
4607 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
4608 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
4609 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
4610 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
4611 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
4612 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
4613 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
4614 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
4615 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
4616 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
4617 | //SDMA1_RLC3_RB_RPTR_ADDR_HI |
4618 | #define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4619 | #define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4620 | //SDMA1_RLC3_RB_RPTR_ADDR_LO |
4621 | #define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4622 | #define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4623 | //SDMA1_RLC3_IB_CNTL |
4624 | #define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4625 | #define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4626 | #define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4627 | #define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4628 | #define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4629 | #define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4630 | #define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4631 | #define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4632 | //SDMA1_RLC3_IB_RPTR |
4633 | #define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 |
4634 | #define SDMA1_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4635 | //SDMA1_RLC3_IB_OFFSET |
4636 | #define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 |
4637 | #define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4638 | //SDMA1_RLC3_IB_BASE_LO |
4639 | #define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 |
4640 | #define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4641 | //SDMA1_RLC3_IB_BASE_HI |
4642 | #define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 |
4643 | #define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4644 | //SDMA1_RLC3_IB_SIZE |
4645 | #define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT 0x0 |
4646 | #define SDMA1_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4647 | //SDMA1_RLC3_SKIP_CNTL |
4648 | #define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4649 | #define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4650 | //SDMA1_RLC3_CONTEXT_STATUS |
4651 | #define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4652 | #define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4653 | #define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4654 | #define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4655 | #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4656 | #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
4657 | #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
4658 | #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4659 | #define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4660 | #define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4661 | #define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4662 | #define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4663 | #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4664 | #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
4665 | #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
4666 | #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4667 | //SDMA1_RLC3_DOORBELL |
4668 | #define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT 0x1c |
4669 | #define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e |
4670 | #define SDMA1_RLC3_DOORBELL__ENABLE_MASK 0x10000000L |
4671 | #define SDMA1_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L |
4672 | //SDMA1_RLC3_STATUS |
4673 | #define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
4674 | #define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
4675 | #define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
4676 | #define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
4677 | //SDMA1_RLC3_DOORBELL_LOG |
4678 | //SDMA1_RLC3_WATERMARK |
4679 | #define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
4680 | #define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
4681 | #define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
4682 | #define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
4683 | //SDMA1_RLC3_DOORBELL_OFFSET |
4684 | #define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4685 | #define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4686 | //SDMA1_RLC3_CSA_ADDR_LO |
4687 | #define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4688 | #define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4689 | //SDMA1_RLC3_CSA_ADDR_HI |
4690 | #define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4691 | #define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4692 | //SDMA1_RLC3_IB_SUB_REMAIN |
4693 | #define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4694 | #define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4695 | //SDMA1_RLC3_PREEMPT |
4696 | #define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4697 | #define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4698 | //SDMA1_RLC3_DUMMY_REG |
4699 | #define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 |
4700 | #define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4701 | //SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI |
4702 | #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4703 | #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4704 | //SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO |
4705 | #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4706 | #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4707 | //SDMA1_RLC3_RB_AQL_CNTL |
4708 | #define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4709 | #define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4710 | #define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4711 | #define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4712 | #define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4713 | #define SDMA1_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4714 | #define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4715 | #define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4716 | #define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4717 | #define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4718 | #define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4719 | #define SDMA1_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4720 | //SDMA1_RLC3_MINOR_PTR_UPDATE |
4721 | #define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4722 | #define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4723 | //SDMA1_RLC3_MIDCMD_DATA0 |
4724 | #define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4725 | #define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4726 | //SDMA1_RLC3_MIDCMD_DATA1 |
4727 | #define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4728 | #define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4729 | //SDMA1_RLC3_MIDCMD_DATA2 |
4730 | #define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4731 | #define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4732 | //SDMA1_RLC3_MIDCMD_DATA3 |
4733 | #define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4734 | #define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4735 | //SDMA1_RLC3_MIDCMD_DATA4 |
4736 | #define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4737 | #define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4738 | //SDMA1_RLC3_MIDCMD_DATA5 |
4739 | #define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4740 | #define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4741 | //SDMA1_RLC3_MIDCMD_DATA6 |
4742 | #define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4743 | #define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4744 | //SDMA1_RLC3_MIDCMD_DATA7 |
4745 | #define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4746 | #define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4747 | //SDMA1_RLC3_MIDCMD_DATA8 |
4748 | #define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4749 | #define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4750 | //SDMA1_RLC3_MIDCMD_CNTL |
4751 | #define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4752 | #define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4753 | #define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4754 | #define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4755 | #define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4756 | #define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4757 | #define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4758 | #define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4759 | //SDMA1_RLC4_RB_CNTL |
4760 | #define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4761 | #define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4762 | #define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4763 | #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4764 | #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4765 | #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4766 | #define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4767 | #define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 |
4768 | #define SDMA1_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
4769 | #define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4770 | #define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4771 | #define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4772 | #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4773 | #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4774 | #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4775 | #define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4776 | #define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4777 | #define SDMA1_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
4778 | //SDMA1_RLC4_RB_BASE |
4779 | #define SDMA1_RLC4_RB_BASE__ADDR__SHIFT 0x0 |
4780 | #define SDMA1_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4781 | //SDMA1_RLC4_RB_BASE_HI |
4782 | #define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 |
4783 | #define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4784 | //SDMA1_RLC4_RB_RPTR |
4785 | #define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 |
4786 | #define SDMA1_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4787 | //SDMA1_RLC4_RB_RPTR_HI |
4788 | #define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4789 | #define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4790 | //SDMA1_RLC4_RB_WPTR |
4791 | #define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 |
4792 | #define SDMA1_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4793 | //SDMA1_RLC4_RB_WPTR_HI |
4794 | #define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4795 | #define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4796 | //SDMA1_RLC4_RB_WPTR_POLL_CNTL |
4797 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
4798 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
4799 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
4800 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
4801 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
4802 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
4803 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
4804 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
4805 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
4806 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
4807 | //SDMA1_RLC4_RB_RPTR_ADDR_HI |
4808 | #define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4809 | #define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4810 | //SDMA1_RLC4_RB_RPTR_ADDR_LO |
4811 | #define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4812 | #define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4813 | //SDMA1_RLC4_IB_CNTL |
4814 | #define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4815 | #define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4816 | #define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4817 | #define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4818 | #define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4819 | #define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4820 | #define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4821 | #define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4822 | //SDMA1_RLC4_IB_RPTR |
4823 | #define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 |
4824 | #define SDMA1_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4825 | //SDMA1_RLC4_IB_OFFSET |
4826 | #define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 |
4827 | #define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4828 | //SDMA1_RLC4_IB_BASE_LO |
4829 | #define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 |
4830 | #define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4831 | //SDMA1_RLC4_IB_BASE_HI |
4832 | #define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 |
4833 | #define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4834 | //SDMA1_RLC4_IB_SIZE |
4835 | #define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT 0x0 |
4836 | #define SDMA1_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4837 | //SDMA1_RLC4_SKIP_CNTL |
4838 | #define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4839 | #define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4840 | //SDMA1_RLC4_CONTEXT_STATUS |
4841 | #define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4842 | #define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4843 | #define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4844 | #define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4845 | #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4846 | #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
4847 | #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
4848 | #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4849 | #define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4850 | #define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4851 | #define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4852 | #define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4853 | #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4854 | #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
4855 | #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
4856 | #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4857 | //SDMA1_RLC4_DOORBELL |
4858 | #define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT 0x1c |
4859 | #define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e |
4860 | #define SDMA1_RLC4_DOORBELL__ENABLE_MASK 0x10000000L |
4861 | #define SDMA1_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L |
4862 | //SDMA1_RLC4_STATUS |
4863 | #define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
4864 | #define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
4865 | #define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
4866 | #define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
4867 | //SDMA1_RLC4_DOORBELL_LOG |
4868 | //SDMA1_RLC4_WATERMARK |
4869 | #define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
4870 | #define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
4871 | #define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
4872 | #define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
4873 | //SDMA1_RLC4_DOORBELL_OFFSET |
4874 | #define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4875 | #define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4876 | //SDMA1_RLC4_CSA_ADDR_LO |
4877 | #define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4878 | #define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4879 | //SDMA1_RLC4_CSA_ADDR_HI |
4880 | #define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4881 | #define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4882 | //SDMA1_RLC4_IB_SUB_REMAIN |
4883 | #define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4884 | #define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4885 | //SDMA1_RLC4_PREEMPT |
4886 | #define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4887 | #define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4888 | //SDMA1_RLC4_DUMMY_REG |
4889 | #define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 |
4890 | #define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4891 | //SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI |
4892 | #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4893 | #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4894 | //SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO |
4895 | #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4896 | #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4897 | //SDMA1_RLC4_RB_AQL_CNTL |
4898 | #define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4899 | #define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4900 | #define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4901 | #define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4902 | #define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4903 | #define SDMA1_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4904 | #define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4905 | #define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4906 | #define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4907 | #define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4908 | #define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4909 | #define SDMA1_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4910 | //SDMA1_RLC4_MINOR_PTR_UPDATE |
4911 | #define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4912 | #define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4913 | //SDMA1_RLC4_MIDCMD_DATA0 |
4914 | #define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4915 | #define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4916 | //SDMA1_RLC4_MIDCMD_DATA1 |
4917 | #define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4918 | #define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4919 | //SDMA1_RLC4_MIDCMD_DATA2 |
4920 | #define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4921 | #define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4922 | //SDMA1_RLC4_MIDCMD_DATA3 |
4923 | #define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4924 | #define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4925 | //SDMA1_RLC4_MIDCMD_DATA4 |
4926 | #define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4927 | #define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4928 | //SDMA1_RLC4_MIDCMD_DATA5 |
4929 | #define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4930 | #define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4931 | //SDMA1_RLC4_MIDCMD_DATA6 |
4932 | #define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4933 | #define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4934 | //SDMA1_RLC4_MIDCMD_DATA7 |
4935 | #define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4936 | #define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4937 | //SDMA1_RLC4_MIDCMD_DATA8 |
4938 | #define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4939 | #define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4940 | //SDMA1_RLC4_MIDCMD_CNTL |
4941 | #define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4942 | #define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4943 | #define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4944 | #define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4945 | #define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4946 | #define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4947 | #define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4948 | #define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4949 | //SDMA1_RLC5_RB_CNTL |
4950 | #define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4951 | #define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4952 | #define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4953 | #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4954 | #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4955 | #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4956 | #define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4957 | #define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 |
4958 | #define SDMA1_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
4959 | #define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4960 | #define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4961 | #define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4962 | #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4963 | #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4964 | #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4965 | #define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4966 | #define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4967 | #define SDMA1_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
4968 | //SDMA1_RLC5_RB_BASE |
4969 | #define SDMA1_RLC5_RB_BASE__ADDR__SHIFT 0x0 |
4970 | #define SDMA1_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4971 | //SDMA1_RLC5_RB_BASE_HI |
4972 | #define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 |
4973 | #define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4974 | //SDMA1_RLC5_RB_RPTR |
4975 | #define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 |
4976 | #define SDMA1_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4977 | //SDMA1_RLC5_RB_RPTR_HI |
4978 | #define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4979 | #define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4980 | //SDMA1_RLC5_RB_WPTR |
4981 | #define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 |
4982 | #define SDMA1_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4983 | //SDMA1_RLC5_RB_WPTR_HI |
4984 | #define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4985 | #define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4986 | //SDMA1_RLC5_RB_WPTR_POLL_CNTL |
4987 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
4988 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
4989 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
4990 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
4991 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
4992 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
4993 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
4994 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
4995 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
4996 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
4997 | //SDMA1_RLC5_RB_RPTR_ADDR_HI |
4998 | #define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4999 | #define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5000 | //SDMA1_RLC5_RB_RPTR_ADDR_LO |
5001 | #define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
5002 | #define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5003 | //SDMA1_RLC5_IB_CNTL |
5004 | #define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
5005 | #define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
5006 | #define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
5007 | #define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 |
5008 | #define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
5009 | #define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
5010 | #define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
5011 | #define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
5012 | //SDMA1_RLC5_IB_RPTR |
5013 | #define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 |
5014 | #define SDMA1_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
5015 | //SDMA1_RLC5_IB_OFFSET |
5016 | #define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 |
5017 | #define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
5018 | //SDMA1_RLC5_IB_BASE_LO |
5019 | #define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 |
5020 | #define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
5021 | //SDMA1_RLC5_IB_BASE_HI |
5022 | #define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 |
5023 | #define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
5024 | //SDMA1_RLC5_IB_SIZE |
5025 | #define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT 0x0 |
5026 | #define SDMA1_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL |
5027 | //SDMA1_RLC5_SKIP_CNTL |
5028 | #define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
5029 | #define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
5030 | //SDMA1_RLC5_CONTEXT_STATUS |
5031 | #define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
5032 | #define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
5033 | #define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
5034 | #define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
5035 | #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
5036 | #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
5037 | #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
5038 | #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
5039 | #define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
5040 | #define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
5041 | #define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
5042 | #define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
5043 | #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
5044 | #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
5045 | #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
5046 | #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
5047 | //SDMA1_RLC5_DOORBELL |
5048 | #define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT 0x1c |
5049 | #define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e |
5050 | #define SDMA1_RLC5_DOORBELL__ENABLE_MASK 0x10000000L |
5051 | #define SDMA1_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L |
5052 | //SDMA1_RLC5_STATUS |
5053 | #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
5054 | #define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
5055 | #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
5056 | #define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
5057 | //SDMA1_RLC5_DOORBELL_LOG |
5058 | //SDMA1_RLC5_WATERMARK |
5059 | #define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
5060 | #define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
5061 | #define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
5062 | #define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
5063 | //SDMA1_RLC5_DOORBELL_OFFSET |
5064 | #define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
5065 | #define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
5066 | //SDMA1_RLC5_CSA_ADDR_LO |
5067 | #define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
5068 | #define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5069 | //SDMA1_RLC5_CSA_ADDR_HI |
5070 | #define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
5071 | #define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5072 | //SDMA1_RLC5_IB_SUB_REMAIN |
5073 | #define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
5074 | #define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
5075 | //SDMA1_RLC5_PREEMPT |
5076 | #define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
5077 | #define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
5078 | //SDMA1_RLC5_DUMMY_REG |
5079 | #define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 |
5080 | #define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
5081 | //SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI |
5082 | #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
5083 | #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5084 | //SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO |
5085 | #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
5086 | #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5087 | //SDMA1_RLC5_RB_AQL_CNTL |
5088 | #define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
5089 | #define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
5090 | #define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
5091 | #define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
5092 | #define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
5093 | #define SDMA1_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
5094 | #define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
5095 | #define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
5096 | #define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
5097 | #define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
5098 | #define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
5099 | #define SDMA1_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
5100 | //SDMA1_RLC5_MINOR_PTR_UPDATE |
5101 | #define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
5102 | #define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
5103 | //SDMA1_RLC5_MIDCMD_DATA0 |
5104 | #define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
5105 | #define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
5106 | //SDMA1_RLC5_MIDCMD_DATA1 |
5107 | #define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
5108 | #define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
5109 | //SDMA1_RLC5_MIDCMD_DATA2 |
5110 | #define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
5111 | #define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
5112 | //SDMA1_RLC5_MIDCMD_DATA3 |
5113 | #define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
5114 | #define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
5115 | //SDMA1_RLC5_MIDCMD_DATA4 |
5116 | #define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
5117 | #define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
5118 | //SDMA1_RLC5_MIDCMD_DATA5 |
5119 | #define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
5120 | #define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
5121 | //SDMA1_RLC5_MIDCMD_DATA6 |
5122 | #define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
5123 | #define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
5124 | //SDMA1_RLC5_MIDCMD_DATA7 |
5125 | #define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
5126 | #define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
5127 | //SDMA1_RLC5_MIDCMD_DATA8 |
5128 | #define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
5129 | #define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
5130 | //SDMA1_RLC5_MIDCMD_CNTL |
5131 | #define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
5132 | #define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
5133 | #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
5134 | #define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
5135 | #define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
5136 | #define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
5137 | #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
5138 | #define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
5139 | //SDMA1_RLC6_RB_CNTL |
5140 | #define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
5141 | #define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 |
5142 | #define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
5143 | #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
5144 | #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
5145 | #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
5146 | #define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 |
5147 | #define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 |
5148 | #define SDMA1_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
5149 | #define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
5150 | #define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
5151 | #define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
5152 | #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
5153 | #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
5154 | #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
5155 | #define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L |
5156 | #define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L |
5157 | #define SDMA1_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
5158 | //SDMA1_RLC6_RB_BASE |
5159 | #define SDMA1_RLC6_RB_BASE__ADDR__SHIFT 0x0 |
5160 | #define SDMA1_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
5161 | //SDMA1_RLC6_RB_BASE_HI |
5162 | #define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 |
5163 | #define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
5164 | //SDMA1_RLC6_RB_RPTR |
5165 | #define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 |
5166 | #define SDMA1_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
5167 | //SDMA1_RLC6_RB_RPTR_HI |
5168 | #define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
5169 | #define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
5170 | //SDMA1_RLC6_RB_WPTR |
5171 | #define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 |
5172 | #define SDMA1_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
5173 | //SDMA1_RLC6_RB_WPTR_HI |
5174 | #define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
5175 | #define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
5176 | //SDMA1_RLC6_RB_WPTR_POLL_CNTL |
5177 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
5178 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
5179 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
5180 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
5181 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
5182 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
5183 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
5184 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
5185 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
5186 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
5187 | //SDMA1_RLC6_RB_RPTR_ADDR_HI |
5188 | #define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
5189 | #define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5190 | //SDMA1_RLC6_RB_RPTR_ADDR_LO |
5191 | #define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
5192 | #define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5193 | //SDMA1_RLC6_IB_CNTL |
5194 | #define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
5195 | #define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
5196 | #define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
5197 | #define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 |
5198 | #define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
5199 | #define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
5200 | #define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
5201 | #define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
5202 | //SDMA1_RLC6_IB_RPTR |
5203 | #define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 |
5204 | #define SDMA1_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
5205 | //SDMA1_RLC6_IB_OFFSET |
5206 | #define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 |
5207 | #define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
5208 | //SDMA1_RLC6_IB_BASE_LO |
5209 | #define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 |
5210 | #define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
5211 | //SDMA1_RLC6_IB_BASE_HI |
5212 | #define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 |
5213 | #define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
5214 | //SDMA1_RLC6_IB_SIZE |
5215 | #define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT 0x0 |
5216 | #define SDMA1_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL |
5217 | //SDMA1_RLC6_SKIP_CNTL |
5218 | #define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
5219 | #define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
5220 | //SDMA1_RLC6_CONTEXT_STATUS |
5221 | #define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
5222 | #define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
5223 | #define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
5224 | #define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
5225 | #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
5226 | #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
5227 | #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
5228 | #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
5229 | #define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
5230 | #define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
5231 | #define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
5232 | #define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
5233 | #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
5234 | #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
5235 | #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
5236 | #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
5237 | //SDMA1_RLC6_DOORBELL |
5238 | #define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT 0x1c |
5239 | #define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e |
5240 | #define SDMA1_RLC6_DOORBELL__ENABLE_MASK 0x10000000L |
5241 | #define SDMA1_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L |
5242 | //SDMA1_RLC6_STATUS |
5243 | #define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
5244 | #define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
5245 | #define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
5246 | #define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
5247 | //SDMA1_RLC6_DOORBELL_LOG |
5248 | //SDMA1_RLC6_WATERMARK |
5249 | #define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
5250 | #define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
5251 | #define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
5252 | #define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
5253 | //SDMA1_RLC6_DOORBELL_OFFSET |
5254 | #define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
5255 | #define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
5256 | //SDMA1_RLC6_CSA_ADDR_LO |
5257 | #define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
5258 | #define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5259 | //SDMA1_RLC6_CSA_ADDR_HI |
5260 | #define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
5261 | #define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5262 | //SDMA1_RLC6_IB_SUB_REMAIN |
5263 | #define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
5264 | #define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
5265 | //SDMA1_RLC6_PREEMPT |
5266 | #define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
5267 | #define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
5268 | //SDMA1_RLC6_DUMMY_REG |
5269 | #define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 |
5270 | #define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
5271 | //SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI |
5272 | #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
5273 | #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5274 | //SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO |
5275 | #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
5276 | #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5277 | //SDMA1_RLC6_RB_AQL_CNTL |
5278 | #define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
5279 | #define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
5280 | #define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
5281 | #define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
5282 | #define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
5283 | #define SDMA1_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
5284 | #define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
5285 | #define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
5286 | #define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
5287 | #define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
5288 | #define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
5289 | #define SDMA1_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
5290 | //SDMA1_RLC6_MINOR_PTR_UPDATE |
5291 | #define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
5292 | #define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
5293 | //SDMA1_RLC6_MIDCMD_DATA0 |
5294 | #define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
5295 | #define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
5296 | //SDMA1_RLC6_MIDCMD_DATA1 |
5297 | #define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
5298 | #define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
5299 | //SDMA1_RLC6_MIDCMD_DATA2 |
5300 | #define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
5301 | #define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
5302 | //SDMA1_RLC6_MIDCMD_DATA3 |
5303 | #define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
5304 | #define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
5305 | //SDMA1_RLC6_MIDCMD_DATA4 |
5306 | #define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
5307 | #define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
5308 | //SDMA1_RLC6_MIDCMD_DATA5 |
5309 | #define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
5310 | #define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
5311 | //SDMA1_RLC6_MIDCMD_DATA6 |
5312 | #define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
5313 | #define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
5314 | //SDMA1_RLC6_MIDCMD_DATA7 |
5315 | #define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
5316 | #define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
5317 | //SDMA1_RLC6_MIDCMD_DATA8 |
5318 | #define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
5319 | #define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
5320 | //SDMA1_RLC6_MIDCMD_CNTL |
5321 | #define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
5322 | #define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
5323 | #define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
5324 | #define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
5325 | #define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
5326 | #define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
5327 | #define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
5328 | #define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
5329 | //SDMA1_RLC7_RB_CNTL |
5330 | #define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
5331 | #define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 |
5332 | #define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
5333 | #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
5334 | #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
5335 | #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
5336 | #define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 |
5337 | #define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 |
5338 | #define SDMA1_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
5339 | #define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
5340 | #define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
5341 | #define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
5342 | #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
5343 | #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
5344 | #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
5345 | #define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L |
5346 | #define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L |
5347 | #define SDMA1_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
5348 | //SDMA1_RLC7_RB_BASE |
5349 | #define SDMA1_RLC7_RB_BASE__ADDR__SHIFT 0x0 |
5350 | #define SDMA1_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
5351 | //SDMA1_RLC7_RB_BASE_HI |
5352 | #define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 |
5353 | #define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
5354 | //SDMA1_RLC7_RB_RPTR |
5355 | #define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 |
5356 | #define SDMA1_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
5357 | //SDMA1_RLC7_RB_RPTR_HI |
5358 | #define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
5359 | #define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
5360 | //SDMA1_RLC7_RB_WPTR |
5361 | #define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 |
5362 | #define SDMA1_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
5363 | //SDMA1_RLC7_RB_WPTR_HI |
5364 | #define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
5365 | #define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
5366 | //SDMA1_RLC7_RB_WPTR_POLL_CNTL |
5367 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
5368 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
5369 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
5370 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
5371 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
5372 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
5373 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
5374 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
5375 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
5376 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
5377 | //SDMA1_RLC7_RB_RPTR_ADDR_HI |
5378 | #define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
5379 | #define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5380 | //SDMA1_RLC7_RB_RPTR_ADDR_LO |
5381 | #define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
5382 | #define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5383 | //SDMA1_RLC7_IB_CNTL |
5384 | #define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
5385 | #define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
5386 | #define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
5387 | #define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 |
5388 | #define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
5389 | #define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
5390 | #define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
5391 | #define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
5392 | //SDMA1_RLC7_IB_RPTR |
5393 | #define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 |
5394 | #define SDMA1_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
5395 | //SDMA1_RLC7_IB_OFFSET |
5396 | #define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 |
5397 | #define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
5398 | //SDMA1_RLC7_IB_BASE_LO |
5399 | #define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 |
5400 | #define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
5401 | //SDMA1_RLC7_IB_BASE_HI |
5402 | #define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 |
5403 | #define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
5404 | //SDMA1_RLC7_IB_SIZE |
5405 | #define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT 0x0 |
5406 | #define SDMA1_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL |
5407 | //SDMA1_RLC7_SKIP_CNTL |
5408 | #define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
5409 | #define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
5410 | //SDMA1_RLC7_CONTEXT_STATUS |
5411 | #define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
5412 | #define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
5413 | #define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
5414 | #define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
5415 | #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
5416 | #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
5417 | #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
5418 | #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
5419 | #define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
5420 | #define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
5421 | #define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
5422 | #define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
5423 | #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
5424 | #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
5425 | #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
5426 | #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
5427 | //SDMA1_RLC7_DOORBELL |
5428 | #define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT 0x1c |
5429 | #define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e |
5430 | #define SDMA1_RLC7_DOORBELL__ENABLE_MASK 0x10000000L |
5431 | #define SDMA1_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L |
5432 | //SDMA1_RLC7_STATUS |
5433 | #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
5434 | #define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
5435 | #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
5436 | #define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
5437 | //SDMA1_RLC7_DOORBELL_LOG |
5438 | //SDMA1_RLC7_WATERMARK |
5439 | #define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
5440 | #define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
5441 | #define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
5442 | #define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
5443 | //SDMA1_RLC7_DOORBELL_OFFSET |
5444 | #define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
5445 | #define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
5446 | //SDMA1_RLC7_CSA_ADDR_LO |
5447 | #define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
5448 | #define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5449 | //SDMA1_RLC7_CSA_ADDR_HI |
5450 | #define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
5451 | #define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5452 | //SDMA1_RLC7_IB_SUB_REMAIN |
5453 | #define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
5454 | #define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
5455 | //SDMA1_RLC7_PREEMPT |
5456 | #define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
5457 | #define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
5458 | //SDMA1_RLC7_DUMMY_REG |
5459 | #define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 |
5460 | #define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
5461 | //SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI |
5462 | #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
5463 | #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5464 | //SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO |
5465 | #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
5466 | #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5467 | //SDMA1_RLC7_RB_AQL_CNTL |
5468 | #define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
5469 | #define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
5470 | #define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
5471 | #define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
5472 | #define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
5473 | #define SDMA1_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
5474 | #define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
5475 | #define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
5476 | #define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
5477 | #define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
5478 | #define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
5479 | #define SDMA1_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
5480 | //SDMA1_RLC7_MINOR_PTR_UPDATE |
5481 | #define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
5482 | #define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
5483 | //SDMA1_RLC7_MIDCMD_DATA0 |
5484 | #define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
5485 | #define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
5486 | //SDMA1_RLC7_MIDCMD_DATA1 |
5487 | #define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
5488 | #define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
5489 | //SDMA1_RLC7_MIDCMD_DATA2 |
5490 | #define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
5491 | #define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
5492 | //SDMA1_RLC7_MIDCMD_DATA3 |
5493 | #define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
5494 | #define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
5495 | //SDMA1_RLC7_MIDCMD_DATA4 |
5496 | #define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
5497 | #define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
5498 | //SDMA1_RLC7_MIDCMD_DATA5 |
5499 | #define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
5500 | #define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
5501 | //SDMA1_RLC7_MIDCMD_DATA6 |
5502 | #define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
5503 | #define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
5504 | //SDMA1_RLC7_MIDCMD_DATA7 |
5505 | #define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
5506 | #define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
5507 | //SDMA1_RLC7_MIDCMD_DATA8 |
5508 | #define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
5509 | #define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
5510 | //SDMA1_RLC7_MIDCMD_CNTL |
5511 | #define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
5512 | #define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
5513 | #define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
5514 | #define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
5515 | #define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
5516 | #define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
5517 | #define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
5518 | #define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
5519 | |
5520 | |
5521 | // addressBlock: gc_grbmdec |
5522 | //GRBM_CNTL |
5523 | #define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 |
5524 | #define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f |
5525 | #define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL |
5526 | #define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L |
5527 | //GRBM_SKEW_CNTL |
5528 | #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 |
5529 | #define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 |
5530 | #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL |
5531 | #define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L |
5532 | //GRBM_STATUS2 |
5533 | #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 |
5534 | #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 |
5535 | #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 |
5536 | #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 |
5537 | #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 |
5538 | #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 |
5539 | #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 |
5540 | #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa |
5541 | #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb |
5542 | #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc |
5543 | #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd |
5544 | #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe |
5545 | #define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf |
5546 | #define GRBM_STATUS2__EA_BUSY__SHIFT 0x10 |
5547 | #define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11 |
5548 | #define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 |
5549 | #define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13 |
5550 | #define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14 |
5551 | #define GRBM_STATUS2__SDMA_BUSY__SHIFT 0x15 |
5552 | #define GRBM_STATUS2__SDMA0_RQ_PENDING__SHIFT 0x16 |
5553 | #define GRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x17 |
5554 | #define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 |
5555 | #define GRBM_STATUS2__TCP_BUSY__SHIFT 0x19 |
5556 | #define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c |
5557 | #define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d |
5558 | #define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e |
5559 | #define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f |
5560 | #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL |
5561 | #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L |
5562 | #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L |
5563 | #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L |
5564 | #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L |
5565 | #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L |
5566 | #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L |
5567 | #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L |
5568 | #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L |
5569 | #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L |
5570 | #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L |
5571 | #define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L |
5572 | #define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L |
5573 | #define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L |
5574 | #define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L |
5575 | #define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L |
5576 | #define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L |
5577 | #define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L |
5578 | #define GRBM_STATUS2__SDMA_BUSY_MASK 0x00200000L |
5579 | #define GRBM_STATUS2__SDMA0_RQ_PENDING_MASK 0x00400000L |
5580 | #define GRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x00800000L |
5581 | #define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L |
5582 | #define GRBM_STATUS2__TCP_BUSY_MASK 0x02000000L |
5583 | #define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L |
5584 | #define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L |
5585 | #define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L |
5586 | #define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L |
5587 | //GRBM_PWR_CNTL |
5588 | #define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 |
5589 | #define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 |
5590 | #define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 |
5591 | #define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 |
5592 | #define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe |
5593 | #define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf |
5594 | #define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L |
5595 | #define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL |
5596 | #define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L |
5597 | #define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L |
5598 | #define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L |
5599 | #define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L |
5600 | //GRBM_STATUS |
5601 | #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 |
5602 | #define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5 |
5603 | #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 |
5604 | #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 |
5605 | #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 |
5606 | #define GRBM_STATUS__DB_CLEAN__SHIFT 0xc |
5607 | #define GRBM_STATUS__CB_CLEAN__SHIFT 0xd |
5608 | #define GRBM_STATUS__TA_BUSY__SHIFT 0xe |
5609 | #define GRBM_STATUS__GDS_BUSY__SHIFT 0xf |
5610 | #define GRBM_STATUS__GE_BUSY_NO_DMA__SHIFT 0x10 |
5611 | #define GRBM_STATUS__SX_BUSY__SHIFT 0x14 |
5612 | #define GRBM_STATUS__GE_BUSY__SHIFT 0x15 |
5613 | #define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 |
5614 | #define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 |
5615 | #define GRBM_STATUS__SC_BUSY__SHIFT 0x18 |
5616 | #define GRBM_STATUS__PA_BUSY__SHIFT 0x19 |
5617 | #define GRBM_STATUS__DB_BUSY__SHIFT 0x1a |
5618 | #define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c |
5619 | #define GRBM_STATUS__CP_BUSY__SHIFT 0x1d |
5620 | #define GRBM_STATUS__CB_BUSY__SHIFT 0x1e |
5621 | #define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f |
5622 | #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL |
5623 | #define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L |
5624 | #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L |
5625 | #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L |
5626 | #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L |
5627 | #define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L |
5628 | #define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L |
5629 | #define GRBM_STATUS__TA_BUSY_MASK 0x00004000L |
5630 | #define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L |
5631 | #define GRBM_STATUS__GE_BUSY_NO_DMA_MASK 0x00010000L |
5632 | #define GRBM_STATUS__SX_BUSY_MASK 0x00100000L |
5633 | #define GRBM_STATUS__GE_BUSY_MASK 0x00200000L |
5634 | #define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L |
5635 | #define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L |
5636 | #define GRBM_STATUS__SC_BUSY_MASK 0x01000000L |
5637 | #define GRBM_STATUS__PA_BUSY_MASK 0x02000000L |
5638 | #define GRBM_STATUS__DB_BUSY_MASK 0x04000000L |
5639 | #define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L |
5640 | #define GRBM_STATUS__CP_BUSY_MASK 0x20000000L |
5641 | #define GRBM_STATUS__CB_BUSY_MASK 0x40000000L |
5642 | #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L |
5643 | //GRBM_STATUS_SE0 |
5644 | #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 |
5645 | #define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 |
5646 | #define GRBM_STATUS_SE0__UTCL1_BUSY__SHIFT 0x3 |
5647 | #define GRBM_STATUS_SE0__TCP_BUSY__SHIFT 0x4 |
5648 | #define GRBM_STATUS_SE0__GL1CC_BUSY__SHIFT 0x5 |
5649 | #define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15 |
5650 | #define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 |
5651 | #define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 |
5652 | #define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 |
5653 | #define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a |
5654 | #define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b |
5655 | #define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d |
5656 | #define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e |
5657 | #define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f |
5658 | #define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L |
5659 | #define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L |
5660 | #define GRBM_STATUS_SE0__UTCL1_BUSY_MASK 0x00000008L |
5661 | #define GRBM_STATUS_SE0__TCP_BUSY_MASK 0x00000010L |
5662 | #define GRBM_STATUS_SE0__GL1CC_BUSY_MASK 0x00000020L |
5663 | #define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L |
5664 | #define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L |
5665 | #define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L |
5666 | #define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L |
5667 | #define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L |
5668 | #define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L |
5669 | #define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L |
5670 | #define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L |
5671 | #define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L |
5672 | //GRBM_STATUS_SE1 |
5673 | #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 |
5674 | #define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 |
5675 | #define GRBM_STATUS_SE1__UTCL1_BUSY__SHIFT 0x3 |
5676 | #define GRBM_STATUS_SE1__TCP_BUSY__SHIFT 0x4 |
5677 | #define GRBM_STATUS_SE1__GL1CC_BUSY__SHIFT 0x5 |
5678 | #define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15 |
5679 | #define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 |
5680 | #define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 |
5681 | #define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 |
5682 | #define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a |
5683 | #define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b |
5684 | #define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d |
5685 | #define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e |
5686 | #define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f |
5687 | #define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L |
5688 | #define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L |
5689 | #define GRBM_STATUS_SE1__UTCL1_BUSY_MASK 0x00000008L |
5690 | #define GRBM_STATUS_SE1__TCP_BUSY_MASK 0x00000010L |
5691 | #define GRBM_STATUS_SE1__GL1CC_BUSY_MASK 0x00000020L |
5692 | #define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L |
5693 | #define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L |
5694 | #define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L |
5695 | #define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L |
5696 | #define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L |
5697 | #define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L |
5698 | #define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L |
5699 | #define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L |
5700 | #define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L |
5701 | //GRBM_STATUS3 |
5702 | #define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING__SHIFT 0x5 |
5703 | #define GRBM_STATUS3__GRBM_UTCL2_INTR_CREDIT_PENDING__SHIFT 0x6 |
5704 | #define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING__SHIFT 0x7 |
5705 | #define GRBM_STATUS3__MESPIPE0_RQ_PENDING__SHIFT 0x8 |
5706 | #define GRBM_STATUS3__MESPIPE1_RQ_PENDING__SHIFT 0x9 |
5707 | #define GRBM_STATUS3__MESPIPE2_RQ_PENDING__SHIFT 0xa |
5708 | #define GRBM_STATUS3__MESPIPE3_RQ_PENDING__SHIFT 0xb |
5709 | #define GRBM_STATUS3__PH_BUSY__SHIFT 0xd |
5710 | #define GRBM_STATUS3__CH_BUSY__SHIFT 0xe |
5711 | #define GRBM_STATUS3__GL2CC_BUSY__SHIFT 0xf |
5712 | #define GRBM_STATUS3__GL1CC_BUSY__SHIFT 0x10 |
5713 | #define GRBM_STATUS3__GUS_LINK_BUSY__SHIFT 0x1c |
5714 | #define GRBM_STATUS3__GUS_BUSY__SHIFT 0x1d |
5715 | #define GRBM_STATUS3__UTCL1_BUSY__SHIFT 0x1e |
5716 | #define GRBM_STATUS3__PMM_BUSY__SHIFT 0x1f |
5717 | #define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING_MASK 0x00000020L |
5718 | #define GRBM_STATUS3__GRBM_UTCL2_INTR_CREDIT_PENDING_MASK 0x00000040L |
5719 | #define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING_MASK 0x00000080L |
5720 | #define GRBM_STATUS3__MESPIPE0_RQ_PENDING_MASK 0x00000100L |
5721 | #define GRBM_STATUS3__MESPIPE1_RQ_PENDING_MASK 0x00000200L |
5722 | #define GRBM_STATUS3__MESPIPE2_RQ_PENDING_MASK 0x00000400L |
5723 | #define GRBM_STATUS3__MESPIPE3_RQ_PENDING_MASK 0x00000800L |
5724 | #define GRBM_STATUS3__PH_BUSY_MASK 0x00002000L |
5725 | #define GRBM_STATUS3__CH_BUSY_MASK 0x00004000L |
5726 | #define GRBM_STATUS3__GL2CC_BUSY_MASK 0x00008000L |
5727 | #define GRBM_STATUS3__GL1CC_BUSY_MASK 0x00010000L |
5728 | #define GRBM_STATUS3__GUS_LINK_BUSY_MASK 0x10000000L |
5729 | #define GRBM_STATUS3__GUS_BUSY_MASK 0x20000000L |
5730 | #define GRBM_STATUS3__UTCL1_BUSY_MASK 0x40000000L |
5731 | #define GRBM_STATUS3__PMM_BUSY_MASK 0x80000000L |
5732 | //GRBM_SOFT_RESET |
5733 | #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 |
5734 | #define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 |
5735 | #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 |
5736 | #define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 |
5737 | #define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 |
5738 | #define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 |
5739 | #define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 |
5740 | #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15 |
5741 | #define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 |
5742 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT 0x17 |
5743 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x18 |
5744 | #define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L |
5745 | #define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L |
5746 | #define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L |
5747 | #define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L |
5748 | #define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L |
5749 | #define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L |
5750 | #define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L |
5751 | #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L |
5752 | #define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L |
5753 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK 0x00800000L |
5754 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x01000000L |
5755 | //GRBM_GFX_CLKEN_CNTL |
5756 | #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 |
5757 | #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 |
5758 | #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL |
5759 | #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L |
5760 | //GRBM_WAIT_IDLE_CLOCKS |
5761 | #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 |
5762 | #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL |
5763 | //GRBM_STATUS_SE2 |
5764 | #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 |
5765 | #define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 |
5766 | #define GRBM_STATUS_SE2__UTCL1_BUSY__SHIFT 0x3 |
5767 | #define GRBM_STATUS_SE2__TCP_BUSY__SHIFT 0x4 |
5768 | #define GRBM_STATUS_SE2__GL1CC_BUSY__SHIFT 0x5 |
5769 | #define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15 |
5770 | #define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 |
5771 | #define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 |
5772 | #define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 |
5773 | #define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a |
5774 | #define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b |
5775 | #define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d |
5776 | #define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e |
5777 | #define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f |
5778 | #define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L |
5779 | #define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L |
5780 | #define GRBM_STATUS_SE2__UTCL1_BUSY_MASK 0x00000008L |
5781 | #define GRBM_STATUS_SE2__TCP_BUSY_MASK 0x00000010L |
5782 | #define GRBM_STATUS_SE2__GL1CC_BUSY_MASK 0x00000020L |
5783 | #define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L |
5784 | #define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L |
5785 | #define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L |
5786 | #define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L |
5787 | #define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L |
5788 | #define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L |
5789 | #define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L |
5790 | #define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L |
5791 | #define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L |
5792 | //GRBM_STATUS_SE3 |
5793 | #define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 |
5794 | #define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 |
5795 | #define GRBM_STATUS_SE3__UTCL1_BUSY__SHIFT 0x3 |
5796 | #define GRBM_STATUS_SE3__TCP_BUSY__SHIFT 0x4 |
5797 | #define GRBM_STATUS_SE3__GL1CC_BUSY__SHIFT 0x5 |
5798 | #define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15 |
5799 | #define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 |
5800 | #define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 |
5801 | #define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 |
5802 | #define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a |
5803 | #define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b |
5804 | #define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d |
5805 | #define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e |
5806 | #define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f |
5807 | #define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L |
5808 | #define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L |
5809 | #define GRBM_STATUS_SE3__UTCL1_BUSY_MASK 0x00000008L |
5810 | #define GRBM_STATUS_SE3__TCP_BUSY_MASK 0x00000010L |
5811 | #define GRBM_STATUS_SE3__GL1CC_BUSY_MASK 0x00000020L |
5812 | #define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L |
5813 | #define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L |
5814 | #define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L |
5815 | #define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L |
5816 | #define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L |
5817 | #define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L |
5818 | #define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L |
5819 | #define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L |
5820 | #define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L |
5821 | //GRBM_PM_CNTL |
5822 | #define GRBM_PM_CNTL__PM_READY__SHIFT 0x0 |
5823 | #define GRBM_PM_CNTL__PM_START__SHIFT 0x10 |
5824 | #define GRBM_PM_CNTL__PM_READY_MASK 0x00000001L |
5825 | #define GRBM_PM_CNTL__PM_START_MASK 0x00010000L |
5826 | //GRBM_READ_ERROR |
5827 | #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 |
5828 | #define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 |
5829 | #define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 |
5830 | #define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f |
5831 | #define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL |
5832 | #define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L |
5833 | #define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L |
5834 | #define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L |
5835 | //GRBM_READ_ERROR2 |
5836 | #define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10 |
5837 | #define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11 |
5838 | #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 |
5839 | #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 |
5840 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 |
5841 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 |
5842 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 |
5843 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 |
5844 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 |
5845 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 |
5846 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a |
5847 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b |
5848 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c |
5849 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d |
5850 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e |
5851 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f |
5852 | #define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L |
5853 | #define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L |
5854 | #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L |
5855 | #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L |
5856 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L |
5857 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L |
5858 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L |
5859 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L |
5860 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L |
5861 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L |
5862 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L |
5863 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L |
5864 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L |
5865 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L |
5866 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L |
5867 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L |
5868 | //GRBM_INT_CNTL |
5869 | #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 |
5870 | #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 |
5871 | #define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L |
5872 | #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L |
5873 | //GRBM_TRAP_OP |
5874 | #define GRBM_TRAP_OP__RW__SHIFT 0x0 |
5875 | #define GRBM_TRAP_OP__RW_MASK 0x00000001L |
5876 | //GRBM_TRAP_ADDR |
5877 | #define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 |
5878 | #define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL |
5879 | //GRBM_TRAP_ADDR_MSK |
5880 | #define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 |
5881 | #define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL |
5882 | //GRBM_TRAP_WD |
5883 | #define GRBM_TRAP_WD__DATA__SHIFT 0x0 |
5884 | #define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL |
5885 | //GRBM_TRAP_WD_MSK |
5886 | #define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 |
5887 | #define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL |
5888 | //GRBM_DSM_BYPASS |
5889 | #define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 |
5890 | #define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 |
5891 | #define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L |
5892 | #define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L |
5893 | //GRBM_WRITE_ERROR |
5894 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 |
5895 | #define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 |
5896 | #define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 |
5897 | #define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc |
5898 | #define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd |
5899 | #define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 |
5900 | #define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 |
5901 | #define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f |
5902 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L |
5903 | #define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL |
5904 | #define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000007E0L |
5905 | #define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L |
5906 | #define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L |
5907 | #define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L |
5908 | #define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L |
5909 | #define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L |
5910 | //GRBM_IOV_ERROR |
5911 | #define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2 |
5912 | #define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14 |
5913 | #define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a |
5914 | #define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b |
5915 | #define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f |
5916 | #define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL |
5917 | #define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L |
5918 | #define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L |
5919 | #define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L |
5920 | #define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L |
5921 | //GRBM_CHIP_REVISION |
5922 | #define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 |
5923 | #define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL |
5924 | //GRBM_GFX_CNTL |
5925 | #define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 |
5926 | #define GRBM_GFX_CNTL__MEID__SHIFT 0x2 |
5927 | #define GRBM_GFX_CNTL__VMID__SHIFT 0x4 |
5928 | #define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 |
5929 | #define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L |
5930 | #define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL |
5931 | #define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L |
5932 | #define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L |
5933 | //GRBM_IH_CREDIT |
5934 | #define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 |
5935 | #define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 |
5936 | #define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L |
5937 | #define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L |
5938 | //GRBM_PWR_CNTL2 |
5939 | #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 |
5940 | #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 |
5941 | #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L |
5942 | #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L |
5943 | //GRBM_UTCL2_INVAL_RANGE_START |
5944 | #define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 |
5945 | #define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL |
5946 | //GRBM_UTCL2_INVAL_RANGE_END |
5947 | #define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 |
5948 | #define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL |
5949 | //GRBM_IOV_READ_ERROR |
5950 | #define GRBM_IOV_READ_ERROR__IOV_ADDR__SHIFT 0x2 |
5951 | #define GRBM_IOV_READ_ERROR__IOV_VFID__SHIFT 0x14 |
5952 | #define GRBM_IOV_READ_ERROR__IOV_VF__SHIFT 0x1a |
5953 | #define GRBM_IOV_READ_ERROR__IOV_OP__SHIFT 0x1b |
5954 | #define GRBM_IOV_READ_ERROR__IOV_ERROR__SHIFT 0x1f |
5955 | #define GRBM_IOV_READ_ERROR__IOV_ADDR_MASK 0x000FFFFCL |
5956 | #define GRBM_IOV_READ_ERROR__IOV_VFID_MASK 0x03F00000L |
5957 | #define GRBM_IOV_READ_ERROR__IOV_VF_MASK 0x04000000L |
5958 | #define GRBM_IOV_READ_ERROR__IOV_OP_MASK 0x08000000L |
5959 | #define GRBM_IOV_READ_ERROR__IOV_ERROR_MASK 0x80000000L |
5960 | //GRBM_FENCE_RANGE0 |
5961 | #define GRBM_FENCE_RANGE0__START__SHIFT 0x0 |
5962 | #define GRBM_FENCE_RANGE0__END__SHIFT 0x10 |
5963 | #define GRBM_FENCE_RANGE0__START_MASK 0x0000FFFFL |
5964 | #define GRBM_FENCE_RANGE0__END_MASK 0xFFFF0000L |
5965 | //GRBM_FENCE_RANGE1 |
5966 | #define GRBM_FENCE_RANGE1__START__SHIFT 0x0 |
5967 | #define GRBM_FENCE_RANGE1__END__SHIFT 0x10 |
5968 | #define GRBM_FENCE_RANGE1__START_MASK 0x0000FFFFL |
5969 | #define GRBM_FENCE_RANGE1__END_MASK 0xFFFF0000L |
5970 | //GRBM_NOWHERE |
5971 | #define GRBM_NOWHERE__DATA__SHIFT 0x0 |
5972 | #define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL |
5973 | //GRBM_SCRATCH_REG0 |
5974 | #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 |
5975 | #define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL |
5976 | //GRBM_SCRATCH_REG1 |
5977 | #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 |
5978 | #define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL |
5979 | //GRBM_SCRATCH_REG2 |
5980 | #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 |
5981 | #define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL |
5982 | //GRBM_SCRATCH_REG3 |
5983 | #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 |
5984 | #define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL |
5985 | //GRBM_SCRATCH_REG4 |
5986 | #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 |
5987 | #define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL |
5988 | //GRBM_SCRATCH_REG5 |
5989 | #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 |
5990 | #define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL |
5991 | //GRBM_SCRATCH_REG6 |
5992 | #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 |
5993 | #define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL |
5994 | //GRBM_SCRATCH_REG7 |
5995 | #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 |
5996 | #define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL |
5997 | |
5998 | |
5999 | // addressBlock: gc_cpdec |
6000 | //CP_CPC_STATUS |
6001 | #define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 |
6002 | #define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 |
6003 | #define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 |
6004 | #define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 |
6005 | #define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 |
6006 | #define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 |
6007 | #define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 |
6008 | #define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 |
6009 | #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa |
6010 | #define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb |
6011 | #define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc |
6012 | #define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd |
6013 | #define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe |
6014 | #define CP_CPC_STATUS__GCRIU_BUSY__SHIFT 0xf |
6015 | #define CP_CPC_STATUS__MES_BUSY__SHIFT 0x10 |
6016 | #define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY__SHIFT 0x11 |
6017 | #define CP_CPC_STATUS__RCIU3_BUSY__SHIFT 0x12 |
6018 | #define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY__SHIFT 0x13 |
6019 | #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d |
6020 | #define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e |
6021 | #define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f |
6022 | #define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L |
6023 | #define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L |
6024 | #define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L |
6025 | #define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L |
6026 | #define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L |
6027 | #define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L |
6028 | #define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L |
6029 | #define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L |
6030 | #define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L |
6031 | #define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L |
6032 | #define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L |
6033 | #define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L |
6034 | #define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L |
6035 | #define CP_CPC_STATUS__GCRIU_BUSY_MASK 0x00008000L |
6036 | #define CP_CPC_STATUS__MES_BUSY_MASK 0x00010000L |
6037 | #define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY_MASK 0x00020000L |
6038 | #define CP_CPC_STATUS__RCIU3_BUSY_MASK 0x00040000L |
6039 | #define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY_MASK 0x00080000L |
6040 | #define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L |
6041 | #define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L |
6042 | #define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L |
6043 | //CP_CPC_BUSY_STAT |
6044 | #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 |
6045 | #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 |
6046 | #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 |
6047 | #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 |
6048 | #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 |
6049 | #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 |
6050 | #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 |
6051 | #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 |
6052 | #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 |
6053 | #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 |
6054 | #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa |
6055 | #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb |
6056 | #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc |
6057 | #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd |
6058 | #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 |
6059 | #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 |
6060 | #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 |
6061 | #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 |
6062 | #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 |
6063 | #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 |
6064 | #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 |
6065 | #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 |
6066 | #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 |
6067 | #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 |
6068 | #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a |
6069 | #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b |
6070 | #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c |
6071 | #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d |
6072 | #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L |
6073 | #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L |
6074 | #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L |
6075 | #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L |
6076 | #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L |
6077 | #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L |
6078 | #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L |
6079 | #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L |
6080 | #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L |
6081 | #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L |
6082 | #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L |
6083 | #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L |
6084 | #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L |
6085 | #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L |
6086 | #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L |
6087 | #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L |
6088 | #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L |
6089 | #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L |
6090 | #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L |
6091 | #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L |
6092 | #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L |
6093 | #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L |
6094 | #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L |
6095 | #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L |
6096 | #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L |
6097 | #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L |
6098 | #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L |
6099 | #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L |
6100 | //CP_CPC_STALLED_STAT1 |
6101 | #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 |
6102 | #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 |
6103 | #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 |
6104 | #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 |
6105 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 |
6106 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa |
6107 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd |
6108 | #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 |
6109 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 |
6110 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 |
6111 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 |
6112 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 |
6113 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 |
6114 | #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 |
6115 | #define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE__SHIFT 0x19 |
6116 | #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L |
6117 | #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L |
6118 | #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L |
6119 | #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L |
6120 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L |
6121 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L |
6122 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L |
6123 | #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L |
6124 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L |
6125 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L |
6126 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L |
6127 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L |
6128 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L |
6129 | #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L |
6130 | #define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE_MASK 0x02000000L |
6131 | //CP_CPF_STATUS |
6132 | #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 |
6133 | #define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 |
6134 | #define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 |
6135 | #define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 |
6136 | #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 |
6137 | #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 |
6138 | #define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 |
6139 | #define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 |
6140 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa |
6141 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb |
6142 | #define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc |
6143 | #define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd |
6144 | #define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe |
6145 | #define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf |
6146 | #define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 |
6147 | #define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 |
6148 | #define CP_CPF_STATUS__RCIU_BUSY__SHIFT 0x12 |
6149 | #define CP_CPF_STATUS__RCIU_GFX_BUSY__SHIFT 0x13 |
6150 | #define CP_CPF_STATUS__RCIU_CMP_BUSY__SHIFT 0x14 |
6151 | #define CP_CPF_STATUS__ROQ_DATA_BUSY__SHIFT 0x15 |
6152 | #define CP_CPF_STATUS__ROQ_CE_DATA_BUSY__SHIFT 0x16 |
6153 | #define CP_CPF_STATUS__GCRIU_BUSY__SHIFT 0x17 |
6154 | #define CP_CPF_STATUS__MES_HQD_BUSY__SHIFT 0x18 |
6155 | #define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a |
6156 | #define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b |
6157 | #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c |
6158 | #define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e |
6159 | #define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f |
6160 | #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L |
6161 | #define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L |
6162 | #define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L |
6163 | #define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L |
6164 | #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L |
6165 | #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L |
6166 | #define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L |
6167 | #define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L |
6168 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L |
6169 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L |
6170 | #define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L |
6171 | #define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L |
6172 | #define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L |
6173 | #define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L |
6174 | #define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L |
6175 | #define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L |
6176 | #define CP_CPF_STATUS__RCIU_BUSY_MASK 0x00040000L |
6177 | #define CP_CPF_STATUS__RCIU_GFX_BUSY_MASK 0x00080000L |
6178 | #define CP_CPF_STATUS__RCIU_CMP_BUSY_MASK 0x00100000L |
6179 | #define CP_CPF_STATUS__ROQ_DATA_BUSY_MASK 0x00200000L |
6180 | #define CP_CPF_STATUS__ROQ_CE_DATA_BUSY_MASK 0x00400000L |
6181 | #define CP_CPF_STATUS__GCRIU_BUSY_MASK 0x00800000L |
6182 | #define CP_CPF_STATUS__MES_HQD_BUSY_MASK 0x01000000L |
6183 | #define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L |
6184 | #define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L |
6185 | #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L |
6186 | #define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L |
6187 | #define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L |
6188 | //CP_CPF_BUSY_STAT |
6189 | #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 |
6190 | #define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 |
6191 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 |
6192 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 |
6193 | #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 |
6194 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 |
6195 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 |
6196 | #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 |
6197 | #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 |
6198 | #define CP_CPF_BUSY_STAT__CSF_DATA_BUSY__SHIFT 0x9 |
6199 | #define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY__SHIFT 0xa |
6200 | #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb |
6201 | #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc |
6202 | #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd |
6203 | #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe |
6204 | #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf |
6205 | #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 |
6206 | #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 |
6207 | #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 |
6208 | #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 |
6209 | #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 |
6210 | #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 |
6211 | #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 |
6212 | #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 |
6213 | #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 |
6214 | #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 |
6215 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a |
6216 | #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b |
6217 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c |
6218 | #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d |
6219 | #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e |
6220 | #define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f |
6221 | #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L |
6222 | #define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L |
6223 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L |
6224 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L |
6225 | #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L |
6226 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L |
6227 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L |
6228 | #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L |
6229 | #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L |
6230 | #define CP_CPF_BUSY_STAT__CSF_DATA_BUSY_MASK 0x00000200L |
6231 | #define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY_MASK 0x00000400L |
6232 | #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L |
6233 | #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L |
6234 | #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L |
6235 | #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L |
6236 | #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L |
6237 | #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L |
6238 | #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L |
6239 | #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L |
6240 | #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L |
6241 | #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L |
6242 | #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L |
6243 | #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L |
6244 | #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L |
6245 | #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L |
6246 | #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L |
6247 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L |
6248 | #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L |
6249 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L |
6250 | #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L |
6251 | #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L |
6252 | #define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L |
6253 | //CP_CPF_STALLED_STAT1 |
6254 | #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 |
6255 | #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 |
6256 | #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 |
6257 | #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 |
6258 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 |
6259 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 |
6260 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 |
6261 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 |
6262 | #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 |
6263 | #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa |
6264 | #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb |
6265 | #define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA__SHIFT 0xc |
6266 | #define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE__SHIFT 0xd |
6267 | #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L |
6268 | #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L |
6269 | #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L |
6270 | #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L |
6271 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L |
6272 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L |
6273 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L |
6274 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L |
6275 | #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L |
6276 | #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L |
6277 | #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L |
6278 | #define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA_MASK 0x00001000L |
6279 | #define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE_MASK 0x00002000L |
6280 | //CP_CPC_BUSY_STAT2 |
6281 | #define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY__SHIFT 0x0 |
6282 | #define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY__SHIFT 0x2 |
6283 | #define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY__SHIFT 0x3 |
6284 | #define CP_CPC_BUSY_STAT2__MES_TC_BUSY__SHIFT 0x7 |
6285 | #define CP_CPC_BUSY_STAT2__MES_DMA_BUSY__SHIFT 0x8 |
6286 | #define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT 0xa |
6287 | #define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY__SHIFT 0xb |
6288 | #define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY__SHIFT 0xc |
6289 | #define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY__SHIFT 0xd |
6290 | #define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY_MASK 0x00000001L |
6291 | #define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY_MASK 0x00000004L |
6292 | #define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY_MASK 0x00000008L |
6293 | #define CP_CPC_BUSY_STAT2__MES_TC_BUSY_MASK 0x00000080L |
6294 | #define CP_CPC_BUSY_STAT2__MES_DMA_BUSY_MASK 0x00000100L |
6295 | #define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY_MASK 0x00000400L |
6296 | #define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY_MASK 0x00000800L |
6297 | #define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY_MASK 0x00001000L |
6298 | #define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY_MASK 0x00002000L |
6299 | //CP_CPC_GRBM_FREE_COUNT |
6300 | #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
6301 | #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL |
6302 | //CP_MEC_CNTL |
6303 | #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 |
6304 | #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 |
6305 | #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 |
6306 | #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 |
6307 | #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 |
6308 | #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 |
6309 | #define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET__SHIFT 0x16 |
6310 | #define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET__SHIFT 0x17 |
6311 | #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x1b |
6312 | #define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c |
6313 | #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d |
6314 | #define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e |
6315 | #define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f |
6316 | #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L |
6317 | #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L |
6318 | #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L |
6319 | #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L |
6320 | #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L |
6321 | #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L |
6322 | #define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET_MASK 0x00400000L |
6323 | #define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET_MASK 0x00800000L |
6324 | #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x08000000L |
6325 | #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L |
6326 | #define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L |
6327 | #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L |
6328 | #define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L |
6329 | //CP_MEC_ME1_HEADER_DUMP |
6330 | #define 0x0 |
6331 | #define 0xFFFFFFFFL |
6332 | //CP_MEC_ME2_HEADER_DUMP |
6333 | #define 0x0 |
6334 | #define 0xFFFFFFFFL |
6335 | //CP_CPC_SCRATCH_INDEX |
6336 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 |
6337 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f |
6338 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL |
6339 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L |
6340 | //CP_CPC_SCRATCH_DATA |
6341 | #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 |
6342 | #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL |
6343 | //CP_CPF_GRBM_FREE_COUNT |
6344 | #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
6345 | #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L |
6346 | //CP_CPF_BUSY_STAT2 |
6347 | #define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY__SHIFT 0xc |
6348 | #define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe |
6349 | #define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY__SHIFT 0x11 |
6350 | #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY__SHIFT 0x12 |
6351 | #define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 |
6352 | #define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY__SHIFT 0x17 |
6353 | #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 |
6354 | #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY__SHIFT 0x1b |
6355 | #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY__SHIFT 0x1e |
6356 | #define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY_MASK 0x00001000L |
6357 | #define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L |
6358 | #define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY_MASK 0x00020000L |
6359 | #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY_MASK 0x00040000L |
6360 | #define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L |
6361 | #define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY_MASK 0x00800000L |
6362 | #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L |
6363 | #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY_MASK 0x08000000L |
6364 | #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY_MASK 0x40000000L |
6365 | //CP_CPC_HALT_HYST_COUNT |
6366 | #define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 |
6367 | #define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL |
6368 | //CP_CE_COMPARE_COUNT |
6369 | #define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 |
6370 | #define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL |
6371 | //CP_CE_DE_COUNT |
6372 | #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 |
6373 | #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL |
6374 | //CP_DE_CE_COUNT |
6375 | #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 |
6376 | #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL |
6377 | //CP_DE_LAST_INVAL_COUNT |
6378 | #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 |
6379 | #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL |
6380 | //CP_DE_DE_COUNT |
6381 | #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 |
6382 | #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL |
6383 | //CP_STALLED_STAT3 |
6384 | #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 |
6385 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 |
6386 | #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 |
6387 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 |
6388 | #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 |
6389 | #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 |
6390 | #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 |
6391 | #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 |
6392 | #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa |
6393 | #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb |
6394 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc |
6395 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd |
6396 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe |
6397 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf |
6398 | #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 |
6399 | #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 |
6400 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 |
6401 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 |
6402 | #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 |
6403 | #define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE__SHIFT 0x15 |
6404 | #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L |
6405 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L |
6406 | #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L |
6407 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L |
6408 | #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L |
6409 | #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L |
6410 | #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L |
6411 | #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L |
6412 | #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L |
6413 | #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L |
6414 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L |
6415 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L |
6416 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L |
6417 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L |
6418 | #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L |
6419 | #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L |
6420 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L |
6421 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L |
6422 | #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L |
6423 | #define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE_MASK 0x00200000L |
6424 | //CP_STALLED_STAT1 |
6425 | #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 |
6426 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 |
6427 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 |
6428 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa |
6429 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb |
6430 | #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc |
6431 | #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd |
6432 | #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe |
6433 | #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf |
6434 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 |
6435 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 |
6436 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 |
6437 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a |
6438 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b |
6439 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c |
6440 | #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d |
6441 | #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L |
6442 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L |
6443 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L |
6444 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L |
6445 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L |
6446 | #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L |
6447 | #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L |
6448 | #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L |
6449 | #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L |
6450 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L |
6451 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L |
6452 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L |
6453 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L |
6454 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L |
6455 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L |
6456 | #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L |
6457 | //CP_STALLED_STAT2 |
6458 | #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 |
6459 | #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 |
6460 | #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 |
6461 | #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 |
6462 | #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 |
6463 | #define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV__SHIFT 0x6 |
6464 | #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 |
6465 | #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 |
6466 | #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa |
6467 | #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb |
6468 | #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc |
6469 | #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd |
6470 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe |
6471 | #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf |
6472 | #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 |
6473 | #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 |
6474 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 |
6475 | #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 |
6476 | #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 |
6477 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 |
6478 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 |
6479 | #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 |
6480 | #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 |
6481 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 |
6482 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a |
6483 | #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b |
6484 | #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c |
6485 | #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d |
6486 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e |
6487 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f |
6488 | #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L |
6489 | #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L |
6490 | #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L |
6491 | #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L |
6492 | #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L |
6493 | #define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV_MASK 0x00000040L |
6494 | #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L |
6495 | #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L |
6496 | #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L |
6497 | #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L |
6498 | #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L |
6499 | #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L |
6500 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L |
6501 | #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L |
6502 | #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L |
6503 | #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L |
6504 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L |
6505 | #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L |
6506 | #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L |
6507 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L |
6508 | #define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L |
6509 | #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L |
6510 | #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L |
6511 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L |
6512 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L |
6513 | #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L |
6514 | #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L |
6515 | #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L |
6516 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L |
6517 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L |
6518 | //CP_BUSY_STAT |
6519 | #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 |
6520 | #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 |
6521 | #define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 |
6522 | #define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 |
6523 | #define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 |
6524 | #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa |
6525 | #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc |
6526 | #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd |
6527 | #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe |
6528 | #define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf |
6529 | #define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 |
6530 | #define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 |
6531 | #define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 |
6532 | #define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 |
6533 | #define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 |
6534 | #define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 |
6535 | #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L |
6536 | #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L |
6537 | #define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L |
6538 | #define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L |
6539 | #define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L |
6540 | #define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L |
6541 | #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L |
6542 | #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L |
6543 | #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L |
6544 | #define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L |
6545 | #define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L |
6546 | #define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L |
6547 | #define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L |
6548 | #define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L |
6549 | #define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L |
6550 | #define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L |
6551 | //CP_STAT |
6552 | #define CP_STAT__ROQ_DB_BUSY__SHIFT 0x5 |
6553 | #define CP_STAT__ROQ_CE_DB_BUSY__SHIFT 0x6 |
6554 | #define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 |
6555 | #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa |
6556 | #define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb |
6557 | #define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc |
6558 | #define CP_STAT__DC_BUSY__SHIFT 0xd |
6559 | #define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe |
6560 | #define CP_STAT__PFP_BUSY__SHIFT 0xf |
6561 | #define CP_STAT__MEQ_BUSY__SHIFT 0x10 |
6562 | #define CP_STAT__ME_BUSY__SHIFT 0x11 |
6563 | #define CP_STAT__QUERY_BUSY__SHIFT 0x12 |
6564 | #define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 |
6565 | #define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 |
6566 | #define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 |
6567 | #define CP_STAT__DMA_BUSY__SHIFT 0x16 |
6568 | #define CP_STAT__RCIU_BUSY__SHIFT 0x17 |
6569 | #define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 |
6570 | #define CP_STAT__GCRIU_BUSY__SHIFT 0x19 |
6571 | #define CP_STAT__CE_BUSY__SHIFT 0x1a |
6572 | #define CP_STAT__TCIU_BUSY__SHIFT 0x1b |
6573 | #define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c |
6574 | #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d |
6575 | #define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e |
6576 | #define CP_STAT__CP_BUSY__SHIFT 0x1f |
6577 | #define CP_STAT__ROQ_DB_BUSY_MASK 0x00000020L |
6578 | #define CP_STAT__ROQ_CE_DB_BUSY_MASK 0x00000040L |
6579 | #define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L |
6580 | #define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L |
6581 | #define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L |
6582 | #define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L |
6583 | #define CP_STAT__DC_BUSY_MASK 0x00002000L |
6584 | #define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L |
6585 | #define CP_STAT__PFP_BUSY_MASK 0x00008000L |
6586 | #define CP_STAT__MEQ_BUSY_MASK 0x00010000L |
6587 | #define CP_STAT__ME_BUSY_MASK 0x00020000L |
6588 | #define CP_STAT__QUERY_BUSY_MASK 0x00040000L |
6589 | #define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L |
6590 | #define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L |
6591 | #define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L |
6592 | #define CP_STAT__DMA_BUSY_MASK 0x00400000L |
6593 | #define CP_STAT__RCIU_BUSY_MASK 0x00800000L |
6594 | #define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L |
6595 | #define CP_STAT__GCRIU_BUSY_MASK 0x02000000L |
6596 | #define CP_STAT__CE_BUSY_MASK 0x04000000L |
6597 | #define CP_STAT__TCIU_BUSY_MASK 0x08000000L |
6598 | #define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L |
6599 | #define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L |
6600 | #define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L |
6601 | #define CP_STAT__CP_BUSY_MASK 0x80000000L |
6602 | //CP_ME_HEADER_DUMP |
6603 | #define 0x0 |
6604 | #define 0xFFFFFFFFL |
6605 | //CP_PFP_HEADER_DUMP |
6606 | #define 0x0 |
6607 | #define 0xFFFFFFFFL |
6608 | //CP_GRBM_FREE_COUNT |
6609 | #define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
6610 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 |
6611 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 |
6612 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL |
6613 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L |
6614 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L |
6615 | //CP_CE_HEADER_DUMP |
6616 | #define 0x0 |
6617 | #define 0xFFFFFFFFL |
6618 | //CP_PFP_INSTR_PNTR |
6619 | #define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
6620 | #define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
6621 | //CP_ME_INSTR_PNTR |
6622 | #define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
6623 | #define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
6624 | //CP_CE_INSTR_PNTR |
6625 | #define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
6626 | #define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
6627 | //CP_MEC1_INSTR_PNTR |
6628 | #define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
6629 | #define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
6630 | //CP_MEC2_INSTR_PNTR |
6631 | #define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
6632 | #define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
6633 | //CP_CSF_STAT |
6634 | #define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 |
6635 | #define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L |
6636 | //CP_ME_CNTL |
6637 | #define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 |
6638 | #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 |
6639 | #define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 |
6640 | #define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 |
6641 | #define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 |
6642 | #define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 |
6643 | #define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 |
6644 | #define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 |
6645 | #define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 |
6646 | #define CP_ME_CNTL__CE_HALT__SHIFT 0x18 |
6647 | #define CP_ME_CNTL__CE_STEP__SHIFT 0x19 |
6648 | #define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a |
6649 | #define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b |
6650 | #define CP_ME_CNTL__ME_HALT__SHIFT 0x1c |
6651 | #define CP_ME_CNTL__ME_STEP__SHIFT 0x1d |
6652 | #define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L |
6653 | #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L |
6654 | #define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L |
6655 | #define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L |
6656 | #define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L |
6657 | #define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L |
6658 | #define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L |
6659 | #define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L |
6660 | #define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L |
6661 | #define CP_ME_CNTL__CE_HALT_MASK 0x01000000L |
6662 | #define CP_ME_CNTL__CE_STEP_MASK 0x02000000L |
6663 | #define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L |
6664 | #define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L |
6665 | #define CP_ME_CNTL__ME_HALT_MASK 0x10000000L |
6666 | #define CP_ME_CNTL__ME_STEP_MASK 0x20000000L |
6667 | //CP_CNTX_STAT |
6668 | #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 |
6669 | #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 |
6670 | #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 |
6671 | #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c |
6672 | #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL |
6673 | #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L |
6674 | #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L |
6675 | #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L |
6676 | //CP_ME_PREEMPTION |
6677 | #define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 |
6678 | #define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L |
6679 | //CP_ROQ_THRESHOLDS |
6680 | #define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 |
6681 | #define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 |
6682 | #define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL |
6683 | #define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L |
6684 | //CP_MEQ_STQ_THRESHOLD |
6685 | #define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 |
6686 | #define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL |
6687 | //CP_RB2_RPTR |
6688 | #define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 |
6689 | #define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL |
6690 | //CP_RB1_RPTR |
6691 | #define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 |
6692 | #define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL |
6693 | //CP_RB0_RPTR |
6694 | #define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 |
6695 | #define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL |
6696 | //CP_RB_RPTR |
6697 | #define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 |
6698 | #define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL |
6699 | //CP_RB_WPTR_DELAY |
6700 | #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 |
6701 | #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c |
6702 | #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL |
6703 | #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L |
6704 | //CP_RB_WPTR_POLL_CNTL |
6705 | #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 |
6706 | #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
6707 | #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL |
6708 | #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
6709 | //CP_ROQ1_THRESHOLDS |
6710 | #define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 |
6711 | #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0xa |
6712 | #define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x14 |
6713 | #define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000003FFL |
6714 | #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x000FFC00L |
6715 | #define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0x3FF00000L |
6716 | //CP_ROQ2_THRESHOLDS |
6717 | #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x0 |
6718 | #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0xa |
6719 | #define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x000003FFL |
6720 | #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x000FFC00L |
6721 | //CP_STQ_THRESHOLDS |
6722 | #define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 |
6723 | #define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 |
6724 | #define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 |
6725 | #define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL |
6726 | #define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L |
6727 | #define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L |
6728 | //CP_QUEUE_THRESHOLDS |
6729 | #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 |
6730 | #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 |
6731 | #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL |
6732 | #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L |
6733 | //CP_MEQ_THRESHOLDS |
6734 | #define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 |
6735 | #define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 |
6736 | #define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL |
6737 | #define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L |
6738 | //CP_ROQ_AVAIL |
6739 | #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 |
6740 | #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 |
6741 | #define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x00000FFFL |
6742 | #define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x0FFF0000L |
6743 | //CP_STQ_AVAIL |
6744 | #define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 |
6745 | #define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL |
6746 | //CP_ROQ2_AVAIL |
6747 | #define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 |
6748 | #define CP_ROQ2_AVAIL__ROQ_CNT_DB__SHIFT 0x10 |
6749 | #define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x00000FFFL |
6750 | #define CP_ROQ2_AVAIL__ROQ_CNT_DB_MASK 0x0FFF0000L |
6751 | //CP_MEQ_AVAIL |
6752 | #define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 |
6753 | #define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL |
6754 | //CP_CMD_INDEX |
6755 | #define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 |
6756 | #define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc |
6757 | #define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 |
6758 | #define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL |
6759 | #define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L |
6760 | #define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L |
6761 | //CP_CMD_DATA |
6762 | #define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 |
6763 | #define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL |
6764 | //CP_ROQ_RB_STAT |
6765 | #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 |
6766 | #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 |
6767 | #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x00000FFFL |
6768 | #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x0FFF0000L |
6769 | //CP_ROQ_IB1_STAT |
6770 | #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 |
6771 | #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 |
6772 | #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x00000FFFL |
6773 | #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x0FFF0000L |
6774 | //CP_ROQ_IB2_STAT |
6775 | #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 |
6776 | #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 |
6777 | #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x00000FFFL |
6778 | #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x0FFF0000L |
6779 | //CP_STQ_STAT |
6780 | #define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 |
6781 | #define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL |
6782 | //CP_STQ_WR_STAT |
6783 | #define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 |
6784 | #define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL |
6785 | //CP_MEQ_STAT |
6786 | #define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 |
6787 | #define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 |
6788 | #define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL |
6789 | #define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L |
6790 | //CP_CEQ1_AVAIL |
6791 | #define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 |
6792 | #define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 |
6793 | #define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x00000FFFL |
6794 | #define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x0FFF0000L |
6795 | //CP_CEQ2_AVAIL |
6796 | #define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 |
6797 | #define CP_CEQ2_AVAIL__CEQ_CNT_DB__SHIFT 0x10 |
6798 | #define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x00000FFFL |
6799 | #define CP_CEQ2_AVAIL__CEQ_CNT_DB_MASK 0x0FFF0000L |
6800 | //CP_CE_ROQ_RB_STAT |
6801 | #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 |
6802 | #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 |
6803 | #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x00000FFFL |
6804 | #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x0FFF0000L |
6805 | //CP_CE_ROQ_IB1_STAT |
6806 | #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 |
6807 | #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 |
6808 | #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x00000FFFL |
6809 | #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x0FFF0000L |
6810 | //CP_CE_ROQ_IB2_STAT |
6811 | #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 |
6812 | #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 |
6813 | #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x00000FFFL |
6814 | #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x0FFF0000L |
6815 | //CP_CE_ROQ_DB_STAT |
6816 | #define CP_CE_ROQ_DB_STAT__CEQ_RPTR_DB__SHIFT 0x0 |
6817 | #define CP_CE_ROQ_DB_STAT__CEQ_WPTR_DB__SHIFT 0x10 |
6818 | #define CP_CE_ROQ_DB_STAT__CEQ_RPTR_DB_MASK 0x00000FFFL |
6819 | #define CP_CE_ROQ_DB_STAT__CEQ_WPTR_DB_MASK 0x0FFF0000L |
6820 | //CP_ROQ3_THRESHOLDS |
6821 | #define CP_ROQ3_THRESHOLDS__R0_DB_START__SHIFT 0x0 |
6822 | #define CP_ROQ3_THRESHOLDS__R1_DB_START__SHIFT 0xa |
6823 | #define CP_ROQ3_THRESHOLDS__R0_DB_START_MASK 0x000003FFL |
6824 | #define CP_ROQ3_THRESHOLDS__R1_DB_START_MASK 0x000FFC00L |
6825 | //CP_ROQ_DB_STAT |
6826 | #define CP_ROQ_DB_STAT__ROQ_RPTR_DB__SHIFT 0x0 |
6827 | #define CP_ROQ_DB_STAT__ROQ_WPTR_DB__SHIFT 0x10 |
6828 | #define CP_ROQ_DB_STAT__ROQ_RPTR_DB_MASK 0x00000FFFL |
6829 | #define CP_ROQ_DB_STAT__ROQ_WPTR_DB_MASK 0x0FFF0000L |
6830 | #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 |
6831 | #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
6832 | #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L |
6833 | #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
6834 | |
6835 | |
6836 | // addressBlock: gc_padec |
6837 | //VGT_VTX_VECT_EJECT_REG |
6838 | #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 |
6839 | #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x000003FFL |
6840 | //VGT_DMA_DATA_FIFO_DEPTH |
6841 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 |
6842 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000003FFL |
6843 | //VGT_DMA_REQ_FIFO_DEPTH |
6844 | #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 |
6845 | #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL |
6846 | //VGT_DRAW_INIT_FIFO_DEPTH |
6847 | #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 |
6848 | #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL |
6849 | //VGT_LAST_COPY_STATE |
6850 | #define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 |
6851 | #define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 |
6852 | #define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L |
6853 | #define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L |
6854 | //VGT_CACHE_INVALIDATION |
6855 | #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 |
6856 | #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 |
6857 | #define 0x5 |
6858 | #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 |
6859 | #define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 |
6860 | #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb |
6861 | #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc |
6862 | #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd |
6863 | #define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 |
6864 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15 |
6865 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16 |
6866 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19 |
6867 | #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c |
6868 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d |
6869 | #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L |
6870 | #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L |
6871 | #define 0x00000020L |
6872 | #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L |
6873 | #define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L |
6874 | #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L |
6875 | #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L |
6876 | #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L |
6877 | #define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L |
6878 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L |
6879 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L |
6880 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L |
6881 | #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L |
6882 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L |
6883 | //VGT_ESGS_RING_SIZE |
6884 | #define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0 |
6885 | #define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL |
6886 | //VGT_GSVS_RING_SIZE |
6887 | #define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 |
6888 | #define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL |
6889 | //VGT_FIFO_DEPTHS |
6890 | #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 |
6891 | #define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 |
6892 | #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 |
6893 | #define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT 0x16 |
6894 | #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x17 |
6895 | #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL |
6896 | #define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L |
6897 | #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L |
6898 | #define VGT_FIFO_DEPTHS__RESERVED_1_MASK 0x00400000L |
6899 | #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x1F800000L |
6900 | //VGT_GS_VERTEX_REUSE |
6901 | #define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 |
6902 | #define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL |
6903 | //VGT_MC_LAT_CNTL |
6904 | #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 |
6905 | #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL |
6906 | //IA_UTCL1_STATUS_2 |
6907 | #define IA_UTCL1_STATUS_2__IA_BUSY__SHIFT 0x0 |
6908 | #define IA_UTCL1_STATUS_2__IA_DMA_BUSY__SHIFT 0x1 |
6909 | #define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY__SHIFT 0x2 |
6910 | #define IA_UTCL1_STATUS_2__IA_GRP_BUSY__SHIFT 0x3 |
6911 | #define IA_UTCL1_STATUS_2__IA_ADC_BUSY__SHIFT 0x4 |
6912 | #define IA_UTCL1_STATUS_2__FAULT_DETECTED__SHIFT 0x5 |
6913 | #define IA_UTCL1_STATUS_2__RETRY_DETECTED__SHIFT 0x6 |
6914 | #define IA_UTCL1_STATUS_2__PRT_DETECTED__SHIFT 0x7 |
6915 | #define IA_UTCL1_STATUS_2__FAULT_UTCL1ID__SHIFT 0x8 |
6916 | #define IA_UTCL1_STATUS_2__RETRY_UTCL1ID__SHIFT 0x10 |
6917 | #define IA_UTCL1_STATUS_2__PRT_UTCL1ID__SHIFT 0x18 |
6918 | #define IA_UTCL1_STATUS_2__IA_BUSY_MASK 0x00000001L |
6919 | #define IA_UTCL1_STATUS_2__IA_DMA_BUSY_MASK 0x00000002L |
6920 | #define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY_MASK 0x00000004L |
6921 | #define IA_UTCL1_STATUS_2__IA_GRP_BUSY_MASK 0x00000008L |
6922 | #define IA_UTCL1_STATUS_2__IA_ADC_BUSY_MASK 0x00000010L |
6923 | #define IA_UTCL1_STATUS_2__FAULT_DETECTED_MASK 0x00000020L |
6924 | #define IA_UTCL1_STATUS_2__RETRY_DETECTED_MASK 0x00000040L |
6925 | #define IA_UTCL1_STATUS_2__PRT_DETECTED_MASK 0x00000080L |
6926 | #define IA_UTCL1_STATUS_2__FAULT_UTCL1ID_MASK 0x00003F00L |
6927 | #define IA_UTCL1_STATUS_2__RETRY_UTCL1ID_MASK 0x003F0000L |
6928 | #define IA_UTCL1_STATUS_2__PRT_UTCL1ID_MASK 0x3F000000L |
6929 | //VGT_CNTL_STATUS |
6930 | #define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 |
6931 | #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 |
6932 | #define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 |
6933 | #define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 |
6934 | #define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 |
6935 | #define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 |
6936 | #define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 |
6937 | #define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 |
6938 | #define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 |
6939 | #define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 |
6940 | #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa |
6941 | #define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L |
6942 | #define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L |
6943 | #define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L |
6944 | #define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L |
6945 | #define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L |
6946 | #define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L |
6947 | #define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L |
6948 | #define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L |
6949 | #define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L |
6950 | #define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L |
6951 | #define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L |
6952 | //WD_CNTL_STATUS |
6953 | #define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 |
6954 | #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 |
6955 | #define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 |
6956 | #define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 |
6957 | #define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L |
6958 | #define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L |
6959 | #define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L |
6960 | #define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L |
6961 | //CC_GC_PRIM_CONFIG |
6962 | #define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 |
6963 | #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 |
6964 | #define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L |
6965 | #define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L |
6966 | //GC_USER_PRIM_CONFIG |
6967 | #define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 |
6968 | #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 |
6969 | #define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L |
6970 | #define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L |
6971 | //WD_QOS |
6972 | #define WD_QOS__DRAW_STALL__SHIFT 0x0 |
6973 | #define WD_QOS__DRAW_STALL_MASK 0x00000001L |
6974 | //WD_UTCL1_CNTL |
6975 | #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
6976 | #define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
6977 | #define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
6978 | #define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
6979 | #define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
6980 | #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
6981 | #define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
6982 | #define WD_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d |
6983 | #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
6984 | #define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
6985 | #define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
6986 | #define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
6987 | #define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
6988 | #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
6989 | #define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
6990 | #define WD_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L |
6991 | //WD_UTCL1_STATUS |
6992 | #define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
6993 | #define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
6994 | #define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
6995 | #define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
6996 | #define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
6997 | #define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
6998 | #define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
6999 | #define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
7000 | #define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
7001 | #define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
7002 | #define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
7003 | #define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
7004 | //GE_PC_CNTL |
7005 | #define GE_PC_CNTL__PC_SIZE__SHIFT 0x0 |
7006 | #define GE_PC_CNTL__EN_GEN_0_1_LATE_ALLOC__SHIFT 0x10 |
7007 | #define GE_PC_CNTL__PC_SIZE_MASK 0x0000FFFFL |
7008 | #define GE_PC_CNTL__EN_GEN_0_1_LATE_ALLOC_MASK 0x00010000L |
7009 | //IA_UTCL1_CNTL |
7010 | #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
7011 | #define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
7012 | #define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
7013 | #define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
7014 | #define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
7015 | #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
7016 | #define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
7017 | #define IA_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d |
7018 | #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
7019 | #define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
7020 | #define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
7021 | #define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
7022 | #define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
7023 | #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
7024 | #define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
7025 | #define IA_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L |
7026 | //IA_UTCL1_STATUS |
7027 | #define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
7028 | #define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
7029 | #define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
7030 | #define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
7031 | #define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
7032 | #define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
7033 | #define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
7034 | #define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
7035 | #define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
7036 | #define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
7037 | #define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
7038 | #define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
7039 | //GE_FAST_CLKS |
7040 | #define GE_FAST_CLKS__HYSTERESIS__SHIFT 0x0 |
7041 | #define GE_FAST_CLKS__LOCK__SHIFT 0x1e |
7042 | #define GE_FAST_CLKS__FORCE_FAST_CLK__SHIFT 0x1f |
7043 | #define GE_FAST_CLKS__HYSTERESIS_MASK 0x3FFFFFFFL |
7044 | #define GE_FAST_CLKS__LOCK_MASK 0x40000000L |
7045 | #define GE_FAST_CLKS__FORCE_FAST_CLK_MASK 0x80000000L |
7046 | //VGT_TF_RING_SIZE |
7047 | #define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 |
7048 | #define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL |
7049 | //VGT_SYS_CONFIG |
7050 | #define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 |
7051 | #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 |
7052 | #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 |
7053 | #define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L |
7054 | #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL |
7055 | #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L |
7056 | //GE_PRIV_CONTROL |
7057 | #define GE_PRIV_CONTROL__DISCARD_LEGACY__SHIFT 0x0 |
7058 | #define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE__SHIFT 0x1 |
7059 | #define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE__SHIFT 0xa |
7060 | #define GE_PRIV_CONTROL__DISCARD_LEGACY_MASK 0x00000001L |
7061 | #define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE_MASK 0x000003FEL |
7062 | #define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE_MASK 0x00000400L |
7063 | //GE_STATUS |
7064 | #define GE_STATUS__PERFCOUNTER_STATUS__SHIFT 0x0 |
7065 | #define GE_STATUS__THREAD_TRACE_STATUS__SHIFT 0x1 |
7066 | #define GE_STATUS__PERFCOUNTER_STATUS_MASK 0x00000001L |
7067 | #define GE_STATUS__THREAD_TRACE_STATUS_MASK 0x00000002L |
7068 | //VGT_VS_MAX_WAVE_ID |
7069 | #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
7070 | #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
7071 | //VGT_GS_MAX_WAVE_ID |
7072 | #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
7073 | #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
7074 | //CC_GC_SHADER_ARRAY_CONFIG_GEN0 |
7075 | #define CC_GC_SHADER_ARRAY_CONFIG_GEN0__GEN0_INACTIVE_CU__SHIFT 0x10 |
7076 | #define CC_GC_SHADER_ARRAY_CONFIG_GEN0__GEN0_INACTIVE_CU_MASK 0x03FF0000L |
7077 | //VGT_HS_OFFCHIP_PARAM |
7078 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 |
7079 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 |
7080 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL |
7081 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L |
7082 | //GFX_PIPE_CONTROL |
7083 | #define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 |
7084 | #define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd |
7085 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 |
7086 | #define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL |
7087 | #define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L |
7088 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L |
7089 | //VGT_TF_MEMORY_BASE |
7090 | #define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 |
7091 | #define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL |
7092 | //CC_GC_SHADER_ARRAY_CONFIG |
7093 | #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10 |
7094 | #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L |
7095 | //GC_USER_SHADER_ARRAY_CONFIG |
7096 | #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10 |
7097 | #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L |
7098 | //VGT_DMA_PRIMITIVE_TYPE |
7099 | #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 |
7100 | #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL |
7101 | //VGT_DMA_CONTROL |
7102 | #define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 |
7103 | #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 |
7104 | #define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13 |
7105 | #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 |
7106 | #define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL |
7107 | #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L |
7108 | #define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L |
7109 | #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L |
7110 | //VGT_DMA_LS_HS_CONFIG |
7111 | #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 |
7112 | #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L |
7113 | //VGT_STRMOUT_DELAY |
7114 | #define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 |
7115 | #define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 |
7116 | #define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb |
7117 | #define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe |
7118 | #define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 |
7119 | #define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL |
7120 | #define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L |
7121 | #define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L |
7122 | #define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L |
7123 | #define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L |
7124 | //WD_BUF_RESOURCE_1 |
7125 | #define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0 |
7126 | #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10 |
7127 | #define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL |
7128 | #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L |
7129 | //WD_BUF_RESOURCE_2 |
7130 | #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0 |
7131 | #define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf |
7132 | #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10 |
7133 | #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL |
7134 | #define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L |
7135 | #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L |
7136 | //VGT_TF_MEMORY_BASE_HI |
7137 | #define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0 |
7138 | #define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL |
7139 | //PA_CL_CNTL_STATUS |
7140 | #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0 |
7141 | #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1 |
7142 | #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2 |
7143 | #define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f |
7144 | #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L |
7145 | #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L |
7146 | #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L |
7147 | #define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L |
7148 | //PA_CL_ENHANCE |
7149 | #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 |
7150 | #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 |
7151 | #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 |
7152 | #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 |
7153 | #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 |
7154 | #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 |
7155 | #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 |
7156 | #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 |
7157 | #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb |
7158 | #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc |
7159 | #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe |
7160 | #define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT 0x11 |
7161 | #define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT 0x12 |
7162 | #define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT 0x13 |
7163 | #define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT 0x14 |
7164 | #define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT 0x15 |
7165 | #define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE__SHIFT 0x16 |
7166 | #define PA_CL_ENHANCE__EN_32BIT_OBJPRIMID__SHIFT 0x17 |
7167 | #define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c |
7168 | #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d |
7169 | #define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e |
7170 | #define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f |
7171 | #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L |
7172 | #define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L |
7173 | #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L |
7174 | #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L |
7175 | #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L |
7176 | #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L |
7177 | #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L |
7178 | #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L |
7179 | #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L |
7180 | #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L |
7181 | #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L |
7182 | #define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK 0x00020000L |
7183 | #define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK 0x00040000L |
7184 | #define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK 0x00080000L |
7185 | #define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK 0x00100000L |
7186 | #define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK 0x00200000L |
7187 | #define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE_MASK 0x00400000L |
7188 | #define PA_CL_ENHANCE__EN_32BIT_OBJPRIMID_MASK 0x00800000L |
7189 | #define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L |
7190 | #define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L |
7191 | #define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L |
7192 | #define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L |
7193 | //PA_SU_CNTL_STATUS |
7194 | #define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f |
7195 | #define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L |
7196 | //PA_SC_FIFO_DEPTH_CNTL |
7197 | #define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 |
7198 | #define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL |
7199 | //PA_SC_P3D_TRAP_SCREEN_HV_LOCK |
7200 | #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
7201 | #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
7202 | //PA_SC_HP3D_TRAP_SCREEN_HV_LOCK |
7203 | #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
7204 | #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
7205 | //PA_SC_TRAP_SCREEN_HV_LOCK |
7206 | #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
7207 | #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
7208 | //PA_SC_FORCE_EOV_MAX_CNTS |
7209 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 |
7210 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 |
7211 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL |
7212 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L |
7213 | //PA_SC_BINNER_EVENT_CNTL_0 |
7214 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 |
7215 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 |
7216 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 |
7217 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 |
7218 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 |
7219 | #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa |
7220 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc |
7221 | #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe |
7222 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 |
7223 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12 |
7224 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 |
7225 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 |
7226 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 |
7227 | #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a |
7228 | #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c |
7229 | #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e |
7230 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L |
7231 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL |
7232 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L |
7233 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L |
7234 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L |
7235 | #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L |
7236 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L |
7237 | #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L |
7238 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L |
7239 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L |
7240 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L |
7241 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L |
7242 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L |
7243 | #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L |
7244 | #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L |
7245 | #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L |
7246 | //PA_SC_BINNER_EVENT_CNTL_1 |
7247 | #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 |
7248 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 |
7249 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 |
7250 | #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 |
7251 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 |
7252 | #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa |
7253 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc |
7254 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe |
7255 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 |
7256 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 |
7257 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 |
7258 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 |
7259 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 |
7260 | #define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK__SHIFT 0x1a |
7261 | #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c |
7262 | #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e |
7263 | #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L |
7264 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL |
7265 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L |
7266 | #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L |
7267 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L |
7268 | #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L |
7269 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L |
7270 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L |
7271 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L |
7272 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L |
7273 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L |
7274 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L |
7275 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L |
7276 | #define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK_MASK 0x0C000000L |
7277 | #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L |
7278 | #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L |
7279 | //PA_SC_BINNER_EVENT_CNTL_2 |
7280 | #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 |
7281 | #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 |
7282 | #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 |
7283 | #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35__SHIFT 0x6 |
7284 | #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 |
7285 | #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa |
7286 | #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc |
7287 | #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe |
7288 | #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 |
7289 | #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41__SHIFT 0x12 |
7290 | #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 |
7291 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 |
7292 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 |
7293 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a |
7294 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c |
7295 | #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e |
7296 | #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L |
7297 | #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL |
7298 | #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L |
7299 | #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35_MASK 0x000000C0L |
7300 | #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L |
7301 | #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L |
7302 | #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L |
7303 | #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L |
7304 | #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L |
7305 | #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41_MASK 0x000C0000L |
7306 | #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L |
7307 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L |
7308 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L |
7309 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L |
7310 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L |
7311 | #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L |
7312 | //PA_SC_BINNER_EVENT_CNTL_3 |
7313 | #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 |
7314 | #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 |
7315 | #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50__SHIFT 0x4 |
7316 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 |
7317 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 |
7318 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa |
7319 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW__SHIFT 0xc |
7320 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe |
7321 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 |
7322 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 |
7323 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 |
7324 | #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 |
7325 | #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 |
7326 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a |
7327 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c |
7328 | #define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE__SHIFT 0x1e |
7329 | #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L |
7330 | #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL |
7331 | #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50_MASK 0x00000030L |
7332 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L |
7333 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L |
7334 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L |
7335 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW_MASK 0x00003000L |
7336 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L |
7337 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L |
7338 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L |
7339 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L |
7340 | #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L |
7341 | #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L |
7342 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L |
7343 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L |
7344 | #define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE_MASK 0xC0000000L |
7345 | //PA_SC_BINNER_TIMEOUT_COUNTER |
7346 | #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 |
7347 | #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL |
7348 | //PA_SC_BINNER_PERF_CNTL_0 |
7349 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 |
7350 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa |
7351 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 |
7352 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 |
7353 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL |
7354 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L |
7355 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L |
7356 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L |
7357 | //PA_SC_BINNER_PERF_CNTL_1 |
7358 | #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 |
7359 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 |
7360 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa |
7361 | #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL |
7362 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L |
7363 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L |
7364 | //PA_SC_BINNER_PERF_CNTL_2 |
7365 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 |
7366 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb |
7367 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL |
7368 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L |
7369 | //PA_SC_BINNER_PERF_CNTL_3 |
7370 | #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 |
7371 | #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL |
7372 | //PA_SC_ENHANCE_2 |
7373 | #define PA_SC_ENHANCE_2__ECO_SPARE0__SHIFT 0x0 |
7374 | #define PA_SC_ENHANCE_2__ECO_SPARE1__SHIFT 0x1 |
7375 | #define PA_SC_ENHANCE_2__ECO_SPARE2__SHIFT 0x2 |
7376 | #define PA_SC_ENHANCE_2__ECO_SPARE3__SHIFT 0x3 |
7377 | #define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK__SHIFT 0x4 |
7378 | #define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK__SHIFT 0x5 |
7379 | #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN__SHIFT 0x6 |
7380 | #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD__SHIFT 0x7 |
7381 | #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH__SHIFT 0x8 |
7382 | #define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT 0x9 |
7383 | #define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT 0xa |
7384 | #define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE__SHIFT 0xb |
7385 | #define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xc |
7386 | #define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP__SHIFT 0xd |
7387 | #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP__SHIFT 0xe |
7388 | #define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ__SHIFT 0xf |
7389 | #define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP__SHIFT 0x10 |
7390 | #define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP__SHIFT 0x11 |
7391 | #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET__SHIFT 0x12 |
7392 | #define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN1_REG__SHIFT 0x13 |
7393 | #define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN2_REG__SHIFT 0x14 |
7394 | #define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG__SHIFT 0x15 |
7395 | #define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO__SHIFT 0x17 |
7396 | #define PA_SC_ENHANCE_2__DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE__SHIFT 0x18 |
7397 | #define PA_SC_ENHANCE_2__DISABLE_DFSM_FLUSH__SHIFT 0x19 |
7398 | #define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH__SHIFT 0x1a |
7399 | #define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT__SHIFT 0x1b |
7400 | #define PA_SC_ENHANCE_2__RSVD__SHIFT 0x1e |
7401 | #define PA_SC_ENHANCE_2__ECO_SPARE0_MASK 0x00000001L |
7402 | #define PA_SC_ENHANCE_2__ECO_SPARE1_MASK 0x00000002L |
7403 | #define PA_SC_ENHANCE_2__ECO_SPARE2_MASK 0x00000004L |
7404 | #define PA_SC_ENHANCE_2__ECO_SPARE3_MASK 0x00000008L |
7405 | #define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK_MASK 0x00000010L |
7406 | #define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK_MASK 0x00000020L |
7407 | #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_COMPOUND_INDEX_EN_MASK 0x00000040L |
7408 | #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD_MASK 0x00000080L |
7409 | #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH_MASK 0x00000100L |
7410 | #define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK_MASK 0x00000200L |
7411 | #define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS_MASK 0x00000400L |
7412 | #define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE_MASK 0x00000800L |
7413 | #define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00001000L |
7414 | #define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP_MASK 0x00002000L |
7415 | #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP_MASK 0x00004000L |
7416 | #define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ_MASK 0x00008000L |
7417 | #define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP_MASK 0x00010000L |
7418 | #define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP_MASK 0x00020000L |
7419 | #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET_MASK 0x00040000L |
7420 | #define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN1_REG_MASK 0x00080000L |
7421 | #define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN2_REG_MASK 0x00100000L |
7422 | #define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG_MASK 0x00200000L |
7423 | #define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO_MASK 0x00800000L |
7424 | #define PA_SC_ENHANCE_2__DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE_MASK 0x01000000L |
7425 | #define PA_SC_ENHANCE_2__DISABLE_DFSM_FLUSH_MASK 0x02000000L |
7426 | #define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH_MASK 0x04000000L |
7427 | #define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT_MASK 0x38000000L |
7428 | #define PA_SC_ENHANCE_2__RSVD_MASK 0xC0000000L |
7429 | //PA_SC_ENHANCE_INTERNAL |
7430 | #define PA_SC_ENHANCE_INTERNAL__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x0 |
7431 | #define PA_SC_ENHANCE_INTERNAL__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000001L |
7432 | //PA_SC_BINNER_CNTL_OVERRIDE |
7433 | #define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE__SHIFT 0x0 |
7434 | #define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT 0xa |
7435 | #define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN__SHIFT 0xd |
7436 | #define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH__SHIFT 0x13 |
7437 | #define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE__SHIFT 0x1b |
7438 | #define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE__SHIFT 0x1c |
7439 | #define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE_MASK 0x00000003L |
7440 | #define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L |
7441 | #define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L |
7442 | #define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH_MASK 0x07F80000L |
7443 | #define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE_MASK 0x08000000L |
7444 | #define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE_MASK 0xF0000000L |
7445 | //PA_SC_PBB_OVERRIDE_FLAG |
7446 | #define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE__SHIFT 0x0 |
7447 | #define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID__SHIFT 0x1 |
7448 | #define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE_MASK 0x00000001L |
7449 | #define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID_MASK 0x00000002L |
7450 | //PA_PH_INTERFACE_FIFO_SIZE |
7451 | #define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE__SHIFT 0x0 |
7452 | #define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE__SHIFT 0x10 |
7453 | #define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE_MASK 0x000003FFL |
7454 | #define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE_MASK 0x003F0000L |
7455 | //PA_PH_ENHANCE |
7456 | #define PA_PH_ENHANCE__ECO_SPARE0__SHIFT 0x0 |
7457 | #define PA_PH_ENHANCE__ECO_SPARE1__SHIFT 0x1 |
7458 | #define PA_PH_ENHANCE__ECO_SPARE2__SHIFT 0x2 |
7459 | #define PA_PH_ENHANCE__ECO_SPARE3__SHIFT 0x3 |
7460 | #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE__SHIFT 0x4 |
7461 | #define PA_PH_ENHANCE__DISABLE_FOPKT__SHIFT 0x5 |
7462 | #define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET__SHIFT 0x6 |
7463 | #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE__SHIFT 0x7 |
7464 | #define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG__SHIFT 0x9 |
7465 | #define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT 0xa |
7466 | #define PA_PH_ENHANCE__ECO_SPARE0_MASK 0x00000001L |
7467 | #define PA_PH_ENHANCE__ECO_SPARE1_MASK 0x00000002L |
7468 | #define PA_PH_ENHANCE__ECO_SPARE2_MASK 0x00000004L |
7469 | #define PA_PH_ENHANCE__ECO_SPARE3_MASK 0x00000008L |
7470 | #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE_MASK 0x00000010L |
7471 | #define PA_PH_ENHANCE__DISABLE_FOPKT_MASK 0x00000020L |
7472 | #define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET_MASK 0x00000040L |
7473 | #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE_MASK 0x00000080L |
7474 | #define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG_MASK 0x00000200L |
7475 | #define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH_MASK 0x00001C00L |
7476 | //PA_SC_BC_WAVE_BREAK |
7477 | #define PA_SC_BC_WAVE_BREAK__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 |
7478 | #define PA_SC_BC_WAVE_BREAK__MAX_FPOVS_IN_WAVE__SHIFT 0x10 |
7479 | #define PA_SC_BC_WAVE_BREAK__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL |
7480 | #define PA_SC_BC_WAVE_BREAK__MAX_FPOVS_IN_WAVE_MASK 0x00FF0000L |
7481 | //PA_SC_FIFO_SIZE |
7482 | #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 |
7483 | #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 |
7484 | #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf |
7485 | #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 |
7486 | #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL |
7487 | #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L |
7488 | #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L |
7489 | #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L |
7490 | //PA_SC_IF_FIFO_SIZE |
7491 | #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 |
7492 | #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 |
7493 | #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc |
7494 | #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 |
7495 | #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL |
7496 | #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L |
7497 | #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L |
7498 | #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L |
7499 | //PA_SC_PKR_WAVE_TABLE_CNTL |
7500 | #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 |
7501 | #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL |
7502 | //PA_SIDEBAND_REQUEST_DELAYS |
7503 | #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0 |
7504 | #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10 |
7505 | #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL |
7506 | #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L |
7507 | //PA_SC_ENHANCE |
7508 | #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 |
7509 | #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 |
7510 | #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 |
7511 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 |
7512 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 |
7513 | #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 |
7514 | #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 |
7515 | #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 |
7516 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 |
7517 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 |
7518 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa |
7519 | #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb |
7520 | #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc |
7521 | #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd |
7522 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe |
7523 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf |
7524 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 |
7525 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 |
7526 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 |
7527 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 |
7528 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 |
7529 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 |
7530 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 |
7531 | #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 |
7532 | #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 |
7533 | #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 |
7534 | #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a |
7535 | #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b |
7536 | #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c |
7537 | #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d |
7538 | #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L |
7539 | #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L |
7540 | #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L |
7541 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L |
7542 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L |
7543 | #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L |
7544 | #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L |
7545 | #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L |
7546 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L |
7547 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L |
7548 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L |
7549 | #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L |
7550 | #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L |
7551 | #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L |
7552 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L |
7553 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L |
7554 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L |
7555 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L |
7556 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L |
7557 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L |
7558 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L |
7559 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L |
7560 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L |
7561 | #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L |
7562 | #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L |
7563 | #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L |
7564 | #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L |
7565 | #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L |
7566 | #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L |
7567 | #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L |
7568 | //PA_SC_ENHANCE_1 |
7569 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 |
7570 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 |
7571 | #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 |
7572 | #define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 |
7573 | #define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5 |
7574 | #define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 |
7575 | #define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 |
7576 | #define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 |
7577 | #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 |
7578 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa |
7579 | #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb |
7580 | #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe |
7581 | #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf |
7582 | #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 |
7583 | #define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11 |
7584 | #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 |
7585 | #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 |
7586 | #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 |
7587 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 |
7588 | #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 |
7589 | #define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT 0x17 |
7590 | #define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 |
7591 | #define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT 0x19 |
7592 | #define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1a |
7593 | #define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT 0x1b |
7594 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT 0x1c |
7595 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT 0x1d |
7596 | #define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT 0x1e |
7597 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L |
7598 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L |
7599 | #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L |
7600 | #define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L |
7601 | #define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L |
7602 | #define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L |
7603 | #define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L |
7604 | #define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L |
7605 | #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L |
7606 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L |
7607 | #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L |
7608 | #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L |
7609 | #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L |
7610 | #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L |
7611 | #define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L |
7612 | #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L |
7613 | #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L |
7614 | #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L |
7615 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L |
7616 | #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L |
7617 | #define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK 0x00800000L |
7618 | #define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L |
7619 | #define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK 0x02000000L |
7620 | #define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK 0x04000000L |
7621 | #define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK 0x08000000L |
7622 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK 0x10000000L |
7623 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK 0x20000000L |
7624 | #define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK 0x40000000L |
7625 | //PA_SC_DSM_CNTL |
7626 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 |
7627 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 |
7628 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L |
7629 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L |
7630 | //PA_SC_TILE_STEERING_CREST_OVERRIDE |
7631 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 |
7632 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 |
7633 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 |
7634 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT__SHIFT 0x8 |
7635 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE__SHIFT 0x1f |
7636 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L |
7637 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L |
7638 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L |
7639 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT_MASK 0x00000700L |
7640 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE_MASK 0x80000000L |
7641 | |
7642 | |
7643 | // addressBlock: gc_sqdec |
7644 | //SQ_CONFIG |
7645 | #define SQ_CONFIG__UNUSED__SHIFT 0x0 |
7646 | #define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb |
7647 | #define SQ_CONFIG__VGPR_SWIZZLE_EN__SHIFT 0xc |
7648 | #define SQ_CONFIG__LDS_BUSY_HYSTERESIS_CNT__SHIFT 0xd |
7649 | #define SQ_CONFIG__SP_BUSY_HYSTERESIS_CNT__SHIFT 0xf |
7650 | #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 |
7651 | #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 |
7652 | #define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15 |
7653 | #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d |
7654 | #define SQ_CONFIG__TA_BUSY_HYSTERESIS_CNT__SHIFT 0x1e |
7655 | #define SQ_CONFIG__UNUSED_MASK 0x0000007FL |
7656 | #define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L |
7657 | #define SQ_CONFIG__VGPR_SWIZZLE_EN_MASK 0x00001000L |
7658 | #define SQ_CONFIG__LDS_BUSY_HYSTERESIS_CNT_MASK 0x00006000L |
7659 | #define SQ_CONFIG__SP_BUSY_HYSTERESIS_CNT_MASK 0x00018000L |
7660 | #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L |
7661 | #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L |
7662 | #define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L |
7663 | #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L |
7664 | #define SQ_CONFIG__TA_BUSY_HYSTERESIS_CNT_MASK 0xC0000000L |
7665 | //SQC_CONFIG |
7666 | #define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 |
7667 | #define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 |
7668 | #define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 |
7669 | #define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 |
7670 | #define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 |
7671 | #define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 |
7672 | #define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 |
7673 | #define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa |
7674 | #define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb |
7675 | #define SQC_CONFIG__EVICT_LRU__SHIFT 0xc |
7676 | #define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe |
7677 | #define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf |
7678 | #define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 |
7679 | #define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L |
7680 | #define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL |
7681 | #define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L |
7682 | #define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L |
7683 | #define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L |
7684 | #define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L |
7685 | #define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L |
7686 | #define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L |
7687 | #define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L |
7688 | #define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L |
7689 | #define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L |
7690 | #define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L |
7691 | #define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L |
7692 | //LDS_CONFIG |
7693 | #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0 |
7694 | #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L |
7695 | //SQ_RANDOM_WAVE_PRI |
7696 | #define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 |
7697 | #define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 |
7698 | #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa |
7699 | #define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL |
7700 | #define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L |
7701 | #define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x00FFFC00L |
7702 | //SQG_STATUS |
7703 | #define SQG_STATUS__REG_BUSY__SHIFT 0x0 |
7704 | #define SQG_STATUS__REG_BUSY_MASK 0x00000001L |
7705 | //SQ_FIFO_SIZES |
7706 | #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 |
7707 | #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 |
7708 | #define SQ_FIFO_SIZES__EXPORT_BUF_VS_RESERVED__SHIFT 0xc |
7709 | #define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED__SHIFT 0xe |
7710 | #define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE__SHIFT 0x10 |
7711 | #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 |
7712 | #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL |
7713 | #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000300L |
7714 | #define SQ_FIFO_SIZES__EXPORT_BUF_VS_RESERVED_MASK 0x00003000L |
7715 | #define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED_MASK 0x0000C000L |
7716 | #define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE_MASK 0x00030000L |
7717 | #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L |
7718 | //SQ_DSM_CNTL |
7719 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 |
7720 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 |
7721 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 |
7722 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 |
7723 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 |
7724 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 |
7725 | #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa |
7726 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 |
7727 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 |
7728 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 |
7729 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 |
7730 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 |
7731 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 |
7732 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 |
7733 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 |
7734 | #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a |
7735 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L |
7736 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L |
7737 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L |
7738 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L |
7739 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L |
7740 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L |
7741 | #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L |
7742 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L |
7743 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L |
7744 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L |
7745 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L |
7746 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L |
7747 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L |
7748 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L |
7749 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L |
7750 | #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L |
7751 | //SQ_DSM_CNTL2 |
7752 | #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 |
7753 | #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 |
7754 | #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 |
7755 | #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 |
7756 | #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 |
7757 | #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 |
7758 | #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 |
7759 | #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb |
7760 | #define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe |
7761 | #define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 |
7762 | #define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a |
7763 | #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L |
7764 | #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L |
7765 | #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L |
7766 | #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L |
7767 | #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
7768 | #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L |
7769 | #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L |
7770 | #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L |
7771 | #define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L |
7772 | #define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L |
7773 | #define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L |
7774 | //SQ_RUNTIME_CONFIG |
7775 | #define SQ_RUNTIME_CONFIG__UNUSED_REGISTER__SHIFT 0x0 |
7776 | #define SQ_RUNTIME_CONFIG__UNUSED_REGISTER_MASK 0x00000001L |
7777 | //SH_MEM_BASES |
7778 | #define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 |
7779 | #define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 |
7780 | #define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL |
7781 | #define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L |
7782 | //SP_CONFIG |
7783 | #define SP_CONFIG__DEST_CACHE_EVICT_COUNTER__SHIFT 0x0 |
7784 | #define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE__SHIFT 0x2 |
7785 | #define SP_CONFIG__DISABLE_TRANS_COEXEC__SHIFT 0x3 |
7786 | #define SP_CONFIG__TRANS_MGCG_OVERRIDE__SHIFT 0x4 |
7787 | #define SP_CONFIG__CAC_COUNTER_OVERRIDE__SHIFT 0x5 |
7788 | #define SP_CONFIG__DPMACC_MGCG_OVERRIDE__SHIFT 0x6 |
7789 | #define SP_CONFIG__SMACC_MGCG_OVERRIDE__SHIFT 0x7 |
7790 | #define SP_CONFIG__UNUSED__SHIFT 0x8 |
7791 | #define SP_CONFIG__DEST_CACHE_EVICT_COUNTER_MASK 0x00000003L |
7792 | #define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE_MASK 0x00000004L |
7793 | #define SP_CONFIG__DISABLE_TRANS_COEXEC_MASK 0x00000008L |
7794 | #define SP_CONFIG__TRANS_MGCG_OVERRIDE_MASK 0x00000010L |
7795 | #define SP_CONFIG__CAC_COUNTER_OVERRIDE_MASK 0x00000020L |
7796 | #define SP_CONFIG__DPMACC_MGCG_OVERRIDE_MASK 0x00000040L |
7797 | #define SP_CONFIG__SMACC_MGCG_OVERRIDE_MASK 0x00000080L |
7798 | #define SP_CONFIG__UNUSED_MASK 0x00000100L |
7799 | //SQ_ARB_CONFIG |
7800 | #define SQ_ARB_CONFIG__WG_RR_INTERVAL__SHIFT 0x0 |
7801 | #define SQ_ARB_CONFIG__FWD_PROG_INTERVAL__SHIFT 0x4 |
7802 | #define SQ_ARB_CONFIG__DISABLE_SECOND_TRY__SHIFT 0x8 |
7803 | #define SQ_ARB_CONFIG__WG_RR_INTERVAL_MASK 0x00000003L |
7804 | #define SQ_ARB_CONFIG__FWD_PROG_INTERVAL_MASK 0x00000030L |
7805 | #define SQ_ARB_CONFIG__DISABLE_SECOND_TRY_MASK 0x00000100L |
7806 | //SH_MEM_CONFIG |
7807 | #define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 |
7808 | #define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x2 |
7809 | #define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x4 |
7810 | #define SH_MEM_CONFIG__RETRY_MODE__SHIFT 0xc |
7811 | #define SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT 0xe |
7812 | #define SH_MEM_CONFIG__NO_PREFETCH_ACROSS_PAGE__SHIFT 0x10 |
7813 | #define SH_MEM_CONFIG__ILLEGAL_INST_CHECK_DISABLE__SHIFT 0x11 |
7814 | #define SH_MEM_CONFIG__ICACHE_USE_GL1__SHIFT 0x12 |
7815 | #define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L |
7816 | #define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x0000000CL |
7817 | #define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0x00000070L |
7818 | #define SH_MEM_CONFIG__RETRY_MODE_MASK 0x00003000L |
7819 | #define SH_MEM_CONFIG__INITIAL_INST_PREFETCH_MASK 0x0000C000L |
7820 | #define SH_MEM_CONFIG__NO_PREFETCH_ACROSS_PAGE_MASK 0x00010000L |
7821 | #define SH_MEM_CONFIG__ILLEGAL_INST_CHECK_DISABLE_MASK 0x00020000L |
7822 | #define SH_MEM_CONFIG__ICACHE_USE_GL1_MASK 0x00040000L |
7823 | //CC_GC_SHADER_RATE_CONFIG |
7824 | #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 |
7825 | #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 |
7826 | #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L |
7827 | #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L |
7828 | //GC_USER_SHADER_RATE_CONFIG |
7829 | #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 |
7830 | #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 |
7831 | #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L |
7832 | #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L |
7833 | //SQ_INTERRUPT_AUTO_MASK |
7834 | #define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 |
7835 | #define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL |
7836 | //SQ_INTERRUPT_MSG_CTRL |
7837 | #define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 |
7838 | #define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L |
7839 | //SQG_UTCL0_CNTL1 |
7840 | #define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
7841 | #define SQG_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
7842 | #define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
7843 | #define SQG_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 |
7844 | #define SQG_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
7845 | #define SQG_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 |
7846 | #define SQG_UTCL0_CNTL1__RESERVED__SHIFT 0x10 |
7847 | #define SQG_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
7848 | #define SQG_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
7849 | #define SQG_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13 |
7850 | #define SQG_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 |
7851 | #define SQG_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 |
7852 | #define SQG_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
7853 | #define SQG_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a |
7854 | #define SQG_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
7855 | #define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
7856 | #define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
7857 | #define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
7858 | #define SQG_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
7859 | #define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
7860 | #define SQG_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L |
7861 | #define SQG_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
7862 | #define SQG_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L |
7863 | #define SQG_UTCL0_CNTL1__RESERVED_MASK 0x00010000L |
7864 | #define SQG_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
7865 | #define SQG_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
7866 | #define SQG_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L |
7867 | #define SQG_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L |
7868 | #define SQG_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L |
7869 | #define SQG_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
7870 | #define SQG_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L |
7871 | #define SQG_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
7872 | #define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
7873 | #define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
7874 | //SQG_UTCL0_CNTL2 |
7875 | #define SQG_UTCL0_CNTL2__SPARE__SHIFT 0x0 |
7876 | #define SQG_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 |
7877 | #define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
7878 | #define SQG_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa |
7879 | #define SQG_UTCL0_CNTL2__DIS_EDC__SHIFT 0xb |
7880 | #define SQG_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
7881 | #define SQG_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
7882 | #define SQG_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe |
7883 | #define SQG_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
7884 | #define SQG_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT 0x10 |
7885 | #define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
7886 | #define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 |
7887 | #define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
7888 | #define SQG_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 |
7889 | #define SQG_UTCL0_CNTL2__DIS_DUAL_L2_REQ__SHIFT 0x19 |
7890 | #define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
7891 | #define SQG_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b |
7892 | #define SQG_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c |
7893 | #define SQG_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT 0x1d |
7894 | #define SQG_UTCL0_CNTL2__RESERVED__SHIFT 0x1e |
7895 | #define SQG_UTCL0_CNTL2__SPARE_MASK 0x000000FFL |
7896 | #define SQG_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L |
7897 | #define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
7898 | #define SQG_UTCL0_CNTL2__LINE_VALID_MASK 0x00000400L |
7899 | #define SQG_UTCL0_CNTL2__DIS_EDC_MASK 0x00000800L |
7900 | #define SQG_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
7901 | #define SQG_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
7902 | #define SQG_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
7903 | #define SQG_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
7904 | #define SQG_UTCL0_CNTL2__ARB_BURST_MODE_MASK 0x00030000L |
7905 | #define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
7906 | #define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L |
7907 | #define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
7908 | #define SQG_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L |
7909 | #define SQG_UTCL0_CNTL2__DIS_DUAL_L2_REQ_MASK 0x02000000L |
7910 | #define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
7911 | #define SQG_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L |
7912 | #define SQG_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L |
7913 | #define SQG_UTCL0_CNTL2__GPUVM_16K_DEF_MASK 0x20000000L |
7914 | #define SQG_UTCL0_CNTL2__RESERVED_MASK 0xC0000000L |
7915 | //SQG_UTCL0_STATUS |
7916 | #define SQG_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 |
7917 | #define SQG_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 |
7918 | #define SQG_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 |
7919 | #define SQG_UTCL0_STATUS__RESERVED__SHIFT 0x3 |
7920 | #define SQG_UTCL0_STATUS__UNUSED__SHIFT 0x8 |
7921 | #define SQG_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L |
7922 | #define SQG_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L |
7923 | #define SQG_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L |
7924 | #define SQG_UTCL0_STATUS__RESERVED_MASK 0x000000F8L |
7925 | #define SQG_UTCL0_STATUS__UNUSED_MASK 0xFFFFFF00L |
7926 | //SQG_CONFIG |
7927 | #define SQG_CONFIG__UTCL0_PREFETCH_PAGE__SHIFT 0x0 |
7928 | #define SQG_CONFIG__UTCL0_RETRY_TIMER__SHIFT 0x4 |
7929 | #define SQG_CONFIG__UTCL0_PREFETCH_PAGE_MASK 0x0000000FL |
7930 | #define SQG_CONFIG__UTCL0_RETRY_TIMER_MASK 0x000007F0L |
7931 | //SQ_SHADER_TBA_LO |
7932 | #define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 |
7933 | #define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL |
7934 | //SQ_SHADER_TBA_HI |
7935 | #define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 |
7936 | #define SQ_SHADER_TBA_HI__TRAP_EN__SHIFT 0x1f |
7937 | #define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL |
7938 | #define SQ_SHADER_TBA_HI__TRAP_EN_MASK 0x80000000L |
7939 | //SQ_SHADER_TMA_LO |
7940 | #define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 |
7941 | #define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL |
7942 | //SQ_SHADER_TMA_HI |
7943 | #define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 |
7944 | #define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL |
7945 | //SQ_WATCH0_ADDR_H |
7946 | #define SQ_WATCH0_ADDR_H__ADDR__SHIFT 0x0 |
7947 | #define SQ_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL |
7948 | //SQ_WATCH0_ADDR_L |
7949 | #define SQ_WATCH0_ADDR_L__ADDR__SHIFT 0x6 |
7950 | #define SQ_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
7951 | //SQ_WATCH0_CNTL |
7952 | #define SQ_WATCH0_CNTL__MASK__SHIFT 0x0 |
7953 | #define SQ_WATCH0_CNTL__VMID__SHIFT 0x18 |
7954 | #define SQ_WATCH0_CNTL__MODE__SHIFT 0x1d |
7955 | #define SQ_WATCH0_CNTL__VALID__SHIFT 0x1f |
7956 | #define SQ_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL |
7957 | #define SQ_WATCH0_CNTL__VMID_MASK 0x0F000000L |
7958 | #define SQ_WATCH0_CNTL__MODE_MASK 0x60000000L |
7959 | #define SQ_WATCH0_CNTL__VALID_MASK 0x80000000L |
7960 | //SQ_WATCH1_ADDR_H |
7961 | #define SQ_WATCH1_ADDR_H__ADDR__SHIFT 0x0 |
7962 | #define SQ_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL |
7963 | //SQ_WATCH1_ADDR_L |
7964 | #define SQ_WATCH1_ADDR_L__ADDR__SHIFT 0x6 |
7965 | #define SQ_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
7966 | //SQ_WATCH1_CNTL |
7967 | #define SQ_WATCH1_CNTL__MASK__SHIFT 0x0 |
7968 | #define SQ_WATCH1_CNTL__VMID__SHIFT 0x18 |
7969 | #define SQ_WATCH1_CNTL__MODE__SHIFT 0x1d |
7970 | #define SQ_WATCH1_CNTL__VALID__SHIFT 0x1f |
7971 | #define SQ_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL |
7972 | #define SQ_WATCH1_CNTL__VMID_MASK 0x0F000000L |
7973 | #define SQ_WATCH1_CNTL__MODE_MASK 0x60000000L |
7974 | #define SQ_WATCH1_CNTL__VALID_MASK 0x80000000L |
7975 | //SQ_WATCH2_ADDR_H |
7976 | #define SQ_WATCH2_ADDR_H__ADDR__SHIFT 0x0 |
7977 | #define SQ_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL |
7978 | //SQ_WATCH2_ADDR_L |
7979 | #define SQ_WATCH2_ADDR_L__ADDR__SHIFT 0x6 |
7980 | #define SQ_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
7981 | //SQ_WATCH2_CNTL |
7982 | #define SQ_WATCH2_CNTL__MASK__SHIFT 0x0 |
7983 | #define SQ_WATCH2_CNTL__VMID__SHIFT 0x18 |
7984 | #define SQ_WATCH2_CNTL__MODE__SHIFT 0x1d |
7985 | #define SQ_WATCH2_CNTL__VALID__SHIFT 0x1f |
7986 | #define SQ_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL |
7987 | #define SQ_WATCH2_CNTL__VMID_MASK 0x0F000000L |
7988 | #define SQ_WATCH2_CNTL__MODE_MASK 0x60000000L |
7989 | #define SQ_WATCH2_CNTL__VALID_MASK 0x80000000L |
7990 | //SQ_WATCH3_ADDR_H |
7991 | #define SQ_WATCH3_ADDR_H__ADDR__SHIFT 0x0 |
7992 | #define SQ_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL |
7993 | //SQ_WATCH3_ADDR_L |
7994 | #define SQ_WATCH3_ADDR_L__ADDR__SHIFT 0x6 |
7995 | #define SQ_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
7996 | //SQ_WATCH3_CNTL |
7997 | #define SQ_WATCH3_CNTL__MASK__SHIFT 0x0 |
7998 | #define SQ_WATCH3_CNTL__VMID__SHIFT 0x18 |
7999 | #define SQ_WATCH3_CNTL__MODE__SHIFT 0x1d |
8000 | #define SQ_WATCH3_CNTL__VALID__SHIFT 0x1f |
8001 | #define SQ_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL |
8002 | #define SQ_WATCH3_CNTL__VMID_MASK 0x0F000000L |
8003 | #define SQ_WATCH3_CNTL__MODE_MASK 0x60000000L |
8004 | #define SQ_WATCH3_CNTL__VALID_MASK 0x80000000L |
8005 | //SQ_THREAD_TRACE_BUF0_BASE |
8006 | #define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO__SHIFT 0x0 |
8007 | #define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO_MASK 0xFFFFFFFFL |
8008 | //SQ_THREAD_TRACE_BUF0_SIZE |
8009 | #define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI__SHIFT 0x0 |
8010 | #define SQ_THREAD_TRACE_BUF0_SIZE__SIZE__SHIFT 0x8 |
8011 | #define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI_MASK 0x0000000FL |
8012 | #define SQ_THREAD_TRACE_BUF0_SIZE__SIZE_MASK 0x3FFFFF00L |
8013 | //SQ_THREAD_TRACE_BUF1_BASE |
8014 | #define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO__SHIFT 0x0 |
8015 | #define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO_MASK 0xFFFFFFFFL |
8016 | //SQ_THREAD_TRACE_BUF1_SIZE |
8017 | #define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI__SHIFT 0x0 |
8018 | #define SQ_THREAD_TRACE_BUF1_SIZE__SIZE__SHIFT 0x8 |
8019 | #define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI_MASK 0x0000000FL |
8020 | #define SQ_THREAD_TRACE_BUF1_SIZE__SIZE_MASK 0x3FFFFF00L |
8021 | //SQ_THREAD_TRACE_WPTR |
8022 | #define SQ_THREAD_TRACE_WPTR__OFFSET__SHIFT 0x0 |
8023 | #define SQ_THREAD_TRACE_WPTR__BUFFER_ID__SHIFT 0x1f |
8024 | #define SQ_THREAD_TRACE_WPTR__OFFSET_MASK 0x1FFFFFFFL |
8025 | #define SQ_THREAD_TRACE_WPTR__BUFFER_ID_MASK 0x80000000L |
8026 | //SQ_THREAD_TRACE_MASK |
8027 | #define SQ_THREAD_TRACE_MASK__SIMD_SEL__SHIFT 0x0 |
8028 | #define SQ_THREAD_TRACE_MASK__WGP_SEL__SHIFT 0x4 |
8029 | #define SQ_THREAD_TRACE_MASK__SA_SEL__SHIFT 0x9 |
8030 | #define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE__SHIFT 0xa |
8031 | #define SQ_THREAD_TRACE_MASK__SIMD_SEL_MASK 0x00000003L |
8032 | #define SQ_THREAD_TRACE_MASK__WGP_SEL_MASK 0x000000F0L |
8033 | #define SQ_THREAD_TRACE_MASK__SA_SEL_MASK 0x00000200L |
8034 | #define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE_MASK 0x0001FC00L |
8035 | //SQ_THREAD_TRACE_TOKEN_MASK |
8036 | #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE__SHIFT 0x0 |
8037 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE__SHIFT 0x10 |
8038 | #define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE__SHIFT 0x18 |
8039 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL__SHIFT 0x1f |
8040 | #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE_MASK 0x00000FFFL |
8041 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE_MASK 0x00FF0000L |
8042 | #define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE_MASK 0x03000000L |
8043 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL_MASK 0x80000000L |
8044 | //SQ_THREAD_TRACE_CTRL |
8045 | #define SQ_THREAD_TRACE_CTRL__MODE__SHIFT 0x0 |
8046 | #define SQ_THREAD_TRACE_CTRL__ALL_VMID__SHIFT 0x2 |
8047 | #define SQ_THREAD_TRACE_CTRL__CH_PERF_EN__SHIFT 0x3 |
8048 | #define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN__SHIFT 0x4 |
8049 | #define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER__SHIFT 0x5 |
8050 | #define SQ_THREAD_TRACE_CTRL__HIWATER__SHIFT 0x6 |
8051 | #define SQ_THREAD_TRACE_CTRL__REG_STALL_EN__SHIFT 0x9 |
8052 | #define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN__SHIFT 0xa |
8053 | #define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN__SHIFT 0xb |
8054 | #define SQ_THREAD_TRACE_CTRL__REG_DROP_ON_STALL__SHIFT 0xc |
8055 | #define SQ_THREAD_TRACE_CTRL__UTIL_TIMER__SHIFT 0xd |
8056 | #define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE__SHIFT 0xe |
8057 | #define SQ_THREAD_TRACE_CTRL__RT_FREQ__SHIFT 0x10 |
8058 | #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS__SHIFT 0x12 |
8059 | #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS__SHIFT 0x13 |
8060 | #define SQ_THREAD_TRACE_CTRL__CAPTURE_ALL__SHIFT 0x1e |
8061 | #define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN__SHIFT 0x1f |
8062 | #define SQ_THREAD_TRACE_CTRL__MODE_MASK 0x00000003L |
8063 | #define SQ_THREAD_TRACE_CTRL__ALL_VMID_MASK 0x00000004L |
8064 | #define SQ_THREAD_TRACE_CTRL__CH_PERF_EN_MASK 0x00000008L |
8065 | #define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN_MASK 0x00000010L |
8066 | #define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER_MASK 0x00000020L |
8067 | #define SQ_THREAD_TRACE_CTRL__HIWATER_MASK 0x000001C0L |
8068 | #define SQ_THREAD_TRACE_CTRL__REG_STALL_EN_MASK 0x00000200L |
8069 | #define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN_MASK 0x00000400L |
8070 | #define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN_MASK 0x00000800L |
8071 | #define SQ_THREAD_TRACE_CTRL__REG_DROP_ON_STALL_MASK 0x00001000L |
8072 | #define SQ_THREAD_TRACE_CTRL__UTIL_TIMER_MASK 0x00002000L |
8073 | #define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE_MASK 0x0000C000L |
8074 | #define SQ_THREAD_TRACE_CTRL__RT_FREQ_MASK 0x00030000L |
8075 | #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS_MASK 0x00040000L |
8076 | #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS_MASK 0x00080000L |
8077 | #define SQ_THREAD_TRACE_CTRL__CAPTURE_ALL_MASK 0x40000000L |
8078 | #define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN_MASK 0x80000000L |
8079 | //SQ_THREAD_TRACE_STATUS |
8080 | #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 |
8081 | #define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0xc |
8082 | #define SQ_THREAD_TRACE_STATUS__UTC_ERR__SHIFT 0x18 |
8083 | #define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x19 |
8084 | #define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_OVERFLOW__SHIFT 0x1a |
8085 | #define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_STALL__SHIFT 0x1b |
8086 | #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x00000FFFL |
8087 | #define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x00FFF000L |
8088 | #define SQ_THREAD_TRACE_STATUS__UTC_ERR_MASK 0x01000000L |
8089 | #define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x02000000L |
8090 | #define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_OVERFLOW_MASK 0x04000000L |
8091 | #define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_STALL_MASK 0x08000000L |
8092 | //SQ_THREAD_TRACE_DROPPED_CNTR |
8093 | #define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR__SHIFT 0x0 |
8094 | #define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR_MASK 0xFFFFFFFFL |
8095 | //SQ_THREAD_TRACE_GFX_DRAW_CNTR |
8096 | #define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR__SHIFT 0x0 |
8097 | #define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL |
8098 | //SQ_THREAD_TRACE_GFX_MARKER_CNTR |
8099 | #define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR__SHIFT 0x0 |
8100 | #define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL |
8101 | //SQ_THREAD_TRACE_HP3D_DRAW_CNTR |
8102 | #define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR__SHIFT 0x0 |
8103 | #define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL |
8104 | //SQ_THREAD_TRACE_HP3D_MARKER_CNTR |
8105 | #define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR__SHIFT 0x0 |
8106 | #define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL |
8107 | //SQ_IND_INDEX |
8108 | #define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 |
8109 | #define SQ_IND_INDEX__WORKITEM_ID__SHIFT 0x5 |
8110 | #define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xb |
8111 | #define SQ_IND_INDEX__INDEX__SHIFT 0x10 |
8112 | #define SQ_IND_INDEX__WAVE_ID_MASK 0x0000001FL |
8113 | #define SQ_IND_INDEX__WORKITEM_ID_MASK 0x000007E0L |
8114 | #define SQ_IND_INDEX__AUTO_INCR_MASK 0x00000800L |
8115 | #define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L |
8116 | //SQ_IND_DATA |
8117 | #define SQ_IND_DATA__DATA__SHIFT 0x0 |
8118 | #define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL |
8119 | //SQ_CMD |
8120 | #define SQ_CMD__CMD__SHIFT 0x0 |
8121 | #define SQ_CMD__MODE__SHIFT 0x4 |
8122 | #define SQ_CMD__CHECK_VMID__SHIFT 0x7 |
8123 | #define SQ_CMD__DATA__SHIFT 0x8 |
8124 | #define SQ_CMD__WAVE_ID__SHIFT 0x10 |
8125 | #define SQ_CMD__QUEUE_ID__SHIFT 0x18 |
8126 | #define SQ_CMD__VM_ID__SHIFT 0x1c |
8127 | #define SQ_CMD__CMD_MASK 0x0000000FL |
8128 | #define SQ_CMD__MODE_MASK 0x00000070L |
8129 | #define SQ_CMD__CHECK_VMID_MASK 0x00000080L |
8130 | #define SQ_CMD__DATA_MASK 0x00000F00L |
8131 | #define SQ_CMD__WAVE_ID_MASK 0x001F0000L |
8132 | #define SQ_CMD__QUEUE_ID_MASK 0x07000000L |
8133 | #define SQ_CMD__VM_ID_MASK 0xF0000000L |
8134 | //SQ_TIME_HI |
8135 | #define SQ_TIME_HI__TIME__SHIFT 0x0 |
8136 | #define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL |
8137 | //SQ_TIME_LO |
8138 | #define SQ_TIME_LO__TIME__SHIFT 0x0 |
8139 | #define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL |
8140 | //SQ_LB_CTR_CTRL |
8141 | #define SQ_LB_CTR_CTRL__START__SHIFT 0x0 |
8142 | #define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 |
8143 | #define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 |
8144 | #define SQ_LB_CTR_CTRL__START_MASK 0x00000001L |
8145 | #define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L |
8146 | #define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L |
8147 | //SQ_LB_DATA0 |
8148 | #define SQ_LB_DATA0__DATA__SHIFT 0x0 |
8149 | #define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL |
8150 | //SQ_LB_DATA1 |
8151 | #define SQ_LB_DATA1__DATA__SHIFT 0x0 |
8152 | #define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL |
8153 | //SQ_LB_DATA2 |
8154 | #define SQ_LB_DATA2__DATA__SHIFT 0x0 |
8155 | #define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL |
8156 | //SQ_LB_DATA3 |
8157 | #define SQ_LB_DATA3__DATA__SHIFT 0x0 |
8158 | #define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL |
8159 | //SQ_LB_CTR_SEL0 |
8160 | #define SQ_LB_CTR_SEL0__SEL0__SHIFT 0x0 |
8161 | #define SQ_LB_CTR_SEL0__DIV0__SHIFT 0xf |
8162 | #define SQ_LB_CTR_SEL0__SEL1__SHIFT 0x10 |
8163 | #define SQ_LB_CTR_SEL0__DIV1__SHIFT 0x1f |
8164 | #define SQ_LB_CTR_SEL0__SEL0_MASK 0x000000FFL |
8165 | #define SQ_LB_CTR_SEL0__DIV0_MASK 0x00008000L |
8166 | #define SQ_LB_CTR_SEL0__SEL1_MASK 0x00FF0000L |
8167 | #define SQ_LB_CTR_SEL0__DIV1_MASK 0x80000000L |
8168 | //SQ_LB_CTR_SEL1 |
8169 | #define SQ_LB_CTR_SEL1__SEL2__SHIFT 0x0 |
8170 | #define SQ_LB_CTR_SEL1__DIV2__SHIFT 0xf |
8171 | #define SQ_LB_CTR_SEL1__SEL3__SHIFT 0x10 |
8172 | #define SQ_LB_CTR_SEL1__DIV3__SHIFT 0x1f |
8173 | #define SQ_LB_CTR_SEL1__SEL2_MASK 0x000000FFL |
8174 | #define SQ_LB_CTR_SEL1__DIV2_MASK 0x00008000L |
8175 | #define SQ_LB_CTR_SEL1__SEL3_MASK 0x00FF0000L |
8176 | #define SQ_LB_CTR_SEL1__DIV3_MASK 0x80000000L |
8177 | //SQ_EDC_CNT |
8178 | #define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0 |
8179 | #define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2 |
8180 | #define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4 |
8181 | #define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6 |
8182 | #define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8 |
8183 | #define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa |
8184 | #define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc |
8185 | #define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe |
8186 | #define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10 |
8187 | #define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12 |
8188 | #define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14 |
8189 | #define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16 |
8190 | #define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18 |
8191 | #define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a |
8192 | #define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L |
8193 | #define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL |
8194 | #define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L |
8195 | #define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L |
8196 | #define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L |
8197 | #define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L |
8198 | #define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L |
8199 | #define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L |
8200 | #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L |
8201 | #define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L |
8202 | #define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L |
8203 | #define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L |
8204 | #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L |
8205 | #define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L |
8206 | //SQ_EDC_FUE_CNTL |
8207 | #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 |
8208 | #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 |
8209 | #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL |
8210 | #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L |
8211 | //SQ_WREXEC_EXEC_HI |
8212 | #define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 |
8213 | #define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a |
8214 | #define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c |
8215 | #define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f |
8216 | #define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL |
8217 | #define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L |
8218 | #define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L |
8219 | #define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L |
8220 | //SQ_WREXEC_EXEC_LO |
8221 | #define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 |
8222 | #define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL |
8223 | //SQC_ICACHE_UTCL0_CNTL1 |
8224 | #define SQC_ICACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
8225 | #define SQC_ICACHE_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
8226 | #define SQC_ICACHE_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
8227 | #define SQC_ICACHE_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 |
8228 | #define SQC_ICACHE_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
8229 | #define SQC_ICACHE_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 |
8230 | #define SQC_ICACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
8231 | #define SQC_ICACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
8232 | #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13 |
8233 | #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 |
8234 | #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 |
8235 | #define SQC_ICACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
8236 | #define SQC_ICACHE_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a |
8237 | #define SQC_ICACHE_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
8238 | #define SQC_ICACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
8239 | #define SQC_ICACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
8240 | #define SQC_ICACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
8241 | #define SQC_ICACHE_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
8242 | #define SQC_ICACHE_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
8243 | #define SQC_ICACHE_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L |
8244 | #define SQC_ICACHE_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
8245 | #define SQC_ICACHE_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L |
8246 | #define SQC_ICACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
8247 | #define SQC_ICACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
8248 | #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L |
8249 | #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L |
8250 | #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L |
8251 | #define SQC_ICACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
8252 | #define SQC_ICACHE_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L |
8253 | #define SQC_ICACHE_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
8254 | #define SQC_ICACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
8255 | #define SQC_ICACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
8256 | //SQC_ICACHE_UTCL0_CNTL2 |
8257 | #define SQC_ICACHE_UTCL0_CNTL2__SPARE__SHIFT 0x0 |
8258 | #define SQC_ICACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 |
8259 | #define SQC_ICACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
8260 | #define SQC_ICACHE_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa |
8261 | #define SQC_ICACHE_UTCL0_CNTL2__DIS_EDC__SHIFT 0xb |
8262 | #define SQC_ICACHE_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
8263 | #define SQC_ICACHE_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
8264 | #define SQC_ICACHE_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe |
8265 | #define SQC_ICACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
8266 | #define SQC_ICACHE_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT 0x10 |
8267 | #define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
8268 | #define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 |
8269 | #define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
8270 | #define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 |
8271 | #define SQC_ICACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
8272 | #define SQC_ICACHE_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b |
8273 | #define SQC_ICACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c |
8274 | #define SQC_ICACHE_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT 0x1d |
8275 | #define SQC_ICACHE_UTCL0_CNTL2__SPARE_MASK 0x000000FFL |
8276 | #define SQC_ICACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L |
8277 | #define SQC_ICACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
8278 | #define SQC_ICACHE_UTCL0_CNTL2__LINE_VALID_MASK 0x00000400L |
8279 | #define SQC_ICACHE_UTCL0_CNTL2__DIS_EDC_MASK 0x00000800L |
8280 | #define SQC_ICACHE_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
8281 | #define SQC_ICACHE_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
8282 | #define SQC_ICACHE_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
8283 | #define SQC_ICACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
8284 | #define SQC_ICACHE_UTCL0_CNTL2__ARB_BURST_MODE_MASK 0x00030000L |
8285 | #define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
8286 | #define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L |
8287 | #define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
8288 | #define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L |
8289 | #define SQC_ICACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
8290 | #define SQC_ICACHE_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L |
8291 | #define SQC_ICACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L |
8292 | #define SQC_ICACHE_UTCL0_CNTL2__GPUVM_16K_DEF_MASK 0x20000000L |
8293 | //SQC_DCACHE_UTCL0_CNTL1 |
8294 | #define SQC_DCACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
8295 | #define SQC_DCACHE_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
8296 | #define SQC_DCACHE_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
8297 | #define SQC_DCACHE_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 |
8298 | #define SQC_DCACHE_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
8299 | #define SQC_DCACHE_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 |
8300 | #define SQC_DCACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
8301 | #define SQC_DCACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
8302 | #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13 |
8303 | #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 |
8304 | #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 |
8305 | #define SQC_DCACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
8306 | #define SQC_DCACHE_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a |
8307 | #define SQC_DCACHE_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
8308 | #define SQC_DCACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
8309 | #define SQC_DCACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
8310 | #define SQC_DCACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
8311 | #define SQC_DCACHE_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
8312 | #define SQC_DCACHE_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
8313 | #define SQC_DCACHE_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L |
8314 | #define SQC_DCACHE_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
8315 | #define SQC_DCACHE_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L |
8316 | #define SQC_DCACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
8317 | #define SQC_DCACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
8318 | #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L |
8319 | #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L |
8320 | #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L |
8321 | #define SQC_DCACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
8322 | #define SQC_DCACHE_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L |
8323 | #define SQC_DCACHE_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
8324 | #define SQC_DCACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
8325 | #define SQC_DCACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
8326 | //SQC_DCACHE_UTCL0_CNTL2 |
8327 | #define SQC_DCACHE_UTCL0_CNTL2__SPARE__SHIFT 0x0 |
8328 | #define SQC_DCACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 |
8329 | #define SQC_DCACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
8330 | #define SQC_DCACHE_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa |
8331 | #define SQC_DCACHE_UTCL0_CNTL2__DIS_EDC__SHIFT 0xb |
8332 | #define SQC_DCACHE_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
8333 | #define SQC_DCACHE_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
8334 | #define SQC_DCACHE_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe |
8335 | #define SQC_DCACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
8336 | #define SQC_DCACHE_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT 0x10 |
8337 | #define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
8338 | #define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 |
8339 | #define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
8340 | #define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 |
8341 | #define SQC_DCACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
8342 | #define SQC_DCACHE_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b |
8343 | #define SQC_DCACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c |
8344 | #define SQC_DCACHE_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT 0x1d |
8345 | #define SQC_DCACHE_UTCL0_CNTL2__SPARE_MASK 0x000000FFL |
8346 | #define SQC_DCACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L |
8347 | #define SQC_DCACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
8348 | #define SQC_DCACHE_UTCL0_CNTL2__LINE_VALID_MASK 0x00000400L |
8349 | #define SQC_DCACHE_UTCL0_CNTL2__DIS_EDC_MASK 0x00000800L |
8350 | #define SQC_DCACHE_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
8351 | #define SQC_DCACHE_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
8352 | #define SQC_DCACHE_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
8353 | #define SQC_DCACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
8354 | #define SQC_DCACHE_UTCL0_CNTL2__ARB_BURST_MODE_MASK 0x00030000L |
8355 | #define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
8356 | #define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L |
8357 | #define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
8358 | #define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L |
8359 | #define SQC_DCACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
8360 | #define SQC_DCACHE_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L |
8361 | #define SQC_DCACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L |
8362 | #define SQC_DCACHE_UTCL0_CNTL2__GPUVM_16K_DEF_MASK 0x20000000L |
8363 | //SQC_ICACHE_UTCL0_STATUS |
8364 | #define SQC_ICACHE_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 |
8365 | #define SQC_ICACHE_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 |
8366 | #define SQC_ICACHE_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 |
8367 | #define SQC_ICACHE_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L |
8368 | #define SQC_ICACHE_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L |
8369 | #define SQC_ICACHE_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L |
8370 | //SQC_DCACHE_UTCL0_STATUS |
8371 | #define SQC_DCACHE_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 |
8372 | #define SQC_DCACHE_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 |
8373 | #define SQC_DCACHE_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 |
8374 | #define SQC_DCACHE_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L |
8375 | #define SQC_DCACHE_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L |
8376 | #define SQC_DCACHE_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L |
8377 | //SQC_MISC_CONFIG |
8378 | #define SQC_MISC_CONFIG__PERFTOKEN_DELAY__SHIFT 0x0 |
8379 | #define SQC_MISC_CONFIG__SQC_SPI_TTRACE_FGCG_OVERRIDE__SHIFT 0x5 |
8380 | #define SQC_MISC_CONFIG__PERFTOKEN_DELAY_MASK 0x0000001FL |
8381 | #define SQC_MISC_CONFIG__SQC_SPI_TTRACE_FGCG_OVERRIDE_MASK 0x00000020L |
8382 | |
8383 | |
8384 | // addressBlock: gc_shsdec |
8385 | //SX_DEBUG_1 |
8386 | #define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 |
8387 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 |
8388 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 |
8389 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa |
8390 | #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb |
8391 | #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc |
8392 | #define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT 0xd |
8393 | #define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS__SHIFT 0xe |
8394 | #define SX_DEBUG_1__DISABLE_RAM_FGCG__SHIFT 0xf |
8395 | #define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT__SHIFT 0x10 |
8396 | #define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT__SHIFT 0x11 |
8397 | #define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x12 |
8398 | #define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL |
8399 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L |
8400 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L |
8401 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L |
8402 | #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L |
8403 | #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L |
8404 | #define SX_DEBUG_1__DISABLE_REP_FGCG_MASK 0x00002000L |
8405 | #define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS_MASK 0x00004000L |
8406 | #define SX_DEBUG_1__DISABLE_RAM_FGCG_MASK 0x00008000L |
8407 | #define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT_MASK 0x00010000L |
8408 | #define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT_MASK 0x00020000L |
8409 | #define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFC0000L |
8410 | //SPI_PS_MAX_WAVE_ID |
8411 | #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
8412 | #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10 |
8413 | #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
8414 | #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L |
8415 | //SPI_START_PHASE |
8416 | #define SPI_START_PHASE__PC_X_PHASE_SE0__SHIFT 0x0 |
8417 | #define SPI_START_PHASE__PC_X_PHASE_SE1__SHIFT 0x2 |
8418 | #define SPI_START_PHASE__PC_X_PHASE_SE2__SHIFT 0x4 |
8419 | #define SPI_START_PHASE__PC_X_PHASE_SE3__SHIFT 0x6 |
8420 | #define SPI_START_PHASE__PC_X_PHASE_SE0_MASK 0x00000003L |
8421 | #define SPI_START_PHASE__PC_X_PHASE_SE1_MASK 0x0000000CL |
8422 | #define SPI_START_PHASE__PC_X_PHASE_SE2_MASK 0x00000030L |
8423 | #define SPI_START_PHASE__PC_X_PHASE_SE3_MASK 0x000000C0L |
8424 | //SPI_GFX_CNTL |
8425 | #define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 |
8426 | #define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L |
8427 | //SPI_USER_ACCUM_VMID_CNTL |
8428 | #define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM__SHIFT 0x0 |
8429 | #define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM_MASK 0x0000000FL |
8430 | //SPI_CONFIG_CNTL |
8431 | #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 |
8432 | #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 |
8433 | #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 |
8434 | #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 |
8435 | #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a |
8436 | #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b |
8437 | #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c |
8438 | #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d |
8439 | #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e |
8440 | #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL |
8441 | #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L |
8442 | #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L |
8443 | #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L |
8444 | #define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L |
8445 | #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L |
8446 | #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L |
8447 | #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L |
8448 | #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L |
8449 | //SPI_DSM_CNTL |
8450 | #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
8451 | #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
8452 | #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
8453 | #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
8454 | //SPI_DSM_CNTL2 |
8455 | #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
8456 | #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
8457 | #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x3 |
8458 | #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
8459 | #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
8460 | #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000001F8L |
8461 | //SPI_EDC_CNT |
8462 | #define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0 |
8463 | #define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L |
8464 | //SPI_WAVE_LIMIT_CNTL |
8465 | #define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT 0x0 |
8466 | #define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT 0x2 |
8467 | #define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT 0x4 |
8468 | #define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT 0x6 |
8469 | #define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK 0x00000003L |
8470 | #define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK 0x0000000CL |
8471 | #define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK 0x00000030L |
8472 | #define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK 0x000000C0L |
8473 | //SPI_CONFIG_CNTL_2 |
8474 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 |
8475 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 |
8476 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL |
8477 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L |
8478 | //SPI_CONFIG_CNTL_1 |
8479 | #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 |
8480 | #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 |
8481 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x5 |
8482 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 |
8483 | #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 |
8484 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 |
8485 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa |
8486 | #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe |
8487 | #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf |
8488 | #define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT__SHIFT 0x10 |
8489 | #define SPI_CONFIG_CNTL_1__EN_USER_ACCUM__SHIFT 0x15 |
8490 | #define SPI_CONFIG_CNTL_1__RESERVED__SHIFT 0x16 |
8491 | #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL |
8492 | #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L |
8493 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000060L |
8494 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L |
8495 | #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L |
8496 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L |
8497 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L |
8498 | #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L |
8499 | #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L |
8500 | #define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT_MASK 0x001F0000L |
8501 | #define SPI_CONFIG_CNTL_1__EN_USER_ACCUM_MASK 0x00200000L |
8502 | #define SPI_CONFIG_CNTL_1__RESERVED_MASK 0xFFC00000L |
8503 | //SPI_WF_LIFETIME_CNTL |
8504 | #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 |
8505 | #define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 |
8506 | #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL |
8507 | #define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L |
8508 | //SPI_WF_LIFETIME_LIMIT_0 |
8509 | #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 |
8510 | #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f |
8511 | #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL |
8512 | #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L |
8513 | //SPI_WF_LIFETIME_LIMIT_1 |
8514 | #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 |
8515 | #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f |
8516 | #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL |
8517 | #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L |
8518 | //SPI_WF_LIFETIME_LIMIT_2 |
8519 | #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 |
8520 | #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f |
8521 | #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL |
8522 | #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L |
8523 | //SPI_WF_LIFETIME_LIMIT_3 |
8524 | #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 |
8525 | #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f |
8526 | #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL |
8527 | #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L |
8528 | //SPI_WF_LIFETIME_LIMIT_4 |
8529 | #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 |
8530 | #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f |
8531 | #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL |
8532 | #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L |
8533 | //SPI_WF_LIFETIME_LIMIT_5 |
8534 | #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 |
8535 | #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f |
8536 | #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL |
8537 | #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L |
8538 | //SPI_WF_LIFETIME_LIMIT_6 |
8539 | #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 |
8540 | #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f |
8541 | #define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL |
8542 | #define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L |
8543 | //SPI_WF_LIFETIME_LIMIT_7 |
8544 | #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 |
8545 | #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f |
8546 | #define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL |
8547 | #define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L |
8548 | //SPI_WF_LIFETIME_LIMIT_8 |
8549 | #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 |
8550 | #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f |
8551 | #define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL |
8552 | #define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L |
8553 | //SPI_WF_LIFETIME_LIMIT_9 |
8554 | #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 |
8555 | #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f |
8556 | #define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL |
8557 | #define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L |
8558 | //SPI_WF_LIFETIME_STATUS_0 |
8559 | #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 |
8560 | #define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f |
8561 | #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL |
8562 | #define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L |
8563 | //SPI_WF_LIFETIME_STATUS_1 |
8564 | #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 |
8565 | #define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f |
8566 | #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL |
8567 | #define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L |
8568 | //SPI_WF_LIFETIME_STATUS_2 |
8569 | #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 |
8570 | #define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f |
8571 | #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL |
8572 | #define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L |
8573 | //SPI_WF_LIFETIME_STATUS_3 |
8574 | #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 |
8575 | #define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f |
8576 | #define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL |
8577 | #define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L |
8578 | //SPI_WF_LIFETIME_STATUS_4 |
8579 | #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 |
8580 | #define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f |
8581 | #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL |
8582 | #define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L |
8583 | //SPI_WF_LIFETIME_STATUS_5 |
8584 | #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 |
8585 | #define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f |
8586 | #define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL |
8587 | #define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L |
8588 | //SPI_WF_LIFETIME_STATUS_6 |
8589 | #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 |
8590 | #define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f |
8591 | #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL |
8592 | #define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L |
8593 | //SPI_WF_LIFETIME_STATUS_7 |
8594 | #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 |
8595 | #define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f |
8596 | #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL |
8597 | #define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L |
8598 | //SPI_WF_LIFETIME_STATUS_8 |
8599 | #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 |
8600 | #define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f |
8601 | #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL |
8602 | #define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L |
8603 | //SPI_WF_LIFETIME_STATUS_9 |
8604 | #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 |
8605 | #define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f |
8606 | #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL |
8607 | #define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L |
8608 | //SPI_WF_LIFETIME_STATUS_10 |
8609 | #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 |
8610 | #define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f |
8611 | #define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL |
8612 | #define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L |
8613 | //SPI_WF_LIFETIME_STATUS_11 |
8614 | #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 |
8615 | #define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f |
8616 | #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL |
8617 | #define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L |
8618 | //SPI_WF_LIFETIME_STATUS_12 |
8619 | #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 |
8620 | #define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f |
8621 | #define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL |
8622 | #define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L |
8623 | //SPI_WF_LIFETIME_STATUS_13 |
8624 | #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 |
8625 | #define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f |
8626 | #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL |
8627 | #define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L |
8628 | //SPI_WF_LIFETIME_STATUS_14 |
8629 | #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 |
8630 | #define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f |
8631 | #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL |
8632 | #define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L |
8633 | //SPI_WF_LIFETIME_STATUS_15 |
8634 | #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 |
8635 | #define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f |
8636 | #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL |
8637 | #define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L |
8638 | //SPI_WF_LIFETIME_STATUS_16 |
8639 | #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 |
8640 | #define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f |
8641 | #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL |
8642 | #define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L |
8643 | //SPI_WF_LIFETIME_STATUS_17 |
8644 | #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 |
8645 | #define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f |
8646 | #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL |
8647 | #define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L |
8648 | //SPI_WF_LIFETIME_STATUS_18 |
8649 | #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 |
8650 | #define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f |
8651 | #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL |
8652 | #define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L |
8653 | //SPI_WF_LIFETIME_STATUS_19 |
8654 | #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 |
8655 | #define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f |
8656 | #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL |
8657 | #define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L |
8658 | //SPI_WF_LIFETIME_STATUS_20 |
8659 | #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 |
8660 | #define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f |
8661 | #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL |
8662 | #define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L |
8663 | //SPI_LB_CTR_CTRL |
8664 | #define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 |
8665 | #define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1 |
8666 | #define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3 |
8667 | #define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4 |
8668 | #define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L |
8669 | #define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L |
8670 | #define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L |
8671 | #define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L |
8672 | //SPI_LB_WGP_MASK |
8673 | #define SPI_LB_WGP_MASK__WGP_MASK__SHIFT 0x0 |
8674 | #define SPI_LB_WGP_MASK__WGP_MASK_MASK 0xFFFFL |
8675 | //SPI_LB_DATA_REG |
8676 | #define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 |
8677 | #define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL |
8678 | //SPI_PG_ENABLE_STATIC_WGP_MASK |
8679 | #define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK__SHIFT 0x0 |
8680 | #define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK_MASK 0xFFFFL |
8681 | //SPI_GDS_CREDITS |
8682 | #define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 |
8683 | #define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 |
8684 | #define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL |
8685 | #define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L |
8686 | //SPI_SX_EXPORT_BUFFER_SIZES |
8687 | #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 |
8688 | #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 |
8689 | #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL |
8690 | #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L |
8691 | //SPI_SX_SCOREBOARD_BUFFER_SIZES |
8692 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 |
8693 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 |
8694 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL |
8695 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L |
8696 | //SPI_CSQ_WF_ACTIVE_STATUS |
8697 | #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 |
8698 | #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL |
8699 | //SPI_CSQ_WF_ACTIVE_COUNT_0 |
8700 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 |
8701 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10 |
8702 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL |
8703 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L |
8704 | //SPI_CSQ_WF_ACTIVE_COUNT_1 |
8705 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 |
8706 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10 |
8707 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL |
8708 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L |
8709 | //SPI_CSQ_WF_ACTIVE_COUNT_2 |
8710 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 |
8711 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10 |
8712 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL |
8713 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L |
8714 | //SPI_CSQ_WF_ACTIVE_COUNT_3 |
8715 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 |
8716 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10 |
8717 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL |
8718 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L |
8719 | //SPI_CSQ_WF_ACTIVE_COUNT_4 |
8720 | #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 |
8721 | #define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10 |
8722 | #define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL |
8723 | #define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L |
8724 | //SPI_CSQ_WF_ACTIVE_COUNT_5 |
8725 | #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 |
8726 | #define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10 |
8727 | #define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL |
8728 | #define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L |
8729 | //SPI_CSQ_WF_ACTIVE_COUNT_6 |
8730 | #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 |
8731 | #define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10 |
8732 | #define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL |
8733 | #define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L |
8734 | //SPI_CSQ_WF_ACTIVE_COUNT_7 |
8735 | #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 |
8736 | #define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10 |
8737 | #define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL |
8738 | #define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L |
8739 | //SPI_LB_DATA_WAVES |
8740 | #define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0 |
8741 | #define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10 |
8742 | #define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL |
8743 | #define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L |
8744 | //SPI_LB_DATA_PERWGP_WAVE_HSGS |
8745 | #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS__SHIFT 0x0 |
8746 | #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS__SHIFT 0x10 |
8747 | #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS_MASK 0x0000FFFFL |
8748 | #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS_MASK 0xFFFF0000L |
8749 | //SPI_LB_DATA_PERWGP_WAVE_VSPS |
8750 | #define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_VS__SHIFT 0x0 |
8751 | #define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_PS__SHIFT 0x10 |
8752 | #define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_VS_MASK 0x0000FFFFL |
8753 | #define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_PS_MASK 0xFFFF0000L |
8754 | //SPI_LB_DATA_PERWGP_WAVE_CS |
8755 | #define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE__SHIFT 0x0 |
8756 | #define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE_MASK 0xFFFFL |
8757 | //SPI_P0_TRAP_SCREEN_PSBA_LO |
8758 | #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 |
8759 | #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
8760 | //SPI_P0_TRAP_SCREEN_PSBA_HI |
8761 | #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 |
8762 | #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL |
8763 | //SPI_P0_TRAP_SCREEN_PSMA_LO |
8764 | #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 |
8765 | #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
8766 | //SPI_P0_TRAP_SCREEN_PSMA_HI |
8767 | #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 |
8768 | #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL |
8769 | //SPI_P0_TRAP_SCREEN_GPR_MIN |
8770 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 |
8771 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 |
8772 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL |
8773 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L |
8774 | //SPI_P1_TRAP_SCREEN_PSBA_LO |
8775 | #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 |
8776 | #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
8777 | //SPI_P1_TRAP_SCREEN_PSBA_HI |
8778 | #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 |
8779 | #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL |
8780 | //SPI_P1_TRAP_SCREEN_PSMA_LO |
8781 | #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 |
8782 | #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
8783 | //SPI_P1_TRAP_SCREEN_PSMA_HI |
8784 | #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 |
8785 | #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL |
8786 | //SPI_P1_TRAP_SCREEN_GPR_MIN |
8787 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 |
8788 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 |
8789 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL |
8790 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L |
8791 | |
8792 | |
8793 | // addressBlock: gc_tpdec |
8794 | //TD_CNTL |
8795 | #define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0 |
8796 | #define TD_CNTL__DISABLE_SAMPLER_NEG_SCALED_NUM_CLAMP__SHIFT 0x3 |
8797 | #define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4 |
8798 | #define TD_CNTL__DISABLE_SAMPLER_MAX_NORM_NUM_CLAMP__SHIFT 0x6 |
8799 | #define TD_CNTL__PAD_STALL_EN__SHIFT 0x8 |
8800 | #define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9 |
8801 | #define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb |
8802 | #define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf |
8803 | #define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 |
8804 | #define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12 |
8805 | #define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 |
8806 | #define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 |
8807 | #define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15 |
8808 | #define TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT__SHIFT 0x16 |
8809 | #define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17 |
8810 | #define TD_CNTL__ARBITER_OLDEST_PRIORITY__SHIFT 0x19 |
8811 | #define TD_CNTL__DONE_SCOREBOARD_DEPTH__SHIFT 0x1a |
8812 | #define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L |
8813 | #define TD_CNTL__DISABLE_SAMPLER_NEG_SCALED_NUM_CLAMP_MASK 0x00000008L |
8814 | #define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L |
8815 | #define TD_CNTL__DISABLE_SAMPLER_MAX_NORM_NUM_CLAMP_MASK 0x00000040L |
8816 | #define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L |
8817 | #define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L |
8818 | #define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L |
8819 | #define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L |
8820 | #define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L |
8821 | #define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L |
8822 | #define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L |
8823 | #define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L |
8824 | #define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L |
8825 | #define TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT_MASK 0x00400000L |
8826 | #define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L |
8827 | #define TD_CNTL__ARBITER_OLDEST_PRIORITY_MASK 0x02000000L |
8828 | #define TD_CNTL__DONE_SCOREBOARD_DEPTH_MASK 0x7C000000L |
8829 | //TD_STATUS |
8830 | #define TD_STATUS__BUSY__SHIFT 0x1f |
8831 | #define TD_STATUS__BUSY_MASK 0x80000000L |
8832 | //TD_POWER_CNTL |
8833 | #define TD_POWER_CNTL__FORCE_SAMPLER_CLK_TO_CORE__SHIFT 0x0 |
8834 | #define TD_POWER_CNTL__FORCE_NOFILTER_CLK_TO_CORE__SHIFT 0x1 |
8835 | #define TD_POWER_CNTL__SAMPLER_CLK_VALID_DELAY__SHIFT 0x2 |
8836 | #define TD_POWER_CNTL__NOFILTER_CLK_VALID_DELAY__SHIFT 0x5 |
8837 | #define TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT__SHIFT 0x8 |
8838 | #define TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON__SHIFT 0x9 |
8839 | #define TD_POWER_CNTL__FORCE_SAMPLER_CLK_TO_CORE_MASK 0x00000001L |
8840 | #define TD_POWER_CNTL__FORCE_NOFILTER_CLK_TO_CORE_MASK 0x00000002L |
8841 | #define TD_POWER_CNTL__SAMPLER_CLK_VALID_DELAY_MASK 0x0000001CL |
8842 | #define TD_POWER_CNTL__NOFILTER_CLK_VALID_DELAY_MASK 0x000000E0L |
8843 | #define TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT_MASK 0x00000100L |
8844 | #define TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON_MASK 0x00000200L |
8845 | //TD_DSM_CNTL |
8846 | #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0 |
8847 | #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
8848 | #define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3 |
8849 | #define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
8850 | #define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 |
8851 | #define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
8852 | #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L |
8853 | #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
8854 | #define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L |
8855 | #define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
8856 | #define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
8857 | #define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
8858 | //TD_DSM_CNTL2 |
8859 | #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0 |
8860 | #define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2 |
8861 | #define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3 |
8862 | #define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5 |
8863 | #define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 |
8864 | #define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 |
8865 | #define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a |
8866 | #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L |
8867 | #define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L |
8868 | #define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L |
8869 | #define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L |
8870 | #define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
8871 | #define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L |
8872 | #define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L |
8873 | //TD_SCRATCH |
8874 | #define TD_SCRATCH__SCRATCH__SHIFT 0x0 |
8875 | #define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL |
8876 | //TA_POWER_CNTL |
8877 | #define TA_POWER_CNTL__SAMPLER_CLK_VALID_DELAY__SHIFT 0x0 |
8878 | #define TA_POWER_CNTL__SAMPLER_CLK_EN_MODE__SHIFT 0x3 |
8879 | #define TA_POWER_CNTL__NOSAMPLER_CLK_VALID_DELAY__SHIFT 0x10 |
8880 | #define TA_POWER_CNTL__NOSAMPLER_CLK_EN_MODE__SHIFT 0x13 |
8881 | #define TA_POWER_CNTL__SAMPLER_CLK_VALID_DELAY_MASK 0x00000007L |
8882 | #define TA_POWER_CNTL__SAMPLER_CLK_EN_MODE_MASK 0x00000008L |
8883 | #define TA_POWER_CNTL__NOSAMPLER_CLK_VALID_DELAY_MASK 0x00070000L |
8884 | #define TA_POWER_CNTL__NOSAMPLER_CLK_EN_MODE_MASK 0x00080000L |
8885 | //TA_CNTL |
8886 | #define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0 |
8887 | #define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 |
8888 | #define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 |
8889 | #define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL |
8890 | #define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L |
8891 | #define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L |
8892 | //TA_CNTL_AUX |
8893 | #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 |
8894 | #define TA_CNTL_AUX__RESERVED__SHIFT 0x1 |
8895 | #define TA_CNTL_AUX__DERIV_ADJUST_DIS__SHIFT 0x4 |
8896 | #define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5 |
8897 | #define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6 |
8898 | #define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7 |
8899 | #define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP__SHIFT 0x8 |
8900 | #define TA_CNTL_AUX__AUTO_ALIGN_FORMAT__SHIFT 0x9 |
8901 | #define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa |
8902 | #define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc |
8903 | #define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd |
8904 | #define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe |
8905 | #define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf |
8906 | #define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 |
8907 | #define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 |
8908 | #define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 |
8909 | #define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 |
8910 | #define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 |
8911 | #define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 |
8912 | #define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17 |
8913 | #define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18 |
8914 | #define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 |
8915 | #define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a |
8916 | #define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b |
8917 | #define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c |
8918 | #define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d |
8919 | #define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e |
8920 | #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L |
8921 | #define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL |
8922 | #define TA_CNTL_AUX__DERIV_ADJUST_DIS_MASK 0x00000010L |
8923 | #define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L |
8924 | #define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L |
8925 | #define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L |
8926 | #define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP_MASK 0x00000100L |
8927 | #define TA_CNTL_AUX__AUTO_ALIGN_FORMAT_MASK 0x00000200L |
8928 | #define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L |
8929 | #define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L |
8930 | #define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L |
8931 | #define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L |
8932 | #define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L |
8933 | #define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L |
8934 | #define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L |
8935 | #define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L |
8936 | #define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L |
8937 | #define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L |
8938 | #define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L |
8939 | #define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L |
8940 | #define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L |
8941 | #define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L |
8942 | #define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L |
8943 | #define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L |
8944 | #define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L |
8945 | #define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L |
8946 | #define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L |
8947 | //TA_RESERVED_010C |
8948 | #define TA_RESERVED_010C__Unused__SHIFT 0x0 |
8949 | #define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL |
8950 | //TA_STATUS |
8951 | #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc |
8952 | #define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd |
8953 | #define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe |
8954 | #define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 |
8955 | #define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 |
8956 | #define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 |
8957 | #define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 |
8958 | #define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 |
8959 | #define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 |
8960 | #define TA_STATUS__IN_BUSY__SHIFT 0x18 |
8961 | #define TA_STATUS__FG_BUSY__SHIFT 0x19 |
8962 | #define TA_STATUS__LA_BUSY__SHIFT 0x1a |
8963 | #define TA_STATUS__FL_BUSY__SHIFT 0x1b |
8964 | #define TA_STATUS__TA_BUSY__SHIFT 0x1c |
8965 | #define TA_STATUS__FA_BUSY__SHIFT 0x1d |
8966 | #define TA_STATUS__AL_BUSY__SHIFT 0x1e |
8967 | #define TA_STATUS__BUSY__SHIFT 0x1f |
8968 | #define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L |
8969 | #define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L |
8970 | #define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L |
8971 | #define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L |
8972 | #define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L |
8973 | #define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L |
8974 | #define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L |
8975 | #define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L |
8976 | #define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L |
8977 | #define TA_STATUS__IN_BUSY_MASK 0x01000000L |
8978 | #define TA_STATUS__FG_BUSY_MASK 0x02000000L |
8979 | #define TA_STATUS__LA_BUSY_MASK 0x04000000L |
8980 | #define TA_STATUS__FL_BUSY_MASK 0x08000000L |
8981 | #define TA_STATUS__TA_BUSY_MASK 0x10000000L |
8982 | #define TA_STATUS__FA_BUSY_MASK 0x20000000L |
8983 | #define TA_STATUS__AL_BUSY_MASK 0x40000000L |
8984 | #define TA_STATUS__BUSY_MASK 0x80000000L |
8985 | //TA_SCRATCH |
8986 | #define TA_SCRATCH__SCRATCH__SHIFT 0x0 |
8987 | #define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL |
8988 | |
8989 | |
8990 | // addressBlock: gc_gdsdec |
8991 | //GDS_CONFIG |
8992 | #define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 |
8993 | #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 |
8994 | #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 |
8995 | #define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 |
8996 | #define GDS_CONFIG__UNUSED__SHIFT 0x9 |
8997 | #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L |
8998 | #define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L |
8999 | #define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L |
9000 | #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L |
9001 | #define GDS_CONFIG__UNUSED_MASK 0xFFFFFE00L |
9002 | //GDS_CNTL_STATUS |
9003 | #define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 |
9004 | #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 |
9005 | #define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 |
9006 | #define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 |
9007 | #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 |
9008 | #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 |
9009 | #define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 |
9010 | #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7 |
9011 | #define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8 |
9012 | #define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9 |
9013 | #define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa |
9014 | #define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb |
9015 | #define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc |
9016 | #define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd |
9017 | #define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe |
9018 | #define GDS_CNTL_STATUS__UNUSED__SHIFT 0xf |
9019 | #define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L |
9020 | #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L |
9021 | #define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L |
9022 | #define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L |
9023 | #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L |
9024 | #define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L |
9025 | #define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L |
9026 | #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L |
9027 | #define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L |
9028 | #define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L |
9029 | #define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L |
9030 | #define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L |
9031 | #define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L |
9032 | #define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L |
9033 | #define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L |
9034 | #define GDS_CNTL_STATUS__UNUSED_MASK 0xFFFF8000L |
9035 | //GDS_ENHANCE |
9036 | #define GDS_ENHANCE__MISC__SHIFT 0x0 |
9037 | #define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 |
9038 | #define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 |
9039 | #define GDS_ENHANCE__UNUSED__SHIFT 0x12 |
9040 | #define GDS_ENHANCE__MISC_MASK 0x0000FFFFL |
9041 | #define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L |
9042 | #define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L |
9043 | #define GDS_ENHANCE__UNUSED_MASK 0xFFFC0000L |
9044 | //GDS_PROTECTION_FAULT |
9045 | #define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 |
9046 | #define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 |
9047 | #define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 |
9048 | #define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 |
9049 | #define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 |
9050 | #define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa |
9051 | #define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc |
9052 | #define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 |
9053 | #define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L |
9054 | #define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L |
9055 | #define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L |
9056 | #define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L |
9057 | #define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L |
9058 | #define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L |
9059 | #define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L |
9060 | #define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L |
9061 | //GDS_VM_PROTECTION_FAULT |
9062 | #define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 |
9063 | #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 |
9064 | #define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 |
9065 | #define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 |
9066 | #define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 |
9067 | #define GDS_VM_PROTECTION_FAULT__UNUSED1__SHIFT 0x6 |
9068 | #define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 |
9069 | #define GDS_VM_PROTECTION_FAULT__UNUSED2__SHIFT 0xc |
9070 | #define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 |
9071 | #define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L |
9072 | #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L |
9073 | #define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L |
9074 | #define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L |
9075 | #define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L |
9076 | #define GDS_VM_PROTECTION_FAULT__UNUSED1_MASK 0x000000C0L |
9077 | #define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L |
9078 | #define GDS_VM_PROTECTION_FAULT__UNUSED2_MASK 0x0000F000L |
9079 | #define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L |
9080 | //GDS_EDC_CNT |
9081 | #define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0 |
9082 | #define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2 |
9083 | #define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4 |
9084 | #define GDS_EDC_CNT__UNUSED__SHIFT 0x6 |
9085 | #define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L |
9086 | #define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL |
9087 | #define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L |
9088 | #define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L |
9089 | //GDS_EDC_GRBM_CNT |
9090 | #define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 |
9091 | #define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2 |
9092 | #define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4 |
9093 | #define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L |
9094 | #define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL |
9095 | #define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L |
9096 | //GDS_EDC_OA_DED |
9097 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 |
9098 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 |
9099 | #define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 |
9100 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3 |
9101 | #define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 |
9102 | #define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 |
9103 | #define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 |
9104 | #define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 |
9105 | #define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 |
9106 | #define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 |
9107 | #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa |
9108 | #define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb |
9109 | #define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc |
9110 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L |
9111 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L |
9112 | #define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L |
9113 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L |
9114 | #define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L |
9115 | #define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L |
9116 | #define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L |
9117 | #define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L |
9118 | #define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L |
9119 | #define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L |
9120 | #define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L |
9121 | #define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L |
9122 | #define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L |
9123 | //GDS_DSM_CNTL |
9124 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0 |
9125 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1 |
9126 | #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
9127 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3 |
9128 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4 |
9129 | #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
9130 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6 |
9131 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7 |
9132 | #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
9133 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9 |
9134 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa |
9135 | #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
9136 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc |
9137 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd |
9138 | #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
9139 | #define GDS_DSM_CNTL__UNUSED__SHIFT 0xf |
9140 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L |
9141 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L |
9142 | #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
9143 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L |
9144 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L |
9145 | #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
9146 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L |
9147 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L |
9148 | #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
9149 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L |
9150 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L |
9151 | #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
9152 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L |
9153 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L |
9154 | #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
9155 | #define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L |
9156 | //GDS_EDC_OA_PHY_CNT |
9157 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0 |
9158 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2 |
9159 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4 |
9160 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6 |
9161 | #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8 |
9162 | #define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa |
9163 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L |
9164 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL |
9165 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L |
9166 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L |
9167 | #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L |
9168 | #define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L |
9169 | //GDS_EDC_OA_PIPE_CNT |
9170 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0 |
9171 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2 |
9172 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4 |
9173 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6 |
9174 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8 |
9175 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa |
9176 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc |
9177 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe |
9178 | #define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10 |
9179 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L |
9180 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL |
9181 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L |
9182 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L |
9183 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L |
9184 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L |
9185 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L |
9186 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L |
9187 | #define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L |
9188 | //GDS_DSM_CNTL2 |
9189 | #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
9190 | #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
9191 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3 |
9192 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5 |
9193 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
9194 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 |
9195 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
9196 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb |
9197 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
9198 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe |
9199 | #define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf |
9200 | #define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a |
9201 | #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
9202 | #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
9203 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L |
9204 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L |
9205 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
9206 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L |
9207 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
9208 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L |
9209 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
9210 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
9211 | #define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L |
9212 | #define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L |
9213 | //GDS_WD_GDS_CSB |
9214 | #define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0 |
9215 | #define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd |
9216 | #define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL |
9217 | #define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L |
9218 | |
9219 | |
9220 | // addressBlock: gc_rbdec |
9221 | //DB_DEBUG |
9222 | #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 |
9223 | #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 |
9224 | #define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 |
9225 | #define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 |
9226 | #define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 |
9227 | #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 |
9228 | #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 |
9229 | #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 |
9230 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa |
9231 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc |
9232 | #define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe |
9233 | #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf |
9234 | #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 |
9235 | #define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 |
9236 | #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 |
9237 | #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 |
9238 | #define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 |
9239 | #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 |
9240 | #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 |
9241 | #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 |
9242 | #define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c |
9243 | #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d |
9244 | #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e |
9245 | #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f |
9246 | #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L |
9247 | #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L |
9248 | #define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L |
9249 | #define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L |
9250 | #define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L |
9251 | #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L |
9252 | #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L |
9253 | #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L |
9254 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L |
9255 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L |
9256 | #define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L |
9257 | #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L |
9258 | #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L |
9259 | #define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L |
9260 | #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L |
9261 | #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L |
9262 | #define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L |
9263 | #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L |
9264 | #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L |
9265 | #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L |
9266 | #define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L |
9267 | #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L |
9268 | #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L |
9269 | #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L |
9270 | //DB_DEBUG2 |
9271 | #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 |
9272 | #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 |
9273 | #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 |
9274 | #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 |
9275 | #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 |
9276 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5 |
9277 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6 |
9278 | #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7 |
9279 | #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8 |
9280 | #define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 |
9281 | #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe |
9282 | #define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT 0xf |
9283 | #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10 |
9284 | #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 |
9285 | #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 |
9286 | #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 |
9287 | #define DB_DEBUG2__FULL_TILE_WAVE_BREAK_MODE__SHIFT 0x14 |
9288 | #define DB_DEBUG2__DUAL_PIPE_REZ_STALL_MANUAL_CONTROL__SHIFT 0x16 |
9289 | #define DB_DEBUG2__DUAL_PIPE_REZ_STALL_SELECT_NEW__SHIFT 0x17 |
9290 | #define DB_DEBUG2__FORCE_ITERATE_256__SHIFT 0x18 |
9291 | #define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID__SHIFT 0x1a |
9292 | #define DB_DEBUG2__DISABLE_VR_PS_INVOKE__SHIFT 0x1b |
9293 | #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c |
9294 | #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d |
9295 | #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e |
9296 | #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f |
9297 | #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L |
9298 | #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L |
9299 | #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L |
9300 | #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L |
9301 | #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L |
9302 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L |
9303 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L |
9304 | #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L |
9305 | #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L |
9306 | #define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L |
9307 | #define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L |
9308 | #define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK 0x00008000L |
9309 | #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x00010000L |
9310 | #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L |
9311 | #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L |
9312 | #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L |
9313 | #define DB_DEBUG2__FULL_TILE_WAVE_BREAK_MODE_MASK 0x00300000L |
9314 | #define DB_DEBUG2__DUAL_PIPE_REZ_STALL_MANUAL_CONTROL_MASK 0x00400000L |
9315 | #define DB_DEBUG2__DUAL_PIPE_REZ_STALL_SELECT_NEW_MASK 0x00800000L |
9316 | #define DB_DEBUG2__FORCE_ITERATE_256_MASK 0x03000000L |
9317 | #define DB_DEBUG2__DISABLE_VR_OBJ_PRIM_ID_MASK 0x04000000L |
9318 | #define DB_DEBUG2__DISABLE_VR_PS_INVOKE_MASK 0x08000000L |
9319 | #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L |
9320 | #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L |
9321 | #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L |
9322 | #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L |
9323 | //DB_DEBUG3 |
9324 | #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0 |
9325 | #define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA__SHIFT 0x1 |
9326 | #define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 |
9327 | #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 |
9328 | #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 |
9329 | #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 |
9330 | #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 |
9331 | #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 |
9332 | #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 |
9333 | #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 |
9334 | #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa |
9335 | #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb |
9336 | #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc |
9337 | #define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd |
9338 | #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe |
9339 | #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf |
9340 | #define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH__SHIFT 0x10 |
9341 | #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 |
9342 | #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 |
9343 | #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 |
9344 | #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 |
9345 | #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 |
9346 | #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 |
9347 | #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 |
9348 | #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 |
9349 | #define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 |
9350 | #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a |
9351 | #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b |
9352 | #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c |
9353 | #define DB_DEBUG3__DELETE_CONTEXT_SUSPEND__SHIFT 0x1d |
9354 | #define DB_DEBUG3__DISABLE_TS_WRITE_L0__SHIFT 0x1e |
9355 | #define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT__SHIFT 0x1f |
9356 | #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L |
9357 | #define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA_MASK 0x00000002L |
9358 | #define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L |
9359 | #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L |
9360 | #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L |
9361 | #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L |
9362 | #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L |
9363 | #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L |
9364 | #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L |
9365 | #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L |
9366 | #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L |
9367 | #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L |
9368 | #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L |
9369 | #define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L |
9370 | #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L |
9371 | #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L |
9372 | #define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH_MASK 0x00010000L |
9373 | #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L |
9374 | #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L |
9375 | #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L |
9376 | #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L |
9377 | #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L |
9378 | #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L |
9379 | #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L |
9380 | #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L |
9381 | #define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L |
9382 | #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L |
9383 | #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L |
9384 | #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L |
9385 | #define DB_DEBUG3__DELETE_CONTEXT_SUSPEND_MASK 0x20000000L |
9386 | #define DB_DEBUG3__DISABLE_TS_WRITE_L0_MASK 0x40000000L |
9387 | #define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT_MASK 0x80000000L |
9388 | //DB_DEBUG4 |
9389 | #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 |
9390 | #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 |
9391 | #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 |
9392 | #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 |
9393 | #define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK__SHIFT 0x4 |
9394 | #define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0x5 |
9395 | #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x6 |
9396 | #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x7 |
9397 | #define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8 |
9398 | #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9 |
9399 | #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa |
9400 | #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb |
9401 | #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0xc |
9402 | #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd |
9403 | #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe |
9404 | #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0xf |
9405 | #define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT__SHIFT 0x10 |
9406 | #define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT__SHIFT 0x11 |
9407 | #define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE__SHIFT 0x12 |
9408 | #define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE__SHIFT 0x13 |
9409 | #define DB_DEBUG4__DISABLE_LATEZ_NO_EXPORT_POWER_SAVING__SHIFT 0x14 |
9410 | #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO__SHIFT 0x15 |
9411 | #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT__SHIFT 0x16 |
9412 | #define DB_DEBUG4__DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK__SHIFT 0x17 |
9413 | #define DB_DEBUG4__WR_MEM_BURST_CTL__SHIFT 0x18 |
9414 | #define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING__SHIFT 0x1b |
9415 | #define DB_DEBUG4__DISABLE_RD_MEM_BURST__SHIFT 0x1c |
9416 | #define DB_DEBUG4__LATE_ACK_SCOREBOARD_NEW__SHIFT 0x1d |
9417 | #define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT__SHIFT 0x1e |
9418 | #define DB_DEBUG4__LATE_ACK_PSD_EOP_GFX9_METHOD__SHIFT 0x1f |
9419 | #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L |
9420 | #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L |
9421 | #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L |
9422 | #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L |
9423 | #define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK_MASK 0x00000010L |
9424 | #define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00000020L |
9425 | #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000040L |
9426 | #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000080L |
9427 | #define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L |
9428 | #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L |
9429 | #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L |
9430 | #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L |
9431 | #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00001000L |
9432 | #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L |
9433 | #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L |
9434 | #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00008000L |
9435 | #define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT_MASK 0x00010000L |
9436 | #define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT_MASK 0x00020000L |
9437 | #define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE_MASK 0x00040000L |
9438 | #define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE_MASK 0x00080000L |
9439 | #define DB_DEBUG4__DISABLE_LATEZ_NO_EXPORT_POWER_SAVING_MASK 0x00100000L |
9440 | #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_MASK 0x00200000L |
9441 | #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT_MASK 0x00400000L |
9442 | #define DB_DEBUG4__DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK_MASK 0x00800000L |
9443 | #define DB_DEBUG4__WR_MEM_BURST_CTL_MASK 0x07000000L |
9444 | #define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING_MASK 0x08000000L |
9445 | #define DB_DEBUG4__DISABLE_RD_MEM_BURST_MASK 0x10000000L |
9446 | #define DB_DEBUG4__LATE_ACK_SCOREBOARD_NEW_MASK 0x20000000L |
9447 | #define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT_MASK 0x40000000L |
9448 | #define DB_DEBUG4__LATE_ACK_PSD_EOP_GFX9_METHOD_MASK 0x80000000L |
9449 | //DB_ETILE_STUTTER_CONTROL |
9450 | #define DB_ETILE_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 |
9451 | #define DB_ETILE_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 |
9452 | #define DB_ETILE_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL |
9453 | #define DB_ETILE_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L |
9454 | //DB_LTILE_STUTTER_CONTROL |
9455 | #define DB_LTILE_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 |
9456 | #define DB_LTILE_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 |
9457 | #define DB_LTILE_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL |
9458 | #define DB_LTILE_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L |
9459 | //DB_EQUAD_STUTTER_CONTROL |
9460 | #define DB_EQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 |
9461 | #define DB_EQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 |
9462 | #define DB_EQUAD_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL |
9463 | #define DB_EQUAD_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L |
9464 | //DB_LQUAD_STUTTER_CONTROL |
9465 | #define DB_LQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 |
9466 | #define DB_LQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 |
9467 | #define DB_LQUAD_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL |
9468 | #define DB_LQUAD_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L |
9469 | //DB_CREDIT_LIMIT |
9470 | #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 |
9471 | #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 |
9472 | #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa |
9473 | #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 |
9474 | #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL |
9475 | #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L |
9476 | #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L |
9477 | #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L |
9478 | //DB_WATERMARKS |
9479 | #define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 |
9480 | #define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x8 |
9481 | #define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x10 |
9482 | #define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x18 |
9483 | #define DB_WATERMARKS__DEPTH_FREE_MASK 0x000000FFL |
9484 | #define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x0000FF00L |
9485 | #define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x00FF0000L |
9486 | #define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0xFF000000L |
9487 | //DB_SUBTILE_CONTROL |
9488 | #define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 |
9489 | #define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 |
9490 | #define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 |
9491 | #define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 |
9492 | #define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 |
9493 | #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa |
9494 | #define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc |
9495 | #define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe |
9496 | #define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 |
9497 | #define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 |
9498 | #define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L |
9499 | #define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL |
9500 | #define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L |
9501 | #define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L |
9502 | #define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L |
9503 | #define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L |
9504 | #define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L |
9505 | #define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L |
9506 | #define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L |
9507 | #define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L |
9508 | //DB_FREE_CACHELINES |
9509 | #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 |
9510 | #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x8 |
9511 | #define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x10 |
9512 | #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x18 |
9513 | #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x000000FFL |
9514 | #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x0000FF00L |
9515 | #define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x00FF0000L |
9516 | #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0xFF000000L |
9517 | //DB_FIFO_DEPTH1 |
9518 | #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0 |
9519 | #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x8 |
9520 | #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0x10 |
9521 | #define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x18 |
9522 | #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x000000FFL |
9523 | #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x0000FF00L |
9524 | #define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x00FF0000L |
9525 | #define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0xFF000000L |
9526 | //DB_FIFO_DEPTH2 |
9527 | #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 |
9528 | #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 |
9529 | #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x10 |
9530 | #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 |
9531 | #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL |
9532 | #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x0000FF00L |
9533 | #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF0000L |
9534 | #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L |
9535 | //DB_LAST_OF_BURST_CONFIG |
9536 | #define DB_LAST_OF_BURST_CONFIG__MAXBURST__SHIFT 0x0 |
9537 | #define DB_LAST_OF_BURST_CONFIG__TIMEOUT__SHIFT 0x8 |
9538 | #define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT__SHIFT 0xb |
9539 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT__SHIFT 0x12 |
9540 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB__SHIFT 0x13 |
9541 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B__SHIFT 0x14 |
9542 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB__SHIFT 0x15 |
9543 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO__SHIFT 0x16 |
9544 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN__SHIFT 0x17 |
9545 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN__SHIFT 0x18 |
9546 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_CB_LOB_GEN__SHIFT 0x19 |
9547 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST__SHIFT 0x1a |
9548 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR__SHIFT 0x1b |
9549 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_RD_BA_ACCUM__SHIFT 0x1c |
9550 | #define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA__SHIFT 0x1d |
9551 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST__SHIFT 0x1e |
9552 | #define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN__SHIFT 0x1f |
9553 | #define DB_LAST_OF_BURST_CONFIG__MAXBURST_MASK 0x000000FFL |
9554 | #define DB_LAST_OF_BURST_CONFIG__TIMEOUT_MASK 0x00000700L |
9555 | #define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT_MASK 0x0003F800L |
9556 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT_MASK 0x00040000L |
9557 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB_MASK 0x00080000L |
9558 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B_MASK 0x00100000L |
9559 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB_MASK 0x00200000L |
9560 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO_MASK 0x00400000L |
9561 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN_MASK 0x00800000L |
9562 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN_MASK 0x01000000L |
9563 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_CB_LOB_GEN_MASK 0x02000000L |
9564 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST_MASK 0x04000000L |
9565 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR_MASK 0x08000000L |
9566 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_RD_BA_ACCUM_MASK 0x10000000L |
9567 | #define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA_MASK 0x20000000L |
9568 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST_MASK 0x40000000L |
9569 | #define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN_MASK 0x80000000L |
9570 | //DB_RING_CONTROL |
9571 | #define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 |
9572 | #define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L |
9573 | //DB_MEM_ARB_WATERMARKS |
9574 | #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0 |
9575 | #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8 |
9576 | #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10 |
9577 | #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18 |
9578 | #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L |
9579 | #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L |
9580 | #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L |
9581 | #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L |
9582 | //DB_FIFO_DEPTH3 |
9583 | #define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x0 |
9584 | #define DB_FIFO_DEPTH3__QUAD_READ_REQS__SHIFT 0x18 |
9585 | #define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH_MASK 0x000000FFL |
9586 | #define DB_FIFO_DEPTH3__QUAD_READ_REQS_MASK 0xFF000000L |
9587 | //DB_RMI_BC_GL2_CACHE_CONTROL |
9588 | #define DB_RMI_BC_GL2_CACHE_CONTROL__Z_WR_POLICY__SHIFT 0x0 |
9589 | #define DB_RMI_BC_GL2_CACHE_CONTROL__S_WR_POLICY__SHIFT 0x2 |
9590 | #define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT 0x4 |
9591 | #define DB_RMI_BC_GL2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT 0x6 |
9592 | #define DB_RMI_BC_GL2_CACHE_CONTROL__Z_RD_POLICY__SHIFT 0x10 |
9593 | #define DB_RMI_BC_GL2_CACHE_CONTROL__S_RD_POLICY__SHIFT 0x12 |
9594 | #define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT 0x14 |
9595 | #define DB_RMI_BC_GL2_CACHE_CONTROL__VOL__SHIFT 0x1f |
9596 | #define DB_RMI_BC_GL2_CACHE_CONTROL__Z_WR_POLICY_MASK 0x00000003L |
9597 | #define DB_RMI_BC_GL2_CACHE_CONTROL__S_WR_POLICY_MASK 0x0000000CL |
9598 | #define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_WR_POLICY_MASK 0x00000030L |
9599 | #define DB_RMI_BC_GL2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK 0x000000C0L |
9600 | #define DB_RMI_BC_GL2_CACHE_CONTROL__Z_RD_POLICY_MASK 0x00030000L |
9601 | #define DB_RMI_BC_GL2_CACHE_CONTROL__S_RD_POLICY_MASK 0x000C0000L |
9602 | #define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_RD_POLICY_MASK 0x00300000L |
9603 | #define DB_RMI_BC_GL2_CACHE_CONTROL__VOL_MASK 0x80000000L |
9604 | //DB_EXCEPTION_CONTROL |
9605 | #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0 |
9606 | #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1 |
9607 | #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2 |
9608 | #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE__SHIFT 0x3 |
9609 | #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT 0x4 |
9610 | #define 0x5 |
9611 | #define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT 0x8 |
9612 | #define 0xc |
9613 | #define DB_EXCEPTION_CONTROL__DTAG_WATERMARK__SHIFT 0x18 |
9614 | #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L |
9615 | #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L |
9616 | #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L |
9617 | #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE_MASK 0x00000008L |
9618 | #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD_MASK 0x00000010L |
9619 | #define 0x000000E0L |
9620 | #define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE_MASK 0x00000F00L |
9621 | #define 0x00FFF000L |
9622 | #define DB_EXCEPTION_CONTROL__DTAG_WATERMARK_MASK 0x7F000000L |
9623 | //DB_DFSM_CONFIG |
9624 | #define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0 |
9625 | #define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1 |
9626 | #define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2 |
9627 | #define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3 |
9628 | #define DB_DFSM_CONFIG__SQUAD_WATERMARK__SHIFT 0x4 |
9629 | #define DB_DFSM_CONFIG__CAM_WATERMARK__SHIFT 0x10 |
9630 | #define DB_DFSM_CONFIG__OUTPUT_WATCHDOG__SHIFT 0x18 |
9631 | #define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L |
9632 | #define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L |
9633 | #define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L |
9634 | #define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L |
9635 | #define DB_DFSM_CONFIG__SQUAD_WATERMARK_MASK 0x00003FF0L |
9636 | #define DB_DFSM_CONFIG__CAM_WATERMARK_MASK 0x00FF0000L |
9637 | #define DB_DFSM_CONFIG__OUTPUT_WATCHDOG_MASK 0xFF000000L |
9638 | //DB_DFSM_TILES_IN_FLIGHT |
9639 | #define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 |
9640 | #define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL |
9641 | //DB_DFSM_PRIMS_IN_FLIGHT |
9642 | #define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 |
9643 | #define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL |
9644 | //DB_DFSM_WATCHDOG |
9645 | #define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0 |
9646 | #define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL |
9647 | //DB_DFSM_FLUSH_ENABLE |
9648 | #define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0 |
9649 | #define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18 |
9650 | #define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c |
9651 | #define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000007FFL |
9652 | #define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L |
9653 | #define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L |
9654 | //DB_DFSM_FLUSH_AUX_EVENT |
9655 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0 |
9656 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8 |
9657 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10 |
9658 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18 |
9659 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL |
9660 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L |
9661 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L |
9662 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L |
9663 | //DB_FGCG_SRAMS_CLK_CTRL |
9664 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0__SHIFT 0x0 |
9665 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1__SHIFT 0x1 |
9666 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2__SHIFT 0x2 |
9667 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3__SHIFT 0x3 |
9668 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4__SHIFT 0x4 |
9669 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5__SHIFT 0x5 |
9670 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6__SHIFT 0x6 |
9671 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7__SHIFT 0x7 |
9672 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8__SHIFT 0x8 |
9673 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9__SHIFT 0x9 |
9674 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT 0xa |
9675 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11__SHIFT 0xb |
9676 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12__SHIFT 0xc |
9677 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13__SHIFT 0xd |
9678 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14__SHIFT 0xe |
9679 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15__SHIFT 0xf |
9680 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16__SHIFT 0x10 |
9681 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17__SHIFT 0x11 |
9682 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18__SHIFT 0x12 |
9683 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19__SHIFT 0x13 |
9684 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20__SHIFT 0x14 |
9685 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21__SHIFT 0x15 |
9686 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22__SHIFT 0x16 |
9687 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23__SHIFT 0x17 |
9688 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24__SHIFT 0x18 |
9689 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25__SHIFT 0x19 |
9690 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26__SHIFT 0x1a |
9691 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0_MASK 0x00000001L |
9692 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1_MASK 0x00000002L |
9693 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2_MASK 0x00000004L |
9694 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3_MASK 0x00000008L |
9695 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4_MASK 0x00000010L |
9696 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5_MASK 0x00000020L |
9697 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6_MASK 0x00000040L |
9698 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7_MASK 0x00000080L |
9699 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8_MASK 0x00000100L |
9700 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9_MASK 0x00000200L |
9701 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10_MASK 0x00000400L |
9702 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11_MASK 0x00000800L |
9703 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12_MASK 0x00001000L |
9704 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13_MASK 0x00002000L |
9705 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14_MASK 0x00004000L |
9706 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15_MASK 0x00008000L |
9707 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16_MASK 0x00010000L |
9708 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17_MASK 0x00020000L |
9709 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18_MASK 0x00040000L |
9710 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19_MASK 0x00080000L |
9711 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20_MASK 0x00100000L |
9712 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21_MASK 0x00200000L |
9713 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22_MASK 0x00400000L |
9714 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23_MASK 0x00800000L |
9715 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24_MASK 0x01000000L |
9716 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25_MASK 0x02000000L |
9717 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26_MASK 0x04000000L |
9718 | //DB_FGCG_INTERFACES_CLK_CTRL |
9719 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE__SHIFT 0x0 |
9720 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_TILE_OVERRIDE__SHIFT 0x1 |
9721 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_LQUAD_OVERRIDE__SHIFT 0x2 |
9722 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE__SHIFT 0x3 |
9723 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE__SHIFT 0x4 |
9724 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE__SHIFT 0x5 |
9725 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE__SHIFT 0x6 |
9726 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE_MASK 0x00000001L |
9727 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_TILE_OVERRIDE_MASK 0x00000002L |
9728 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_LQUAD_OVERRIDE_MASK 0x00000004L |
9729 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE_MASK 0x00000008L |
9730 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE_MASK 0x00000010L |
9731 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE_MASK 0x00000020L |
9732 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE_MASK 0x00000040L |
9733 | //CC_RB_REDUNDANCY |
9734 | #define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 |
9735 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc |
9736 | #define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 |
9737 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 |
9738 | #define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L |
9739 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L |
9740 | #define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L |
9741 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L |
9742 | //CC_RB_BACKEND_DISABLE |
9743 | #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 |
9744 | #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L |
9745 | //GB_ADDR_CONFIG |
9746 | #define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
9747 | #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
9748 | #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
9749 | #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
9750 | #define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a |
9751 | #define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
9752 | #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
9753 | #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
9754 | #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
9755 | #define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L |
9756 | //GB_BACKEND_MAP |
9757 | #define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 |
9758 | #define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL |
9759 | //GB_GPU_ID |
9760 | #define GB_GPU_ID__GPU_ID__SHIFT 0x0 |
9761 | #define GB_GPU_ID__GPU_ID_MASK 0x0000000FL |
9762 | //CC_RB_DAISY_CHAIN |
9763 | #define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 |
9764 | #define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 |
9765 | #define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 |
9766 | #define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc |
9767 | #define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 |
9768 | #define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 |
9769 | #define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 |
9770 | #define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c |
9771 | #define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL |
9772 | #define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L |
9773 | #define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L |
9774 | #define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L |
9775 | #define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L |
9776 | #define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L |
9777 | #define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L |
9778 | #define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L |
9779 | //GB_ADDR_CONFIG_READ |
9780 | #define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 |
9781 | #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
9782 | #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
9783 | #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 |
9784 | #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a |
9785 | #define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L |
9786 | #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
9787 | #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
9788 | #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L |
9789 | #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L |
9790 | //GB_TILE_MODE0 |
9791 | #define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 |
9792 | #define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 |
9793 | #define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb |
9794 | #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9795 | #define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 |
9796 | #define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL |
9797 | #define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L |
9798 | #define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L |
9799 | #define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9800 | #define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L |
9801 | //GB_TILE_MODE1 |
9802 | #define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 |
9803 | #define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 |
9804 | #define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb |
9805 | #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9806 | #define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 |
9807 | #define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL |
9808 | #define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L |
9809 | #define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L |
9810 | #define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9811 | #define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L |
9812 | //GB_TILE_MODE2 |
9813 | #define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 |
9814 | #define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 |
9815 | #define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb |
9816 | #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9817 | #define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 |
9818 | #define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL |
9819 | #define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L |
9820 | #define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L |
9821 | #define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9822 | #define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L |
9823 | //GB_TILE_MODE3 |
9824 | #define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 |
9825 | #define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 |
9826 | #define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb |
9827 | #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9828 | #define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 |
9829 | #define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL |
9830 | #define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L |
9831 | #define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L |
9832 | #define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9833 | #define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L |
9834 | //GB_TILE_MODE4 |
9835 | #define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 |
9836 | #define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 |
9837 | #define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb |
9838 | #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9839 | #define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 |
9840 | #define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL |
9841 | #define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L |
9842 | #define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L |
9843 | #define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9844 | #define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L |
9845 | //GB_TILE_MODE5 |
9846 | #define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 |
9847 | #define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 |
9848 | #define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb |
9849 | #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9850 | #define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 |
9851 | #define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL |
9852 | #define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L |
9853 | #define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L |
9854 | #define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9855 | #define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L |
9856 | //GB_TILE_MODE6 |
9857 | #define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 |
9858 | #define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 |
9859 | #define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb |
9860 | #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9861 | #define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 |
9862 | #define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL |
9863 | #define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L |
9864 | #define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L |
9865 | #define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9866 | #define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L |
9867 | //GB_TILE_MODE7 |
9868 | #define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 |
9869 | #define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 |
9870 | #define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb |
9871 | #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9872 | #define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 |
9873 | #define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL |
9874 | #define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L |
9875 | #define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L |
9876 | #define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9877 | #define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L |
9878 | //GB_TILE_MODE8 |
9879 | #define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 |
9880 | #define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 |
9881 | #define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb |
9882 | #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9883 | #define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 |
9884 | #define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL |
9885 | #define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L |
9886 | #define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L |
9887 | #define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9888 | #define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L |
9889 | //GB_TILE_MODE9 |
9890 | #define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 |
9891 | #define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 |
9892 | #define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb |
9893 | #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9894 | #define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 |
9895 | #define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL |
9896 | #define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L |
9897 | #define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L |
9898 | #define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9899 | #define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L |
9900 | //GB_TILE_MODE10 |
9901 | #define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 |
9902 | #define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 |
9903 | #define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb |
9904 | #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9905 | #define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 |
9906 | #define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL |
9907 | #define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L |
9908 | #define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L |
9909 | #define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9910 | #define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L |
9911 | //GB_TILE_MODE11 |
9912 | #define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 |
9913 | #define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 |
9914 | #define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb |
9915 | #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9916 | #define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 |
9917 | #define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL |
9918 | #define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L |
9919 | #define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L |
9920 | #define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9921 | #define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L |
9922 | //GB_TILE_MODE12 |
9923 | #define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 |
9924 | #define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 |
9925 | #define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb |
9926 | #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9927 | #define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 |
9928 | #define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL |
9929 | #define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L |
9930 | #define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L |
9931 | #define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9932 | #define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L |
9933 | //GB_TILE_MODE13 |
9934 | #define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 |
9935 | #define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 |
9936 | #define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb |
9937 | #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9938 | #define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 |
9939 | #define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL |
9940 | #define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L |
9941 | #define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L |
9942 | #define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9943 | #define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L |
9944 | //GB_TILE_MODE14 |
9945 | #define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 |
9946 | #define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 |
9947 | #define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb |
9948 | #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9949 | #define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 |
9950 | #define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL |
9951 | #define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L |
9952 | #define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L |
9953 | #define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9954 | #define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L |
9955 | //GB_TILE_MODE15 |
9956 | #define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 |
9957 | #define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 |
9958 | #define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb |
9959 | #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9960 | #define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 |
9961 | #define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL |
9962 | #define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L |
9963 | #define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L |
9964 | #define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9965 | #define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L |
9966 | //GB_TILE_MODE16 |
9967 | #define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 |
9968 | #define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 |
9969 | #define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb |
9970 | #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9971 | #define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 |
9972 | #define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL |
9973 | #define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L |
9974 | #define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L |
9975 | #define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9976 | #define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L |
9977 | //GB_TILE_MODE17 |
9978 | #define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 |
9979 | #define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 |
9980 | #define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb |
9981 | #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9982 | #define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 |
9983 | #define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL |
9984 | #define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L |
9985 | #define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L |
9986 | #define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9987 | #define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L |
9988 | //GB_TILE_MODE18 |
9989 | #define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 |
9990 | #define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 |
9991 | #define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb |
9992 | #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
9993 | #define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 |
9994 | #define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL |
9995 | #define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L |
9996 | #define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L |
9997 | #define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
9998 | #define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L |
9999 | //GB_TILE_MODE19 |
10000 | #define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 |
10001 | #define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 |
10002 | #define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb |
10003 | #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
10004 | #define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 |
10005 | #define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL |
10006 | #define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L |
10007 | #define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L |
10008 | #define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
10009 | #define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L |
10010 | //GB_TILE_MODE20 |
10011 | #define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 |
10012 | #define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 |
10013 | #define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb |
10014 | #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
10015 | #define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 |
10016 | #define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL |
10017 | #define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L |
10018 | #define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L |
10019 | #define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
10020 | #define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L |
10021 | //GB_TILE_MODE21 |
10022 | #define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 |
10023 | #define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 |
10024 | #define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb |
10025 | #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
10026 | #define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 |
10027 | #define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL |
10028 | #define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L |
10029 | #define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L |
10030 | #define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
10031 | #define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L |
10032 | //GB_TILE_MODE22 |
10033 | #define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 |
10034 | #define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 |
10035 | #define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb |
10036 | #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
10037 | #define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 |
10038 | #define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL |
10039 | #define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L |
10040 | #define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L |
10041 | #define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
10042 | #define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L |
10043 | //GB_TILE_MODE23 |
10044 | #define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 |
10045 | #define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 |
10046 | #define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb |
10047 | #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
10048 | #define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 |
10049 | #define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL |
10050 | #define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L |
10051 | #define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L |
10052 | #define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
10053 | #define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L |
10054 | //GB_TILE_MODE24 |
10055 | #define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 |
10056 | #define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 |
10057 | #define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb |
10058 | #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
10059 | #define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 |
10060 | #define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL |
10061 | #define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L |
10062 | #define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L |
10063 | #define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
10064 | #define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L |
10065 | //GB_TILE_MODE25 |
10066 | #define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 |
10067 | #define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 |
10068 | #define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb |
10069 | #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
10070 | #define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 |
10071 | #define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL |
10072 | #define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L |
10073 | #define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L |
10074 | #define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
10075 | #define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L |
10076 | //GB_TILE_MODE26 |
10077 | #define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 |
10078 | #define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 |
10079 | #define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb |
10080 | #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
10081 | #define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 |
10082 | #define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL |
10083 | #define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L |
10084 | #define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L |
10085 | #define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
10086 | #define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L |
10087 | //GB_TILE_MODE27 |
10088 | #define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 |
10089 | #define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 |
10090 | #define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb |
10091 | #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
10092 | #define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 |
10093 | #define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL |
10094 | #define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L |
10095 | #define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L |
10096 | #define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
10097 | #define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L |
10098 | //GB_TILE_MODE28 |
10099 | #define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 |
10100 | #define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 |
10101 | #define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb |
10102 | #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
10103 | #define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 |
10104 | #define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL |
10105 | #define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L |
10106 | #define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L |
10107 | #define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
10108 | #define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L |
10109 | //GB_TILE_MODE29 |
10110 | #define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 |
10111 | #define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 |
10112 | #define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb |
10113 | #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
10114 | #define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 |
10115 | #define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL |
10116 | #define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L |
10117 | #define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L |
10118 | #define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
10119 | #define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L |
10120 | //GB_TILE_MODE30 |
10121 | #define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 |
10122 | #define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 |
10123 | #define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb |
10124 | #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
10125 | #define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 |
10126 | #define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL |
10127 | #define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L |
10128 | #define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L |
10129 | #define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
10130 | #define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L |
10131 | //GB_TILE_MODE31 |
10132 | #define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 |
10133 | #define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 |
10134 | #define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb |
10135 | #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 |
10136 | #define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 |
10137 | #define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL |
10138 | #define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L |
10139 | #define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L |
10140 | #define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L |
10141 | #define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L |
10142 | //GB_MACROTILE_MODE0 |
10143 | #define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 |
10144 | #define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 |
10145 | #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 |
10146 | #define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 |
10147 | #define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L |
10148 | #define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL |
10149 | #define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L |
10150 | #define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L |
10151 | //GB_MACROTILE_MODE1 |
10152 | #define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 |
10153 | #define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 |
10154 | #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 |
10155 | #define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 |
10156 | #define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L |
10157 | #define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL |
10158 | #define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L |
10159 | #define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L |
10160 | //GB_MACROTILE_MODE2 |
10161 | #define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 |
10162 | #define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 |
10163 | #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 |
10164 | #define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 |
10165 | #define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L |
10166 | #define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL |
10167 | #define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L |
10168 | #define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L |
10169 | //GB_MACROTILE_MODE3 |
10170 | #define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 |
10171 | #define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 |
10172 | #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 |
10173 | #define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 |
10174 | #define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L |
10175 | #define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL |
10176 | #define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L |
10177 | #define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L |
10178 | //GB_MACROTILE_MODE4 |
10179 | #define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 |
10180 | #define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 |
10181 | #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 |
10182 | #define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 |
10183 | #define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L |
10184 | #define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL |
10185 | #define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L |
10186 | #define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L |
10187 | //GB_MACROTILE_MODE5 |
10188 | #define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 |
10189 | #define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 |
10190 | #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 |
10191 | #define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 |
10192 | #define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L |
10193 | #define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL |
10194 | #define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L |
10195 | #define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L |
10196 | //GB_MACROTILE_MODE6 |
10197 | #define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 |
10198 | #define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 |
10199 | #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 |
10200 | #define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 |
10201 | #define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L |
10202 | #define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL |
10203 | #define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L |
10204 | #define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L |
10205 | //GB_MACROTILE_MODE7 |
10206 | #define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 |
10207 | #define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 |
10208 | #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 |
10209 | #define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 |
10210 | #define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L |
10211 | #define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL |
10212 | #define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L |
10213 | #define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L |
10214 | //GB_MACROTILE_MODE8 |
10215 | #define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 |
10216 | #define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 |
10217 | #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 |
10218 | #define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 |
10219 | #define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L |
10220 | #define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL |
10221 | #define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L |
10222 | #define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L |
10223 | //GB_MACROTILE_MODE9 |
10224 | #define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 |
10225 | #define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 |
10226 | #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 |
10227 | #define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 |
10228 | #define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L |
10229 | #define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL |
10230 | #define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L |
10231 | #define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L |
10232 | //GB_MACROTILE_MODE10 |
10233 | #define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 |
10234 | #define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 |
10235 | #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 |
10236 | #define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 |
10237 | #define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L |
10238 | #define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL |
10239 | #define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L |
10240 | #define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L |
10241 | //GB_MACROTILE_MODE11 |
10242 | #define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 |
10243 | #define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 |
10244 | #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 |
10245 | #define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 |
10246 | #define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L |
10247 | #define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL |
10248 | #define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L |
10249 | #define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L |
10250 | //GB_MACROTILE_MODE12 |
10251 | #define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 |
10252 | #define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 |
10253 | #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 |
10254 | #define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 |
10255 | #define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L |
10256 | #define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL |
10257 | #define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L |
10258 | #define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L |
10259 | //GB_MACROTILE_MODE13 |
10260 | #define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 |
10261 | #define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 |
10262 | #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 |
10263 | #define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 |
10264 | #define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L |
10265 | #define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL |
10266 | #define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L |
10267 | #define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L |
10268 | //GB_MACROTILE_MODE14 |
10269 | #define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 |
10270 | #define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 |
10271 | #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 |
10272 | #define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 |
10273 | #define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L |
10274 | #define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL |
10275 | #define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L |
10276 | #define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L |
10277 | //GB_MACROTILE_MODE15 |
10278 | #define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 |
10279 | #define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 |
10280 | #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 |
10281 | #define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 |
10282 | #define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L |
10283 | #define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL |
10284 | #define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L |
10285 | #define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L |
10286 | //CB_HW_CONTROL_4 |
10287 | #define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_CLS_LOG2__SHIFT 0x0 |
10288 | #define CB_HW_CONTROL_4__FMASK_CACHE_FETCH_NUM_CLS_LOG2__SHIFT 0x3 |
10289 | #define CB_HW_CONTROL_4__DISABLE_USE_OF_QUAD_SCOREBOARD__SHIFT 0x5 |
10290 | #define CB_HW_CONTROL_4__DISABLE_CMASK_CLOCK_GATING__SHIFT 0x6 |
10291 | #define CB_HW_CONTROL_4__DISABLE_FMASK_CLOCK_GATING__SHIFT 0x7 |
10292 | #define CB_HW_CONTROL_4__DISABLE_COLOR_CLOCK_GATING__SHIFT 0x8 |
10293 | #define CB_HW_CONTROL_4__DISABLE_QSB_AA_MODE__SHIFT 0x9 |
10294 | #define CB_HW_CONTROL_4__DISABLE_QSB_WAIT_FOR_SCORE__SHIFT 0xa |
10295 | #define CB_HW_CONTROL_4__DISABLE_QSB_FRAG_GT0__SHIFT 0xb |
10296 | #define CB_HW_CONTROL_4__REVERSE_KEYXFR_RD_PRIORITY__SHIFT 0xc |
10297 | #define CB_HW_CONTROL_4__DISABLE_KEYXFR_HIT_RETURNS__SHIFT 0xd |
10298 | #define CB_HW_CONTROL_4__DISABLE_BC_COLOR_CACHE_PREFETCH__SHIFT 0xe |
10299 | #define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST__SHIFT 0xf |
10300 | #define CB_HW_CONTROL_4__DISABLE_QSB_SPECULATIVE__SHIFT 0x10 |
10301 | #define CB_HW_CONTROL_4__QSB_WAIT_FOR_SCORE__SHIFT 0x11 |
10302 | #define CB_HW_CONTROL_4__DISABLE_TILE_FGCG__SHIFT 0x16 |
10303 | #define CB_HW_CONTROL_4__DISABLE_LQUAD_FGCG__SHIFT 0x17 |
10304 | #define CB_HW_CONTROL_4__FC_QSB_FIFO_DEPTH__SHIFT 0x18 |
10305 | #define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_CLS_LOG2_MASK 0x00000007L |
10306 | #define CB_HW_CONTROL_4__FMASK_CACHE_FETCH_NUM_CLS_LOG2_MASK 0x00000018L |
10307 | #define CB_HW_CONTROL_4__DISABLE_USE_OF_QUAD_SCOREBOARD_MASK 0x00000020L |
10308 | #define CB_HW_CONTROL_4__DISABLE_CMASK_CLOCK_GATING_MASK 0x00000040L |
10309 | #define CB_HW_CONTROL_4__DISABLE_FMASK_CLOCK_GATING_MASK 0x00000080L |
10310 | #define CB_HW_CONTROL_4__DISABLE_COLOR_CLOCK_GATING_MASK 0x00000100L |
10311 | #define CB_HW_CONTROL_4__DISABLE_QSB_AA_MODE_MASK 0x00000200L |
10312 | #define CB_HW_CONTROL_4__DISABLE_QSB_WAIT_FOR_SCORE_MASK 0x00000400L |
10313 | #define CB_HW_CONTROL_4__DISABLE_QSB_FRAG_GT0_MASK 0x00000800L |
10314 | #define CB_HW_CONTROL_4__REVERSE_KEYXFR_RD_PRIORITY_MASK 0x00001000L |
10315 | #define CB_HW_CONTROL_4__DISABLE_KEYXFR_HIT_RETURNS_MASK 0x00002000L |
10316 | #define CB_HW_CONTROL_4__DISABLE_BC_COLOR_CACHE_PREFETCH_MASK 0x00004000L |
10317 | #define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST_MASK 0x00008000L |
10318 | #define CB_HW_CONTROL_4__DISABLE_QSB_SPECULATIVE_MASK 0x00010000L |
10319 | #define CB_HW_CONTROL_4__QSB_WAIT_FOR_SCORE_MASK 0x003E0000L |
10320 | #define CB_HW_CONTROL_4__DISABLE_TILE_FGCG_MASK 0x00400000L |
10321 | #define CB_HW_CONTROL_4__DISABLE_LQUAD_FGCG_MASK 0x00800000L |
10322 | #define CB_HW_CONTROL_4__FC_QSB_FIFO_DEPTH_MASK 0xFF000000L |
10323 | //CB_HW_CONTROL_3 |
10324 | #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 |
10325 | #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 |
10326 | #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2 |
10327 | #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3 |
10328 | #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4 |
10329 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5 |
10330 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7 |
10331 | #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8 |
10332 | #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9 |
10333 | #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa |
10334 | #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb |
10335 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc |
10336 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd |
10337 | #define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe |
10338 | #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf |
10339 | #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10 |
10340 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11 |
10341 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12 |
10342 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13 |
10343 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14 |
10344 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15 |
10345 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16 |
10346 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17 |
10347 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18 |
10348 | #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19 |
10349 | #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a |
10350 | #define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b |
10351 | #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x1e |
10352 | #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_BC__SHIFT 0x1f |
10353 | #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L |
10354 | #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L |
10355 | #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L |
10356 | #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L |
10357 | #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L |
10358 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L |
10359 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L |
10360 | #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L |
10361 | #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L |
10362 | #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L |
10363 | #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L |
10364 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L |
10365 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L |
10366 | #define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L |
10367 | #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L |
10368 | #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L |
10369 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L |
10370 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L |
10371 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L |
10372 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L |
10373 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L |
10374 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L |
10375 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L |
10376 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L |
10377 | #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L |
10378 | #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L |
10379 | #define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L |
10380 | #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_MASK 0x40000000L |
10381 | #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_BC_MASK 0x80000000L |
10382 | //CB_HW_CONTROL |
10383 | #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x0 |
10384 | #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 |
10385 | #define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 |
10386 | #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 |
10387 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 |
10388 | #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 |
10389 | #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 |
10390 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 |
10391 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 |
10392 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a |
10393 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b |
10394 | #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c |
10395 | #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d |
10396 | #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e |
10397 | #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f |
10398 | #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00000001L |
10399 | #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L |
10400 | #define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L |
10401 | #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L |
10402 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L |
10403 | #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L |
10404 | #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L |
10405 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L |
10406 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L |
10407 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L |
10408 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L |
10409 | #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L |
10410 | #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L |
10411 | #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L |
10412 | #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L |
10413 | //CB_HW_CONTROL_1 |
10414 | #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 |
10415 | #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 |
10416 | #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb |
10417 | #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 |
10418 | #define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a |
10419 | #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL |
10420 | #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L |
10421 | #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L |
10422 | #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L |
10423 | #define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L |
10424 | //CB_HW_CONTROL_2 |
10425 | #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 |
10426 | #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 |
10427 | #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf |
10428 | #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18 |
10429 | #define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1e |
10430 | #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL |
10431 | #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L |
10432 | #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L |
10433 | #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x3F000000L |
10434 | #define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xC0000000L |
10435 | //CB_DCC_CONFIG |
10436 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0 |
10437 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5 |
10438 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6 |
10439 | #define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT 0x7 |
10440 | #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8 |
10441 | #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 |
10442 | #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1a |
10443 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL |
10444 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L |
10445 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L |
10446 | #define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK 0x00000080L |
10447 | #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L |
10448 | #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x01FF0000L |
10449 | #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xFC000000L |
10450 | //CB_HW_MEM_ARBITER_RD |
10451 | #define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0 |
10452 | #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2 |
10453 | #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6 |
10454 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa |
10455 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc |
10456 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe |
10457 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10 |
10458 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12 |
10459 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14 |
10460 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16 |
10461 | #define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17 |
10462 | #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a |
10463 | #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d |
10464 | #define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L |
10465 | #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL |
10466 | #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L |
10467 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L |
10468 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L |
10469 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L |
10470 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L |
10471 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L |
10472 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L |
10473 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L |
10474 | #define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L |
10475 | #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L |
10476 | #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L |
10477 | //CB_HW_MEM_ARBITER_WR |
10478 | #define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0 |
10479 | #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2 |
10480 | #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6 |
10481 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa |
10482 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc |
10483 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe |
10484 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10 |
10485 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12 |
10486 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14 |
10487 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16 |
10488 | #define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17 |
10489 | #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a |
10490 | #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d |
10491 | #define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L |
10492 | #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL |
10493 | #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L |
10494 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L |
10495 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L |
10496 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L |
10497 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L |
10498 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L |
10499 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L |
10500 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L |
10501 | #define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L |
10502 | #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L |
10503 | #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L |
10504 | //CB_RMI_BC_GL2_CACHE_CONTROL |
10505 | #define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_WR_POLICY__SHIFT 0x0 |
10506 | #define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_WR_POLICY__SHIFT 0x2 |
10507 | #define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT 0x4 |
10508 | #define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT 0x6 |
10509 | #define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_RD_POLICY__SHIFT 0x10 |
10510 | #define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_RD_POLICY__SHIFT 0x12 |
10511 | #define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT 0x14 |
10512 | #define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT 0x16 |
10513 | #define CB_RMI_BC_GL2_CACHE_CONTROL__VOLAT__SHIFT 0x1f |
10514 | #define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_WR_POLICY_MASK 0x00000003L |
10515 | #define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_WR_POLICY_MASK 0x0000000CL |
10516 | #define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK 0x00000030L |
10517 | #define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK 0x000000C0L |
10518 | #define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_RD_POLICY_MASK 0x00030000L |
10519 | #define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_RD_POLICY_MASK 0x000C0000L |
10520 | #define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK 0x00300000L |
10521 | #define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK 0x00C00000L |
10522 | #define CB_RMI_BC_GL2_CACHE_CONTROL__VOLAT_MASK 0x80000000L |
10523 | //CB_STUTTER_CONTROL_CMASK_RDLAT |
10524 | #define CB_STUTTER_CONTROL_CMASK_RDLAT__THRESHOLD__SHIFT 0x0 |
10525 | #define CB_STUTTER_CONTROL_CMASK_RDLAT__TIMEOUT__SHIFT 0x8 |
10526 | #define CB_STUTTER_CONTROL_CMASK_RDLAT__THRESHOLD_MASK 0x000000FFL |
10527 | #define CB_STUTTER_CONTROL_CMASK_RDLAT__TIMEOUT_MASK 0x0000FF00L |
10528 | //CB_STUTTER_CONTROL_FMASK_RDLAT |
10529 | #define CB_STUTTER_CONTROL_FMASK_RDLAT__THRESHOLD__SHIFT 0x0 |
10530 | #define CB_STUTTER_CONTROL_FMASK_RDLAT__TIMEOUT__SHIFT 0x8 |
10531 | #define CB_STUTTER_CONTROL_FMASK_RDLAT__THRESHOLD_MASK 0x000000FFL |
10532 | #define CB_STUTTER_CONTROL_FMASK_RDLAT__TIMEOUT_MASK 0x0000FF00L |
10533 | //CB_STUTTER_CONTROL_COLOR_RDLAT |
10534 | #define CB_STUTTER_CONTROL_COLOR_RDLAT__THRESHOLD__SHIFT 0x0 |
10535 | #define CB_STUTTER_CONTROL_COLOR_RDLAT__TIMEOUT__SHIFT 0x8 |
10536 | #define CB_STUTTER_CONTROL_COLOR_RDLAT__THRESHOLD_MASK 0x000000FFL |
10537 | #define CB_STUTTER_CONTROL_COLOR_RDLAT__TIMEOUT_MASK 0x0000FF00L |
10538 | //CB_CACHE_EVICT_POINTS |
10539 | #define CB_CACHE_EVICT_POINTS__CM_CACHE_EVICT_POINT__SHIFT 0x0 |
10540 | #define CB_CACHE_EVICT_POINTS__FC_CACHE_EVICT_POINT__SHIFT 0x8 |
10541 | #define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT__SHIFT 0x10 |
10542 | #define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT__SHIFT 0x18 |
10543 | #define CB_CACHE_EVICT_POINTS__CM_CACHE_EVICT_POINT_MASK 0x000000FFL |
10544 | #define CB_CACHE_EVICT_POINTS__FC_CACHE_EVICT_POINT_MASK 0x0000FF00L |
10545 | #define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT_MASK 0x00FF0000L |
10546 | #define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT_MASK 0xFF000000L |
10547 | //GC_USER_RB_REDUNDANCY |
10548 | #define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 |
10549 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc |
10550 | #define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 |
10551 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 |
10552 | #define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L |
10553 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L |
10554 | #define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L |
10555 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L |
10556 | //GC_USER_RB_BACKEND_DISABLE |
10557 | #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 |
10558 | #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L |
10559 | |
10560 | |
10561 | // addressBlock: gc_gceadec2 |
10562 | //GCEA_SDP_VCD_RESERVE1 |
10563 | #define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
10564 | #define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
10565 | #define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc |
10566 | #define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
10567 | #define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
10568 | #define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
10569 | #define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
10570 | #define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
10571 | //GCEA_SDP_REQ_CNTL |
10572 | #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 |
10573 | #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 |
10574 | #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 |
10575 | #define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 |
10576 | #define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 |
10577 | #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L |
10578 | #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L |
10579 | #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L |
10580 | #define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L |
10581 | #define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L |
10582 | //GCEA_MISC |
10583 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 |
10584 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 |
10585 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 |
10586 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 |
10587 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 |
10588 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 |
10589 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 |
10590 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 |
10591 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 |
10592 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 |
10593 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa |
10594 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb |
10595 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc |
10596 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd |
10597 | #define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe |
10598 | #define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf |
10599 | #define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 |
10600 | #define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 |
10601 | #define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 |
10602 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a |
10603 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b |
10604 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c |
10605 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d |
10606 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e |
10607 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f |
10608 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L |
10609 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L |
10610 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L |
10611 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L |
10612 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L |
10613 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L |
10614 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L |
10615 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L |
10616 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L |
10617 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L |
10618 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L |
10619 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L |
10620 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L |
10621 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L |
10622 | #define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L |
10623 | #define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L |
10624 | #define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L |
10625 | #define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L |
10626 | #define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L |
10627 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L |
10628 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L |
10629 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L |
10630 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L |
10631 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L |
10632 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L |
10633 | //GCEA_LATENCY_SAMPLING |
10634 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 |
10635 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 |
10636 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 |
10637 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 |
10638 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 |
10639 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 |
10640 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 |
10641 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 |
10642 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 |
10643 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 |
10644 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa |
10645 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb |
10646 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc |
10647 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd |
10648 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe |
10649 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 |
10650 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L |
10651 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L |
10652 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L |
10653 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L |
10654 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L |
10655 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L |
10656 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L |
10657 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L |
10658 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L |
10659 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L |
10660 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L |
10661 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L |
10662 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L |
10663 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L |
10664 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L |
10665 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L |
10666 | //GCEA_PERFCOUNTER_LO |
10667 | #define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
10668 | #define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
10669 | //GCEA_PERFCOUNTER_HI |
10670 | #define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
10671 | #define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
10672 | #define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
10673 | #define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
10674 | //GCEA_PERFCOUNTER0_CFG |
10675 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
10676 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
10677 | #define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
10678 | #define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
10679 | #define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
10680 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
10681 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
10682 | #define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
10683 | #define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
10684 | #define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
10685 | //GCEA_PERFCOUNTER1_CFG |
10686 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
10687 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
10688 | #define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
10689 | #define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
10690 | #define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
10691 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
10692 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
10693 | #define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
10694 | #define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
10695 | #define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
10696 | //GCEA_PERFCOUNTER_RSLT_CNTL |
10697 | #define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
10698 | #define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
10699 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
10700 | #define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
10701 | #define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
10702 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
10703 | #define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
10704 | #define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
10705 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
10706 | #define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
10707 | #define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
10708 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
10709 | //GCEA_EDC_CNT |
10710 | #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 |
10711 | #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 |
10712 | #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 |
10713 | #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 |
10714 | #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 |
10715 | #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa |
10716 | #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc |
10717 | #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe |
10718 | #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 |
10719 | #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 |
10720 | #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 |
10721 | #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 |
10722 | #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 |
10723 | #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a |
10724 | #define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c |
10725 | #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L |
10726 | #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL |
10727 | #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L |
10728 | #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L |
10729 | #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L |
10730 | #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L |
10731 | #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L |
10732 | #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L |
10733 | #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L |
10734 | #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L |
10735 | #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L |
10736 | #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L |
10737 | #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L |
10738 | #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L |
10739 | #define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L |
10740 | //GCEA_EDC_CNT2 |
10741 | #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 |
10742 | #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 |
10743 | #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 |
10744 | #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 |
10745 | #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 |
10746 | #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa |
10747 | #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc |
10748 | #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe |
10749 | #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L |
10750 | #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL |
10751 | #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L |
10752 | #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L |
10753 | #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L |
10754 | #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L |
10755 | #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L |
10756 | #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L |
10757 | //GCEA_DSM_CNTL |
10758 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
10759 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
10760 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
10761 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
10762 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
10763 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
10764 | #define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
10765 | #define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
10766 | #define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
10767 | #define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
10768 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
10769 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
10770 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
10771 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
10772 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
10773 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
10774 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
10775 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
10776 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
10777 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
10778 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
10779 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
10780 | #define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
10781 | #define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
10782 | #define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
10783 | #define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
10784 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
10785 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
10786 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
10787 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
10788 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
10789 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
10790 | //GCEA_DSM_CNTLA |
10791 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
10792 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
10793 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
10794 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
10795 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
10796 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
10797 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
10798 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
10799 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
10800 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
10801 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
10802 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
10803 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
10804 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
10805 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
10806 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
10807 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
10808 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
10809 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
10810 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
10811 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
10812 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
10813 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
10814 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
10815 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
10816 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
10817 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
10818 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
10819 | //GCEA_DSM_CNTLB |
10820 | //GCEA_DSM_CNTL2 |
10821 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
10822 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
10823 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
10824 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
10825 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
10826 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
10827 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
10828 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
10829 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
10830 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
10831 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
10832 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
10833 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
10834 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
10835 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
10836 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 |
10837 | #define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
10838 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
10839 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
10840 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
10841 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
10842 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
10843 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
10844 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
10845 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
10846 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
10847 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
10848 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
10849 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
10850 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
10851 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
10852 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
10853 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L |
10854 | #define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
10855 | //GCEA_DSM_CNTL2A |
10856 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
10857 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
10858 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
10859 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
10860 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
10861 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
10862 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
10863 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
10864 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
10865 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
10866 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
10867 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
10868 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
10869 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
10870 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
10871 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
10872 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
10873 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
10874 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
10875 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
10876 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
10877 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
10878 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
10879 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
10880 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
10881 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
10882 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
10883 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
10884 | //GCEA_DSM_CNTL2B |
10885 | //GCEA_GL2C_XBR_CREDITS |
10886 | #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0 |
10887 | #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6 |
10888 | #define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8 |
10889 | #define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe |
10890 | #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10 |
10891 | #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16 |
10892 | #define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18 |
10893 | #define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e |
10894 | #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL |
10895 | #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L |
10896 | #define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L |
10897 | #define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L |
10898 | #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L |
10899 | #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L |
10900 | #define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L |
10901 | #define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L |
10902 | //GCEA_GL2C_XBR_MAXBURST |
10903 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD__SHIFT 0x0 |
10904 | #define GCEA_GL2C_XBR_MAXBURST__IO_RD__SHIFT 0x4 |
10905 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR__SHIFT 0x8 |
10906 | #define GCEA_GL2C_XBR_MAXBURST__IO_WR__SHIFT 0xc |
10907 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER__SHIFT 0x10 |
10908 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY__SHIFT 0x13 |
10909 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER__SHIFT 0x14 |
10910 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY__SHIFT 0x17 |
10911 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL |
10912 | #define GCEA_GL2C_XBR_MAXBURST__IO_RD_MASK 0x000000F0L |
10913 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L |
10914 | #define GCEA_GL2C_XBR_MAXBURST__IO_WR_MASK 0x0000F000L |
10915 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER_MASK 0x00070000L |
10916 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY_MASK 0x00080000L |
10917 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER_MASK 0x00700000L |
10918 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY_MASK 0x00800000L |
10919 | //GCEA_PROBE_CNTL |
10920 | #define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0 |
10921 | #define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5 |
10922 | #define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL |
10923 | #define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L |
10924 | //GCEA_PROBE_MAP |
10925 | #define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C__SHIFT 0x0 |
10926 | #define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C__SHIFT 0x1 |
10927 | #define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C__SHIFT 0x2 |
10928 | #define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C__SHIFT 0x3 |
10929 | #define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C__SHIFT 0x4 |
10930 | #define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C__SHIFT 0x5 |
10931 | #define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C__SHIFT 0x6 |
10932 | #define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C__SHIFT 0x7 |
10933 | #define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C__SHIFT 0x8 |
10934 | #define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C__SHIFT 0x9 |
10935 | #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C__SHIFT 0xa |
10936 | #define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C__SHIFT 0xb |
10937 | #define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C__SHIFT 0xc |
10938 | #define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C__SHIFT 0xd |
10939 | #define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C__SHIFT 0xe |
10940 | #define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C__SHIFT 0xf |
10941 | #define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10 |
10942 | #define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C_MASK 0x00000001L |
10943 | #define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C_MASK 0x00000002L |
10944 | #define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C_MASK 0x00000004L |
10945 | #define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C_MASK 0x00000008L |
10946 | #define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C_MASK 0x00000010L |
10947 | #define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C_MASK 0x00000020L |
10948 | #define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C_MASK 0x00000040L |
10949 | #define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C_MASK 0x00000080L |
10950 | #define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C_MASK 0x00000100L |
10951 | #define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C_MASK 0x00000200L |
10952 | #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C_MASK 0x00000400L |
10953 | #define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C_MASK 0x00000800L |
10954 | #define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C_MASK 0x00001000L |
10955 | #define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C_MASK 0x00002000L |
10956 | #define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C_MASK 0x00004000L |
10957 | #define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C_MASK 0x00008000L |
10958 | #define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L |
10959 | //GCEA_ERR_STATUS |
10960 | #define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 |
10961 | #define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 |
10962 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 |
10963 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa |
10964 | #define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb |
10965 | #define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc |
10966 | #define GCEA_ERR_STATUS__FUE_FLAG__SHIFT 0xd |
10967 | #define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL |
10968 | #define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L |
10969 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L |
10970 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L |
10971 | #define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L |
10972 | #define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L |
10973 | #define GCEA_ERR_STATUS__FUE_FLAG_MASK 0x00002000L |
10974 | //GCEA_MISC2 |
10975 | #define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 |
10976 | #define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 |
10977 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 |
10978 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 |
10979 | #define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc |
10980 | #define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L |
10981 | #define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L |
10982 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL |
10983 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L |
10984 | #define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L |
10985 | |
10986 | |
10987 | // addressBlock: gc_spipdec2 |
10988 | //SPI_PQEV_CTRL |
10989 | #define SPI_PQEV_CTRL__SCAN_PERIOD__SHIFT 0x0 |
10990 | #define SPI_PQEV_CTRL__QUEUE_DURATION__SHIFT 0xa |
10991 | #define SPI_PQEV_CTRL__COMPUTE_PIPE_EN__SHIFT 0x10 |
10992 | #define SPI_PQEV_CTRL__SCAN_PERIOD_MASK 0x000003FFL |
10993 | #define SPI_PQEV_CTRL__QUEUE_DURATION_MASK 0x0000FC00L |
10994 | #define SPI_PQEV_CTRL__COMPUTE_PIPE_EN_MASK 0x00FF0000L |
10995 | //SPI_SYS_COMPUTE |
10996 | #define SPI_SYS_COMPUTE__PIPE__SHIFT 0x0 |
10997 | #define SPI_SYS_COMPUTE__PIPE_MASK 0x000000FFL |
10998 | //SPI_SYS_WIF_CNTL |
10999 | #define SPI_SYS_WIF_CNTL__THRESHOLD__SHIFT 0x0 |
11000 | #define SPI_SYS_WIF_CNTL__THRESHOLD_MASK 0x000000FFL |
11001 | |
11002 | |
11003 | // addressBlock: gc_gceadec3 |
11004 | //GCEA_DRAM_BANK_ARB |
11005 | #define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB__SHIFT 0x0 |
11006 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM__SHIFT 0x1 |
11007 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM__SHIFT 0x8 |
11008 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE__SHIFT 0xe |
11009 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_RD_DECRATE__SHIFT 0xf |
11010 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_WR_DECRATE__SHIFT 0x11 |
11011 | #define GCEA_DRAM_BANK_ARB__AGEBASED_BANKARB_MASK 0x00000001L |
11012 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_CYCLIM_MASK 0x000000FEL |
11013 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_REQLIM_MASK 0x00003F00L |
11014 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_STALLMODE_MASK 0x00004000L |
11015 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_RD_DECRATE_MASK 0x00018000L |
11016 | #define GCEA_DRAM_BANK_ARB__BANK_STAY_AWAY_WR_DECRATE_MASK 0x00060000L |
11017 | //GCEA_DRAM_BANK_ARB_RFSH |
11018 | #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_INTERVAL__SHIFT 0x0 |
11019 | #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_CYCLE__SHIFT 0xc |
11020 | #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_ENABLE__SHIFT 0x15 |
11021 | #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_PAIRMSB__SHIFT 0x16 |
11022 | #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_INTERVAL_MASK 0x00000FFFL |
11023 | #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_CYCLE_MASK 0x001FF000L |
11024 | #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_ENABLE_MASK 0x00200000L |
11025 | #define GCEA_DRAM_BANK_ARB_RFSH__REFRESH_P2B_PAIRMSB_MASK 0x00400000L |
11026 | //GCEA_SDP_BACKDOOR_CMDCREDITS0 |
11027 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0 |
11028 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7 |
11029 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe |
11030 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15 |
11031 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c |
11032 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL |
11033 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L |
11034 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L |
11035 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L |
11036 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L |
11037 | //GCEA_SDP_BACKDOOR_CMDCREDITS1 |
11038 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0 |
11039 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3 |
11040 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa |
11041 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11 |
11042 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18 |
11043 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L |
11044 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L |
11045 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L |
11046 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L |
11047 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L |
11048 | //GCEA_SDP_BACKDOOR_DATACREDITS0 |
11049 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0 |
11050 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7 |
11051 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe |
11052 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15 |
11053 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c |
11054 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL |
11055 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L |
11056 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L |
11057 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L |
11058 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L |
11059 | //GCEA_SDP_BACKDOOR_DATACREDITS1 |
11060 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0 |
11061 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3 |
11062 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa |
11063 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11 |
11064 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18 |
11065 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L |
11066 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L |
11067 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L |
11068 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L |
11069 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L |
11070 | //GCEA_SDP_BACKDOOR_MISCCREDITS |
11071 | #define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0 |
11072 | #define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8 |
11073 | #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT 0x10 |
11074 | #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT 0x17 |
11075 | #define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL |
11076 | #define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L |
11077 | #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007F0000L |
11078 | #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3F800000L |
11079 | //GCEA_ADDRDECDRAM_ADDR_HASH_PACH |
11080 | #define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__XOR_ENABLE__SHIFT 0x0 |
11081 | #define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__NA_XOR__SHIFT 0x1 |
11082 | #define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__XOR_ENABLE_MASK 0x00000001L |
11083 | #define GCEA_ADDRDECDRAM_ADDR_HASH_PACH__NA_XOR_MASK 0xFFFFFFFEL |
11084 | //GCEA_RRET_MEM_RESERVE |
11085 | #define GCEA_RRET_MEM_RESERVE__VC0__SHIFT 0x0 |
11086 | #define GCEA_RRET_MEM_RESERVE__VC1__SHIFT 0x4 |
11087 | #define GCEA_RRET_MEM_RESERVE__VC2__SHIFT 0x8 |
11088 | #define GCEA_RRET_MEM_RESERVE__VC3__SHIFT 0xc |
11089 | #define GCEA_RRET_MEM_RESERVE__VC4__SHIFT 0x10 |
11090 | #define GCEA_RRET_MEM_RESERVE__VC5__SHIFT 0x14 |
11091 | #define GCEA_RRET_MEM_RESERVE__VC6__SHIFT 0x18 |
11092 | #define GCEA_RRET_MEM_RESERVE__VC7__SHIFT 0x1c |
11093 | #define GCEA_RRET_MEM_RESERVE__VC0_MASK 0x0000000FL |
11094 | #define GCEA_RRET_MEM_RESERVE__VC1_MASK 0x000000F0L |
11095 | #define GCEA_RRET_MEM_RESERVE__VC2_MASK 0x00000F00L |
11096 | #define GCEA_RRET_MEM_RESERVE__VC3_MASK 0x0000F000L |
11097 | #define GCEA_RRET_MEM_RESERVE__VC4_MASK 0x000F0000L |
11098 | #define GCEA_RRET_MEM_RESERVE__VC5_MASK 0x00F00000L |
11099 | #define GCEA_RRET_MEM_RESERVE__VC6_MASK 0x0F000000L |
11100 | #define GCEA_RRET_MEM_RESERVE__VC7_MASK 0xF0000000L |
11101 | //GCEA_ADDRDEC_SELECT |
11102 | #define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 |
11103 | #define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 |
11104 | #define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa |
11105 | #define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf |
11106 | #define GCEA_ADDRDEC_SELECT__DRAM_GECC_ENABLE__SHIFT 0x14 |
11107 | #define GCEA_ADDRDEC_SELECT__GMI_GECC_ENABLE__SHIFT 0x15 |
11108 | #define GCEA_ADDRDEC_SELECT__DRAM_SKIP_MSB__SHIFT 0x16 |
11109 | #define GCEA_ADDRDEC_SELECT__GMI_SKIP_MSB__SHIFT 0x17 |
11110 | #define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL |
11111 | #define GCEA_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L |
11112 | #define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L |
11113 | #define GCEA_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L |
11114 | #define GCEA_ADDRDEC_SELECT__DRAM_GECC_ENABLE_MASK 0x00100000L |
11115 | #define GCEA_ADDRDEC_SELECT__GMI_GECC_ENABLE_MASK 0x00200000L |
11116 | #define GCEA_ADDRDEC_SELECT__DRAM_SKIP_MSB_MASK 0x00400000L |
11117 | #define GCEA_ADDRDEC_SELECT__GMI_SKIP_MSB_MASK 0x00800000L |
11118 | //GCEA_SDP_ENABLE |
11119 | #define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0 |
11120 | #define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L |
11121 | |
11122 | |
11123 | // addressBlock: gc_rmi_rmidec |
11124 | //RMI_GENERAL_CNTL |
11125 | #define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0 |
11126 | #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1 |
11127 | #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11 |
11128 | #define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13 |
11129 | #define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14 |
11130 | #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15 |
11131 | #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19 |
11132 | #define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a |
11133 | #define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b |
11134 | #define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c |
11135 | #define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d |
11136 | #define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e |
11137 | #define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L |
11138 | #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL |
11139 | #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L |
11140 | #define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L |
11141 | #define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L |
11142 | #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L |
11143 | #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L |
11144 | #define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L |
11145 | #define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L |
11146 | #define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L |
11147 | #define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L |
11148 | #define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L |
11149 | //RMI_GENERAL_CNTL1 |
11150 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0 |
11151 | #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4 |
11152 | #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6 |
11153 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8 |
11154 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9 |
11155 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xb |
11156 | #define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xc |
11157 | #define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xd |
11158 | #define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE__SHIFT 0xe |
11159 | #define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE__SHIFT 0xf |
11160 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL |
11161 | #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L |
11162 | #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L |
11163 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L |
11164 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000600L |
11165 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000800L |
11166 | #define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00001000L |
11167 | #define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00002000L |
11168 | #define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE_MASK 0x00004000L |
11169 | #define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE_MASK 0x00008000L |
11170 | //RMI_GENERAL_STATUS |
11171 | #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0 |
11172 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1 |
11173 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2 |
11174 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3 |
11175 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4 |
11176 | #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5 |
11177 | #define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6 |
11178 | #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7 |
11179 | #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8 |
11180 | #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9 |
11181 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa |
11182 | #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb |
11183 | #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc |
11184 | #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd |
11185 | #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe |
11186 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf |
11187 | #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10 |
11188 | #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11 |
11189 | #define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12 |
11190 | #define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13 |
11191 | #define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14 |
11192 | #define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15 |
11193 | #define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d |
11194 | #define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e |
11195 | #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f |
11196 | #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L |
11197 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L |
11198 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L |
11199 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L |
11200 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L |
11201 | #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L |
11202 | #define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L |
11203 | #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L |
11204 | #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L |
11205 | #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L |
11206 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L |
11207 | #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L |
11208 | #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L |
11209 | #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L |
11210 | #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L |
11211 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L |
11212 | #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L |
11213 | #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L |
11214 | #define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L |
11215 | #define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L |
11216 | #define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L |
11217 | #define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L |
11218 | #define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L |
11219 | #define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L |
11220 | #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L |
11221 | //RMI_SUBBLOCK_STATUS0 |
11222 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0 |
11223 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7 |
11224 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8 |
11225 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9 |
11226 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10 |
11227 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11 |
11228 | #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12 |
11229 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL |
11230 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L |
11231 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L |
11232 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L |
11233 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L |
11234 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L |
11235 | #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L |
11236 | //RMI_SUBBLOCK_STATUS1 |
11237 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0 |
11238 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa |
11239 | #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14 |
11240 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL |
11241 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L |
11242 | #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L |
11243 | //RMI_SUBBLOCK_STATUS2 |
11244 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0 |
11245 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9 |
11246 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL |
11247 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L |
11248 | //RMI_SUBBLOCK_STATUS3 |
11249 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0 |
11250 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa |
11251 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL |
11252 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L |
11253 | //RMI_XBAR_CONFIG |
11254 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0 |
11255 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2 |
11256 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6 |
11257 | #define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7 |
11258 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8 |
11259 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc |
11260 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd |
11261 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe |
11262 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L |
11263 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL |
11264 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L |
11265 | #define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L |
11266 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L |
11267 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L |
11268 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L |
11269 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L |
11270 | //RMI_PROBE_POP_LOGIC_CNTL |
11271 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0 |
11272 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7 |
11273 | #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8 |
11274 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa |
11275 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11 |
11276 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL |
11277 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L |
11278 | #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L |
11279 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L |
11280 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L |
11281 | //RMI_UTC_XNACK_N_MISC_CNTL |
11282 | #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0 |
11283 | #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8 |
11284 | #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc |
11285 | #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd |
11286 | #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL |
11287 | #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L |
11288 | #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L |
11289 | #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L |
11290 | //RMI_DEMUX_CNTL |
11291 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0 |
11292 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1 |
11293 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN__SHIFT 0x2 |
11294 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4 |
11295 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6 |
11296 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe |
11297 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10 |
11298 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11 |
11299 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN__SHIFT 0x12 |
11300 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14 |
11301 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16 |
11302 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e |
11303 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L |
11304 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L |
11305 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN_MASK 0x00000004L |
11306 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L |
11307 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L |
11308 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L |
11309 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L |
11310 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L |
11311 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN_MASK 0x00040000L |
11312 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L |
11313 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L |
11314 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L |
11315 | //RMI_UTCL1_CNTL1 |
11316 | #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
11317 | #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
11318 | #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
11319 | #define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 |
11320 | #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
11321 | #define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 |
11322 | #define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 |
11323 | #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
11324 | #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
11325 | #define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 |
11326 | #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 |
11327 | #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 |
11328 | #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
11329 | #define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a |
11330 | #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
11331 | #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
11332 | #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
11333 | #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
11334 | #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
11335 | #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
11336 | #define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L |
11337 | #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
11338 | #define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L |
11339 | #define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L |
11340 | #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
11341 | #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
11342 | #define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L |
11343 | #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L |
11344 | #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L |
11345 | #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
11346 | #define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L |
11347 | #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
11348 | #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
11349 | #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
11350 | //RMI_UTCL1_CNTL2 |
11351 | #define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0 |
11352 | #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
11353 | #define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa |
11354 | #define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb |
11355 | #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
11356 | #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
11357 | #define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe |
11358 | #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
11359 | #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10 |
11360 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
11361 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13 |
11362 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
11363 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15 |
11364 | #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19 |
11365 | #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
11366 | #define RMI_UTCL1_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b |
11367 | #define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c |
11368 | #define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT__SHIFT 0x1d |
11369 | #define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL |
11370 | #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
11371 | #define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L |
11372 | #define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L |
11373 | #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
11374 | #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
11375 | #define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
11376 | #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
11377 | #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L |
11378 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
11379 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L |
11380 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
11381 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L |
11382 | #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L |
11383 | #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
11384 | #define RMI_UTCL1_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L |
11385 | #define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L |
11386 | #define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT_MASK 0x20000000L |
11387 | //RMI_TCIW_FORMATTER0_CNTL |
11388 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0 |
11389 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1 |
11390 | #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 |
11391 | #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13 |
11392 | #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b |
11393 | #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c |
11394 | #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d |
11395 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e |
11396 | #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f |
11397 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L |
11398 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL |
11399 | #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L |
11400 | #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L |
11401 | #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L |
11402 | #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L |
11403 | #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L |
11404 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L |
11405 | #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L |
11406 | //RMI_TCIW_FORMATTER1_CNTL |
11407 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0 |
11408 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1 |
11409 | #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 |
11410 | #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13 |
11411 | #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b |
11412 | #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c |
11413 | #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d |
11414 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e |
11415 | #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f |
11416 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L |
11417 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL |
11418 | #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L |
11419 | #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L |
11420 | #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L |
11421 | #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L |
11422 | #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L |
11423 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L |
11424 | #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L |
11425 | //RMI_SCOREBOARD_CNTL |
11426 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0 |
11427 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1 |
11428 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2 |
11429 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3 |
11430 | #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4 |
11431 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5 |
11432 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6 |
11433 | #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7 |
11434 | #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8 |
11435 | #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9 |
11436 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L |
11437 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L |
11438 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L |
11439 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L |
11440 | #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L |
11441 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L |
11442 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L |
11443 | #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L |
11444 | #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L |
11445 | #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L |
11446 | //RMI_SCOREBOARD_STATUS0 |
11447 | #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0 |
11448 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1 |
11449 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2 |
11450 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12 |
11451 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13 |
11452 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14 |
11453 | #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15 |
11454 | #define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT__SHIFT 0x16 |
11455 | #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L |
11456 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L |
11457 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL |
11458 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L |
11459 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L |
11460 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L |
11461 | #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L |
11462 | #define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT_MASK 0x07C00000L |
11463 | //RMI_SCOREBOARD_STATUS1 |
11464 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0 |
11465 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc |
11466 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd |
11467 | #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe |
11468 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf |
11469 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b |
11470 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c |
11471 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d |
11472 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e |
11473 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL |
11474 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L |
11475 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L |
11476 | #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L |
11477 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L |
11478 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L |
11479 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L |
11480 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L |
11481 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L |
11482 | //RMI_SCOREBOARD_STATUS2 |
11483 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0 |
11484 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc |
11485 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd |
11486 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19 |
11487 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a |
11488 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b |
11489 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c |
11490 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d |
11491 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e |
11492 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f |
11493 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL |
11494 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L |
11495 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L |
11496 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L |
11497 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L |
11498 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L |
11499 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L |
11500 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L |
11501 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L |
11502 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L |
11503 | //RMI_XBAR_ARBITER_CONFIG |
11504 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0 |
11505 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2 |
11506 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3 |
11507 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4 |
11508 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN__SHIFT 0x5 |
11509 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6 |
11510 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8 |
11511 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10 |
11512 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12 |
11513 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13 |
11514 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14 |
11515 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN__SHIFT 0x15 |
11516 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16 |
11517 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18 |
11518 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L |
11519 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L |
11520 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L |
11521 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L |
11522 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN_MASK 0x00000020L |
11523 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L |
11524 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L |
11525 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L |
11526 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L |
11527 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L |
11528 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L |
11529 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN_MASK 0x00200000L |
11530 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L |
11531 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L |
11532 | //RMI_XBAR_ARBITER_CONFIG_1 |
11533 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0 |
11534 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8 |
11535 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10 |
11536 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18 |
11537 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL |
11538 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L |
11539 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L |
11540 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L |
11541 | //RMI_CLOCK_CNTRL |
11542 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0 |
11543 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5 |
11544 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa |
11545 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf |
11546 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14 |
11547 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19 |
11548 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL |
11549 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L |
11550 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L |
11551 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L |
11552 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L |
11553 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L |
11554 | //RMI_UTCL1_STATUS |
11555 | #define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
11556 | #define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
11557 | #define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
11558 | #define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
11559 | #define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
11560 | #define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
11561 | //RMI_RB_GLX_CID_MAP |
11562 | #define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP__SHIFT 0x0 |
11563 | #define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP__SHIFT 0x4 |
11564 | #define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP__SHIFT 0x8 |
11565 | #define RMI_RB_GLX_CID_MAP__CB_DCC_MAP__SHIFT 0xc |
11566 | #define RMI_RB_GLX_CID_MAP__DB_Z_MAP__SHIFT 0x10 |
11567 | #define RMI_RB_GLX_CID_MAP__DB_S_MAP__SHIFT 0x14 |
11568 | #define RMI_RB_GLX_CID_MAP__DB_TILE_MAP__SHIFT 0x18 |
11569 | #define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP__SHIFT 0x1c |
11570 | #define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP_MASK 0x0000000FL |
11571 | #define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP_MASK 0x000000F0L |
11572 | #define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP_MASK 0x00000F00L |
11573 | #define RMI_RB_GLX_CID_MAP__CB_DCC_MAP_MASK 0x0000F000L |
11574 | #define RMI_RB_GLX_CID_MAP__DB_Z_MAP_MASK 0x000F0000L |
11575 | #define RMI_RB_GLX_CID_MAP__DB_S_MAP_MASK 0x00F00000L |
11576 | #define RMI_RB_GLX_CID_MAP__DB_TILE_MAP_MASK 0x0F000000L |
11577 | #define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP_MASK 0xF0000000L |
11578 | //RMI_SPARE |
11579 | #define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0 |
11580 | #define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE__SHIFT 0x1 |
11581 | #define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE__SHIFT 0x2 |
11582 | #define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE__SHIFT 0x3 |
11583 | #define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS__SHIFT 0x4 |
11584 | #define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS__SHIFT 0x5 |
11585 | #define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6 |
11586 | #define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7 |
11587 | #define RMI_SPARE__NOFILL_RMI_CID_CC__SHIFT 0x8 |
11588 | #define RMI_SPARE__NOFILL_RMI_CID_FC__SHIFT 0x9 |
11589 | #define RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT 0xa |
11590 | #define RMI_SPARE__NOFILL_RMI_CID_DC__SHIFT 0xb |
11591 | #define RMI_SPARE__NOFILL_RMI_CID_Z__SHIFT 0xc |
11592 | #define RMI_SPARE__NOFILL_RMI_CID_S__SHIFT 0xd |
11593 | #define RMI_SPARE__NOFILL_RMI_CID_TILE__SHIFT 0xe |
11594 | #define RMI_SPARE__SPARE_BIT_15_0__SHIFT 0xf |
11595 | #define RMI_SPARE__ARBITER_ADDRESS_MASK__SHIFT 0x10 |
11596 | #define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L |
11597 | #define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE_MASK 0x00000002L |
11598 | #define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE_MASK 0x00000004L |
11599 | #define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE_MASK 0x00000008L |
11600 | #define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS_MASK 0x00000010L |
11601 | #define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS_MASK 0x00000020L |
11602 | #define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L |
11603 | #define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L |
11604 | #define RMI_SPARE__NOFILL_RMI_CID_CC_MASK 0x00000100L |
11605 | #define RMI_SPARE__NOFILL_RMI_CID_FC_MASK 0x00000200L |
11606 | #define RMI_SPARE__NOFILL_RMI_CID_CM_MASK 0x00000400L |
11607 | #define RMI_SPARE__NOFILL_RMI_CID_DC_MASK 0x00000800L |
11608 | #define RMI_SPARE__NOFILL_RMI_CID_Z_MASK 0x00001000L |
11609 | #define RMI_SPARE__NOFILL_RMI_CID_S_MASK 0x00002000L |
11610 | #define RMI_SPARE__NOFILL_RMI_CID_TILE_MASK 0x00004000L |
11611 | #define RMI_SPARE__SPARE_BIT_15_0_MASK 0x00008000L |
11612 | #define RMI_SPARE__ARBITER_ADDRESS_MASK_MASK 0xFFFF0000L |
11613 | //RMI_SPARE_1 |
11614 | #define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0 |
11615 | #define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1 |
11616 | #define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2 |
11617 | #define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3 |
11618 | #define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4 |
11619 | #define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5 |
11620 | #define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6 |
11621 | #define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7 |
11622 | #define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID__SHIFT 0x8 |
11623 | #define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10 |
11624 | #define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L |
11625 | #define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L |
11626 | #define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L |
11627 | #define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L |
11628 | #define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L |
11629 | #define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L |
11630 | #define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L |
11631 | #define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L |
11632 | #define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID_MASK 0x0000FF00L |
11633 | #define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L |
11634 | //RMI_SPARE_2 |
11635 | #define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0 |
11636 | #define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1 |
11637 | #define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2 |
11638 | #define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3 |
11639 | #define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4 |
11640 | #define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5 |
11641 | #define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6 |
11642 | #define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7 |
11643 | #define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8 |
11644 | #define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc |
11645 | #define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10 |
11646 | #define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18 |
11647 | #define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L |
11648 | #define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L |
11649 | #define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L |
11650 | #define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L |
11651 | #define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L |
11652 | #define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L |
11653 | #define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L |
11654 | #define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L |
11655 | #define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L |
11656 | #define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L |
11657 | #define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L |
11658 | #define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L |
11659 | //CC_RMI_REDUNDANCY |
11660 | #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1 |
11661 | #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2 |
11662 | #define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3 |
11663 | #define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4 |
11664 | #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L |
11665 | #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L |
11666 | #define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L |
11667 | #define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L |
11668 | //GC_USER_RMI_REDUNDANCY |
11669 | #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1 |
11670 | #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2 |
11671 | #define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3 |
11672 | #define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4 |
11673 | #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L |
11674 | #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L |
11675 | #define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L |
11676 | #define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L |
11677 | |
11678 | |
11679 | // addressBlock: gc_pmmdec |
11680 | //PMM_GENERAL_CNTL |
11681 | #define PMM_GENERAL_CNTL__PMM_MODE__SHIFT 0x0 |
11682 | #define PMM_GENERAL_CNTL__PMM_DISABLE__SHIFT 0x1 |
11683 | #define PMM_GENERAL_CNTL__PMM_ALOG_IH_IDLE__SHIFT 0x2 |
11684 | #define PMM_GENERAL_CNTL__PMM_MODE_MASK 0x00000001L |
11685 | #define PMM_GENERAL_CNTL__PMM_DISABLE_MASK 0x00000002L |
11686 | #define PMM_GENERAL_CNTL__PMM_ALOG_IH_IDLE_MASK 0x00000004L |
11687 | //GCR_PIO_CNTL |
11688 | #define GCR_PIO_CNTL__GCR_DATA_INDEX__SHIFT 0x0 |
11689 | #define GCR_PIO_CNTL__GCR_REG_DONE__SHIFT 0x2 |
11690 | #define GCR_PIO_CNTL__GCR_REG_RESET__SHIFT 0x3 |
11691 | #define GCR_PIO_CNTL__GCR_PIO_RSP_TAG__SHIFT 0x10 |
11692 | #define GCR_PIO_CNTL__GCR_PIO_RSP_DONE__SHIFT 0x1e |
11693 | #define GCR_PIO_CNTL__GCR_READY__SHIFT 0x1f |
11694 | #define GCR_PIO_CNTL__GCR_DATA_INDEX_MASK 0x00000003L |
11695 | #define GCR_PIO_CNTL__GCR_REG_DONE_MASK 0x00000004L |
11696 | #define GCR_PIO_CNTL__GCR_REG_RESET_MASK 0x00000008L |
11697 | #define GCR_PIO_CNTL__GCR_PIO_RSP_TAG_MASK 0x00FF0000L |
11698 | #define GCR_PIO_CNTL__GCR_PIO_RSP_DONE_MASK 0x40000000L |
11699 | #define GCR_PIO_CNTL__GCR_READY_MASK 0x80000000L |
11700 | //GCR_PIO_DATA |
11701 | #define GCR_PIO_DATA__GCR_DATA__SHIFT 0x0 |
11702 | #define GCR_PIO_DATA__GCR_DATA_MASK 0xFFFFFFFFL |
11703 | //GCR_GENERAL_CNTL |
11704 | #define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP__SHIFT 0x0 |
11705 | #define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ__SHIFT 0x1 |
11706 | #define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ__SHIFT 0x2 |
11707 | #define GCR_GENERAL_CNTL__FORCE_INV_ALL__SHIFT 0x3 |
11708 | #define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL__SHIFT 0x4 |
11709 | #define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE__SHIFT 0x6 |
11710 | #define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE__SHIFT 0x7 |
11711 | #define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE__SHIFT 0x8 |
11712 | #define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ__SHIFT 0x9 |
11713 | #define GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT 0xa |
11714 | #define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS__SHIFT 0xd |
11715 | #define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS__SHIFT 0xe |
11716 | #define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ__SHIFT 0xf |
11717 | #define GCR_GENERAL_CNTL__CLIENT_ID__SHIFT 0x14 |
11718 | #define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP_MASK 0x00000001L |
11719 | #define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ_MASK 0x00000002L |
11720 | #define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK 0x00000004L |
11721 | #define GCR_GENERAL_CNTL__FORCE_INV_ALL_MASK 0x00000008L |
11722 | #define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL_MASK 0x00000030L |
11723 | #define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE_MASK 0x00000040L |
11724 | #define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE_MASK 0x00000080L |
11725 | #define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE_MASK 0x00000100L |
11726 | #define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ_MASK 0x00000200L |
11727 | #define GCR_GENERAL_CNTL__UTCL2_REQ_PERM_MASK 0x00001C00L |
11728 | #define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS_MASK 0x00002000L |
11729 | #define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS_MASK 0x00004000L |
11730 | #define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ_MASK 0x00008000L |
11731 | #define GCR_GENERAL_CNTL__CLIENT_ID_MASK 0x1FF00000L |
11732 | //GCR_TARGET_DISABLE |
11733 | #define GCR_TARGET_DISABLE__DISABLE_SA0_PHY__SHIFT 0x0 |
11734 | #define GCR_TARGET_DISABLE__DISABLE_SA0_VIRT__SHIFT 0x1 |
11735 | #define GCR_TARGET_DISABLE__DISABLE_SA1_PHY__SHIFT 0x2 |
11736 | #define GCR_TARGET_DISABLE__DISABLE_SA1_VIRT__SHIFT 0x3 |
11737 | #define GCR_TARGET_DISABLE__DISABLE_SA2_PHY__SHIFT 0x4 |
11738 | #define GCR_TARGET_DISABLE__DISABLE_SA2_VIRT__SHIFT 0x5 |
11739 | #define GCR_TARGET_DISABLE__DISABLE_SA3_PHY__SHIFT 0x6 |
11740 | #define GCR_TARGET_DISABLE__DISABLE_SA3_VIRT__SHIFT 0x7 |
11741 | #define GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY__SHIFT 0x8 |
11742 | #define GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY__SHIFT 0x9 |
11743 | #define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY__SHIFT 0xa |
11744 | #define GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY__SHIFT 0xb |
11745 | #define GCR_TARGET_DISABLE__DISABLE_SA0_PHY_MASK 0x00000001L |
11746 | #define GCR_TARGET_DISABLE__DISABLE_SA0_VIRT_MASK 0x00000002L |
11747 | #define GCR_TARGET_DISABLE__DISABLE_SA1_PHY_MASK 0x00000004L |
11748 | #define GCR_TARGET_DISABLE__DISABLE_SA1_VIRT_MASK 0x00000008L |
11749 | #define GCR_TARGET_DISABLE__DISABLE_SA2_PHY_MASK 0x00000010L |
11750 | #define GCR_TARGET_DISABLE__DISABLE_SA2_VIRT_MASK 0x00000020L |
11751 | #define GCR_TARGET_DISABLE__DISABLE_SA3_PHY_MASK 0x00000040L |
11752 | #define GCR_TARGET_DISABLE__DISABLE_SA3_VIRT_MASK 0x00000080L |
11753 | #define GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY_MASK 0x00000100L |
11754 | #define GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY_MASK 0x00000200L |
11755 | #define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY_MASK 0x00000400L |
11756 | #define GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY_MASK 0x00000800L |
11757 | //GCR_CMD_STATUS |
11758 | #define GCR_CMD_STATUS__GCR_CONTROL__SHIFT 0x0 |
11759 | #define GCR_CMD_STATUS__GCR_SRC__SHIFT 0x14 |
11760 | #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN__SHIFT 0x17 |
11761 | #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID__SHIFT 0x18 |
11762 | #define GCR_CMD_STATUS__UTCL2_NACK_STATUS__SHIFT 0x1c |
11763 | #define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR__SHIFT 0x1e |
11764 | #define GCR_CMD_STATUS__UTCL2_NACK_ERROR__SHIFT 0x1f |
11765 | #define GCR_CMD_STATUS__GCR_CONTROL_MASK 0x0007FFFFL |
11766 | #define GCR_CMD_STATUS__GCR_SRC_MASK 0x00700000L |
11767 | #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_MASK 0x00800000L |
11768 | #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID_MASK 0x0F000000L |
11769 | #define GCR_CMD_STATUS__UTCL2_NACK_STATUS_MASK 0x30000000L |
11770 | #define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR_MASK 0x40000000L |
11771 | #define GCR_CMD_STATUS__UTCL2_NACK_ERROR_MASK 0x80000000L |
11772 | //GCR_SPARE |
11773 | #define GCR_SPARE__SPARE_BIT_1__SHIFT 0x1 |
11774 | #define GCR_SPARE__SPARE_BIT_2__SHIFT 0x2 |
11775 | #define GCR_SPARE__SPARE_BIT_3__SHIFT 0x3 |
11776 | #define GCR_SPARE__SPARE_BIT_4__SHIFT 0x4 |
11777 | #define GCR_SPARE__SPARE_BIT_5__SHIFT 0x5 |
11778 | #define GCR_SPARE__SPARE_BIT_6__SHIFT 0x6 |
11779 | #define GCR_SPARE__SPARE_BIT_7__SHIFT 0x7 |
11780 | #define GCR_SPARE__SPARE_BIT_8_0__SHIFT 0x8 |
11781 | #define GCR_SPARE__SPARE_BIT_31_16__SHIFT 0x10 |
11782 | #define GCR_SPARE__SPARE_BIT_1_MASK 0x00000002L |
11783 | #define GCR_SPARE__SPARE_BIT_2_MASK 0x00000004L |
11784 | #define GCR_SPARE__SPARE_BIT_3_MASK 0x00000008L |
11785 | #define GCR_SPARE__SPARE_BIT_4_MASK 0x00000010L |
11786 | #define GCR_SPARE__SPARE_BIT_5_MASK 0x00000020L |
11787 | #define GCR_SPARE__SPARE_BIT_6_MASK 0x00000040L |
11788 | #define GCR_SPARE__SPARE_BIT_7_MASK 0x00000080L |
11789 | #define GCR_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L |
11790 | #define GCR_SPARE__SPARE_BIT_31_16_MASK 0xFFFF0000L |
11791 | |
11792 | |
11793 | // addressBlock: gc_utcl1dec |
11794 | //UTCL1_CTRL |
11795 | #define UTCL1_CTRL__UTCL1_SMALL_PAGE_SIZE__SHIFT 0x0 |
11796 | #define UTCL1_CTRL__UTCL1_LARGE_PAGE_SIZE__SHIFT 0x1 |
11797 | #define UTCL1_CTRL__UTCL1_CACHE_CORE_BYPASS__SHIFT 0x2 |
11798 | #define UTCL1_CTRL__UTCL1_TCP_BYPASS__SHIFT 0x3 |
11799 | #define UTCL1_CTRL__UTCL1_SQCI_BYPASS__SHIFT 0x4 |
11800 | #define UTCL1_CTRL__UTCL1_SQCD_BYPASS__SHIFT 0x5 |
11801 | #define UTCL1_CTRL__UTCL1_RMI_BYPASS__SHIFT 0x6 |
11802 | #define UTCL1_CTRL__UTCL1_SQG_BYPASS__SHIFT 0x7 |
11803 | #define UTCL1_CTRL__UTCL1_RMI_DEDICATED_CACHE_CORE__SHIFT 0x8 |
11804 | #define UTCL1_CTRL__UTCL1_FORCE_RANGE_INV_TO_VMID__SHIFT 0x9 |
11805 | #define UTCL1_CTRL__UTCL1_FORCE_INV_ALL__SHIFT 0xa |
11806 | #define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_DONE__SHIFT 0xb |
11807 | #define UTCL1_CTRL__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE__SHIFT 0xc |
11808 | #define UTCL1_CTRL__UTCL1_INV_FILTER_2M__SHIFT 0xd |
11809 | #define UTCL1_CTRL__UTCL1_RANGE_INV_FORCE_CHK_ALL__SHIFT 0xe |
11810 | #define UTCL1_CTRL__RESERVED__SHIFT 0xf |
11811 | #define UTCL1_CTRL__UTCL1_MH_INV_FRAG_SIZE_OVERRIDE__SHIFT 0x12 |
11812 | #define UTCL1_CTRL__UTCL1_CACHE_WRITE_PERM__SHIFT 0x13 |
11813 | #define UTCL1_CTRL__UTCL1_MH_CAM_DUPLICATE_4K_FILTER__SHIFT 0x14 |
11814 | #define UTCL1_CTRL__UTCL1_MH_DISABLE_DUPLICATES__SHIFT 0x15 |
11815 | #define UTCL1_CTRL__UTCL1_MH_DISABLE_REQUEST_SQUASHING__SHIFT 0x16 |
11816 | #define UTCL1_CTRL__UTCL1_MH_DISABLE_RECENT_BUFFER__SHIFT 0x17 |
11817 | #define UTCL1_CTRL__UTCL1_MISS_CC_PRIORITY__SHIFT 0x18 |
11818 | #define UTCL1_CTRL__UTCL1_REDUCE_CC_SIZE__SHIFT 0x1a |
11819 | #define UTCL1_CTRL__UTCL1_REDUCE_MH_CFIFO_SIZE__SHIFT 0x1c |
11820 | #define UTCL1_CTRL__UTCL1_REDUCE_MH_CAM_SIZE__SHIFT 0x1e |
11821 | #define UTCL1_CTRL__UTCL1_SMALL_PAGE_SIZE_MASK 0x00000001L |
11822 | #define UTCL1_CTRL__UTCL1_LARGE_PAGE_SIZE_MASK 0x00000002L |
11823 | #define UTCL1_CTRL__UTCL1_CACHE_CORE_BYPASS_MASK 0x00000004L |
11824 | #define UTCL1_CTRL__UTCL1_TCP_BYPASS_MASK 0x00000008L |
11825 | #define UTCL1_CTRL__UTCL1_SQCI_BYPASS_MASK 0x00000010L |
11826 | #define UTCL1_CTRL__UTCL1_SQCD_BYPASS_MASK 0x00000020L |
11827 | #define UTCL1_CTRL__UTCL1_RMI_BYPASS_MASK 0x00000040L |
11828 | #define UTCL1_CTRL__UTCL1_SQG_BYPASS_MASK 0x00000080L |
11829 | #define UTCL1_CTRL__UTCL1_RMI_DEDICATED_CACHE_CORE_MASK 0x00000100L |
11830 | #define UTCL1_CTRL__UTCL1_FORCE_RANGE_INV_TO_VMID_MASK 0x00000200L |
11831 | #define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_MASK 0x00000400L |
11832 | #define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_DONE_MASK 0x00000800L |
11833 | #define UTCL1_CTRL__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE_MASK 0x00001000L |
11834 | #define UTCL1_CTRL__UTCL1_INV_FILTER_2M_MASK 0x00002000L |
11835 | #define UTCL1_CTRL__UTCL1_RANGE_INV_FORCE_CHK_ALL_MASK 0x00004000L |
11836 | #define UTCL1_CTRL__RESERVED_MASK 0x00038000L |
11837 | #define UTCL1_CTRL__UTCL1_MH_INV_FRAG_SIZE_OVERRIDE_MASK 0x00040000L |
11838 | #define UTCL1_CTRL__UTCL1_CACHE_WRITE_PERM_MASK 0x00080000L |
11839 | #define UTCL1_CTRL__UTCL1_MH_CAM_DUPLICATE_4K_FILTER_MASK 0x00100000L |
11840 | #define UTCL1_CTRL__UTCL1_MH_DISABLE_DUPLICATES_MASK 0x00200000L |
11841 | #define UTCL1_CTRL__UTCL1_MH_DISABLE_REQUEST_SQUASHING_MASK 0x00400000L |
11842 | #define UTCL1_CTRL__UTCL1_MH_DISABLE_RECENT_BUFFER_MASK 0x00800000L |
11843 | #define UTCL1_CTRL__UTCL1_MISS_CC_PRIORITY_MASK 0x03000000L |
11844 | #define UTCL1_CTRL__UTCL1_REDUCE_CC_SIZE_MASK 0x0C000000L |
11845 | #define UTCL1_CTRL__UTCL1_REDUCE_MH_CFIFO_SIZE_MASK 0x30000000L |
11846 | #define UTCL1_CTRL__UTCL1_REDUCE_MH_CAM_SIZE_MASK 0xC0000000L |
11847 | //UTCL1_ALOG |
11848 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD__SHIFT 0x0 |
11849 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS__SHIFT 0x3 |
11850 | #define UTCL1_ALOG__UTCL1_ALOG_ACTIVE__SHIFT 0x4 |
11851 | #define UTCL1_ALOG__UTCL1_ALOG_MODE__SHIFT 0x5 |
11852 | #define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW__SHIFT 0x6 |
11853 | #define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS__SHIFT 0x9 |
11854 | #define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT 0xa |
11855 | #define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN__SHIFT 0xc |
11856 | #define UTCL1_ALOG__UTCL1_ALOG_CLEAN__SHIFT 0xf |
11857 | #define UTCL1_ALOG__UTCL1_ALOG_IDLE__SHIFT 0x10 |
11858 | #define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE__SHIFT 0x11 |
11859 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS__SHIFT 0x17 |
11860 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC__SHIFT 0x18 |
11861 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD_MASK 0x00000007L |
11862 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS_MASK 0x00000008L |
11863 | #define UTCL1_ALOG__UTCL1_ALOG_ACTIVE_MASK 0x00000010L |
11864 | #define UTCL1_ALOG__UTCL1_ALOG_MODE_MASK 0x00000020L |
11865 | #define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW_MASK 0x000001C0L |
11866 | #define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS_MASK 0x00000200L |
11867 | #define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD_MASK 0x00000C00L |
11868 | #define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN_MASK 0x00007000L |
11869 | #define UTCL1_ALOG__UTCL1_ALOG_CLEAN_MASK 0x00008000L |
11870 | #define UTCL1_ALOG__UTCL1_ALOG_IDLE_MASK 0x00010000L |
11871 | #define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE_MASK 0x007E0000L |
11872 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS_MASK 0x00800000L |
11873 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC_MASK 0x01000000L |
11874 | //UTCL1_UTCL0_INVREQ_DISABLE |
11875 | #define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE__SHIFT 0x0 |
11876 | #define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE_MASK 0x01FFFFFFL |
11877 | //GCRD_SA_TARGETS_DISABLE |
11878 | #define GCRD_SA_TARGETS_DISABLE__GCRD_TARGETS_DISABLE__SHIFT 0x0 |
11879 | #define GCRD_SA_TARGETS_DISABLE__GCRD_TARGETS_DISABLE_MASK 0x0007FFFFL |
11880 | |
11881 | |
11882 | // addressBlock: gc_gcatcl2dec |
11883 | //GC_ATC_L2_CNTL |
11884 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 |
11885 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 |
11886 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 |
11887 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 |
11888 | #define GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 |
11889 | #define GC_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb |
11890 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L |
11891 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L |
11892 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L |
11893 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L |
11894 | #define GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L |
11895 | #define GC_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L |
11896 | //GC_ATC_L2_CNTL2 |
11897 | #define GC_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 |
11898 | #define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 |
11899 | #define GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 |
11900 | #define GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 |
11901 | #define GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc |
11902 | #define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf |
11903 | #define GC_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL |
11904 | #define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L |
11905 | #define GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L |
11906 | #define GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L |
11907 | #define GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L |
11908 | #define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L |
11909 | //GC_ATC_L2_CACHE_DATA0 |
11910 | #define GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 |
11911 | #define GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 |
11912 | #define GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 |
11913 | #define GC_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18 |
11914 | #define GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L |
11915 | #define GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L |
11916 | #define GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL |
11917 | #define GC_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L |
11918 | //GC_ATC_L2_CACHE_DATA1 |
11919 | #define GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 |
11920 | #define GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL |
11921 | //GC_ATC_L2_CACHE_DATA2 |
11922 | #define GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 |
11923 | #define GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL |
11924 | //GC_ATC_L2_CNTL3 |
11925 | #define GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 |
11926 | #define GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 |
11927 | #define GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9 |
11928 | #define GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0xc |
11929 | #define GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L |
11930 | #define GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L |
11931 | #define GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L |
11932 | #define GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x00001000L |
11933 | //GC_ATC_L2_STATUS |
11934 | #define GC_ATC_L2_STATUS__BUSY__SHIFT 0x0 |
11935 | #define GC_ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 |
11936 | #define GC_ATC_L2_STATUS__BUSY_MASK 0x00000001L |
11937 | #define GC_ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL |
11938 | //GC_ATC_L2_STATUS2 |
11939 | #define GC_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 |
11940 | #define GC_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 |
11941 | #define GC_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL |
11942 | #define GC_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L |
11943 | //GC_ATC_L2_MISC_CG |
11944 | #define GC_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 |
11945 | #define GC_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 |
11946 | #define GC_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 |
11947 | #define GC_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L |
11948 | #define GC_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L |
11949 | #define GC_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L |
11950 | //GC_ATC_L2_MEM_POWER_LS |
11951 | #define GC_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 |
11952 | #define GC_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 |
11953 | #define GC_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL |
11954 | #define GC_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L |
11955 | //GC_ATC_L2_CGTT_CLK_CTRL |
11956 | #define GC_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
11957 | #define GC_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
11958 | #define GC_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
11959 | #define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 |
11960 | #define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 |
11961 | #define GC_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
11962 | #define GC_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
11963 | #define GC_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
11964 | #define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L |
11965 | #define GC_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L |
11966 | //GC_ATC_L2_SDPPORT_CTRL |
11967 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 |
11968 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 |
11969 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 |
11970 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 |
11971 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 |
11972 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 |
11973 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 |
11974 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 |
11975 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 |
11976 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 |
11977 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L |
11978 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L |
11979 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L |
11980 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L |
11981 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L |
11982 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L |
11983 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L |
11984 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L |
11985 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L |
11986 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L |
11987 | |
11988 | |
11989 | // addressBlock: gc_gcvml2pfdec |
11990 | //GCVM_L2_CNTL |
11991 | #define GCVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 |
11992 | #define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 |
11993 | #define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 |
11994 | #define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 |
11995 | #define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 |
11996 | #define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 |
11997 | #define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa |
11998 | #define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb |
11999 | #define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc |
12000 | #define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf |
12001 | #define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 |
12002 | #define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 |
12003 | #define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 |
12004 | #define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a |
12005 | #define GCVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L |
12006 | #define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L |
12007 | #define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL |
12008 | #define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L |
12009 | #define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L |
12010 | #define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L |
12011 | #define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L |
12012 | #define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L |
12013 | #define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L |
12014 | #define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L |
12015 | #define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L |
12016 | #define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L |
12017 | #define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L |
12018 | #define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L |
12019 | //GCVM_L2_CNTL2 |
12020 | #define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 |
12021 | #define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 |
12022 | #define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 |
12023 | #define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 |
12024 | #define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 |
12025 | #define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a |
12026 | #define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c |
12027 | #define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L |
12028 | #define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L |
12029 | #define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L |
12030 | #define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L |
12031 | #define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L |
12032 | #define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L |
12033 | #define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L |
12034 | //GCVM_L2_CNTL3 |
12035 | #define GCVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 |
12036 | #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 |
12037 | #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 |
12038 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf |
12039 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 |
12040 | #define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 |
12041 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 |
12042 | #define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c |
12043 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d |
12044 | #define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e |
12045 | #define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f |
12046 | #define GCVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL |
12047 | #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L |
12048 | #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L |
12049 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L |
12050 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L |
12051 | #define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L |
12052 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L |
12053 | #define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L |
12054 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L |
12055 | #define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L |
12056 | #define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L |
12057 | //GCVM_L2_STATUS |
12058 | #define GCVM_L2_STATUS__L2_BUSY__SHIFT 0x0 |
12059 | #define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 |
12060 | #define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 |
12061 | #define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 |
12062 | #define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 |
12063 | #define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 |
12064 | #define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 |
12065 | #define GCVM_L2_STATUS__L2_BUSY_MASK 0x00000001L |
12066 | #define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL |
12067 | #define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L |
12068 | #define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L |
12069 | #define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L |
12070 | #define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L |
12071 | #define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L |
12072 | //GCVM_DUMMY_PAGE_FAULT_CNTL |
12073 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 |
12074 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 |
12075 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 |
12076 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L |
12077 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L |
12078 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL |
12079 | //GCVM_DUMMY_PAGE_FAULT_ADDR_LO32 |
12080 | #define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 |
12081 | #define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
12082 | //GCVM_DUMMY_PAGE_FAULT_ADDR_HI32 |
12083 | #define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 |
12084 | #define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL |
12085 | //GCVM_INVALIDATE_CNTL |
12086 | #define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 |
12087 | #define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 |
12088 | #define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL |
12089 | #define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L |
12090 | //GCVM_L2_PROTECTION_FAULT_CNTL |
12091 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 |
12092 | #define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 |
12093 | #define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 |
12094 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 |
12095 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 |
12096 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 |
12097 | #define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 |
12098 | #define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 |
12099 | #define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 |
12100 | #define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 |
12101 | #define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12102 | #define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb |
12103 | #define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12104 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd |
12105 | #define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d |
12106 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e |
12107 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f |
12108 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L |
12109 | #define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L |
12110 | #define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L |
12111 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L |
12112 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L |
12113 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L |
12114 | #define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L |
12115 | #define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L |
12116 | #define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L |
12117 | #define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L |
12118 | #define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12119 | #define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L |
12120 | #define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12121 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L |
12122 | #define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L |
12123 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L |
12124 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L |
12125 | //GCVM_L2_PROTECTION_FAULT_CNTL2 |
12126 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 |
12127 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 |
12128 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 |
12129 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 |
12130 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 |
12131 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL |
12132 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L |
12133 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L |
12134 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L |
12135 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L |
12136 | //GCVM_L2_PROTECTION_FAULT_MM_CNTL3 |
12137 | #define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 |
12138 | #define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL |
12139 | //GCVM_L2_PROTECTION_FAULT_MM_CNTL4 |
12140 | #define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 |
12141 | #define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL |
12142 | //GCVM_L2_PROTECTION_FAULT_STATUS |
12143 | #define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 |
12144 | #define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 |
12145 | #define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 |
12146 | #define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 |
12147 | #define GCVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 |
12148 | #define GCVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 |
12149 | #define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 |
12150 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 |
12151 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 |
12152 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 |
12153 | #define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L |
12154 | #define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL |
12155 | #define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L |
12156 | #define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L |
12157 | #define GCVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L |
12158 | #define GCVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L |
12159 | #define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L |
12160 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L |
12161 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L |
12162 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x3E000000L |
12163 | //GCVM_L2_PROTECTION_FAULT_ADDR_LO32 |
12164 | #define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 |
12165 | #define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
12166 | //GCVM_L2_PROTECTION_FAULT_ADDR_HI32 |
12167 | #define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 |
12168 | #define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL |
12169 | //GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 |
12170 | #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 |
12171 | #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
12172 | //GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 |
12173 | #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 |
12174 | #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL |
12175 | //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 |
12176 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
12177 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
12178 | //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 |
12179 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
12180 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
12181 | //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 |
12182 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
12183 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
12184 | //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 |
12185 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
12186 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
12187 | //GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 |
12188 | #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 |
12189 | #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL |
12190 | //GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 |
12191 | #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 |
12192 | #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL |
12193 | //GCVM_L2_CNTL4 |
12194 | #define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 |
12195 | #define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 |
12196 | #define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 |
12197 | #define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 |
12198 | #define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 |
12199 | #define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c |
12200 | #define GCVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d |
12201 | #define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL |
12202 | #define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L |
12203 | #define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L |
12204 | #define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L |
12205 | #define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L |
12206 | #define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L |
12207 | #define GCVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L |
12208 | //GCVM_L2_MM_GROUP_RT_CLASSES |
12209 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 |
12210 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 |
12211 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 |
12212 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 |
12213 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 |
12214 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 |
12215 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 |
12216 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 |
12217 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 |
12218 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 |
12219 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa |
12220 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb |
12221 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc |
12222 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd |
12223 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe |
12224 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf |
12225 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 |
12226 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 |
12227 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 |
12228 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 |
12229 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 |
12230 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 |
12231 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 |
12232 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 |
12233 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 |
12234 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 |
12235 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a |
12236 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b |
12237 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c |
12238 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d |
12239 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e |
12240 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f |
12241 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L |
12242 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L |
12243 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L |
12244 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L |
12245 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L |
12246 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L |
12247 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L |
12248 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L |
12249 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L |
12250 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L |
12251 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L |
12252 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L |
12253 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L |
12254 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L |
12255 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L |
12256 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L |
12257 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L |
12258 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L |
12259 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L |
12260 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L |
12261 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L |
12262 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L |
12263 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L |
12264 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L |
12265 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L |
12266 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L |
12267 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L |
12268 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L |
12269 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L |
12270 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L |
12271 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L |
12272 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L |
12273 | //GCVM_L2_BANK_SELECT_RESERVED_CID |
12274 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 |
12275 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa |
12276 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 |
12277 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 |
12278 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 |
12279 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a |
12280 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL |
12281 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L |
12282 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L |
12283 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L |
12284 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L |
12285 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L |
12286 | //GCVM_L2_BANK_SELECT_RESERVED_CID2 |
12287 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 |
12288 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa |
12289 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 |
12290 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 |
12291 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 |
12292 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a |
12293 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL |
12294 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L |
12295 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L |
12296 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L |
12297 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L |
12298 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L |
12299 | //GCVM_L2_CACHE_PARITY_CNTL |
12300 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 |
12301 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 |
12302 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 |
12303 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 |
12304 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 |
12305 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 |
12306 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 |
12307 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 |
12308 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc |
12309 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L |
12310 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L |
12311 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L |
12312 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L |
12313 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L |
12314 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L |
12315 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L |
12316 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L |
12317 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L |
12318 | //GCVM_L2_CGTT_CLK_CTRL |
12319 | #define GCVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
12320 | #define GCVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
12321 | #define GCVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
12322 | #define GCVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 |
12323 | #define GCVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 |
12324 | #define GCVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
12325 | #define GCVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
12326 | #define GCVM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
12327 | #define GCVM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L |
12328 | #define GCVM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L |
12329 | //GCVM_L2_CNTL5 |
12330 | #define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
12331 | #define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 |
12332 | #define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
12333 | #define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L |
12334 | //GCVM_L2_GCR_CNTL |
12335 | #define GCVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 |
12336 | #define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 |
12337 | #define GCVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L |
12338 | #define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL |
12339 | //GCVML2_WALKER_MACRO_THROTTLE_TIME |
12340 | #define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT 0x0 |
12341 | #define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL |
12342 | //GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT |
12343 | #define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 |
12344 | #define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL |
12345 | //GCVML2_WALKER_MICRO_THROTTLE_TIME |
12346 | #define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT 0x0 |
12347 | #define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL |
12348 | //GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT |
12349 | #define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 |
12350 | #define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL |
12351 | |
12352 | |
12353 | // addressBlock: gc_gcvml2vcdec |
12354 | //GCVM_CONTEXT0_CNTL |
12355 | #define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12356 | #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12357 | #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12358 | #define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12359 | #define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12360 | #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12361 | #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12362 | #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12363 | #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12364 | #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12365 | #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12366 | #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12367 | #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12368 | #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12369 | #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12370 | #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12371 | #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12372 | #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12373 | #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12374 | #define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12375 | #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12376 | #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12377 | #define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12378 | #define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12379 | #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12380 | #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12381 | #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12382 | #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12383 | #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12384 | #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12385 | #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12386 | #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12387 | #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12388 | #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12389 | #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12390 | #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12391 | #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12392 | #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12393 | //GCVM_CONTEXT1_CNTL |
12394 | #define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12395 | #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12396 | #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12397 | #define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12398 | #define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12399 | #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12400 | #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12401 | #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12402 | #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12403 | #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12404 | #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12405 | #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12406 | #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12407 | #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12408 | #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12409 | #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12410 | #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12411 | #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12412 | #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12413 | #define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12414 | #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12415 | #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12416 | #define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12417 | #define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12418 | #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12419 | #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12420 | #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12421 | #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12422 | #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12423 | #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12424 | #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12425 | #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12426 | #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12427 | #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12428 | #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12429 | #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12430 | #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12431 | #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12432 | //GCVM_CONTEXT2_CNTL |
12433 | #define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12434 | #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12435 | #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12436 | #define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12437 | #define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12438 | #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12439 | #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12440 | #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12441 | #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12442 | #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12443 | #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12444 | #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12445 | #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12446 | #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12447 | #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12448 | #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12449 | #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12450 | #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12451 | #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12452 | #define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12453 | #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12454 | #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12455 | #define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12456 | #define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12457 | #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12458 | #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12459 | #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12460 | #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12461 | #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12462 | #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12463 | #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12464 | #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12465 | #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12466 | #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12467 | #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12468 | #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12469 | #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12470 | #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12471 | //GCVM_CONTEXT3_CNTL |
12472 | #define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12473 | #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12474 | #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12475 | #define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12476 | #define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12477 | #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12478 | #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12479 | #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12480 | #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12481 | #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12482 | #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12483 | #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12484 | #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12485 | #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12486 | #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12487 | #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12488 | #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12489 | #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12490 | #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12491 | #define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12492 | #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12493 | #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12494 | #define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12495 | #define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12496 | #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12497 | #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12498 | #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12499 | #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12500 | #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12501 | #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12502 | #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12503 | #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12504 | #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12505 | #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12506 | #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12507 | #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12508 | #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12509 | #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12510 | //GCVM_CONTEXT4_CNTL |
12511 | #define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12512 | #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12513 | #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12514 | #define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12515 | #define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12516 | #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12517 | #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12518 | #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12519 | #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12520 | #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12521 | #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12522 | #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12523 | #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12524 | #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12525 | #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12526 | #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12527 | #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12528 | #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12529 | #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12530 | #define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12531 | #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12532 | #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12533 | #define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12534 | #define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12535 | #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12536 | #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12537 | #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12538 | #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12539 | #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12540 | #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12541 | #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12542 | #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12543 | #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12544 | #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12545 | #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12546 | #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12547 | #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12548 | #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12549 | //GCVM_CONTEXT5_CNTL |
12550 | #define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12551 | #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12552 | #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12553 | #define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12554 | #define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12555 | #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12556 | #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12557 | #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12558 | #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12559 | #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12560 | #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12561 | #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12562 | #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12563 | #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12564 | #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12565 | #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12566 | #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12567 | #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12568 | #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12569 | #define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12570 | #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12571 | #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12572 | #define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12573 | #define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12574 | #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12575 | #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12576 | #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12577 | #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12578 | #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12579 | #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12580 | #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12581 | #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12582 | #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12583 | #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12584 | #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12585 | #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12586 | #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12587 | #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12588 | //GCVM_CONTEXT6_CNTL |
12589 | #define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12590 | #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12591 | #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12592 | #define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12593 | #define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12594 | #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12595 | #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12596 | #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12597 | #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12598 | #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12599 | #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12600 | #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12601 | #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12602 | #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12603 | #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12604 | #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12605 | #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12606 | #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12607 | #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12608 | #define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12609 | #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12610 | #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12611 | #define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12612 | #define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12613 | #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12614 | #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12615 | #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12616 | #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12617 | #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12618 | #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12619 | #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12620 | #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12621 | #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12622 | #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12623 | #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12624 | #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12625 | #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12626 | #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12627 | //GCVM_CONTEXT7_CNTL |
12628 | #define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12629 | #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12630 | #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12631 | #define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12632 | #define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12633 | #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12634 | #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12635 | #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12636 | #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12637 | #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12638 | #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12639 | #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12640 | #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12641 | #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12642 | #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12643 | #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12644 | #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12645 | #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12646 | #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12647 | #define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12648 | #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12649 | #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12650 | #define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12651 | #define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12652 | #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12653 | #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12654 | #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12655 | #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12656 | #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12657 | #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12658 | #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12659 | #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12660 | #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12661 | #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12662 | #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12663 | #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12664 | #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12665 | #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12666 | //GCVM_CONTEXT8_CNTL |
12667 | #define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12668 | #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12669 | #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12670 | #define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12671 | #define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12672 | #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12673 | #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12674 | #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12675 | #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12676 | #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12677 | #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12678 | #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12679 | #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12680 | #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12681 | #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12682 | #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12683 | #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12684 | #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12685 | #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12686 | #define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12687 | #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12688 | #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12689 | #define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12690 | #define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12691 | #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12692 | #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12693 | #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12694 | #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12695 | #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12696 | #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12697 | #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12698 | #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12699 | #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12700 | #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12701 | #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12702 | #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12703 | #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12704 | #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12705 | //GCVM_CONTEXT9_CNTL |
12706 | #define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12707 | #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12708 | #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12709 | #define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12710 | #define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12711 | #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12712 | #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12713 | #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12714 | #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12715 | #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12716 | #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12717 | #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12718 | #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12719 | #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12720 | #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12721 | #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12722 | #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12723 | #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12724 | #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12725 | #define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12726 | #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12727 | #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12728 | #define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12729 | #define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12730 | #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12731 | #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12732 | #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12733 | #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12734 | #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12735 | #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12736 | #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12737 | #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12738 | #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12739 | #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12740 | #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12741 | #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12742 | #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12743 | #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12744 | //GCVM_CONTEXT10_CNTL |
12745 | #define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12746 | #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12747 | #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12748 | #define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12749 | #define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12750 | #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12751 | #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12752 | #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12753 | #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12754 | #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12755 | #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12756 | #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12757 | #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12758 | #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12759 | #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12760 | #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12761 | #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12762 | #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12763 | #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12764 | #define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12765 | #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12766 | #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12767 | #define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12768 | #define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12769 | #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12770 | #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12771 | #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12772 | #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12773 | #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12774 | #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12775 | #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12776 | #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12777 | #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12778 | #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12779 | #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12780 | #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12781 | #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12782 | #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12783 | //GCVM_CONTEXT11_CNTL |
12784 | #define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12785 | #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12786 | #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12787 | #define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12788 | #define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12789 | #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12790 | #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12791 | #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12792 | #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12793 | #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12794 | #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12795 | #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12796 | #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12797 | #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12798 | #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12799 | #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12800 | #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12801 | #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12802 | #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12803 | #define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12804 | #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12805 | #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12806 | #define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12807 | #define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12808 | #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12809 | #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12810 | #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12811 | #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12812 | #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12813 | #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12814 | #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12815 | #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12816 | #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12817 | #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12818 | #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12819 | #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12820 | #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12821 | #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12822 | //GCVM_CONTEXT12_CNTL |
12823 | #define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12824 | #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12825 | #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12826 | #define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12827 | #define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12828 | #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12829 | #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12830 | #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12831 | #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12832 | #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12833 | #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12834 | #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12835 | #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12836 | #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12837 | #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12838 | #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12839 | #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12840 | #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12841 | #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12842 | #define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12843 | #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12844 | #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12845 | #define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12846 | #define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12847 | #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12848 | #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12849 | #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12850 | #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12851 | #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12852 | #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12853 | #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12854 | #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12855 | #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12856 | #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12857 | #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12858 | #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12859 | #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12860 | #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12861 | //GCVM_CONTEXT13_CNTL |
12862 | #define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12863 | #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12864 | #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12865 | #define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12866 | #define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12867 | #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12868 | #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12869 | #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12870 | #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12871 | #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12872 | #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12873 | #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12874 | #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12875 | #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12876 | #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12877 | #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12878 | #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12879 | #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12880 | #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12881 | #define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12882 | #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12883 | #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12884 | #define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12885 | #define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12886 | #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12887 | #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12888 | #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12889 | #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12890 | #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12891 | #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12892 | #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12893 | #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12894 | #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12895 | #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12896 | #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12897 | #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12898 | #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12899 | #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12900 | //GCVM_CONTEXT14_CNTL |
12901 | #define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12902 | #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12903 | #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12904 | #define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12905 | #define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12906 | #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12907 | #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12908 | #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12909 | #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12910 | #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12911 | #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12912 | #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12913 | #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12914 | #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12915 | #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12916 | #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12917 | #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12918 | #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12919 | #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12920 | #define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12921 | #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12922 | #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12923 | #define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12924 | #define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12925 | #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12926 | #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12927 | #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12928 | #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12929 | #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12930 | #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12931 | #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12932 | #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12933 | #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12934 | #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12935 | #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12936 | #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12937 | #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12938 | #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12939 | //GCVM_CONTEXT15_CNTL |
12940 | #define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12941 | #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12942 | #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12943 | #define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12944 | #define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12945 | #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12946 | #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12947 | #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12948 | #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12949 | #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12950 | #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12951 | #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12952 | #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12953 | #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12954 | #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12955 | #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12956 | #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12957 | #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12958 | #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12959 | #define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12960 | #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12961 | #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12962 | #define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12963 | #define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12964 | #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12965 | #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12966 | #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12967 | #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12968 | #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12969 | #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12970 | #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12971 | #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12972 | #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12973 | #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12974 | #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12975 | #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12976 | #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12977 | #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12978 | //GCVM_CONTEXTS_DISABLE |
12979 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 |
12980 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 |
12981 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 |
12982 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 |
12983 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 |
12984 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 |
12985 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 |
12986 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 |
12987 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 |
12988 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 |
12989 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa |
12990 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb |
12991 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc |
12992 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd |
12993 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe |
12994 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf |
12995 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L |
12996 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L |
12997 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L |
12998 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L |
12999 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L |
13000 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L |
13001 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L |
13002 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L |
13003 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L |
13004 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L |
13005 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L |
13006 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L |
13007 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L |
13008 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L |
13009 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L |
13010 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L |
13011 | //GCVM_INVALIDATE_ENG0_SEM |
13012 | #define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 |
13013 | #define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L |
13014 | //GCVM_INVALIDATE_ENG1_SEM |
13015 | #define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 |
13016 | #define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L |
13017 | //GCVM_INVALIDATE_ENG2_SEM |
13018 | #define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 |
13019 | #define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L |
13020 | //GCVM_INVALIDATE_ENG3_SEM |
13021 | #define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 |
13022 | #define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L |
13023 | //GCVM_INVALIDATE_ENG4_SEM |
13024 | #define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 |
13025 | #define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L |
13026 | //GCVM_INVALIDATE_ENG5_SEM |
13027 | #define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 |
13028 | #define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L |
13029 | //GCVM_INVALIDATE_ENG6_SEM |
13030 | #define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 |
13031 | #define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L |
13032 | //GCVM_INVALIDATE_ENG7_SEM |
13033 | #define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 |
13034 | #define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L |
13035 | //GCVM_INVALIDATE_ENG8_SEM |
13036 | #define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 |
13037 | #define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L |
13038 | //GCVM_INVALIDATE_ENG9_SEM |
13039 | #define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 |
13040 | #define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L |
13041 | //GCVM_INVALIDATE_ENG10_SEM |
13042 | #define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 |
13043 | #define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L |
13044 | //GCVM_INVALIDATE_ENG11_SEM |
13045 | #define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 |
13046 | #define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L |
13047 | //GCVM_INVALIDATE_ENG12_SEM |
13048 | #define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 |
13049 | #define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L |
13050 | //GCVM_INVALIDATE_ENG13_SEM |
13051 | #define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 |
13052 | #define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L |
13053 | //GCVM_INVALIDATE_ENG14_SEM |
13054 | #define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 |
13055 | #define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L |
13056 | //GCVM_INVALIDATE_ENG15_SEM |
13057 | #define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 |
13058 | #define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L |
13059 | //GCVM_INVALIDATE_ENG16_SEM |
13060 | #define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 |
13061 | #define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L |
13062 | //GCVM_INVALIDATE_ENG17_SEM |
13063 | #define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 |
13064 | #define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L |
13065 | //GCVM_INVALIDATE_ENG0_REQ |
13066 | #define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13067 | #define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 |
13068 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13069 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13070 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13071 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13072 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13073 | #define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13074 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13075 | #define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13076 | #define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L |
13077 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13078 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13079 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13080 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13081 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13082 | #define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13083 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13084 | //GCVM_INVALIDATE_ENG1_REQ |
13085 | #define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13086 | #define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 |
13087 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13088 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13089 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13090 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13091 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13092 | #define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13093 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13094 | #define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13095 | #define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L |
13096 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13097 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13098 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13099 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13100 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13101 | #define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13102 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13103 | //GCVM_INVALIDATE_ENG2_REQ |
13104 | #define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13105 | #define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 |
13106 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13107 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13108 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13109 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13110 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13111 | #define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13112 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13113 | #define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13114 | #define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L |
13115 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13116 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13117 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13118 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13119 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13120 | #define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13121 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13122 | //GCVM_INVALIDATE_ENG3_REQ |
13123 | #define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13124 | #define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 |
13125 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13126 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13127 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13128 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13129 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13130 | #define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13131 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13132 | #define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13133 | #define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L |
13134 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13135 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13136 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13137 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13138 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13139 | #define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13140 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13141 | //GCVM_INVALIDATE_ENG4_REQ |
13142 | #define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13143 | #define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 |
13144 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13145 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13146 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13147 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13148 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13149 | #define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13150 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13151 | #define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13152 | #define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L |
13153 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13154 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13155 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13156 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13157 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13158 | #define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13159 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13160 | //GCVM_INVALIDATE_ENG5_REQ |
13161 | #define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13162 | #define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 |
13163 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13164 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13165 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13166 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13167 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13168 | #define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13169 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13170 | #define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13171 | #define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L |
13172 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13173 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13174 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13175 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13176 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13177 | #define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13178 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13179 | //GCVM_INVALIDATE_ENG6_REQ |
13180 | #define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13181 | #define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 |
13182 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13183 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13184 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13185 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13186 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13187 | #define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13188 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13189 | #define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13190 | #define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L |
13191 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13192 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13193 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13194 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13195 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13196 | #define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13197 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13198 | //GCVM_INVALIDATE_ENG7_REQ |
13199 | #define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13200 | #define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 |
13201 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13202 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13203 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13204 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13205 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13206 | #define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13207 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13208 | #define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13209 | #define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L |
13210 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13211 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13212 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13213 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13214 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13215 | #define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13216 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13217 | //GCVM_INVALIDATE_ENG8_REQ |
13218 | #define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13219 | #define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 |
13220 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13221 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13222 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13223 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13224 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13225 | #define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13226 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13227 | #define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13228 | #define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L |
13229 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13230 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13231 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13232 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13233 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13234 | #define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13235 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13236 | //GCVM_INVALIDATE_ENG9_REQ |
13237 | #define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13238 | #define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 |
13239 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13240 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13241 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13242 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13243 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13244 | #define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13245 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13246 | #define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13247 | #define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L |
13248 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13249 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13250 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13251 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13252 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13253 | #define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13254 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13255 | //GCVM_INVALIDATE_ENG10_REQ |
13256 | #define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13257 | #define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 |
13258 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13259 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13260 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13261 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13262 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13263 | #define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13264 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13265 | #define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13266 | #define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L |
13267 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13268 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13269 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13270 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13271 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13272 | #define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13273 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13274 | //GCVM_INVALIDATE_ENG11_REQ |
13275 | #define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13276 | #define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 |
13277 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13278 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13279 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13280 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13281 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13282 | #define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13283 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13284 | #define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13285 | #define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L |
13286 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13287 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13288 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13289 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13290 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13291 | #define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13292 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13293 | //GCVM_INVALIDATE_ENG12_REQ |
13294 | #define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13295 | #define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 |
13296 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13297 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13298 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13299 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13300 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13301 | #define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13302 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13303 | #define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13304 | #define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L |
13305 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13306 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13307 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13308 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13309 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13310 | #define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13311 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13312 | //GCVM_INVALIDATE_ENG13_REQ |
13313 | #define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13314 | #define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 |
13315 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13316 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13317 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13318 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13319 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13320 | #define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13321 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13322 | #define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13323 | #define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L |
13324 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13325 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13326 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13327 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13328 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13329 | #define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13330 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13331 | //GCVM_INVALIDATE_ENG14_REQ |
13332 | #define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13333 | #define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 |
13334 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13335 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13336 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13337 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13338 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13339 | #define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13340 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13341 | #define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13342 | #define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L |
13343 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13344 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13345 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13346 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13347 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13348 | #define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13349 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13350 | //GCVM_INVALIDATE_ENG15_REQ |
13351 | #define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13352 | #define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 |
13353 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13354 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13355 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13356 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13357 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13358 | #define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13359 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13360 | #define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13361 | #define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L |
13362 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13363 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13364 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13365 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13366 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13367 | #define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13368 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13369 | //GCVM_INVALIDATE_ENG16_REQ |
13370 | #define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13371 | #define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 |
13372 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13373 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13374 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13375 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13376 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13377 | #define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13378 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13379 | #define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13380 | #define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L |
13381 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13382 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13383 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13384 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13385 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13386 | #define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13387 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13388 | //GCVM_INVALIDATE_ENG17_REQ |
13389 | #define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
13390 | #define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 |
13391 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
13392 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
13393 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
13394 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
13395 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
13396 | #define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
13397 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
13398 | #define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
13399 | #define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L |
13400 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
13401 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
13402 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
13403 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
13404 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
13405 | #define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
13406 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
13407 | //GCVM_INVALIDATE_ENG0_ACK |
13408 | #define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13409 | #define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 |
13410 | #define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13411 | #define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L |
13412 | //GCVM_INVALIDATE_ENG1_ACK |
13413 | #define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13414 | #define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 |
13415 | #define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13416 | #define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L |
13417 | //GCVM_INVALIDATE_ENG2_ACK |
13418 | #define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13419 | #define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 |
13420 | #define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13421 | #define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L |
13422 | //GCVM_INVALIDATE_ENG3_ACK |
13423 | #define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13424 | #define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 |
13425 | #define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13426 | #define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L |
13427 | //GCVM_INVALIDATE_ENG4_ACK |
13428 | #define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13429 | #define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 |
13430 | #define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13431 | #define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L |
13432 | //GCVM_INVALIDATE_ENG5_ACK |
13433 | #define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13434 | #define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 |
13435 | #define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13436 | #define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L |
13437 | //GCVM_INVALIDATE_ENG6_ACK |
13438 | #define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13439 | #define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 |
13440 | #define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13441 | #define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L |
13442 | //GCVM_INVALIDATE_ENG7_ACK |
13443 | #define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13444 | #define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 |
13445 | #define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13446 | #define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L |
13447 | //GCVM_INVALIDATE_ENG8_ACK |
13448 | #define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13449 | #define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 |
13450 | #define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13451 | #define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L |
13452 | //GCVM_INVALIDATE_ENG9_ACK |
13453 | #define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13454 | #define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 |
13455 | #define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13456 | #define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L |
13457 | //GCVM_INVALIDATE_ENG10_ACK |
13458 | #define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13459 | #define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 |
13460 | #define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13461 | #define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L |
13462 | //GCVM_INVALIDATE_ENG11_ACK |
13463 | #define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13464 | #define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 |
13465 | #define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13466 | #define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L |
13467 | //GCVM_INVALIDATE_ENG12_ACK |
13468 | #define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13469 | #define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 |
13470 | #define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13471 | #define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L |
13472 | //GCVM_INVALIDATE_ENG13_ACK |
13473 | #define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13474 | #define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 |
13475 | #define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13476 | #define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L |
13477 | //GCVM_INVALIDATE_ENG14_ACK |
13478 | #define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13479 | #define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 |
13480 | #define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13481 | #define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L |
13482 | //GCVM_INVALIDATE_ENG15_ACK |
13483 | #define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13484 | #define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 |
13485 | #define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13486 | #define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L |
13487 | //GCVM_INVALIDATE_ENG16_ACK |
13488 | #define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13489 | #define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 |
13490 | #define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13491 | #define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L |
13492 | //GCVM_INVALIDATE_ENG17_ACK |
13493 | #define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
13494 | #define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 |
13495 | #define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
13496 | #define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L |
13497 | //GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 |
13498 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13499 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13500 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13501 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13502 | //GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 |
13503 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13504 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13505 | //GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 |
13506 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13507 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13508 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13509 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13510 | //GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 |
13511 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13512 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13513 | //GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 |
13514 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13515 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13516 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13517 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13518 | //GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 |
13519 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13520 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13521 | //GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 |
13522 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13523 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13524 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13525 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13526 | //GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 |
13527 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13528 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13529 | //GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 |
13530 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13531 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13532 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13533 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13534 | //GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 |
13535 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13536 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13537 | //GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 |
13538 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13539 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13540 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13541 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13542 | //GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 |
13543 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13544 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13545 | //GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 |
13546 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13547 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13548 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13549 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13550 | //GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 |
13551 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13552 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13553 | //GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 |
13554 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13555 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13556 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13557 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13558 | //GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 |
13559 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13560 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13561 | //GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 |
13562 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13563 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13564 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13565 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13566 | //GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 |
13567 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13568 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13569 | //GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 |
13570 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13571 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13572 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13573 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13574 | //GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 |
13575 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13576 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13577 | //GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 |
13578 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13579 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13580 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13581 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13582 | //GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 |
13583 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13584 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13585 | //GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 |
13586 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13587 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13588 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13589 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13590 | //GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 |
13591 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13592 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13593 | //GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 |
13594 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13595 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13596 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13597 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13598 | //GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 |
13599 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13600 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13601 | //GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 |
13602 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13603 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13604 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13605 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13606 | //GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 |
13607 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13608 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13609 | //GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 |
13610 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13611 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13612 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13613 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13614 | //GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 |
13615 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13616 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13617 | //GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 |
13618 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13619 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13620 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13621 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13622 | //GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 |
13623 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13624 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13625 | //GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 |
13626 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13627 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13628 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13629 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13630 | //GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 |
13631 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13632 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13633 | //GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 |
13634 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13635 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13636 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13637 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13638 | //GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 |
13639 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13640 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13641 | //GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 |
13642 | #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13643 | #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13644 | //GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 |
13645 | #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13646 | #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13647 | //GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 |
13648 | #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13649 | #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13650 | //GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 |
13651 | #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13652 | #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13653 | //GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 |
13654 | #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13655 | #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13656 | //GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 |
13657 | #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13658 | #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13659 | //GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 |
13660 | #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13661 | #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13662 | //GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 |
13663 | #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13664 | #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13665 | //GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 |
13666 | #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13667 | #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13668 | //GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 |
13669 | #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13670 | #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13671 | //GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 |
13672 | #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13673 | #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13674 | //GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 |
13675 | #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13676 | #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13677 | //GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 |
13678 | #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13679 | #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13680 | //GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 |
13681 | #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13682 | #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13683 | //GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 |
13684 | #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13685 | #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13686 | //GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 |
13687 | #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13688 | #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13689 | //GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 |
13690 | #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13691 | #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13692 | //GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 |
13693 | #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13694 | #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13695 | //GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 |
13696 | #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13697 | #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13698 | //GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 |
13699 | #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13700 | #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13701 | //GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 |
13702 | #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13703 | #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13704 | //GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 |
13705 | #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13706 | #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13707 | //GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 |
13708 | #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13709 | #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13710 | //GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 |
13711 | #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13712 | #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13713 | //GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 |
13714 | #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13715 | #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13716 | //GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 |
13717 | #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13718 | #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13719 | //GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 |
13720 | #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13721 | #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13722 | //GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 |
13723 | #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13724 | #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13725 | //GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 |
13726 | #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13727 | #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13728 | //GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 |
13729 | #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13730 | #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13731 | //GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 |
13732 | #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13733 | #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13734 | //GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 |
13735 | #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13736 | #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13737 | //GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 |
13738 | #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13739 | #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13740 | //GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 |
13741 | #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13742 | #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13743 | //GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 |
13744 | #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13745 | #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13746 | //GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 |
13747 | #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13748 | #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13749 | //GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 |
13750 | #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13751 | #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13752 | //GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 |
13753 | #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13754 | #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13755 | //GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 |
13756 | #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13757 | #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13758 | //GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 |
13759 | #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13760 | #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13761 | //GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 |
13762 | #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13763 | #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13764 | //GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 |
13765 | #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13766 | #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13767 | //GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 |
13768 | #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13769 | #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13770 | //GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 |
13771 | #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13772 | #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13773 | //GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 |
13774 | #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13775 | #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13776 | //GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 |
13777 | #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13778 | #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13779 | //GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 |
13780 | #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13781 | #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13782 | //GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 |
13783 | #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13784 | #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13785 | //GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 |
13786 | #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13787 | #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13788 | //GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 |
13789 | #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13790 | #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13791 | //GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 |
13792 | #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13793 | #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13794 | //GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 |
13795 | #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13796 | #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13797 | //GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 |
13798 | #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13799 | #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13800 | //GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 |
13801 | #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13802 | #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13803 | //GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 |
13804 | #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13805 | #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13806 | //GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 |
13807 | #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13808 | #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13809 | //GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 |
13810 | #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13811 | #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13812 | //GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 |
13813 | #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13814 | #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13815 | //GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 |
13816 | #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13817 | #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13818 | //GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 |
13819 | #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13820 | #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13821 | //GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 |
13822 | #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13823 | #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13824 | //GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 |
13825 | #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13826 | #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13827 | //GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 |
13828 | #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13829 | #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13830 | //GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 |
13831 | #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13832 | #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13833 | //GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 |
13834 | #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13835 | #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13836 | //GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 |
13837 | #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13838 | #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13839 | //GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 |
13840 | #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13841 | #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13842 | //GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 |
13843 | #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13844 | #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13845 | //GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 |
13846 | #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13847 | #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13848 | //GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 |
13849 | #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13850 | #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13851 | //GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 |
13852 | #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13853 | #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13854 | //GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 |
13855 | #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13856 | #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13857 | //GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 |
13858 | #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13859 | #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13860 | //GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 |
13861 | #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13862 | #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13863 | //GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 |
13864 | #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13865 | #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13866 | //GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 |
13867 | #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13868 | #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13869 | //GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 |
13870 | #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13871 | #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13872 | //GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 |
13873 | #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13874 | #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13875 | //GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 |
13876 | #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13877 | #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13878 | //GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 |
13879 | #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13880 | #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13881 | //GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 |
13882 | #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13883 | #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13884 | //GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 |
13885 | #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13886 | #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13887 | //GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 |
13888 | #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13889 | #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13890 | //GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 |
13891 | #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13892 | #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13893 | //GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 |
13894 | #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13895 | #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13896 | //GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 |
13897 | #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13898 | #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13899 | //GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 |
13900 | #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13901 | #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13902 | //GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 |
13903 | #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13904 | #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13905 | //GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 |
13906 | #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13907 | #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13908 | //GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 |
13909 | #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13910 | #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13911 | //GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 |
13912 | #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13913 | #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13914 | //GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 |
13915 | #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13916 | #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13917 | //GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 |
13918 | #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13919 | #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13920 | //GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 |
13921 | #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13922 | #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13923 | //GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 |
13924 | #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13925 | #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13926 | //GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 |
13927 | #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13928 | #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13929 | |
13930 | |
13931 | // addressBlock: gc_gcvmsharedpfdec |
13932 | //GCMC_VM_NB_MMIOBASE |
13933 | #define GCMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 |
13934 | #define GCMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL |
13935 | //GCMC_VM_NB_MMIOLIMIT |
13936 | #define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 |
13937 | #define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL |
13938 | //GCMC_VM_NB_PCI_CTRL |
13939 | #define GCMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 |
13940 | #define GCMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L |
13941 | //GCMC_VM_NB_PCI_ARB |
13942 | #define GCMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 |
13943 | #define GCMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L |
13944 | //GCMC_VM_NB_TOP_OF_DRAM_SLOT1 |
13945 | #define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 |
13946 | #define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L |
13947 | //GCMC_VM_NB_LOWER_TOP_OF_DRAM2 |
13948 | #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 |
13949 | #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 |
13950 | #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L |
13951 | #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L |
13952 | //GCMC_VM_NB_UPPER_TOP_OF_DRAM2 |
13953 | #define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 |
13954 | #define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL |
13955 | //GCMC_VM_FB_OFFSET |
13956 | #define GCMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 |
13957 | #define GCMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL |
13958 | //GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB |
13959 | #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 |
13960 | #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL |
13961 | //GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB |
13962 | #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 |
13963 | #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL |
13964 | //GCMC_VM_STEERING |
13965 | #define GCMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 |
13966 | #define GCMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L |
13967 | //GCMC_SHARED_VIRT_RESET_REQ |
13968 | #define GCMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 |
13969 | #define GCMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f |
13970 | #define GCMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL |
13971 | #define GCMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L |
13972 | //GCMC_MEM_POWER_LS |
13973 | #define GCMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 |
13974 | #define GCMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 |
13975 | #define GCMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL |
13976 | #define GCMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L |
13977 | //GCMC_VM_CACHEABLE_DRAM_ADDRESS_START |
13978 | #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 |
13979 | #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL |
13980 | //GCMC_VM_CACHEABLE_DRAM_ADDRESS_END |
13981 | #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 |
13982 | #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL |
13983 | //GCMC_VM_APT_CNTL |
13984 | #define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 |
13985 | #define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 |
13986 | #define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L |
13987 | #define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L |
13988 | //GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL |
13989 | #define GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 |
13990 | #define GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L |
13991 | //GCMC_VM_LOCAL_HBM_ADDRESS_START |
13992 | #define GCMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 |
13993 | #define GCMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL |
13994 | //GCMC_VM_LOCAL_HBM_ADDRESS_END |
13995 | #define GCMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 |
13996 | #define GCMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL |
13997 | //GCMC_SHARED_VIRT_RESET_REQ2 |
13998 | #define GCMC_SHARED_VIRT_RESET_REQ2__VF__SHIFT 0x0 |
13999 | #define GCMC_SHARED_VIRT_RESET_REQ2__VF_MASK 0x00000001L |
14000 | |
14001 | |
14002 | // addressBlock: gc_gcvmsharedvcdec |
14003 | //GCMC_VM_FB_LOCATION_BASE |
14004 | #define GCMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 |
14005 | #define GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL |
14006 | //GCMC_VM_FB_LOCATION_TOP |
14007 | #define GCMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 |
14008 | #define GCMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL |
14009 | //GCMC_VM_AGP_TOP |
14010 | #define GCMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 |
14011 | #define GCMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL |
14012 | //GCMC_VM_AGP_BOT |
14013 | #define GCMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 |
14014 | #define GCMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL |
14015 | //GCMC_VM_AGP_BASE |
14016 | #define GCMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 |
14017 | #define GCMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL |
14018 | //GCMC_VM_SYSTEM_APERTURE_LOW_ADDR |
14019 | #define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 |
14020 | #define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL |
14021 | //GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR |
14022 | #define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 |
14023 | #define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL |
14024 | //GCMC_VM_MX_L1_TLB_CNTL |
14025 | #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 |
14026 | #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 |
14027 | #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 |
14028 | #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 |
14029 | #define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 |
14030 | #define GCMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb |
14031 | #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L |
14032 | #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L |
14033 | #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L |
14034 | #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L |
14035 | #define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L |
14036 | #define GCMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L |
14037 | |
14038 | |
14039 | // addressBlock: gc_gceadec |
14040 | //GCEA_DRAM_RD_CLI2GRP_MAP0 |
14041 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
14042 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
14043 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
14044 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
14045 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
14046 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
14047 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
14048 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
14049 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
14050 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
14051 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
14052 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
14053 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
14054 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
14055 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
14056 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
14057 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
14058 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
14059 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
14060 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
14061 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
14062 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
14063 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
14064 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
14065 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
14066 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
14067 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
14068 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
14069 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
14070 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
14071 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
14072 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
14073 | //GCEA_DRAM_RD_CLI2GRP_MAP1 |
14074 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
14075 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
14076 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
14077 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
14078 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
14079 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
14080 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
14081 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
14082 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
14083 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
14084 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
14085 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
14086 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
14087 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
14088 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
14089 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
14090 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
14091 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
14092 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
14093 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
14094 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
14095 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
14096 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
14097 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
14098 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
14099 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
14100 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
14101 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
14102 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
14103 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
14104 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
14105 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
14106 | //GCEA_DRAM_WR_CLI2GRP_MAP0 |
14107 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
14108 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
14109 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
14110 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
14111 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
14112 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
14113 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
14114 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
14115 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
14116 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
14117 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
14118 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
14119 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
14120 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
14121 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
14122 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
14123 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
14124 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
14125 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
14126 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
14127 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
14128 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
14129 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
14130 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
14131 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
14132 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
14133 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
14134 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
14135 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
14136 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
14137 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
14138 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
14139 | //GCEA_DRAM_WR_CLI2GRP_MAP1 |
14140 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
14141 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
14142 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
14143 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
14144 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
14145 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
14146 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
14147 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
14148 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
14149 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
14150 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
14151 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
14152 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
14153 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
14154 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
14155 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
14156 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
14157 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
14158 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
14159 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
14160 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
14161 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
14162 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
14163 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
14164 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
14165 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
14166 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
14167 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
14168 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
14169 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
14170 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
14171 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
14172 | //GCEA_DRAM_RD_GRP2VC_MAP |
14173 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
14174 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
14175 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
14176 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
14177 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
14178 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
14179 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
14180 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
14181 | //GCEA_DRAM_WR_GRP2VC_MAP |
14182 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
14183 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
14184 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
14185 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
14186 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
14187 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
14188 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
14189 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
14190 | //GCEA_DRAM_RD_LAZY |
14191 | #define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
14192 | #define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
14193 | #define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
14194 | #define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
14195 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
14196 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
14197 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
14198 | #define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
14199 | #define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
14200 | #define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
14201 | #define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
14202 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
14203 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
14204 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
14205 | //GCEA_DRAM_WR_LAZY |
14206 | #define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
14207 | #define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
14208 | #define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
14209 | #define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
14210 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
14211 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
14212 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
14213 | #define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
14214 | #define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
14215 | #define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
14216 | #define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
14217 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
14218 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
14219 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
14220 | //GCEA_DRAM_RD_CAM_CNTL |
14221 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
14222 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
14223 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
14224 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
14225 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
14226 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
14227 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
14228 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
14229 | #define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
14230 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
14231 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
14232 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
14233 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
14234 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
14235 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
14236 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
14237 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
14238 | #define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
14239 | //GCEA_DRAM_WR_CAM_CNTL |
14240 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
14241 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
14242 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
14243 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
14244 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
14245 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
14246 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
14247 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
14248 | #define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
14249 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
14250 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
14251 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
14252 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
14253 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
14254 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
14255 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
14256 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
14257 | #define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
14258 | //GCEA_DRAM_PAGE_BURST |
14259 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
14260 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
14261 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
14262 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
14263 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
14264 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
14265 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
14266 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
14267 | //GCEA_DRAM_RD_PRI_AGE |
14268 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
14269 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
14270 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
14271 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
14272 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
14273 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
14274 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
14275 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
14276 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
14277 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
14278 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
14279 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
14280 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
14281 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
14282 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
14283 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
14284 | //GCEA_DRAM_WR_PRI_AGE |
14285 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
14286 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
14287 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
14288 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
14289 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
14290 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
14291 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
14292 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
14293 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
14294 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
14295 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
14296 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
14297 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
14298 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
14299 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
14300 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
14301 | //GCEA_DRAM_RD_PRI_QUEUING |
14302 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
14303 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
14304 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
14305 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
14306 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
14307 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
14308 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
14309 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
14310 | //GCEA_DRAM_WR_PRI_QUEUING |
14311 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
14312 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
14313 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
14314 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
14315 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
14316 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
14317 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
14318 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
14319 | //GCEA_DRAM_RD_PRI_FIXED |
14320 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
14321 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
14322 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
14323 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
14324 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
14325 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
14326 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
14327 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
14328 | //GCEA_DRAM_WR_PRI_FIXED |
14329 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
14330 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
14331 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
14332 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
14333 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
14334 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
14335 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
14336 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
14337 | //GCEA_DRAM_RD_PRI_URGENCY |
14338 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
14339 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
14340 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
14341 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
14342 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
14343 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
14344 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
14345 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
14346 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
14347 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
14348 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
14349 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
14350 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
14351 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
14352 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
14353 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
14354 | //GCEA_DRAM_WR_PRI_URGENCY |
14355 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
14356 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
14357 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
14358 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
14359 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
14360 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
14361 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
14362 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
14363 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
14364 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
14365 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
14366 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
14367 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
14368 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
14369 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
14370 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
14371 | //GCEA_DRAM_RD_PRI_QUANT_PRI1 |
14372 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
14373 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
14374 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
14375 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
14376 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
14377 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14378 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14379 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
14380 | //GCEA_DRAM_RD_PRI_QUANT_PRI2 |
14381 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
14382 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
14383 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
14384 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
14385 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
14386 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14387 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14388 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
14389 | //GCEA_DRAM_RD_PRI_QUANT_PRI3 |
14390 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
14391 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
14392 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
14393 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
14394 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
14395 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14396 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14397 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
14398 | //GCEA_DRAM_WR_PRI_QUANT_PRI1 |
14399 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
14400 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
14401 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
14402 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
14403 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
14404 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14405 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14406 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
14407 | //GCEA_DRAM_WR_PRI_QUANT_PRI2 |
14408 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
14409 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
14410 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
14411 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
14412 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
14413 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14414 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14415 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
14416 | //GCEA_DRAM_WR_PRI_QUANT_PRI3 |
14417 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
14418 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
14419 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
14420 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
14421 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
14422 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14423 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14424 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
14425 | //GCEA_ADDRNORM_BASE_ADDR0 |
14426 | #define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 |
14427 | #define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 |
14428 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 |
14429 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x6 |
14430 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 |
14431 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 |
14432 | #define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc |
14433 | #define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L |
14434 | #define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L |
14435 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000003CL |
14436 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x000000C0L |
14437 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L |
14438 | #define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L |
14439 | #define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L |
14440 | //GCEA_ADDRNORM_LIMIT_ADDR0 |
14441 | #define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 |
14442 | #define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc |
14443 | #define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL |
14444 | #define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L |
14445 | //GCEA_ADDRNORM_BASE_ADDR1 |
14446 | #define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 |
14447 | #define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 |
14448 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 |
14449 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x6 |
14450 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 |
14451 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 |
14452 | #define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc |
14453 | #define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L |
14454 | #define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L |
14455 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000003CL |
14456 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x000000C0L |
14457 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L |
14458 | #define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L |
14459 | #define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L |
14460 | //GCEA_ADDRNORM_LIMIT_ADDR1 |
14461 | #define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 |
14462 | #define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc |
14463 | #define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL |
14464 | #define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L |
14465 | //GCEA_ADDRNORM_OFFSET_ADDR1 |
14466 | #define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 |
14467 | #define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 |
14468 | #define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L |
14469 | #define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L |
14470 | //GCEA_ADDRNORMDRAM_HOLE_CNTL |
14471 | #define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 |
14472 | #define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 |
14473 | #define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L |
14474 | #define GCEA_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L |
14475 | //GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG |
14476 | #define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 |
14477 | #define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 |
14478 | #define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL |
14479 | #define GCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L |
14480 | //GCEA_ADDRDEC_BANK_CFG |
14481 | #define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 |
14482 | #define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 |
14483 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa |
14484 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd |
14485 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 |
14486 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 |
14487 | #define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL |
14488 | #define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L |
14489 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L |
14490 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L |
14491 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L |
14492 | #define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L |
14493 | //GCEA_ADDRDEC_MISC_CFG |
14494 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 |
14495 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 |
14496 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 |
14497 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 |
14498 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 |
14499 | #define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 |
14500 | #define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 |
14501 | #define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc |
14502 | #define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 |
14503 | #define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 |
14504 | #define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 |
14505 | #define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a |
14506 | #define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d |
14507 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L |
14508 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L |
14509 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L |
14510 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L |
14511 | #define GCEA_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L |
14512 | #define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L |
14513 | #define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L |
14514 | #define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L |
14515 | #define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L |
14516 | #define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L |
14517 | #define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L |
14518 | #define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L |
14519 | #define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L |
14520 | //GCEA_ADDRDECDRAM_ADDR_HASH_BANK0 |
14521 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 |
14522 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 |
14523 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe |
14524 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L |
14525 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL |
14526 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L |
14527 | //GCEA_ADDRDECDRAM_ADDR_HASH_BANK1 |
14528 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 |
14529 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 |
14530 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe |
14531 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L |
14532 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL |
14533 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L |
14534 | //GCEA_ADDRDECDRAM_ADDR_HASH_BANK2 |
14535 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 |
14536 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 |
14537 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe |
14538 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L |
14539 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL |
14540 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L |
14541 | //GCEA_ADDRDECDRAM_ADDR_HASH_BANK3 |
14542 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 |
14543 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 |
14544 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe |
14545 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L |
14546 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL |
14547 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L |
14548 | //GCEA_ADDRDECDRAM_ADDR_HASH_BANK4 |
14549 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 |
14550 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 |
14551 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe |
14552 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L |
14553 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL |
14554 | #define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L |
14555 | //GCEA_ADDRDECDRAM_ADDR_HASH_PC |
14556 | #define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 |
14557 | #define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 |
14558 | #define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe |
14559 | #define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L |
14560 | #define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL |
14561 | #define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L |
14562 | //GCEA_ADDRDECDRAM_ADDR_HASH_PC2 |
14563 | #define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 |
14564 | #define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL |
14565 | //GCEA_ADDRDECDRAM_ADDR_HASH_CS0 |
14566 | #define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 |
14567 | #define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 |
14568 | #define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L |
14569 | #define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL |
14570 | //GCEA_ADDRDECDRAM_ADDR_HASH_CS1 |
14571 | #define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 |
14572 | #define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 |
14573 | #define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L |
14574 | #define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL |
14575 | //GCEA_ADDRDECDRAM_HARVEST_ENABLE |
14576 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 |
14577 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 |
14578 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 |
14579 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 |
14580 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L |
14581 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L |
14582 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L |
14583 | #define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L |
14584 | //GCEA_ADDRDECDRAM_HARVNA_ADDR_START0 |
14585 | #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__START__SHIFT 0x0 |
14586 | #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR__SHIFT 0x1c |
14587 | #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__START_MASK 0x000FFFFFL |
14588 | #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START0__BANK_XOR_MASK 0xF0000000L |
14589 | //GCEA_ADDRDECDRAM_HARVNA_ADDR_END0 |
14590 | #define GCEA_ADDRDECDRAM_HARVNA_ADDR_END0__END__SHIFT 0x0 |
14591 | #define GCEA_ADDRDECDRAM_HARVNA_ADDR_END0__END_MASK 0x000FFFFFL |
14592 | //GCEA_ADDRDECDRAM_HARVNA_ADDR_START1 |
14593 | #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__START__SHIFT 0x0 |
14594 | #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR__SHIFT 0x1c |
14595 | #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__START_MASK 0x000FFFFFL |
14596 | #define GCEA_ADDRDECDRAM_HARVNA_ADDR_START1__BANK_XOR_MASK 0xF0000000L |
14597 | //GCEA_ADDRDECDRAM_HARVNA_ADDR_END1 |
14598 | #define GCEA_ADDRDECDRAM_HARVNA_ADDR_END1__END__SHIFT 0x0 |
14599 | #define GCEA_ADDRDECDRAM_HARVNA_ADDR_END1__END_MASK 0x000FFFFFL |
14600 | //GCEA_ADDRDEC0_BASE_ADDR_CS0 |
14601 | #define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 |
14602 | #define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 |
14603 | #define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L |
14604 | #define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL |
14605 | //GCEA_ADDRDEC0_BASE_ADDR_CS1 |
14606 | #define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 |
14607 | #define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 |
14608 | #define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L |
14609 | #define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL |
14610 | //GCEA_ADDRDEC0_BASE_ADDR_CS2 |
14611 | #define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 |
14612 | #define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 |
14613 | #define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L |
14614 | #define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL |
14615 | //GCEA_ADDRDEC0_BASE_ADDR_CS3 |
14616 | #define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 |
14617 | #define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 |
14618 | #define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L |
14619 | #define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL |
14620 | //GCEA_ADDRDEC0_BASE_ADDR_SECCS0 |
14621 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 |
14622 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 |
14623 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L |
14624 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL |
14625 | //GCEA_ADDRDEC0_BASE_ADDR_SECCS1 |
14626 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 |
14627 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 |
14628 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L |
14629 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL |
14630 | //GCEA_ADDRDEC0_BASE_ADDR_SECCS2 |
14631 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 |
14632 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 |
14633 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L |
14634 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL |
14635 | //GCEA_ADDRDEC0_BASE_ADDR_SECCS3 |
14636 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 |
14637 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 |
14638 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L |
14639 | #define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL |
14640 | //GCEA_ADDRDEC0_ADDR_MASK_CS01 |
14641 | #define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 |
14642 | #define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL |
14643 | //GCEA_ADDRDEC0_ADDR_MASK_CS23 |
14644 | #define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 |
14645 | #define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL |
14646 | //GCEA_ADDRDEC0_ADDR_MASK_SECCS01 |
14647 | #define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 |
14648 | #define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL |
14649 | //GCEA_ADDRDEC0_ADDR_MASK_SECCS23 |
14650 | #define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 |
14651 | #define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL |
14652 | //GCEA_ADDRDEC0_ADDR_CFG_CS01 |
14653 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 |
14654 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 |
14655 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 |
14656 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc |
14657 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 |
14658 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 |
14659 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f |
14660 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL |
14661 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L |
14662 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L |
14663 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L |
14664 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L |
14665 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L |
14666 | #define GCEA_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L |
14667 | //GCEA_ADDRDEC0_ADDR_CFG_CS23 |
14668 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 |
14669 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 |
14670 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 |
14671 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc |
14672 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 |
14673 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 |
14674 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f |
14675 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL |
14676 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L |
14677 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L |
14678 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L |
14679 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L |
14680 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L |
14681 | #define GCEA_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L |
14682 | //GCEA_ADDRDEC0_ADDR_SEL_CS01 |
14683 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 |
14684 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 |
14685 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 |
14686 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc |
14687 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 |
14688 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 |
14689 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c |
14690 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL |
14691 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L |
14692 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L |
14693 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L |
14694 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L |
14695 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L |
14696 | #define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L |
14697 | //GCEA_ADDRDEC0_ADDR_SEL_CS23 |
14698 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 |
14699 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 |
14700 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 |
14701 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc |
14702 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 |
14703 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 |
14704 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c |
14705 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL |
14706 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L |
14707 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L |
14708 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L |
14709 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L |
14710 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L |
14711 | #define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L |
14712 | //GCEA_ADDRDEC0_COL_SEL_LO_CS01 |
14713 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 |
14714 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 |
14715 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 |
14716 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc |
14717 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 |
14718 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 |
14719 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 |
14720 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c |
14721 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL |
14722 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L |
14723 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L |
14724 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L |
14725 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L |
14726 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L |
14727 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L |
14728 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L |
14729 | //GCEA_ADDRDEC0_COL_SEL_LO_CS23 |
14730 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 |
14731 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 |
14732 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 |
14733 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc |
14734 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 |
14735 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 |
14736 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 |
14737 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c |
14738 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL |
14739 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L |
14740 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L |
14741 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L |
14742 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L |
14743 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L |
14744 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L |
14745 | #define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L |
14746 | //GCEA_ADDRDEC0_COL_SEL_HI_CS01 |
14747 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 |
14748 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 |
14749 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 |
14750 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc |
14751 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 |
14752 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 |
14753 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 |
14754 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c |
14755 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL |
14756 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L |
14757 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L |
14758 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L |
14759 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L |
14760 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L |
14761 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L |
14762 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L |
14763 | //GCEA_ADDRDEC0_COL_SEL_HI_CS23 |
14764 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 |
14765 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 |
14766 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 |
14767 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc |
14768 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 |
14769 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 |
14770 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 |
14771 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c |
14772 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL |
14773 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L |
14774 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L |
14775 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L |
14776 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L |
14777 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L |
14778 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L |
14779 | #define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L |
14780 | //GCEA_ADDRDEC0_RM_SEL_CS01 |
14781 | #define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 |
14782 | #define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 |
14783 | #define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 |
14784 | #define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc |
14785 | #define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
14786 | #define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
14787 | #define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL |
14788 | #define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L |
14789 | #define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L |
14790 | #define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L |
14791 | #define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
14792 | #define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
14793 | //GCEA_ADDRDEC0_RM_SEL_CS23 |
14794 | #define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 |
14795 | #define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 |
14796 | #define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 |
14797 | #define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc |
14798 | #define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
14799 | #define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
14800 | #define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL |
14801 | #define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L |
14802 | #define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L |
14803 | #define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L |
14804 | #define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
14805 | #define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
14806 | //GCEA_ADDRDEC0_RM_SEL_SECCS01 |
14807 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 |
14808 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 |
14809 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 |
14810 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc |
14811 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
14812 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
14813 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL |
14814 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L |
14815 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L |
14816 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L |
14817 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
14818 | #define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
14819 | //GCEA_ADDRDEC0_RM_SEL_SECCS23 |
14820 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 |
14821 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 |
14822 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 |
14823 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc |
14824 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
14825 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
14826 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL |
14827 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L |
14828 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L |
14829 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L |
14830 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
14831 | #define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
14832 | //GCEA_ADDRDEC1_BASE_ADDR_CS0 |
14833 | #define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 |
14834 | #define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 |
14835 | #define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L |
14836 | #define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL |
14837 | //GCEA_ADDRDEC1_BASE_ADDR_CS1 |
14838 | #define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 |
14839 | #define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 |
14840 | #define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L |
14841 | #define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL |
14842 | //GCEA_ADDRDEC1_BASE_ADDR_CS2 |
14843 | #define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 |
14844 | #define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 |
14845 | #define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L |
14846 | #define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL |
14847 | //GCEA_ADDRDEC1_BASE_ADDR_CS3 |
14848 | #define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 |
14849 | #define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 |
14850 | #define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L |
14851 | #define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL |
14852 | //GCEA_ADDRDEC1_BASE_ADDR_SECCS0 |
14853 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 |
14854 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 |
14855 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L |
14856 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL |
14857 | //GCEA_ADDRDEC1_BASE_ADDR_SECCS1 |
14858 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 |
14859 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 |
14860 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L |
14861 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL |
14862 | //GCEA_ADDRDEC1_BASE_ADDR_SECCS2 |
14863 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 |
14864 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 |
14865 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L |
14866 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL |
14867 | //GCEA_ADDRDEC1_BASE_ADDR_SECCS3 |
14868 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 |
14869 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 |
14870 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L |
14871 | #define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL |
14872 | //GCEA_ADDRDEC1_ADDR_MASK_CS01 |
14873 | #define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 |
14874 | #define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL |
14875 | //GCEA_ADDRDEC1_ADDR_MASK_CS23 |
14876 | #define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 |
14877 | #define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL |
14878 | //GCEA_ADDRDEC1_ADDR_MASK_SECCS01 |
14879 | #define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 |
14880 | #define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL |
14881 | //GCEA_ADDRDEC1_ADDR_MASK_SECCS23 |
14882 | #define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 |
14883 | #define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL |
14884 | //GCEA_ADDRDEC1_ADDR_CFG_CS01 |
14885 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 |
14886 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 |
14887 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 |
14888 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc |
14889 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 |
14890 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 |
14891 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f |
14892 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL |
14893 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L |
14894 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L |
14895 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L |
14896 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L |
14897 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L |
14898 | #define GCEA_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L |
14899 | //GCEA_ADDRDEC1_ADDR_CFG_CS23 |
14900 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 |
14901 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 |
14902 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 |
14903 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc |
14904 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 |
14905 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 |
14906 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f |
14907 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL |
14908 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L |
14909 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L |
14910 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L |
14911 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L |
14912 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L |
14913 | #define GCEA_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L |
14914 | //GCEA_ADDRDEC1_ADDR_SEL_CS01 |
14915 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 |
14916 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 |
14917 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 |
14918 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc |
14919 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 |
14920 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 |
14921 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c |
14922 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL |
14923 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L |
14924 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L |
14925 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L |
14926 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L |
14927 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L |
14928 | #define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L |
14929 | //GCEA_ADDRDEC1_ADDR_SEL_CS23 |
14930 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 |
14931 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 |
14932 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 |
14933 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc |
14934 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 |
14935 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 |
14936 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c |
14937 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL |
14938 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L |
14939 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L |
14940 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L |
14941 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L |
14942 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L |
14943 | #define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L |
14944 | //GCEA_ADDRDEC1_COL_SEL_LO_CS01 |
14945 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 |
14946 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 |
14947 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 |
14948 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc |
14949 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 |
14950 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 |
14951 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 |
14952 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c |
14953 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL |
14954 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L |
14955 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L |
14956 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L |
14957 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L |
14958 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L |
14959 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L |
14960 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L |
14961 | //GCEA_ADDRDEC1_COL_SEL_LO_CS23 |
14962 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 |
14963 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 |
14964 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 |
14965 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc |
14966 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 |
14967 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 |
14968 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 |
14969 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c |
14970 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL |
14971 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L |
14972 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L |
14973 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L |
14974 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L |
14975 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L |
14976 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L |
14977 | #define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L |
14978 | //GCEA_ADDRDEC1_COL_SEL_HI_CS01 |
14979 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 |
14980 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 |
14981 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 |
14982 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc |
14983 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 |
14984 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 |
14985 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 |
14986 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c |
14987 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL |
14988 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L |
14989 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L |
14990 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L |
14991 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L |
14992 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L |
14993 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L |
14994 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L |
14995 | //GCEA_ADDRDEC1_COL_SEL_HI_CS23 |
14996 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 |
14997 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 |
14998 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 |
14999 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc |
15000 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 |
15001 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 |
15002 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 |
15003 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c |
15004 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL |
15005 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L |
15006 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L |
15007 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L |
15008 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L |
15009 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L |
15010 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L |
15011 | #define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L |
15012 | //GCEA_ADDRDEC1_RM_SEL_CS01 |
15013 | #define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 |
15014 | #define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 |
15015 | #define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 |
15016 | #define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc |
15017 | #define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
15018 | #define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
15019 | #define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL |
15020 | #define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L |
15021 | #define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L |
15022 | #define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L |
15023 | #define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
15024 | #define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
15025 | //GCEA_ADDRDEC1_RM_SEL_CS23 |
15026 | #define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 |
15027 | #define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 |
15028 | #define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 |
15029 | #define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc |
15030 | #define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
15031 | #define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
15032 | #define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL |
15033 | #define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L |
15034 | #define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L |
15035 | #define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L |
15036 | #define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
15037 | #define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
15038 | //GCEA_ADDRDEC1_RM_SEL_SECCS01 |
15039 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 |
15040 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 |
15041 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 |
15042 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc |
15043 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
15044 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
15045 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL |
15046 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L |
15047 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L |
15048 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L |
15049 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
15050 | #define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
15051 | //GCEA_ADDRDEC1_RM_SEL_SECCS23 |
15052 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 |
15053 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 |
15054 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 |
15055 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc |
15056 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 |
15057 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 |
15058 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL |
15059 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L |
15060 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L |
15061 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L |
15062 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L |
15063 | #define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L |
15064 | //GCEA_IO_RD_CLI2GRP_MAP0 |
15065 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
15066 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
15067 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
15068 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
15069 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
15070 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
15071 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
15072 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
15073 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
15074 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
15075 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
15076 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
15077 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
15078 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
15079 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
15080 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
15081 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
15082 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
15083 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
15084 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
15085 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
15086 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
15087 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
15088 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
15089 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
15090 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
15091 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
15092 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
15093 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
15094 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
15095 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
15096 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
15097 | //GCEA_IO_RD_CLI2GRP_MAP1 |
15098 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
15099 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
15100 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
15101 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
15102 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
15103 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
15104 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
15105 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
15106 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
15107 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
15108 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
15109 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
15110 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
15111 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
15112 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
15113 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
15114 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
15115 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
15116 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
15117 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
15118 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
15119 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
15120 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
15121 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
15122 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
15123 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
15124 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
15125 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
15126 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
15127 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
15128 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
15129 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
15130 | //GCEA_IO_WR_CLI2GRP_MAP0 |
15131 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
15132 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
15133 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
15134 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
15135 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
15136 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
15137 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
15138 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
15139 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
15140 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
15141 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
15142 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
15143 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
15144 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
15145 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
15146 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
15147 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
15148 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
15149 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
15150 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
15151 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
15152 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
15153 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
15154 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
15155 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
15156 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
15157 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
15158 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
15159 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
15160 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
15161 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
15162 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
15163 | //GCEA_IO_WR_CLI2GRP_MAP1 |
15164 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
15165 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
15166 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
15167 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
15168 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
15169 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
15170 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
15171 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
15172 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
15173 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
15174 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
15175 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
15176 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
15177 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
15178 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
15179 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
15180 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
15181 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
15182 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
15183 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
15184 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
15185 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
15186 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
15187 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
15188 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
15189 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
15190 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
15191 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
15192 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
15193 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
15194 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
15195 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
15196 | //GCEA_IO_RD_COMBINE_FLUSH |
15197 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
15198 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
15199 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
15200 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
15201 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
15202 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
15203 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
15204 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
15205 | //GCEA_IO_WR_COMBINE_FLUSH |
15206 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
15207 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
15208 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
15209 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
15210 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
15211 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
15212 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
15213 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
15214 | //GCEA_IO_GROUP_BURST |
15215 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 |
15216 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 |
15217 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 |
15218 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 |
15219 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
15220 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
15221 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
15222 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
15223 | //GCEA_IO_RD_PRI_AGE |
15224 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
15225 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
15226 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
15227 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
15228 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
15229 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
15230 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
15231 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
15232 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
15233 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
15234 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
15235 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
15236 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
15237 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
15238 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
15239 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
15240 | //GCEA_IO_WR_PRI_AGE |
15241 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
15242 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
15243 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
15244 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
15245 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
15246 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
15247 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
15248 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
15249 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
15250 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
15251 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
15252 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
15253 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
15254 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
15255 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
15256 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
15257 | //GCEA_IO_RD_PRI_QUEUING |
15258 | #define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
15259 | #define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
15260 | #define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
15261 | #define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
15262 | #define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
15263 | #define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
15264 | #define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
15265 | #define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
15266 | //GCEA_IO_WR_PRI_QUEUING |
15267 | #define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
15268 | #define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
15269 | #define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
15270 | #define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
15271 | #define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
15272 | #define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
15273 | #define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
15274 | #define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
15275 | //GCEA_IO_RD_PRI_FIXED |
15276 | #define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
15277 | #define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
15278 | #define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
15279 | #define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
15280 | #define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
15281 | #define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
15282 | #define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
15283 | #define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
15284 | //GCEA_IO_WR_PRI_FIXED |
15285 | #define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
15286 | #define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
15287 | #define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
15288 | #define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
15289 | #define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
15290 | #define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
15291 | #define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
15292 | #define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
15293 | //GCEA_IO_RD_PRI_URGENCY |
15294 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
15295 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
15296 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
15297 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
15298 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
15299 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
15300 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
15301 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
15302 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
15303 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
15304 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
15305 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
15306 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
15307 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
15308 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
15309 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
15310 | //GCEA_IO_WR_PRI_URGENCY |
15311 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
15312 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
15313 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
15314 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
15315 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
15316 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
15317 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
15318 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
15319 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
15320 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
15321 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
15322 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
15323 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
15324 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
15325 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
15326 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
15327 | //GCEA_IO_RD_PRI_URGENCY_MASKING |
15328 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
15329 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
15330 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
15331 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
15332 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
15333 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
15334 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
15335 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
15336 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
15337 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
15338 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
15339 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
15340 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
15341 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
15342 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
15343 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
15344 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
15345 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
15346 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
15347 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
15348 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
15349 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
15350 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
15351 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
15352 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
15353 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
15354 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
15355 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
15356 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
15357 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
15358 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
15359 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
15360 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
15361 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
15362 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
15363 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
15364 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
15365 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
15366 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
15367 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
15368 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
15369 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
15370 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
15371 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
15372 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
15373 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
15374 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
15375 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
15376 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
15377 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
15378 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
15379 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
15380 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
15381 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
15382 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
15383 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
15384 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
15385 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
15386 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
15387 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
15388 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
15389 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
15390 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
15391 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
15392 | //GCEA_IO_WR_PRI_URGENCY_MASKING |
15393 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
15394 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
15395 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
15396 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
15397 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
15398 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
15399 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
15400 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
15401 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
15402 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
15403 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
15404 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
15405 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
15406 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
15407 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
15408 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
15409 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
15410 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
15411 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
15412 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
15413 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
15414 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
15415 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
15416 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
15417 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
15418 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
15419 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
15420 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
15421 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
15422 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
15423 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
15424 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
15425 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
15426 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
15427 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
15428 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
15429 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
15430 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
15431 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
15432 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
15433 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
15434 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
15435 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
15436 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
15437 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
15438 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
15439 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
15440 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
15441 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
15442 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
15443 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
15444 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
15445 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
15446 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
15447 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
15448 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
15449 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
15450 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
15451 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
15452 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
15453 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
15454 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
15455 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
15456 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
15457 | //GCEA_IO_RD_PRI_QUANT_PRI1 |
15458 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
15459 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
15460 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
15461 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
15462 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
15463 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15464 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15465 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
15466 | //GCEA_IO_RD_PRI_QUANT_PRI2 |
15467 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
15468 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
15469 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
15470 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
15471 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
15472 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15473 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15474 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
15475 | //GCEA_IO_RD_PRI_QUANT_PRI3 |
15476 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
15477 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
15478 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
15479 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
15480 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
15481 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15482 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15483 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
15484 | //GCEA_IO_WR_PRI_QUANT_PRI1 |
15485 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
15486 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
15487 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
15488 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
15489 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
15490 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15491 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15492 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
15493 | //GCEA_IO_WR_PRI_QUANT_PRI2 |
15494 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
15495 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
15496 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
15497 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
15498 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
15499 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15500 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15501 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
15502 | //GCEA_IO_WR_PRI_QUANT_PRI3 |
15503 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
15504 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
15505 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
15506 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
15507 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
15508 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
15509 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
15510 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
15511 | //GCEA_SDP_ARB_DRAM |
15512 | #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 |
15513 | #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 |
15514 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 |
15515 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 |
15516 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 |
15517 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 |
15518 | #define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 |
15519 | #define GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 |
15520 | #define GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING__SHIFT 0x16 |
15521 | #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL |
15522 | #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L |
15523 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L |
15524 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L |
15525 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L |
15526 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L |
15527 | #define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L |
15528 | #define GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L |
15529 | #define GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING_MASK 0x00400000L |
15530 | //GCEA_SDP_ARB_FINAL |
15531 | #define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 |
15532 | #define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 |
15533 | #define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa |
15534 | #define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf |
15535 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 |
15536 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 |
15537 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 |
15538 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 |
15539 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 |
15540 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 |
15541 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 |
15542 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 |
15543 | #define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 |
15544 | #define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a |
15545 | #define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL |
15546 | #define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L |
15547 | #define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L |
15548 | #define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L |
15549 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L |
15550 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L |
15551 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L |
15552 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L |
15553 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L |
15554 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L |
15555 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L |
15556 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L |
15557 | #define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L |
15558 | #define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L |
15559 | //GCEA_SDP_DRAM_PRIORITY |
15560 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
15561 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
15562 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
15563 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
15564 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
15565 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
15566 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
15567 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
15568 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
15569 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
15570 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
15571 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
15572 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
15573 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
15574 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
15575 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
15576 | //GCEA_SDP_IO_PRIORITY |
15577 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
15578 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
15579 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
15580 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
15581 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
15582 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
15583 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
15584 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
15585 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
15586 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
15587 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
15588 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
15589 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
15590 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
15591 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
15592 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
15593 | //GCEA_SDP_CREDITS |
15594 | #define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 |
15595 | #define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 |
15596 | #define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 |
15597 | #define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x18 |
15598 | #define GCEA_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL |
15599 | #define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L |
15600 | #define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L |
15601 | #define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F000000L |
15602 | //GCEA_SDP_TAG_RESERVE0 |
15603 | #define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 |
15604 | #define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 |
15605 | #define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 |
15606 | #define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 |
15607 | #define GCEA_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL |
15608 | #define GCEA_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L |
15609 | #define GCEA_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L |
15610 | #define GCEA_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L |
15611 | //GCEA_SDP_TAG_RESERVE1 |
15612 | #define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 |
15613 | #define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 |
15614 | #define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 |
15615 | #define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 |
15616 | #define GCEA_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL |
15617 | #define GCEA_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L |
15618 | #define GCEA_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L |
15619 | #define GCEA_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L |
15620 | //GCEA_SDP_VCC_RESERVE0 |
15621 | #define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
15622 | #define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
15623 | #define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc |
15624 | #define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
15625 | #define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
15626 | #define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
15627 | #define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
15628 | #define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
15629 | #define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
15630 | #define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
15631 | //GCEA_SDP_VCC_RESERVE1 |
15632 | #define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
15633 | #define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
15634 | #define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc |
15635 | #define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
15636 | #define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
15637 | #define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
15638 | #define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
15639 | #define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
15640 | //GCEA_SDP_VCD_RESERVE0 |
15641 | #define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
15642 | #define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
15643 | #define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc |
15644 | #define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
15645 | #define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
15646 | #define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
15647 | #define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
15648 | #define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
15649 | #define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
15650 | #define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
15651 | |
15652 | |
15653 | // addressBlock: gc_tcdec |
15654 | //TCP_INVALIDATE |
15655 | #define TCP_INVALIDATE__START__SHIFT 0x0 |
15656 | #define TCP_INVALIDATE__START_MASK 0x00000001L |
15657 | //TCP_STATUS |
15658 | #define TCP_STATUS__TCP_BUSY__SHIFT 0x0 |
15659 | #define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 |
15660 | #define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 |
15661 | #define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 |
15662 | #define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 |
15663 | #define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 |
15664 | #define TCP_STATUS__READ_BUSY__SHIFT 0x6 |
15665 | #define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 |
15666 | #define TCP_STATUS__VM_BUSY__SHIFT 0x8 |
15667 | #define TCP_STATUS__OFIFO_BUSY__SHIFT 0x9 |
15668 | #define TCP_STATUS__MEMIF_BUSY__SHIFT 0xa |
15669 | #define TCP_STATUS__TCP_BUSY_MASK 0x00000001L |
15670 | #define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L |
15671 | #define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L |
15672 | #define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L |
15673 | #define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L |
15674 | #define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L |
15675 | #define TCP_STATUS__READ_BUSY_MASK 0x00000040L |
15676 | #define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L |
15677 | #define TCP_STATUS__VM_BUSY_MASK 0x00000100L |
15678 | #define TCP_STATUS__OFIFO_BUSY_MASK 0x00000200L |
15679 | #define TCP_STATUS__MEMIF_BUSY_MASK 0x00000400L |
15680 | //TCP_CNTL |
15681 | #define TCP_CNTL__FORCE_HIT__SHIFT 0x0 |
15682 | #define TCP_CNTL__FORCE_MISS__SHIFT 0x1 |
15683 | #define TCP_CNTL__L0_SIZE__SHIFT 0x2 |
15684 | #define TCP_CNTL__BIG_PAGE_ADDR_COMBINE_DISABLE__SHIFT 0x4 |
15685 | #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 |
15686 | #define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf |
15687 | #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16 |
15688 | #define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c |
15689 | #define TCP_CNTL__LFIFO_SIZE__SHIFT 0x1d |
15690 | #define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1f |
15691 | #define TCP_CNTL__FORCE_HIT_MASK 0x00000001L |
15692 | #define TCP_CNTL__FORCE_MISS_MASK 0x00000002L |
15693 | #define TCP_CNTL__L0_SIZE_MASK 0x0000000CL |
15694 | #define TCP_CNTL__BIG_PAGE_ADDR_COMBINE_DISABLE_MASK 0x00000010L |
15695 | #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L |
15696 | #define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L |
15697 | #define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0FC00000L |
15698 | #define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L |
15699 | #define TCP_CNTL__LFIFO_SIZE_MASK 0x60000000L |
15700 | #define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x80000000L |
15701 | //TCP_CREDIT |
15702 | #define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 |
15703 | #define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d |
15704 | #define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007F0000L |
15705 | #define TCP_CREDIT__TD_CREDIT_MASK 0xE0000000L |
15706 | //TCP_BUFFER_ADDR_HASH_CNTL |
15707 | #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0 |
15708 | #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8 |
15709 | #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10 |
15710 | #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18 |
15711 | #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L |
15712 | #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L |
15713 | #define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L |
15714 | #define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L |
15715 | //TCP_EDC_CNT |
15716 | #define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0 |
15717 | #define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8 |
15718 | #define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10 |
15719 | #define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL |
15720 | #define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L |
15721 | #define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L |
15722 | //TCI_STATUS |
15723 | #define TCI_STATUS__TCI_BUSY__SHIFT 0x0 |
15724 | #define TCI_STATUS__TCI_BUSY_MASK 0x00000001L |
15725 | //TCI_CNTL_1 |
15726 | #define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 |
15727 | #define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 |
15728 | #define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 |
15729 | #define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL |
15730 | #define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L |
15731 | #define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L |
15732 | //TCI_CNTL_2 |
15733 | #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 |
15734 | #define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 |
15735 | #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L |
15736 | #define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL |
15737 | |
15738 | |
15739 | // addressBlock: gc_shdec |
15740 | //SPI_SHADER_PGM_RSRC4_PS |
15741 | #define SPI_SHADER_PGM_RSRC4_PS__CU_EN__SHIFT 0x0 |
15742 | #define SPI_SHADER_PGM_RSRC4_PS__CU_EN_MASK 0x0000FFFFL |
15743 | //SPI_SHADER_PGM_CHKSUM_PS |
15744 | #define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM__SHIFT 0x0 |
15745 | #define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM_MASK 0xFFFFFFFFL |
15746 | //SPI_SHADER_PGM_RSRC3_PS |
15747 | #define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 |
15748 | #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 |
15749 | #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 |
15750 | #define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL |
15751 | #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L |
15752 | #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L |
15753 | //SPI_SHADER_PGM_LO_PS |
15754 | #define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 |
15755 | #define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL |
15756 | //SPI_SHADER_PGM_HI_PS |
15757 | #define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 |
15758 | #define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL |
15759 | //SPI_SHADER_PGM_RSRC1_PS |
15760 | #define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 |
15761 | #define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 |
15762 | #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa |
15763 | #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc |
15764 | #define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 |
15765 | #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 |
15766 | #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 |
15767 | #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 |
15768 | #define SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED__SHIFT 0x19 |
15769 | #define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS__SHIFT 0x1a |
15770 | #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d |
15771 | #define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL |
15772 | #define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L |
15773 | #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L |
15774 | #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L |
15775 | #define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L |
15776 | #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L |
15777 | #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L |
15778 | #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L |
15779 | #define SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED_MASK 0x02000000L |
15780 | #define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS_MASK 0x04000000L |
15781 | #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L |
15782 | //SPI_SHADER_PGM_RSRC2_PS |
15783 | #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 |
15784 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 |
15785 | #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 |
15786 | #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 |
15787 | #define 0x8 |
15788 | #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 |
15789 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19 |
15790 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a |
15791 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1b |
15792 | #define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT__SHIFT 0x1c |
15793 | #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L |
15794 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL |
15795 | #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L |
15796 | #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L |
15797 | #define 0x0000FF00L |
15798 | #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L |
15799 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L |
15800 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L |
15801 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x08000000L |
15802 | #define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT_MASK 0xF0000000L |
15803 | //SPI_SHADER_USER_DATA_PS_0 |
15804 | #define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 |
15805 | #define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL |
15806 | //SPI_SHADER_USER_DATA_PS_1 |
15807 | #define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 |
15808 | #define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL |
15809 | //SPI_SHADER_USER_DATA_PS_2 |
15810 | #define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 |
15811 | #define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL |
15812 | //SPI_SHADER_USER_DATA_PS_3 |
15813 | #define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 |
15814 | #define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL |
15815 | //SPI_SHADER_USER_DATA_PS_4 |
15816 | #define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 |
15817 | #define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL |
15818 | //SPI_SHADER_USER_DATA_PS_5 |
15819 | #define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 |
15820 | #define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL |
15821 | //SPI_SHADER_USER_DATA_PS_6 |
15822 | #define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 |
15823 | #define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL |
15824 | //SPI_SHADER_USER_DATA_PS_7 |
15825 | #define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 |
15826 | #define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL |
15827 | //SPI_SHADER_USER_DATA_PS_8 |
15828 | #define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 |
15829 | #define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL |
15830 | //SPI_SHADER_USER_DATA_PS_9 |
15831 | #define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 |
15832 | #define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL |
15833 | //SPI_SHADER_USER_DATA_PS_10 |
15834 | #define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 |
15835 | #define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL |
15836 | //SPI_SHADER_USER_DATA_PS_11 |
15837 | #define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 |
15838 | #define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL |
15839 | //SPI_SHADER_USER_DATA_PS_12 |
15840 | #define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 |
15841 | #define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL |
15842 | //SPI_SHADER_USER_DATA_PS_13 |
15843 | #define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 |
15844 | #define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL |
15845 | //SPI_SHADER_USER_DATA_PS_14 |
15846 | #define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 |
15847 | #define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL |
15848 | //SPI_SHADER_USER_DATA_PS_15 |
15849 | #define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 |
15850 | #define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL |
15851 | //SPI_SHADER_USER_DATA_PS_16 |
15852 | #define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0 |
15853 | #define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL |
15854 | //SPI_SHADER_USER_DATA_PS_17 |
15855 | #define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0 |
15856 | #define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL |
15857 | //SPI_SHADER_USER_DATA_PS_18 |
15858 | #define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0 |
15859 | #define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL |
15860 | //SPI_SHADER_USER_DATA_PS_19 |
15861 | #define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0 |
15862 | #define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL |
15863 | //SPI_SHADER_USER_DATA_PS_20 |
15864 | #define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0 |
15865 | #define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL |
15866 | //SPI_SHADER_USER_DATA_PS_21 |
15867 | #define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0 |
15868 | #define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL |
15869 | //SPI_SHADER_USER_DATA_PS_22 |
15870 | #define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0 |
15871 | #define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL |
15872 | //SPI_SHADER_USER_DATA_PS_23 |
15873 | #define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0 |
15874 | #define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL |
15875 | //SPI_SHADER_USER_DATA_PS_24 |
15876 | #define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0 |
15877 | #define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL |
15878 | //SPI_SHADER_USER_DATA_PS_25 |
15879 | #define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0 |
15880 | #define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL |
15881 | //SPI_SHADER_USER_DATA_PS_26 |
15882 | #define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0 |
15883 | #define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL |
15884 | //SPI_SHADER_USER_DATA_PS_27 |
15885 | #define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0 |
15886 | #define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL |
15887 | //SPI_SHADER_USER_DATA_PS_28 |
15888 | #define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0 |
15889 | #define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL |
15890 | //SPI_SHADER_USER_DATA_PS_29 |
15891 | #define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0 |
15892 | #define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL |
15893 | //SPI_SHADER_USER_DATA_PS_30 |
15894 | #define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0 |
15895 | #define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL |
15896 | //SPI_SHADER_USER_DATA_PS_31 |
15897 | #define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0 |
15898 | #define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL |
15899 | //SPI_SHADER_REQ_CTRL_PS |
15900 | #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN__SHIFT 0x0 |
15901 | #define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 |
15902 | #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 |
15903 | #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 |
15904 | #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa |
15905 | #define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf |
15906 | #define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN__SHIFT 0x10 |
15907 | #define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 |
15908 | #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN_MASK 0x00000001L |
15909 | #define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL |
15910 | #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L |
15911 | #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L |
15912 | #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L |
15913 | #define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L |
15914 | #define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN_MASK 0x00010000L |
15915 | #define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L |
15916 | //SPI_SHADER_PREF_PRI_CNTR_CTRL_PS |
15917 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__TOTAL_WAVE_COUNT_HIER_SELECT__SHIFT 0x0 |
15918 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__PER_TYPE_WAVE_COUNT_HIER_SELECT__SHIFT 0x3 |
15919 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__GROUP_UPDATE_EN__SHIFT 0x6 |
15920 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__TOTAL_WAVE_COUNT_COEFFICIENT__SHIFT 0x8 |
15921 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__PER_TYPE_WAVE_COUNT_COEFFICIENT__SHIFT 0x10 |
15922 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__TOTAL_WAVE_COUNT_HIER_SELECT_MASK 0x00000007L |
15923 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__PER_TYPE_WAVE_COUNT_HIER_SELECT_MASK 0x00000038L |
15924 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__GROUP_UPDATE_EN_MASK 0x00000040L |
15925 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__TOTAL_WAVE_COUNT_COEFFICIENT_MASK 0x0000FF00L |
15926 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_PS__PER_TYPE_WAVE_COUNT_COEFFICIENT_MASK 0x00FF0000L |
15927 | //SPI_SHADER_PREF_PRI_ACCUM_PS_0 |
15928 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__CONTRIBUTION__SHIFT 0x0 |
15929 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
15930 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
15931 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__GROUP_UPDATE_EN__SHIFT 0xd |
15932 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__RESERVED__SHIFT 0xe |
15933 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__COEFFICIENT__SHIFT 0xf |
15934 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__CONTRIBUTION_MASK 0x0000007FL |
15935 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
15936 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
15937 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__GROUP_UPDATE_EN_MASK 0x00002000L |
15938 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__RESERVED_MASK 0x00004000L |
15939 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_0__COEFFICIENT_MASK 0x007F8000L |
15940 | //SPI_SHADER_USER_ACCUM_PS_0 |
15941 | #define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION__SHIFT 0x0 |
15942 | #define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION_MASK 0x0000007FL |
15943 | //SPI_SHADER_PREF_PRI_ACCUM_PS_1 |
15944 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__CONTRIBUTION__SHIFT 0x0 |
15945 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
15946 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
15947 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__GROUP_UPDATE_EN__SHIFT 0xd |
15948 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__RESERVED__SHIFT 0xe |
15949 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__COEFFICIENT__SHIFT 0xf |
15950 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__CONTRIBUTION_MASK 0x0000007FL |
15951 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
15952 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
15953 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__GROUP_UPDATE_EN_MASK 0x00002000L |
15954 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__RESERVED_MASK 0x00004000L |
15955 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_1__COEFFICIENT_MASK 0x007F8000L |
15956 | //SPI_SHADER_USER_ACCUM_PS_1 |
15957 | #define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION__SHIFT 0x0 |
15958 | #define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION_MASK 0x0000007FL |
15959 | //SPI_SHADER_PREF_PRI_ACCUM_PS_2 |
15960 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__CONTRIBUTION__SHIFT 0x0 |
15961 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
15962 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
15963 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__GROUP_UPDATE_EN__SHIFT 0xd |
15964 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__RESERVED__SHIFT 0xe |
15965 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__COEFFICIENT__SHIFT 0xf |
15966 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__CONTRIBUTION_MASK 0x0000007FL |
15967 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
15968 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
15969 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__GROUP_UPDATE_EN_MASK 0x00002000L |
15970 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__RESERVED_MASK 0x00004000L |
15971 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_2__COEFFICIENT_MASK 0x007F8000L |
15972 | //SPI_SHADER_USER_ACCUM_PS_2 |
15973 | #define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION__SHIFT 0x0 |
15974 | #define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION_MASK 0x0000007FL |
15975 | //SPI_SHADER_PREF_PRI_ACCUM_PS_3 |
15976 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__CONTRIBUTION__SHIFT 0x0 |
15977 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
15978 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
15979 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__GROUP_UPDATE_EN__SHIFT 0xd |
15980 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__RESERVED__SHIFT 0xe |
15981 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__COEFFICIENT__SHIFT 0xf |
15982 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__CONTRIBUTION_MASK 0x0000007FL |
15983 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
15984 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
15985 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__GROUP_UPDATE_EN_MASK 0x00002000L |
15986 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__RESERVED_MASK 0x00004000L |
15987 | #define SPI_SHADER_PREF_PRI_ACCUM_PS_3__COEFFICIENT_MASK 0x007F8000L |
15988 | //SPI_SHADER_USER_ACCUM_PS_3 |
15989 | #define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION__SHIFT 0x0 |
15990 | #define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION_MASK 0x0000007FL |
15991 | //SPI_SHADER_PGM_RSRC4_VS |
15992 | #define SPI_SHADER_PGM_RSRC4_VS__CU_EN__SHIFT 0x0 |
15993 | #define SPI_SHADER_PGM_RSRC4_VS__CU_EN_MASK 0x0000FFFFL |
15994 | //SPI_SHADER_PGM_CHKSUM_VS |
15995 | #define SPI_SHADER_PGM_CHKSUM_VS__CHECKSUM__SHIFT 0x0 |
15996 | #define SPI_SHADER_PGM_CHKSUM_VS__CHECKSUM_MASK 0xFFFFFFFFL |
15997 | //SPI_SHADER_PGM_RSRC3_VS |
15998 | #define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 |
15999 | #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 |
16000 | #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 |
16001 | #define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL |
16002 | #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L |
16003 | #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L |
16004 | //SPI_SHADER_LATE_ALLOC_VS |
16005 | #define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 |
16006 | #define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL |
16007 | //SPI_SHADER_PGM_LO_VS |
16008 | #define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 |
16009 | #define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL |
16010 | //SPI_SHADER_PGM_HI_VS |
16011 | #define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 |
16012 | #define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL |
16013 | //SPI_SHADER_PGM_RSRC1_VS |
16014 | #define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 |
16015 | #define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 |
16016 | #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa |
16017 | #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc |
16018 | #define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 |
16019 | #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 |
16020 | #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 |
16021 | #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 |
16022 | #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a |
16023 | #define SPI_SHADER_PGM_RSRC1_VS__MEM_ORDERED__SHIFT 0x1b |
16024 | #define SPI_SHADER_PGM_RSRC1_VS__FWD_PROGRESS__SHIFT 0x1c |
16025 | #define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f |
16026 | #define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL |
16027 | #define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L |
16028 | #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L |
16029 | #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L |
16030 | #define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L |
16031 | #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L |
16032 | #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L |
16033 | #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L |
16034 | #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L |
16035 | #define SPI_SHADER_PGM_RSRC1_VS__MEM_ORDERED_MASK 0x08000000L |
16036 | #define SPI_SHADER_PGM_RSRC1_VS__FWD_PROGRESS_MASK 0x10000000L |
16037 | #define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L |
16038 | //SPI_SHADER_PGM_RSRC2_VS |
16039 | #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 |
16040 | #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 |
16041 | #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 |
16042 | #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 |
16043 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 |
16044 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 |
16045 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa |
16046 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb |
16047 | #define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc |
16048 | #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd |
16049 | #define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16 |
16050 | #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18 |
16051 | #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1b |
16052 | #define SPI_SHADER_PGM_RSRC2_VS__SHARED_VGPR_CNT__SHIFT 0x1c |
16053 | #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L |
16054 | #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL |
16055 | #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L |
16056 | #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L |
16057 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L |
16058 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L |
16059 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L |
16060 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L |
16061 | #define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L |
16062 | #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L |
16063 | #define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L |
16064 | #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L |
16065 | #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x08000000L |
16066 | #define SPI_SHADER_PGM_RSRC2_VS__SHARED_VGPR_CNT_MASK 0xF0000000L |
16067 | //SPI_SHADER_USER_DATA_VS_0 |
16068 | #define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 |
16069 | #define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL |
16070 | //SPI_SHADER_USER_DATA_VS_1 |
16071 | #define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 |
16072 | #define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL |
16073 | //SPI_SHADER_USER_DATA_VS_2 |
16074 | #define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 |
16075 | #define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL |
16076 | //SPI_SHADER_USER_DATA_VS_3 |
16077 | #define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 |
16078 | #define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL |
16079 | //SPI_SHADER_USER_DATA_VS_4 |
16080 | #define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 |
16081 | #define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL |
16082 | //SPI_SHADER_USER_DATA_VS_5 |
16083 | #define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 |
16084 | #define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL |
16085 | //SPI_SHADER_USER_DATA_VS_6 |
16086 | #define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 |
16087 | #define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL |
16088 | //SPI_SHADER_USER_DATA_VS_7 |
16089 | #define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 |
16090 | #define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL |
16091 | //SPI_SHADER_USER_DATA_VS_8 |
16092 | #define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 |
16093 | #define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL |
16094 | //SPI_SHADER_USER_DATA_VS_9 |
16095 | #define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 |
16096 | #define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL |
16097 | //SPI_SHADER_USER_DATA_VS_10 |
16098 | #define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 |
16099 | #define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL |
16100 | //SPI_SHADER_USER_DATA_VS_11 |
16101 | #define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 |
16102 | #define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL |
16103 | //SPI_SHADER_USER_DATA_VS_12 |
16104 | #define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 |
16105 | #define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL |
16106 | //SPI_SHADER_USER_DATA_VS_13 |
16107 | #define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 |
16108 | #define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL |
16109 | //SPI_SHADER_USER_DATA_VS_14 |
16110 | #define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 |
16111 | #define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL |
16112 | //SPI_SHADER_USER_DATA_VS_15 |
16113 | #define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 |
16114 | #define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL |
16115 | //SPI_SHADER_USER_DATA_VS_16 |
16116 | #define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0 |
16117 | #define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL |
16118 | //SPI_SHADER_USER_DATA_VS_17 |
16119 | #define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0 |
16120 | #define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL |
16121 | //SPI_SHADER_USER_DATA_VS_18 |
16122 | #define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0 |
16123 | #define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL |
16124 | //SPI_SHADER_USER_DATA_VS_19 |
16125 | #define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0 |
16126 | #define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL |
16127 | //SPI_SHADER_USER_DATA_VS_20 |
16128 | #define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0 |
16129 | #define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL |
16130 | //SPI_SHADER_USER_DATA_VS_21 |
16131 | #define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0 |
16132 | #define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL |
16133 | //SPI_SHADER_USER_DATA_VS_22 |
16134 | #define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0 |
16135 | #define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL |
16136 | //SPI_SHADER_USER_DATA_VS_23 |
16137 | #define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0 |
16138 | #define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL |
16139 | //SPI_SHADER_USER_DATA_VS_24 |
16140 | #define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0 |
16141 | #define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL |
16142 | //SPI_SHADER_USER_DATA_VS_25 |
16143 | #define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0 |
16144 | #define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL |
16145 | //SPI_SHADER_USER_DATA_VS_26 |
16146 | #define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0 |
16147 | #define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL |
16148 | //SPI_SHADER_USER_DATA_VS_27 |
16149 | #define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0 |
16150 | #define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL |
16151 | //SPI_SHADER_USER_DATA_VS_28 |
16152 | #define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0 |
16153 | #define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL |
16154 | //SPI_SHADER_USER_DATA_VS_29 |
16155 | #define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0 |
16156 | #define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL |
16157 | //SPI_SHADER_USER_DATA_VS_30 |
16158 | #define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0 |
16159 | #define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL |
16160 | //SPI_SHADER_USER_DATA_VS_31 |
16161 | #define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0 |
16162 | #define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL |
16163 | //SPI_SHADER_REQ_CTRL_VS |
16164 | #define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_EN__SHIFT 0x0 |
16165 | #define SPI_SHADER_REQ_CTRL_VS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 |
16166 | #define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 |
16167 | #define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 |
16168 | #define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa |
16169 | #define SPI_SHADER_REQ_CTRL_VS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf |
16170 | #define SPI_SHADER_REQ_CTRL_VS__GLOBAL_SCANNING_EN__SHIFT 0x10 |
16171 | #define SPI_SHADER_REQ_CTRL_VS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 |
16172 | #define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_EN_MASK 0x00000001L |
16173 | #define SPI_SHADER_REQ_CTRL_VS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL |
16174 | #define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L |
16175 | #define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L |
16176 | #define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L |
16177 | #define SPI_SHADER_REQ_CTRL_VS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L |
16178 | #define SPI_SHADER_REQ_CTRL_VS__GLOBAL_SCANNING_EN_MASK 0x00010000L |
16179 | #define SPI_SHADER_REQ_CTRL_VS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L |
16180 | //SPI_SHADER_PREF_PRI_CNTR_CTRL_VS |
16181 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__TOTAL_WAVE_COUNT_HIER_SELECT__SHIFT 0x0 |
16182 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__PER_TYPE_WAVE_COUNT_HIER_SELECT__SHIFT 0x3 |
16183 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__GROUP_UPDATE_EN__SHIFT 0x6 |
16184 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__TOTAL_WAVE_COUNT_COEFFICIENT__SHIFT 0x8 |
16185 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__PER_TYPE_WAVE_COUNT_COEFFICIENT__SHIFT 0x10 |
16186 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__TOTAL_WAVE_COUNT_HIER_SELECT_MASK 0x00000007L |
16187 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__PER_TYPE_WAVE_COUNT_HIER_SELECT_MASK 0x00000038L |
16188 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__GROUP_UPDATE_EN_MASK 0x00000040L |
16189 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__TOTAL_WAVE_COUNT_COEFFICIENT_MASK 0x0000FF00L |
16190 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_VS__PER_TYPE_WAVE_COUNT_COEFFICIENT_MASK 0x00FF0000L |
16191 | //SPI_SHADER_PREF_PRI_ACCUM_VS_0 |
16192 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__CONTRIBUTION__SHIFT 0x0 |
16193 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
16194 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
16195 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__GROUP_UPDATE_EN__SHIFT 0xd |
16196 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__RESERVED__SHIFT 0xe |
16197 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__COEFFICIENT__SHIFT 0xf |
16198 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__CONTRIBUTION_MASK 0x0000007FL |
16199 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
16200 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
16201 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__GROUP_UPDATE_EN_MASK 0x00002000L |
16202 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__RESERVED_MASK 0x00004000L |
16203 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_0__COEFFICIENT_MASK 0x007F8000L |
16204 | //SPI_SHADER_USER_ACCUM_VS_0 |
16205 | #define SPI_SHADER_USER_ACCUM_VS_0__CONTRIBUTION__SHIFT 0x0 |
16206 | #define SPI_SHADER_USER_ACCUM_VS_0__CONTRIBUTION_MASK 0x0000007FL |
16207 | //SPI_SHADER_PREF_PRI_ACCUM_VS_1 |
16208 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__CONTRIBUTION__SHIFT 0x0 |
16209 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
16210 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
16211 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__GROUP_UPDATE_EN__SHIFT 0xd |
16212 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__RESERVED__SHIFT 0xe |
16213 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__COEFFICIENT__SHIFT 0xf |
16214 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__CONTRIBUTION_MASK 0x0000007FL |
16215 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
16216 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
16217 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__GROUP_UPDATE_EN_MASK 0x00002000L |
16218 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__RESERVED_MASK 0x00004000L |
16219 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_1__COEFFICIENT_MASK 0x007F8000L |
16220 | //SPI_SHADER_USER_ACCUM_VS_1 |
16221 | #define SPI_SHADER_USER_ACCUM_VS_1__CONTRIBUTION__SHIFT 0x0 |
16222 | #define SPI_SHADER_USER_ACCUM_VS_1__CONTRIBUTION_MASK 0x0000007FL |
16223 | //SPI_SHADER_PREF_PRI_ACCUM_VS_2 |
16224 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__CONTRIBUTION__SHIFT 0x0 |
16225 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
16226 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
16227 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__GROUP_UPDATE_EN__SHIFT 0xd |
16228 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__RESERVED__SHIFT 0xe |
16229 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__COEFFICIENT__SHIFT 0xf |
16230 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__CONTRIBUTION_MASK 0x0000007FL |
16231 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
16232 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
16233 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__GROUP_UPDATE_EN_MASK 0x00002000L |
16234 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__RESERVED_MASK 0x00004000L |
16235 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_2__COEFFICIENT_MASK 0x007F8000L |
16236 | //SPI_SHADER_USER_ACCUM_VS_2 |
16237 | #define SPI_SHADER_USER_ACCUM_VS_2__CONTRIBUTION__SHIFT 0x0 |
16238 | #define SPI_SHADER_USER_ACCUM_VS_2__CONTRIBUTION_MASK 0x0000007FL |
16239 | //SPI_SHADER_PREF_PRI_ACCUM_VS_3 |
16240 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__CONTRIBUTION__SHIFT 0x0 |
16241 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
16242 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
16243 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__GROUP_UPDATE_EN__SHIFT 0xd |
16244 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__RESERVED__SHIFT 0xe |
16245 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__COEFFICIENT__SHIFT 0xf |
16246 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__CONTRIBUTION_MASK 0x0000007FL |
16247 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
16248 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
16249 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__GROUP_UPDATE_EN_MASK 0x00002000L |
16250 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__RESERVED_MASK 0x00004000L |
16251 | #define SPI_SHADER_PREF_PRI_ACCUM_VS_3__COEFFICIENT_MASK 0x007F8000L |
16252 | //SPI_SHADER_USER_ACCUM_VS_3 |
16253 | #define SPI_SHADER_USER_ACCUM_VS_3__CONTRIBUTION__SHIFT 0x0 |
16254 | #define SPI_SHADER_USER_ACCUM_VS_3__CONTRIBUTION_MASK 0x0000007FL |
16255 | //SPI_SHADER_PGM_RSRC2_GS_VS |
16256 | #define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0 |
16257 | #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1 |
16258 | #define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6 |
16259 | #define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7 |
16260 | #define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10 |
16261 | #define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12 |
16262 | #define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13 |
16263 | #define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b |
16264 | #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c |
16265 | #define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L |
16266 | #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL |
16267 | #define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L |
16268 | #define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L |
16269 | #define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L |
16270 | #define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L |
16271 | #define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L |
16272 | #define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L |
16273 | #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L |
16274 | //SPI_SHADER_PGM_RSRC2_ES_VS |
16275 | #define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0 |
16276 | #define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1 |
16277 | #define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6 |
16278 | #define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7 |
16279 | #define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8 |
16280 | #define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14 |
16281 | #define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x00000001L |
16282 | #define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x0000003EL |
16283 | #define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x00000040L |
16284 | #define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x00000080L |
16285 | #define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x0001FF00L |
16286 | #define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1FF00000L |
16287 | //SPI_SHADER_PGM_RSRC2_LS_VS |
16288 | #define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0 |
16289 | #define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1 |
16290 | #define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6 |
16291 | #define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7 |
16292 | #define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10 |
16293 | #define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x00000001L |
16294 | #define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x0000003EL |
16295 | #define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x00000040L |
16296 | #define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0x0000FF80L |
16297 | #define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x01FF0000L |
16298 | //SPI_SHADER_PGM_CHKSUM_GS |
16299 | #define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM__SHIFT 0x0 |
16300 | #define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM_MASK 0xFFFFFFFFL |
16301 | //SPI_SHADER_PGM_RSRC4_GS |
16302 | #define SPI_SHADER_PGM_RSRC4_GS__CU_EN__SHIFT 0x0 |
16303 | #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x10 |
16304 | #define SPI_SHADER_PGM_RSRC4_GS__CU_EN_MASK 0x0000FFFFL |
16305 | #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x007F0000L |
16306 | //SPI_SHADER_USER_DATA_ADDR_LO_GS |
16307 | #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0 |
16308 | #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL |
16309 | //SPI_SHADER_USER_DATA_ADDR_HI_GS |
16310 | #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0 |
16311 | #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL |
16312 | //SPI_SHADER_PGM_LO_ES_GS |
16313 | #define SPI_SHADER_PGM_LO_ES_GS__MEM_BASE__SHIFT 0x0 |
16314 | #define SPI_SHADER_PGM_LO_ES_GS__MEM_BASE_MASK 0xFFFFFFFFL |
16315 | //SPI_SHADER_PGM_HI_ES_GS |
16316 | #define SPI_SHADER_PGM_HI_ES_GS__MEM_BASE__SHIFT 0x0 |
16317 | #define SPI_SHADER_PGM_HI_ES_GS__MEM_BASE_MASK 0xFFL |
16318 | //SPI_SHADER_PGM_RSRC3_GS |
16319 | #define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 |
16320 | #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 |
16321 | #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 |
16322 | #define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a |
16323 | #define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL |
16324 | #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L |
16325 | #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L |
16326 | #define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xFC000000L |
16327 | //SPI_SHADER_PGM_LO_GS |
16328 | #define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 |
16329 | #define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL |
16330 | //SPI_SHADER_PGM_HI_GS |
16331 | #define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 |
16332 | #define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL |
16333 | //SPI_SHADER_PGM_RSRC1_GS |
16334 | #define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 |
16335 | #define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 |
16336 | #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa |
16337 | #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc |
16338 | #define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 |
16339 | #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 |
16340 | #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 |
16341 | #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 |
16342 | #define SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED__SHIFT 0x19 |
16343 | #define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS__SHIFT 0x1a |
16344 | #define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE__SHIFT 0x1b |
16345 | #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d |
16346 | #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f |
16347 | #define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL |
16348 | #define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L |
16349 | #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L |
16350 | #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L |
16351 | #define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L |
16352 | #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L |
16353 | #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L |
16354 | #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L |
16355 | #define SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED_MASK 0x02000000L |
16356 | #define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS_MASK 0x04000000L |
16357 | #define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE_MASK 0x08000000L |
16358 | #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L |
16359 | #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L |
16360 | //SPI_SHADER_PGM_RSRC2_GS |
16361 | #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 |
16362 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 |
16363 | #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 |
16364 | #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 |
16365 | #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10 |
16366 | #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12 |
16367 | #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13 |
16368 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1b |
16369 | #define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT__SHIFT 0x1c |
16370 | #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L |
16371 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL |
16372 | #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L |
16373 | #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L |
16374 | #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L |
16375 | #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L |
16376 | #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L |
16377 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x08000000L |
16378 | #define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT_MASK 0xF0000000L |
16379 | //SPI_SHADER_USER_DATA_GS_0 |
16380 | #define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0 |
16381 | #define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xFFFFFFFFL |
16382 | //SPI_SHADER_USER_DATA_GS_1 |
16383 | #define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0 |
16384 | #define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xFFFFFFFFL |
16385 | //SPI_SHADER_USER_DATA_GS_2 |
16386 | #define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0 |
16387 | #define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xFFFFFFFFL |
16388 | //SPI_SHADER_USER_DATA_GS_3 |
16389 | #define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0 |
16390 | #define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xFFFFFFFFL |
16391 | //SPI_SHADER_USER_DATA_GS_4 |
16392 | #define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0 |
16393 | #define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xFFFFFFFFL |
16394 | //SPI_SHADER_USER_DATA_GS_5 |
16395 | #define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0 |
16396 | #define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xFFFFFFFFL |
16397 | //SPI_SHADER_USER_DATA_GS_6 |
16398 | #define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0 |
16399 | #define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xFFFFFFFFL |
16400 | //SPI_SHADER_USER_DATA_GS_7 |
16401 | #define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0 |
16402 | #define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xFFFFFFFFL |
16403 | //SPI_SHADER_USER_DATA_GS_8 |
16404 | #define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0 |
16405 | #define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xFFFFFFFFL |
16406 | //SPI_SHADER_USER_DATA_GS_9 |
16407 | #define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0 |
16408 | #define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xFFFFFFFFL |
16409 | //SPI_SHADER_USER_DATA_GS_10 |
16410 | #define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0 |
16411 | #define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xFFFFFFFFL |
16412 | //SPI_SHADER_USER_DATA_GS_11 |
16413 | #define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0 |
16414 | #define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xFFFFFFFFL |
16415 | //SPI_SHADER_USER_DATA_GS_12 |
16416 | #define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0 |
16417 | #define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xFFFFFFFFL |
16418 | //SPI_SHADER_USER_DATA_GS_13 |
16419 | #define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0 |
16420 | #define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xFFFFFFFFL |
16421 | //SPI_SHADER_USER_DATA_GS_14 |
16422 | #define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0 |
16423 | #define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xFFFFFFFFL |
16424 | //SPI_SHADER_USER_DATA_GS_15 |
16425 | #define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0 |
16426 | #define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xFFFFFFFFL |
16427 | //SPI_SHADER_USER_DATA_GS_16 |
16428 | #define SPI_SHADER_USER_DATA_GS_16__DATA__SHIFT 0x0 |
16429 | #define SPI_SHADER_USER_DATA_GS_16__DATA_MASK 0xFFFFFFFFL |
16430 | //SPI_SHADER_USER_DATA_GS_17 |
16431 | #define SPI_SHADER_USER_DATA_GS_17__DATA__SHIFT 0x0 |
16432 | #define SPI_SHADER_USER_DATA_GS_17__DATA_MASK 0xFFFFFFFFL |
16433 | //SPI_SHADER_USER_DATA_GS_18 |
16434 | #define SPI_SHADER_USER_DATA_GS_18__DATA__SHIFT 0x0 |
16435 | #define SPI_SHADER_USER_DATA_GS_18__DATA_MASK 0xFFFFFFFFL |
16436 | //SPI_SHADER_USER_DATA_GS_19 |
16437 | #define SPI_SHADER_USER_DATA_GS_19__DATA__SHIFT 0x0 |
16438 | #define SPI_SHADER_USER_DATA_GS_19__DATA_MASK 0xFFFFFFFFL |
16439 | //SPI_SHADER_USER_DATA_GS_20 |
16440 | #define SPI_SHADER_USER_DATA_GS_20__DATA__SHIFT 0x0 |
16441 | #define SPI_SHADER_USER_DATA_GS_20__DATA_MASK 0xFFFFFFFFL |
16442 | //SPI_SHADER_USER_DATA_GS_21 |
16443 | #define SPI_SHADER_USER_DATA_GS_21__DATA__SHIFT 0x0 |
16444 | #define SPI_SHADER_USER_DATA_GS_21__DATA_MASK 0xFFFFFFFFL |
16445 | //SPI_SHADER_USER_DATA_GS_22 |
16446 | #define SPI_SHADER_USER_DATA_GS_22__DATA__SHIFT 0x0 |
16447 | #define SPI_SHADER_USER_DATA_GS_22__DATA_MASK 0xFFFFFFFFL |
16448 | //SPI_SHADER_USER_DATA_GS_23 |
16449 | #define SPI_SHADER_USER_DATA_GS_23__DATA__SHIFT 0x0 |
16450 | #define SPI_SHADER_USER_DATA_GS_23__DATA_MASK 0xFFFFFFFFL |
16451 | //SPI_SHADER_USER_DATA_GS_24 |
16452 | #define SPI_SHADER_USER_DATA_GS_24__DATA__SHIFT 0x0 |
16453 | #define SPI_SHADER_USER_DATA_GS_24__DATA_MASK 0xFFFFFFFFL |
16454 | //SPI_SHADER_USER_DATA_GS_25 |
16455 | #define SPI_SHADER_USER_DATA_GS_25__DATA__SHIFT 0x0 |
16456 | #define SPI_SHADER_USER_DATA_GS_25__DATA_MASK 0xFFFFFFFFL |
16457 | //SPI_SHADER_USER_DATA_GS_26 |
16458 | #define SPI_SHADER_USER_DATA_GS_26__DATA__SHIFT 0x0 |
16459 | #define SPI_SHADER_USER_DATA_GS_26__DATA_MASK 0xFFFFFFFFL |
16460 | //SPI_SHADER_USER_DATA_GS_27 |
16461 | #define SPI_SHADER_USER_DATA_GS_27__DATA__SHIFT 0x0 |
16462 | #define SPI_SHADER_USER_DATA_GS_27__DATA_MASK 0xFFFFFFFFL |
16463 | //SPI_SHADER_USER_DATA_GS_28 |
16464 | #define SPI_SHADER_USER_DATA_GS_28__DATA__SHIFT 0x0 |
16465 | #define SPI_SHADER_USER_DATA_GS_28__DATA_MASK 0xFFFFFFFFL |
16466 | //SPI_SHADER_USER_DATA_GS_29 |
16467 | #define SPI_SHADER_USER_DATA_GS_29__DATA__SHIFT 0x0 |
16468 | #define SPI_SHADER_USER_DATA_GS_29__DATA_MASK 0xFFFFFFFFL |
16469 | //SPI_SHADER_USER_DATA_GS_30 |
16470 | #define SPI_SHADER_USER_DATA_GS_30__DATA__SHIFT 0x0 |
16471 | #define SPI_SHADER_USER_DATA_GS_30__DATA_MASK 0xFFFFFFFFL |
16472 | //SPI_SHADER_USER_DATA_GS_31 |
16473 | #define SPI_SHADER_USER_DATA_GS_31__DATA__SHIFT 0x0 |
16474 | #define SPI_SHADER_USER_DATA_GS_31__DATA_MASK 0xFFFFFFFFL |
16475 | //SPI_SHADER_REQ_CTRL_ESGS |
16476 | #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN__SHIFT 0x0 |
16477 | #define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 |
16478 | #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 |
16479 | #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 |
16480 | #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa |
16481 | #define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf |
16482 | #define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN__SHIFT 0x10 |
16483 | #define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 |
16484 | #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN_MASK 0x00000001L |
16485 | #define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL |
16486 | #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L |
16487 | #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L |
16488 | #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L |
16489 | #define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L |
16490 | #define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN_MASK 0x00010000L |
16491 | #define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L |
16492 | //SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS |
16493 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__TOTAL_WAVE_COUNT_HIER_SELECT__SHIFT 0x0 |
16494 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__PER_TYPE_WAVE_COUNT_HIER_SELECT__SHIFT 0x3 |
16495 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__GROUP_UPDATE_EN__SHIFT 0x6 |
16496 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__TOTAL_WAVE_COUNT_COEFFICIENT__SHIFT 0x8 |
16497 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__PER_TYPE_WAVE_COUNT_COEFFICIENT__SHIFT 0x10 |
16498 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__TOTAL_WAVE_COUNT_HIER_SELECT_MASK 0x00000007L |
16499 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__PER_TYPE_WAVE_COUNT_HIER_SELECT_MASK 0x00000038L |
16500 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__GROUP_UPDATE_EN_MASK 0x00000040L |
16501 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__TOTAL_WAVE_COUNT_COEFFICIENT_MASK 0x0000FF00L |
16502 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS__PER_TYPE_WAVE_COUNT_COEFFICIENT_MASK 0x00FF0000L |
16503 | //SPI_SHADER_PREF_PRI_ACCUM_ESGS_0 |
16504 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__CONTRIBUTION__SHIFT 0x0 |
16505 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
16506 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
16507 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__GROUP_UPDATE_EN__SHIFT 0xd |
16508 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__RESERVED__SHIFT 0xe |
16509 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__COEFFICIENT__SHIFT 0xf |
16510 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__CONTRIBUTION_MASK 0x0000007FL |
16511 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
16512 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
16513 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__GROUP_UPDATE_EN_MASK 0x00002000L |
16514 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__RESERVED_MASK 0x00004000L |
16515 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_0__COEFFICIENT_MASK 0x007F8000L |
16516 | //SPI_SHADER_USER_ACCUM_ESGS_0 |
16517 | #define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION__SHIFT 0x0 |
16518 | #define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION_MASK 0x0000007FL |
16519 | //SPI_SHADER_PREF_PRI_ACCUM_ESGS_1 |
16520 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__CONTRIBUTION__SHIFT 0x0 |
16521 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
16522 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
16523 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__GROUP_UPDATE_EN__SHIFT 0xd |
16524 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__RESERVED__SHIFT 0xe |
16525 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__COEFFICIENT__SHIFT 0xf |
16526 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__CONTRIBUTION_MASK 0x0000007FL |
16527 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
16528 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
16529 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__GROUP_UPDATE_EN_MASK 0x00002000L |
16530 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__RESERVED_MASK 0x00004000L |
16531 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_1__COEFFICIENT_MASK 0x007F8000L |
16532 | //SPI_SHADER_USER_ACCUM_ESGS_1 |
16533 | #define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION__SHIFT 0x0 |
16534 | #define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION_MASK 0x0000007FL |
16535 | //SPI_SHADER_PREF_PRI_ACCUM_ESGS_2 |
16536 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__CONTRIBUTION__SHIFT 0x0 |
16537 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
16538 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
16539 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__GROUP_UPDATE_EN__SHIFT 0xd |
16540 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__RESERVED__SHIFT 0xe |
16541 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__COEFFICIENT__SHIFT 0xf |
16542 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__CONTRIBUTION_MASK 0x0000007FL |
16543 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
16544 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
16545 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__GROUP_UPDATE_EN_MASK 0x00002000L |
16546 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__RESERVED_MASK 0x00004000L |
16547 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_2__COEFFICIENT_MASK 0x007F8000L |
16548 | //SPI_SHADER_USER_ACCUM_ESGS_2 |
16549 | #define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION__SHIFT 0x0 |
16550 | #define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION_MASK 0x0000007FL |
16551 | //SPI_SHADER_PREF_PRI_ACCUM_ESGS_3 |
16552 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__CONTRIBUTION__SHIFT 0x0 |
16553 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
16554 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
16555 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__GROUP_UPDATE_EN__SHIFT 0xd |
16556 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__RESERVED__SHIFT 0xe |
16557 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__COEFFICIENT__SHIFT 0xf |
16558 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__CONTRIBUTION_MASK 0x0000007FL |
16559 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
16560 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
16561 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__GROUP_UPDATE_EN_MASK 0x00002000L |
16562 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__RESERVED_MASK 0x00004000L |
16563 | #define SPI_SHADER_PREF_PRI_ACCUM_ESGS_3__COEFFICIENT_MASK 0x007F8000L |
16564 | //SPI_SHADER_USER_ACCUM_ESGS_3 |
16565 | #define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION__SHIFT 0x0 |
16566 | #define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION_MASK 0x0000007FL |
16567 | //SPI_SHADER_PGM_RSRC2_ES_GS |
16568 | #define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0 |
16569 | #define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1 |
16570 | #define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6 |
16571 | #define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7 |
16572 | #define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8 |
16573 | #define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14 |
16574 | #define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x00000001L |
16575 | #define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x0000003EL |
16576 | #define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x00000040L |
16577 | #define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x00000080L |
16578 | #define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x0001FF00L |
16579 | #define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1FF00000L |
16580 | //SPI_SHADER_PGM_RSRC3_ES |
16581 | #define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0 |
16582 | #define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10 |
16583 | #define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16 |
16584 | #define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH__SHIFT 0x1a |
16585 | #define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0x0000FFFFL |
16586 | #define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x003F0000L |
16587 | #define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x03C00000L |
16588 | #define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH_MASK 0xFC000000L |
16589 | //SPI_SHADER_PGM_LO_ES |
16590 | #define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 |
16591 | #define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL |
16592 | //SPI_SHADER_PGM_HI_ES |
16593 | #define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 |
16594 | #define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL |
16595 | //SPI_SHADER_PGM_RSRC1_ES |
16596 | #define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0 |
16597 | #define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6 |
16598 | #define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa |
16599 | #define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc |
16600 | #define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14 |
16601 | #define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15 |
16602 | #define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17 |
16603 | #define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18 |
16604 | #define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a |
16605 | #define SPI_SHADER_PGM_RSRC1_ES__FP16_OVFL__SHIFT 0x1f |
16606 | #define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x0000003FL |
16607 | #define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x000003C0L |
16608 | #define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0x00000C00L |
16609 | #define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0x000FF000L |
16610 | #define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x00100000L |
16611 | #define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x00200000L |
16612 | #define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x00800000L |
16613 | #define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x03000000L |
16614 | #define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x04000000L |
16615 | #define SPI_SHADER_PGM_RSRC1_ES__FP16_OVFL_MASK 0x80000000L |
16616 | //SPI_SHADER_PGM_RSRC2_ES |
16617 | #define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0 |
16618 | #define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1 |
16619 | #define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6 |
16620 | #define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7 |
16621 | #define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8 |
16622 | #define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14 |
16623 | #define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x00000001L |
16624 | #define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x0000003EL |
16625 | #define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x00000040L |
16626 | #define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x00000080L |
16627 | #define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x0001FF00L |
16628 | #define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1FF00000L |
16629 | //SPI_SHADER_USER_DATA_ES_0 |
16630 | #define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 |
16631 | #define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL |
16632 | //SPI_SHADER_USER_DATA_ES_1 |
16633 | #define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 |
16634 | #define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL |
16635 | //SPI_SHADER_USER_DATA_ES_2 |
16636 | #define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 |
16637 | #define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL |
16638 | //SPI_SHADER_USER_DATA_ES_3 |
16639 | #define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 |
16640 | #define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL |
16641 | //SPI_SHADER_USER_DATA_ES_4 |
16642 | #define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 |
16643 | #define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL |
16644 | //SPI_SHADER_USER_DATA_ES_5 |
16645 | #define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 |
16646 | #define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL |
16647 | //SPI_SHADER_USER_DATA_ES_6 |
16648 | #define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 |
16649 | #define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL |
16650 | //SPI_SHADER_USER_DATA_ES_7 |
16651 | #define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 |
16652 | #define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL |
16653 | //SPI_SHADER_USER_DATA_ES_8 |
16654 | #define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 |
16655 | #define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL |
16656 | //SPI_SHADER_USER_DATA_ES_9 |
16657 | #define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 |
16658 | #define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL |
16659 | //SPI_SHADER_USER_DATA_ES_10 |
16660 | #define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 |
16661 | #define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL |
16662 | //SPI_SHADER_USER_DATA_ES_11 |
16663 | #define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 |
16664 | #define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL |
16665 | //SPI_SHADER_USER_DATA_ES_12 |
16666 | #define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 |
16667 | #define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL |
16668 | //SPI_SHADER_USER_DATA_ES_13 |
16669 | #define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 |
16670 | #define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL |
16671 | //SPI_SHADER_USER_DATA_ES_14 |
16672 | #define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 |
16673 | #define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL |
16674 | //SPI_SHADER_USER_DATA_ES_15 |
16675 | #define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 |
16676 | #define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL |
16677 | //SPI_SHADER_PGM_RSRC2_LS_ES |
16678 | #define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0 |
16679 | #define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1 |
16680 | #define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6 |
16681 | #define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7 |
16682 | #define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10 |
16683 | #define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x00000001L |
16684 | #define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x0000003EL |
16685 | #define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x00000040L |
16686 | #define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0x0000FF80L |
16687 | #define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x01FF0000L |
16688 | //SPI_SHADER_PGM_CHKSUM_HS |
16689 | #define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM__SHIFT 0x0 |
16690 | #define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM_MASK 0xFFFFFFFFL |
16691 | //SPI_SHADER_PGM_RSRC4_HS |
16692 | #define SPI_SHADER_PGM_RSRC4_HS__CU_EN__SHIFT 0x0 |
16693 | #define SPI_SHADER_PGM_RSRC4_HS__CU_EN_MASK 0x0000FFFFL |
16694 | //SPI_SHADER_USER_DATA_ADDR_LO_HS |
16695 | #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0 |
16696 | #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL |
16697 | //SPI_SHADER_USER_DATA_ADDR_HI_HS |
16698 | #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0 |
16699 | #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL |
16700 | //SPI_SHADER_PGM_LO_LS_HS |
16701 | #define SPI_SHADER_PGM_LO_LS_HS__MEM_BASE__SHIFT 0x0 |
16702 | #define SPI_SHADER_PGM_LO_LS_HS__MEM_BASE_MASK 0xFFFFFFFFL |
16703 | //SPI_SHADER_PGM_HI_LS_HS |
16704 | #define SPI_SHADER_PGM_HI_LS_HS__MEM_BASE__SHIFT 0x0 |
16705 | #define SPI_SHADER_PGM_HI_LS_HS__MEM_BASE_MASK 0xFFL |
16706 | //SPI_SHADER_PGM_RSRC3_HS |
16707 | #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 |
16708 | #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 |
16709 | #define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa |
16710 | #define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10 |
16711 | #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL |
16712 | #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L |
16713 | #define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0x0000FC00L |
16714 | #define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L |
16715 | //SPI_SHADER_PGM_LO_HS |
16716 | #define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 |
16717 | #define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL |
16718 | //SPI_SHADER_PGM_HI_HS |
16719 | #define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 |
16720 | #define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL |
16721 | //SPI_SHADER_PGM_RSRC1_HS |
16722 | #define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 |
16723 | #define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 |
16724 | #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa |
16725 | #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc |
16726 | #define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 |
16727 | #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 |
16728 | #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 |
16729 | #define SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED__SHIFT 0x18 |
16730 | #define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS__SHIFT 0x19 |
16731 | #define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE__SHIFT 0x1a |
16732 | #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c |
16733 | #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e |
16734 | #define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL |
16735 | #define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L |
16736 | #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L |
16737 | #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L |
16738 | #define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L |
16739 | #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L |
16740 | #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L |
16741 | #define SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED_MASK 0x01000000L |
16742 | #define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS_MASK 0x02000000L |
16743 | #define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE_MASK 0x04000000L |
16744 | #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L |
16745 | #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L |
16746 | //SPI_SHADER_PGM_RSRC2_HS |
16747 | #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 |
16748 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 |
16749 | #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 |
16750 | #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7 |
16751 | #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8 |
16752 | #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9 |
16753 | #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x12 |
16754 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1b |
16755 | #define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT__SHIFT 0x1c |
16756 | #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L |
16757 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL |
16758 | #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L |
16759 | #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x00000080L |
16760 | #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x00000100L |
16761 | #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0003FE00L |
16762 | #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x07FC0000L |
16763 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x08000000L |
16764 | #define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT_MASK 0xF0000000L |
16765 | //SPI_SHADER_USER_DATA_HS_0 |
16766 | #define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0 |
16767 | #define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xFFFFFFFFL |
16768 | //SPI_SHADER_USER_DATA_HS_1 |
16769 | #define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0 |
16770 | #define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xFFFFFFFFL |
16771 | //SPI_SHADER_USER_DATA_HS_2 |
16772 | #define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0 |
16773 | #define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xFFFFFFFFL |
16774 | //SPI_SHADER_USER_DATA_HS_3 |
16775 | #define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0 |
16776 | #define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xFFFFFFFFL |
16777 | //SPI_SHADER_USER_DATA_HS_4 |
16778 | #define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0 |
16779 | #define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xFFFFFFFFL |
16780 | //SPI_SHADER_USER_DATA_HS_5 |
16781 | #define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0 |
16782 | #define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xFFFFFFFFL |
16783 | //SPI_SHADER_USER_DATA_HS_6 |
16784 | #define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0 |
16785 | #define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xFFFFFFFFL |
16786 | //SPI_SHADER_USER_DATA_HS_7 |
16787 | #define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0 |
16788 | #define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xFFFFFFFFL |
16789 | //SPI_SHADER_USER_DATA_HS_8 |
16790 | #define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0 |
16791 | #define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xFFFFFFFFL |
16792 | //SPI_SHADER_USER_DATA_HS_9 |
16793 | #define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0 |
16794 | #define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xFFFFFFFFL |
16795 | //SPI_SHADER_USER_DATA_HS_10 |
16796 | #define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0 |
16797 | #define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xFFFFFFFFL |
16798 | //SPI_SHADER_USER_DATA_HS_11 |
16799 | #define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0 |
16800 | #define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xFFFFFFFFL |
16801 | //SPI_SHADER_USER_DATA_HS_12 |
16802 | #define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0 |
16803 | #define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xFFFFFFFFL |
16804 | //SPI_SHADER_USER_DATA_HS_13 |
16805 | #define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0 |
16806 | #define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xFFFFFFFFL |
16807 | //SPI_SHADER_USER_DATA_HS_14 |
16808 | #define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0 |
16809 | #define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xFFFFFFFFL |
16810 | //SPI_SHADER_USER_DATA_HS_15 |
16811 | #define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0 |
16812 | #define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xFFFFFFFFL |
16813 | //SPI_SHADER_USER_DATA_HS_16 |
16814 | #define SPI_SHADER_USER_DATA_HS_16__DATA__SHIFT 0x0 |
16815 | #define SPI_SHADER_USER_DATA_HS_16__DATA_MASK 0xFFFFFFFFL |
16816 | //SPI_SHADER_USER_DATA_HS_17 |
16817 | #define SPI_SHADER_USER_DATA_HS_17__DATA__SHIFT 0x0 |
16818 | #define SPI_SHADER_USER_DATA_HS_17__DATA_MASK 0xFFFFFFFFL |
16819 | //SPI_SHADER_USER_DATA_HS_18 |
16820 | #define SPI_SHADER_USER_DATA_HS_18__DATA__SHIFT 0x0 |
16821 | #define SPI_SHADER_USER_DATA_HS_18__DATA_MASK 0xFFFFFFFFL |
16822 | //SPI_SHADER_USER_DATA_HS_19 |
16823 | #define SPI_SHADER_USER_DATA_HS_19__DATA__SHIFT 0x0 |
16824 | #define SPI_SHADER_USER_DATA_HS_19__DATA_MASK 0xFFFFFFFFL |
16825 | //SPI_SHADER_USER_DATA_HS_20 |
16826 | #define SPI_SHADER_USER_DATA_HS_20__DATA__SHIFT 0x0 |
16827 | #define SPI_SHADER_USER_DATA_HS_20__DATA_MASK 0xFFFFFFFFL |
16828 | //SPI_SHADER_USER_DATA_HS_21 |
16829 | #define SPI_SHADER_USER_DATA_HS_21__DATA__SHIFT 0x0 |
16830 | #define SPI_SHADER_USER_DATA_HS_21__DATA_MASK 0xFFFFFFFFL |
16831 | //SPI_SHADER_USER_DATA_HS_22 |
16832 | #define SPI_SHADER_USER_DATA_HS_22__DATA__SHIFT 0x0 |
16833 | #define SPI_SHADER_USER_DATA_HS_22__DATA_MASK 0xFFFFFFFFL |
16834 | //SPI_SHADER_USER_DATA_HS_23 |
16835 | #define SPI_SHADER_USER_DATA_HS_23__DATA__SHIFT 0x0 |
16836 | #define SPI_SHADER_USER_DATA_HS_23__DATA_MASK 0xFFFFFFFFL |
16837 | //SPI_SHADER_USER_DATA_HS_24 |
16838 | #define SPI_SHADER_USER_DATA_HS_24__DATA__SHIFT 0x0 |
16839 | #define SPI_SHADER_USER_DATA_HS_24__DATA_MASK 0xFFFFFFFFL |
16840 | //SPI_SHADER_USER_DATA_HS_25 |
16841 | #define SPI_SHADER_USER_DATA_HS_25__DATA__SHIFT 0x0 |
16842 | #define SPI_SHADER_USER_DATA_HS_25__DATA_MASK 0xFFFFFFFFL |
16843 | //SPI_SHADER_USER_DATA_HS_26 |
16844 | #define SPI_SHADER_USER_DATA_HS_26__DATA__SHIFT 0x0 |
16845 | #define SPI_SHADER_USER_DATA_HS_26__DATA_MASK 0xFFFFFFFFL |
16846 | //SPI_SHADER_USER_DATA_HS_27 |
16847 | #define SPI_SHADER_USER_DATA_HS_27__DATA__SHIFT 0x0 |
16848 | #define SPI_SHADER_USER_DATA_HS_27__DATA_MASK 0xFFFFFFFFL |
16849 | //SPI_SHADER_USER_DATA_HS_28 |
16850 | #define SPI_SHADER_USER_DATA_HS_28__DATA__SHIFT 0x0 |
16851 | #define SPI_SHADER_USER_DATA_HS_28__DATA_MASK 0xFFFFFFFFL |
16852 | //SPI_SHADER_USER_DATA_HS_29 |
16853 | #define SPI_SHADER_USER_DATA_HS_29__DATA__SHIFT 0x0 |
16854 | #define SPI_SHADER_USER_DATA_HS_29__DATA_MASK 0xFFFFFFFFL |
16855 | //SPI_SHADER_USER_DATA_HS_30 |
16856 | #define SPI_SHADER_USER_DATA_HS_30__DATA__SHIFT 0x0 |
16857 | #define SPI_SHADER_USER_DATA_HS_30__DATA_MASK 0xFFFFFFFFL |
16858 | //SPI_SHADER_USER_DATA_HS_31 |
16859 | #define SPI_SHADER_USER_DATA_HS_31__DATA__SHIFT 0x0 |
16860 | #define SPI_SHADER_USER_DATA_HS_31__DATA_MASK 0xFFFFFFFFL |
16861 | //SPI_SHADER_REQ_CTRL_LSHS |
16862 | #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN__SHIFT 0x0 |
16863 | #define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 |
16864 | #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 |
16865 | #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 |
16866 | #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa |
16867 | #define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf |
16868 | #define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN__SHIFT 0x10 |
16869 | #define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 |
16870 | #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN_MASK 0x00000001L |
16871 | #define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL |
16872 | #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L |
16873 | #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L |
16874 | #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L |
16875 | #define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L |
16876 | #define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN_MASK 0x00010000L |
16877 | #define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L |
16878 | //SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS |
16879 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__TOTAL_WAVE_COUNT_HIER_SELECT__SHIFT 0x0 |
16880 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__PER_TYPE_WAVE_COUNT_HIER_SELECT__SHIFT 0x3 |
16881 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__GROUP_UPDATE_EN__SHIFT 0x6 |
16882 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__TOTAL_WAVE_COUNT_COEFFICIENT__SHIFT 0x8 |
16883 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__PER_TYPE_WAVE_COUNT_COEFFICIENT__SHIFT 0x10 |
16884 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__TOTAL_WAVE_COUNT_HIER_SELECT_MASK 0x00000007L |
16885 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__PER_TYPE_WAVE_COUNT_HIER_SELECT_MASK 0x00000038L |
16886 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__GROUP_UPDATE_EN_MASK 0x00000040L |
16887 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__TOTAL_WAVE_COUNT_COEFFICIENT_MASK 0x0000FF00L |
16888 | #define SPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS__PER_TYPE_WAVE_COUNT_COEFFICIENT_MASK 0x00FF0000L |
16889 | //SPI_SHADER_PREF_PRI_ACCUM_LSHS_0 |
16890 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__CONTRIBUTION__SHIFT 0x0 |
16891 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
16892 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
16893 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__GROUP_UPDATE_EN__SHIFT 0xd |
16894 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__RESERVED__SHIFT 0xe |
16895 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__COEFFICIENT__SHIFT 0xf |
16896 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__CONTRIBUTION_MASK 0x0000007FL |
16897 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
16898 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
16899 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__GROUP_UPDATE_EN_MASK 0x00002000L |
16900 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__RESERVED_MASK 0x00004000L |
16901 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_0__COEFFICIENT_MASK 0x007F8000L |
16902 | //SPI_SHADER_USER_ACCUM_LSHS_0 |
16903 | #define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION__SHIFT 0x0 |
16904 | #define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION_MASK 0x0000007FL |
16905 | //SPI_SHADER_PREF_PRI_ACCUM_LSHS_1 |
16906 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__CONTRIBUTION__SHIFT 0x0 |
16907 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
16908 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
16909 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__GROUP_UPDATE_EN__SHIFT 0xd |
16910 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__RESERVED__SHIFT 0xe |
16911 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__COEFFICIENT__SHIFT 0xf |
16912 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__CONTRIBUTION_MASK 0x0000007FL |
16913 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
16914 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
16915 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__GROUP_UPDATE_EN_MASK 0x00002000L |
16916 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__RESERVED_MASK 0x00004000L |
16917 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_1__COEFFICIENT_MASK 0x007F8000L |
16918 | //SPI_SHADER_USER_ACCUM_LSHS_1 |
16919 | #define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION__SHIFT 0x0 |
16920 | #define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION_MASK 0x0000007FL |
16921 | //SPI_SHADER_PREF_PRI_ACCUM_LSHS_2 |
16922 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__CONTRIBUTION__SHIFT 0x0 |
16923 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
16924 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
16925 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__GROUP_UPDATE_EN__SHIFT 0xd |
16926 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__RESERVED__SHIFT 0xe |
16927 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__COEFFICIENT__SHIFT 0xf |
16928 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__CONTRIBUTION_MASK 0x0000007FL |
16929 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
16930 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
16931 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__GROUP_UPDATE_EN_MASK 0x00002000L |
16932 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__RESERVED_MASK 0x00004000L |
16933 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_2__COEFFICIENT_MASK 0x007F8000L |
16934 | //SPI_SHADER_USER_ACCUM_LSHS_2 |
16935 | #define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION__SHIFT 0x0 |
16936 | #define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION_MASK 0x0000007FL |
16937 | //SPI_SHADER_PREF_PRI_ACCUM_LSHS_3 |
16938 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__CONTRIBUTION__SHIFT 0x0 |
16939 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
16940 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
16941 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__GROUP_UPDATE_EN__SHIFT 0xd |
16942 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__RESERVED__SHIFT 0xe |
16943 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__COEFFICIENT__SHIFT 0xf |
16944 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__CONTRIBUTION_MASK 0x0000007FL |
16945 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
16946 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
16947 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__GROUP_UPDATE_EN_MASK 0x00002000L |
16948 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__RESERVED_MASK 0x00004000L |
16949 | #define SPI_SHADER_PREF_PRI_ACCUM_LSHS_3__COEFFICIENT_MASK 0x007F8000L |
16950 | //SPI_SHADER_USER_ACCUM_LSHS_3 |
16951 | #define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION__SHIFT 0x0 |
16952 | #define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION_MASK 0x0000007FL |
16953 | //SPI_SHADER_PGM_RSRC2_LS_HS |
16954 | #define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0 |
16955 | #define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1 |
16956 | #define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6 |
16957 | #define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7 |
16958 | #define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10 |
16959 | #define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x00000001L |
16960 | #define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x0000003EL |
16961 | #define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x00000040L |
16962 | #define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0x0000FF80L |
16963 | #define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x01FF0000L |
16964 | //SPI_SHADER_PGM_RSRC3_LS |
16965 | #define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0 |
16966 | #define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10 |
16967 | #define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16 |
16968 | #define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH__SHIFT 0x1a |
16969 | #define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0x0000FFFFL |
16970 | #define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x003F0000L |
16971 | #define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L |
16972 | #define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH_MASK 0xFC000000L |
16973 | //SPI_SHADER_PGM_LO_LS |
16974 | #define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 |
16975 | #define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL |
16976 | //SPI_SHADER_PGM_HI_LS |
16977 | #define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 |
16978 | #define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL |
16979 | //SPI_SHADER_PGM_RSRC1_LS |
16980 | #define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0 |
16981 | #define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6 |
16982 | #define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa |
16983 | #define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc |
16984 | #define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14 |
16985 | #define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15 |
16986 | #define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17 |
16987 | #define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18 |
16988 | #define SPI_SHADER_PGM_RSRC1_LS__FP16_OVFL__SHIFT 0x1e |
16989 | #define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x0000003FL |
16990 | #define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x000003C0L |
16991 | #define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0x00000C00L |
16992 | #define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0x000FF000L |
16993 | #define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x00100000L |
16994 | #define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x00200000L |
16995 | #define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x00800000L |
16996 | #define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x03000000L |
16997 | #define SPI_SHADER_PGM_RSRC1_LS__FP16_OVFL_MASK 0x40000000L |
16998 | //SPI_SHADER_PGM_RSRC2_LS |
16999 | #define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0 |
17000 | #define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1 |
17001 | #define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6 |
17002 | #define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7 |
17003 | #define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10 |
17004 | #define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x00000001L |
17005 | #define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x0000003EL |
17006 | #define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x00000040L |
17007 | #define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0x0000FF80L |
17008 | #define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x01FF0000L |
17009 | //SPI_SHADER_USER_DATA_LS_0 |
17010 | #define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 |
17011 | #define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL |
17012 | //SPI_SHADER_USER_DATA_LS_1 |
17013 | #define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 |
17014 | #define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL |
17015 | //SPI_SHADER_USER_DATA_LS_2 |
17016 | #define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 |
17017 | #define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL |
17018 | //SPI_SHADER_USER_DATA_LS_3 |
17019 | #define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 |
17020 | #define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL |
17021 | //SPI_SHADER_USER_DATA_LS_4 |
17022 | #define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 |
17023 | #define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL |
17024 | //SPI_SHADER_USER_DATA_LS_5 |
17025 | #define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 |
17026 | #define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL |
17027 | //SPI_SHADER_USER_DATA_LS_6 |
17028 | #define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 |
17029 | #define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL |
17030 | //SPI_SHADER_USER_DATA_LS_7 |
17031 | #define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 |
17032 | #define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL |
17033 | //SPI_SHADER_USER_DATA_LS_8 |
17034 | #define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 |
17035 | #define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL |
17036 | //SPI_SHADER_USER_DATA_LS_9 |
17037 | #define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 |
17038 | #define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL |
17039 | //SPI_SHADER_USER_DATA_LS_10 |
17040 | #define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 |
17041 | #define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL |
17042 | //SPI_SHADER_USER_DATA_LS_11 |
17043 | #define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 |
17044 | #define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL |
17045 | //SPI_SHADER_USER_DATA_LS_12 |
17046 | #define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 |
17047 | #define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL |
17048 | //SPI_SHADER_USER_DATA_LS_13 |
17049 | #define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 |
17050 | #define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL |
17051 | //SPI_SHADER_USER_DATA_LS_14 |
17052 | #define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 |
17053 | #define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL |
17054 | //SPI_SHADER_USER_DATA_LS_15 |
17055 | #define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 |
17056 | #define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL |
17057 | //COMPUTE_DISPATCH_INITIATOR |
17058 | #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 |
17059 | #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 |
17060 | #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 |
17061 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 |
17062 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 |
17063 | #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 |
17064 | #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 |
17065 | #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa |
17066 | #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb |
17067 | #define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc |
17068 | #define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE__SHIFT 0xd |
17069 | #define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe |
17070 | #define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN__SHIFT 0xf |
17071 | #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L |
17072 | #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L |
17073 | #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L |
17074 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L |
17075 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L |
17076 | #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L |
17077 | #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L |
17078 | #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L |
17079 | #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L |
17080 | #define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L |
17081 | #define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE_MASK 0x00002000L |
17082 | #define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L |
17083 | #define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN_MASK 0x00008000L |
17084 | //COMPUTE_DIM_X |
17085 | #define COMPUTE_DIM_X__SIZE__SHIFT 0x0 |
17086 | #define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL |
17087 | //COMPUTE_DIM_Y |
17088 | #define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 |
17089 | #define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL |
17090 | //COMPUTE_DIM_Z |
17091 | #define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 |
17092 | #define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL |
17093 | //COMPUTE_START_X |
17094 | #define COMPUTE_START_X__START__SHIFT 0x0 |
17095 | #define COMPUTE_START_X__START_MASK 0xFFFFFFFFL |
17096 | //COMPUTE_START_Y |
17097 | #define COMPUTE_START_Y__START__SHIFT 0x0 |
17098 | #define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL |
17099 | //COMPUTE_START_Z |
17100 | #define COMPUTE_START_Z__START__SHIFT 0x0 |
17101 | #define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL |
17102 | //COMPUTE_NUM_THREAD_X |
17103 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 |
17104 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 |
17105 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL |
17106 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L |
17107 | //COMPUTE_NUM_THREAD_Y |
17108 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 |
17109 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 |
17110 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL |
17111 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L |
17112 | //COMPUTE_NUM_THREAD_Z |
17113 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 |
17114 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 |
17115 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL |
17116 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L |
17117 | //COMPUTE_PIPELINESTAT_ENABLE |
17118 | #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 |
17119 | #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L |
17120 | //COMPUTE_PERFCOUNT_ENABLE |
17121 | #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 |
17122 | #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L |
17123 | //COMPUTE_PGM_LO |
17124 | #define COMPUTE_PGM_LO__DATA__SHIFT 0x0 |
17125 | #define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL |
17126 | //COMPUTE_PGM_HI |
17127 | #define COMPUTE_PGM_HI__DATA__SHIFT 0x0 |
17128 | #define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL |
17129 | //COMPUTE_DISPATCH_PKT_ADDR_LO |
17130 | #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 |
17131 | #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL |
17132 | //COMPUTE_DISPATCH_PKT_ADDR_HI |
17133 | #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 |
17134 | #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL |
17135 | //COMPUTE_DISPATCH_SCRATCH_BASE_LO |
17136 | #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 |
17137 | #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL |
17138 | //COMPUTE_DISPATCH_SCRATCH_BASE_HI |
17139 | #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 |
17140 | #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL |
17141 | //COMPUTE_PGM_RSRC1 |
17142 | #define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 |
17143 | #define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 |
17144 | #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa |
17145 | #define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc |
17146 | #define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 |
17147 | #define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 |
17148 | #define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 |
17149 | #define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 |
17150 | #define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a |
17151 | #define COMPUTE_PGM_RSRC1__WGP_MODE__SHIFT 0x1d |
17152 | #define COMPUTE_PGM_RSRC1__MEM_ORDERED__SHIFT 0x1e |
17153 | #define COMPUTE_PGM_RSRC1__FWD_PROGRESS__SHIFT 0x1f |
17154 | #define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL |
17155 | #define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L |
17156 | #define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L |
17157 | #define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L |
17158 | #define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L |
17159 | #define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L |
17160 | #define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L |
17161 | #define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L |
17162 | #define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L |
17163 | #define COMPUTE_PGM_RSRC1__WGP_MODE_MASK 0x20000000L |
17164 | #define COMPUTE_PGM_RSRC1__MEM_ORDERED_MASK 0x40000000L |
17165 | #define COMPUTE_PGM_RSRC1__FWD_PROGRESS_MASK 0x80000000L |
17166 | //COMPUTE_PGM_RSRC2 |
17167 | #define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 |
17168 | #define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 |
17169 | #define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 |
17170 | #define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 |
17171 | #define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 |
17172 | #define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 |
17173 | #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa |
17174 | #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb |
17175 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd |
17176 | #define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf |
17177 | #define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 |
17178 | #define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L |
17179 | #define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL |
17180 | #define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L |
17181 | #define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L |
17182 | #define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L |
17183 | #define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L |
17184 | #define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L |
17185 | #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L |
17186 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L |
17187 | #define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L |
17188 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L |
17189 | //COMPUTE_VMID |
17190 | #define COMPUTE_VMID__DATA__SHIFT 0x0 |
17191 | #define COMPUTE_VMID__DATA_MASK 0x0000000FL |
17192 | //COMPUTE_RESOURCE_LIMITS |
17193 | #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 |
17194 | #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc |
17195 | #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 |
17196 | #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 |
17197 | #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 |
17198 | #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 |
17199 | #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL |
17200 | #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L |
17201 | #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L |
17202 | #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L |
17203 | #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L |
17204 | #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L |
17205 | //COMPUTE_DESTINATION_EN_SE0 |
17206 | #define COMPUTE_DESTINATION_EN_SE0__CU_EN__SHIFT 0x0 |
17207 | #define COMPUTE_DESTINATION_EN_SE0__CU_EN_MASK 0xFFFFFFFFL |
17208 | //COMPUTE_STATIC_THREAD_MGMT_SE0 |
17209 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN__SHIFT 0x0 |
17210 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN__SHIFT 0x10 |
17211 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN_MASK 0x0000FFFFL |
17212 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN_MASK 0xFFFF0000L |
17213 | //COMPUTE_DESTINATION_EN_SE1 |
17214 | #define COMPUTE_DESTINATION_EN_SE1__CU_EN__SHIFT 0x0 |
17215 | #define COMPUTE_DESTINATION_EN_SE1__CU_EN_MASK 0xFFFFFFFFL |
17216 | //COMPUTE_STATIC_THREAD_MGMT_SE1 |
17217 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN__SHIFT 0x0 |
17218 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN__SHIFT 0x10 |
17219 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN_MASK 0x0000FFFFL |
17220 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN_MASK 0xFFFF0000L |
17221 | //COMPUTE_TMPRING_SIZE |
17222 | #define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 |
17223 | #define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc |
17224 | #define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL |
17225 | #define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L |
17226 | //COMPUTE_DESTINATION_EN_SE2 |
17227 | #define COMPUTE_DESTINATION_EN_SE2__CU_EN__SHIFT 0x0 |
17228 | #define COMPUTE_DESTINATION_EN_SE2__CU_EN_MASK 0xFFFFFFFFL |
17229 | //COMPUTE_STATIC_THREAD_MGMT_SE2 |
17230 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN__SHIFT 0x0 |
17231 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN__SHIFT 0x10 |
17232 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN_MASK 0x0000FFFFL |
17233 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN_MASK 0xFFFF0000L |
17234 | //COMPUTE_DESTINATION_EN_SE3 |
17235 | #define COMPUTE_DESTINATION_EN_SE3__CU_EN__SHIFT 0x0 |
17236 | #define COMPUTE_DESTINATION_EN_SE3__CU_EN_MASK 0xFFFFFFFFL |
17237 | //COMPUTE_STATIC_THREAD_MGMT_SE3 |
17238 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN__SHIFT 0x0 |
17239 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN__SHIFT 0x10 |
17240 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN_MASK 0x0000FFFFL |
17241 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN_MASK 0xFFFF0000L |
17242 | //COMPUTE_RESTART_X |
17243 | #define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 |
17244 | #define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL |
17245 | //COMPUTE_RESTART_Y |
17246 | #define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 |
17247 | #define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL |
17248 | //COMPUTE_RESTART_Z |
17249 | #define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 |
17250 | #define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL |
17251 | //COMPUTE_THREAD_TRACE_ENABLE |
17252 | #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 |
17253 | #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L |
17254 | //COMPUTE_MISC_RESERVED |
17255 | #define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 |
17256 | #define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2 |
17257 | #define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 |
17258 | #define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 |
17259 | #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 |
17260 | #define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L |
17261 | #define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x00000004L |
17262 | #define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L |
17263 | #define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L |
17264 | #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L |
17265 | //COMPUTE_DISPATCH_ID |
17266 | #define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 |
17267 | #define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL |
17268 | //COMPUTE_THREADGROUP_ID |
17269 | #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 |
17270 | #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL |
17271 | //COMPUTE_REQ_CTRL |
17272 | #define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN__SHIFT 0x0 |
17273 | #define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 |
17274 | #define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 |
17275 | #define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS__SHIFT 0x9 |
17276 | #define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa |
17277 | #define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf |
17278 | #define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN__SHIFT 0x10 |
17279 | #define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 |
17280 | #define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT__SHIFT 0x14 |
17281 | #define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN_MASK 0x00000001L |
17282 | #define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL |
17283 | #define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L |
17284 | #define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS_MASK 0x00000200L |
17285 | #define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L |
17286 | #define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L |
17287 | #define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN_MASK 0x00010000L |
17288 | #define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L |
17289 | #define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT_MASK 0x07F00000L |
17290 | //COMPUTE_PREF_PRI_ACCUM_0 |
17291 | #define COMPUTE_PREF_PRI_ACCUM_0__CONTRIBUTION__SHIFT 0x0 |
17292 | #define COMPUTE_PREF_PRI_ACCUM_0__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
17293 | #define COMPUTE_PREF_PRI_ACCUM_0__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
17294 | #define COMPUTE_PREF_PRI_ACCUM_0__GROUP_UPDATE_EN__SHIFT 0xd |
17295 | #define COMPUTE_PREF_PRI_ACCUM_0__RESERVED__SHIFT 0xe |
17296 | #define COMPUTE_PREF_PRI_ACCUM_0__COEFFICIENT__SHIFT 0xf |
17297 | #define COMPUTE_PREF_PRI_ACCUM_0__CONTRIBUTION_MASK 0x0000007FL |
17298 | #define COMPUTE_PREF_PRI_ACCUM_0__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
17299 | #define COMPUTE_PREF_PRI_ACCUM_0__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
17300 | #define COMPUTE_PREF_PRI_ACCUM_0__GROUP_UPDATE_EN_MASK 0x00002000L |
17301 | #define COMPUTE_PREF_PRI_ACCUM_0__RESERVED_MASK 0x00004000L |
17302 | #define COMPUTE_PREF_PRI_ACCUM_0__COEFFICIENT_MASK 0x007F8000L |
17303 | //COMPUTE_USER_ACCUM_0 |
17304 | #define COMPUTE_USER_ACCUM_0__CONTRIBUTION__SHIFT 0x0 |
17305 | #define COMPUTE_USER_ACCUM_0__CONTRIBUTION_MASK 0x0000007FL |
17306 | //COMPUTE_PREF_PRI_ACCUM_1 |
17307 | #define COMPUTE_PREF_PRI_ACCUM_1__CONTRIBUTION__SHIFT 0x0 |
17308 | #define COMPUTE_PREF_PRI_ACCUM_1__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
17309 | #define COMPUTE_PREF_PRI_ACCUM_1__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
17310 | #define COMPUTE_PREF_PRI_ACCUM_1__GROUP_UPDATE_EN__SHIFT 0xd |
17311 | #define COMPUTE_PREF_PRI_ACCUM_1__RESERVED__SHIFT 0xe |
17312 | #define COMPUTE_PREF_PRI_ACCUM_1__COEFFICIENT__SHIFT 0xf |
17313 | #define COMPUTE_PREF_PRI_ACCUM_1__CONTRIBUTION_MASK 0x0000007FL |
17314 | #define COMPUTE_PREF_PRI_ACCUM_1__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
17315 | #define COMPUTE_PREF_PRI_ACCUM_1__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
17316 | #define COMPUTE_PREF_PRI_ACCUM_1__GROUP_UPDATE_EN_MASK 0x00002000L |
17317 | #define COMPUTE_PREF_PRI_ACCUM_1__RESERVED_MASK 0x00004000L |
17318 | #define COMPUTE_PREF_PRI_ACCUM_1__COEFFICIENT_MASK 0x007F8000L |
17319 | //COMPUTE_USER_ACCUM_1 |
17320 | #define COMPUTE_USER_ACCUM_1__CONTRIBUTION__SHIFT 0x0 |
17321 | #define COMPUTE_USER_ACCUM_1__CONTRIBUTION_MASK 0x0000007FL |
17322 | //COMPUTE_PREF_PRI_ACCUM_2 |
17323 | #define COMPUTE_PREF_PRI_ACCUM_2__CONTRIBUTION__SHIFT 0x0 |
17324 | #define COMPUTE_PREF_PRI_ACCUM_2__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
17325 | #define COMPUTE_PREF_PRI_ACCUM_2__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
17326 | #define COMPUTE_PREF_PRI_ACCUM_2__GROUP_UPDATE_EN__SHIFT 0xd |
17327 | #define COMPUTE_PREF_PRI_ACCUM_2__RESERVED__SHIFT 0xe |
17328 | #define COMPUTE_PREF_PRI_ACCUM_2__COEFFICIENT__SHIFT 0xf |
17329 | #define COMPUTE_PREF_PRI_ACCUM_2__CONTRIBUTION_MASK 0x0000007FL |
17330 | #define COMPUTE_PREF_PRI_ACCUM_2__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
17331 | #define COMPUTE_PREF_PRI_ACCUM_2__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
17332 | #define COMPUTE_PREF_PRI_ACCUM_2__GROUP_UPDATE_EN_MASK 0x00002000L |
17333 | #define COMPUTE_PREF_PRI_ACCUM_2__RESERVED_MASK 0x00004000L |
17334 | #define COMPUTE_PREF_PRI_ACCUM_2__COEFFICIENT_MASK 0x007F8000L |
17335 | //COMPUTE_USER_ACCUM_2 |
17336 | #define COMPUTE_USER_ACCUM_2__CONTRIBUTION__SHIFT 0x0 |
17337 | #define COMPUTE_USER_ACCUM_2__CONTRIBUTION_MASK 0x0000007FL |
17338 | //COMPUTE_PREF_PRI_ACCUM_3 |
17339 | #define COMPUTE_PREF_PRI_ACCUM_3__CONTRIBUTION__SHIFT 0x0 |
17340 | #define COMPUTE_PREF_PRI_ACCUM_3__COEFFICIENT_HIER_SELECT__SHIFT 0x7 |
17341 | #define COMPUTE_PREF_PRI_ACCUM_3__CONTRIBUTION_HIER_SELECT__SHIFT 0xa |
17342 | #define COMPUTE_PREF_PRI_ACCUM_3__GROUP_UPDATE_EN__SHIFT 0xd |
17343 | #define COMPUTE_PREF_PRI_ACCUM_3__RESERVED__SHIFT 0xe |
17344 | #define COMPUTE_PREF_PRI_ACCUM_3__COEFFICIENT__SHIFT 0xf |
17345 | #define COMPUTE_PREF_PRI_ACCUM_3__CONTRIBUTION_MASK 0x0000007FL |
17346 | #define COMPUTE_PREF_PRI_ACCUM_3__COEFFICIENT_HIER_SELECT_MASK 0x00000380L |
17347 | #define COMPUTE_PREF_PRI_ACCUM_3__CONTRIBUTION_HIER_SELECT_MASK 0x00001C00L |
17348 | #define COMPUTE_PREF_PRI_ACCUM_3__GROUP_UPDATE_EN_MASK 0x00002000L |
17349 | #define COMPUTE_PREF_PRI_ACCUM_3__RESERVED_MASK 0x00004000L |
17350 | #define COMPUTE_PREF_PRI_ACCUM_3__COEFFICIENT_MASK 0x007F8000L |
17351 | //COMPUTE_USER_ACCUM_3 |
17352 | #define COMPUTE_USER_ACCUM_3__CONTRIBUTION__SHIFT 0x0 |
17353 | #define COMPUTE_USER_ACCUM_3__CONTRIBUTION_MASK 0x0000007FL |
17354 | //COMPUTE_PGM_RSRC3 |
17355 | #define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT__SHIFT 0x0 |
17356 | #define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT_MASK 0x0000000FL |
17357 | //COMPUTE_DDID_INDEX |
17358 | #define COMPUTE_DDID_INDEX__INDEX__SHIFT 0x0 |
17359 | #define COMPUTE_DDID_INDEX__INDEX_MASK 0x000007FFL |
17360 | //COMPUTE_SHADER_CHKSUM |
17361 | #define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0 |
17362 | #define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL |
17363 | //COMPUTE_RELAUNCH |
17364 | #define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 |
17365 | #define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e |
17366 | #define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f |
17367 | #define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL |
17368 | #define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L |
17369 | #define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L |
17370 | //COMPUTE_WAVE_RESTORE_ADDR_LO |
17371 | #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 |
17372 | #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL |
17373 | //COMPUTE_WAVE_RESTORE_ADDR_HI |
17374 | #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 |
17375 | #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL |
17376 | //COMPUTE_RELAUNCH2 |
17377 | #define COMPUTE_RELAUNCH2__PAYLOAD__SHIFT 0x0 |
17378 | #define COMPUTE_RELAUNCH2__IS_EVENT__SHIFT 0x1e |
17379 | #define COMPUTE_RELAUNCH2__IS_STATE__SHIFT 0x1f |
17380 | #define COMPUTE_RELAUNCH2__PAYLOAD_MASK 0x3FFFFFFFL |
17381 | #define COMPUTE_RELAUNCH2__IS_EVENT_MASK 0x40000000L |
17382 | #define COMPUTE_RELAUNCH2__IS_STATE_MASK 0x80000000L |
17383 | //COMPUTE_USER_DATA_0 |
17384 | #define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 |
17385 | #define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL |
17386 | //COMPUTE_USER_DATA_1 |
17387 | #define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 |
17388 | #define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL |
17389 | //COMPUTE_USER_DATA_2 |
17390 | #define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 |
17391 | #define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL |
17392 | //COMPUTE_USER_DATA_3 |
17393 | #define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 |
17394 | #define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL |
17395 | //COMPUTE_USER_DATA_4 |
17396 | #define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 |
17397 | #define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL |
17398 | //COMPUTE_USER_DATA_5 |
17399 | #define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 |
17400 | #define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL |
17401 | //COMPUTE_USER_DATA_6 |
17402 | #define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 |
17403 | #define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL |
17404 | //COMPUTE_USER_DATA_7 |
17405 | #define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 |
17406 | #define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL |
17407 | //COMPUTE_USER_DATA_8 |
17408 | #define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 |
17409 | #define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL |
17410 | //COMPUTE_USER_DATA_9 |
17411 | #define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 |
17412 | #define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL |
17413 | //COMPUTE_USER_DATA_10 |
17414 | #define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 |
17415 | #define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL |
17416 | //COMPUTE_USER_DATA_11 |
17417 | #define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 |
17418 | #define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL |
17419 | //COMPUTE_USER_DATA_12 |
17420 | #define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 |
17421 | #define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL |
17422 | //COMPUTE_USER_DATA_13 |
17423 | #define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 |
17424 | #define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL |
17425 | //COMPUTE_USER_DATA_14 |
17426 | #define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 |
17427 | #define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL |
17428 | //COMPUTE_USER_DATA_15 |
17429 | #define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 |
17430 | #define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL |
17431 | //COMPUTE_DISPATCH_TUNNEL |
17432 | #define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY__SHIFT 0x0 |
17433 | #define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE__SHIFT 0xa |
17434 | #define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY_MASK 0x000003FFL |
17435 | #define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE_MASK 0x00000400L |
17436 | //COMPUTE_DISPATCH_END |
17437 | #define COMPUTE_DISPATCH_END__DATA__SHIFT 0x0 |
17438 | #define COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL |
17439 | //COMPUTE_NOWHERE |
17440 | #define COMPUTE_NOWHERE__DATA__SHIFT 0x0 |
17441 | #define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL |
17442 | |
17443 | |
17444 | // addressBlock: gc_cppdec |
17445 | //CP_EOPQ_WAIT_TIME |
17446 | #define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0 |
17447 | #define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa |
17448 | #define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL |
17449 | #define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L |
17450 | //CP_CPC_MGCG_SYNC_CNTL |
17451 | #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 |
17452 | #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 |
17453 | #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL |
17454 | #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L |
17455 | //CPC_INT_INFO |
17456 | #define CPC_INT_INFO__ADDR_HI__SHIFT 0x0 |
17457 | #define CPC_INT_INFO__TYPE__SHIFT 0x10 |
17458 | #define CPC_INT_INFO__VMID__SHIFT 0x14 |
17459 | #define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c |
17460 | #define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL |
17461 | #define CPC_INT_INFO__TYPE_MASK 0x00010000L |
17462 | #define CPC_INT_INFO__VMID_MASK 0x00F00000L |
17463 | #define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L |
17464 | //CP_VIRT_STATUS |
17465 | #define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0 |
17466 | #define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL |
17467 | //CPC_INT_ADDR |
17468 | #define CPC_INT_ADDR__ADDR__SHIFT 0x0 |
17469 | #define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL |
17470 | //CPC_INT_PASID |
17471 | #define CPC_INT_PASID__PASID__SHIFT 0x0 |
17472 | #define CPC_INT_PASID__BYPASS_PASID__SHIFT 0x10 |
17473 | #define CPC_INT_PASID__PASID_MASK 0x0000FFFFL |
17474 | #define CPC_INT_PASID__BYPASS_PASID_MASK 0x00010000L |
17475 | //CP_GFX_ERROR |
17476 | #define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0 |
17477 | #define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4 |
17478 | #define CP_GFX_ERROR__CE_DATA_FETCHER_UTCL1_ERROR__SHIFT 0x5 |
17479 | #define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR__SHIFT 0x6 |
17480 | #define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7 |
17481 | #define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8 |
17482 | #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9 |
17483 | #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa |
17484 | #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb |
17485 | #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc |
17486 | #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd |
17487 | #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe |
17488 | #define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf |
17489 | #define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10 |
17490 | #define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11 |
17491 | #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12 |
17492 | #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13 |
17493 | #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14 |
17494 | #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15 |
17495 | #define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16 |
17496 | #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17 |
17497 | #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18 |
17498 | #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19 |
17499 | #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a |
17500 | #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b |
17501 | #define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c |
17502 | #define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d |
17503 | #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e |
17504 | #define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f |
17505 | #define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL |
17506 | #define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L |
17507 | #define CP_GFX_ERROR__CE_DATA_FETCHER_UTCL1_ERROR_MASK 0x00000020L |
17508 | #define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR_MASK 0x00000040L |
17509 | #define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L |
17510 | #define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L |
17511 | #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L |
17512 | #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L |
17513 | #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L |
17514 | #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L |
17515 | #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L |
17516 | #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L |
17517 | #define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L |
17518 | #define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L |
17519 | #define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L |
17520 | #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L |
17521 | #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L |
17522 | #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L |
17523 | #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L |
17524 | #define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L |
17525 | #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L |
17526 | #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L |
17527 | #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L |
17528 | #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L |
17529 | #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L |
17530 | #define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L |
17531 | #define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L |
17532 | #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L |
17533 | #define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L |
17534 | //CPG_UTCL1_CNTL |
17535 | #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
17536 | #define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
17537 | #define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
17538 | #define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
17539 | #define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
17540 | #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
17541 | #define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
17542 | #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e |
17543 | #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
17544 | #define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
17545 | #define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
17546 | #define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
17547 | #define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
17548 | #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
17549 | #define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
17550 | #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L |
17551 | //CPC_UTCL1_CNTL |
17552 | #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
17553 | #define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
17554 | #define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
17555 | #define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
17556 | #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
17557 | #define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
17558 | #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e |
17559 | #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
17560 | #define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
17561 | #define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
17562 | #define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
17563 | #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
17564 | #define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
17565 | #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L |
17566 | //CPF_UTCL1_CNTL |
17567 | #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
17568 | #define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
17569 | #define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
17570 | #define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
17571 | #define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
17572 | #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
17573 | #define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
17574 | #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e |
17575 | #define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f |
17576 | #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
17577 | #define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
17578 | #define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
17579 | #define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
17580 | #define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
17581 | #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
17582 | #define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
17583 | #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L |
17584 | #define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L |
17585 | //CP_AQL_SMM_STATUS |
17586 | #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0 |
17587 | #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL |
17588 | //CP_RB0_BASE |
17589 | #define CP_RB0_BASE__RB_BASE__SHIFT 0x0 |
17590 | #define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL |
17591 | //CP_RB_BASE |
17592 | #define CP_RB_BASE__RB_BASE__SHIFT 0x0 |
17593 | #define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL |
17594 | //CP_RB0_CNTL |
17595 | #define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 |
17596 | #define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 |
17597 | #define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x10 |
17598 | #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
17599 | #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
17600 | #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 |
17601 | #define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x1a |
17602 | #define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
17603 | #define CP_RB0_CNTL__RB_EXE__SHIFT 0x1c |
17604 | #define CP_RB0_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e |
17605 | #define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
17606 | #define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL |
17607 | #define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L |
17608 | #define CP_RB0_CNTL__BUF_SWAP_MASK 0x00030000L |
17609 | #define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
17610 | #define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
17611 | #define CP_RB0_CNTL__CACHE_POLICY_MASK 0x03000000L |
17612 | #define CP_RB0_CNTL__RB_VOLATILE_MASK 0x04000000L |
17613 | #define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
17614 | #define CP_RB0_CNTL__RB_EXE_MASK 0x10000000L |
17615 | #define CP_RB0_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L |
17616 | #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
17617 | //CP_RB_CNTL |
17618 | #define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 |
17619 | #define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 |
17620 | #define CP_RB_CNTL__BUF_SWAP__SHIFT 0x10 |
17621 | #define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
17622 | #define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
17623 | #define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 |
17624 | #define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x1a |
17625 | #define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
17626 | #define CP_RB_CNTL__RB_EXE__SHIFT 0x1c |
17627 | #define CP_RB_CNTL__KMD_QUEUE__SHIFT 0x1d |
17628 | #define CP_RB_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e |
17629 | #define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
17630 | #define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL |
17631 | #define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L |
17632 | #define CP_RB_CNTL__BUF_SWAP_MASK 0x00030000L |
17633 | #define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
17634 | #define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
17635 | #define CP_RB_CNTL__CACHE_POLICY_MASK 0x03000000L |
17636 | #define CP_RB_CNTL__RB_VOLATILE_MASK 0x04000000L |
17637 | #define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
17638 | #define CP_RB_CNTL__RB_EXE_MASK 0x10000000L |
17639 | #define CP_RB_CNTL__KMD_QUEUE_MASK 0x20000000L |
17640 | #define CP_RB_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L |
17641 | #define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
17642 | //CP_RB_RPTR_WR |
17643 | #define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 |
17644 | #define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL |
17645 | //CP_RB0_RPTR_ADDR |
17646 | #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
17647 | #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
17648 | //CP_RB_RPTR_ADDR |
17649 | #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
17650 | #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
17651 | //CP_RB0_RPTR_ADDR_HI |
17652 | #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
17653 | #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
17654 | //CP_RB_RPTR_ADDR_HI |
17655 | #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
17656 | #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
17657 | //CP_RB0_BUFSZ_MASK |
17658 | #define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0 |
17659 | #define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL |
17660 | //CP_RB_BUFSZ_MASK |
17661 | #define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0 |
17662 | #define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL |
17663 | //CP_INT_CNTL |
17664 | #define CP_INT_CNTL__RESUME_INT_ENABLE__SHIFT 0x8 |
17665 | #define CP_INT_CNTL__SUSPEND_INT_ENABLE__SHIFT 0x9 |
17666 | #define CP_INT_CNTL__DMA_WATCH_INT_ENABLE__SHIFT 0xa |
17667 | #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb |
17668 | #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
17669 | #define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
17670 | #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
17671 | #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 |
17672 | #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 |
17673 | #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 |
17674 | #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 |
17675 | #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
17676 | #define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
17677 | #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
17678 | #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
17679 | #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
17680 | #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
17681 | #define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
17682 | #define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
17683 | #define CP_INT_CNTL__RESUME_INT_ENABLE_MASK 0x00000100L |
17684 | #define CP_INT_CNTL__SUSPEND_INT_ENABLE_MASK 0x00000200L |
17685 | #define CP_INT_CNTL__DMA_WATCH_INT_ENABLE_MASK 0x00000400L |
17686 | #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L |
17687 | #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
17688 | #define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
17689 | #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
17690 | #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L |
17691 | #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L |
17692 | #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L |
17693 | #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L |
17694 | #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
17695 | #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
17696 | #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
17697 | #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
17698 | #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
17699 | #define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
17700 | #define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
17701 | #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
17702 | //CP_INT_STATUS |
17703 | #define CP_INT_STATUS__RESUME_INT_STAT__SHIFT 0x8 |
17704 | #define CP_INT_STATUS__SUSPEND_INT_STAT__SHIFT 0x9 |
17705 | #define CP_INT_STATUS__DMA_WATCH_INT_STAT__SHIFT 0xa |
17706 | #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb |
17707 | #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
17708 | #define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10 |
17709 | #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
17710 | #define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 |
17711 | #define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 |
17712 | #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 |
17713 | #define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 |
17714 | #define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
17715 | #define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 |
17716 | #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
17717 | #define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a |
17718 | #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
17719 | #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d |
17720 | #define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e |
17721 | #define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f |
17722 | #define CP_INT_STATUS__RESUME_INT_STAT_MASK 0x00000100L |
17723 | #define CP_INT_STATUS__SUSPEND_INT_STAT_MASK 0x00000200L |
17724 | #define CP_INT_STATUS__DMA_WATCH_INT_STAT_MASK 0x00000400L |
17725 | #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L |
17726 | #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
17727 | #define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L |
17728 | #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
17729 | #define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L |
17730 | #define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L |
17731 | #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L |
17732 | #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L |
17733 | #define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
17734 | #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L |
17735 | #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
17736 | #define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L |
17737 | #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
17738 | #define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L |
17739 | #define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L |
17740 | #define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L |
17741 | //CP_DEVICE_ID |
17742 | #define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
17743 | #define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL |
17744 | //CP_ME0_PIPE_PRIORITY_CNTS |
17745 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
17746 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
17747 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
17748 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
17749 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
17750 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
17751 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
17752 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
17753 | //CP_RING_PRIORITY_CNTS |
17754 | #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
17755 | #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
17756 | #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
17757 | #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
17758 | #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
17759 | #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
17760 | #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
17761 | #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
17762 | //CP_ME0_PIPE0_PRIORITY |
17763 | #define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
17764 | #define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
17765 | //CP_RING0_PRIORITY |
17766 | #define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 |
17767 | #define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L |
17768 | //CP_ME0_PIPE1_PRIORITY |
17769 | #define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
17770 | #define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
17771 | //CP_RING1_PRIORITY |
17772 | #define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 |
17773 | #define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L |
17774 | //CP_ME0_PIPE2_PRIORITY |
17775 | #define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
17776 | #define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
17777 | //CP_RING2_PRIORITY |
17778 | #define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 |
17779 | #define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L |
17780 | //CP_FATAL_ERROR |
17781 | #define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0 |
17782 | #define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1 |
17783 | #define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2 |
17784 | #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3 |
17785 | #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4 |
17786 | #define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L |
17787 | #define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L |
17788 | #define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L |
17789 | #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L |
17790 | #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L |
17791 | //CP_RB_VMID |
17792 | #define CP_RB_VMID__RB0_VMID__SHIFT 0x0 |
17793 | #define CP_RB_VMID__RB1_VMID__SHIFT 0x8 |
17794 | #define CP_RB_VMID__RB2_VMID__SHIFT 0x10 |
17795 | #define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL |
17796 | #define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L |
17797 | #define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L |
17798 | //CP_ME0_PIPE0_VMID |
17799 | #define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 |
17800 | #define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL |
17801 | //CP_ME0_PIPE1_VMID |
17802 | #define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 |
17803 | #define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL |
17804 | //CP_RB0_WPTR |
17805 | #define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 |
17806 | #define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
17807 | //CP_RB_WPTR |
17808 | #define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 |
17809 | #define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
17810 | //CP_RB0_WPTR_HI |
17811 | #define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0 |
17812 | #define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
17813 | //CP_RB_WPTR_HI |
17814 | #define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0 |
17815 | #define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
17816 | //CP_RB1_WPTR |
17817 | #define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 |
17818 | #define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
17819 | //CP_RB1_WPTR_HI |
17820 | #define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0 |
17821 | #define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
17822 | //CP_RB2_WPTR |
17823 | #define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 |
17824 | #define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL |
17825 | //CP_PROCESS_QUANTUM |
17826 | #define CP_PROCESS_QUANTUM__QUANTUM_DURATION__SHIFT 0x0 |
17827 | #define CP_PROCESS_QUANTUM__TIMER_EXPIRED__SHIFT 0x1c |
17828 | #define CP_PROCESS_QUANTUM__QUANTUM_SCALE__SHIFT 0x1d |
17829 | #define CP_PROCESS_QUANTUM__QUANTUM_EN__SHIFT 0x1f |
17830 | #define CP_PROCESS_QUANTUM__QUANTUM_DURATION_MASK 0x0FFFFFFFL |
17831 | #define CP_PROCESS_QUANTUM__TIMER_EXPIRED_MASK 0x10000000L |
17832 | #define CP_PROCESS_QUANTUM__QUANTUM_SCALE_MASK 0x60000000L |
17833 | #define CP_PROCESS_QUANTUM__QUANTUM_EN_MASK 0x80000000L |
17834 | //CP_RB_DOORBELL_RANGE_LOWER |
17835 | #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 |
17836 | #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL |
17837 | //CP_RB_DOORBELL_RANGE_UPPER |
17838 | #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 |
17839 | #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL |
17840 | //CP_MEC_DOORBELL_RANGE_LOWER |
17841 | #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 |
17842 | #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL |
17843 | //CP_MEC_DOORBELL_RANGE_UPPER |
17844 | #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 |
17845 | #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL |
17846 | //CPG_UTCL1_ERROR |
17847 | #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 |
17848 | #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L |
17849 | //CPC_UTCL1_ERROR |
17850 | #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 |
17851 | #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L |
17852 | //CP_RB1_BASE |
17853 | #define CP_RB1_BASE__RB_BASE__SHIFT 0x0 |
17854 | #define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL |
17855 | //CP_RB1_CNTL |
17856 | #define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 |
17857 | #define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 |
17858 | #define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
17859 | #define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
17860 | #define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 |
17861 | #define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x1a |
17862 | #define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
17863 | #define CP_RB1_CNTL__RB_EXE__SHIFT 0x1c |
17864 | #define CP_RB1_CNTL__KMD_QUEUE__SHIFT 0x1d |
17865 | #define CP_RB1_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e |
17866 | #define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
17867 | #define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL |
17868 | #define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L |
17869 | #define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
17870 | #define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
17871 | #define CP_RB1_CNTL__CACHE_POLICY_MASK 0x03000000L |
17872 | #define CP_RB1_CNTL__RB_VOLATILE_MASK 0x04000000L |
17873 | #define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
17874 | #define CP_RB1_CNTL__RB_EXE_MASK 0x10000000L |
17875 | #define CP_RB1_CNTL__KMD_QUEUE_MASK 0x20000000L |
17876 | #define CP_RB1_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L |
17877 | #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
17878 | //CP_RB1_RPTR_ADDR |
17879 | #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
17880 | #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
17881 | //CP_RB1_RPTR_ADDR_HI |
17882 | #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
17883 | #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
17884 | //CP_RB1_BUFSZ_MASK |
17885 | #define CP_RB1_BUFSZ_MASK__DATA__SHIFT 0x0 |
17886 | #define CP_RB1_BUFSZ_MASK__DATA_MASK 0x000FFFFFL |
17887 | //CP_RB2_BASE |
17888 | #define CP_RB2_BASE__RB_BASE__SHIFT 0x0 |
17889 | #define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL |
17890 | //CP_RB2_CNTL |
17891 | #define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 |
17892 | #define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 |
17893 | #define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
17894 | #define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
17895 | #define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 |
17896 | #define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x1a |
17897 | #define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
17898 | #define CP_RB2_CNTL__RB_EXE__SHIFT 0x1c |
17899 | #define CP_RB2_CNTL__KMD_QUEUE__SHIFT 0x1d |
17900 | #define CP_RB2_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e |
17901 | #define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
17902 | #define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL |
17903 | #define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L |
17904 | #define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
17905 | #define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
17906 | #define CP_RB2_CNTL__CACHE_POLICY_MASK 0x03000000L |
17907 | #define CP_RB2_CNTL__RB_VOLATILE_MASK 0x04000000L |
17908 | #define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
17909 | #define CP_RB2_CNTL__RB_EXE_MASK 0x10000000L |
17910 | #define CP_RB2_CNTL__KMD_QUEUE_MASK 0x20000000L |
17911 | #define CP_RB2_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L |
17912 | #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
17913 | //CP_RB2_RPTR_ADDR |
17914 | #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
17915 | #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
17916 | //CP_RB2_RPTR_ADDR_HI |
17917 | #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
17918 | #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
17919 | //CP_INT_CNTL_RING0 |
17920 | #define CP_INT_CNTL_RING0__RESUME_INT_ENABLE__SHIFT 0x8 |
17921 | #define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE__SHIFT 0x9 |
17922 | #define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE__SHIFT 0xa |
17923 | #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb |
17924 | #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
17925 | #define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10 |
17926 | #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
17927 | #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 |
17928 | #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 |
17929 | #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 |
17930 | #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 |
17931 | #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
17932 | #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
17933 | #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
17934 | #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
17935 | #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
17936 | #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d |
17937 | #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e |
17938 | #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f |
17939 | #define CP_INT_CNTL_RING0__RESUME_INT_ENABLE_MASK 0x00000100L |
17940 | #define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE_MASK 0x00000200L |
17941 | #define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE_MASK 0x00000400L |
17942 | #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L |
17943 | #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
17944 | #define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L |
17945 | #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
17946 | #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L |
17947 | #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L |
17948 | #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L |
17949 | #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L |
17950 | #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
17951 | #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
17952 | #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
17953 | #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
17954 | #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
17955 | #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L |
17956 | #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L |
17957 | #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L |
17958 | //CP_INT_CNTL_RING1 |
17959 | #define CP_INT_CNTL_RING1__DMA_WATCH_INT_ENABLE__SHIFT 0xa |
17960 | #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb |
17961 | #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
17962 | #define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10 |
17963 | #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
17964 | #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12 |
17965 | #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 |
17966 | #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 |
17967 | #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15 |
17968 | #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
17969 | #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
17970 | #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
17971 | #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
17972 | #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
17973 | #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d |
17974 | #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e |
17975 | #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f |
17976 | #define CP_INT_CNTL_RING1__DMA_WATCH_INT_ENABLE_MASK 0x00000400L |
17977 | #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L |
17978 | #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
17979 | #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L |
17980 | #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
17981 | #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L |
17982 | #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L |
17983 | #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L |
17984 | #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L |
17985 | #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
17986 | #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
17987 | #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
17988 | #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
17989 | #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
17990 | #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L |
17991 | #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L |
17992 | #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L |
17993 | //CP_INT_CNTL_RING2 |
17994 | #define CP_INT_CNTL_RING2__DMA_WATCH_INT_ENABLE__SHIFT 0xa |
17995 | #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb |
17996 | #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
17997 | #define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10 |
17998 | #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
17999 | #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12 |
18000 | #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 |
18001 | #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 |
18002 | #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15 |
18003 | #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
18004 | #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18005 | #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18006 | #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18007 | #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18008 | #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18009 | #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18010 | #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18011 | #define CP_INT_CNTL_RING2__DMA_WATCH_INT_ENABLE_MASK 0x00000400L |
18012 | #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L |
18013 | #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18014 | #define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L |
18015 | #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18016 | #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L |
18017 | #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L |
18018 | #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L |
18019 | #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L |
18020 | #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
18021 | #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18022 | #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18023 | #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18024 | #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18025 | #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18026 | #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18027 | #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18028 | //CP_INT_STATUS_RING0 |
18029 | #define CP_INT_STATUS_RING0__RESUME_INT_STAT__SHIFT 0x8 |
18030 | #define CP_INT_STATUS_RING0__SUSPEND_INT_STAT__SHIFT 0x9 |
18031 | #define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT__SHIFT 0xa |
18032 | #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb |
18033 | #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
18034 | #define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10 |
18035 | #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
18036 | #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 |
18037 | #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 |
18038 | #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 |
18039 | #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 |
18040 | #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
18041 | #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 |
18042 | #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
18043 | #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a |
18044 | #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
18045 | #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d |
18046 | #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e |
18047 | #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f |
18048 | #define CP_INT_STATUS_RING0__RESUME_INT_STAT_MASK 0x00000100L |
18049 | #define CP_INT_STATUS_RING0__SUSPEND_INT_STAT_MASK 0x00000200L |
18050 | #define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT_MASK 0x00000400L |
18051 | #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L |
18052 | #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
18053 | #define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L |
18054 | #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
18055 | #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L |
18056 | #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L |
18057 | #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L |
18058 | #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L |
18059 | #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
18060 | #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L |
18061 | #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
18062 | #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L |
18063 | #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
18064 | #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L |
18065 | #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L |
18066 | #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L |
18067 | //CP_INT_STATUS_RING1 |
18068 | #define CP_INT_STATUS_RING1__DMA_WATCH_INT_STAT__SHIFT 0xa |
18069 | #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb |
18070 | #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
18071 | #define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10 |
18072 | #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
18073 | #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12 |
18074 | #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 |
18075 | #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 |
18076 | #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15 |
18077 | #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
18078 | #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 |
18079 | #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
18080 | #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a |
18081 | #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
18082 | #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d |
18083 | #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e |
18084 | #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f |
18085 | #define CP_INT_STATUS_RING1__DMA_WATCH_INT_STAT_MASK 0x00000400L |
18086 | #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L |
18087 | #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
18088 | #define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L |
18089 | #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
18090 | #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L |
18091 | #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L |
18092 | #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L |
18093 | #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L |
18094 | #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
18095 | #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L |
18096 | #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
18097 | #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L |
18098 | #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
18099 | #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L |
18100 | #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L |
18101 | #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L |
18102 | //CP_INT_STATUS_RING2 |
18103 | #define CP_INT_STATUS_RING2__DMA_WATCH_INT_STAT__SHIFT 0xa |
18104 | #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb |
18105 | #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
18106 | #define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10 |
18107 | #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
18108 | #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12 |
18109 | #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 |
18110 | #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 |
18111 | #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15 |
18112 | #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
18113 | #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 |
18114 | #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
18115 | #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a |
18116 | #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
18117 | #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d |
18118 | #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e |
18119 | #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f |
18120 | #define CP_INT_STATUS_RING2__DMA_WATCH_INT_STAT_MASK 0x00000400L |
18121 | #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L |
18122 | #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
18123 | #define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L |
18124 | #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
18125 | #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L |
18126 | #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L |
18127 | #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L |
18128 | #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L |
18129 | #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
18130 | #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L |
18131 | #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
18132 | #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L |
18133 | #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
18134 | #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L |
18135 | #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L |
18136 | #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L |
18137 | #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 |
18138 | #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L |
18139 | #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 |
18140 | #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L |
18141 | #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 |
18142 | #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L |
18143 | //CP_PWR_CNTL |
18144 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 |
18145 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 |
18146 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 |
18147 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 |
18148 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa |
18149 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb |
18150 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 |
18151 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 |
18152 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 |
18153 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 |
18154 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0__SHIFT 0x14 |
18155 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1__SHIFT 0x15 |
18156 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2__SHIFT 0x16 |
18157 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3__SHIFT 0x17 |
18158 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L |
18159 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L |
18160 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L |
18161 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L |
18162 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L |
18163 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L |
18164 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L |
18165 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L |
18166 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L |
18167 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L |
18168 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0_MASK 0x00100000L |
18169 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1_MASK 0x00200000L |
18170 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2_MASK 0x00400000L |
18171 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3_MASK 0x00800000L |
18172 | //CP_MEM_SLP_CNTL |
18173 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 |
18174 | #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 |
18175 | #define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 |
18176 | #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 |
18177 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 |
18178 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 |
18179 | #define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 |
18180 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L |
18181 | #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L |
18182 | #define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL |
18183 | #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L |
18184 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L |
18185 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L |
18186 | #define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L |
18187 | //CP_ECC_FIRSTOCCURRENCE |
18188 | #define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 |
18189 | #define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 |
18190 | #define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 |
18191 | #define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa |
18192 | #define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc |
18193 | #define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 |
18194 | #define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L |
18195 | #define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L |
18196 | #define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L |
18197 | #define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L |
18198 | #define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L |
18199 | #define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L |
18200 | //CP_ECC_FIRSTOCCURRENCE_RING0 |
18201 | #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 |
18202 | #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL |
18203 | //CP_ECC_FIRSTOCCURRENCE_RING1 |
18204 | #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 |
18205 | #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL |
18206 | //CP_ECC_FIRSTOCCURRENCE_RING2 |
18207 | #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0 |
18208 | #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL |
18209 | //GB_EDC_MODE |
18210 | #define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf |
18211 | #define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 |
18212 | #define GB_EDC_MODE__GATE_FUE__SHIFT 0x11 |
18213 | #define GB_EDC_MODE__DED_MODE__SHIFT 0x14 |
18214 | #define GB_EDC_MODE__PROP_FED__SHIFT 0x1d |
18215 | #define GB_EDC_MODE__BYPASS__SHIFT 0x1f |
18216 | #define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L |
18217 | #define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L |
18218 | #define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L |
18219 | #define GB_EDC_MODE__DED_MODE_MASK 0x00300000L |
18220 | #define GB_EDC_MODE__PROP_FED_MASK 0x20000000L |
18221 | #define GB_EDC_MODE__BYPASS_MASK 0x80000000L |
18222 | //CP_FETCHER_SOURCE |
18223 | #define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0 |
18224 | #define CP_FETCHER_SOURCE__ME_SRC_MASK 0x00000001L |
18225 | //CP_PQ_WPTR_POLL_CNTL |
18226 | #define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 |
18227 | #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d |
18228 | #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e |
18229 | #define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f |
18230 | #define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL |
18231 | #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L |
18232 | #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L |
18233 | #define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L |
18234 | //CP_PQ_WPTR_POLL_CNTL1 |
18235 | #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 |
18236 | #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL |
18237 | //CP_ME1_PIPE0_INT_CNTL |
18238 | #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18239 | #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18240 | #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18241 | #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18242 | #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18243 | #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18244 | #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18245 | #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18246 | #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18247 | #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18248 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18249 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18250 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18251 | #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18252 | #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18253 | #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18254 | #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18255 | #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18256 | #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18257 | #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18258 | #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18259 | #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18260 | #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18261 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18262 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18263 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18264 | //CP_ME1_PIPE1_INT_CNTL |
18265 | #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18266 | #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18267 | #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18268 | #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18269 | #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18270 | #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18271 | #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18272 | #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18273 | #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18274 | #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18275 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18276 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18277 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18278 | #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18279 | #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18280 | #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18281 | #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18282 | #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18283 | #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18284 | #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18285 | #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18286 | #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18287 | #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18288 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18289 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18290 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18291 | //CP_ME1_PIPE2_INT_CNTL |
18292 | #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18293 | #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18294 | #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18295 | #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18296 | #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18297 | #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18298 | #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18299 | #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18300 | #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18301 | #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18302 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18303 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18304 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18305 | #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18306 | #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18307 | #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18308 | #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18309 | #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18310 | #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18311 | #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18312 | #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18313 | #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18314 | #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18315 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18316 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18317 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18318 | //CP_ME1_PIPE3_INT_CNTL |
18319 | #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18320 | #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18321 | #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18322 | #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18323 | #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18324 | #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18325 | #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18326 | #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18327 | #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18328 | #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18329 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18330 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18331 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18332 | #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18333 | #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18334 | #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18335 | #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18336 | #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18337 | #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18338 | #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18339 | #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18340 | #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18341 | #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18342 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18343 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18344 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18345 | //CP_ME2_PIPE0_INT_CNTL |
18346 | #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18347 | #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18348 | #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18349 | #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18350 | #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18351 | #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18352 | #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18353 | #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18354 | #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18355 | #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18356 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18357 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18358 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18359 | #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18360 | #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18361 | #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18362 | #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18363 | #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18364 | #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18365 | #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18366 | #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18367 | #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18368 | #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18369 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18370 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18371 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18372 | //CP_ME2_PIPE1_INT_CNTL |
18373 | #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18374 | #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18375 | #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18376 | #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18377 | #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18378 | #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18379 | #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18380 | #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18381 | #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18382 | #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18383 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18384 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18385 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18386 | #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18387 | #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18388 | #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18389 | #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18390 | #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18391 | #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18392 | #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18393 | #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18394 | #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18395 | #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18396 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18397 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18398 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18399 | //CP_ME2_PIPE2_INT_CNTL |
18400 | #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18401 | #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18402 | #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18403 | #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18404 | #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18405 | #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18406 | #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18407 | #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18408 | #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18409 | #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18410 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18411 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18412 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18413 | #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18414 | #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18415 | #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18416 | #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18417 | #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18418 | #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18419 | #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18420 | #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18421 | #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18422 | #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18423 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18424 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18425 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18426 | //CP_ME2_PIPE3_INT_CNTL |
18427 | #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18428 | #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18429 | #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18430 | #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18431 | #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18432 | #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18433 | #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18434 | #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18435 | #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18436 | #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18437 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18438 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18439 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18440 | #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18441 | #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18442 | #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18443 | #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18444 | #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18445 | #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18446 | #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18447 | #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18448 | #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18449 | #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18450 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18451 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18452 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18453 | //CP_ME1_PIPE0_INT_STATUS |
18454 | #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18455 | #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18456 | #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18457 | #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18458 | #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18459 | #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18460 | #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18461 | #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18462 | #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18463 | #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18464 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18465 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18466 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18467 | #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18468 | #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18469 | #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18470 | #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18471 | #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18472 | #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18473 | #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18474 | #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18475 | #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18476 | #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18477 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18478 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18479 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18480 | //CP_ME1_PIPE1_INT_STATUS |
18481 | #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18482 | #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18483 | #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18484 | #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18485 | #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18486 | #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18487 | #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18488 | #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18489 | #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18490 | #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18491 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18492 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18493 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18494 | #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18495 | #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18496 | #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18497 | #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18498 | #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18499 | #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18500 | #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18501 | #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18502 | #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18503 | #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18504 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18505 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18506 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18507 | //CP_ME1_PIPE2_INT_STATUS |
18508 | #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18509 | #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18510 | #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18511 | #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18512 | #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18513 | #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18514 | #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18515 | #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18516 | #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18517 | #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18518 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18519 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18520 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18521 | #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18522 | #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18523 | #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18524 | #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18525 | #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18526 | #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18527 | #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18528 | #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18529 | #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18530 | #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18531 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18532 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18533 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18534 | //CP_ME1_PIPE3_INT_STATUS |
18535 | #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18536 | #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18537 | #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18538 | #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18539 | #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18540 | #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18541 | #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18542 | #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18543 | #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18544 | #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18545 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18546 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18547 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18548 | #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18549 | #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18550 | #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18551 | #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18552 | #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18553 | #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18554 | #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18555 | #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18556 | #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18557 | #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18558 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18559 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18560 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18561 | //CP_ME2_PIPE0_INT_STATUS |
18562 | #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18563 | #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18564 | #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18565 | #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18566 | #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18567 | #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18568 | #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18569 | #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18570 | #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18571 | #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18572 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18573 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18574 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18575 | #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18576 | #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18577 | #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18578 | #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18579 | #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18580 | #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18581 | #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18582 | #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18583 | #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18584 | #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18585 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18586 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18587 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18588 | //CP_ME2_PIPE1_INT_STATUS |
18589 | #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18590 | #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18591 | #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18592 | #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18593 | #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18594 | #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18595 | #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18596 | #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18597 | #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18598 | #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18599 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18600 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18601 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18602 | #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18603 | #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18604 | #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18605 | #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18606 | #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18607 | #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18608 | #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18609 | #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18610 | #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18611 | #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18612 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18613 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18614 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18615 | //CP_ME2_PIPE2_INT_STATUS |
18616 | #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18617 | #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18618 | #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18619 | #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18620 | #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18621 | #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18622 | #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18623 | #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18624 | #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18625 | #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18626 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18627 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18628 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18629 | #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18630 | #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18631 | #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18632 | #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18633 | #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18634 | #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18635 | #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18636 | #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18637 | #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18638 | #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18639 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18640 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18641 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18642 | //CP_ME2_PIPE3_INT_STATUS |
18643 | #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18644 | #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18645 | #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18646 | #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18647 | #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18648 | #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18649 | #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18650 | #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18651 | #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18652 | #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18653 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18654 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18655 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18656 | #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18657 | #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18658 | #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18659 | #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18660 | #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18661 | #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18662 | #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18663 | #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18664 | #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18665 | #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18666 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18667 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18668 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18669 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
18670 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
18671 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
18672 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
18673 | //CP_GFX_QUEUE_INDEX |
18674 | #define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS__SHIFT 0x0 |
18675 | #define CP_GFX_QUEUE_INDEX__PIPE_ID__SHIFT 0x4 |
18676 | #define CP_GFX_QUEUE_INDEX__QUEUE_ID__SHIFT 0x8 |
18677 | #define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS_MASK 0x00000001L |
18678 | #define CP_GFX_QUEUE_INDEX__PIPE_ID_MASK 0x00000030L |
18679 | #define CP_GFX_QUEUE_INDEX__QUEUE_ID_MASK 0x00000700L |
18680 | //CC_GC_EDC_CONFIG |
18681 | #define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 |
18682 | #define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L |
18683 | //CP_ME1_INT_STAT_DEBUG |
18684 | #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc |
18685 | #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd |
18686 | #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe |
18687 | #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18688 | #define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 |
18689 | #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 |
18690 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
18691 | #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 |
18692 | #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a |
18693 | #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b |
18694 | #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d |
18695 | #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e |
18696 | #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f |
18697 | #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L |
18698 | #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L |
18699 | #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L |
18700 | #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18701 | #define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L |
18702 | #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L |
18703 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
18704 | #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L |
18705 | #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L |
18706 | #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L |
18707 | #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L |
18708 | #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L |
18709 | #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L |
18710 | //CP_ME2_INT_STAT_DEBUG |
18711 | #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc |
18712 | #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd |
18713 | #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe |
18714 | #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18715 | #define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 |
18716 | #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 |
18717 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
18718 | #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 |
18719 | #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a |
18720 | #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b |
18721 | #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d |
18722 | #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e |
18723 | #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f |
18724 | #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L |
18725 | #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L |
18726 | #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L |
18727 | #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18728 | #define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L |
18729 | #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L |
18730 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
18731 | #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L |
18732 | #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L |
18733 | #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L |
18734 | #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L |
18735 | #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L |
18736 | #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L |
18737 | //CP_ME1_PIPE_PRIORITY_CNTS |
18738 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
18739 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
18740 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
18741 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
18742 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
18743 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
18744 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
18745 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
18746 | //CP_ME1_PIPE0_PRIORITY |
18747 | #define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
18748 | #define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
18749 | //CP_ME1_PIPE1_PRIORITY |
18750 | #define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
18751 | #define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
18752 | //CP_ME1_PIPE2_PRIORITY |
18753 | #define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
18754 | #define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
18755 | //CP_ME1_PIPE3_PRIORITY |
18756 | #define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 |
18757 | #define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L |
18758 | //CP_ME2_PIPE_PRIORITY_CNTS |
18759 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
18760 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
18761 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
18762 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
18763 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
18764 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
18765 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
18766 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
18767 | //CP_ME2_PIPE0_PRIORITY |
18768 | #define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
18769 | #define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
18770 | //CP_ME2_PIPE1_PRIORITY |
18771 | #define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
18772 | #define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
18773 | //CP_ME2_PIPE2_PRIORITY |
18774 | #define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
18775 | #define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
18776 | //CP_ME2_PIPE3_PRIORITY |
18777 | #define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 |
18778 | #define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L |
18779 | //CP_CE_PRGRM_CNTR_START |
18780 | #define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
18781 | #define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL |
18782 | //CP_PFP_PRGRM_CNTR_START |
18783 | #define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
18784 | #define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL |
18785 | //CP_ME_PRGRM_CNTR_START |
18786 | #define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
18787 | #define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL |
18788 | //CP_MEC1_PRGRM_CNTR_START |
18789 | #define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
18790 | #define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL |
18791 | //CP_MEC2_PRGRM_CNTR_START |
18792 | #define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
18793 | #define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL |
18794 | //CP_CE_INTR_ROUTINE_START |
18795 | #define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
18796 | #define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL |
18797 | //CP_PFP_INTR_ROUTINE_START |
18798 | #define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
18799 | #define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL |
18800 | //CP_ME_INTR_ROUTINE_START |
18801 | #define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
18802 | #define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL |
18803 | //CP_MEC1_INTR_ROUTINE_START |
18804 | #define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
18805 | #define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL |
18806 | //CP_MEC2_INTR_ROUTINE_START |
18807 | #define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
18808 | #define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL |
18809 | //CP_CONTEXT_CNTL |
18810 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX__SHIFT 0x0 |
18811 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 |
18812 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX__SHIFT 0x10 |
18813 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 |
18814 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX_MASK 0x00000007L |
18815 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L |
18816 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX_MASK 0x00070000L |
18817 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L |
18818 | //CP_MAX_CONTEXT |
18819 | #define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 |
18820 | #define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L |
18821 | //CP_IQ_WAIT_TIME1 |
18822 | #define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 |
18823 | #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 |
18824 | #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 |
18825 | #define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 |
18826 | #define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL |
18827 | #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L |
18828 | #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L |
18829 | #define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L |
18830 | //CP_IQ_WAIT_TIME2 |
18831 | #define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 |
18832 | #define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 |
18833 | #define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 |
18834 | #define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 |
18835 | #define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL |
18836 | #define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L |
18837 | #define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L |
18838 | #define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L |
18839 | //CP_RB0_BASE_HI |
18840 | #define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
18841 | #define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL |
18842 | //CP_RB1_BASE_HI |
18843 | #define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
18844 | #define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL |
18845 | //CP_VMID_RESET |
18846 | #define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 |
18847 | #define CP_VMID_RESET__PIPE0_QUEUES__SHIFT 0x10 |
18848 | #define CP_VMID_RESET__PIPE1_QUEUES__SHIFT 0x18 |
18849 | #define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL |
18850 | #define CP_VMID_RESET__PIPE0_QUEUES_MASK 0x00FF0000L |
18851 | #define CP_VMID_RESET__PIPE1_QUEUES_MASK 0xFF000000L |
18852 | //CPC_INT_CNTL |
18853 | #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18854 | #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18855 | #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18856 | #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18857 | #define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18858 | #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18859 | #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18860 | #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18861 | #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18862 | #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18863 | #define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18864 | #define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18865 | #define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18866 | #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18867 | #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18868 | #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18869 | #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18870 | #define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18871 | #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18872 | #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18873 | #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18874 | #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18875 | #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18876 | #define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18877 | #define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18878 | #define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18879 | //CPC_INT_STATUS |
18880 | #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18881 | #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18882 | #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18883 | #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18884 | #define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18885 | #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18886 | #define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18887 | #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18888 | #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18889 | #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18890 | #define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18891 | #define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18892 | #define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18893 | #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18894 | #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18895 | #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18896 | #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18897 | #define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18898 | #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18899 | #define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18900 | #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18901 | #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18902 | #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18903 | #define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18904 | #define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18905 | #define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18906 | //CP_VMID_PREEMPT |
18907 | #define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 |
18908 | #define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 |
18909 | #define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL |
18910 | #define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L |
18911 | //CPC_INT_CNTX_ID |
18912 | #define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 |
18913 | #define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL |
18914 | //CP_PQ_STATUS |
18915 | #define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 |
18916 | #define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 |
18917 | #define CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT 0x2 |
18918 | #define CP_PQ_STATUS__DOORBELL_UPDATED_MODE__SHIFT 0x3 |
18919 | #define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L |
18920 | #define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L |
18921 | #define CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK 0x00000004L |
18922 | #define CP_PQ_STATUS__DOORBELL_UPDATED_MODE_MASK 0x00000008L |
18923 | //CP_CE_CS_PARTITION_INDEX |
18924 | #define CP_CE_CS_PARTITION_INDEX__CS1_INDEX__SHIFT 0x0 |
18925 | #define CP_CE_CS_PARTITION_INDEX__CS1_INDEX_MASK 0x0001FFFFL |
18926 | //CP_MEC1_F32_INT_DIS |
18927 | #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 |
18928 | #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 |
18929 | #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
18930 | #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 |
18931 | #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 |
18932 | #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 |
18933 | #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 |
18934 | #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 |
18935 | #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 |
18936 | #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 |
18937 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa |
18938 | #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb |
18939 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc |
18940 | #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd |
18941 | #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe |
18942 | #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf |
18943 | #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L |
18944 | #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L |
18945 | #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
18946 | #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L |
18947 | #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L |
18948 | #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L |
18949 | #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L |
18950 | #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L |
18951 | #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L |
18952 | #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L |
18953 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L |
18954 | #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L |
18955 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L |
18956 | #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L |
18957 | #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L |
18958 | #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L |
18959 | //CP_MEC2_F32_INT_DIS |
18960 | #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 |
18961 | #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 |
18962 | #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
18963 | #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 |
18964 | #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 |
18965 | #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 |
18966 | #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 |
18967 | #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 |
18968 | #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 |
18969 | #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 |
18970 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa |
18971 | #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb |
18972 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc |
18973 | #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd |
18974 | #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe |
18975 | #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf |
18976 | #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L |
18977 | #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L |
18978 | #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
18979 | #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L |
18980 | #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L |
18981 | #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L |
18982 | #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L |
18983 | #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L |
18984 | #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L |
18985 | #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L |
18986 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L |
18987 | #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L |
18988 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L |
18989 | #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L |
18990 | #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L |
18991 | #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L |
18992 | //CP_VMID_STATUS |
18993 | #define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 |
18994 | #define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 |
18995 | #define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL |
18996 | #define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L |
18997 | //CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO |
18998 | #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc |
18999 | #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L |
19000 | //CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI |
19001 | #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
19002 | #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
19003 | //CPC_SUSPEND_CTX_SAVE_CONTROL |
19004 | #define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 |
19005 | #define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 |
19006 | #define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L |
19007 | #define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L |
19008 | //CPC_SUSPEND_CNTL_STACK_OFFSET |
19009 | #define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 |
19010 | #define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL |
19011 | //CPC_SUSPEND_CNTL_STACK_SIZE |
19012 | #define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE__SHIFT 0xc |
19013 | #define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L |
19014 | //CPC_SUSPEND_WG_STATE_OFFSET |
19015 | #define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 |
19016 | #define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL |
19017 | //CPC_SUSPEND_CTX_SAVE_SIZE |
19018 | #define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE__SHIFT 0xc |
19019 | #define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L |
19020 | //CPC_OS_PIPES |
19021 | #define CPC_OS_PIPES__OS_PIPES__SHIFT 0x0 |
19022 | #define CPC_OS_PIPES__OS_PIPES_MASK 0x000000FFL |
19023 | //CP_SUSPEND_RESUME_REQ |
19024 | #define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ__SHIFT 0x0 |
19025 | #define CP_SUSPEND_RESUME_REQ__RESUME_REQ__SHIFT 0x1 |
19026 | #define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ_MASK 0x00000001L |
19027 | #define CP_SUSPEND_RESUME_REQ__RESUME_REQ_MASK 0x00000002L |
19028 | //CP_SUSPEND_CNTL |
19029 | #define CP_SUSPEND_CNTL__SUSPEND_MODE__SHIFT 0x0 |
19030 | #define CP_SUSPEND_CNTL__SUSPEND_ENABLE__SHIFT 0x1 |
19031 | #define CP_SUSPEND_CNTL__RESUME_LOCK__SHIFT 0x2 |
19032 | #define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE__SHIFT 0x3 |
19033 | #define CP_SUSPEND_CNTL__SUSPEND_MODE_MASK 0x00000001L |
19034 | #define CP_SUSPEND_CNTL__SUSPEND_ENABLE_MASK 0x00000002L |
19035 | #define CP_SUSPEND_CNTL__RESUME_LOCK_MASK 0x00000004L |
19036 | #define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE_MASK 0x00000008L |
19037 | //CP_IQ_WAIT_TIME3 |
19038 | #define CP_IQ_WAIT_TIME3__SUSPEND_QUE__SHIFT 0x0 |
19039 | #define CP_IQ_WAIT_TIME3__SUSPEND_QUE_MASK 0x000000FFL |
19040 | //CPC_DDID_BASE_ADDR_LO |
19041 | #define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6 |
19042 | #define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L |
19043 | //CP_DDID_BASE_ADDR_LO |
19044 | #define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6 |
19045 | #define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L |
19046 | //CPC_DDID_BASE_ADDR_HI |
19047 | #define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
19048 | #define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL |
19049 | //CP_DDID_BASE_ADDR_HI |
19050 | #define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
19051 | #define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL |
19052 | //CPC_DDID_CNTL |
19053 | #define CPC_DDID_CNTL__THRESHOLD__SHIFT 0x0 |
19054 | #define CPC_DDID_CNTL__SIZE__SHIFT 0x10 |
19055 | #define CPC_DDID_CNTL__POLICY__SHIFT 0x1c |
19056 | #define CPC_DDID_CNTL__MODE__SHIFT 0x1e |
19057 | #define CPC_DDID_CNTL__ENABLE__SHIFT 0x1f |
19058 | #define CPC_DDID_CNTL__THRESHOLD_MASK 0x000000FFL |
19059 | #define CPC_DDID_CNTL__SIZE_MASK 0x00010000L |
19060 | #define CPC_DDID_CNTL__POLICY_MASK 0x30000000L |
19061 | #define CPC_DDID_CNTL__MODE_MASK 0x40000000L |
19062 | #define CPC_DDID_CNTL__ENABLE_MASK 0x80000000L |
19063 | //CP_DDID_CNTL |
19064 | #define CP_DDID_CNTL__THRESHOLD__SHIFT 0x0 |
19065 | #define CP_DDID_CNTL__SIZE__SHIFT 0x10 |
19066 | #define CP_DDID_CNTL__VMID__SHIFT 0x14 |
19067 | #define CP_DDID_CNTL__VMID_SEL__SHIFT 0x18 |
19068 | #define CP_DDID_CNTL__POLICY__SHIFT 0x1c |
19069 | #define CP_DDID_CNTL__MODE__SHIFT 0x1e |
19070 | #define CP_DDID_CNTL__ENABLE__SHIFT 0x1f |
19071 | #define CP_DDID_CNTL__THRESHOLD_MASK 0x000000FFL |
19072 | #define CP_DDID_CNTL__SIZE_MASK 0x00010000L |
19073 | #define CP_DDID_CNTL__VMID_MASK 0x00F00000L |
19074 | #define CP_DDID_CNTL__VMID_SEL_MASK 0x01000000L |
19075 | #define CP_DDID_CNTL__POLICY_MASK 0x30000000L |
19076 | #define CP_DDID_CNTL__MODE_MASK 0x40000000L |
19077 | #define CP_DDID_CNTL__ENABLE_MASK 0x80000000L |
19078 | //CP_GFX_DDID_INFLIGHT_COUNT |
19079 | #define CP_GFX_DDID_INFLIGHT_COUNT__COUNT__SHIFT 0x0 |
19080 | #define CP_GFX_DDID_INFLIGHT_COUNT__COUNT_MASK 0x0000FFFFL |
19081 | //CP_GFX_DDID_WPTR |
19082 | #define CP_GFX_DDID_WPTR__COUNT__SHIFT 0x0 |
19083 | #define CP_GFX_DDID_WPTR__COUNT_MASK 0x0000FFFFL |
19084 | //CP_GFX_DDID_RPTR |
19085 | #define CP_GFX_DDID_RPTR__COUNT__SHIFT 0x0 |
19086 | #define CP_GFX_DDID_RPTR__COUNT_MASK 0x0000FFFFL |
19087 | //CP_GFX_DDID_DELTA_RPT_COUNT |
19088 | #define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT__SHIFT 0x0 |
19089 | #define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT_MASK 0x000000FFL |
19090 | //CP_GFX_HPD_STATUS0 |
19091 | #define CP_GFX_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 |
19092 | #define CP_GFX_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 |
19093 | #define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 |
19094 | #define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE__SHIFT 0x10 |
19095 | #define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 |
19096 | #define CP_GFX_HPD_STATUS0__SUSPEND_REQ__SHIFT 0x1c |
19097 | #define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID__SHIFT 0x1d |
19098 | #define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID__SHIFT 0x1e |
19099 | #define CP_GFX_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f |
19100 | #define CP_GFX_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL |
19101 | #define CP_GFX_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L |
19102 | #define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L |
19103 | #define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE_MASK 0x00070000L |
19104 | #define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L |
19105 | #define CP_GFX_HPD_STATUS0__SUSPEND_REQ_MASK 0x10000000L |
19106 | #define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID_MASK 0x20000000L |
19107 | #define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID_MASK 0x40000000L |
19108 | #define CP_GFX_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L |
19109 | //CP_GFX_HPD_CONTROL0 |
19110 | #define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE__SHIFT 0x0 |
19111 | #define CP_GFX_HPD_CONTROL0__PIPE_HOLDING__SHIFT 0x4 |
19112 | #define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE_MASK 0x00000001L |
19113 | #define CP_GFX_HPD_CONTROL0__PIPE_HOLDING_MASK 0x00000010L |
19114 | //CP_GFX_HPD_OSPRE_FENCE_ADDR_LO |
19115 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO__SHIFT 0x2 |
19116 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
19117 | //CP_GFX_HPD_OSPRE_FENCE_ADDR_HI |
19118 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
19119 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD__SHIFT 0x10 |
19120 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
19121 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD_MASK 0xFFFF0000L |
19122 | //CP_GFX_HPD_OSPRE_FENCE_DATA_LO |
19123 | #define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO__SHIFT 0x0 |
19124 | #define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL |
19125 | //CP_GFX_HPD_OSPRE_FENCE_DATA_HI |
19126 | #define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI__SHIFT 0x0 |
19127 | #define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL |
19128 | //CP_GFX_INDEX_MUTEX |
19129 | #define CP_GFX_INDEX_MUTEX__REQUEST__SHIFT 0x0 |
19130 | #define CP_GFX_INDEX_MUTEX__CLIENTID__SHIFT 0x1 |
19131 | #define CP_GFX_INDEX_MUTEX__REQUEST_MASK 0x00000001L |
19132 | #define CP_GFX_INDEX_MUTEX__CLIENTID_MASK 0x0000000EL |
19133 | //CP_GFX_MQD_BASE_ADDR |
19134 | #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 |
19135 | #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL |
19136 | //CP_GFX_MQD_BASE_ADDR_HI |
19137 | #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
19138 | #define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID__SHIFT 0x1c |
19139 | #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL |
19140 | #define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID_MASK 0xF0000000L |
19141 | //CP_GFX_HQD_ACTIVE |
19142 | #define CP_GFX_HQD_ACTIVE__ACTIVE__SHIFT 0x0 |
19143 | #define CP_GFX_HQD_ACTIVE__ACTIVE_MASK 0x00000001L |
19144 | //CP_GFX_HQD_VMID |
19145 | #define CP_GFX_HQD_VMID__VMID__SHIFT 0x0 |
19146 | #define CP_GFX_HQD_VMID__VMID_MASK 0x0000000FL |
19147 | //CP_GFX_HQD_QUEUE_PRIORITY |
19148 | #define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 |
19149 | #define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL |
19150 | //CP_GFX_HQD_QUANTUM |
19151 | #define CP_GFX_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 |
19152 | #define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x3 |
19153 | #define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 |
19154 | #define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f |
19155 | #define CP_GFX_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L |
19156 | #define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000018L |
19157 | #define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x0000FF00L |
19158 | #define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L |
19159 | //CP_GFX_HQD_BASE |
19160 | #define CP_GFX_HQD_BASE__RB_BASE__SHIFT 0x0 |
19161 | #define CP_GFX_HQD_BASE__RB_BASE_MASK 0xFFFFFFFFL |
19162 | //CP_GFX_HQD_BASE_HI |
19163 | #define CP_GFX_HQD_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
19164 | #define CP_GFX_HQD_BASE_HI__RB_BASE_HI_MASK 0x000000FFL |
19165 | //CP_GFX_HQD_RPTR |
19166 | #define CP_GFX_HQD_RPTR__RB_RPTR__SHIFT 0x0 |
19167 | #define CP_GFX_HQD_RPTR__RB_RPTR_MASK 0x000FFFFFL |
19168 | //CP_GFX_HQD_RPTR_ADDR |
19169 | #define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
19170 | #define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
19171 | //CP_GFX_HQD_RPTR_ADDR_HI |
19172 | #define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
19173 | #define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
19174 | //CP_RB_WPTR_POLL_ADDR_LO |
19175 | #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 |
19176 | #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL |
19177 | //CP_RB_WPTR_POLL_ADDR_HI |
19178 | #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 |
19179 | #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL |
19180 | //CP_RB_DOORBELL_CONTROL |
19181 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 |
19182 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 |
19183 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e |
19184 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f |
19185 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L |
19186 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
19187 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L |
19188 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L |
19189 | //CP_GFX_HQD_OFFSET |
19190 | #define CP_GFX_HQD_OFFSET__RB_OFFSET__SHIFT 0x0 |
19191 | #define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET__SHIFT 0x1f |
19192 | #define CP_GFX_HQD_OFFSET__RB_OFFSET_MASK 0x000FFFFFL |
19193 | #define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET_MASK 0x80000000L |
19194 | //CP_GFX_HQD_CNTL |
19195 | #define CP_GFX_HQD_CNTL__RB_BUFSZ__SHIFT 0x0 |
19196 | #define CP_GFX_HQD_CNTL__RB_BLKSZ__SHIFT 0x8 |
19197 | #define CP_GFX_HQD_CNTL__BUF_SWAP__SHIFT 0x10 |
19198 | #define CP_GFX_HQD_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
19199 | #define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
19200 | #define CP_GFX_HQD_CNTL__CACHE_POLICY__SHIFT 0x18 |
19201 | #define CP_GFX_HQD_CNTL__RB_VOLATILE__SHIFT 0x1a |
19202 | #define CP_GFX_HQD_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
19203 | #define CP_GFX_HQD_CNTL__RB_EXE__SHIFT 0x1c |
19204 | #define CP_GFX_HQD_CNTL__KMD_QUEUE__SHIFT 0x1d |
19205 | #define CP_GFX_HQD_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e |
19206 | #define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
19207 | #define CP_GFX_HQD_CNTL__RB_BUFSZ_MASK 0x0000003FL |
19208 | #define CP_GFX_HQD_CNTL__RB_BLKSZ_MASK 0x00003F00L |
19209 | #define CP_GFX_HQD_CNTL__BUF_SWAP_MASK 0x00030000L |
19210 | #define CP_GFX_HQD_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
19211 | #define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
19212 | #define CP_GFX_HQD_CNTL__CACHE_POLICY_MASK 0x03000000L |
19213 | #define CP_GFX_HQD_CNTL__RB_VOLATILE_MASK 0x04000000L |
19214 | #define CP_GFX_HQD_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
19215 | #define CP_GFX_HQD_CNTL__RB_EXE_MASK 0x10000000L |
19216 | #define CP_GFX_HQD_CNTL__KMD_QUEUE_MASK 0x20000000L |
19217 | #define CP_GFX_HQD_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L |
19218 | #define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
19219 | //CP_GFX_HQD_CSMD_RPTR |
19220 | #define CP_GFX_HQD_CSMD_RPTR__RB_RPTR__SHIFT 0x0 |
19221 | #define CP_GFX_HQD_CSMD_RPTR__RB_RPTR_MASK 0x000FFFFFL |
19222 | //CP_GFX_HQD_WPTR |
19223 | #define CP_GFX_HQD_WPTR__RB_WPTR__SHIFT 0x0 |
19224 | #define CP_GFX_HQD_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
19225 | //CP_GFX_HQD_WPTR_HI |
19226 | #define CP_GFX_HQD_WPTR_HI__RB_WPTR__SHIFT 0x0 |
19227 | #define CP_GFX_HQD_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
19228 | //CP_GFX_HQD_DEQUEUE_REQUEST |
19229 | #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 |
19230 | #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 |
19231 | #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 |
19232 | #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa |
19233 | #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000001L |
19234 | #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L |
19235 | #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L |
19236 | #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L |
19237 | //CP_GFX_HQD_MAPPED |
19238 | #define CP_GFX_HQD_MAPPED__MAPPED__SHIFT 0x0 |
19239 | #define CP_GFX_HQD_MAPPED__MAPPED_MASK 0x00000001L |
19240 | //CP_GFX_HQD_QUE_MGR_CONTROL |
19241 | #define CP_GFX_HQD_QUE_MGR_CONTROL__CONTROL__SHIFT 0x0 |
19242 | #define CP_GFX_HQD_QUE_MGR_CONTROL__CONTROL_MASK 0x00FFFFFFL |
19243 | //CP_GFX_HQD_HQ_STATUS0 |
19244 | #define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 |
19245 | #define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS__SHIFT 0x4 |
19246 | #define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK__SHIFT 0x6 |
19247 | #define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e |
19248 | #define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000001L |
19249 | #define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS_MASK 0x00000030L |
19250 | #define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK_MASK 0x00000040L |
19251 | #define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L |
19252 | //CP_GFX_HQD_HQ_CONTROL0 |
19253 | #define CP_GFX_HQD_HQ_CONTROL0__COMMAND__SHIFT 0x0 |
19254 | #define CP_GFX_HQD_HQ_CONTROL0__COMMAND_MASK 0x0000000FL |
19255 | //CP_GFX_MQD_CONTROL |
19256 | #define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0 |
19257 | #define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 |
19258 | #define CP_GFX_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc |
19259 | #define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd |
19260 | #define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 |
19261 | #define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 |
19262 | #define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL |
19263 | #define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L |
19264 | #define CP_GFX_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L |
19265 | #define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L |
19266 | #define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L |
19267 | #define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x03000000L |
19268 | //CP_HQD_GFX_CONTROL |
19269 | #define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0 |
19270 | #define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4 |
19271 | #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf |
19272 | #define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL |
19273 | #define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L |
19274 | #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L |
19275 | //CP_HQD_GFX_STATUS |
19276 | #define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0 |
19277 | #define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL |
19278 | //CP_GFX_HQD_CE_RPTR_WR |
19279 | #define CP_GFX_HQD_CE_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 |
19280 | #define CP_GFX_HQD_CE_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL |
19281 | //CP_GFX_HQD_CE_BASE |
19282 | #define CP_GFX_HQD_CE_BASE__RB_BASE__SHIFT 0x0 |
19283 | #define CP_GFX_HQD_CE_BASE__RB_BASE_MASK 0xFFFFFFFFL |
19284 | //CP_GFX_HQD_CE_BASE_HI |
19285 | #define CP_GFX_HQD_CE_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
19286 | #define CP_GFX_HQD_CE_BASE_HI__RB_BASE_HI_MASK 0x000000FFL |
19287 | //CP_GFX_HQD_CE_RPTR |
19288 | #define CP_GFX_HQD_CE_RPTR__RB_RPTR__SHIFT 0x0 |
19289 | #define CP_GFX_HQD_CE_RPTR__RB_RPTR_MASK 0x000FFFFFL |
19290 | //CP_GFX_HQD_CE_RPTR_ADDR |
19291 | #define CP_GFX_HQD_CE_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
19292 | #define CP_GFX_HQD_CE_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
19293 | //CP_GFX_HQD_CE_RPTR_ADDR_HI |
19294 | #define CP_GFX_HQD_CE_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
19295 | #define CP_GFX_HQD_CE_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
19296 | //CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO |
19297 | #define CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 |
19298 | #define CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL |
19299 | //CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI |
19300 | #define CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 |
19301 | #define CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL |
19302 | //CP_GFX_HQD_CE_OFFSET |
19303 | #define CP_GFX_HQD_CE_OFFSET__RB_OFFSET__SHIFT 0x0 |
19304 | #define CP_GFX_HQD_CE_OFFSET__DISABLE_RB_OFFSET__SHIFT 0x1f |
19305 | #define CP_GFX_HQD_CE_OFFSET__RB_OFFSET_MASK 0x000FFFFFL |
19306 | #define CP_GFX_HQD_CE_OFFSET__DISABLE_RB_OFFSET_MASK 0x80000000L |
19307 | //CP_GFX_HQD_CE_CNTL |
19308 | #define CP_GFX_HQD_CE_CNTL__RB_BUFSZ__SHIFT 0x0 |
19309 | #define CP_GFX_HQD_CE_CNTL__RB_BLKSZ__SHIFT 0x8 |
19310 | #define CP_GFX_HQD_CE_CNTL__BUF_SWAP__SHIFT 0x10 |
19311 | #define CP_GFX_HQD_CE_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
19312 | #define CP_GFX_HQD_CE_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
19313 | #define CP_GFX_HQD_CE_CNTL__CACHE_POLICY__SHIFT 0x18 |
19314 | #define CP_GFX_HQD_CE_CNTL__RB_VOLATILE__SHIFT 0x1a |
19315 | #define CP_GFX_HQD_CE_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
19316 | #define CP_GFX_HQD_CE_CNTL__RB_EXE__SHIFT 0x1c |
19317 | #define CP_GFX_HQD_CE_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
19318 | #define CP_GFX_HQD_CE_CNTL__RB_BUFSZ_MASK 0x0000003FL |
19319 | #define CP_GFX_HQD_CE_CNTL__RB_BLKSZ_MASK 0x00003F00L |
19320 | #define CP_GFX_HQD_CE_CNTL__BUF_SWAP_MASK 0x00030000L |
19321 | #define CP_GFX_HQD_CE_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
19322 | #define CP_GFX_HQD_CE_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
19323 | #define CP_GFX_HQD_CE_CNTL__CACHE_POLICY_MASK 0x03000000L |
19324 | #define CP_GFX_HQD_CE_CNTL__RB_VOLATILE_MASK 0x04000000L |
19325 | #define CP_GFX_HQD_CE_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
19326 | #define CP_GFX_HQD_CE_CNTL__RB_EXE_MASK 0x10000000L |
19327 | #define CP_GFX_HQD_CE_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
19328 | //CP_GFX_HQD_CE_CSMD_RPTR |
19329 | #define CP_GFX_HQD_CE_CSMD_RPTR__RB_RPTR__SHIFT 0x0 |
19330 | #define CP_GFX_HQD_CE_CSMD_RPTR__RB_RPTR_MASK 0x000FFFFFL |
19331 | //CP_GFX_HQD_CE_WPTR |
19332 | #define CP_GFX_HQD_CE_WPTR__RB_WPTR__SHIFT 0x0 |
19333 | #define CP_GFX_HQD_CE_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
19334 | //CP_GFX_HQD_CE_WPTR_HI |
19335 | #define CP_GFX_HQD_CE_WPTR_HI__RB_WPTR__SHIFT 0x0 |
19336 | #define CP_GFX_HQD_CE_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
19337 | //CP_CE_DOORBELL_CONTROL |
19338 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 |
19339 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 |
19340 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e |
19341 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f |
19342 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L |
19343 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
19344 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L |
19345 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L |
19346 | //CP_DMA_WATCH0_ADDR_LO |
19347 | #define CP_DMA_WATCH0_ADDR_LO__RSVD__SHIFT 0x0 |
19348 | #define CP_DMA_WATCH0_ADDR_LO__ADDR_LO__SHIFT 0x7 |
19349 | #define CP_DMA_WATCH0_ADDR_LO__RSVD_MASK 0x0000007FL |
19350 | #define CP_DMA_WATCH0_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L |
19351 | //CP_DMA_WATCH0_ADDR_HI |
19352 | #define CP_DMA_WATCH0_ADDR_HI__ADDR_HI__SHIFT 0x0 |
19353 | #define CP_DMA_WATCH0_ADDR_HI__RSVD__SHIFT 0x10 |
19354 | #define CP_DMA_WATCH0_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
19355 | #define CP_DMA_WATCH0_ADDR_HI__RSVD_MASK 0xFFFF0000L |
19356 | //CP_DMA_WATCH0_MASK |
19357 | #define CP_DMA_WATCH0_MASK__RSVD__SHIFT 0x0 |
19358 | #define CP_DMA_WATCH0_MASK__MASK__SHIFT 0x7 |
19359 | #define CP_DMA_WATCH0_MASK__RSVD_MASK 0x0000007FL |
19360 | #define CP_DMA_WATCH0_MASK__MASK_MASK 0xFFFFFF80L |
19361 | //CP_DMA_WATCH0_CNTL |
19362 | #define CP_DMA_WATCH0_CNTL__VMID__SHIFT 0x0 |
19363 | #define CP_DMA_WATCH0_CNTL__RSVD1__SHIFT 0x4 |
19364 | #define CP_DMA_WATCH0_CNTL__WATCH_READS__SHIFT 0x8 |
19365 | #define CP_DMA_WATCH0_CNTL__WATCH_WRITES__SHIFT 0x9 |
19366 | #define CP_DMA_WATCH0_CNTL__ANY_VMID__SHIFT 0xa |
19367 | #define CP_DMA_WATCH0_CNTL__RSVD2__SHIFT 0xb |
19368 | #define CP_DMA_WATCH0_CNTL__VMID_MASK 0x0000000FL |
19369 | #define CP_DMA_WATCH0_CNTL__RSVD1_MASK 0x000000F0L |
19370 | #define CP_DMA_WATCH0_CNTL__WATCH_READS_MASK 0x00000100L |
19371 | #define CP_DMA_WATCH0_CNTL__WATCH_WRITES_MASK 0x00000200L |
19372 | #define CP_DMA_WATCH0_CNTL__ANY_VMID_MASK 0x00000400L |
19373 | #define CP_DMA_WATCH0_CNTL__RSVD2_MASK 0xFFFFF800L |
19374 | //CP_DMA_WATCH1_ADDR_LO |
19375 | #define CP_DMA_WATCH1_ADDR_LO__RSVD__SHIFT 0x0 |
19376 | #define CP_DMA_WATCH1_ADDR_LO__ADDR_LO__SHIFT 0x7 |
19377 | #define CP_DMA_WATCH1_ADDR_LO__RSVD_MASK 0x0000007FL |
19378 | #define CP_DMA_WATCH1_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L |
19379 | //CP_DMA_WATCH1_ADDR_HI |
19380 | #define CP_DMA_WATCH1_ADDR_HI__ADDR_HI__SHIFT 0x0 |
19381 | #define CP_DMA_WATCH1_ADDR_HI__RSVD__SHIFT 0x10 |
19382 | #define CP_DMA_WATCH1_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
19383 | #define CP_DMA_WATCH1_ADDR_HI__RSVD_MASK 0xFFFF0000L |
19384 | //CP_DMA_WATCH1_MASK |
19385 | #define CP_DMA_WATCH1_MASK__RSVD__SHIFT 0x0 |
19386 | #define CP_DMA_WATCH1_MASK__MASK__SHIFT 0x7 |
19387 | #define CP_DMA_WATCH1_MASK__RSVD_MASK 0x0000007FL |
19388 | #define CP_DMA_WATCH1_MASK__MASK_MASK 0xFFFFFF80L |
19389 | //CP_DMA_WATCH1_CNTL |
19390 | #define CP_DMA_WATCH1_CNTL__VMID__SHIFT 0x0 |
19391 | #define CP_DMA_WATCH1_CNTL__RSVD1__SHIFT 0x4 |
19392 | #define CP_DMA_WATCH1_CNTL__WATCH_READS__SHIFT 0x8 |
19393 | #define CP_DMA_WATCH1_CNTL__WATCH_WRITES__SHIFT 0x9 |
19394 | #define CP_DMA_WATCH1_CNTL__ANY_VMID__SHIFT 0xa |
19395 | #define CP_DMA_WATCH1_CNTL__RSVD2__SHIFT 0xb |
19396 | #define CP_DMA_WATCH1_CNTL__VMID_MASK 0x0000000FL |
19397 | #define CP_DMA_WATCH1_CNTL__RSVD1_MASK 0x000000F0L |
19398 | #define CP_DMA_WATCH1_CNTL__WATCH_READS_MASK 0x00000100L |
19399 | #define CP_DMA_WATCH1_CNTL__WATCH_WRITES_MASK 0x00000200L |
19400 | #define CP_DMA_WATCH1_CNTL__ANY_VMID_MASK 0x00000400L |
19401 | #define CP_DMA_WATCH1_CNTL__RSVD2_MASK 0xFFFFF800L |
19402 | //CP_DMA_WATCH2_ADDR_LO |
19403 | #define CP_DMA_WATCH2_ADDR_LO__RSVD__SHIFT 0x0 |
19404 | #define CP_DMA_WATCH2_ADDR_LO__ADDR_LO__SHIFT 0x7 |
19405 | #define CP_DMA_WATCH2_ADDR_LO__RSVD_MASK 0x0000007FL |
19406 | #define CP_DMA_WATCH2_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L |
19407 | //CP_DMA_WATCH2_ADDR_HI |
19408 | #define CP_DMA_WATCH2_ADDR_HI__ADDR_HI__SHIFT 0x0 |
19409 | #define CP_DMA_WATCH2_ADDR_HI__RSVD__SHIFT 0x10 |
19410 | #define CP_DMA_WATCH2_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
19411 | #define CP_DMA_WATCH2_ADDR_HI__RSVD_MASK 0xFFFF0000L |
19412 | //CP_DMA_WATCH2_MASK |
19413 | #define CP_DMA_WATCH2_MASK__RSVD__SHIFT 0x0 |
19414 | #define CP_DMA_WATCH2_MASK__MASK__SHIFT 0x7 |
19415 | #define CP_DMA_WATCH2_MASK__RSVD_MASK 0x0000007FL |
19416 | #define CP_DMA_WATCH2_MASK__MASK_MASK 0xFFFFFF80L |
19417 | //CP_DMA_WATCH2_CNTL |
19418 | #define CP_DMA_WATCH2_CNTL__VMID__SHIFT 0x0 |
19419 | #define CP_DMA_WATCH2_CNTL__RSVD1__SHIFT 0x4 |
19420 | #define CP_DMA_WATCH2_CNTL__WATCH_READS__SHIFT 0x8 |
19421 | #define CP_DMA_WATCH2_CNTL__WATCH_WRITES__SHIFT 0x9 |
19422 | #define CP_DMA_WATCH2_CNTL__ANY_VMID__SHIFT 0xa |
19423 | #define CP_DMA_WATCH2_CNTL__RSVD2__SHIFT 0xb |
19424 | #define CP_DMA_WATCH2_CNTL__VMID_MASK 0x0000000FL |
19425 | #define CP_DMA_WATCH2_CNTL__RSVD1_MASK 0x000000F0L |
19426 | #define CP_DMA_WATCH2_CNTL__WATCH_READS_MASK 0x00000100L |
19427 | #define CP_DMA_WATCH2_CNTL__WATCH_WRITES_MASK 0x00000200L |
19428 | #define CP_DMA_WATCH2_CNTL__ANY_VMID_MASK 0x00000400L |
19429 | #define CP_DMA_WATCH2_CNTL__RSVD2_MASK 0xFFFFF800L |
19430 | //CP_DMA_WATCH3_ADDR_LO |
19431 | #define CP_DMA_WATCH3_ADDR_LO__RSVD__SHIFT 0x0 |
19432 | #define CP_DMA_WATCH3_ADDR_LO__ADDR_LO__SHIFT 0x7 |
19433 | #define CP_DMA_WATCH3_ADDR_LO__RSVD_MASK 0x0000007FL |
19434 | #define CP_DMA_WATCH3_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L |
19435 | //CP_DMA_WATCH3_ADDR_HI |
19436 | #define CP_DMA_WATCH3_ADDR_HI__ADDR_HI__SHIFT 0x0 |
19437 | #define CP_DMA_WATCH3_ADDR_HI__RSVD__SHIFT 0x10 |
19438 | #define CP_DMA_WATCH3_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
19439 | #define CP_DMA_WATCH3_ADDR_HI__RSVD_MASK 0xFFFF0000L |
19440 | //CP_DMA_WATCH3_MASK |
19441 | #define CP_DMA_WATCH3_MASK__RSVD__SHIFT 0x0 |
19442 | #define CP_DMA_WATCH3_MASK__MASK__SHIFT 0x7 |
19443 | #define CP_DMA_WATCH3_MASK__RSVD_MASK 0x0000007FL |
19444 | #define CP_DMA_WATCH3_MASK__MASK_MASK 0xFFFFFF80L |
19445 | //CP_DMA_WATCH3_CNTL |
19446 | #define CP_DMA_WATCH3_CNTL__VMID__SHIFT 0x0 |
19447 | #define CP_DMA_WATCH3_CNTL__RSVD1__SHIFT 0x4 |
19448 | #define CP_DMA_WATCH3_CNTL__WATCH_READS__SHIFT 0x8 |
19449 | #define CP_DMA_WATCH3_CNTL__WATCH_WRITES__SHIFT 0x9 |
19450 | #define CP_DMA_WATCH3_CNTL__ANY_VMID__SHIFT 0xa |
19451 | #define CP_DMA_WATCH3_CNTL__RSVD2__SHIFT 0xb |
19452 | #define CP_DMA_WATCH3_CNTL__VMID_MASK 0x0000000FL |
19453 | #define CP_DMA_WATCH3_CNTL__RSVD1_MASK 0x000000F0L |
19454 | #define CP_DMA_WATCH3_CNTL__WATCH_READS_MASK 0x00000100L |
19455 | #define CP_DMA_WATCH3_CNTL__WATCH_WRITES_MASK 0x00000200L |
19456 | #define CP_DMA_WATCH3_CNTL__ANY_VMID_MASK 0x00000400L |
19457 | #define CP_DMA_WATCH3_CNTL__RSVD2_MASK 0xFFFFF800L |
19458 | //CP_DMA_WATCH_STAT_ADDR_LO |
19459 | #define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO__SHIFT 0x2 |
19460 | #define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
19461 | //CP_DMA_WATCH_STAT_ADDR_HI |
19462 | #define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI__SHIFT 0x0 |
19463 | #define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
19464 | //CP_DMA_WATCH_STAT |
19465 | #define CP_DMA_WATCH_STAT__VMID__SHIFT 0x0 |
19466 | #define CP_DMA_WATCH_STAT__CLIENT_ID__SHIFT 0x8 |
19467 | #define CP_DMA_WATCH_STAT__PIPE__SHIFT 0xc |
19468 | #define CP_DMA_WATCH_STAT__WATCH_ID__SHIFT 0x10 |
19469 | #define CP_DMA_WATCH_STAT__RD_WR__SHIFT 0x14 |
19470 | #define CP_DMA_WATCH_STAT__TRAP_FLAG__SHIFT 0x1f |
19471 | #define CP_DMA_WATCH_STAT__VMID_MASK 0x0000000FL |
19472 | #define CP_DMA_WATCH_STAT__CLIENT_ID_MASK 0x00000700L |
19473 | #define CP_DMA_WATCH_STAT__PIPE_MASK 0x00003000L |
19474 | #define CP_DMA_WATCH_STAT__WATCH_ID_MASK 0x00030000L |
19475 | #define CP_DMA_WATCH_STAT__RD_WR_MASK 0x00100000L |
19476 | #define CP_DMA_WATCH_STAT__TRAP_FLAG_MASK 0x80000000L |
19477 | //CP_PFP_JT_STAT |
19478 | #define CP_PFP_JT_STAT__JT_LOADED__SHIFT 0x0 |
19479 | #define CP_PFP_JT_STAT__WR_MASK__SHIFT 0x10 |
19480 | #define CP_PFP_JT_STAT__JT_LOADED_MASK 0x00000003L |
19481 | #define CP_PFP_JT_STAT__WR_MASK_MASK 0x00030000L |
19482 | //CP_CE_JT_STAT |
19483 | #define CP_CE_JT_STAT__JT_LOADED__SHIFT 0x0 |
19484 | #define CP_CE_JT_STAT__WR_MASK__SHIFT 0x10 |
19485 | #define CP_CE_JT_STAT__JT_LOADED_MASK 0x00000003L |
19486 | #define CP_CE_JT_STAT__WR_MASK_MASK 0x00030000L |
19487 | //CP_MEC_JT_STAT |
19488 | #define CP_MEC_JT_STAT__JT_LOADED__SHIFT 0x0 |
19489 | #define CP_MEC_JT_STAT__WR_MASK__SHIFT 0x10 |
19490 | #define CP_MEC_JT_STAT__JT_LOADED_MASK 0x000000FFL |
19491 | #define CP_MEC_JT_STAT__WR_MASK_MASK 0x00FF0000L |
19492 | //CP_RB_DOORBELL_CLEAR |
19493 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0 |
19494 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8 |
19495 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9 |
19496 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa |
19497 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb |
19498 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc |
19499 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd |
19500 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L |
19501 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L |
19502 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L |
19503 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L |
19504 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L |
19505 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L |
19506 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L |
19507 | //CP_RB0_ACTIVE |
19508 | #define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0 |
19509 | #define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L |
19510 | //CP_RB_ACTIVE |
19511 | #define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0 |
19512 | #define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L |
19513 | //CP_RB1_ACTIVE |
19514 | #define CP_RB1_ACTIVE__ACTIVE__SHIFT 0x0 |
19515 | #define CP_RB1_ACTIVE__ACTIVE_MASK 0x00000001L |
19516 | //CP_RB_STATUS |
19517 | #define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0 |
19518 | #define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1 |
19519 | #define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L |
19520 | #define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L |
19521 | //CPG_RCIU_CAM_INDEX |
19522 | #define CPG_RCIU_CAM_INDEX__INDEX__SHIFT 0x0 |
19523 | #define CPG_RCIU_CAM_INDEX__INDEX_MASK 0x0000001FL |
19524 | //CPG_RCIU_CAM_DATA |
19525 | #define CPG_RCIU_CAM_DATA__DATA__SHIFT 0x0 |
19526 | #define CPG_RCIU_CAM_DATA__DATA_MASK 0xFFFFFFFFL |
19527 | //CPG_RCIU_CAM_DATA_PHASE0 |
19528 | #define CPG_RCIU_CAM_DATA_PHASE0__ADDR__SHIFT 0x0 |
19529 | #define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN__SHIFT 0x18 |
19530 | #define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN__SHIFT 0x19 |
19531 | #define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR__SHIFT 0x1f |
19532 | #define CPG_RCIU_CAM_DATA_PHASE0__ADDR_MASK 0x0003FFFFL |
19533 | #define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN_MASK 0x01000000L |
19534 | #define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN_MASK 0x02000000L |
19535 | #define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR_MASK 0x80000000L |
19536 | //CPG_RCIU_CAM_DATA_PHASE1 |
19537 | #define CPG_RCIU_CAM_DATA_PHASE1__MASK__SHIFT 0x0 |
19538 | #define CPG_RCIU_CAM_DATA_PHASE1__MASK_MASK 0xFFFFFFFFL |
19539 | //CPG_RCIU_CAM_DATA_PHASE2 |
19540 | #define CPG_RCIU_CAM_DATA_PHASE2__VALUE__SHIFT 0x0 |
19541 | #define CPG_RCIU_CAM_DATA_PHASE2__VALUE_MASK 0xFFFFFFFFL |
19542 | //CPF_GCR_CNTL |
19543 | #define CPF_GCR_CNTL__GCR_GL_CMD__SHIFT 0x0 |
19544 | #define CPF_GCR_CNTL__GCR_GL_CMD_MASK 0x0007FFFFL |
19545 | //CPG_UTCL1_STATUS |
19546 | #define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
19547 | #define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
19548 | #define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
19549 | #define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
19550 | #define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
19551 | #define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
19552 | #define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
19553 | #define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
19554 | #define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
19555 | #define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
19556 | #define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
19557 | #define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
19558 | //CPC_UTCL1_STATUS |
19559 | #define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
19560 | #define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
19561 | #define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
19562 | #define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
19563 | #define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
19564 | #define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
19565 | #define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
19566 | #define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
19567 | #define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
19568 | #define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
19569 | #define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
19570 | #define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
19571 | //CPF_UTCL1_STATUS |
19572 | #define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
19573 | #define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
19574 | #define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
19575 | #define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
19576 | #define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
19577 | #define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
19578 | #define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
19579 | #define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
19580 | #define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
19581 | #define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
19582 | #define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
19583 | #define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
19584 | //CP_SD_CNTL |
19585 | #define CP_SD_CNTL__CPF_EN__SHIFT 0x0 |
19586 | #define CP_SD_CNTL__CPG_EN__SHIFT 0x1 |
19587 | #define CP_SD_CNTL__CPC_EN__SHIFT 0x2 |
19588 | #define CP_SD_CNTL__RLC_EN__SHIFT 0x3 |
19589 | #define CP_SD_CNTL__SPI_EN__SHIFT 0x4 |
19590 | #define CP_SD_CNTL__GE_EN__SHIFT 0x5 |
19591 | #define CP_SD_CNTL__UTCL1_EN__SHIFT 0x6 |
19592 | #define CP_SD_CNTL__RMI_EN__SHIFT 0x8 |
19593 | #define CP_SD_CNTL__EA_EN__SHIFT 0x9 |
19594 | #define CP_SD_CNTL__SDMA_EN__SHIFT 0xa |
19595 | #define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE__SHIFT 0x1f |
19596 | #define CP_SD_CNTL__CPF_EN_MASK 0x00000001L |
19597 | #define CP_SD_CNTL__CPG_EN_MASK 0x00000002L |
19598 | #define CP_SD_CNTL__CPC_EN_MASK 0x00000004L |
19599 | #define CP_SD_CNTL__RLC_EN_MASK 0x00000008L |
19600 | #define CP_SD_CNTL__SPI_EN_MASK 0x00000010L |
19601 | #define CP_SD_CNTL__GE_EN_MASK 0x00000020L |
19602 | #define CP_SD_CNTL__UTCL1_EN_MASK 0x00000040L |
19603 | #define CP_SD_CNTL__RMI_EN_MASK 0x00000100L |
19604 | #define CP_SD_CNTL__EA_EN_MASK 0x00000200L |
19605 | #define CP_SD_CNTL__SDMA_EN_MASK 0x00000400L |
19606 | #define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE_MASK 0x80000000L |
19607 | //CP_SOFT_RESET_CNTL |
19608 | #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0 |
19609 | #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1 |
19610 | #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2 |
19611 | #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3 |
19612 | #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4 |
19613 | #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5 |
19614 | #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6 |
19615 | #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L |
19616 | #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L |
19617 | #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L |
19618 | #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L |
19619 | #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L |
19620 | #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L |
19621 | #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L |
19622 | //CP_CPC_GFX_CNTL |
19623 | #define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0 |
19624 | #define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3 |
19625 | #define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5 |
19626 | #define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7 |
19627 | #define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L |
19628 | #define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L |
19629 | #define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L |
19630 | #define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L |
19631 | |
19632 | |
19633 | // addressBlock: gc_spipdec |
19634 | //SPI_ARB_PRIORITY |
19635 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 |
19636 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 |
19637 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 |
19638 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 |
19639 | #define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc |
19640 | #define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe |
19641 | #define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 |
19642 | #define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 |
19643 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L |
19644 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L |
19645 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L |
19646 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L |
19647 | #define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L |
19648 | #define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L |
19649 | #define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L |
19650 | #define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L |
19651 | //SPI_ARB_CYCLES_0 |
19652 | #define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 |
19653 | #define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 |
19654 | #define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL |
19655 | #define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L |
19656 | //SPI_ARB_CYCLES_1 |
19657 | #define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 |
19658 | #define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 |
19659 | #define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL |
19660 | #define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L |
19661 | //SPI_WCL_PIPE_PERCENT_GFX |
19662 | #define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 |
19663 | #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7 |
19664 | #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc |
19665 | #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11 |
19666 | #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 |
19667 | #define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL |
19668 | #define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L |
19669 | #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L |
19670 | #define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L |
19671 | #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L |
19672 | //SPI_WCL_PIPE_PERCENT_HP3D |
19673 | #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 |
19674 | #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc |
19675 | #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 |
19676 | #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL |
19677 | #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L |
19678 | #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L |
19679 | //SPI_WCL_PIPE_PERCENT_CS0 |
19680 | #define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 |
19681 | #define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL |
19682 | //SPI_WCL_PIPE_PERCENT_CS1 |
19683 | #define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 |
19684 | #define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL |
19685 | //SPI_WCL_PIPE_PERCENT_CS2 |
19686 | #define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 |
19687 | #define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL |
19688 | //SPI_WCL_PIPE_PERCENT_CS3 |
19689 | #define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 |
19690 | #define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL |
19691 | //SPI_WCL_PIPE_PERCENT_CS4 |
19692 | #define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 |
19693 | #define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL |
19694 | //SPI_WCL_PIPE_PERCENT_CS5 |
19695 | #define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 |
19696 | #define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL |
19697 | //SPI_WCL_PIPE_PERCENT_CS6 |
19698 | #define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 |
19699 | #define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL |
19700 | //SPI_WCL_PIPE_PERCENT_CS7 |
19701 | #define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 |
19702 | #define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL |
19703 | //SPI_GDBG_WAVE_CNTL |
19704 | #define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 |
19705 | #define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1 |
19706 | #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L |
19707 | #define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x0001FFFEL |
19708 | //SPI_GDBG_TRAP_CONFIG |
19709 | #define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0 |
19710 | #define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2 |
19711 | #define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4 |
19712 | #define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7 |
19713 | #define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8 |
19714 | #define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9 |
19715 | #define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf |
19716 | #define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10 |
19717 | #define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x00000003L |
19718 | #define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0x0000000CL |
19719 | #define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x00000070L |
19720 | #define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x00000080L |
19721 | #define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x00000100L |
19722 | #define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x00000200L |
19723 | #define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x00008000L |
19724 | #define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xFFFF0000L |
19725 | //SPI_GDBG_TRAP_MASK |
19726 | #define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0 |
19727 | #define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9 |
19728 | #define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x01FFL |
19729 | #define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x0200L |
19730 | //SPI_GDBG_WAVE_CNTL2 |
19731 | #define SPI_GDBG_WAVE_CNTL2__VMID_MASK__SHIFT 0x0 |
19732 | #define SPI_GDBG_WAVE_CNTL2__MODE__SHIFT 0x10 |
19733 | #define SPI_GDBG_WAVE_CNTL2__VMID_MASK_MASK 0x0000FFFFL |
19734 | #define SPI_GDBG_WAVE_CNTL2__MODE_MASK 0x00030000L |
19735 | //SPI_GDBG_WAVE_CNTL3 |
19736 | #define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0 |
19737 | #define SPI_GDBG_WAVE_CNTL3__STALL_VS__SHIFT 0x1 |
19738 | #define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2 |
19739 | #define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3 |
19740 | #define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4 |
19741 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5 |
19742 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6 |
19743 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7 |
19744 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8 |
19745 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9 |
19746 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa |
19747 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb |
19748 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc |
19749 | #define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd |
19750 | #define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c |
19751 | #define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L |
19752 | #define SPI_GDBG_WAVE_CNTL3__STALL_VS_MASK 0x00000002L |
19753 | #define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L |
19754 | #define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L |
19755 | #define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L |
19756 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L |
19757 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L |
19758 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L |
19759 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L |
19760 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L |
19761 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L |
19762 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L |
19763 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L |
19764 | #define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L |
19765 | #define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L |
19766 | //SPI_GDBG_TRAP_DATA0 |
19767 | #define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0 |
19768 | #define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xFFFFFFFFL |
19769 | //SPI_GDBG_TRAP_DATA1 |
19770 | #define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0 |
19771 | #define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xFFFFFFFFL |
19772 | //SPI_COMPUTE_QUEUE_RESET |
19773 | #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 |
19774 | #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L |
19775 | //SPI_RESOURCE_RESERVE_CU_0 |
19776 | #define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 |
19777 | #define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 |
19778 | #define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 |
19779 | #define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc |
19780 | #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf |
19781 | #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL |
19782 | #define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L |
19783 | #define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L |
19784 | #define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L |
19785 | #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L |
19786 | //SPI_RESOURCE_RESERVE_CU_1 |
19787 | #define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 |
19788 | #define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 |
19789 | #define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 |
19790 | #define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc |
19791 | #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf |
19792 | #define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL |
19793 | #define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L |
19794 | #define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L |
19795 | #define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L |
19796 | #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L |
19797 | //SPI_RESOURCE_RESERVE_CU_2 |
19798 | #define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 |
19799 | #define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 |
19800 | #define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 |
19801 | #define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc |
19802 | #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf |
19803 | #define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL |
19804 | #define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L |
19805 | #define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L |
19806 | #define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L |
19807 | #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L |
19808 | //SPI_RESOURCE_RESERVE_CU_3 |
19809 | #define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 |
19810 | #define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 |
19811 | #define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 |
19812 | #define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc |
19813 | #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf |
19814 | #define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL |
19815 | #define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L |
19816 | #define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L |
19817 | #define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L |
19818 | #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L |
19819 | //SPI_RESOURCE_RESERVE_CU_4 |
19820 | #define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 |
19821 | #define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 |
19822 | #define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 |
19823 | #define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc |
19824 | #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf |
19825 | #define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL |
19826 | #define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L |
19827 | #define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L |
19828 | #define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L |
19829 | #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L |
19830 | //SPI_RESOURCE_RESERVE_CU_5 |
19831 | #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 |
19832 | #define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 |
19833 | #define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 |
19834 | #define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc |
19835 | #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf |
19836 | #define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL |
19837 | #define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L |
19838 | #define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L |
19839 | #define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L |
19840 | #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L |
19841 | //SPI_RESOURCE_RESERVE_CU_6 |
19842 | #define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 |
19843 | #define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 |
19844 | #define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 |
19845 | #define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc |
19846 | #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf |
19847 | #define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL |
19848 | #define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L |
19849 | #define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L |
19850 | #define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L |
19851 | #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L |
19852 | //SPI_RESOURCE_RESERVE_CU_7 |
19853 | #define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 |
19854 | #define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 |
19855 | #define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 |
19856 | #define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc |
19857 | #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf |
19858 | #define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL |
19859 | #define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L |
19860 | #define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L |
19861 | #define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L |
19862 | #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L |
19863 | //SPI_RESOURCE_RESERVE_CU_8 |
19864 | #define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 |
19865 | #define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 |
19866 | #define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 |
19867 | #define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc |
19868 | #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf |
19869 | #define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL |
19870 | #define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L |
19871 | #define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L |
19872 | #define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L |
19873 | #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L |
19874 | //SPI_RESOURCE_RESERVE_CU_9 |
19875 | #define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 |
19876 | #define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 |
19877 | #define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 |
19878 | #define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc |
19879 | #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf |
19880 | #define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL |
19881 | #define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L |
19882 | #define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L |
19883 | #define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L |
19884 | #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L |
19885 | //SPI_RESOURCE_RESERVE_EN_CU_0 |
19886 | #define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 |
19887 | #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 |
19888 | #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 |
19889 | #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 |
19890 | #define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L |
19891 | #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL |
19892 | #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L |
19893 | #define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L |
19894 | //SPI_RESOURCE_RESERVE_EN_CU_1 |
19895 | #define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 |
19896 | #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 |
19897 | #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 |
19898 | #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 |
19899 | #define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L |
19900 | #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL |
19901 | #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L |
19902 | #define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L |
19903 | //SPI_RESOURCE_RESERVE_EN_CU_2 |
19904 | #define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 |
19905 | #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 |
19906 | #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 |
19907 | #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 |
19908 | #define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L |
19909 | #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL |
19910 | #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L |
19911 | #define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L |
19912 | //SPI_RESOURCE_RESERVE_EN_CU_3 |
19913 | #define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 |
19914 | #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 |
19915 | #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 |
19916 | #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 |
19917 | #define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L |
19918 | #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL |
19919 | #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L |
19920 | #define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L |
19921 | //SPI_RESOURCE_RESERVE_EN_CU_4 |
19922 | #define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 |
19923 | #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 |
19924 | #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 |
19925 | #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 |
19926 | #define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L |
19927 | #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL |
19928 | #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L |
19929 | #define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L |
19930 | //SPI_RESOURCE_RESERVE_EN_CU_5 |
19931 | #define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 |
19932 | #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 |
19933 | #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 |
19934 | #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 |
19935 | #define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L |
19936 | #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL |
19937 | #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L |
19938 | #define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L |
19939 | //SPI_RESOURCE_RESERVE_EN_CU_6 |
19940 | #define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 |
19941 | #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 |
19942 | #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 |
19943 | #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 |
19944 | #define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L |
19945 | #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL |
19946 | #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L |
19947 | #define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L |
19948 | //SPI_RESOURCE_RESERVE_EN_CU_7 |
19949 | #define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 |
19950 | #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 |
19951 | #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 |
19952 | #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 |
19953 | #define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L |
19954 | #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL |
19955 | #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L |
19956 | #define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L |
19957 | //SPI_RESOURCE_RESERVE_EN_CU_8 |
19958 | #define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 |
19959 | #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 |
19960 | #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 |
19961 | #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 |
19962 | #define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L |
19963 | #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL |
19964 | #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L |
19965 | #define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L |
19966 | //SPI_RESOURCE_RESERVE_EN_CU_9 |
19967 | #define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 |
19968 | #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 |
19969 | #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 |
19970 | #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 |
19971 | #define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L |
19972 | #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL |
19973 | #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L |
19974 | #define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L |
19975 | //SPI_RESOURCE_RESERVE_CU_10 |
19976 | #define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 |
19977 | #define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 |
19978 | #define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 |
19979 | #define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc |
19980 | #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf |
19981 | #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL |
19982 | #define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L |
19983 | #define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L |
19984 | #define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L |
19985 | #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L |
19986 | //SPI_RESOURCE_RESERVE_CU_11 |
19987 | #define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 |
19988 | #define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 |
19989 | #define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 |
19990 | #define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc |
19991 | #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf |
19992 | #define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL |
19993 | #define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L |
19994 | #define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L |
19995 | #define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L |
19996 | #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L |
19997 | //SPI_RESOURCE_RESERVE_EN_CU_10 |
19998 | #define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 |
19999 | #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 |
20000 | #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 |
20001 | #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 |
20002 | #define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L |
20003 | #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL |
20004 | #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L |
20005 | #define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L |
20006 | //SPI_RESOURCE_RESERVE_EN_CU_11 |
20007 | #define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 |
20008 | #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 |
20009 | #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 |
20010 | #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 |
20011 | #define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L |
20012 | #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL |
20013 | #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L |
20014 | #define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L |
20015 | //SPI_RESOURCE_RESERVE_CU_12 |
20016 | #define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 |
20017 | #define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 |
20018 | #define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 |
20019 | #define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc |
20020 | #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf |
20021 | #define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL |
20022 | #define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L |
20023 | #define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L |
20024 | #define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L |
20025 | #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L |
20026 | //SPI_RESOURCE_RESERVE_CU_13 |
20027 | #define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 |
20028 | #define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 |
20029 | #define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 |
20030 | #define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc |
20031 | #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf |
20032 | #define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL |
20033 | #define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L |
20034 | #define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L |
20035 | #define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L |
20036 | #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L |
20037 | //SPI_RESOURCE_RESERVE_CU_14 |
20038 | #define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 |
20039 | #define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 |
20040 | #define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 |
20041 | #define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc |
20042 | #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf |
20043 | #define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL |
20044 | #define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L |
20045 | #define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L |
20046 | #define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L |
20047 | #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L |
20048 | //SPI_RESOURCE_RESERVE_CU_15 |
20049 | #define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 |
20050 | #define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 |
20051 | #define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 |
20052 | #define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc |
20053 | #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf |
20054 | #define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL |
20055 | #define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L |
20056 | #define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L |
20057 | #define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L |
20058 | #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L |
20059 | //SPI_RESOURCE_RESERVE_EN_CU_12 |
20060 | #define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 |
20061 | #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 |
20062 | #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 |
20063 | #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18 |
20064 | #define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L |
20065 | #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL |
20066 | #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L |
20067 | #define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L |
20068 | //SPI_RESOURCE_RESERVE_EN_CU_13 |
20069 | #define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 |
20070 | #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 |
20071 | #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 |
20072 | #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18 |
20073 | #define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L |
20074 | #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL |
20075 | #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L |
20076 | #define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L |
20077 | //SPI_RESOURCE_RESERVE_EN_CU_14 |
20078 | #define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 |
20079 | #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 |
20080 | #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 |
20081 | #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18 |
20082 | #define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L |
20083 | #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL |
20084 | #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L |
20085 | #define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L |
20086 | //SPI_RESOURCE_RESERVE_EN_CU_15 |
20087 | #define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 |
20088 | #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 |
20089 | #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 |
20090 | #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18 |
20091 | #define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L |
20092 | #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL |
20093 | #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L |
20094 | #define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L |
20095 | //SPI_COMPUTE_WF_CTX_SAVE |
20096 | #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 |
20097 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 |
20098 | #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 |
20099 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e |
20100 | #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f |
20101 | #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L |
20102 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L |
20103 | #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L |
20104 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L |
20105 | #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L |
20106 | //SPI_ARB_CNTL_0 |
20107 | #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0 |
20108 | #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4 |
20109 | #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8 |
20110 | #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL |
20111 | #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L |
20112 | #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L |
20113 | //SPI_FEATURE_CTRL |
20114 | #define SPI_FEATURE_CTRL__CU_LOCKING_FAIRNESS_DISABLE__SHIFT 0x0 |
20115 | #define SPI_FEATURE_CTRL__ALLOCATION_RATE_THROTTLE_THRESHOLD__SHIFT 0x2 |
20116 | #define SPI_FEATURE_CTRL__ACTIVE_HARD_LOCK_LIMIT__SHIFT 0x7 |
20117 | #define SPI_FEATURE_CTRL__LR_IMBALANCE_THRESHOLD__SHIFT 0xc |
20118 | #define SPI_FEATURE_CTRL__RA_PIPE_DEPTH_THRESHOLD_ALLOC_STALL_EN__SHIFT 0x12 |
20119 | #define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_ALLOC_STALL_EN__SHIFT 0x13 |
20120 | #define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD__SHIFT 0x14 |
20121 | #define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT__SHIFT 0x1c |
20122 | #define SPI_FEATURE_CTRL__CU_LOCKING_FAIRNESS_DISABLE_MASK 0x00000001L |
20123 | #define SPI_FEATURE_CTRL__ALLOCATION_RATE_THROTTLE_THRESHOLD_MASK 0x0000007CL |
20124 | #define SPI_FEATURE_CTRL__ACTIVE_HARD_LOCK_LIMIT_MASK 0x00000F80L |
20125 | #define SPI_FEATURE_CTRL__LR_IMBALANCE_THRESHOLD_MASK 0x0003F000L |
20126 | #define SPI_FEATURE_CTRL__RA_PIPE_DEPTH_THRESHOLD_ALLOC_STALL_EN_MASK 0x00040000L |
20127 | #define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_ALLOC_STALL_EN_MASK 0x00080000L |
20128 | #define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_MASK 0x0FF00000L |
20129 | #define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT_MASK 0xF0000000L |
20130 | //SPI_SHADER_RSRC_LIMIT_CTRL |
20131 | #define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32__SHIFT 0x0 |
20132 | #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32__SHIFT 0x5 |
20133 | #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE__SHIFT 0xc |
20134 | #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT__SHIFT 0xd |
20135 | #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL__SHIFT 0x13 |
20136 | #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT__SHIFT 0x14 |
20137 | #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL__SHIFT 0x1c |
20138 | #define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE__SHIFT 0x1f |
20139 | #define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32_MASK 0x0000001FL |
20140 | #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32_MASK 0x00000FE0L |
20141 | #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE_MASK 0x00001000L |
20142 | #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_MASK 0x0007E000L |
20143 | #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL_MASK 0x00080000L |
20144 | #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_MASK 0x0FF00000L |
20145 | #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL_MASK 0x10000000L |
20146 | #define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE_MASK 0x80000000L |
20147 | |
20148 | |
20149 | // addressBlock: gc_cpphqddec |
20150 | //CP_HPD_MES_ROQ_OFFSETS |
20151 | #define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 |
20152 | #define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 |
20153 | #define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 |
20154 | #define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L |
20155 | #define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L |
20156 | #define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET_MASK 0x007F0000L |
20157 | //CP_HPD_ROQ_OFFSETS |
20158 | #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 |
20159 | #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 |
20160 | #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 |
20161 | #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L |
20162 | #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L |
20163 | #define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x007F0000L |
20164 | //CP_HPD_STATUS0 |
20165 | #define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 |
20166 | #define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 |
20167 | #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 |
20168 | #define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10 |
20169 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11 |
20170 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12 |
20171 | #define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 |
20172 | #define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS__SHIFT 0x1b |
20173 | #define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT 0x1c |
20174 | #define CP_HPD_STATUS0__FREEZE_QUEUE_STATE__SHIFT 0x1e |
20175 | #define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f |
20176 | #define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL |
20177 | #define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L |
20178 | #define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L |
20179 | #define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L |
20180 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L |
20181 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L |
20182 | #define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L |
20183 | #define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS_MASK 0x08000000L |
20184 | #define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK 0x30000000L |
20185 | #define CP_HPD_STATUS0__FREEZE_QUEUE_STATE_MASK 0x40000000L |
20186 | #define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L |
20187 | //CP_HPD_UTCL1_CNTL |
20188 | #define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0 |
20189 | #define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL |
20190 | //CP_HPD_UTCL1_ERROR |
20191 | #define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0 |
20192 | #define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10 |
20193 | #define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14 |
20194 | #define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL |
20195 | #define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L |
20196 | #define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L |
20197 | //CP_HPD_UTCL1_ERROR_ADDR |
20198 | #define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc |
20199 | #define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L |
20200 | //CP_MQD_BASE_ADDR |
20201 | #define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 |
20202 | #define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL |
20203 | //CP_MQD_BASE_ADDR_HI |
20204 | #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
20205 | #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL |
20206 | //CP_HQD_ACTIVE |
20207 | #define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 |
20208 | #define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 |
20209 | #define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L |
20210 | #define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L |
20211 | //CP_HQD_VMID |
20212 | #define CP_HQD_VMID__VMID__SHIFT 0x0 |
20213 | #define CP_HQD_VMID__IB_VMID__SHIFT 0x8 |
20214 | #define CP_HQD_VMID__VQID__SHIFT 0x10 |
20215 | #define CP_HQD_VMID__VMID_MASK 0x0000000FL |
20216 | #define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L |
20217 | #define CP_HQD_VMID__VQID_MASK 0x03FF0000L |
20218 | //CP_HQD_PERSISTENT_STATE |
20219 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 |
20220 | #define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS__SHIFT 0x7 |
20221 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 |
20222 | #define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN__SHIFT 0x14 |
20223 | #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15 |
20224 | #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16 |
20225 | #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17 |
20226 | #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18 |
20227 | #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19 |
20228 | #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a |
20229 | #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b |
20230 | #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c |
20231 | #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d |
20232 | #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e |
20233 | #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f |
20234 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L |
20235 | #define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS_MASK 0x00000080L |
20236 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L |
20237 | #define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN_MASK 0x00100000L |
20238 | #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L |
20239 | #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L |
20240 | #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L |
20241 | #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L |
20242 | #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L |
20243 | #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L |
20244 | #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L |
20245 | #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L |
20246 | #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L |
20247 | #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L |
20248 | #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L |
20249 | //CP_HQD_PIPE_PRIORITY |
20250 | #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 |
20251 | #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L |
20252 | //CP_HQD_QUEUE_PRIORITY |
20253 | #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 |
20254 | #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL |
20255 | //CP_HQD_QUANTUM |
20256 | #define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 |
20257 | #define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 |
20258 | #define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 |
20259 | #define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f |
20260 | #define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L |
20261 | #define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L |
20262 | #define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L |
20263 | #define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L |
20264 | //CP_HQD_PQ_BASE |
20265 | #define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 |
20266 | #define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL |
20267 | //CP_HQD_PQ_BASE_HI |
20268 | #define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 |
20269 | #define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL |
20270 | //CP_HQD_PQ_RPTR |
20271 | #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 |
20272 | #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL |
20273 | //CP_HQD_PQ_RPTR_REPORT_ADDR |
20274 | #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 |
20275 | #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL |
20276 | //CP_HQD_PQ_RPTR_REPORT_ADDR_HI |
20277 | #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 |
20278 | #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL |
20279 | //CP_HQD_PQ_WPTR_POLL_ADDR |
20280 | #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3 |
20281 | #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L |
20282 | //CP_HQD_PQ_WPTR_POLL_ADDR_HI |
20283 | #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 |
20284 | #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL |
20285 | //CP_HQD_PQ_DOORBELL_CONTROL |
20286 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 |
20287 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 |
20288 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 |
20289 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c |
20290 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d |
20291 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e |
20292 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f |
20293 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L |
20294 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L |
20295 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
20296 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L |
20297 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L |
20298 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L |
20299 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L |
20300 | //CP_HQD_PQ_CONTROL |
20301 | #define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 |
20302 | #define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6 |
20303 | #define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7 |
20304 | #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 |
20305 | #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe |
20306 | #define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf |
20307 | #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x10 |
20308 | #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x12 |
20309 | #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 |
20310 | #define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17 |
20311 | #define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 |
20312 | #define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT 0x1a |
20313 | #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b |
20314 | #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c |
20315 | #define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH__SHIFT 0x1d |
20316 | #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e |
20317 | #define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f |
20318 | #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL |
20319 | #define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L |
20320 | #define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L |
20321 | #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L |
20322 | #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L |
20323 | #define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L |
20324 | #define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00030000L |
20325 | #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x000C0000L |
20326 | #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L |
20327 | #define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L |
20328 | #define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x03000000L |
20329 | #define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK 0x04000000L |
20330 | #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L |
20331 | #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L |
20332 | #define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH_MASK 0x20000000L |
20333 | #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L |
20334 | #define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L |
20335 | //CP_HQD_IB_BASE_ADDR |
20336 | #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 |
20337 | #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL |
20338 | //CP_HQD_IB_BASE_ADDR_HI |
20339 | #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 |
20340 | #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL |
20341 | //CP_HQD_IB_RPTR |
20342 | #define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 |
20343 | #define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL |
20344 | //CP_HQD_IB_CONTROL |
20345 | #define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 |
20346 | #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 |
20347 | #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17 |
20348 | #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 |
20349 | #define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT 0x1a |
20350 | #define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f |
20351 | #define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL |
20352 | #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L |
20353 | #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L |
20354 | #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x03000000L |
20355 | #define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK 0x04000000L |
20356 | #define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L |
20357 | //CP_HQD_IQ_TIMER |
20358 | #define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 |
20359 | #define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 |
20360 | #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb |
20361 | #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc |
20362 | #define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe |
20363 | #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 |
20364 | #define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 |
20365 | #define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17 |
20366 | #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 |
20367 | #define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT 0x1a |
20368 | #define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x1b |
20369 | #define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c |
20370 | #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d |
20371 | #define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e |
20372 | #define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f |
20373 | #define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL |
20374 | #define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L |
20375 | #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L |
20376 | #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L |
20377 | #define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L |
20378 | #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L |
20379 | #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L |
20380 | #define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L |
20381 | #define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x03000000L |
20382 | #define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK 0x04000000L |
20383 | #define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x08000000L |
20384 | #define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L |
20385 | #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L |
20386 | #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L |
20387 | #define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L |
20388 | //CP_HQD_IQ_RPTR |
20389 | #define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 |
20390 | #define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL |
20391 | //CP_HQD_DEQUEUE_REQUEST |
20392 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 |
20393 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 |
20394 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 |
20395 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 |
20396 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa |
20397 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x0000000FL |
20398 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L |
20399 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L |
20400 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L |
20401 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L |
20402 | //CP_HQD_DMA_OFFLOAD |
20403 | #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 |
20404 | #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L |
20405 | //CP_HQD_OFFLOAD |
20406 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 |
20407 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 |
20408 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 |
20409 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 |
20410 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 |
20411 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 |
20412 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L |
20413 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L |
20414 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L |
20415 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L |
20416 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L |
20417 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L |
20418 | //CP_HQD_SEMA_CMD |
20419 | #define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 |
20420 | #define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 |
20421 | #define CP_HQD_SEMA_CMD__POLLING_DIS__SHIFT 0x8 |
20422 | #define CP_HQD_SEMA_CMD__MESSAGE_EN__SHIFT 0x9 |
20423 | #define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L |
20424 | #define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L |
20425 | #define CP_HQD_SEMA_CMD__POLLING_DIS_MASK 0x00000100L |
20426 | #define CP_HQD_SEMA_CMD__MESSAGE_EN_MASK 0x00000200L |
20427 | //CP_HQD_MSG_TYPE |
20428 | #define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 |
20429 | #define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 |
20430 | #define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L |
20431 | #define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L |
20432 | //CP_HQD_ATOMIC0_PREOP_LO |
20433 | #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 |
20434 | #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
20435 | //CP_HQD_ATOMIC0_PREOP_HI |
20436 | #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 |
20437 | #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
20438 | //CP_HQD_ATOMIC1_PREOP_LO |
20439 | #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 |
20440 | #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
20441 | //CP_HQD_ATOMIC1_PREOP_HI |
20442 | #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 |
20443 | #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
20444 | //CP_HQD_HQ_SCHEDULER0 |
20445 | #define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0 |
20446 | #define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL |
20447 | //CP_HQD_HQ_STATUS0 |
20448 | #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 |
20449 | #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2 |
20450 | #define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4 |
20451 | #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 |
20452 | #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 |
20453 | #define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9 |
20454 | #define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa |
20455 | #define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e |
20456 | #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f |
20457 | #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L |
20458 | #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL |
20459 | #define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L |
20460 | #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L |
20461 | #define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L |
20462 | #define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L |
20463 | #define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L |
20464 | #define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L |
20465 | #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L |
20466 | //CP_HQD_HQ_CONTROL0 |
20467 | #define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 |
20468 | #define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL |
20469 | //CP_HQD_HQ_SCHEDULER1 |
20470 | #define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 |
20471 | #define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL |
20472 | //CP_MQD_CONTROL |
20473 | #define CP_MQD_CONTROL__VMID__SHIFT 0x0 |
20474 | #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 |
20475 | #define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc |
20476 | #define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd |
20477 | #define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 |
20478 | #define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 |
20479 | #define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT 0x1a |
20480 | #define CP_MQD_CONTROL__VMID_MASK 0x0000000FL |
20481 | #define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L |
20482 | #define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L |
20483 | #define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L |
20484 | #define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L |
20485 | #define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x03000000L |
20486 | #define CP_MQD_CONTROL__MQD_VOLATILE_MASK 0x04000000L |
20487 | //CP_HQD_HQ_STATUS1 |
20488 | #define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 |
20489 | #define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL |
20490 | //CP_HQD_HQ_CONTROL1 |
20491 | #define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 |
20492 | #define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL |
20493 | //CP_HQD_EOP_BASE_ADDR |
20494 | #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
20495 | #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
20496 | //CP_HQD_EOP_BASE_ADDR_HI |
20497 | #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
20498 | #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL |
20499 | //CP_HQD_EOP_CONTROL |
20500 | #define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 |
20501 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 |
20502 | #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc |
20503 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd |
20504 | #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe |
20505 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15 |
20506 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16 |
20507 | #define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17 |
20508 | #define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 |
20509 | #define CP_HQD_EOP_CONTROL__EOP_VOLATILE__SHIFT 0x1a |
20510 | #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d |
20511 | #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f |
20512 | #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL |
20513 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L |
20514 | #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L |
20515 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L |
20516 | #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L |
20517 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L |
20518 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L |
20519 | #define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L |
20520 | #define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x03000000L |
20521 | #define CP_HQD_EOP_CONTROL__EOP_VOLATILE_MASK 0x04000000L |
20522 | #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L |
20523 | #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L |
20524 | //CP_HQD_EOP_RPTR |
20525 | #define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 |
20526 | #define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c |
20527 | #define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d |
20528 | #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e |
20529 | #define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f |
20530 | #define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL |
20531 | #define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L |
20532 | #define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L |
20533 | #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L |
20534 | #define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L |
20535 | //CP_HQD_EOP_WPTR |
20536 | #define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 |
20537 | #define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf |
20538 | #define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 |
20539 | #define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL |
20540 | #define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L |
20541 | #define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L |
20542 | //CP_HQD_EOP_EVENTS |
20543 | #define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 |
20544 | #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 |
20545 | #define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL |
20546 | #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L |
20547 | //CP_HQD_CTX_SAVE_BASE_ADDR_LO |
20548 | #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc |
20549 | #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L |
20550 | //CP_HQD_CTX_SAVE_BASE_ADDR_HI |
20551 | #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
20552 | #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
20553 | //CP_HQD_CTX_SAVE_CONTROL |
20554 | #define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 |
20555 | #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 |
20556 | #define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L |
20557 | #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L |
20558 | //CP_HQD_CNTL_STACK_OFFSET |
20559 | #define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 |
20560 | #define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL |
20561 | //CP_HQD_CNTL_STACK_SIZE |
20562 | #define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc |
20563 | #define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L |
20564 | //CP_HQD_WG_STATE_OFFSET |
20565 | #define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 |
20566 | #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL |
20567 | //CP_HQD_CTX_SAVE_SIZE |
20568 | #define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc |
20569 | #define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L |
20570 | //CP_HQD_GDS_RESOURCE_STATE |
20571 | #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 |
20572 | #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 |
20573 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 |
20574 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc |
20575 | #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L |
20576 | #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L |
20577 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L |
20578 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L |
20579 | //CP_HQD_ERROR |
20580 | #define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 |
20581 | #define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 |
20582 | #define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5 |
20583 | #define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8 |
20584 | #define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9 |
20585 | #define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa |
20586 | #define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb |
20587 | #define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc |
20588 | #define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd |
20589 | #define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe |
20590 | #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf |
20591 | #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10 |
20592 | #define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11 |
20593 | #define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12 |
20594 | #define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13 |
20595 | #define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL |
20596 | #define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L |
20597 | #define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L |
20598 | #define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L |
20599 | #define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L |
20600 | #define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L |
20601 | #define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L |
20602 | #define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L |
20603 | #define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L |
20604 | #define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L |
20605 | #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L |
20606 | #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L |
20607 | #define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L |
20608 | #define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L |
20609 | #define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L |
20610 | //CP_HQD_EOP_WPTR_MEM |
20611 | #define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 |
20612 | #define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL |
20613 | //CP_HQD_AQL_CONTROL |
20614 | #define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0 |
20615 | #define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf |
20616 | #define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10 |
20617 | #define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f |
20618 | #define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL |
20619 | #define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L |
20620 | #define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L |
20621 | #define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L |
20622 | //CP_HQD_PQ_WPTR_LO |
20623 | #define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0 |
20624 | #define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL |
20625 | //CP_HQD_PQ_WPTR_HI |
20626 | #define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0 |
20627 | #define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL |
20628 | //CP_HQD_SUSPEND_CNTL_STACK_OFFSET |
20629 | #define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 |
20630 | #define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL |
20631 | //CP_HQD_SUSPEND_CNTL_STACK_DW_CNT |
20632 | #define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT__SHIFT 0x0 |
20633 | #define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT_MASK 0x00001FFFL |
20634 | //CP_HQD_SUSPEND_WG_STATE_OFFSET |
20635 | #define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 |
20636 | #define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL |
20637 | //CP_HQD_DDID_RPTR |
20638 | #define CP_HQD_DDID_RPTR__RPTR__SHIFT 0x0 |
20639 | #define CP_HQD_DDID_RPTR__RPTR_MASK 0x000007FFL |
20640 | //CP_HQD_DDID_WPTR |
20641 | #define CP_HQD_DDID_WPTR__WPTR__SHIFT 0x0 |
20642 | #define CP_HQD_DDID_WPTR__WPTR_MASK 0x000007FFL |
20643 | //CP_HQD_DDID_INFLIGHT_COUNT |
20644 | #define CP_HQD_DDID_INFLIGHT_COUNT__COUNT__SHIFT 0x0 |
20645 | #define CP_HQD_DDID_INFLIGHT_COUNT__COUNT_MASK 0x0000FFFFL |
20646 | //CP_HQD_DDID_DELTA_RPT_COUNT |
20647 | #define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT__SHIFT 0x0 |
20648 | #define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT_MASK 0x000000FFL |
20649 | //CP_HQD_DEQUEUE_STATUS |
20650 | #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT__SHIFT 0x0 |
20651 | #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND__SHIFT 0x4 |
20652 | #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN__SHIFT 0x9 |
20653 | #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN__SHIFT 0xa |
20654 | #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_MASK 0x0000000FL |
20655 | #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_MASK 0x00000010L |
20656 | #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN_MASK 0x00000200L |
20657 | #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN_MASK 0x00000400L |
20658 | |
20659 | |
20660 | // addressBlock: gc_didtdec |
20661 | //DIDT_IND_INDEX |
20662 | #define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 |
20663 | #define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL |
20664 | //DIDT_IND_DATA |
20665 | #define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 |
20666 | #define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL |
20667 | //DIDT_INDEX_AUTO_INCR_EN |
20668 | #define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT 0x0 |
20669 | #define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK 0x00000001L |
20670 | |
20671 | |
20672 | // addressBlock: gc_gccacdec |
20673 | //GC_CAC_CTRL_1 |
20674 | #define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 |
20675 | #define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18 |
20676 | #define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL |
20677 | #define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L |
20678 | //GC_CAC_CTRL_2 |
20679 | #define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 |
20680 | #define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1 |
20681 | #define GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT 0x2 |
20682 | #define GC_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT 0x3 |
20683 | #define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x4 |
20684 | #define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L |
20685 | #define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L |
20686 | #define GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK 0x00000004L |
20687 | #define GC_CAC_CTRL_2__SE_LCAC_ENABLE_MASK 0x00000008L |
20688 | #define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000010L |
20689 | //GC_CAC_AGGR_LOWER |
20690 | #define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0 |
20691 | #define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL |
20692 | //GC_CAC_AGGR_UPPER |
20693 | #define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0 |
20694 | #define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL |
20695 | //GC_CAC_SOFT_CTRL |
20696 | #define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0 |
20697 | #define GC_CAC_SOFT_CTRL__UNUSED__SHIFT 0x1 |
20698 | #define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L |
20699 | #define GC_CAC_SOFT_CTRL__UNUSED_MASK 0xFFFFFFFEL |
20700 | //GC_DIDT_CTRL0 |
20701 | #define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 |
20702 | #define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1 |
20703 | #define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3 |
20704 | #define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 |
20705 | #define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5 |
20706 | #define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L |
20707 | #define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L |
20708 | #define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L |
20709 | #define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L |
20710 | #define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L |
20711 | //GC_DIDT_CTRL1 |
20712 | #define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0 |
20713 | #define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10 |
20714 | #define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL |
20715 | #define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L |
20716 | //GC_DIDT_CTRL2 |
20717 | #define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 |
20718 | #define GC_DIDT_CTRL2__UNUSED_0__SHIFT 0xe |
20719 | #define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
20720 | #define GC_DIDT_CTRL2__UNUSED_1__SHIFT 0x1a |
20721 | #define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
20722 | #define GC_DIDT_CTRL2__UNUSED_2__SHIFT 0x1f |
20723 | #define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL |
20724 | #define GC_DIDT_CTRL2__UNUSED_0_MASK 0x0000C000L |
20725 | #define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
20726 | #define GC_DIDT_CTRL2__UNUSED_1_MASK 0x04000000L |
20727 | #define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
20728 | #define GC_DIDT_CTRL2__UNUSED_2_MASK 0x80000000L |
20729 | //GC_DIDT_WEIGHT |
20730 | #define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0 |
20731 | #define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8 |
20732 | #define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10 |
20733 | #define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18 |
20734 | #define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL |
20735 | #define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L |
20736 | #define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L |
20737 | #define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L |
20738 | //GC_THROTTLE_CTRL |
20739 | #define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT 0x0 |
20740 | #define GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x1 |
20741 | #define GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
20742 | #define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL__SHIFT 0x3 |
20743 | #define GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x4 |
20744 | #define GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT 0x5 |
20745 | #define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x6 |
20746 | #define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT 0x7 |
20747 | #define GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT 0x8 |
20748 | #define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE__SHIFT 0x9 |
20749 | #define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT 0xa |
20750 | #define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT 0xb |
20751 | #define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN__SHIFT 0xc |
20752 | #define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT 0xd |
20753 | #define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT 0x17 |
20754 | #define GC_THROTTLE_CTRL__LUT_HW_UPDATE__SHIFT 0x1d |
20755 | #define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE__SHIFT 0x1e |
20756 | #define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK 0x00000001L |
20757 | #define GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000002L |
20758 | #define GC_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
20759 | #define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL_MASK 0x00000008L |
20760 | #define GC_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000010L |
20761 | #define GC_THROTTLE_CTRL__PATTERN_MODE_MASK 0x00000020L |
20762 | #define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000040L |
20763 | #define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK 0x00000080L |
20764 | #define GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK 0x00000100L |
20765 | #define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE_MASK 0x00000200L |
20766 | #define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK 0x00000400L |
20767 | #define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK 0x00000800L |
20768 | #define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN_MASK 0x00001000L |
20769 | #define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL_MASK 0x007FE000L |
20770 | #define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK 0x00800000L |
20771 | #define GC_THROTTLE_CTRL__LUT_HW_UPDATE_MASK 0x20000000L |
20772 | #define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE_MASK 0x40000000L |
20773 | //GC_EDC_CTRL |
20774 | #define GC_EDC_CTRL__EDC_EN__SHIFT 0x0 |
20775 | #define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
20776 | #define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
20777 | #define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
20778 | #define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
20779 | #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9 |
20780 | #define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0xa |
20781 | #define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0xe |
20782 | #define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L |
20783 | #define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
20784 | #define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
20785 | #define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
20786 | #define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
20787 | #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L |
20788 | #define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00003C00L |
20789 | #define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x00004000L |
20790 | //GC_EDC_THRESHOLD |
20791 | #define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
20792 | #define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
20793 | //GC_EDC_STATUS |
20794 | #define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0 |
20795 | #define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L |
20796 | //GC_EDC_OVERFLOW |
20797 | #define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
20798 | #define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
20799 | #define GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT 0x12 |
20800 | #define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
20801 | #define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
20802 | #define GC_EDC_OVERFLOW__PSM_COUNTER_MASK 0xFFFC0000L |
20803 | //GC_EDC_ROLLING_POWER_DELTA |
20804 | #define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
20805 | #define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
20806 | //GC_THROTTLE_CTRL1 |
20807 | #define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT 0x0 |
20808 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT 0x1 |
20809 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT 0x5 |
20810 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0xa |
20811 | #define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT 0xd |
20812 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP__SHIFT 0xe |
20813 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP__SHIFT 0x12 |
20814 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0x17 |
20815 | #define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK 0x00000001L |
20816 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK 0x0000001EL |
20817 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK 0x000003E0L |
20818 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x00001C00L |
20819 | #define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN_MASK 0x00002000L |
20820 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP_MASK 0x0003C000L |
20821 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP_MASK 0x007C0000L |
20822 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x03800000L |
20823 | //GC_THROTTLE_STATUS |
20824 | #define GC_THROTTLE_STATUS__FSM_STATE__SHIFT 0x0 |
20825 | #define GC_THROTTLE_STATUS__PATTERN_INDEX__SHIFT 0x4 |
20826 | #define GC_THROTTLE_STATUS__FSM_STATE_MASK 0x0000000FL |
20827 | #define GC_THROTTLE_STATUS__PATTERN_INDEX_MASK 0x000003F0L |
20828 | //EDC_PERF_COUNTER |
20829 | #define EDC_PERF_COUNTER__EDC_PERF_COUNTER__SHIFT 0x0 |
20830 | #define EDC_PERF_COUNTER__EDC_PERF_COUNTER_MASK 0xFFFFFFFFL |
20831 | //PCC_PERF_COUNTER |
20832 | #define PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT 0x0 |
20833 | #define PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK 0xFFFFFFFFL |
20834 | //PWRBRK_PERF_COUNTER |
20835 | #define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT 0x0 |
20836 | #define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK 0xFFFFFFFFL |
20837 | //GC_CAC_IND_INDEX |
20838 | #define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0 |
20839 | #define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL |
20840 | //GC_CAC_IND_DATA |
20841 | #define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0 |
20842 | #define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL |
20843 | //SE_CAC_IND_INDEX |
20844 | #define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0 |
20845 | #define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL |
20846 | //SE_CAC_IND_DATA |
20847 | #define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0 |
20848 | #define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL |
20849 | |
20850 | |
20851 | // addressBlock: gc_tcpdec |
20852 | //TCP_WATCH0_ADDR_H |
20853 | #define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 |
20854 | #define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL |
20855 | //TCP_WATCH0_ADDR_L |
20856 | #define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x7 |
20857 | #define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFF80L |
20858 | //TCP_WATCH0_CNTL |
20859 | #define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 |
20860 | #define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 |
20861 | #define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d |
20862 | #define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f |
20863 | #define TCP_WATCH0_CNTL__MASK_MASK 0x007FFFFFL |
20864 | #define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L |
20865 | #define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L |
20866 | #define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L |
20867 | //TCP_WATCH1_ADDR_H |
20868 | #define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 |
20869 | #define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL |
20870 | //TCP_WATCH1_ADDR_L |
20871 | #define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x7 |
20872 | #define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFF80L |
20873 | //TCP_WATCH1_CNTL |
20874 | #define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 |
20875 | #define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 |
20876 | #define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d |
20877 | #define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f |
20878 | #define TCP_WATCH1_CNTL__MASK_MASK 0x007FFFFFL |
20879 | #define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L |
20880 | #define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L |
20881 | #define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L |
20882 | //TCP_WATCH2_ADDR_H |
20883 | #define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 |
20884 | #define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL |
20885 | //TCP_WATCH2_ADDR_L |
20886 | #define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x7 |
20887 | #define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFF80L |
20888 | //TCP_WATCH2_CNTL |
20889 | #define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 |
20890 | #define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 |
20891 | #define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d |
20892 | #define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f |
20893 | #define TCP_WATCH2_CNTL__MASK_MASK 0x007FFFFFL |
20894 | #define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L |
20895 | #define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L |
20896 | #define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L |
20897 | //TCP_WATCH3_ADDR_H |
20898 | #define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 |
20899 | #define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL |
20900 | //TCP_WATCH3_ADDR_L |
20901 | #define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x7 |
20902 | #define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFF80L |
20903 | //TCP_WATCH3_CNTL |
20904 | #define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 |
20905 | #define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 |
20906 | #define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d |
20907 | #define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f |
20908 | #define TCP_WATCH3_CNTL__MASK_MASK 0x007FFFFFL |
20909 | #define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L |
20910 | #define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L |
20911 | #define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L |
20912 | //TCP_CNTL2 |
20913 | #define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0 |
20914 | #define TCP_CNTL2__TCPF_FMT_MGCG_DISABLE__SHIFT 0x8 |
20915 | #define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE__SHIFT 0x9 |
20916 | #define TCP_CNTL2__TCPI_WRITE_DATA_MGCG_DISABLE__SHIFT 0xa |
20917 | #define TCP_CNTL2__TCPI_INNER_BLOCK_MGCG_DISABLE__SHIFT 0xb |
20918 | #define TCP_CNTL2__TCPI_ADRS_IMG_CALC_MGCG_DISABLE__SHIFT 0xc |
20919 | #define TCP_CNTL2__V64_COMBINE_ENABLE__SHIFT 0xd |
20920 | #define TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE__SHIFT 0xe |
20921 | #define TCP_CNTL2__RETURN_ORDER_OVERRIDE__SHIFT 0xf |
20922 | #define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL |
20923 | #define TCP_CNTL2__TCPF_FMT_MGCG_DISABLE_MASK 0x00000100L |
20924 | #define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE_MASK 0x00000200L |
20925 | #define TCP_CNTL2__TCPI_WRITE_DATA_MGCG_DISABLE_MASK 0x00000400L |
20926 | #define TCP_CNTL2__TCPI_INNER_BLOCK_MGCG_DISABLE_MASK 0x00000800L |
20927 | #define TCP_CNTL2__TCPI_ADRS_IMG_CALC_MGCG_DISABLE_MASK 0x00001000L |
20928 | #define TCP_CNTL2__V64_COMBINE_ENABLE_MASK 0x00002000L |
20929 | #define TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE_MASK 0x00004000L |
20930 | #define TCP_CNTL2__RETURN_ORDER_OVERRIDE_MASK 0x00008000L |
20931 | //TCP_UTCL0_CNTL1 |
20932 | #define TCP_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
20933 | #define TCP_UTCL0_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 |
20934 | #define TCP_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
20935 | #define TCP_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 |
20936 | #define TCP_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
20937 | #define TCP_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 |
20938 | #define TCP_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13 |
20939 | #define TCP_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 |
20940 | #define TCP_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 |
20941 | #define TCP_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
20942 | #define TCP_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a |
20943 | #define TCP_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
20944 | #define TCP_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
20945 | #define TCP_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
20946 | #define TCP_UTCL0_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L |
20947 | #define TCP_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
20948 | #define TCP_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L |
20949 | #define TCP_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
20950 | #define TCP_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L |
20951 | #define TCP_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L |
20952 | #define TCP_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L |
20953 | #define TCP_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L |
20954 | #define TCP_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
20955 | #define TCP_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L |
20956 | #define TCP_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
20957 | #define TCP_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
20958 | //TCP_UTCL0_CNTL2 |
20959 | #define TCP_UTCL0_CNTL2__SPARE__SHIFT 0x0 |
20960 | #define TCP_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
20961 | #define TCP_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT 0xa |
20962 | #define TCP_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
20963 | #define TCP_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe |
20964 | #define TCP_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
20965 | #define TCP_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
20966 | #define TCP_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b |
20967 | #define TCP_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c |
20968 | #define TCP_UTCL0_CNTL2__GPUVM_16K_DEFAULT__SHIFT 0x1d |
20969 | #define TCP_UTCL0_CNTL2__SPARE_MASK 0x000000FFL |
20970 | #define TCP_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
20971 | #define TCP_UTCL0_CNTL2__ANY_LINE_VALID_MASK 0x00000400L |
20972 | #define TCP_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
20973 | #define TCP_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
20974 | #define TCP_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
20975 | #define TCP_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
20976 | #define TCP_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L |
20977 | #define TCP_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L |
20978 | #define TCP_UTCL0_CNTL2__GPUVM_16K_DEFAULT_MASK 0x20000000L |
20979 | //TCP_UTCL0_STATUS |
20980 | #define TCP_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 |
20981 | #define TCP_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 |
20982 | #define TCP_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 |
20983 | #define TCP_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L |
20984 | #define TCP_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L |
20985 | #define TCP_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L |
20986 | //TCP_PERFCOUNTER_FILTER |
20987 | #define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 |
20988 | #define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 |
20989 | #define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2 |
20990 | #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5 |
20991 | #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xd |
20992 | #define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0x11 |
20993 | #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x16 |
20994 | #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x18 |
20995 | #define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1b |
20996 | #define TCP_PERFCOUNTER_FILTER__DLC__SHIFT 0x1c |
20997 | #define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x1d |
20998 | #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1e |
20999 | #define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L |
21000 | #define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L |
21001 | #define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL |
21002 | #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x00000FE0L |
21003 | #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x0001E000L |
21004 | #define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x003E0000L |
21005 | #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00C00000L |
21006 | #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x07000000L |
21007 | #define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x08000000L |
21008 | #define TCP_PERFCOUNTER_FILTER__DLC_MASK 0x10000000L |
21009 | #define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x20000000L |
21010 | #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x40000000L |
21011 | //TCP_PERFCOUNTER_FILTER_EN |
21012 | #define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0 |
21013 | #define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1 |
21014 | #define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2 |
21015 | #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3 |
21016 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4 |
21017 | #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5 |
21018 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6 |
21019 | #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7 |
21020 | #define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x8 |
21021 | #define TCP_PERFCOUNTER_FILTER_EN__DLC__SHIFT 0x9 |
21022 | #define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0xa |
21023 | #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xb |
21024 | #define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE__SHIFT 0xc |
21025 | #define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L |
21026 | #define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L |
21027 | #define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L |
21028 | #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L |
21029 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L |
21030 | #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L |
21031 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L |
21032 | #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L |
21033 | #define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000100L |
21034 | #define TCP_PERFCOUNTER_FILTER_EN__DLC_MASK 0x00000200L |
21035 | #define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000400L |
21036 | #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000800L |
21037 | #define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE_MASK 0x00001000L |
21038 | //TCP_PERFCOUNTER_FILTER2 |
21039 | #define TCP_PERFCOUNTER_FILTER2__REQ_MODE__SHIFT 0x0 |
21040 | #define TCP_PERFCOUNTER_FILTER2__REQ_MODE_MASK 0x00000007L |
21041 | |
21042 | |
21043 | // addressBlock: gc_gdspdec |
21044 | //GDS_VMID0_BASE |
21045 | #define GDS_VMID0_BASE__BASE__SHIFT 0x0 |
21046 | #define GDS_VMID0_BASE__UNUSED__SHIFT 0x10 |
21047 | #define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL |
21048 | #define GDS_VMID0_BASE__UNUSED_MASK 0xFFFF0000L |
21049 | //GDS_VMID0_SIZE |
21050 | #define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 |
21051 | #define GDS_VMID0_SIZE__UNUSED__SHIFT 0x11 |
21052 | #define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL |
21053 | #define GDS_VMID0_SIZE__UNUSED_MASK 0xFFFE0000L |
21054 | //GDS_VMID1_BASE |
21055 | #define GDS_VMID1_BASE__BASE__SHIFT 0x0 |
21056 | #define GDS_VMID1_BASE__UNUSED__SHIFT 0x10 |
21057 | #define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL |
21058 | #define GDS_VMID1_BASE__UNUSED_MASK 0xFFFF0000L |
21059 | //GDS_VMID1_SIZE |
21060 | #define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 |
21061 | #define GDS_VMID1_SIZE__UNUSED__SHIFT 0x11 |
21062 | #define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL |
21063 | #define GDS_VMID1_SIZE__UNUSED_MASK 0xFFFE0000L |
21064 | //GDS_VMID2_BASE |
21065 | #define GDS_VMID2_BASE__BASE__SHIFT 0x0 |
21066 | #define GDS_VMID2_BASE__UNUSED__SHIFT 0x10 |
21067 | #define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL |
21068 | #define GDS_VMID2_BASE__UNUSED_MASK 0xFFFF0000L |
21069 | //GDS_VMID2_SIZE |
21070 | #define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 |
21071 | #define GDS_VMID2_SIZE__UNUSED__SHIFT 0x11 |
21072 | #define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL |
21073 | #define GDS_VMID2_SIZE__UNUSED_MASK 0xFFFE0000L |
21074 | //GDS_VMID3_BASE |
21075 | #define GDS_VMID3_BASE__BASE__SHIFT 0x0 |
21076 | #define GDS_VMID3_BASE__UNUSED__SHIFT 0x10 |
21077 | #define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL |
21078 | #define GDS_VMID3_BASE__UNUSED_MASK 0xFFFF0000L |
21079 | //GDS_VMID3_SIZE |
21080 | #define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 |
21081 | #define GDS_VMID3_SIZE__UNUSED__SHIFT 0x11 |
21082 | #define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL |
21083 | #define GDS_VMID3_SIZE__UNUSED_MASK 0xFFFE0000L |
21084 | //GDS_VMID4_BASE |
21085 | #define GDS_VMID4_BASE__BASE__SHIFT 0x0 |
21086 | #define GDS_VMID4_BASE__UNUSED__SHIFT 0x10 |
21087 | #define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL |
21088 | #define GDS_VMID4_BASE__UNUSED_MASK 0xFFFF0000L |
21089 | //GDS_VMID4_SIZE |
21090 | #define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 |
21091 | #define GDS_VMID4_SIZE__UNUSED__SHIFT 0x11 |
21092 | #define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL |
21093 | #define GDS_VMID4_SIZE__UNUSED_MASK 0xFFFE0000L |
21094 | //GDS_VMID5_BASE |
21095 | #define GDS_VMID5_BASE__BASE__SHIFT 0x0 |
21096 | #define GDS_VMID5_BASE__UNUSED__SHIFT 0x10 |
21097 | #define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL |
21098 | #define GDS_VMID5_BASE__UNUSED_MASK 0xFFFF0000L |
21099 | //GDS_VMID5_SIZE |
21100 | #define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 |
21101 | #define GDS_VMID5_SIZE__UNUSED__SHIFT 0x11 |
21102 | #define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL |
21103 | #define GDS_VMID5_SIZE__UNUSED_MASK 0xFFFE0000L |
21104 | //GDS_VMID6_BASE |
21105 | #define GDS_VMID6_BASE__BASE__SHIFT 0x0 |
21106 | #define GDS_VMID6_BASE__UNUSED__SHIFT 0x10 |
21107 | #define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL |
21108 | #define GDS_VMID6_BASE__UNUSED_MASK 0xFFFF0000L |
21109 | //GDS_VMID6_SIZE |
21110 | #define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 |
21111 | #define GDS_VMID6_SIZE__UNUSED__SHIFT 0x11 |
21112 | #define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL |
21113 | #define GDS_VMID6_SIZE__UNUSED_MASK 0xFFFE0000L |
21114 | //GDS_VMID7_BASE |
21115 | #define GDS_VMID7_BASE__BASE__SHIFT 0x0 |
21116 | #define GDS_VMID7_BASE__UNUSED__SHIFT 0x10 |
21117 | #define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL |
21118 | #define GDS_VMID7_BASE__UNUSED_MASK 0xFFFF0000L |
21119 | //GDS_VMID7_SIZE |
21120 | #define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 |
21121 | #define GDS_VMID7_SIZE__UNUSED__SHIFT 0x11 |
21122 | #define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL |
21123 | #define GDS_VMID7_SIZE__UNUSED_MASK 0xFFFE0000L |
21124 | //GDS_VMID8_BASE |
21125 | #define GDS_VMID8_BASE__BASE__SHIFT 0x0 |
21126 | #define GDS_VMID8_BASE__UNUSED__SHIFT 0x10 |
21127 | #define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL |
21128 | #define GDS_VMID8_BASE__UNUSED_MASK 0xFFFF0000L |
21129 | //GDS_VMID8_SIZE |
21130 | #define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 |
21131 | #define GDS_VMID8_SIZE__UNUSED__SHIFT 0x11 |
21132 | #define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL |
21133 | #define GDS_VMID8_SIZE__UNUSED_MASK 0xFFFE0000L |
21134 | //GDS_VMID9_BASE |
21135 | #define GDS_VMID9_BASE__BASE__SHIFT 0x0 |
21136 | #define GDS_VMID9_BASE__UNUSED__SHIFT 0x10 |
21137 | #define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL |
21138 | #define GDS_VMID9_BASE__UNUSED_MASK 0xFFFF0000L |
21139 | //GDS_VMID9_SIZE |
21140 | #define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 |
21141 | #define GDS_VMID9_SIZE__UNUSED__SHIFT 0x11 |
21142 | #define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL |
21143 | #define GDS_VMID9_SIZE__UNUSED_MASK 0xFFFE0000L |
21144 | //GDS_VMID10_BASE |
21145 | #define GDS_VMID10_BASE__BASE__SHIFT 0x0 |
21146 | #define GDS_VMID10_BASE__UNUSED__SHIFT 0x10 |
21147 | #define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL |
21148 | #define GDS_VMID10_BASE__UNUSED_MASK 0xFFFF0000L |
21149 | //GDS_VMID10_SIZE |
21150 | #define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 |
21151 | #define GDS_VMID10_SIZE__UNUSED__SHIFT 0x11 |
21152 | #define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL |
21153 | #define GDS_VMID10_SIZE__UNUSED_MASK 0xFFFE0000L |
21154 | //GDS_VMID11_BASE |
21155 | #define GDS_VMID11_BASE__BASE__SHIFT 0x0 |
21156 | #define GDS_VMID11_BASE__UNUSED__SHIFT 0x10 |
21157 | #define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL |
21158 | #define GDS_VMID11_BASE__UNUSED_MASK 0xFFFF0000L |
21159 | //GDS_VMID11_SIZE |
21160 | #define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 |
21161 | #define GDS_VMID11_SIZE__UNUSED__SHIFT 0x11 |
21162 | #define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL |
21163 | #define GDS_VMID11_SIZE__UNUSED_MASK 0xFFFE0000L |
21164 | //GDS_VMID12_BASE |
21165 | #define GDS_VMID12_BASE__BASE__SHIFT 0x0 |
21166 | #define GDS_VMID12_BASE__UNUSED__SHIFT 0x10 |
21167 | #define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL |
21168 | #define GDS_VMID12_BASE__UNUSED_MASK 0xFFFF0000L |
21169 | //GDS_VMID12_SIZE |
21170 | #define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 |
21171 | #define GDS_VMID12_SIZE__UNUSED__SHIFT 0x11 |
21172 | #define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL |
21173 | #define GDS_VMID12_SIZE__UNUSED_MASK 0xFFFE0000L |
21174 | //GDS_VMID13_BASE |
21175 | #define GDS_VMID13_BASE__BASE__SHIFT 0x0 |
21176 | #define GDS_VMID13_BASE__UNUSED__SHIFT 0x10 |
21177 | #define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL |
21178 | #define GDS_VMID13_BASE__UNUSED_MASK 0xFFFF0000L |
21179 | //GDS_VMID13_SIZE |
21180 | #define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 |
21181 | #define GDS_VMID13_SIZE__UNUSED__SHIFT 0x11 |
21182 | #define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL |
21183 | #define GDS_VMID13_SIZE__UNUSED_MASK 0xFFFE0000L |
21184 | //GDS_VMID14_BASE |
21185 | #define GDS_VMID14_BASE__BASE__SHIFT 0x0 |
21186 | #define GDS_VMID14_BASE__UNUSED__SHIFT 0x10 |
21187 | #define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL |
21188 | #define GDS_VMID14_BASE__UNUSED_MASK 0xFFFF0000L |
21189 | //GDS_VMID14_SIZE |
21190 | #define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 |
21191 | #define GDS_VMID14_SIZE__UNUSED__SHIFT 0x11 |
21192 | #define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL |
21193 | #define GDS_VMID14_SIZE__UNUSED_MASK 0xFFFE0000L |
21194 | //GDS_VMID15_BASE |
21195 | #define GDS_VMID15_BASE__BASE__SHIFT 0x0 |
21196 | #define GDS_VMID15_BASE__UNUSED__SHIFT 0x10 |
21197 | #define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL |
21198 | #define GDS_VMID15_BASE__UNUSED_MASK 0xFFFF0000L |
21199 | //GDS_VMID15_SIZE |
21200 | #define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 |
21201 | #define GDS_VMID15_SIZE__UNUSED__SHIFT 0x11 |
21202 | #define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL |
21203 | #define GDS_VMID15_SIZE__UNUSED_MASK 0xFFFE0000L |
21204 | //GDS_GWS_VMID0 |
21205 | #define GDS_GWS_VMID0__BASE__SHIFT 0x0 |
21206 | #define GDS_GWS_VMID0__UNUSED1__SHIFT 0x6 |
21207 | #define GDS_GWS_VMID0__SIZE__SHIFT 0x10 |
21208 | #define GDS_GWS_VMID0__UNUSED2__SHIFT 0x17 |
21209 | #define GDS_GWS_VMID0__BASE_MASK 0x0000003FL |
21210 | #define GDS_GWS_VMID0__UNUSED1_MASK 0x0000FFC0L |
21211 | #define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L |
21212 | #define GDS_GWS_VMID0__UNUSED2_MASK 0xFF800000L |
21213 | //GDS_GWS_VMID1 |
21214 | #define GDS_GWS_VMID1__BASE__SHIFT 0x0 |
21215 | #define GDS_GWS_VMID1__UNUSED1__SHIFT 0x6 |
21216 | #define GDS_GWS_VMID1__SIZE__SHIFT 0x10 |
21217 | #define GDS_GWS_VMID1__UNUSED2__SHIFT 0x17 |
21218 | #define GDS_GWS_VMID1__BASE_MASK 0x0000003FL |
21219 | #define GDS_GWS_VMID1__UNUSED1_MASK 0x0000FFC0L |
21220 | #define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L |
21221 | #define GDS_GWS_VMID1__UNUSED2_MASK 0xFF800000L |
21222 | //GDS_GWS_VMID2 |
21223 | #define GDS_GWS_VMID2__BASE__SHIFT 0x0 |
21224 | #define GDS_GWS_VMID2__UNUSED1__SHIFT 0x6 |
21225 | #define GDS_GWS_VMID2__SIZE__SHIFT 0x10 |
21226 | #define GDS_GWS_VMID2__UNUSED2__SHIFT 0x17 |
21227 | #define GDS_GWS_VMID2__BASE_MASK 0x0000003FL |
21228 | #define GDS_GWS_VMID2__UNUSED1_MASK 0x0000FFC0L |
21229 | #define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L |
21230 | #define GDS_GWS_VMID2__UNUSED2_MASK 0xFF800000L |
21231 | //GDS_GWS_VMID3 |
21232 | #define GDS_GWS_VMID3__BASE__SHIFT 0x0 |
21233 | #define GDS_GWS_VMID3__UNUSED1__SHIFT 0x6 |
21234 | #define GDS_GWS_VMID3__SIZE__SHIFT 0x10 |
21235 | #define GDS_GWS_VMID3__UNUSED2__SHIFT 0x17 |
21236 | #define GDS_GWS_VMID3__BASE_MASK 0x0000003FL |
21237 | #define GDS_GWS_VMID3__UNUSED1_MASK 0x0000FFC0L |
21238 | #define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L |
21239 | #define GDS_GWS_VMID3__UNUSED2_MASK 0xFF800000L |
21240 | //GDS_GWS_VMID4 |
21241 | #define GDS_GWS_VMID4__BASE__SHIFT 0x0 |
21242 | #define GDS_GWS_VMID4__UNUSED1__SHIFT 0x6 |
21243 | #define GDS_GWS_VMID4__SIZE__SHIFT 0x10 |
21244 | #define GDS_GWS_VMID4__UNUSED2__SHIFT 0x17 |
21245 | #define GDS_GWS_VMID4__BASE_MASK 0x0000003FL |
21246 | #define GDS_GWS_VMID4__UNUSED1_MASK 0x0000FFC0L |
21247 | #define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L |
21248 | #define GDS_GWS_VMID4__UNUSED2_MASK 0xFF800000L |
21249 | //GDS_GWS_VMID5 |
21250 | #define GDS_GWS_VMID5__BASE__SHIFT 0x0 |
21251 | #define GDS_GWS_VMID5__UNUSED1__SHIFT 0x6 |
21252 | #define GDS_GWS_VMID5__SIZE__SHIFT 0x10 |
21253 | #define GDS_GWS_VMID5__UNUSED2__SHIFT 0x17 |
21254 | #define GDS_GWS_VMID5__BASE_MASK 0x0000003FL |
21255 | #define GDS_GWS_VMID5__UNUSED1_MASK 0x0000FFC0L |
21256 | #define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L |
21257 | #define GDS_GWS_VMID5__UNUSED2_MASK 0xFF800000L |
21258 | //GDS_GWS_VMID6 |
21259 | #define GDS_GWS_VMID6__BASE__SHIFT 0x0 |
21260 | #define GDS_GWS_VMID6__UNUSED1__SHIFT 0x6 |
21261 | #define GDS_GWS_VMID6__SIZE__SHIFT 0x10 |
21262 | #define GDS_GWS_VMID6__UNUSED2__SHIFT 0x17 |
21263 | #define GDS_GWS_VMID6__BASE_MASK 0x0000003FL |
21264 | #define GDS_GWS_VMID6__UNUSED1_MASK 0x0000FFC0L |
21265 | #define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L |
21266 | #define GDS_GWS_VMID6__UNUSED2_MASK 0xFF800000L |
21267 | //GDS_GWS_VMID7 |
21268 | #define GDS_GWS_VMID7__BASE__SHIFT 0x0 |
21269 | #define GDS_GWS_VMID7__UNUSED1__SHIFT 0x6 |
21270 | #define GDS_GWS_VMID7__SIZE__SHIFT 0x10 |
21271 | #define GDS_GWS_VMID7__UNUSED2__SHIFT 0x17 |
21272 | #define GDS_GWS_VMID7__BASE_MASK 0x0000003FL |
21273 | #define GDS_GWS_VMID7__UNUSED1_MASK 0x0000FFC0L |
21274 | #define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L |
21275 | #define GDS_GWS_VMID7__UNUSED2_MASK 0xFF800000L |
21276 | //GDS_GWS_VMID8 |
21277 | #define GDS_GWS_VMID8__BASE__SHIFT 0x0 |
21278 | #define GDS_GWS_VMID8__UNUSED1__SHIFT 0x6 |
21279 | #define GDS_GWS_VMID8__SIZE__SHIFT 0x10 |
21280 | #define GDS_GWS_VMID8__UNUSED2__SHIFT 0x17 |
21281 | #define GDS_GWS_VMID8__BASE_MASK 0x0000003FL |
21282 | #define GDS_GWS_VMID8__UNUSED1_MASK 0x0000FFC0L |
21283 | #define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L |
21284 | #define GDS_GWS_VMID8__UNUSED2_MASK 0xFF800000L |
21285 | //GDS_GWS_VMID9 |
21286 | #define GDS_GWS_VMID9__BASE__SHIFT 0x0 |
21287 | #define GDS_GWS_VMID9__UNUSED1__SHIFT 0x6 |
21288 | #define GDS_GWS_VMID9__SIZE__SHIFT 0x10 |
21289 | #define GDS_GWS_VMID9__UNUSED2__SHIFT 0x17 |
21290 | #define GDS_GWS_VMID9__BASE_MASK 0x0000003FL |
21291 | #define GDS_GWS_VMID9__UNUSED1_MASK 0x0000FFC0L |
21292 | #define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L |
21293 | #define GDS_GWS_VMID9__UNUSED2_MASK 0xFF800000L |
21294 | //GDS_GWS_VMID10 |
21295 | #define GDS_GWS_VMID10__BASE__SHIFT 0x0 |
21296 | #define GDS_GWS_VMID10__UNUSED1__SHIFT 0x6 |
21297 | #define GDS_GWS_VMID10__SIZE__SHIFT 0x10 |
21298 | #define GDS_GWS_VMID10__UNUSED2__SHIFT 0x17 |
21299 | #define GDS_GWS_VMID10__BASE_MASK 0x0000003FL |
21300 | #define GDS_GWS_VMID10__UNUSED1_MASK 0x0000FFC0L |
21301 | #define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L |
21302 | #define GDS_GWS_VMID10__UNUSED2_MASK 0xFF800000L |
21303 | //GDS_GWS_VMID11 |
21304 | #define GDS_GWS_VMID11__BASE__SHIFT 0x0 |
21305 | #define GDS_GWS_VMID11__UNUSED1__SHIFT 0x6 |
21306 | #define GDS_GWS_VMID11__SIZE__SHIFT 0x10 |
21307 | #define GDS_GWS_VMID11__UNUSED2__SHIFT 0x17 |
21308 | #define GDS_GWS_VMID11__BASE_MASK 0x0000003FL |
21309 | #define GDS_GWS_VMID11__UNUSED1_MASK 0x0000FFC0L |
21310 | #define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L |
21311 | #define GDS_GWS_VMID11__UNUSED2_MASK 0xFF800000L |
21312 | //GDS_GWS_VMID12 |
21313 | #define GDS_GWS_VMID12__BASE__SHIFT 0x0 |
21314 | #define GDS_GWS_VMID12__UNUSED1__SHIFT 0x6 |
21315 | #define GDS_GWS_VMID12__SIZE__SHIFT 0x10 |
21316 | #define GDS_GWS_VMID12__UNUSED2__SHIFT 0x17 |
21317 | #define GDS_GWS_VMID12__BASE_MASK 0x0000003FL |
21318 | #define GDS_GWS_VMID12__UNUSED1_MASK 0x0000FFC0L |
21319 | #define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L |
21320 | #define GDS_GWS_VMID12__UNUSED2_MASK 0xFF800000L |
21321 | //GDS_GWS_VMID13 |
21322 | #define GDS_GWS_VMID13__BASE__SHIFT 0x0 |
21323 | #define GDS_GWS_VMID13__UNUSED1__SHIFT 0x6 |
21324 | #define GDS_GWS_VMID13__SIZE__SHIFT 0x10 |
21325 | #define GDS_GWS_VMID13__UNUSED2__SHIFT 0x17 |
21326 | #define GDS_GWS_VMID13__BASE_MASK 0x0000003FL |
21327 | #define GDS_GWS_VMID13__UNUSED1_MASK 0x0000FFC0L |
21328 | #define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L |
21329 | #define GDS_GWS_VMID13__UNUSED2_MASK 0xFF800000L |
21330 | //GDS_GWS_VMID14 |
21331 | #define GDS_GWS_VMID14__BASE__SHIFT 0x0 |
21332 | #define GDS_GWS_VMID14__UNUSED1__SHIFT 0x6 |
21333 | #define GDS_GWS_VMID14__SIZE__SHIFT 0x10 |
21334 | #define GDS_GWS_VMID14__UNUSED2__SHIFT 0x17 |
21335 | #define GDS_GWS_VMID14__BASE_MASK 0x0000003FL |
21336 | #define GDS_GWS_VMID14__UNUSED1_MASK 0x0000FFC0L |
21337 | #define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L |
21338 | #define GDS_GWS_VMID14__UNUSED2_MASK 0xFF800000L |
21339 | //GDS_GWS_VMID15 |
21340 | #define GDS_GWS_VMID15__BASE__SHIFT 0x0 |
21341 | #define GDS_GWS_VMID15__UNUSED1__SHIFT 0x6 |
21342 | #define GDS_GWS_VMID15__SIZE__SHIFT 0x10 |
21343 | #define GDS_GWS_VMID15__UNUSED2__SHIFT 0x17 |
21344 | #define GDS_GWS_VMID15__BASE_MASK 0x0000003FL |
21345 | #define GDS_GWS_VMID15__UNUSED1_MASK 0x0000FFC0L |
21346 | #define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L |
21347 | #define GDS_GWS_VMID15__UNUSED2_MASK 0xFF800000L |
21348 | //GDS_OA_VMID0 |
21349 | #define GDS_OA_VMID0__MASK__SHIFT 0x0 |
21350 | #define GDS_OA_VMID0__UNUSED__SHIFT 0x10 |
21351 | #define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL |
21352 | #define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L |
21353 | //GDS_OA_VMID1 |
21354 | #define GDS_OA_VMID1__MASK__SHIFT 0x0 |
21355 | #define GDS_OA_VMID1__UNUSED__SHIFT 0x10 |
21356 | #define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL |
21357 | #define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L |
21358 | //GDS_OA_VMID2 |
21359 | #define GDS_OA_VMID2__MASK__SHIFT 0x0 |
21360 | #define GDS_OA_VMID2__UNUSED__SHIFT 0x10 |
21361 | #define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL |
21362 | #define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L |
21363 | //GDS_OA_VMID3 |
21364 | #define GDS_OA_VMID3__MASK__SHIFT 0x0 |
21365 | #define GDS_OA_VMID3__UNUSED__SHIFT 0x10 |
21366 | #define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL |
21367 | #define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L |
21368 | //GDS_OA_VMID4 |
21369 | #define GDS_OA_VMID4__MASK__SHIFT 0x0 |
21370 | #define GDS_OA_VMID4__UNUSED__SHIFT 0x10 |
21371 | #define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL |
21372 | #define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L |
21373 | //GDS_OA_VMID5 |
21374 | #define GDS_OA_VMID5__MASK__SHIFT 0x0 |
21375 | #define GDS_OA_VMID5__UNUSED__SHIFT 0x10 |
21376 | #define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL |
21377 | #define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L |
21378 | //GDS_OA_VMID6 |
21379 | #define GDS_OA_VMID6__MASK__SHIFT 0x0 |
21380 | #define GDS_OA_VMID6__UNUSED__SHIFT 0x10 |
21381 | #define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL |
21382 | #define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L |
21383 | //GDS_OA_VMID7 |
21384 | #define GDS_OA_VMID7__MASK__SHIFT 0x0 |
21385 | #define GDS_OA_VMID7__UNUSED__SHIFT 0x10 |
21386 | #define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL |
21387 | #define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L |
21388 | //GDS_OA_VMID8 |
21389 | #define GDS_OA_VMID8__MASK__SHIFT 0x0 |
21390 | #define GDS_OA_VMID8__UNUSED__SHIFT 0x10 |
21391 | #define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL |
21392 | #define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L |
21393 | //GDS_OA_VMID9 |
21394 | #define GDS_OA_VMID9__MASK__SHIFT 0x0 |
21395 | #define GDS_OA_VMID9__UNUSED__SHIFT 0x10 |
21396 | #define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL |
21397 | #define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L |
21398 | //GDS_OA_VMID10 |
21399 | #define GDS_OA_VMID10__MASK__SHIFT 0x0 |
21400 | #define GDS_OA_VMID10__UNUSED__SHIFT 0x10 |
21401 | #define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL |
21402 | #define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L |
21403 | //GDS_OA_VMID11 |
21404 | #define GDS_OA_VMID11__MASK__SHIFT 0x0 |
21405 | #define GDS_OA_VMID11__UNUSED__SHIFT 0x10 |
21406 | #define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL |
21407 | #define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L |
21408 | //GDS_OA_VMID12 |
21409 | #define GDS_OA_VMID12__MASK__SHIFT 0x0 |
21410 | #define GDS_OA_VMID12__UNUSED__SHIFT 0x10 |
21411 | #define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL |
21412 | #define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L |
21413 | //GDS_OA_VMID13 |
21414 | #define GDS_OA_VMID13__MASK__SHIFT 0x0 |
21415 | #define GDS_OA_VMID13__UNUSED__SHIFT 0x10 |
21416 | #define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL |
21417 | #define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L |
21418 | //GDS_OA_VMID14 |
21419 | #define GDS_OA_VMID14__MASK__SHIFT 0x0 |
21420 | #define GDS_OA_VMID14__UNUSED__SHIFT 0x10 |
21421 | #define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL |
21422 | #define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L |
21423 | //GDS_OA_VMID15 |
21424 | #define GDS_OA_VMID15__MASK__SHIFT 0x0 |
21425 | #define GDS_OA_VMID15__UNUSED__SHIFT 0x10 |
21426 | #define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL |
21427 | #define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L |
21428 | //GDS_GWS_RESET0 |
21429 | #define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 |
21430 | #define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 |
21431 | #define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 |
21432 | #define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 |
21433 | #define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 |
21434 | #define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 |
21435 | #define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 |
21436 | #define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 |
21437 | #define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 |
21438 | #define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 |
21439 | #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa |
21440 | #define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb |
21441 | #define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc |
21442 | #define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd |
21443 | #define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe |
21444 | #define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf |
21445 | #define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 |
21446 | #define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 |
21447 | #define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 |
21448 | #define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 |
21449 | #define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 |
21450 | #define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 |
21451 | #define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 |
21452 | #define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 |
21453 | #define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 |
21454 | #define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 |
21455 | #define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a |
21456 | #define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b |
21457 | #define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c |
21458 | #define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d |
21459 | #define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e |
21460 | #define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f |
21461 | #define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L |
21462 | #define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L |
21463 | #define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L |
21464 | #define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L |
21465 | #define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L |
21466 | #define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L |
21467 | #define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L |
21468 | #define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L |
21469 | #define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L |
21470 | #define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L |
21471 | #define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L |
21472 | #define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L |
21473 | #define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L |
21474 | #define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L |
21475 | #define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L |
21476 | #define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L |
21477 | #define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L |
21478 | #define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L |
21479 | #define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L |
21480 | #define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L |
21481 | #define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L |
21482 | #define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L |
21483 | #define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L |
21484 | #define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L |
21485 | #define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L |
21486 | #define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L |
21487 | #define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L |
21488 | #define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L |
21489 | #define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L |
21490 | #define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L |
21491 | #define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L |
21492 | #define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L |
21493 | //GDS_GWS_RESET1 |
21494 | #define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 |
21495 | #define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 |
21496 | #define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 |
21497 | #define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 |
21498 | #define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 |
21499 | #define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 |
21500 | #define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 |
21501 | #define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 |
21502 | #define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 |
21503 | #define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 |
21504 | #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa |
21505 | #define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb |
21506 | #define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc |
21507 | #define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd |
21508 | #define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe |
21509 | #define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf |
21510 | #define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 |
21511 | #define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 |
21512 | #define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 |
21513 | #define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 |
21514 | #define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 |
21515 | #define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 |
21516 | #define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 |
21517 | #define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 |
21518 | #define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 |
21519 | #define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 |
21520 | #define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a |
21521 | #define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b |
21522 | #define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c |
21523 | #define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d |
21524 | #define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e |
21525 | #define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f |
21526 | #define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L |
21527 | #define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L |
21528 | #define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L |
21529 | #define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L |
21530 | #define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L |
21531 | #define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L |
21532 | #define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L |
21533 | #define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L |
21534 | #define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L |
21535 | #define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L |
21536 | #define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L |
21537 | #define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L |
21538 | #define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L |
21539 | #define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L |
21540 | #define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L |
21541 | #define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L |
21542 | #define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L |
21543 | #define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L |
21544 | #define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L |
21545 | #define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L |
21546 | #define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L |
21547 | #define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L |
21548 | #define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L |
21549 | #define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L |
21550 | #define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L |
21551 | #define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L |
21552 | #define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L |
21553 | #define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L |
21554 | #define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L |
21555 | #define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L |
21556 | #define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L |
21557 | #define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L |
21558 | //GDS_GWS_RESOURCE_RESET |
21559 | #define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 |
21560 | #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 |
21561 | #define GDS_GWS_RESOURCE_RESET__UNUSED__SHIFT 0x10 |
21562 | #define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L |
21563 | #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L |
21564 | #define GDS_GWS_RESOURCE_RESET__UNUSED_MASK 0xFFFF0000L |
21565 | //GDS_COMPUTE_MAX_WAVE_ID |
21566 | #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
21567 | #define GDS_COMPUTE_MAX_WAVE_ID__UNUSED__SHIFT 0xc |
21568 | #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
21569 | #define GDS_COMPUTE_MAX_WAVE_ID__UNUSED_MASK 0xFFFFF000L |
21570 | //GDS_OA_RESET_MASK |
21571 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 |
21572 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 |
21573 | #define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 |
21574 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3 |
21575 | #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 |
21576 | #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 |
21577 | #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 |
21578 | #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 |
21579 | #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 |
21580 | #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 |
21581 | #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa |
21582 | #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb |
21583 | #define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc |
21584 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L |
21585 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L |
21586 | #define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L |
21587 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L |
21588 | #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L |
21589 | #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L |
21590 | #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L |
21591 | #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L |
21592 | #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L |
21593 | #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L |
21594 | #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L |
21595 | #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L |
21596 | #define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L |
21597 | //GDS_OA_RESET |
21598 | #define GDS_OA_RESET__RESET__SHIFT 0x0 |
21599 | #define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 |
21600 | #define GDS_OA_RESET__UNUSED__SHIFT 0x10 |
21601 | #define GDS_OA_RESET__RESET_MASK 0x00000001L |
21602 | #define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L |
21603 | #define GDS_OA_RESET__UNUSED_MASK 0xFFFF0000L |
21604 | //GDS_ENHANCE2 |
21605 | #define GDS_ENHANCE2__MISC__SHIFT 0x0 |
21606 | #define GDS_ENHANCE2__RD_BUF_TAG_MISS__SHIFT 0x12 |
21607 | #define GDS_ENHANCE2__GDSA_PC_CGTS_DIS__SHIFT 0x13 |
21608 | #define GDS_ENHANCE2__GDSO_PC_CGTS_DIS__SHIFT 0x14 |
21609 | #define GDS_ENHANCE2__WD_GDS_CSB_OVERRIDE__SHIFT 0x15 |
21610 | #define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS__SHIFT 0x16 |
21611 | #define GDS_ENHANCE2__DISABLE_LOGIC_ID_CLAMP__SHIFT 0x17 |
21612 | #define GDS_ENHANCE2__UNUSED__SHIFT 0x18 |
21613 | #define GDS_ENHANCE2__MISC_MASK 0x0003FFFFL |
21614 | #define GDS_ENHANCE2__RD_BUF_TAG_MISS_MASK 0x00040000L |
21615 | #define GDS_ENHANCE2__GDSA_PC_CGTS_DIS_MASK 0x00080000L |
21616 | #define GDS_ENHANCE2__GDSO_PC_CGTS_DIS_MASK 0x00100000L |
21617 | #define GDS_ENHANCE2__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L |
21618 | #define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS_MASK 0x00400000L |
21619 | #define GDS_ENHANCE2__DISABLE_LOGIC_ID_CLAMP_MASK 0x00800000L |
21620 | #define GDS_ENHANCE2__UNUSED_MASK 0xFF000000L |
21621 | //GDS_OA_CGPG_RESTORE |
21622 | #define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 |
21623 | #define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 |
21624 | #define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc |
21625 | #define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 |
21626 | #define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 |
21627 | #define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL |
21628 | #define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L |
21629 | #define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L |
21630 | #define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L |
21631 | #define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L |
21632 | //GDS_CS_CTXSW_STATUS |
21633 | #define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 |
21634 | #define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 |
21635 | #define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 |
21636 | #define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L |
21637 | #define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L |
21638 | #define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL |
21639 | //GDS_CS_CTXSW_CNT0 |
21640 | #define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 |
21641 | #define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 |
21642 | #define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
21643 | #define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
21644 | //GDS_CS_CTXSW_CNT1 |
21645 | #define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 |
21646 | #define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 |
21647 | #define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
21648 | #define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
21649 | //GDS_CS_CTXSW_CNT2 |
21650 | #define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 |
21651 | #define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 |
21652 | #define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
21653 | #define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
21654 | //GDS_CS_CTXSW_CNT3 |
21655 | #define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 |
21656 | #define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 |
21657 | #define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
21658 | #define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
21659 | //GDS_GFX_CTXSW_STATUS |
21660 | #define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 |
21661 | #define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 |
21662 | #define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 |
21663 | #define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L |
21664 | #define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L |
21665 | #define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL |
21666 | //GDS_VS_CTXSW_CNT0 |
21667 | #define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0 |
21668 | #define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10 |
21669 | #define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
21670 | #define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
21671 | //GDS_VS_CTXSW_CNT1 |
21672 | #define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0 |
21673 | #define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10 |
21674 | #define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
21675 | #define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
21676 | //GDS_VS_CTXSW_CNT2 |
21677 | #define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0 |
21678 | #define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10 |
21679 | #define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
21680 | #define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
21681 | //GDS_VS_CTXSW_CNT3 |
21682 | #define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0 |
21683 | #define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10 |
21684 | #define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
21685 | #define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
21686 | //GDS_PS_CTXSW_CNT0 |
21687 | #define GDS_PS_CTXSW_CNT0__UPDN__SHIFT 0x0 |
21688 | #define GDS_PS_CTXSW_CNT0__PTR__SHIFT 0x10 |
21689 | #define GDS_PS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
21690 | #define GDS_PS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
21691 | //GDS_PS_CTXSW_CNT1 |
21692 | #define GDS_PS_CTXSW_CNT1__UPDN__SHIFT 0x0 |
21693 | #define GDS_PS_CTXSW_CNT1__PTR__SHIFT 0x10 |
21694 | #define GDS_PS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
21695 | #define GDS_PS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
21696 | //GDS_PS_CTXSW_CNT2 |
21697 | #define GDS_PS_CTXSW_CNT2__UPDN__SHIFT 0x0 |
21698 | #define GDS_PS_CTXSW_CNT2__PTR__SHIFT 0x10 |
21699 | #define GDS_PS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
21700 | #define GDS_PS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
21701 | //GDS_PS_CTXSW_CNT3 |
21702 | #define GDS_PS_CTXSW_CNT3__UPDN__SHIFT 0x0 |
21703 | #define GDS_PS_CTXSW_CNT3__PTR__SHIFT 0x10 |
21704 | #define GDS_PS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
21705 | #define GDS_PS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
21706 | //GDS_PS_CTXSW_IDX |
21707 | #define GDS_PS_CTXSW_IDX__PACKER_ID__SHIFT 0x0 |
21708 | #define GDS_PS_CTXSW_IDX__UNUSED__SHIFT 0x4 |
21709 | #define GDS_PS_CTXSW_IDX__PACKER_ID_MASK 0x0000000FL |
21710 | #define GDS_PS_CTXSW_IDX__UNUSED_MASK 0xFFFFFFF0L |
21711 | //GDS_GS_CTXSW_CNT0 |
21712 | #define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0 |
21713 | #define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10 |
21714 | #define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
21715 | #define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
21716 | //GDS_GS_CTXSW_CNT1 |
21717 | #define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0 |
21718 | #define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10 |
21719 | #define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
21720 | #define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
21721 | //GDS_GS_CTXSW_CNT2 |
21722 | #define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0 |
21723 | #define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10 |
21724 | #define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
21725 | #define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
21726 | //GDS_GS_CTXSW_CNT3 |
21727 | #define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0 |
21728 | #define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10 |
21729 | #define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
21730 | #define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
21731 | |
21732 | |
21733 | // addressBlock: gc_gfxdec0 |
21734 | //DB_RENDER_CONTROL |
21735 | #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 |
21736 | #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 |
21737 | #define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 |
21738 | #define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 |
21739 | #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 |
21740 | #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 |
21741 | #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 |
21742 | #define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 |
21743 | #define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 |
21744 | #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc |
21745 | #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L |
21746 | #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L |
21747 | #define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L |
21748 | #define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L |
21749 | #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L |
21750 | #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L |
21751 | #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L |
21752 | #define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L |
21753 | #define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L |
21754 | #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L |
21755 | //DB_COUNT_CONTROL |
21756 | #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 |
21757 | #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 |
21758 | #define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS__SHIFT 0x2 |
21759 | #define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS__SHIFT 0x3 |
21760 | #define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 |
21761 | #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 |
21762 | #define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc |
21763 | #define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 |
21764 | #define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 |
21765 | #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 |
21766 | #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c |
21767 | #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L |
21768 | #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L |
21769 | #define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS_MASK 0x00000004L |
21770 | #define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS_MASK 0x00000008L |
21771 | #define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L |
21772 | #define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L |
21773 | #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L |
21774 | #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L |
21775 | #define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L |
21776 | #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L |
21777 | #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L |
21778 | //DB_DEPTH_VIEW |
21779 | #define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 |
21780 | #define DB_DEPTH_VIEW__SLICE_START_HI__SHIFT 0xb |
21781 | #define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd |
21782 | #define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 |
21783 | #define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 |
21784 | #define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a |
21785 | #define DB_DEPTH_VIEW__SLICE_MAX_HI__SHIFT 0x1e |
21786 | #define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL |
21787 | #define DB_DEPTH_VIEW__SLICE_START_HI_MASK 0x00001800L |
21788 | #define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L |
21789 | #define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L |
21790 | #define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L |
21791 | #define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L |
21792 | #define DB_DEPTH_VIEW__SLICE_MAX_HI_MASK 0xC0000000L |
21793 | //DB_RENDER_OVERRIDE |
21794 | #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 |
21795 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 |
21796 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 |
21797 | #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 |
21798 | #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 |
21799 | #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 |
21800 | #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 |
21801 | #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa |
21802 | #define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb |
21803 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc |
21804 | #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd |
21805 | #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf |
21806 | #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 |
21807 | #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 |
21808 | #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 |
21809 | #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 |
21810 | #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 |
21811 | #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a |
21812 | #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b |
21813 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c |
21814 | #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d |
21815 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e |
21816 | #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f |
21817 | #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L |
21818 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL |
21819 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L |
21820 | #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L |
21821 | #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L |
21822 | #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L |
21823 | #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L |
21824 | #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L |
21825 | #define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L |
21826 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L |
21827 | #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L |
21828 | #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L |
21829 | #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L |
21830 | #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L |
21831 | #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L |
21832 | #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L |
21833 | #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L |
21834 | #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L |
21835 | #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L |
21836 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L |
21837 | #define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L |
21838 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L |
21839 | #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L |
21840 | //DB_RENDER_OVERRIDE2 |
21841 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 |
21842 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 |
21843 | #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 |
21844 | #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 |
21845 | #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 |
21846 | #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 |
21847 | #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 |
21848 | #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa |
21849 | #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb |
21850 | #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc |
21851 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf |
21852 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 |
21853 | #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 |
21854 | #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 |
21855 | #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 |
21856 | #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 |
21857 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L |
21858 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL |
21859 | #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L |
21860 | #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L |
21861 | #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L |
21862 | #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L |
21863 | #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L |
21864 | #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L |
21865 | #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L |
21866 | #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L |
21867 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L |
21868 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L |
21869 | #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L |
21870 | #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L |
21871 | #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L |
21872 | #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L |
21873 | //DB_HTILE_DATA_BASE |
21874 | #define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 |
21875 | #define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL |
21876 | //DB_DEPTH_SIZE_XY |
21877 | #define DB_DEPTH_SIZE_XY__X_MAX__SHIFT 0x0 |
21878 | #define DB_DEPTH_SIZE_XY__Y_MAX__SHIFT 0x10 |
21879 | #define DB_DEPTH_SIZE_XY__X_MAX_MASK 0x00003FFFL |
21880 | #define DB_DEPTH_SIZE_XY__Y_MAX_MASK 0x3FFF0000L |
21881 | //DB_DEPTH_BOUNDS_MIN |
21882 | #define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 |
21883 | #define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL |
21884 | //DB_DEPTH_BOUNDS_MAX |
21885 | #define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 |
21886 | #define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL |
21887 | //DB_STENCIL_CLEAR |
21888 | #define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 |
21889 | #define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL |
21890 | //DB_DEPTH_CLEAR |
21891 | #define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 |
21892 | #define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL |
21893 | //PA_SC_SCREEN_SCISSOR_TL |
21894 | #define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 |
21895 | #define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 |
21896 | #define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL |
21897 | #define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L |
21898 | //PA_SC_SCREEN_SCISSOR_BR |
21899 | #define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 |
21900 | #define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 |
21901 | #define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL |
21902 | #define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L |
21903 | //DB_DFSM_CONTROL |
21904 | #define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0 |
21905 | #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2 |
21906 | #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3 |
21907 | #define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L |
21908 | #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L |
21909 | #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L |
21910 | //DB_RESERVED_REG_2 |
21911 | #define DB_RESERVED_REG_2__FIELD_1__SHIFT 0x0 |
21912 | #define DB_RESERVED_REG_2__FIELD_2__SHIFT 0x4 |
21913 | #define DB_RESERVED_REG_2__FIELD_3__SHIFT 0x8 |
21914 | #define DB_RESERVED_REG_2__FIELD_4__SHIFT 0xd |
21915 | #define DB_RESERVED_REG_2__FIELD_5__SHIFT 0xf |
21916 | #define DB_RESERVED_REG_2__FIELD_6__SHIFT 0x11 |
21917 | #define DB_RESERVED_REG_2__FIELD_7__SHIFT 0x13 |
21918 | #define DB_RESERVED_REG_2__FIELD_8__SHIFT 0x1c |
21919 | #define DB_RESERVED_REG_2__FIELD_1_MASK 0x0000000FL |
21920 | #define DB_RESERVED_REG_2__FIELD_2_MASK 0x000000F0L |
21921 | #define DB_RESERVED_REG_2__FIELD_3_MASK 0x00001F00L |
21922 | #define DB_RESERVED_REG_2__FIELD_4_MASK 0x00006000L |
21923 | #define DB_RESERVED_REG_2__FIELD_5_MASK 0x00018000L |
21924 | #define DB_RESERVED_REG_2__FIELD_6_MASK 0x00060000L |
21925 | #define DB_RESERVED_REG_2__FIELD_7_MASK 0x00180000L |
21926 | #define DB_RESERVED_REG_2__FIELD_8_MASK 0xF0000000L |
21927 | //DB_Z_INFO |
21928 | #define DB_Z_INFO__FORMAT__SHIFT 0x0 |
21929 | #define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 |
21930 | #define DB_Z_INFO__SW_MODE__SHIFT 0x4 |
21931 | #define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0x9 |
21932 | #define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xb |
21933 | #define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc |
21934 | #define DB_Z_INFO__RESERVED_FIELD_1__SHIFT 0xd |
21935 | #define DB_Z_INFO__MAXMIP__SHIFT 0x10 |
21936 | #define DB_Z_INFO__ITERATE_256__SHIFT 0x14 |
21937 | #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 |
21938 | #define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b |
21939 | #define DB_Z_INFO__READ_SIZE__SHIFT 0x1c |
21940 | #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d |
21941 | #define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f |
21942 | #define DB_Z_INFO__FORMAT_MASK 0x00000003L |
21943 | #define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL |
21944 | #define DB_Z_INFO__SW_MODE_MASK 0x000001F0L |
21945 | #define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00000600L |
21946 | #define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00000800L |
21947 | #define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L |
21948 | #define DB_Z_INFO__RESERVED_FIELD_1_MASK 0x0000E000L |
21949 | #define DB_Z_INFO__MAXMIP_MASK 0x000F0000L |
21950 | #define DB_Z_INFO__ITERATE_256_MASK 0x00100000L |
21951 | #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L |
21952 | #define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L |
21953 | #define DB_Z_INFO__READ_SIZE_MASK 0x10000000L |
21954 | #define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L |
21955 | #define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L |
21956 | //DB_STENCIL_INFO |
21957 | #define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 |
21958 | #define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4 |
21959 | #define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0x9 |
21960 | #define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xb |
21961 | #define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc |
21962 | #define DB_STENCIL_INFO__RESERVED_FIELD_1__SHIFT 0xd |
21963 | #define DB_STENCIL_INFO__ITERATE_256__SHIFT 0x14 |
21964 | #define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b |
21965 | #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d |
21966 | #define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L |
21967 | #define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L |
21968 | #define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00000600L |
21969 | #define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00000800L |
21970 | #define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L |
21971 | #define DB_STENCIL_INFO__RESERVED_FIELD_1_MASK 0x0000E000L |
21972 | #define DB_STENCIL_INFO__ITERATE_256_MASK 0x00100000L |
21973 | #define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L |
21974 | #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L |
21975 | //DB_Z_READ_BASE |
21976 | #define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 |
21977 | #define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL |
21978 | //DB_STENCIL_READ_BASE |
21979 | #define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 |
21980 | #define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL |
21981 | //DB_Z_WRITE_BASE |
21982 | #define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 |
21983 | #define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL |
21984 | //DB_STENCIL_WRITE_BASE |
21985 | #define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 |
21986 | #define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL |
21987 | //DB_RESERVED_REG_1 |
21988 | #define DB_RESERVED_REG_1__FIELD_1__SHIFT 0x0 |
21989 | #define DB_RESERVED_REG_1__FIELD_2__SHIFT 0xb |
21990 | #define DB_RESERVED_REG_1__FIELD_1_MASK 0x000007FFL |
21991 | #define DB_RESERVED_REG_1__FIELD_2_MASK 0x003FF800L |
21992 | //DB_RESERVED_REG_3 |
21993 | #define DB_RESERVED_REG_3__FIELD_1__SHIFT 0x0 |
21994 | #define DB_RESERVED_REG_3__FIELD_1_MASK 0x003FFFFFL |
21995 | //DB_Z_READ_BASE_HI |
21996 | #define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 |
21997 | #define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL |
21998 | //DB_STENCIL_READ_BASE_HI |
21999 | #define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0 |
22000 | #define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL |
22001 | //DB_Z_WRITE_BASE_HI |
22002 | #define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 |
22003 | #define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL |
22004 | //DB_STENCIL_WRITE_BASE_HI |
22005 | #define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 |
22006 | #define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL |
22007 | //DB_HTILE_DATA_BASE_HI |
22008 | #define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0 |
22009 | #define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL |
22010 | //DB_RMI_L2_CACHE_CONTROL |
22011 | #define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY__SHIFT 0x0 |
22012 | #define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY__SHIFT 0x2 |
22013 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT 0x4 |
22014 | #define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT 0x6 |
22015 | #define DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY__SHIFT 0x10 |
22016 | #define DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY__SHIFT 0x12 |
22017 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT 0x14 |
22018 | #define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE__SHIFT 0x18 |
22019 | #define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE__SHIFT 0x19 |
22020 | #define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY_MASK 0x00000003L |
22021 | #define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY_MASK 0x0000000CL |
22022 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY_MASK 0x00000030L |
22023 | #define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK 0x000000C0L |
22024 | #define DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY_MASK 0x00030000L |
22025 | #define DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY_MASK 0x000C0000L |
22026 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY_MASK 0x00300000L |
22027 | #define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE_MASK 0x01000000L |
22028 | #define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE_MASK 0x02000000L |
22029 | //TA_BC_BASE_ADDR |
22030 | #define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 |
22031 | #define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL |
22032 | //TA_BC_BASE_ADDR_HI |
22033 | #define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 |
22034 | #define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL |
22035 | //COHER_DEST_BASE_HI_0 |
22036 | #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 |
22037 | #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL |
22038 | //COHER_DEST_BASE_HI_1 |
22039 | #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 |
22040 | #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL |
22041 | //COHER_DEST_BASE_HI_2 |
22042 | #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 |
22043 | #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL |
22044 | //COHER_DEST_BASE_HI_3 |
22045 | #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 |
22046 | #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL |
22047 | //COHER_DEST_BASE_2 |
22048 | #define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 |
22049 | #define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL |
22050 | //COHER_DEST_BASE_3 |
22051 | #define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 |
22052 | #define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL |
22053 | //PA_SC_WINDOW_OFFSET |
22054 | #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 |
22055 | #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 |
22056 | #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL |
22057 | #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L |
22058 | //PA_SC_WINDOW_SCISSOR_TL |
22059 | #define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 |
22060 | #define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 |
22061 | #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22062 | #define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL |
22063 | #define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L |
22064 | #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22065 | //PA_SC_WINDOW_SCISSOR_BR |
22066 | #define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 |
22067 | #define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 |
22068 | #define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL |
22069 | #define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L |
22070 | //PA_SC_CLIPRECT_RULE |
22071 | #define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 |
22072 | #define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL |
22073 | //PA_SC_CLIPRECT_0_TL |
22074 | #define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 |
22075 | #define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 |
22076 | #define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL |
22077 | #define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L |
22078 | //PA_SC_CLIPRECT_0_BR |
22079 | #define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 |
22080 | #define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 |
22081 | #define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL |
22082 | #define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L |
22083 | //PA_SC_CLIPRECT_1_TL |
22084 | #define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 |
22085 | #define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 |
22086 | #define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL |
22087 | #define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L |
22088 | //PA_SC_CLIPRECT_1_BR |
22089 | #define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 |
22090 | #define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 |
22091 | #define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL |
22092 | #define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L |
22093 | //PA_SC_CLIPRECT_2_TL |
22094 | #define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 |
22095 | #define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 |
22096 | #define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL |
22097 | #define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L |
22098 | //PA_SC_CLIPRECT_2_BR |
22099 | #define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 |
22100 | #define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 |
22101 | #define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL |
22102 | #define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L |
22103 | //PA_SC_CLIPRECT_3_TL |
22104 | #define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 |
22105 | #define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 |
22106 | #define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL |
22107 | #define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L |
22108 | //PA_SC_CLIPRECT_3_BR |
22109 | #define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 |
22110 | #define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 |
22111 | #define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL |
22112 | #define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L |
22113 | //PA_SC_EDGERULE |
22114 | #define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 |
22115 | #define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 |
22116 | #define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 |
22117 | #define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc |
22118 | #define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 |
22119 | #define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 |
22120 | #define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c |
22121 | #define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL |
22122 | #define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L |
22123 | #define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L |
22124 | #define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L |
22125 | #define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L |
22126 | #define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L |
22127 | #define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L |
22128 | //PA_SU_HARDWARE_SCREEN_OFFSET |
22129 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 |
22130 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 |
22131 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL |
22132 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L |
22133 | //CB_TARGET_MASK |
22134 | #define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 |
22135 | #define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 |
22136 | #define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 |
22137 | #define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc |
22138 | #define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 |
22139 | #define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 |
22140 | #define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 |
22141 | #define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c |
22142 | #define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL |
22143 | #define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L |
22144 | #define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L |
22145 | #define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L |
22146 | #define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L |
22147 | #define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L |
22148 | #define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L |
22149 | #define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L |
22150 | //CB_SHADER_MASK |
22151 | #define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 |
22152 | #define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 |
22153 | #define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 |
22154 | #define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc |
22155 | #define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 |
22156 | #define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 |
22157 | #define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 |
22158 | #define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c |
22159 | #define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL |
22160 | #define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L |
22161 | #define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L |
22162 | #define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L |
22163 | #define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L |
22164 | #define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L |
22165 | #define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L |
22166 | #define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L |
22167 | //PA_SC_GENERIC_SCISSOR_TL |
22168 | #define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 |
22169 | #define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 |
22170 | #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22171 | #define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL |
22172 | #define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L |
22173 | #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22174 | //PA_SC_GENERIC_SCISSOR_BR |
22175 | #define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 |
22176 | #define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 |
22177 | #define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL |
22178 | #define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L |
22179 | //COHER_DEST_BASE_0 |
22180 | #define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 |
22181 | #define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL |
22182 | //COHER_DEST_BASE_1 |
22183 | #define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 |
22184 | #define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL |
22185 | //PA_SC_VPORT_SCISSOR_0_TL |
22186 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 |
22187 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 |
22188 | #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22189 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL |
22190 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L |
22191 | #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22192 | //PA_SC_VPORT_SCISSOR_0_BR |
22193 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 |
22194 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 |
22195 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL |
22196 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L |
22197 | //PA_SC_VPORT_SCISSOR_1_TL |
22198 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 |
22199 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 |
22200 | #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22201 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL |
22202 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L |
22203 | #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22204 | //PA_SC_VPORT_SCISSOR_1_BR |
22205 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 |
22206 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 |
22207 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL |
22208 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L |
22209 | //PA_SC_VPORT_SCISSOR_2_TL |
22210 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 |
22211 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 |
22212 | #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22213 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL |
22214 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L |
22215 | #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22216 | //PA_SC_VPORT_SCISSOR_2_BR |
22217 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 |
22218 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 |
22219 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL |
22220 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L |
22221 | //PA_SC_VPORT_SCISSOR_3_TL |
22222 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 |
22223 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 |
22224 | #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22225 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL |
22226 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L |
22227 | #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22228 | //PA_SC_VPORT_SCISSOR_3_BR |
22229 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 |
22230 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 |
22231 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL |
22232 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L |
22233 | //PA_SC_VPORT_SCISSOR_4_TL |
22234 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 |
22235 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 |
22236 | #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22237 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL |
22238 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L |
22239 | #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22240 | //PA_SC_VPORT_SCISSOR_4_BR |
22241 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 |
22242 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 |
22243 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL |
22244 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L |
22245 | //PA_SC_VPORT_SCISSOR_5_TL |
22246 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 |
22247 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 |
22248 | #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22249 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL |
22250 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L |
22251 | #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22252 | //PA_SC_VPORT_SCISSOR_5_BR |
22253 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 |
22254 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 |
22255 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL |
22256 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L |
22257 | //PA_SC_VPORT_SCISSOR_6_TL |
22258 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 |
22259 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 |
22260 | #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22261 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL |
22262 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L |
22263 | #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22264 | //PA_SC_VPORT_SCISSOR_6_BR |
22265 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 |
22266 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 |
22267 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL |
22268 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L |
22269 | //PA_SC_VPORT_SCISSOR_7_TL |
22270 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 |
22271 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 |
22272 | #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22273 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL |
22274 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L |
22275 | #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22276 | //PA_SC_VPORT_SCISSOR_7_BR |
22277 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 |
22278 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 |
22279 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL |
22280 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L |
22281 | //PA_SC_VPORT_SCISSOR_8_TL |
22282 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 |
22283 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 |
22284 | #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22285 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL |
22286 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L |
22287 | #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22288 | //PA_SC_VPORT_SCISSOR_8_BR |
22289 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 |
22290 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 |
22291 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL |
22292 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L |
22293 | //PA_SC_VPORT_SCISSOR_9_TL |
22294 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 |
22295 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 |
22296 | #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22297 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL |
22298 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L |
22299 | #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22300 | //PA_SC_VPORT_SCISSOR_9_BR |
22301 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 |
22302 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 |
22303 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL |
22304 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L |
22305 | //PA_SC_VPORT_SCISSOR_10_TL |
22306 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 |
22307 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 |
22308 | #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22309 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL |
22310 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L |
22311 | #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22312 | //PA_SC_VPORT_SCISSOR_10_BR |
22313 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 |
22314 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 |
22315 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL |
22316 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L |
22317 | //PA_SC_VPORT_SCISSOR_11_TL |
22318 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 |
22319 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 |
22320 | #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22321 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL |
22322 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L |
22323 | #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22324 | //PA_SC_VPORT_SCISSOR_11_BR |
22325 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 |
22326 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 |
22327 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL |
22328 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L |
22329 | //PA_SC_VPORT_SCISSOR_12_TL |
22330 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 |
22331 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 |
22332 | #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22333 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL |
22334 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L |
22335 | #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22336 | //PA_SC_VPORT_SCISSOR_12_BR |
22337 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 |
22338 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 |
22339 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL |
22340 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L |
22341 | //PA_SC_VPORT_SCISSOR_13_TL |
22342 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 |
22343 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 |
22344 | #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22345 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL |
22346 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L |
22347 | #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22348 | //PA_SC_VPORT_SCISSOR_13_BR |
22349 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 |
22350 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 |
22351 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL |
22352 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L |
22353 | //PA_SC_VPORT_SCISSOR_14_TL |
22354 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 |
22355 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 |
22356 | #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22357 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL |
22358 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L |
22359 | #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22360 | //PA_SC_VPORT_SCISSOR_14_BR |
22361 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 |
22362 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 |
22363 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL |
22364 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L |
22365 | //PA_SC_VPORT_SCISSOR_15_TL |
22366 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 |
22367 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 |
22368 | #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22369 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL |
22370 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L |
22371 | #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22372 | //PA_SC_VPORT_SCISSOR_15_BR |
22373 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 |
22374 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 |
22375 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL |
22376 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L |
22377 | //PA_SC_VPORT_ZMIN_0 |
22378 | #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 |
22379 | #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22380 | //PA_SC_VPORT_ZMAX_0 |
22381 | #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 |
22382 | #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22383 | //PA_SC_VPORT_ZMIN_1 |
22384 | #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 |
22385 | #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22386 | //PA_SC_VPORT_ZMAX_1 |
22387 | #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 |
22388 | #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22389 | //PA_SC_VPORT_ZMIN_2 |
22390 | #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 |
22391 | #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22392 | //PA_SC_VPORT_ZMAX_2 |
22393 | #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 |
22394 | #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22395 | //PA_SC_VPORT_ZMIN_3 |
22396 | #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 |
22397 | #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22398 | //PA_SC_VPORT_ZMAX_3 |
22399 | #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 |
22400 | #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22401 | //PA_SC_VPORT_ZMIN_4 |
22402 | #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 |
22403 | #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22404 | //PA_SC_VPORT_ZMAX_4 |
22405 | #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 |
22406 | #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22407 | //PA_SC_VPORT_ZMIN_5 |
22408 | #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 |
22409 | #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22410 | //PA_SC_VPORT_ZMAX_5 |
22411 | #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 |
22412 | #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22413 | //PA_SC_VPORT_ZMIN_6 |
22414 | #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 |
22415 | #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22416 | //PA_SC_VPORT_ZMAX_6 |
22417 | #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 |
22418 | #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22419 | //PA_SC_VPORT_ZMIN_7 |
22420 | #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 |
22421 | #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22422 | //PA_SC_VPORT_ZMAX_7 |
22423 | #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 |
22424 | #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22425 | //PA_SC_VPORT_ZMIN_8 |
22426 | #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 |
22427 | #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22428 | //PA_SC_VPORT_ZMAX_8 |
22429 | #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 |
22430 | #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22431 | //PA_SC_VPORT_ZMIN_9 |
22432 | #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 |
22433 | #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22434 | //PA_SC_VPORT_ZMAX_9 |
22435 | #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 |
22436 | #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22437 | //PA_SC_VPORT_ZMIN_10 |
22438 | #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 |
22439 | #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22440 | //PA_SC_VPORT_ZMAX_10 |
22441 | #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 |
22442 | #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22443 | //PA_SC_VPORT_ZMIN_11 |
22444 | #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 |
22445 | #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22446 | //PA_SC_VPORT_ZMAX_11 |
22447 | #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 |
22448 | #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22449 | //PA_SC_VPORT_ZMIN_12 |
22450 | #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 |
22451 | #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22452 | //PA_SC_VPORT_ZMAX_12 |
22453 | #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 |
22454 | #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22455 | //PA_SC_VPORT_ZMIN_13 |
22456 | #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 |
22457 | #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22458 | //PA_SC_VPORT_ZMAX_13 |
22459 | #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 |
22460 | #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22461 | //PA_SC_VPORT_ZMIN_14 |
22462 | #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 |
22463 | #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22464 | //PA_SC_VPORT_ZMAX_14 |
22465 | #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 |
22466 | #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22467 | //PA_SC_VPORT_ZMIN_15 |
22468 | #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 |
22469 | #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22470 | //PA_SC_VPORT_ZMAX_15 |
22471 | #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 |
22472 | #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22473 | //PA_SC_RASTER_CONFIG |
22474 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 |
22475 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 |
22476 | #define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 |
22477 | #define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 |
22478 | #define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 |
22479 | #define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 |
22480 | #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa |
22481 | #define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc |
22482 | #define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe |
22483 | #define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 |
22484 | #define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 |
22485 | #define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 |
22486 | #define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 |
22487 | #define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a |
22488 | #define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c |
22489 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L |
22490 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL |
22491 | #define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L |
22492 | #define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L |
22493 | #define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L |
22494 | #define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L |
22495 | #define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L |
22496 | #define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L |
22497 | #define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L |
22498 | #define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L |
22499 | #define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L |
22500 | #define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L |
22501 | #define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L |
22502 | #define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x0C000000L |
22503 | #define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000L |
22504 | //PA_SC_RASTER_CONFIG_1 |
22505 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 |
22506 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 |
22507 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4 |
22508 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L |
22509 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000000CL |
22510 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x00000030L |
22511 | //PA_SC_SCREEN_EXTENT_CONTROL |
22512 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 |
22513 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 |
22514 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L |
22515 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL |
22516 | //PA_SC_TILE_STEERING_OVERRIDE |
22517 | #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 |
22518 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1 |
22519 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5 |
22520 | #define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x8 |
22521 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT 0xc |
22522 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT 0x10 |
22523 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT 0x14 |
22524 | #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L |
22525 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L |
22526 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L |
22527 | #define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L |
22528 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK 0x00003000L |
22529 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK 0x00030000L |
22530 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK 0x00100000L |
22531 | //CP_PERFMON_CNTX_CNTL |
22532 | #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f |
22533 | #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L |
22534 | //CP_PIPEID |
22535 | #define CP_PIPEID__PIPE_ID__SHIFT 0x0 |
22536 | #define CP_PIPEID__PIPE_ID_MASK 0x00000003L |
22537 | //CP_RINGID |
22538 | #define CP_RINGID__RINGID__SHIFT 0x0 |
22539 | #define CP_RINGID__RINGID_MASK 0x00000003L |
22540 | //CP_VMID |
22541 | #define CP_VMID__VMID__SHIFT 0x0 |
22542 | #define CP_VMID__VMID_MASK 0x0000000FL |
22543 | //PA_SC_RIGHT_VERT_GRID |
22544 | #define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0 |
22545 | #define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8 |
22546 | #define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 |
22547 | #define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 |
22548 | #define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL |
22549 | #define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L |
22550 | #define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L |
22551 | #define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L |
22552 | //PA_SC_LEFT_VERT_GRID |
22553 | #define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0 |
22554 | #define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8 |
22555 | #define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 |
22556 | #define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 |
22557 | #define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL |
22558 | #define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L |
22559 | #define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L |
22560 | #define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L |
22561 | //PA_SC_HORIZ_GRID |
22562 | #define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0 |
22563 | #define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8 |
22564 | #define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10 |
22565 | #define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18 |
22566 | #define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL |
22567 | #define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L |
22568 | #define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L |
22569 | #define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L |
22570 | //VGT_MAX_VTX_INDX |
22571 | #define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 |
22572 | #define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL |
22573 | //VGT_MIN_VTX_INDX |
22574 | #define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 |
22575 | #define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL |
22576 | //VGT_INDX_OFFSET |
22577 | #define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 |
22578 | #define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL |
22579 | //VGT_MULTI_PRIM_IB_RESET_INDX |
22580 | #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 |
22581 | #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL |
22582 | //CB_RMI_GL2_CACHE_CONTROL |
22583 | #define CB_RMI_GL2_CACHE_CONTROL__CMASK_WR_POLICY__SHIFT 0x0 |
22584 | #define CB_RMI_GL2_CACHE_CONTROL__FMASK_WR_POLICY__SHIFT 0x2 |
22585 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT 0x4 |
22586 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT 0x6 |
22587 | #define CB_RMI_GL2_CACHE_CONTROL__CMASK_RD_POLICY__SHIFT 0x10 |
22588 | #define CB_RMI_GL2_CACHE_CONTROL__FMASK_RD_POLICY__SHIFT 0x12 |
22589 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT 0x14 |
22590 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT 0x16 |
22591 | #define CB_RMI_GL2_CACHE_CONTROL__FMASK_BIG_PAGE__SHIFT 0x1e |
22592 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE__SHIFT 0x1f |
22593 | #define CB_RMI_GL2_CACHE_CONTROL__CMASK_WR_POLICY_MASK 0x00000003L |
22594 | #define CB_RMI_GL2_CACHE_CONTROL__FMASK_WR_POLICY_MASK 0x0000000CL |
22595 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK 0x00000030L |
22596 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK 0x000000C0L |
22597 | #define CB_RMI_GL2_CACHE_CONTROL__CMASK_RD_POLICY_MASK 0x00030000L |
22598 | #define CB_RMI_GL2_CACHE_CONTROL__FMASK_RD_POLICY_MASK 0x000C0000L |
22599 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK 0x00300000L |
22600 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK 0x00C00000L |
22601 | #define CB_RMI_GL2_CACHE_CONTROL__FMASK_BIG_PAGE_MASK 0x40000000L |
22602 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE_MASK 0x80000000L |
22603 | //CB_BLEND_RED |
22604 | #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 |
22605 | #define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL |
22606 | //CB_BLEND_GREEN |
22607 | #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 |
22608 | #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL |
22609 | //CB_BLEND_BLUE |
22610 | #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 |
22611 | #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL |
22612 | //CB_BLEND_ALPHA |
22613 | #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 |
22614 | #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL |
22615 | //CB_DCC_CONTROL |
22616 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
22617 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2 |
22618 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT 0x8 |
22619 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT 0x9 |
22620 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0xa |
22621 | #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT 0xc |
22622 | #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT 0xd |
22623 | #define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT 0xe |
22624 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
22625 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL |
22626 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK 0x00000100L |
22627 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK 0x00000200L |
22628 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00000400L |
22629 | #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK 0x00001000L |
22630 | #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK 0x00002000L |
22631 | #define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK 0x00004000L |
22632 | //CB_COVERAGE_OUT_CONTROL |
22633 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE__SHIFT 0x0 |
22634 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT__SHIFT 0x1 |
22635 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL__SHIFT 0x4 |
22636 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES__SHIFT 0x8 |
22637 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE_MASK 0x00000001L |
22638 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT_MASK 0x0000000EL |
22639 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL_MASK 0x00000030L |
22640 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES_MASK 0x00000F00L |
22641 | //DB_STENCIL_CONTROL |
22642 | #define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 |
22643 | #define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 |
22644 | #define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 |
22645 | #define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc |
22646 | #define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 |
22647 | #define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 |
22648 | #define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL |
22649 | #define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L |
22650 | #define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L |
22651 | #define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L |
22652 | #define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L |
22653 | #define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L |
22654 | //DB_STENCILREFMASK |
22655 | #define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 |
22656 | #define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 |
22657 | #define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 |
22658 | #define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 |
22659 | #define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL |
22660 | #define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L |
22661 | #define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L |
22662 | #define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L |
22663 | //DB_STENCILREFMASK_BF |
22664 | #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 |
22665 | #define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 |
22666 | #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 |
22667 | #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 |
22668 | #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL |
22669 | #define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L |
22670 | #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L |
22671 | #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L |
22672 | //PA_CL_VPORT_XSCALE |
22673 | #define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 |
22674 | #define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22675 | //PA_CL_VPORT_XOFFSET |
22676 | #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 |
22677 | #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22678 | //PA_CL_VPORT_YSCALE |
22679 | #define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 |
22680 | #define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22681 | //PA_CL_VPORT_YOFFSET |
22682 | #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 |
22683 | #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22684 | //PA_CL_VPORT_ZSCALE |
22685 | #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 |
22686 | #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22687 | //PA_CL_VPORT_ZOFFSET |
22688 | #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 |
22689 | #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22690 | //PA_CL_VPORT_XSCALE_1 |
22691 | #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 |
22692 | #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22693 | //PA_CL_VPORT_XOFFSET_1 |
22694 | #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 |
22695 | #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22696 | //PA_CL_VPORT_YSCALE_1 |
22697 | #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 |
22698 | #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22699 | //PA_CL_VPORT_YOFFSET_1 |
22700 | #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 |
22701 | #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22702 | //PA_CL_VPORT_ZSCALE_1 |
22703 | #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 |
22704 | #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22705 | //PA_CL_VPORT_ZOFFSET_1 |
22706 | #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 |
22707 | #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22708 | //PA_CL_VPORT_XSCALE_2 |
22709 | #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 |
22710 | #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22711 | //PA_CL_VPORT_XOFFSET_2 |
22712 | #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 |
22713 | #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22714 | //PA_CL_VPORT_YSCALE_2 |
22715 | #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 |
22716 | #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22717 | //PA_CL_VPORT_YOFFSET_2 |
22718 | #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 |
22719 | #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22720 | //PA_CL_VPORT_ZSCALE_2 |
22721 | #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 |
22722 | #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22723 | //PA_CL_VPORT_ZOFFSET_2 |
22724 | #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 |
22725 | #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22726 | //PA_CL_VPORT_XSCALE_3 |
22727 | #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 |
22728 | #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22729 | //PA_CL_VPORT_XOFFSET_3 |
22730 | #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 |
22731 | #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22732 | //PA_CL_VPORT_YSCALE_3 |
22733 | #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 |
22734 | #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22735 | //PA_CL_VPORT_YOFFSET_3 |
22736 | #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 |
22737 | #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22738 | //PA_CL_VPORT_ZSCALE_3 |
22739 | #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 |
22740 | #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22741 | //PA_CL_VPORT_ZOFFSET_3 |
22742 | #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 |
22743 | #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22744 | //PA_CL_VPORT_XSCALE_4 |
22745 | #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 |
22746 | #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22747 | //PA_CL_VPORT_XOFFSET_4 |
22748 | #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 |
22749 | #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22750 | //PA_CL_VPORT_YSCALE_4 |
22751 | #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 |
22752 | #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22753 | //PA_CL_VPORT_YOFFSET_4 |
22754 | #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 |
22755 | #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22756 | //PA_CL_VPORT_ZSCALE_4 |
22757 | #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 |
22758 | #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22759 | //PA_CL_VPORT_ZOFFSET_4 |
22760 | #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 |
22761 | #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22762 | //PA_CL_VPORT_XSCALE_5 |
22763 | #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 |
22764 | #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22765 | //PA_CL_VPORT_XOFFSET_5 |
22766 | #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 |
22767 | #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22768 | //PA_CL_VPORT_YSCALE_5 |
22769 | #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 |
22770 | #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22771 | //PA_CL_VPORT_YOFFSET_5 |
22772 | #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 |
22773 | #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22774 | //PA_CL_VPORT_ZSCALE_5 |
22775 | #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 |
22776 | #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22777 | //PA_CL_VPORT_ZOFFSET_5 |
22778 | #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 |
22779 | #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22780 | //PA_CL_VPORT_XSCALE_6 |
22781 | #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 |
22782 | #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22783 | //PA_CL_VPORT_XOFFSET_6 |
22784 | #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 |
22785 | #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22786 | //PA_CL_VPORT_YSCALE_6 |
22787 | #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 |
22788 | #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22789 | //PA_CL_VPORT_YOFFSET_6 |
22790 | #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 |
22791 | #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22792 | //PA_CL_VPORT_ZSCALE_6 |
22793 | #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 |
22794 | #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22795 | //PA_CL_VPORT_ZOFFSET_6 |
22796 | #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 |
22797 | #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22798 | //PA_CL_VPORT_XSCALE_7 |
22799 | #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 |
22800 | #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22801 | //PA_CL_VPORT_XOFFSET_7 |
22802 | #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 |
22803 | #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22804 | //PA_CL_VPORT_YSCALE_7 |
22805 | #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 |
22806 | #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22807 | //PA_CL_VPORT_YOFFSET_7 |
22808 | #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 |
22809 | #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22810 | //PA_CL_VPORT_ZSCALE_7 |
22811 | #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 |
22812 | #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22813 | //PA_CL_VPORT_ZOFFSET_7 |
22814 | #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 |
22815 | #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22816 | //PA_CL_VPORT_XSCALE_8 |
22817 | #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 |
22818 | #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22819 | //PA_CL_VPORT_XOFFSET_8 |
22820 | #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 |
22821 | #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22822 | //PA_CL_VPORT_YSCALE_8 |
22823 | #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 |
22824 | #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22825 | //PA_CL_VPORT_YOFFSET_8 |
22826 | #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 |
22827 | #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22828 | //PA_CL_VPORT_ZSCALE_8 |
22829 | #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 |
22830 | #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22831 | //PA_CL_VPORT_ZOFFSET_8 |
22832 | #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 |
22833 | #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22834 | //PA_CL_VPORT_XSCALE_9 |
22835 | #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 |
22836 | #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22837 | //PA_CL_VPORT_XOFFSET_9 |
22838 | #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 |
22839 | #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22840 | //PA_CL_VPORT_YSCALE_9 |
22841 | #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 |
22842 | #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22843 | //PA_CL_VPORT_YOFFSET_9 |
22844 | #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 |
22845 | #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22846 | //PA_CL_VPORT_ZSCALE_9 |
22847 | #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 |
22848 | #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22849 | //PA_CL_VPORT_ZOFFSET_9 |
22850 | #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 |
22851 | #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22852 | //PA_CL_VPORT_XSCALE_10 |
22853 | #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 |
22854 | #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22855 | //PA_CL_VPORT_XOFFSET_10 |
22856 | #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 |
22857 | #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22858 | //PA_CL_VPORT_YSCALE_10 |
22859 | #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 |
22860 | #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22861 | //PA_CL_VPORT_YOFFSET_10 |
22862 | #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 |
22863 | #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22864 | //PA_CL_VPORT_ZSCALE_10 |
22865 | #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 |
22866 | #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22867 | //PA_CL_VPORT_ZOFFSET_10 |
22868 | #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 |
22869 | #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22870 | //PA_CL_VPORT_XSCALE_11 |
22871 | #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 |
22872 | #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22873 | //PA_CL_VPORT_XOFFSET_11 |
22874 | #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 |
22875 | #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22876 | //PA_CL_VPORT_YSCALE_11 |
22877 | #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 |
22878 | #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22879 | //PA_CL_VPORT_YOFFSET_11 |
22880 | #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 |
22881 | #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22882 | //PA_CL_VPORT_ZSCALE_11 |
22883 | #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 |
22884 | #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22885 | //PA_CL_VPORT_ZOFFSET_11 |
22886 | #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 |
22887 | #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22888 | //PA_CL_VPORT_XSCALE_12 |
22889 | #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 |
22890 | #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22891 | //PA_CL_VPORT_XOFFSET_12 |
22892 | #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 |
22893 | #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22894 | //PA_CL_VPORT_YSCALE_12 |
22895 | #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 |
22896 | #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22897 | //PA_CL_VPORT_YOFFSET_12 |
22898 | #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 |
22899 | #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22900 | //PA_CL_VPORT_ZSCALE_12 |
22901 | #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 |
22902 | #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22903 | //PA_CL_VPORT_ZOFFSET_12 |
22904 | #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 |
22905 | #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22906 | //PA_CL_VPORT_XSCALE_13 |
22907 | #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 |
22908 | #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22909 | //PA_CL_VPORT_XOFFSET_13 |
22910 | #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 |
22911 | #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22912 | //PA_CL_VPORT_YSCALE_13 |
22913 | #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 |
22914 | #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22915 | //PA_CL_VPORT_YOFFSET_13 |
22916 | #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 |
22917 | #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22918 | //PA_CL_VPORT_ZSCALE_13 |
22919 | #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 |
22920 | #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22921 | //PA_CL_VPORT_ZOFFSET_13 |
22922 | #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 |
22923 | #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22924 | //PA_CL_VPORT_XSCALE_14 |
22925 | #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 |
22926 | #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22927 | //PA_CL_VPORT_XOFFSET_14 |
22928 | #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 |
22929 | #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22930 | //PA_CL_VPORT_YSCALE_14 |
22931 | #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 |
22932 | #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22933 | //PA_CL_VPORT_YOFFSET_14 |
22934 | #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 |
22935 | #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22936 | //PA_CL_VPORT_ZSCALE_14 |
22937 | #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 |
22938 | #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22939 | //PA_CL_VPORT_ZOFFSET_14 |
22940 | #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 |
22941 | #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22942 | //PA_CL_VPORT_XSCALE_15 |
22943 | #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 |
22944 | #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22945 | //PA_CL_VPORT_XOFFSET_15 |
22946 | #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 |
22947 | #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22948 | //PA_CL_VPORT_YSCALE_15 |
22949 | #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 |
22950 | #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22951 | //PA_CL_VPORT_YOFFSET_15 |
22952 | #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 |
22953 | #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22954 | //PA_CL_VPORT_ZSCALE_15 |
22955 | #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 |
22956 | #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22957 | //PA_CL_VPORT_ZOFFSET_15 |
22958 | #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 |
22959 | #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22960 | //PA_CL_UCP_0_X |
22961 | #define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 |
22962 | #define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
22963 | //PA_CL_UCP_0_Y |
22964 | #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 |
22965 | #define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
22966 | //PA_CL_UCP_0_Z |
22967 | #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 |
22968 | #define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
22969 | //PA_CL_UCP_0_W |
22970 | #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 |
22971 | #define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
22972 | //PA_CL_UCP_1_X |
22973 | #define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 |
22974 | #define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
22975 | //PA_CL_UCP_1_Y |
22976 | #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 |
22977 | #define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
22978 | //PA_CL_UCP_1_Z |
22979 | #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 |
22980 | #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
22981 | //PA_CL_UCP_1_W |
22982 | #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 |
22983 | #define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
22984 | //PA_CL_UCP_2_X |
22985 | #define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 |
22986 | #define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
22987 | //PA_CL_UCP_2_Y |
22988 | #define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 |
22989 | #define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
22990 | //PA_CL_UCP_2_Z |
22991 | #define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 |
22992 | #define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
22993 | //PA_CL_UCP_2_W |
22994 | #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 |
22995 | #define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
22996 | //PA_CL_UCP_3_X |
22997 | #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 |
22998 | #define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
22999 | //PA_CL_UCP_3_Y |
23000 | #define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 |
23001 | #define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
23002 | //PA_CL_UCP_3_Z |
23003 | #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 |
23004 | #define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
23005 | //PA_CL_UCP_3_W |
23006 | #define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 |
23007 | #define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
23008 | //PA_CL_UCP_4_X |
23009 | #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 |
23010 | #define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
23011 | //PA_CL_UCP_4_Y |
23012 | #define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 |
23013 | #define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
23014 | //PA_CL_UCP_4_Z |
23015 | #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 |
23016 | #define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
23017 | //PA_CL_UCP_4_W |
23018 | #define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 |
23019 | #define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
23020 | //PA_CL_UCP_5_X |
23021 | #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 |
23022 | #define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
23023 | //PA_CL_UCP_5_Y |
23024 | #define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 |
23025 | #define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
23026 | //PA_CL_UCP_5_Z |
23027 | #define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 |
23028 | #define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
23029 | //PA_CL_UCP_5_W |
23030 | #define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 |
23031 | #define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
23032 | //PA_CL_PROG_NEAR_CLIP_Z |
23033 | #define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT 0x0 |
23034 | #define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
23035 | //SPI_PS_INPUT_CNTL_0 |
23036 | #define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 |
23037 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 |
23038 | #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa |
23039 | #define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd |
23040 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 |
23041 | #define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 |
23042 | #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 |
23043 | #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23044 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23045 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23046 | #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 |
23047 | #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 |
23048 | #define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL |
23049 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L |
23050 | #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L |
23051 | #define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L |
23052 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L |
23053 | #define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L |
23054 | #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L |
23055 | #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23056 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23057 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23058 | #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L |
23059 | #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L |
23060 | //SPI_PS_INPUT_CNTL_1 |
23061 | #define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 |
23062 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 |
23063 | #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa |
23064 | #define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd |
23065 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 |
23066 | #define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 |
23067 | #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 |
23068 | #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23069 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23070 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23071 | #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 |
23072 | #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 |
23073 | #define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL |
23074 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L |
23075 | #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L |
23076 | #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L |
23077 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L |
23078 | #define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L |
23079 | #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L |
23080 | #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23081 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23082 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23083 | #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L |
23084 | #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L |
23085 | //SPI_PS_INPUT_CNTL_2 |
23086 | #define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 |
23087 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 |
23088 | #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa |
23089 | #define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd |
23090 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 |
23091 | #define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 |
23092 | #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 |
23093 | #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23094 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23095 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23096 | #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 |
23097 | #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 |
23098 | #define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL |
23099 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L |
23100 | #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L |
23101 | #define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L |
23102 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L |
23103 | #define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L |
23104 | #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L |
23105 | #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23106 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23107 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23108 | #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L |
23109 | #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L |
23110 | //SPI_PS_INPUT_CNTL_3 |
23111 | #define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 |
23112 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 |
23113 | #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa |
23114 | #define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd |
23115 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 |
23116 | #define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 |
23117 | #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 |
23118 | #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23119 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23120 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23121 | #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 |
23122 | #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 |
23123 | #define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL |
23124 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L |
23125 | #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L |
23126 | #define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L |
23127 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L |
23128 | #define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L |
23129 | #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L |
23130 | #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23131 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23132 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23133 | #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L |
23134 | #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L |
23135 | //SPI_PS_INPUT_CNTL_4 |
23136 | #define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 |
23137 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 |
23138 | #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa |
23139 | #define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd |
23140 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 |
23141 | #define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 |
23142 | #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 |
23143 | #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23144 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23145 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23146 | #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 |
23147 | #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 |
23148 | #define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL |
23149 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L |
23150 | #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L |
23151 | #define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L |
23152 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L |
23153 | #define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L |
23154 | #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L |
23155 | #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23156 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23157 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23158 | #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L |
23159 | #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L |
23160 | //SPI_PS_INPUT_CNTL_5 |
23161 | #define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 |
23162 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 |
23163 | #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa |
23164 | #define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd |
23165 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 |
23166 | #define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 |
23167 | #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 |
23168 | #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23169 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23170 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23171 | #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 |
23172 | #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 |
23173 | #define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL |
23174 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L |
23175 | #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L |
23176 | #define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L |
23177 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L |
23178 | #define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L |
23179 | #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L |
23180 | #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23181 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23182 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23183 | #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L |
23184 | #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L |
23185 | //SPI_PS_INPUT_CNTL_6 |
23186 | #define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 |
23187 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 |
23188 | #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa |
23189 | #define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd |
23190 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 |
23191 | #define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 |
23192 | #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 |
23193 | #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23194 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23195 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23196 | #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 |
23197 | #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 |
23198 | #define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL |
23199 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L |
23200 | #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L |
23201 | #define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L |
23202 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L |
23203 | #define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L |
23204 | #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L |
23205 | #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23206 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23207 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23208 | #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L |
23209 | #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L |
23210 | //SPI_PS_INPUT_CNTL_7 |
23211 | #define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 |
23212 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 |
23213 | #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa |
23214 | #define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd |
23215 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 |
23216 | #define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 |
23217 | #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 |
23218 | #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23219 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23220 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23221 | #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 |
23222 | #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 |
23223 | #define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL |
23224 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L |
23225 | #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L |
23226 | #define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L |
23227 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L |
23228 | #define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L |
23229 | #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L |
23230 | #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23231 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23232 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23233 | #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L |
23234 | #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L |
23235 | //SPI_PS_INPUT_CNTL_8 |
23236 | #define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 |
23237 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 |
23238 | #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa |
23239 | #define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd |
23240 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 |
23241 | #define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 |
23242 | #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 |
23243 | #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23244 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23245 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23246 | #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 |
23247 | #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 |
23248 | #define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL |
23249 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L |
23250 | #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L |
23251 | #define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L |
23252 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L |
23253 | #define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L |
23254 | #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L |
23255 | #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23256 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23257 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23258 | #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L |
23259 | #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L |
23260 | //SPI_PS_INPUT_CNTL_9 |
23261 | #define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 |
23262 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 |
23263 | #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa |
23264 | #define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd |
23265 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 |
23266 | #define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 |
23267 | #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 |
23268 | #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23269 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23270 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23271 | #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 |
23272 | #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 |
23273 | #define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL |
23274 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L |
23275 | #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L |
23276 | #define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L |
23277 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L |
23278 | #define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L |
23279 | #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L |
23280 | #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23281 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23282 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23283 | #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L |
23284 | #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L |
23285 | //SPI_PS_INPUT_CNTL_10 |
23286 | #define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 |
23287 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 |
23288 | #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa |
23289 | #define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd |
23290 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 |
23291 | #define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 |
23292 | #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 |
23293 | #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23294 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23295 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23296 | #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 |
23297 | #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 |
23298 | #define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL |
23299 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L |
23300 | #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L |
23301 | #define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L |
23302 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L |
23303 | #define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L |
23304 | #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L |
23305 | #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23306 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23307 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23308 | #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L |
23309 | #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L |
23310 | //SPI_PS_INPUT_CNTL_11 |
23311 | #define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 |
23312 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 |
23313 | #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa |
23314 | #define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd |
23315 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 |
23316 | #define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 |
23317 | #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 |
23318 | #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23319 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23320 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23321 | #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 |
23322 | #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 |
23323 | #define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL |
23324 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L |
23325 | #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L |
23326 | #define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L |
23327 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L |
23328 | #define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L |
23329 | #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L |
23330 | #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23331 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23332 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23333 | #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L |
23334 | #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L |
23335 | //SPI_PS_INPUT_CNTL_12 |
23336 | #define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 |
23337 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 |
23338 | #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa |
23339 | #define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd |
23340 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 |
23341 | #define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 |
23342 | #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 |
23343 | #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23344 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23345 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23346 | #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 |
23347 | #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 |
23348 | #define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL |
23349 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L |
23350 | #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L |
23351 | #define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L |
23352 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L |
23353 | #define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L |
23354 | #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L |
23355 | #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23356 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23357 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23358 | #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L |
23359 | #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L |
23360 | //SPI_PS_INPUT_CNTL_13 |
23361 | #define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 |
23362 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 |
23363 | #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa |
23364 | #define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd |
23365 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 |
23366 | #define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 |
23367 | #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 |
23368 | #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23369 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23370 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23371 | #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 |
23372 | #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 |
23373 | #define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL |
23374 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L |
23375 | #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L |
23376 | #define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L |
23377 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L |
23378 | #define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L |
23379 | #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L |
23380 | #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23381 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23382 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23383 | #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L |
23384 | #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L |
23385 | //SPI_PS_INPUT_CNTL_14 |
23386 | #define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 |
23387 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 |
23388 | #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa |
23389 | #define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd |
23390 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 |
23391 | #define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 |
23392 | #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 |
23393 | #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23394 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23395 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23396 | #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 |
23397 | #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 |
23398 | #define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL |
23399 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L |
23400 | #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L |
23401 | #define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L |
23402 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L |
23403 | #define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L |
23404 | #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L |
23405 | #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23406 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23407 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23408 | #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L |
23409 | #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L |
23410 | //SPI_PS_INPUT_CNTL_15 |
23411 | #define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 |
23412 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 |
23413 | #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa |
23414 | #define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd |
23415 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 |
23416 | #define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 |
23417 | #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 |
23418 | #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23419 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23420 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23421 | #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 |
23422 | #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 |
23423 | #define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL |
23424 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L |
23425 | #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L |
23426 | #define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L |
23427 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L |
23428 | #define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L |
23429 | #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L |
23430 | #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23431 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23432 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23433 | #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L |
23434 | #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L |
23435 | //SPI_PS_INPUT_CNTL_16 |
23436 | #define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 |
23437 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 |
23438 | #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa |
23439 | #define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd |
23440 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 |
23441 | #define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 |
23442 | #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 |
23443 | #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23444 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23445 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23446 | #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 |
23447 | #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 |
23448 | #define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL |
23449 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L |
23450 | #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L |
23451 | #define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L |
23452 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L |
23453 | #define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L |
23454 | #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L |
23455 | #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23456 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23457 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23458 | #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L |
23459 | #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L |
23460 | //SPI_PS_INPUT_CNTL_17 |
23461 | #define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 |
23462 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 |
23463 | #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa |
23464 | #define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd |
23465 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 |
23466 | #define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 |
23467 | #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 |
23468 | #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23469 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23470 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23471 | #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 |
23472 | #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 |
23473 | #define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL |
23474 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L |
23475 | #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L |
23476 | #define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L |
23477 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L |
23478 | #define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L |
23479 | #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L |
23480 | #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23481 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23482 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23483 | #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L |
23484 | #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L |
23485 | //SPI_PS_INPUT_CNTL_18 |
23486 | #define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 |
23487 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 |
23488 | #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa |
23489 | #define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd |
23490 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 |
23491 | #define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 |
23492 | #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 |
23493 | #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23494 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23495 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23496 | #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 |
23497 | #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 |
23498 | #define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL |
23499 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L |
23500 | #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L |
23501 | #define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L |
23502 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L |
23503 | #define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L |
23504 | #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L |
23505 | #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23506 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23507 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23508 | #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L |
23509 | #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L |
23510 | //SPI_PS_INPUT_CNTL_19 |
23511 | #define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 |
23512 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 |
23513 | #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa |
23514 | #define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd |
23515 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 |
23516 | #define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 |
23517 | #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 |
23518 | #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23519 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23520 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23521 | #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 |
23522 | #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 |
23523 | #define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL |
23524 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L |
23525 | #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L |
23526 | #define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L |
23527 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L |
23528 | #define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L |
23529 | #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L |
23530 | #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23531 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23532 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23533 | #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L |
23534 | #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L |
23535 | //SPI_PS_INPUT_CNTL_20 |
23536 | #define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 |
23537 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 |
23538 | #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa |
23539 | #define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 |
23540 | #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 |
23541 | #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23542 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23543 | #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 |
23544 | #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 |
23545 | #define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL |
23546 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L |
23547 | #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L |
23548 | #define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L |
23549 | #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L |
23550 | #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23551 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23552 | #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L |
23553 | #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L |
23554 | //SPI_PS_INPUT_CNTL_21 |
23555 | #define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 |
23556 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 |
23557 | #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa |
23558 | #define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 |
23559 | #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 |
23560 | #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23561 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23562 | #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 |
23563 | #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 |
23564 | #define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL |
23565 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L |
23566 | #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L |
23567 | #define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L |
23568 | #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L |
23569 | #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23570 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23571 | #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L |
23572 | #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L |
23573 | //SPI_PS_INPUT_CNTL_22 |
23574 | #define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 |
23575 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 |
23576 | #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa |
23577 | #define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 |
23578 | #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 |
23579 | #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23580 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23581 | #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 |
23582 | #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 |
23583 | #define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL |
23584 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L |
23585 | #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L |
23586 | #define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L |
23587 | #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L |
23588 | #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23589 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23590 | #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L |
23591 | #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L |
23592 | //SPI_PS_INPUT_CNTL_23 |
23593 | #define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 |
23594 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 |
23595 | #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa |
23596 | #define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 |
23597 | #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 |
23598 | #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23599 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23600 | #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 |
23601 | #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 |
23602 | #define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL |
23603 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L |
23604 | #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L |
23605 | #define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L |
23606 | #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L |
23607 | #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23608 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23609 | #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L |
23610 | #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L |
23611 | //SPI_PS_INPUT_CNTL_24 |
23612 | #define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 |
23613 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 |
23614 | #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa |
23615 | #define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 |
23616 | #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 |
23617 | #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23618 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23619 | #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 |
23620 | #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 |
23621 | #define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL |
23622 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L |
23623 | #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L |
23624 | #define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L |
23625 | #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L |
23626 | #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23627 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23628 | #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L |
23629 | #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L |
23630 | //SPI_PS_INPUT_CNTL_25 |
23631 | #define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 |
23632 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 |
23633 | #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa |
23634 | #define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 |
23635 | #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 |
23636 | #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23637 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23638 | #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 |
23639 | #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 |
23640 | #define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL |
23641 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L |
23642 | #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L |
23643 | #define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L |
23644 | #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L |
23645 | #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23646 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23647 | #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L |
23648 | #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L |
23649 | //SPI_PS_INPUT_CNTL_26 |
23650 | #define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 |
23651 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 |
23652 | #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa |
23653 | #define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 |
23654 | #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 |
23655 | #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23656 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23657 | #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 |
23658 | #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 |
23659 | #define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL |
23660 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L |
23661 | #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L |
23662 | #define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L |
23663 | #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L |
23664 | #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23665 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23666 | #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L |
23667 | #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L |
23668 | //SPI_PS_INPUT_CNTL_27 |
23669 | #define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 |
23670 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 |
23671 | #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa |
23672 | #define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 |
23673 | #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 |
23674 | #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23675 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23676 | #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 |
23677 | #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 |
23678 | #define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL |
23679 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L |
23680 | #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L |
23681 | #define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L |
23682 | #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L |
23683 | #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23684 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23685 | #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L |
23686 | #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L |
23687 | //SPI_PS_INPUT_CNTL_28 |
23688 | #define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 |
23689 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 |
23690 | #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa |
23691 | #define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 |
23692 | #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 |
23693 | #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23694 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23695 | #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 |
23696 | #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 |
23697 | #define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL |
23698 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L |
23699 | #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L |
23700 | #define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L |
23701 | #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L |
23702 | #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23703 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23704 | #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L |
23705 | #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L |
23706 | //SPI_PS_INPUT_CNTL_29 |
23707 | #define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 |
23708 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 |
23709 | #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa |
23710 | #define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 |
23711 | #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 |
23712 | #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23713 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23714 | #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 |
23715 | #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 |
23716 | #define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL |
23717 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L |
23718 | #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L |
23719 | #define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L |
23720 | #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L |
23721 | #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23722 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23723 | #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L |
23724 | #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L |
23725 | //SPI_PS_INPUT_CNTL_30 |
23726 | #define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 |
23727 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 |
23728 | #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa |
23729 | #define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 |
23730 | #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 |
23731 | #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23732 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23733 | #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 |
23734 | #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 |
23735 | #define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL |
23736 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L |
23737 | #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L |
23738 | #define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L |
23739 | #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L |
23740 | #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23741 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23742 | #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L |
23743 | #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L |
23744 | //SPI_PS_INPUT_CNTL_31 |
23745 | #define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 |
23746 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 |
23747 | #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa |
23748 | #define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 |
23749 | #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 |
23750 | #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23751 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23752 | #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 |
23753 | #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 |
23754 | #define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL |
23755 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L |
23756 | #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L |
23757 | #define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L |
23758 | #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L |
23759 | #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23760 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23761 | #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L |
23762 | #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L |
23763 | //SPI_VS_OUT_CONFIG |
23764 | #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 |
23765 | #define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 |
23766 | #define SPI_VS_OUT_CONFIG__NO_PC_EXPORT__SHIFT 0x7 |
23767 | #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL |
23768 | #define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L |
23769 | #define SPI_VS_OUT_CONFIG__NO_PC_EXPORT_MASK 0x00000080L |
23770 | //SPI_PS_INPUT_ENA |
23771 | #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 |
23772 | #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 |
23773 | #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 |
23774 | #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 |
23775 | #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 |
23776 | #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 |
23777 | #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 |
23778 | #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 |
23779 | #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 |
23780 | #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 |
23781 | #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa |
23782 | #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb |
23783 | #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc |
23784 | #define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd |
23785 | #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe |
23786 | #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf |
23787 | #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L |
23788 | #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L |
23789 | #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L |
23790 | #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L |
23791 | #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L |
23792 | #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L |
23793 | #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L |
23794 | #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L |
23795 | #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L |
23796 | #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L |
23797 | #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L |
23798 | #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L |
23799 | #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L |
23800 | #define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L |
23801 | #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L |
23802 | #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L |
23803 | //SPI_PS_INPUT_ADDR |
23804 | #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 |
23805 | #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 |
23806 | #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 |
23807 | #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 |
23808 | #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 |
23809 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 |
23810 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 |
23811 | #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 |
23812 | #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 |
23813 | #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 |
23814 | #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa |
23815 | #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb |
23816 | #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc |
23817 | #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd |
23818 | #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe |
23819 | #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf |
23820 | #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L |
23821 | #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L |
23822 | #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L |
23823 | #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L |
23824 | #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L |
23825 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L |
23826 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L |
23827 | #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L |
23828 | #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L |
23829 | #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L |
23830 | #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L |
23831 | #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L |
23832 | #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L |
23833 | #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L |
23834 | #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L |
23835 | #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L |
23836 | //SPI_INTERP_CONTROL_0 |
23837 | #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 |
23838 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 |
23839 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 |
23840 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 |
23841 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 |
23842 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb |
23843 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe |
23844 | #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L |
23845 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L |
23846 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL |
23847 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L |
23848 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L |
23849 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L |
23850 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L |
23851 | //SPI_PS_IN_CONTROL |
23852 | #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 |
23853 | #define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 |
23854 | #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7 |
23855 | #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8 |
23856 | #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe |
23857 | #define SPI_PS_IN_CONTROL__PS_W32_EN__SHIFT 0xf |
23858 | #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL |
23859 | #define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L |
23860 | #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L |
23861 | #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L |
23862 | #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L |
23863 | #define SPI_PS_IN_CONTROL__PS_W32_EN_MASK 0x00008000L |
23864 | //SPI_BARYC_CNTL |
23865 | #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 |
23866 | #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 |
23867 | #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 |
23868 | #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc |
23869 | #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 |
23870 | #define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 |
23871 | #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 |
23872 | #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L |
23873 | #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L |
23874 | #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L |
23875 | #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L |
23876 | #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L |
23877 | #define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L |
23878 | #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L |
23879 | //SPI_TMPRING_SIZE |
23880 | #define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 |
23881 | #define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc |
23882 | #define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL |
23883 | #define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L |
23884 | //SPI_SHADER_IDX_FORMAT |
23885 | #define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT__SHIFT 0x0 |
23886 | #define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT_MASK 0x0000000FL |
23887 | //SPI_SHADER_POS_FORMAT |
23888 | #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 |
23889 | #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 |
23890 | #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 |
23891 | #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc |
23892 | #define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT__SHIFT 0x10 |
23893 | #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL |
23894 | #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L |
23895 | #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L |
23896 | #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L |
23897 | #define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT_MASK 0x000F0000L |
23898 | //SPI_SHADER_Z_FORMAT |
23899 | #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 |
23900 | #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL |
23901 | //SPI_SHADER_COL_FORMAT |
23902 | #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 |
23903 | #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 |
23904 | #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 |
23905 | #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc |
23906 | #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 |
23907 | #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 |
23908 | #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 |
23909 | #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c |
23910 | #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL |
23911 | #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L |
23912 | #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L |
23913 | #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L |
23914 | #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L |
23915 | #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L |
23916 | #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L |
23917 | #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L |
23918 | //SX_PS_DOWNCONVERT |
23919 | #define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 |
23920 | #define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 |
23921 | #define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 |
23922 | #define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc |
23923 | #define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 |
23924 | #define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 |
23925 | #define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 |
23926 | #define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c |
23927 | #define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL |
23928 | #define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L |
23929 | #define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L |
23930 | #define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L |
23931 | #define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L |
23932 | #define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L |
23933 | #define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L |
23934 | #define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L |
23935 | //SX_BLEND_OPT_EPSILON |
23936 | #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 |
23937 | #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 |
23938 | #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 |
23939 | #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc |
23940 | #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 |
23941 | #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 |
23942 | #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 |
23943 | #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c |
23944 | #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL |
23945 | #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L |
23946 | #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L |
23947 | #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L |
23948 | #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L |
23949 | #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L |
23950 | #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L |
23951 | #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L |
23952 | //SX_BLEND_OPT_CONTROL |
23953 | #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 |
23954 | #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 |
23955 | #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 |
23956 | #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 |
23957 | #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 |
23958 | #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 |
23959 | #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc |
23960 | #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd |
23961 | #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 |
23962 | #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 |
23963 | #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 |
23964 | #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 |
23965 | #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 |
23966 | #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 |
23967 | #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c |
23968 | #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d |
23969 | #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f |
23970 | #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L |
23971 | #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L |
23972 | #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L |
23973 | #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L |
23974 | #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L |
23975 | #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L |
23976 | #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L |
23977 | #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L |
23978 | #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L |
23979 | #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L |
23980 | #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L |
23981 | #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L |
23982 | #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L |
23983 | #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L |
23984 | #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L |
23985 | #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L |
23986 | #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L |
23987 | //SX_MRT0_BLEND_OPT |
23988 | #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
23989 | #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
23990 | #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
23991 | #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
23992 | #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
23993 | #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
23994 | #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
23995 | #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
23996 | #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
23997 | #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
23998 | #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
23999 | #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24000 | //SX_MRT1_BLEND_OPT |
24001 | #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24002 | #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24003 | #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24004 | #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24005 | #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24006 | #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24007 | #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24008 | #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24009 | #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24010 | #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24011 | #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24012 | #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24013 | //SX_MRT2_BLEND_OPT |
24014 | #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24015 | #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24016 | #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24017 | #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24018 | #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24019 | #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24020 | #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24021 | #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24022 | #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24023 | #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24024 | #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24025 | #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24026 | //SX_MRT3_BLEND_OPT |
24027 | #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24028 | #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24029 | #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24030 | #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24031 | #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24032 | #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24033 | #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24034 | #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24035 | #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24036 | #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24037 | #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24038 | #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24039 | //SX_MRT4_BLEND_OPT |
24040 | #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24041 | #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24042 | #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24043 | #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24044 | #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24045 | #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24046 | #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24047 | #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24048 | #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24049 | #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24050 | #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24051 | #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24052 | //SX_MRT5_BLEND_OPT |
24053 | #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24054 | #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24055 | #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24056 | #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24057 | #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24058 | #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24059 | #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24060 | #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24061 | #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24062 | #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24063 | #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24064 | #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24065 | //SX_MRT6_BLEND_OPT |
24066 | #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24067 | #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24068 | #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24069 | #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24070 | #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24071 | #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24072 | #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24073 | #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24074 | #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24075 | #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24076 | #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24077 | #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24078 | //SX_MRT7_BLEND_OPT |
24079 | #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24080 | #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24081 | #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24082 | #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24083 | #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24084 | #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24085 | #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24086 | #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24087 | #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24088 | #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24089 | #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24090 | #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24091 | //CB_BLEND0_CONTROL |
24092 | #define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24093 | #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24094 | #define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24095 | #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24096 | #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24097 | #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24098 | #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24099 | #define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e |
24100 | #define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24101 | #define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24102 | #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24103 | #define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24104 | #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24105 | #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24106 | #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24107 | #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24108 | #define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L |
24109 | #define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24110 | //CB_BLEND1_CONTROL |
24111 | #define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24112 | #define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24113 | #define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24114 | #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24115 | #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24116 | #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24117 | #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24118 | #define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e |
24119 | #define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24120 | #define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24121 | #define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24122 | #define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24123 | #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24124 | #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24125 | #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24126 | #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24127 | #define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L |
24128 | #define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24129 | //CB_BLEND2_CONTROL |
24130 | #define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24131 | #define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24132 | #define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24133 | #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24134 | #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24135 | #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24136 | #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24137 | #define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e |
24138 | #define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24139 | #define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24140 | #define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24141 | #define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24142 | #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24143 | #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24144 | #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24145 | #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24146 | #define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L |
24147 | #define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24148 | //CB_BLEND3_CONTROL |
24149 | #define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24150 | #define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24151 | #define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24152 | #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24153 | #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24154 | #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24155 | #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24156 | #define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e |
24157 | #define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24158 | #define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24159 | #define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24160 | #define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24161 | #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24162 | #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24163 | #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24164 | #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24165 | #define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L |
24166 | #define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24167 | //CB_BLEND4_CONTROL |
24168 | #define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24169 | #define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24170 | #define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24171 | #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24172 | #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24173 | #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24174 | #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24175 | #define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e |
24176 | #define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24177 | #define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24178 | #define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24179 | #define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24180 | #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24181 | #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24182 | #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24183 | #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24184 | #define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L |
24185 | #define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24186 | //CB_BLEND5_CONTROL |
24187 | #define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24188 | #define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24189 | #define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24190 | #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24191 | #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24192 | #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24193 | #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24194 | #define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e |
24195 | #define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24196 | #define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24197 | #define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24198 | #define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24199 | #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24200 | #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24201 | #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24202 | #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24203 | #define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L |
24204 | #define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24205 | //CB_BLEND6_CONTROL |
24206 | #define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24207 | #define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24208 | #define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24209 | #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24210 | #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24211 | #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24212 | #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24213 | #define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e |
24214 | #define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24215 | #define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24216 | #define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24217 | #define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24218 | #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24219 | #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24220 | #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24221 | #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24222 | #define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L |
24223 | #define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24224 | //CB_BLEND7_CONTROL |
24225 | #define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24226 | #define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24227 | #define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24228 | #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24229 | #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24230 | #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24231 | #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24232 | #define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e |
24233 | #define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24234 | #define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24235 | #define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24236 | #define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24237 | #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24238 | #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24239 | #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24240 | #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24241 | #define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L |
24242 | #define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24243 | //CS_COPY_STATE |
24244 | #define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 |
24245 | #define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L |
24246 | //GFX_COPY_STATE |
24247 | #define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 |
24248 | #define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L |
24249 | //PA_CL_POINT_X_RAD |
24250 | #define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 |
24251 | #define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL |
24252 | //PA_CL_POINT_Y_RAD |
24253 | #define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 |
24254 | #define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL |
24255 | //PA_CL_POINT_SIZE |
24256 | #define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 |
24257 | #define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL |
24258 | //PA_CL_POINT_CULL_RAD |
24259 | #define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 |
24260 | #define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL |
24261 | //VGT_DMA_BASE_HI |
24262 | #define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 |
24263 | #define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL |
24264 | //VGT_DMA_BASE |
24265 | #define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 |
24266 | #define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL |
24267 | //VGT_DRAW_INITIATOR |
24268 | #define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 |
24269 | #define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 |
24270 | #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 |
24271 | #define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 |
24272 | #define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 |
24273 | #define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7 |
24274 | #define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8 |
24275 | #define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d |
24276 | #define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L |
24277 | #define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL |
24278 | #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L |
24279 | #define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L |
24280 | #define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L |
24281 | #define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L |
24282 | #define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L |
24283 | #define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L |
24284 | //VGT_IMMED_DATA |
24285 | #define VGT_IMMED_DATA__DATA__SHIFT 0x0 |
24286 | #define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL |
24287 | //VGT_EVENT_ADDRESS_REG |
24288 | #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 |
24289 | #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL |
24290 | //GE_MAX_OUTPUT_PER_SUBGROUP |
24291 | #define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP__SHIFT 0x0 |
24292 | #define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP_MASK 0x000003FFL |
24293 | //DB_DEPTH_CONTROL |
24294 | #define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 |
24295 | #define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 |
24296 | #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 |
24297 | #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 |
24298 | #define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 |
24299 | #define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 |
24300 | #define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 |
24301 | #define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 |
24302 | #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e |
24303 | #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f |
24304 | #define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L |
24305 | #define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L |
24306 | #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L |
24307 | #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L |
24308 | #define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L |
24309 | #define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L |
24310 | #define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L |
24311 | #define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L |
24312 | #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L |
24313 | #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L |
24314 | //DB_EQAA |
24315 | #define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 |
24316 | #define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 |
24317 | #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 |
24318 | #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc |
24319 | #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 |
24320 | #define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 |
24321 | #define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 |
24322 | #define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 |
24323 | #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 |
24324 | #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 |
24325 | #define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 |
24326 | #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b |
24327 | #define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L |
24328 | #define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L |
24329 | #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L |
24330 | #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L |
24331 | #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L |
24332 | #define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L |
24333 | #define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L |
24334 | #define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L |
24335 | #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L |
24336 | #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L |
24337 | #define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L |
24338 | #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L |
24339 | //CB_COLOR_CONTROL |
24340 | #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 |
24341 | #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 |
24342 | #define CB_COLOR_CONTROL__MODE__SHIFT 0x4 |
24343 | #define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 |
24344 | #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L |
24345 | #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L |
24346 | #define CB_COLOR_CONTROL__MODE_MASK 0x00000070L |
24347 | #define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L |
24348 | //DB_SHADER_CONTROL |
24349 | #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 |
24350 | #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 |
24351 | #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 |
24352 | #define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 |
24353 | #define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 |
24354 | #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 |
24355 | #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 |
24356 | #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 |
24357 | #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa |
24358 | #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb |
24359 | #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc |
24360 | #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd |
24361 | #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf |
24362 | #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10 |
24363 | #define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11 |
24364 | #define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14 |
24365 | #define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE__SHIFT 0x17 |
24366 | #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L |
24367 | #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L |
24368 | #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L |
24369 | #define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L |
24370 | #define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L |
24371 | #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L |
24372 | #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L |
24373 | #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L |
24374 | #define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L |
24375 | #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L |
24376 | #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L |
24377 | #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L |
24378 | #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L |
24379 | #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L |
24380 | #define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L |
24381 | #define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L |
24382 | #define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE_MASK 0x00800000L |
24383 | //PA_CL_CLIP_CNTL |
24384 | #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 |
24385 | #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 |
24386 | #define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 |
24387 | #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 |
24388 | #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 |
24389 | #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 |
24390 | #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd |
24391 | #define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe |
24392 | #define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 |
24393 | #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 |
24394 | #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 |
24395 | #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 |
24396 | #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 |
24397 | #define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 |
24398 | #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 |
24399 | #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 |
24400 | #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 |
24401 | #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a |
24402 | #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b |
24403 | #define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT 0x1c |
24404 | #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L |
24405 | #define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L |
24406 | #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L |
24407 | #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L |
24408 | #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L |
24409 | #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L |
24410 | #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L |
24411 | #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L |
24412 | #define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L |
24413 | #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L |
24414 | #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L |
24415 | #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L |
24416 | #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L |
24417 | #define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L |
24418 | #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L |
24419 | #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L |
24420 | #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L |
24421 | #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L |
24422 | #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L |
24423 | #define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK 0x10000000L |
24424 | //PA_SU_SC_MODE_CNTL |
24425 | #define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 |
24426 | #define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 |
24427 | #define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 |
24428 | #define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 |
24429 | #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 |
24430 | #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 |
24431 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb |
24432 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc |
24433 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd |
24434 | #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 |
24435 | #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 |
24436 | #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 |
24437 | #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 |
24438 | #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16 |
24439 | #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17 |
24440 | #define PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE__SHIFT 0x18 |
24441 | #define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L |
24442 | #define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L |
24443 | #define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L |
24444 | #define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L |
24445 | #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L |
24446 | #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L |
24447 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L |
24448 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L |
24449 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L |
24450 | #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L |
24451 | #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L |
24452 | #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L |
24453 | #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L |
24454 | #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L |
24455 | #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L |
24456 | #define PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE_MASK 0x01000000L |
24457 | //PA_CL_VTE_CNTL |
24458 | #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 |
24459 | #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 |
24460 | #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 |
24461 | #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 |
24462 | #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 |
24463 | #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 |
24464 | #define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 |
24465 | #define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 |
24466 | #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa |
24467 | #define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb |
24468 | #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L |
24469 | #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L |
24470 | #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L |
24471 | #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L |
24472 | #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L |
24473 | #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L |
24474 | #define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L |
24475 | #define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L |
24476 | #define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L |
24477 | #define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L |
24478 | //PA_CL_VS_OUT_CNTL |
24479 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 |
24480 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 |
24481 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 |
24482 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 |
24483 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 |
24484 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 |
24485 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 |
24486 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 |
24487 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 |
24488 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 |
24489 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa |
24490 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb |
24491 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc |
24492 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd |
24493 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe |
24494 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf |
24495 | #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 |
24496 | #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 |
24497 | #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 |
24498 | #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 |
24499 | #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 |
24500 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 |
24501 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 |
24502 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 |
24503 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 |
24504 | #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 |
24505 | #define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1a |
24506 | #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1b |
24507 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L |
24508 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L |
24509 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L |
24510 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L |
24511 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L |
24512 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L |
24513 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L |
24514 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L |
24515 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L |
24516 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L |
24517 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L |
24518 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L |
24519 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L |
24520 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L |
24521 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L |
24522 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L |
24523 | #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L |
24524 | #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L |
24525 | #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L |
24526 | #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L |
24527 | #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L |
24528 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L |
24529 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L |
24530 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L |
24531 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L |
24532 | #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L |
24533 | #define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x04000000L |
24534 | #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x08000000L |
24535 | //PA_CL_NANINF_CNTL |
24536 | #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 |
24537 | #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 |
24538 | #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 |
24539 | #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 |
24540 | #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 |
24541 | #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 |
24542 | #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 |
24543 | #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 |
24544 | #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 |
24545 | #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 |
24546 | #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa |
24547 | #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb |
24548 | #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc |
24549 | #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd |
24550 | #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe |
24551 | #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 |
24552 | #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L |
24553 | #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L |
24554 | #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L |
24555 | #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L |
24556 | #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L |
24557 | #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L |
24558 | #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L |
24559 | #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L |
24560 | #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L |
24561 | #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L |
24562 | #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L |
24563 | #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L |
24564 | #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L |
24565 | #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L |
24566 | #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L |
24567 | #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L |
24568 | //PA_SU_LINE_STIPPLE_CNTL |
24569 | #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 |
24570 | #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 |
24571 | #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 |
24572 | #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 |
24573 | #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L |
24574 | #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L |
24575 | #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L |
24576 | #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L |
24577 | //PA_SU_LINE_STIPPLE_SCALE |
24578 | #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 |
24579 | #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL |
24580 | //PA_SU_PRIM_FILTER_CNTL |
24581 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 |
24582 | #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 |
24583 | #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 |
24584 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 |
24585 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 |
24586 | #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 |
24587 | #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 |
24588 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 |
24589 | #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 |
24590 | #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e |
24591 | #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f |
24592 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L |
24593 | #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L |
24594 | #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L |
24595 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L |
24596 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L |
24597 | #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L |
24598 | #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L |
24599 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L |
24600 | #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L |
24601 | #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L |
24602 | #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L |
24603 | //PA_SU_SMALL_PRIM_FILTER_CNTL |
24604 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0 |
24605 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1 |
24606 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 |
24607 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 |
24608 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 |
24609 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x5 |
24610 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE__SHIFT 0x6 |
24611 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L |
24612 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L |
24613 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L |
24614 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L |
24615 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L |
24616 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L |
24617 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE_MASK 0x00000040L |
24618 | //PA_CL_OBJPRIM_ID_CNTL |
24619 | #define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0 |
24620 | #define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1 |
24621 | #define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L |
24622 | #define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L |
24623 | //PA_CL_NGG_CNTL |
24624 | #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0 |
24625 | #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1 |
24626 | #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L |
24627 | #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L |
24628 | //PA_SU_OVER_RASTERIZATION_CNTL |
24629 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0 |
24630 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1 |
24631 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2 |
24632 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3 |
24633 | #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4 |
24634 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L |
24635 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L |
24636 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L |
24637 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L |
24638 | #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L |
24639 | //PA_STEREO_CNTL |
24640 | #define PA_STEREO_CNTL__STEREO_MODE__SHIFT 0x1 |
24641 | #define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT 0x5 |
24642 | #define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT 0x8 |
24643 | #define PA_STEREO_CNTL__VP_ID_MODE__SHIFT 0x10 |
24644 | #define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT 0x13 |
24645 | #define PA_STEREO_CNTL__STEREO_MODE_MASK 0x0000001EL |
24646 | #define PA_STEREO_CNTL__RT_SLICE_MODE_MASK 0x000000E0L |
24647 | #define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK 0x00000F00L |
24648 | #define PA_STEREO_CNTL__VP_ID_MODE_MASK 0x00070000L |
24649 | #define PA_STEREO_CNTL__VP_ID_OFFSET_MASK 0x00780000L |
24650 | //PA_STATE_STEREO_X |
24651 | #define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT 0x0 |
24652 | #define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK 0xFFFFFFFFL |
24653 | //PA_SU_POINT_SIZE |
24654 | #define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 |
24655 | #define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 |
24656 | #define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL |
24657 | #define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L |
24658 | //PA_SU_POINT_MINMAX |
24659 | #define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 |
24660 | #define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 |
24661 | #define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL |
24662 | #define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L |
24663 | //PA_SU_LINE_CNTL |
24664 | #define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 |
24665 | #define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL |
24666 | //PA_SC_LINE_STIPPLE |
24667 | #define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 |
24668 | #define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 |
24669 | #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c |
24670 | #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d |
24671 | #define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL |
24672 | #define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L |
24673 | #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L |
24674 | #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L |
24675 | //VGT_OUTPUT_PATH_CNTL |
24676 | #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 |
24677 | #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L |
24678 | //VGT_HOS_CNTL |
24679 | #define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 |
24680 | #define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L |
24681 | //VGT_HOS_MAX_TESS_LEVEL |
24682 | #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 |
24683 | #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL |
24684 | //VGT_HOS_MIN_TESS_LEVEL |
24685 | #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 |
24686 | #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL |
24687 | //VGT_HOS_REUSE_DEPTH |
24688 | #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 |
24689 | #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL |
24690 | //VGT_GROUP_PRIM_TYPE |
24691 | #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 |
24692 | #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe |
24693 | #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf |
24694 | #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 |
24695 | #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL |
24696 | #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L |
24697 | #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L |
24698 | #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L |
24699 | //VGT_GROUP_FIRST_DECR |
24700 | #define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 |
24701 | #define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL |
24702 | //VGT_GROUP_DECR |
24703 | #define VGT_GROUP_DECR__DECR__SHIFT 0x0 |
24704 | #define VGT_GROUP_DECR__DECR_MASK 0x0000000FL |
24705 | //VGT_GROUP_VECT_0_CNTL |
24706 | #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 |
24707 | #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 |
24708 | #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 |
24709 | #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 |
24710 | #define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 |
24711 | #define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 |
24712 | #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L |
24713 | #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L |
24714 | #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L |
24715 | #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L |
24716 | #define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L |
24717 | #define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L |
24718 | //VGT_GROUP_VECT_1_CNTL |
24719 | #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 |
24720 | #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 |
24721 | #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 |
24722 | #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 |
24723 | #define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 |
24724 | #define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 |
24725 | #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L |
24726 | #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L |
24727 | #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L |
24728 | #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L |
24729 | #define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L |
24730 | #define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L |
24731 | //VGT_GROUP_VECT_0_FMT_CNTL |
24732 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 |
24733 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 |
24734 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 |
24735 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc |
24736 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 |
24737 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 |
24738 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 |
24739 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c |
24740 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL |
24741 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L |
24742 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L |
24743 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L |
24744 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L |
24745 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L |
24746 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L |
24747 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L |
24748 | //VGT_GROUP_VECT_1_FMT_CNTL |
24749 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 |
24750 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 |
24751 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 |
24752 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc |
24753 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 |
24754 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 |
24755 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 |
24756 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c |
24757 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL |
24758 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L |
24759 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L |
24760 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L |
24761 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L |
24762 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L |
24763 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L |
24764 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L |
24765 | //VGT_GS_MODE |
24766 | #define VGT_GS_MODE__MODE__SHIFT 0x0 |
24767 | #define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 |
24768 | #define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 |
24769 | #define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 |
24770 | #define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb |
24771 | #define VGT_GS_MODE__RESERVED_2__SHIFT 0xc |
24772 | #define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd |
24773 | #define VGT_GS_MODE__COMPUTE_MODE__SHIFT 0xe |
24774 | #define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT 0xf |
24775 | #define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT 0x10 |
24776 | #define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 |
24777 | #define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 |
24778 | #define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 |
24779 | #define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 |
24780 | #define VGT_GS_MODE__ONCHIP__SHIFT 0x15 |
24781 | #define VGT_GS_MODE__MODE_MASK 0x00000007L |
24782 | #define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L |
24783 | #define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L |
24784 | #define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L |
24785 | #define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L |
24786 | #define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L |
24787 | #define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L |
24788 | #define VGT_GS_MODE__COMPUTE_MODE_MASK 0x00004000L |
24789 | #define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK 0x00008000L |
24790 | #define VGT_GS_MODE__ELEMENT_INFO_EN_MASK 0x00010000L |
24791 | #define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L |
24792 | #define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L |
24793 | #define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L |
24794 | #define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L |
24795 | #define VGT_GS_MODE__ONCHIP_MASK 0x00600000L |
24796 | //VGT_GS_ONCHIP_CNTL |
24797 | #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 |
24798 | #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb |
24799 | #define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16 |
24800 | #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL |
24801 | #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L |
24802 | #define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L |
24803 | //PA_SC_MODE_CNTL_0 |
24804 | #define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 |
24805 | #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 |
24806 | #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 |
24807 | #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 |
24808 | #define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4 |
24809 | #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5 |
24810 | #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6 |
24811 | #define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L |
24812 | #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L |
24813 | #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L |
24814 | #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L |
24815 | #define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L |
24816 | #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L |
24817 | #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L |
24818 | //PA_SC_MODE_CNTL_1 |
24819 | #define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 |
24820 | #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 |
24821 | #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 |
24822 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 |
24823 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 |
24824 | #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 |
24825 | #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 |
24826 | #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 |
24827 | #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa |
24828 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb |
24829 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc |
24830 | #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd |
24831 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe |
24832 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf |
24833 | #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 |
24834 | #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 |
24835 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 |
24836 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 |
24837 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 |
24838 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 |
24839 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 |
24840 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a |
24841 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b |
24842 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c |
24843 | #define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L |
24844 | #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L |
24845 | #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L |
24846 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L |
24847 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L |
24848 | #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L |
24849 | #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L |
24850 | #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L |
24851 | #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L |
24852 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L |
24853 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L |
24854 | #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L |
24855 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L |
24856 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L |
24857 | #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L |
24858 | #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L |
24859 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L |
24860 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L |
24861 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L |
24862 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L |
24863 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L |
24864 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L |
24865 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L |
24866 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L |
24867 | //VGT_ENHANCE |
24868 | #define VGT_ENHANCE__MISC__SHIFT 0x0 |
24869 | #define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL |
24870 | //VGT_GS_PER_ES |
24871 | #define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 |
24872 | #define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL |
24873 | //VGT_ES_PER_GS |
24874 | #define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 |
24875 | #define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL |
24876 | //VGT_GS_PER_VS |
24877 | #define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 |
24878 | #define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL |
24879 | //VGT_GSVS_RING_OFFSET_1 |
24880 | #define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 |
24881 | #define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL |
24882 | //VGT_GSVS_RING_OFFSET_2 |
24883 | #define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 |
24884 | #define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL |
24885 | //VGT_GSVS_RING_OFFSET_3 |
24886 | #define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 |
24887 | #define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL |
24888 | //VGT_GS_OUT_PRIM_TYPE |
24889 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 |
24890 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 |
24891 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 |
24892 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 |
24893 | #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f |
24894 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL |
24895 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L |
24896 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L |
24897 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L |
24898 | #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L |
24899 | //IA_ENHANCE |
24900 | #define IA_ENHANCE__MISC__SHIFT 0x0 |
24901 | #define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL |
24902 | //VGT_DMA_SIZE |
24903 | #define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 |
24904 | #define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL |
24905 | //VGT_DMA_MAX_SIZE |
24906 | #define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 |
24907 | #define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL |
24908 | //VGT_DMA_INDEX_TYPE |
24909 | #define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 |
24910 | #define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 |
24911 | #define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 |
24912 | #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 |
24913 | #define VGT_DMA_INDEX_TYPE__ATC__SHIFT 0x8 |
24914 | #define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 |
24915 | #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa |
24916 | #define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb |
24917 | #define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L |
24918 | #define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL |
24919 | #define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L |
24920 | #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x000000C0L |
24921 | #define VGT_DMA_INDEX_TYPE__ATC_MASK 0x00000100L |
24922 | #define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L |
24923 | #define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L |
24924 | #define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x00003800L |
24925 | //WD_ENHANCE |
24926 | #define WD_ENHANCE__MISC__SHIFT 0x0 |
24927 | #define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL |
24928 | //VGT_PRIMITIVEID_EN |
24929 | #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 |
24930 | #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 |
24931 | #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2 |
24932 | #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L |
24933 | #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L |
24934 | #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L |
24935 | //VGT_DMA_NUM_INSTANCES |
24936 | #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 |
24937 | #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL |
24938 | //VGT_PRIMITIVEID_RESET |
24939 | #define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 |
24940 | #define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL |
24941 | //VGT_EVENT_INITIATOR |
24942 | #define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 |
24943 | #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa |
24944 | #define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b |
24945 | #define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL |
24946 | #define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L |
24947 | #define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L |
24948 | //VGT_MULTI_PRIM_IB_RESET_EN |
24949 | #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 |
24950 | #define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 |
24951 | #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L |
24952 | #define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L |
24953 | //VGT_DRAW_PAYLOAD_CNTL |
24954 | #define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0 |
24955 | #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1 |
24956 | #define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x2 |
24957 | #define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD__SHIFT 0x3 |
24958 | #define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP__SHIFT 0x4 |
24959 | #define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L |
24960 | #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L |
24961 | #define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000004L |
24962 | #define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD_MASK 0x00000008L |
24963 | #define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP_MASK 0x00000010L |
24964 | //VGT_INSTANCE_STEP_RATE_0 |
24965 | #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 |
24966 | #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL |
24967 | //VGT_INSTANCE_STEP_RATE_1 |
24968 | #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 |
24969 | #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL |
24970 | //IA_MULTI_VGT_PARAM |
24971 | #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 |
24972 | #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 |
24973 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 |
24974 | #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 |
24975 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 |
24976 | #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 |
24977 | #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL |
24978 | #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L |
24979 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L |
24980 | #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L |
24981 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L |
24982 | #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L |
24983 | //VGT_ESGS_RING_ITEMSIZE |
24984 | #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 |
24985 | #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL |
24986 | //VGT_GSVS_RING_ITEMSIZE |
24987 | #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 |
24988 | #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL |
24989 | //VGT_REUSE_OFF |
24990 | #define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 |
24991 | #define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L |
24992 | //VGT_VTX_CNT_EN |
24993 | #define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 |
24994 | #define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L |
24995 | //DB_HTILE_SURFACE |
24996 | #define DB_HTILE_SURFACE__RESERVED_FIELD_1__SHIFT 0x0 |
24997 | #define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 |
24998 | #define DB_HTILE_SURFACE__RESERVED_FIELD_2__SHIFT 0x2 |
24999 | #define DB_HTILE_SURFACE__RESERVED_FIELD_3__SHIFT 0x3 |
25000 | #define DB_HTILE_SURFACE__RESERVED_FIELD_4__SHIFT 0x4 |
25001 | #define DB_HTILE_SURFACE__RESERVED_FIELD_5__SHIFT 0xa |
25002 | #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 |
25003 | #define DB_HTILE_SURFACE__RESERVED_FIELD_6__SHIFT 0x11 |
25004 | #define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12 |
25005 | #define DB_HTILE_SURFACE__RESERVED_FIELD_1_MASK 0x00000001L |
25006 | #define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L |
25007 | #define DB_HTILE_SURFACE__RESERVED_FIELD_2_MASK 0x00000004L |
25008 | #define DB_HTILE_SURFACE__RESERVED_FIELD_3_MASK 0x00000008L |
25009 | #define DB_HTILE_SURFACE__RESERVED_FIELD_4_MASK 0x000003F0L |
25010 | #define DB_HTILE_SURFACE__RESERVED_FIELD_5_MASK 0x0000FC00L |
25011 | #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L |
25012 | #define DB_HTILE_SURFACE__RESERVED_FIELD_6_MASK 0x00020000L |
25013 | #define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L |
25014 | //DB_SRESULTS_COMPARE_STATE0 |
25015 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 |
25016 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 |
25017 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc |
25018 | #define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 |
25019 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L |
25020 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L |
25021 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L |
25022 | #define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L |
25023 | //DB_SRESULTS_COMPARE_STATE1 |
25024 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 |
25025 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 |
25026 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc |
25027 | #define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 |
25028 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L |
25029 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L |
25030 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L |
25031 | #define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L |
25032 | //DB_PRELOAD_CONTROL |
25033 | #define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 |
25034 | #define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 |
25035 | #define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 |
25036 | #define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 |
25037 | #define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL |
25038 | #define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L |
25039 | #define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L |
25040 | #define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L |
25041 | //VGT_STRMOUT_BUFFER_SIZE_0 |
25042 | #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 |
25043 | #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL |
25044 | //VGT_STRMOUT_VTX_STRIDE_0 |
25045 | #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 |
25046 | #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL |
25047 | //VGT_STRMOUT_BUFFER_OFFSET_0 |
25048 | #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 |
25049 | #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL |
25050 | //VGT_STRMOUT_BUFFER_SIZE_1 |
25051 | #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 |
25052 | #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL |
25053 | //VGT_STRMOUT_VTX_STRIDE_1 |
25054 | #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 |
25055 | #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL |
25056 | //VGT_STRMOUT_BUFFER_OFFSET_1 |
25057 | #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 |
25058 | #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL |
25059 | //VGT_STRMOUT_BUFFER_SIZE_2 |
25060 | #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 |
25061 | #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL |
25062 | //VGT_STRMOUT_VTX_STRIDE_2 |
25063 | #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 |
25064 | #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL |
25065 | //VGT_STRMOUT_BUFFER_OFFSET_2 |
25066 | #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 |
25067 | #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL |
25068 | //VGT_STRMOUT_BUFFER_SIZE_3 |
25069 | #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 |
25070 | #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL |
25071 | //VGT_STRMOUT_VTX_STRIDE_3 |
25072 | #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 |
25073 | #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL |
25074 | //VGT_STRMOUT_BUFFER_OFFSET_3 |
25075 | #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 |
25076 | #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL |
25077 | //VGT_STRMOUT_DRAW_OPAQUE_OFFSET |
25078 | #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 |
25079 | #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL |
25080 | //VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE |
25081 | #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 |
25082 | #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL |
25083 | //VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE |
25084 | #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 |
25085 | #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL |
25086 | //VGT_GS_MAX_VERT_OUT |
25087 | #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 |
25088 | #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL |
25089 | //GE_NGG_SUBGRP_CNTL |
25090 | #define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR__SHIFT 0x0 |
25091 | #define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP__SHIFT 0x9 |
25092 | #define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR_MASK 0x000001FFL |
25093 | #define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP_MASK 0x0003FE00L |
25094 | //VGT_TESS_DISTRIBUTION |
25095 | #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 |
25096 | #define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 |
25097 | #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 |
25098 | #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 |
25099 | #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d |
25100 | #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL |
25101 | #define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L |
25102 | #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L |
25103 | #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L |
25104 | #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L |
25105 | //VGT_SHADER_STAGES_EN |
25106 | #define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 |
25107 | #define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 |
25108 | #define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 |
25109 | #define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 |
25110 | #define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 |
25111 | #define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8 |
25112 | #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9 |
25113 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa |
25114 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb |
25115 | #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc |
25116 | #define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd |
25117 | #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe |
25118 | #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf |
25119 | #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13 |
25120 | #define VGT_SHADER_STAGES_EN__HS_W32_EN__SHIFT 0x15 |
25121 | #define VGT_SHADER_STAGES_EN__GS_W32_EN__SHIFT 0x16 |
25122 | #define VGT_SHADER_STAGES_EN__VS_W32_EN__SHIFT 0x17 |
25123 | #define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN__SHIFT 0x18 |
25124 | #define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN__SHIFT 0x19 |
25125 | #define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L |
25126 | #define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L |
25127 | #define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L |
25128 | #define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L |
25129 | #define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L |
25130 | #define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x00000100L |
25131 | #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L |
25132 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L |
25133 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L |
25134 | #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L |
25135 | #define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L |
25136 | #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L |
25137 | #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L |
25138 | #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00180000L |
25139 | #define VGT_SHADER_STAGES_EN__HS_W32_EN_MASK 0x00200000L |
25140 | #define VGT_SHADER_STAGES_EN__GS_W32_EN_MASK 0x00400000L |
25141 | #define VGT_SHADER_STAGES_EN__VS_W32_EN_MASK 0x00800000L |
25142 | #define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN_MASK 0x01000000L |
25143 | #define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN_MASK 0x02000000L |
25144 | //VGT_LS_HS_CONFIG |
25145 | #define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 |
25146 | #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 |
25147 | #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe |
25148 | #define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL |
25149 | #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L |
25150 | #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L |
25151 | //VGT_GS_VERT_ITEMSIZE |
25152 | #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 |
25153 | #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL |
25154 | //VGT_GS_VERT_ITEMSIZE_1 |
25155 | #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 |
25156 | #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL |
25157 | //VGT_GS_VERT_ITEMSIZE_2 |
25158 | #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 |
25159 | #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL |
25160 | //VGT_GS_VERT_ITEMSIZE_3 |
25161 | #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 |
25162 | #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL |
25163 | //VGT_TF_PARAM |
25164 | #define VGT_TF_PARAM__TYPE__SHIFT 0x0 |
25165 | #define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 |
25166 | #define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 |
25167 | #define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 |
25168 | #define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 |
25169 | #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa |
25170 | #define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe |
25171 | #define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf |
25172 | #define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 |
25173 | #define VGT_TF_PARAM__DETECT_ONE__SHIFT 0x13 |
25174 | #define VGT_TF_PARAM__DETECT_ZERO__SHIFT 0x14 |
25175 | #define VGT_TF_PARAM__MTYPE__SHIFT 0x17 |
25176 | #define VGT_TF_PARAM__TYPE_MASK 0x00000003L |
25177 | #define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL |
25178 | #define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L |
25179 | #define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L |
25180 | #define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L |
25181 | #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x00003C00L |
25182 | #define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L |
25183 | #define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00018000L |
25184 | #define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L |
25185 | #define VGT_TF_PARAM__DETECT_ONE_MASK 0x00080000L |
25186 | #define VGT_TF_PARAM__DETECT_ZERO_MASK 0x00100000L |
25187 | #define VGT_TF_PARAM__MTYPE_MASK 0x03800000L |
25188 | //DB_ALPHA_TO_MASK |
25189 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 |
25190 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 |
25191 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa |
25192 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc |
25193 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe |
25194 | #define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 |
25195 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L |
25196 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L |
25197 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L |
25198 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L |
25199 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L |
25200 | #define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L |
25201 | //VGT_DISPATCH_DRAW_INDEX |
25202 | #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 |
25203 | #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL |
25204 | //PA_SU_POLY_OFFSET_DB_FMT_CNTL |
25205 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 |
25206 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 |
25207 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL |
25208 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L |
25209 | //PA_SU_POLY_OFFSET_CLAMP |
25210 | #define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 |
25211 | #define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL |
25212 | //PA_SU_POLY_OFFSET_FRONT_SCALE |
25213 | #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 |
25214 | #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL |
25215 | //PA_SU_POLY_OFFSET_FRONT_OFFSET |
25216 | #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 |
25217 | #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL |
25218 | //PA_SU_POLY_OFFSET_BACK_SCALE |
25219 | #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 |
25220 | #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL |
25221 | //PA_SU_POLY_OFFSET_BACK_OFFSET |
25222 | #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 |
25223 | #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL |
25224 | //VGT_GS_INSTANCE_CNT |
25225 | #define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 |
25226 | #define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 |
25227 | #define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE__SHIFT 0x1f |
25228 | #define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L |
25229 | #define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL |
25230 | #define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE_MASK 0x80000000L |
25231 | //VGT_STRMOUT_CONFIG |
25232 | #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 |
25233 | #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 |
25234 | #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 |
25235 | #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 |
25236 | #define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 |
25237 | #define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7 |
25238 | #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 |
25239 | #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f |
25240 | #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L |
25241 | #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L |
25242 | #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L |
25243 | #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L |
25244 | #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L |
25245 | #define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L |
25246 | #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L |
25247 | #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L |
25248 | //VGT_STRMOUT_BUFFER_CONFIG |
25249 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 |
25250 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 |
25251 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 |
25252 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc |
25253 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL |
25254 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L |
25255 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L |
25256 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L |
25257 | //VGT_DMA_EVENT_INITIATOR |
25258 | #define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 |
25259 | #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa |
25260 | #define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b |
25261 | #define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL |
25262 | #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L |
25263 | #define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L |
25264 | //PA_SC_CENTROID_PRIORITY_0 |
25265 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 |
25266 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 |
25267 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 |
25268 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc |
25269 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 |
25270 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 |
25271 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 |
25272 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c |
25273 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL |
25274 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L |
25275 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L |
25276 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L |
25277 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L |
25278 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L |
25279 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L |
25280 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L |
25281 | //PA_SC_CENTROID_PRIORITY_1 |
25282 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 |
25283 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 |
25284 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 |
25285 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc |
25286 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 |
25287 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 |
25288 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 |
25289 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c |
25290 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL |
25291 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L |
25292 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L |
25293 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L |
25294 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L |
25295 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L |
25296 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L |
25297 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L |
25298 | //PA_SC_LINE_CNTL |
25299 | #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 |
25300 | #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa |
25301 | #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb |
25302 | #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc |
25303 | #define 0xd |
25304 | #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L |
25305 | #define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L |
25306 | #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L |
25307 | #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L |
25308 | #define 0x00002000L |
25309 | //PA_SC_AA_CONFIG |
25310 | #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 |
25311 | #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 |
25312 | #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd |
25313 | #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 |
25314 | #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 |
25315 | #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a |
25316 | #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L |
25317 | #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L |
25318 | #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L |
25319 | #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L |
25320 | #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L |
25321 | #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L |
25322 | //PA_SU_VTX_CNTL |
25323 | #define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 |
25324 | #define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 |
25325 | #define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 |
25326 | #define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L |
25327 | #define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L |
25328 | #define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L |
25329 | //PA_CL_GB_VERT_CLIP_ADJ |
25330 | #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 |
25331 | #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
25332 | //PA_CL_GB_VERT_DISC_ADJ |
25333 | #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 |
25334 | #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
25335 | //PA_CL_GB_HORZ_CLIP_ADJ |
25336 | #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 |
25337 | #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
25338 | //PA_CL_GB_HORZ_DISC_ADJ |
25339 | #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 |
25340 | #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
25341 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 |
25342 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 |
25343 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 |
25344 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 |
25345 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc |
25346 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 |
25347 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 |
25348 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 |
25349 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c |
25350 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL |
25351 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L |
25352 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L |
25353 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L |
25354 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L |
25355 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L |
25356 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L |
25357 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L |
25358 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 |
25359 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 |
25360 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 |
25361 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 |
25362 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc |
25363 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 |
25364 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 |
25365 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 |
25366 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c |
25367 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL |
25368 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L |
25369 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L |
25370 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L |
25371 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L |
25372 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L |
25373 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L |
25374 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L |
25375 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 |
25376 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 |
25377 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 |
25378 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 |
25379 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc |
25380 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 |
25381 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 |
25382 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 |
25383 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c |
25384 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL |
25385 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L |
25386 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L |
25387 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L |
25388 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L |
25389 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L |
25390 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L |
25391 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L |
25392 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 |
25393 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 |
25394 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 |
25395 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 |
25396 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc |
25397 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 |
25398 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 |
25399 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 |
25400 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c |
25401 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL |
25402 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L |
25403 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L |
25404 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L |
25405 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L |
25406 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L |
25407 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L |
25408 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L |
25409 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 |
25410 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 |
25411 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 |
25412 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 |
25413 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc |
25414 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 |
25415 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 |
25416 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 |
25417 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c |
25418 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL |
25419 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L |
25420 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L |
25421 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L |
25422 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L |
25423 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L |
25424 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L |
25425 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L |
25426 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 |
25427 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 |
25428 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 |
25429 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 |
25430 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc |
25431 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 |
25432 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 |
25433 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 |
25434 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c |
25435 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL |
25436 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L |
25437 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L |
25438 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L |
25439 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L |
25440 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L |
25441 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L |
25442 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L |
25443 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 |
25444 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 |
25445 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 |
25446 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 |
25447 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc |
25448 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 |
25449 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 |
25450 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 |
25451 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c |
25452 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL |
25453 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L |
25454 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L |
25455 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L |
25456 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L |
25457 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L |
25458 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L |
25459 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L |
25460 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 |
25461 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 |
25462 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 |
25463 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 |
25464 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc |
25465 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 |
25466 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 |
25467 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 |
25468 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c |
25469 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL |
25470 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L |
25471 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L |
25472 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L |
25473 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L |
25474 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L |
25475 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L |
25476 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L |
25477 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 |
25478 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 |
25479 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 |
25480 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 |
25481 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc |
25482 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 |
25483 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 |
25484 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 |
25485 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c |
25486 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL |
25487 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L |
25488 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L |
25489 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L |
25490 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L |
25491 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L |
25492 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L |
25493 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L |
25494 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 |
25495 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 |
25496 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 |
25497 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 |
25498 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc |
25499 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 |
25500 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 |
25501 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 |
25502 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c |
25503 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL |
25504 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L |
25505 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L |
25506 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L |
25507 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L |
25508 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L |
25509 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L |
25510 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L |
25511 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 |
25512 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 |
25513 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 |
25514 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 |
25515 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc |
25516 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 |
25517 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 |
25518 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 |
25519 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c |
25520 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL |
25521 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L |
25522 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L |
25523 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L |
25524 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L |
25525 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L |
25526 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L |
25527 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L |
25528 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 |
25529 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 |
25530 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 |
25531 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 |
25532 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc |
25533 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 |
25534 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 |
25535 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 |
25536 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c |
25537 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL |
25538 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L |
25539 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L |
25540 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L |
25541 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L |
25542 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L |
25543 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L |
25544 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L |
25545 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 |
25546 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 |
25547 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 |
25548 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 |
25549 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc |
25550 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 |
25551 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 |
25552 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 |
25553 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c |
25554 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL |
25555 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L |
25556 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L |
25557 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L |
25558 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L |
25559 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L |
25560 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L |
25561 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L |
25562 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 |
25563 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 |
25564 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 |
25565 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 |
25566 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc |
25567 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 |
25568 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 |
25569 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 |
25570 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c |
25571 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL |
25572 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L |
25573 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L |
25574 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L |
25575 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L |
25576 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L |
25577 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L |
25578 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L |
25579 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 |
25580 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 |
25581 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 |
25582 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 |
25583 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc |
25584 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 |
25585 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 |
25586 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 |
25587 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c |
25588 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL |
25589 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L |
25590 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L |
25591 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L |
25592 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L |
25593 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L |
25594 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L |
25595 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L |
25596 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 |
25597 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 |
25598 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 |
25599 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 |
25600 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc |
25601 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 |
25602 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 |
25603 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 |
25604 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c |
25605 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL |
25606 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L |
25607 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L |
25608 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L |
25609 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L |
25610 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L |
25611 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L |
25612 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L |
25613 | //PA_SC_AA_MASK_X0Y0_X1Y0 |
25614 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 |
25615 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 |
25616 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL |
25617 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L |
25618 | //PA_SC_AA_MASK_X0Y1_X1Y1 |
25619 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 |
25620 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 |
25621 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL |
25622 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L |
25623 | //PA_SC_SHADER_CONTROL |
25624 | #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 |
25625 | #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2 |
25626 | #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3 |
25627 | #define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE__SHIFT 0x5 |
25628 | #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L |
25629 | #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L |
25630 | #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L |
25631 | #define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE_MASK 0x00000060L |
25632 | //PA_SC_BINNER_CNTL_0 |
25633 | #define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0 |
25634 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2 |
25635 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3 |
25636 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4 |
25637 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7 |
25638 | #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa |
25639 | #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd |
25640 | #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12 |
25641 | #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13 |
25642 | #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b |
25643 | #define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1c |
25644 | #define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE__SHIFT 0x1d |
25645 | #define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L |
25646 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L |
25647 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L |
25648 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L |
25649 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L |
25650 | #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L |
25651 | #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L |
25652 | #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L |
25653 | #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L |
25654 | #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L |
25655 | #define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK 0x10000000L |
25656 | #define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE_MASK 0x60000000L |
25657 | //PA_SC_BINNER_CNTL_1 |
25658 | #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0 |
25659 | #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10 |
25660 | #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL |
25661 | #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L |
25662 | //PA_SC_CONSERVATIVE_RASTERIZATION_CNTL |
25663 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0 |
25664 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1 |
25665 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5 |
25666 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6 |
25667 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa |
25668 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb |
25669 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc |
25670 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd |
25671 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe |
25672 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf |
25673 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10 |
25674 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12 |
25675 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13 |
25676 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14 |
25677 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15 |
25678 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16 |
25679 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17 |
25680 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18 |
25681 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT__SHIFT 0x19 |
25682 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT__SHIFT 0x1b |
25683 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L |
25684 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL |
25685 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L |
25686 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L |
25687 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L |
25688 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L |
25689 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L |
25690 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L |
25691 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L |
25692 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L |
25693 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L |
25694 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L |
25695 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L |
25696 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L |
25697 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L |
25698 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L |
25699 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L |
25700 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L |
25701 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT_MASK 0x06000000L |
25702 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT_MASK 0x18000000L |
25703 | //PA_SC_NGG_MODE_CNTL |
25704 | #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 |
25705 | #define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE__SHIFT 0x10 |
25706 | #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL |
25707 | #define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE_MASK 0x00FF0000L |
25708 | //VGT_VERTEX_REUSE_BLOCK_CNTL |
25709 | #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 |
25710 | #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL |
25711 | //VGT_OUT_DEALLOC_CNTL |
25712 | #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 |
25713 | #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL |
25714 | //CB_COLOR0_BASE |
25715 | #define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 |
25716 | #define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25717 | //CB_COLOR0_PITCH |
25718 | #define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0 |
25719 | #define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
25720 | #define CB_COLOR0_PITCH__TILE_MAX_MASK 0x000007FFL |
25721 | #define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
25722 | //CB_COLOR0_SLICE |
25723 | #define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0 |
25724 | #define CB_COLOR0_SLICE__TILE_MAX_MASK 0x003FFFFFL |
25725 | //CB_COLOR0_VIEW |
25726 | #define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 |
25727 | #define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd |
25728 | #define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x1a |
25729 | #define CB_COLOR0_VIEW__SLICE_START_MASK 0x00001FFFL |
25730 | #define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x03FFE000L |
25731 | #define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x3C000000L |
25732 | //CB_COLOR0_INFO |
25733 | #define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 |
25734 | #define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 |
25735 | #define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7 |
25736 | #define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 |
25737 | #define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb |
25738 | #define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd |
25739 | #define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe |
25740 | #define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf |
25741 | #define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 |
25742 | #define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
25743 | #define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 |
25744 | #define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
25745 | #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
25746 | #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
25747 | #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
25748 | #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
25749 | #define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c |
25750 | #define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
25751 | #define CB_COLOR0_INFO__ALT_TILE_MODE__SHIFT 0x1f |
25752 | #define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L |
25753 | #define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL |
25754 | #define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x00000080L |
25755 | #define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L |
25756 | #define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L |
25757 | #define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L |
25758 | #define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L |
25759 | #define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L |
25760 | #define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L |
25761 | #define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
25762 | #define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L |
25763 | #define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
25764 | #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
25765 | #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
25766 | #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
25767 | #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
25768 | #define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L |
25769 | #define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
25770 | #define CB_COLOR0_INFO__ALT_TILE_MODE_MASK 0x80000000L |
25771 | //CB_COLOR0_ATTRIB |
25772 | #define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
25773 | #define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
25774 | #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
25775 | #define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
25776 | #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
25777 | #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
25778 | #define CB_COLOR0_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
25779 | #define CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
25780 | #define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
25781 | #define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
25782 | #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
25783 | #define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
25784 | #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
25785 | #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
25786 | #define CB_COLOR0_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
25787 | #define CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
25788 | //CB_COLOR0_DCC_CONTROL |
25789 | #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
25790 | #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
25791 | #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
25792 | #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
25793 | #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
25794 | #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
25795 | #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
25796 | #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
25797 | #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
25798 | #define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
25799 | #define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
25800 | #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
25801 | #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
25802 | #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
25803 | #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
25804 | #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
25805 | #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
25806 | #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
25807 | #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
25808 | #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
25809 | #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
25810 | #define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
25811 | #define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
25812 | #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
25813 | //CB_COLOR0_CMASK |
25814 | #define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 |
25815 | #define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
25816 | //CB_COLOR0_CMASK_SLICE |
25817 | #define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
25818 | #define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
25819 | //CB_COLOR0_FMASK |
25820 | #define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 |
25821 | #define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
25822 | //CB_COLOR0_FMASK_SLICE |
25823 | #define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
25824 | #define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
25825 | //CB_COLOR0_CLEAR_WORD0 |
25826 | #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
25827 | #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
25828 | //CB_COLOR0_CLEAR_WORD1 |
25829 | #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
25830 | #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
25831 | //CB_COLOR0_DCC_BASE |
25832 | #define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 |
25833 | #define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25834 | //CB_COLOR1_BASE |
25835 | #define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 |
25836 | #define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25837 | //CB_COLOR1_PITCH |
25838 | #define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0 |
25839 | #define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
25840 | #define CB_COLOR1_PITCH__TILE_MAX_MASK 0x000007FFL |
25841 | #define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
25842 | //CB_COLOR1_SLICE |
25843 | #define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0 |
25844 | #define CB_COLOR1_SLICE__TILE_MAX_MASK 0x003FFFFFL |
25845 | //CB_COLOR1_VIEW |
25846 | #define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 |
25847 | #define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd |
25848 | #define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x1a |
25849 | #define CB_COLOR1_VIEW__SLICE_START_MASK 0x00001FFFL |
25850 | #define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x03FFE000L |
25851 | #define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x3C000000L |
25852 | //CB_COLOR1_INFO |
25853 | #define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 |
25854 | #define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 |
25855 | #define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7 |
25856 | #define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 |
25857 | #define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb |
25858 | #define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd |
25859 | #define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe |
25860 | #define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf |
25861 | #define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 |
25862 | #define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
25863 | #define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 |
25864 | #define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
25865 | #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
25866 | #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
25867 | #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
25868 | #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
25869 | #define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c |
25870 | #define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
25871 | #define CB_COLOR1_INFO__ALT_TILE_MODE__SHIFT 0x1f |
25872 | #define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L |
25873 | #define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL |
25874 | #define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x00000080L |
25875 | #define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L |
25876 | #define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L |
25877 | #define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L |
25878 | #define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L |
25879 | #define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L |
25880 | #define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L |
25881 | #define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
25882 | #define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L |
25883 | #define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
25884 | #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
25885 | #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
25886 | #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
25887 | #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
25888 | #define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L |
25889 | #define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
25890 | #define CB_COLOR1_INFO__ALT_TILE_MODE_MASK 0x80000000L |
25891 | //CB_COLOR1_ATTRIB |
25892 | #define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
25893 | #define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
25894 | #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
25895 | #define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
25896 | #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
25897 | #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
25898 | #define CB_COLOR1_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
25899 | #define CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
25900 | #define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
25901 | #define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
25902 | #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
25903 | #define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
25904 | #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
25905 | #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
25906 | #define CB_COLOR1_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
25907 | #define CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
25908 | //CB_COLOR1_DCC_CONTROL |
25909 | #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
25910 | #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
25911 | #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
25912 | #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
25913 | #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
25914 | #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
25915 | #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
25916 | #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
25917 | #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
25918 | #define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
25919 | #define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
25920 | #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
25921 | #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
25922 | #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
25923 | #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
25924 | #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
25925 | #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
25926 | #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
25927 | #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
25928 | #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
25929 | #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
25930 | #define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
25931 | #define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
25932 | #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
25933 | //CB_COLOR1_CMASK |
25934 | #define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 |
25935 | #define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
25936 | //CB_COLOR1_CMASK_SLICE |
25937 | #define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
25938 | #define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
25939 | //CB_COLOR1_FMASK |
25940 | #define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 |
25941 | #define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
25942 | //CB_COLOR1_FMASK_SLICE |
25943 | #define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
25944 | #define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
25945 | //CB_COLOR1_CLEAR_WORD0 |
25946 | #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
25947 | #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
25948 | //CB_COLOR1_CLEAR_WORD1 |
25949 | #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
25950 | #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
25951 | //CB_COLOR1_DCC_BASE |
25952 | #define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 |
25953 | #define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25954 | //CB_COLOR2_BASE |
25955 | #define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 |
25956 | #define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25957 | //CB_COLOR2_PITCH |
25958 | #define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0 |
25959 | #define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
25960 | #define CB_COLOR2_PITCH__TILE_MAX_MASK 0x000007FFL |
25961 | #define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
25962 | //CB_COLOR2_SLICE |
25963 | #define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0 |
25964 | #define CB_COLOR2_SLICE__TILE_MAX_MASK 0x003FFFFFL |
25965 | //CB_COLOR2_VIEW |
25966 | #define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 |
25967 | #define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd |
25968 | #define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x1a |
25969 | #define CB_COLOR2_VIEW__SLICE_START_MASK 0x00001FFFL |
25970 | #define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x03FFE000L |
25971 | #define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x3C000000L |
25972 | //CB_COLOR2_INFO |
25973 | #define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 |
25974 | #define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 |
25975 | #define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7 |
25976 | #define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 |
25977 | #define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb |
25978 | #define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd |
25979 | #define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe |
25980 | #define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf |
25981 | #define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 |
25982 | #define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
25983 | #define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 |
25984 | #define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
25985 | #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
25986 | #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
25987 | #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
25988 | #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
25989 | #define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c |
25990 | #define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
25991 | #define CB_COLOR2_INFO__ALT_TILE_MODE__SHIFT 0x1f |
25992 | #define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L |
25993 | #define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL |
25994 | #define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x00000080L |
25995 | #define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L |
25996 | #define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L |
25997 | #define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L |
25998 | #define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L |
25999 | #define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L |
26000 | #define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L |
26001 | #define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
26002 | #define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L |
26003 | #define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
26004 | #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
26005 | #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
26006 | #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
26007 | #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
26008 | #define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L |
26009 | #define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
26010 | #define CB_COLOR2_INFO__ALT_TILE_MODE_MASK 0x80000000L |
26011 | //CB_COLOR2_ATTRIB |
26012 | #define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
26013 | #define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
26014 | #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
26015 | #define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
26016 | #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
26017 | #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
26018 | #define CB_COLOR2_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
26019 | #define CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
26020 | #define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
26021 | #define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
26022 | #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
26023 | #define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
26024 | #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
26025 | #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
26026 | #define CB_COLOR2_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
26027 | #define CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
26028 | //CB_COLOR2_DCC_CONTROL |
26029 | #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
26030 | #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
26031 | #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
26032 | #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
26033 | #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
26034 | #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
26035 | #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
26036 | #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
26037 | #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
26038 | #define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
26039 | #define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
26040 | #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
26041 | #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
26042 | #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
26043 | #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
26044 | #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
26045 | #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
26046 | #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
26047 | #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
26048 | #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
26049 | #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
26050 | #define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
26051 | #define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
26052 | #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
26053 | //CB_COLOR2_CMASK |
26054 | #define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 |
26055 | #define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
26056 | //CB_COLOR2_CMASK_SLICE |
26057 | #define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
26058 | #define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
26059 | //CB_COLOR2_FMASK |
26060 | #define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 |
26061 | #define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
26062 | //CB_COLOR2_FMASK_SLICE |
26063 | #define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
26064 | #define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
26065 | //CB_COLOR2_CLEAR_WORD0 |
26066 | #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
26067 | #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
26068 | //CB_COLOR2_CLEAR_WORD1 |
26069 | #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
26070 | #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
26071 | //CB_COLOR2_DCC_BASE |
26072 | #define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 |
26073 | #define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
26074 | //CB_COLOR3_BASE |
26075 | #define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 |
26076 | #define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL |
26077 | //CB_COLOR3_PITCH |
26078 | #define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0 |
26079 | #define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
26080 | #define CB_COLOR3_PITCH__TILE_MAX_MASK 0x000007FFL |
26081 | #define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
26082 | //CB_COLOR3_SLICE |
26083 | #define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0 |
26084 | #define CB_COLOR3_SLICE__TILE_MAX_MASK 0x003FFFFFL |
26085 | //CB_COLOR3_VIEW |
26086 | #define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 |
26087 | #define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd |
26088 | #define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x1a |
26089 | #define CB_COLOR3_VIEW__SLICE_START_MASK 0x00001FFFL |
26090 | #define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x03FFE000L |
26091 | #define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x3C000000L |
26092 | //CB_COLOR3_INFO |
26093 | #define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 |
26094 | #define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 |
26095 | #define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7 |
26096 | #define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 |
26097 | #define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb |
26098 | #define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd |
26099 | #define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe |
26100 | #define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf |
26101 | #define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 |
26102 | #define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
26103 | #define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 |
26104 | #define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
26105 | #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
26106 | #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
26107 | #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
26108 | #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
26109 | #define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c |
26110 | #define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
26111 | #define CB_COLOR3_INFO__ALT_TILE_MODE__SHIFT 0x1f |
26112 | #define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L |
26113 | #define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL |
26114 | #define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x00000080L |
26115 | #define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L |
26116 | #define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L |
26117 | #define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L |
26118 | #define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L |
26119 | #define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L |
26120 | #define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L |
26121 | #define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
26122 | #define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L |
26123 | #define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
26124 | #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
26125 | #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
26126 | #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
26127 | #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
26128 | #define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L |
26129 | #define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
26130 | #define CB_COLOR3_INFO__ALT_TILE_MODE_MASK 0x80000000L |
26131 | //CB_COLOR3_ATTRIB |
26132 | #define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
26133 | #define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
26134 | #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
26135 | #define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
26136 | #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
26137 | #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
26138 | #define CB_COLOR3_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
26139 | #define CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
26140 | #define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
26141 | #define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
26142 | #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
26143 | #define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
26144 | #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
26145 | #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
26146 | #define CB_COLOR3_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
26147 | #define CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
26148 | //CB_COLOR3_DCC_CONTROL |
26149 | #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
26150 | #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
26151 | #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
26152 | #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
26153 | #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
26154 | #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
26155 | #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
26156 | #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
26157 | #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
26158 | #define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
26159 | #define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
26160 | #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
26161 | #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
26162 | #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
26163 | #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
26164 | #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
26165 | #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
26166 | #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
26167 | #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
26168 | #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
26169 | #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
26170 | #define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
26171 | #define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
26172 | #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
26173 | //CB_COLOR3_CMASK |
26174 | #define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 |
26175 | #define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
26176 | //CB_COLOR3_CMASK_SLICE |
26177 | #define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
26178 | #define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
26179 | //CB_COLOR3_FMASK |
26180 | #define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 |
26181 | #define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
26182 | //CB_COLOR3_FMASK_SLICE |
26183 | #define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
26184 | #define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
26185 | //CB_COLOR3_CLEAR_WORD0 |
26186 | #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
26187 | #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
26188 | //CB_COLOR3_CLEAR_WORD1 |
26189 | #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
26190 | #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
26191 | //CB_COLOR3_DCC_BASE |
26192 | #define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 |
26193 | #define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
26194 | //CB_COLOR4_BASE |
26195 | #define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 |
26196 | #define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL |
26197 | //CB_COLOR4_PITCH |
26198 | #define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0 |
26199 | #define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
26200 | #define CB_COLOR4_PITCH__TILE_MAX_MASK 0x000007FFL |
26201 | #define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
26202 | //CB_COLOR4_SLICE |
26203 | #define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0 |
26204 | #define CB_COLOR4_SLICE__TILE_MAX_MASK 0x003FFFFFL |
26205 | //CB_COLOR4_VIEW |
26206 | #define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 |
26207 | #define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd |
26208 | #define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x1a |
26209 | #define CB_COLOR4_VIEW__SLICE_START_MASK 0x00001FFFL |
26210 | #define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x03FFE000L |
26211 | #define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x3C000000L |
26212 | //CB_COLOR4_INFO |
26213 | #define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 |
26214 | #define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 |
26215 | #define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7 |
26216 | #define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 |
26217 | #define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb |
26218 | #define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd |
26219 | #define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe |
26220 | #define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf |
26221 | #define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 |
26222 | #define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
26223 | #define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 |
26224 | #define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
26225 | #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
26226 | #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
26227 | #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
26228 | #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
26229 | #define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c |
26230 | #define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
26231 | #define CB_COLOR4_INFO__ALT_TILE_MODE__SHIFT 0x1f |
26232 | #define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L |
26233 | #define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL |
26234 | #define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x00000080L |
26235 | #define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L |
26236 | #define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L |
26237 | #define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L |
26238 | #define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L |
26239 | #define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L |
26240 | #define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L |
26241 | #define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
26242 | #define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L |
26243 | #define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
26244 | #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
26245 | #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
26246 | #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
26247 | #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
26248 | #define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L |
26249 | #define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
26250 | #define CB_COLOR4_INFO__ALT_TILE_MODE_MASK 0x80000000L |
26251 | //CB_COLOR4_ATTRIB |
26252 | #define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
26253 | #define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
26254 | #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
26255 | #define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
26256 | #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
26257 | #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
26258 | #define CB_COLOR4_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
26259 | #define CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
26260 | #define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
26261 | #define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
26262 | #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
26263 | #define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
26264 | #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
26265 | #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
26266 | #define CB_COLOR4_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
26267 | #define CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
26268 | //CB_COLOR4_DCC_CONTROL |
26269 | #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
26270 | #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
26271 | #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
26272 | #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
26273 | #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
26274 | #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
26275 | #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
26276 | #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
26277 | #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
26278 | #define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
26279 | #define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
26280 | #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
26281 | #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
26282 | #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
26283 | #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
26284 | #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
26285 | #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
26286 | #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
26287 | #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
26288 | #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
26289 | #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
26290 | #define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
26291 | #define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
26292 | #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
26293 | //CB_COLOR4_CMASK |
26294 | #define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 |
26295 | #define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
26296 | //CB_COLOR4_CMASK_SLICE |
26297 | #define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
26298 | #define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
26299 | //CB_COLOR4_FMASK |
26300 | #define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 |
26301 | #define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
26302 | //CB_COLOR4_FMASK_SLICE |
26303 | #define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
26304 | #define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
26305 | //CB_COLOR4_CLEAR_WORD0 |
26306 | #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
26307 | #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
26308 | //CB_COLOR4_CLEAR_WORD1 |
26309 | #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
26310 | #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
26311 | //CB_COLOR4_DCC_BASE |
26312 | #define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 |
26313 | #define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
26314 | //CB_COLOR5_BASE |
26315 | #define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 |
26316 | #define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL |
26317 | //CB_COLOR5_PITCH |
26318 | #define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0 |
26319 | #define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
26320 | #define CB_COLOR5_PITCH__TILE_MAX_MASK 0x000007FFL |
26321 | #define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
26322 | //CB_COLOR5_SLICE |
26323 | #define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0 |
26324 | #define CB_COLOR5_SLICE__TILE_MAX_MASK 0x003FFFFFL |
26325 | //CB_COLOR5_VIEW |
26326 | #define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 |
26327 | #define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd |
26328 | #define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x1a |
26329 | #define CB_COLOR5_VIEW__SLICE_START_MASK 0x00001FFFL |
26330 | #define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x03FFE000L |
26331 | #define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x3C000000L |
26332 | //CB_COLOR5_INFO |
26333 | #define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 |
26334 | #define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 |
26335 | #define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7 |
26336 | #define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 |
26337 | #define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb |
26338 | #define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd |
26339 | #define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe |
26340 | #define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf |
26341 | #define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 |
26342 | #define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
26343 | #define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 |
26344 | #define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
26345 | #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
26346 | #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
26347 | #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
26348 | #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
26349 | #define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c |
26350 | #define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
26351 | #define CB_COLOR5_INFO__ALT_TILE_MODE__SHIFT 0x1f |
26352 | #define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L |
26353 | #define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL |
26354 | #define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x00000080L |
26355 | #define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L |
26356 | #define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L |
26357 | #define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L |
26358 | #define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L |
26359 | #define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L |
26360 | #define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L |
26361 | #define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
26362 | #define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L |
26363 | #define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
26364 | #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
26365 | #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
26366 | #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
26367 | #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
26368 | #define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L |
26369 | #define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
26370 | #define CB_COLOR5_INFO__ALT_TILE_MODE_MASK 0x80000000L |
26371 | //CB_COLOR5_ATTRIB |
26372 | #define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
26373 | #define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
26374 | #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
26375 | #define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
26376 | #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
26377 | #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
26378 | #define CB_COLOR5_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
26379 | #define CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
26380 | #define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
26381 | #define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
26382 | #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
26383 | #define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
26384 | #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
26385 | #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
26386 | #define CB_COLOR5_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
26387 | #define CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
26388 | //CB_COLOR5_DCC_CONTROL |
26389 | #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
26390 | #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
26391 | #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
26392 | #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
26393 | #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
26394 | #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
26395 | #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
26396 | #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
26397 | #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
26398 | #define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
26399 | #define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
26400 | #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
26401 | #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
26402 | #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
26403 | #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
26404 | #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
26405 | #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
26406 | #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
26407 | #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
26408 | #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
26409 | #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
26410 | #define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
26411 | #define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
26412 | #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
26413 | //CB_COLOR5_CMASK |
26414 | #define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 |
26415 | #define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
26416 | //CB_COLOR5_CMASK_SLICE |
26417 | #define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
26418 | #define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
26419 | //CB_COLOR5_FMASK |
26420 | #define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 |
26421 | #define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
26422 | //CB_COLOR5_FMASK_SLICE |
26423 | #define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
26424 | #define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
26425 | //CB_COLOR5_CLEAR_WORD0 |
26426 | #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
26427 | #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
26428 | //CB_COLOR5_CLEAR_WORD1 |
26429 | #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
26430 | #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
26431 | //CB_COLOR5_DCC_BASE |
26432 | #define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 |
26433 | #define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
26434 | //CB_COLOR6_BASE |
26435 | #define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 |
26436 | #define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL |
26437 | //CB_COLOR6_PITCH |
26438 | #define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0 |
26439 | #define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
26440 | #define CB_COLOR6_PITCH__TILE_MAX_MASK 0x000007FFL |
26441 | #define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
26442 | //CB_COLOR6_SLICE |
26443 | #define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0 |
26444 | #define CB_COLOR6_SLICE__TILE_MAX_MASK 0x003FFFFFL |
26445 | //CB_COLOR6_VIEW |
26446 | #define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 |
26447 | #define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd |
26448 | #define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x1a |
26449 | #define CB_COLOR6_VIEW__SLICE_START_MASK 0x00001FFFL |
26450 | #define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x03FFE000L |
26451 | #define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x3C000000L |
26452 | //CB_COLOR6_INFO |
26453 | #define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 |
26454 | #define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 |
26455 | #define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7 |
26456 | #define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 |
26457 | #define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb |
26458 | #define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd |
26459 | #define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe |
26460 | #define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf |
26461 | #define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 |
26462 | #define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
26463 | #define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 |
26464 | #define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
26465 | #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
26466 | #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
26467 | #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
26468 | #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
26469 | #define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c |
26470 | #define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
26471 | #define CB_COLOR6_INFO__ALT_TILE_MODE__SHIFT 0x1f |
26472 | #define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L |
26473 | #define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL |
26474 | #define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x00000080L |
26475 | #define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L |
26476 | #define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L |
26477 | #define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L |
26478 | #define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L |
26479 | #define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L |
26480 | #define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L |
26481 | #define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
26482 | #define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L |
26483 | #define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
26484 | #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
26485 | #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
26486 | #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
26487 | #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
26488 | #define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L |
26489 | #define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
26490 | #define CB_COLOR6_INFO__ALT_TILE_MODE_MASK 0x80000000L |
26491 | //CB_COLOR6_ATTRIB |
26492 | #define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
26493 | #define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
26494 | #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
26495 | #define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
26496 | #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
26497 | #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
26498 | #define CB_COLOR6_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
26499 | #define CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
26500 | #define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
26501 | #define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
26502 | #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
26503 | #define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
26504 | #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
26505 | #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
26506 | #define CB_COLOR6_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
26507 | #define CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
26508 | //CB_COLOR6_DCC_CONTROL |
26509 | #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
26510 | #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
26511 | #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
26512 | #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
26513 | #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
26514 | #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
26515 | #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
26516 | #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
26517 | #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
26518 | #define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
26519 | #define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
26520 | #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
26521 | #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
26522 | #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
26523 | #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
26524 | #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
26525 | #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
26526 | #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
26527 | #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
26528 | #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
26529 | #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
26530 | #define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
26531 | #define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
26532 | #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
26533 | //CB_COLOR6_CMASK |
26534 | #define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 |
26535 | #define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
26536 | //CB_COLOR6_CMASK_SLICE |
26537 | #define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
26538 | #define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
26539 | //CB_COLOR6_FMASK |
26540 | #define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 |
26541 | #define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
26542 | //CB_COLOR6_FMASK_SLICE |
26543 | #define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
26544 | #define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
26545 | //CB_COLOR6_CLEAR_WORD0 |
26546 | #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
26547 | #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
26548 | //CB_COLOR6_CLEAR_WORD1 |
26549 | #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
26550 | #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
26551 | //CB_COLOR6_DCC_BASE |
26552 | #define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 |
26553 | #define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
26554 | //CB_COLOR7_BASE |
26555 | #define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 |
26556 | #define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL |
26557 | //CB_COLOR7_PITCH |
26558 | #define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0 |
26559 | #define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
26560 | #define CB_COLOR7_PITCH__TILE_MAX_MASK 0x000007FFL |
26561 | #define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
26562 | //CB_COLOR7_SLICE |
26563 | #define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0 |
26564 | #define CB_COLOR7_SLICE__TILE_MAX_MASK 0x003FFFFFL |
26565 | //CB_COLOR7_VIEW |
26566 | #define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 |
26567 | #define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd |
26568 | #define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x1a |
26569 | #define CB_COLOR7_VIEW__SLICE_START_MASK 0x00001FFFL |
26570 | #define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x03FFE000L |
26571 | #define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x3C000000L |
26572 | //CB_COLOR7_INFO |
26573 | #define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 |
26574 | #define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 |
26575 | #define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7 |
26576 | #define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 |
26577 | #define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb |
26578 | #define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd |
26579 | #define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe |
26580 | #define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf |
26581 | #define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 |
26582 | #define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
26583 | #define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 |
26584 | #define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
26585 | #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
26586 | #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
26587 | #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
26588 | #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
26589 | #define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c |
26590 | #define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
26591 | #define CB_COLOR7_INFO__ALT_TILE_MODE__SHIFT 0x1f |
26592 | #define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L |
26593 | #define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL |
26594 | #define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x00000080L |
26595 | #define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L |
26596 | #define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L |
26597 | #define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L |
26598 | #define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L |
26599 | #define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L |
26600 | #define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L |
26601 | #define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
26602 | #define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L |
26603 | #define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
26604 | #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
26605 | #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
26606 | #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
26607 | #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
26608 | #define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L |
26609 | #define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
26610 | #define CB_COLOR7_INFO__ALT_TILE_MODE_MASK 0x80000000L |
26611 | //CB_COLOR7_ATTRIB |
26612 | #define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
26613 | #define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
26614 | #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
26615 | #define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
26616 | #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
26617 | #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
26618 | #define CB_COLOR7_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
26619 | #define CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
26620 | #define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
26621 | #define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
26622 | #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
26623 | #define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
26624 | #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
26625 | #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
26626 | #define CB_COLOR7_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
26627 | #define CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
26628 | //CB_COLOR7_DCC_CONTROL |
26629 | #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
26630 | #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
26631 | #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
26632 | #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
26633 | #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
26634 | #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
26635 | #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
26636 | #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
26637 | #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
26638 | #define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
26639 | #define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
26640 | #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
26641 | #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
26642 | #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
26643 | #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
26644 | #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
26645 | #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
26646 | #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
26647 | #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
26648 | #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
26649 | #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
26650 | #define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
26651 | #define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
26652 | #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
26653 | //CB_COLOR7_CMASK |
26654 | #define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 |
26655 | #define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
26656 | //CB_COLOR7_CMASK_SLICE |
26657 | #define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
26658 | #define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
26659 | //CB_COLOR7_FMASK |
26660 | #define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 |
26661 | #define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
26662 | //CB_COLOR7_FMASK_SLICE |
26663 | #define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
26664 | #define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
26665 | //CB_COLOR7_CLEAR_WORD0 |
26666 | #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
26667 | #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
26668 | //CB_COLOR7_CLEAR_WORD1 |
26669 | #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
26670 | #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
26671 | //CB_COLOR7_DCC_BASE |
26672 | #define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 |
26673 | #define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
26674 | //CB_COLOR0_BASE_EXT |
26675 | #define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0 |
26676 | #define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26677 | //CB_COLOR1_BASE_EXT |
26678 | #define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0 |
26679 | #define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26680 | //CB_COLOR2_BASE_EXT |
26681 | #define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0 |
26682 | #define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26683 | //CB_COLOR3_BASE_EXT |
26684 | #define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0 |
26685 | #define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26686 | //CB_COLOR4_BASE_EXT |
26687 | #define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0 |
26688 | #define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26689 | //CB_COLOR5_BASE_EXT |
26690 | #define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0 |
26691 | #define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26692 | //CB_COLOR6_BASE_EXT |
26693 | #define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0 |
26694 | #define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26695 | //CB_COLOR7_BASE_EXT |
26696 | #define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0 |
26697 | #define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26698 | //CB_COLOR0_CMASK_BASE_EXT |
26699 | #define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26700 | #define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26701 | //CB_COLOR1_CMASK_BASE_EXT |
26702 | #define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26703 | #define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26704 | //CB_COLOR2_CMASK_BASE_EXT |
26705 | #define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26706 | #define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26707 | //CB_COLOR3_CMASK_BASE_EXT |
26708 | #define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26709 | #define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26710 | //CB_COLOR4_CMASK_BASE_EXT |
26711 | #define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26712 | #define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26713 | //CB_COLOR5_CMASK_BASE_EXT |
26714 | #define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26715 | #define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26716 | //CB_COLOR6_CMASK_BASE_EXT |
26717 | #define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26718 | #define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26719 | //CB_COLOR7_CMASK_BASE_EXT |
26720 | #define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26721 | #define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26722 | //CB_COLOR0_FMASK_BASE_EXT |
26723 | #define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26724 | #define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26725 | //CB_COLOR1_FMASK_BASE_EXT |
26726 | #define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26727 | #define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26728 | //CB_COLOR2_FMASK_BASE_EXT |
26729 | #define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26730 | #define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26731 | //CB_COLOR3_FMASK_BASE_EXT |
26732 | #define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26733 | #define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26734 | //CB_COLOR4_FMASK_BASE_EXT |
26735 | #define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26736 | #define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26737 | //CB_COLOR5_FMASK_BASE_EXT |
26738 | #define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26739 | #define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26740 | //CB_COLOR6_FMASK_BASE_EXT |
26741 | #define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26742 | #define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26743 | //CB_COLOR7_FMASK_BASE_EXT |
26744 | #define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
26745 | #define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26746 | //CB_COLOR0_DCC_BASE_EXT |
26747 | #define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26748 | #define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26749 | //CB_COLOR1_DCC_BASE_EXT |
26750 | #define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26751 | #define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26752 | //CB_COLOR2_DCC_BASE_EXT |
26753 | #define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26754 | #define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26755 | //CB_COLOR3_DCC_BASE_EXT |
26756 | #define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26757 | #define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26758 | //CB_COLOR4_DCC_BASE_EXT |
26759 | #define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26760 | #define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26761 | //CB_COLOR5_DCC_BASE_EXT |
26762 | #define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26763 | #define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26764 | //CB_COLOR6_DCC_BASE_EXT |
26765 | #define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26766 | #define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26767 | //CB_COLOR7_DCC_BASE_EXT |
26768 | #define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26769 | #define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26770 | //CB_COLOR0_ATTRIB2 |
26771 | #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26772 | #define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26773 | #define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26774 | #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26775 | #define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26776 | #define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26777 | //CB_COLOR1_ATTRIB2 |
26778 | #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26779 | #define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26780 | #define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26781 | #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26782 | #define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26783 | #define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26784 | //CB_COLOR2_ATTRIB2 |
26785 | #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26786 | #define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26787 | #define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26788 | #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26789 | #define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26790 | #define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26791 | //CB_COLOR3_ATTRIB2 |
26792 | #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26793 | #define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26794 | #define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26795 | #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26796 | #define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26797 | #define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26798 | //CB_COLOR4_ATTRIB2 |
26799 | #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26800 | #define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26801 | #define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26802 | #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26803 | #define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26804 | #define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26805 | //CB_COLOR5_ATTRIB2 |
26806 | #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26807 | #define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26808 | #define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26809 | #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26810 | #define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26811 | #define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26812 | //CB_COLOR6_ATTRIB2 |
26813 | #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26814 | #define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26815 | #define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26816 | #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26817 | #define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26818 | #define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26819 | //CB_COLOR7_ATTRIB2 |
26820 | #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26821 | #define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26822 | #define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26823 | #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26824 | #define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26825 | #define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26826 | //CB_COLOR0_ATTRIB3 |
26827 | #define CB_COLOR0_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26828 | #define CB_COLOR0_ATTRIB3__META_LINEAR__SHIFT 0xd |
26829 | #define CB_COLOR0_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26830 | #define CB_COLOR0_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
26831 | #define CB_COLOR0_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26832 | #define CB_COLOR0_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
26833 | #define CB_COLOR0_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
26834 | #define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26835 | #define CB_COLOR0_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26836 | #define CB_COLOR0_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26837 | #define CB_COLOR0_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26838 | #define CB_COLOR0_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
26839 | #define CB_COLOR0_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26840 | #define CB_COLOR0_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
26841 | #define CB_COLOR0_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
26842 | #define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26843 | //CB_COLOR1_ATTRIB3 |
26844 | #define CB_COLOR1_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26845 | #define CB_COLOR1_ATTRIB3__META_LINEAR__SHIFT 0xd |
26846 | #define CB_COLOR1_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26847 | #define CB_COLOR1_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
26848 | #define CB_COLOR1_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26849 | #define CB_COLOR1_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
26850 | #define CB_COLOR1_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
26851 | #define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26852 | #define CB_COLOR1_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26853 | #define CB_COLOR1_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26854 | #define CB_COLOR1_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26855 | #define CB_COLOR1_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
26856 | #define CB_COLOR1_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26857 | #define CB_COLOR1_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
26858 | #define CB_COLOR1_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
26859 | #define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26860 | //CB_COLOR2_ATTRIB3 |
26861 | #define CB_COLOR2_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26862 | #define CB_COLOR2_ATTRIB3__META_LINEAR__SHIFT 0xd |
26863 | #define CB_COLOR2_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26864 | #define CB_COLOR2_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
26865 | #define CB_COLOR2_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26866 | #define CB_COLOR2_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
26867 | #define CB_COLOR2_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
26868 | #define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26869 | #define CB_COLOR2_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26870 | #define CB_COLOR2_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26871 | #define CB_COLOR2_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26872 | #define CB_COLOR2_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
26873 | #define CB_COLOR2_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26874 | #define CB_COLOR2_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
26875 | #define CB_COLOR2_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
26876 | #define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26877 | //CB_COLOR3_ATTRIB3 |
26878 | #define CB_COLOR3_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26879 | #define CB_COLOR3_ATTRIB3__META_LINEAR__SHIFT 0xd |
26880 | #define CB_COLOR3_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26881 | #define CB_COLOR3_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
26882 | #define CB_COLOR3_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26883 | #define CB_COLOR3_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
26884 | #define CB_COLOR3_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
26885 | #define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26886 | #define CB_COLOR3_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26887 | #define CB_COLOR3_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26888 | #define CB_COLOR3_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26889 | #define CB_COLOR3_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
26890 | #define CB_COLOR3_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26891 | #define CB_COLOR3_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
26892 | #define CB_COLOR3_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
26893 | #define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26894 | //CB_COLOR4_ATTRIB3 |
26895 | #define CB_COLOR4_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26896 | #define CB_COLOR4_ATTRIB3__META_LINEAR__SHIFT 0xd |
26897 | #define CB_COLOR4_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26898 | #define CB_COLOR4_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
26899 | #define CB_COLOR4_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26900 | #define CB_COLOR4_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
26901 | #define CB_COLOR4_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
26902 | #define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26903 | #define CB_COLOR4_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26904 | #define CB_COLOR4_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26905 | #define CB_COLOR4_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26906 | #define CB_COLOR4_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
26907 | #define CB_COLOR4_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26908 | #define CB_COLOR4_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
26909 | #define CB_COLOR4_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
26910 | #define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26911 | //CB_COLOR5_ATTRIB3 |
26912 | #define CB_COLOR5_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26913 | #define CB_COLOR5_ATTRIB3__META_LINEAR__SHIFT 0xd |
26914 | #define CB_COLOR5_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26915 | #define CB_COLOR5_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
26916 | #define CB_COLOR5_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26917 | #define CB_COLOR5_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
26918 | #define CB_COLOR5_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
26919 | #define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26920 | #define CB_COLOR5_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26921 | #define CB_COLOR5_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26922 | #define CB_COLOR5_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26923 | #define CB_COLOR5_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
26924 | #define CB_COLOR5_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26925 | #define CB_COLOR5_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
26926 | #define CB_COLOR5_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
26927 | #define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26928 | //CB_COLOR6_ATTRIB3 |
26929 | #define CB_COLOR6_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26930 | #define CB_COLOR6_ATTRIB3__META_LINEAR__SHIFT 0xd |
26931 | #define CB_COLOR6_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26932 | #define CB_COLOR6_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
26933 | #define CB_COLOR6_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26934 | #define CB_COLOR6_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
26935 | #define CB_COLOR6_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
26936 | #define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26937 | #define CB_COLOR6_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26938 | #define CB_COLOR6_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26939 | #define CB_COLOR6_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26940 | #define CB_COLOR6_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
26941 | #define CB_COLOR6_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26942 | #define CB_COLOR6_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
26943 | #define CB_COLOR6_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
26944 | #define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26945 | //CB_COLOR7_ATTRIB3 |
26946 | #define CB_COLOR7_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26947 | #define CB_COLOR7_ATTRIB3__META_LINEAR__SHIFT 0xd |
26948 | #define CB_COLOR7_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26949 | #define CB_COLOR7_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
26950 | #define CB_COLOR7_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26951 | #define CB_COLOR7_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
26952 | #define CB_COLOR7_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
26953 | #define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26954 | #define CB_COLOR7_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26955 | #define CB_COLOR7_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26956 | #define CB_COLOR7_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26957 | #define CB_COLOR7_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
26958 | #define CB_COLOR7_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26959 | #define CB_COLOR7_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
26960 | #define CB_COLOR7_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
26961 | #define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26962 | |
26963 | |
26964 | // addressBlock: gc_gfxudec |
26965 | //CP_EOP_DONE_ADDR_LO |
26966 | #define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 |
26967 | #define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
26968 | //CP_EOP_DONE_ADDR_HI |
26969 | #define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
26970 | #define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
26971 | //CP_EOP_DONE_DATA_LO |
26972 | #define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 |
26973 | #define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL |
26974 | //CP_EOP_DONE_DATA_HI |
26975 | #define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 |
26976 | #define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL |
26977 | //CP_EOP_LAST_FENCE_LO |
26978 | #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 |
26979 | #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL |
26980 | //CP_EOP_LAST_FENCE_HI |
26981 | #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 |
26982 | #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL |
26983 | //CP_STREAM_OUT_ADDR_LO |
26984 | #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 |
26985 | #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL |
26986 | //CP_STREAM_OUT_ADDR_HI |
26987 | #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 |
26988 | #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL |
26989 | //CP_NUM_PRIM_WRITTEN_COUNT0_LO |
26990 | #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 |
26991 | #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL |
26992 | //CP_NUM_PRIM_WRITTEN_COUNT0_HI |
26993 | #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 |
26994 | #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL |
26995 | //CP_NUM_PRIM_NEEDED_COUNT0_LO |
26996 | #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 |
26997 | #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL |
26998 | //CP_NUM_PRIM_NEEDED_COUNT0_HI |
26999 | #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 |
27000 | #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL |
27001 | //CP_NUM_PRIM_WRITTEN_COUNT1_LO |
27002 | #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 |
27003 | #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL |
27004 | //CP_NUM_PRIM_WRITTEN_COUNT1_HI |
27005 | #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 |
27006 | #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL |
27007 | //CP_NUM_PRIM_NEEDED_COUNT1_LO |
27008 | #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 |
27009 | #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL |
27010 | //CP_NUM_PRIM_NEEDED_COUNT1_HI |
27011 | #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 |
27012 | #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL |
27013 | //CP_NUM_PRIM_WRITTEN_COUNT2_LO |
27014 | #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 |
27015 | #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL |
27016 | //CP_NUM_PRIM_WRITTEN_COUNT2_HI |
27017 | #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 |
27018 | #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL |
27019 | //CP_NUM_PRIM_NEEDED_COUNT2_LO |
27020 | #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 |
27021 | #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL |
27022 | //CP_NUM_PRIM_NEEDED_COUNT2_HI |
27023 | #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 |
27024 | #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL |
27025 | //CP_NUM_PRIM_WRITTEN_COUNT3_LO |
27026 | #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 |
27027 | #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL |
27028 | //CP_NUM_PRIM_WRITTEN_COUNT3_HI |
27029 | #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 |
27030 | #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL |
27031 | //CP_NUM_PRIM_NEEDED_COUNT3_LO |
27032 | #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 |
27033 | #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL |
27034 | //CP_NUM_PRIM_NEEDED_COUNT3_HI |
27035 | #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 |
27036 | #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL |
27037 | //CP_PIPE_STATS_ADDR_LO |
27038 | #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 |
27039 | #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL |
27040 | //CP_PIPE_STATS_ADDR_HI |
27041 | #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 |
27042 | #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL |
27043 | //CP_VGT_IAVERT_COUNT_LO |
27044 | #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 |
27045 | #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL |
27046 | //CP_VGT_IAVERT_COUNT_HI |
27047 | #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 |
27048 | #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL |
27049 | //CP_VGT_IAPRIM_COUNT_LO |
27050 | #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 |
27051 | #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL |
27052 | //CP_VGT_IAPRIM_COUNT_HI |
27053 | #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 |
27054 | #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL |
27055 | //CP_VGT_GSPRIM_COUNT_LO |
27056 | #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 |
27057 | #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL |
27058 | //CP_VGT_GSPRIM_COUNT_HI |
27059 | #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 |
27060 | #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL |
27061 | //CP_VGT_VSINVOC_COUNT_LO |
27062 | #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 |
27063 | #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
27064 | //CP_VGT_VSINVOC_COUNT_HI |
27065 | #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 |
27066 | #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
27067 | //CP_VGT_GSINVOC_COUNT_LO |
27068 | #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 |
27069 | #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
27070 | //CP_VGT_GSINVOC_COUNT_HI |
27071 | #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 |
27072 | #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
27073 | //CP_VGT_HSINVOC_COUNT_LO |
27074 | #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 |
27075 | #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
27076 | //CP_VGT_HSINVOC_COUNT_HI |
27077 | #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 |
27078 | #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
27079 | //CP_VGT_DSINVOC_COUNT_LO |
27080 | #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 |
27081 | #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
27082 | //CP_VGT_DSINVOC_COUNT_HI |
27083 | #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 |
27084 | #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
27085 | //CP_PA_CINVOC_COUNT_LO |
27086 | #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 |
27087 | #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
27088 | //CP_PA_CINVOC_COUNT_HI |
27089 | #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 |
27090 | #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
27091 | //CP_PA_CPRIM_COUNT_LO |
27092 | #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 |
27093 | #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL |
27094 | //CP_PA_CPRIM_COUNT_HI |
27095 | #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 |
27096 | #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL |
27097 | //CP_SC_PSINVOC_COUNT0_LO |
27098 | #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 |
27099 | #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL |
27100 | //CP_SC_PSINVOC_COUNT0_HI |
27101 | #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 |
27102 | #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL |
27103 | //CP_SC_PSINVOC_COUNT1_LO |
27104 | #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 |
27105 | #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL |
27106 | //CP_SC_PSINVOC_COUNT1_HI |
27107 | #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 |
27108 | #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL |
27109 | //CP_VGT_CSINVOC_COUNT_LO |
27110 | #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 |
27111 | #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
27112 | //CP_VGT_CSINVOC_COUNT_HI |
27113 | #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 |
27114 | #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
27115 | //CP_EOP_DONE_DOORBELL |
27116 | #define CP_EOP_DONE_DOORBELL__DOORBELL_OFFSET__SHIFT 0x2 |
27117 | #define CP_EOP_DONE_DOORBELL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
27118 | //CP_STREAM_OUT_DOORBELL |
27119 | #define CP_STREAM_OUT_DOORBELL__DOORBELL_OFFSET__SHIFT 0x2 |
27120 | #define CP_STREAM_OUT_DOORBELL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
27121 | //CP_SEM_DOORBELL |
27122 | #define CP_SEM_DOORBELL__DOORBELL_OFFSET__SHIFT 0x2 |
27123 | #define CP_SEM_DOORBELL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
27124 | //CP_PIPE_STATS_CONTROL |
27125 | #define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19 |
27126 | #define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x06000000L |
27127 | //CP_STREAM_OUT_CONTROL |
27128 | #define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19 |
27129 | #define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x06000000L |
27130 | //CP_STRMOUT_CNTL |
27131 | #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 |
27132 | #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L |
27133 | //SCRATCH_REG0 |
27134 | #define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 |
27135 | #define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL |
27136 | //SCRATCH_REG1 |
27137 | #define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 |
27138 | #define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL |
27139 | //SCRATCH_REG2 |
27140 | #define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 |
27141 | #define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL |
27142 | //SCRATCH_REG3 |
27143 | #define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 |
27144 | #define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL |
27145 | //SCRATCH_REG4 |
27146 | #define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 |
27147 | #define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL |
27148 | //SCRATCH_REG5 |
27149 | #define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 |
27150 | #define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL |
27151 | //SCRATCH_REG6 |
27152 | #define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 |
27153 | #define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL |
27154 | //SCRATCH_REG7 |
27155 | #define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 |
27156 | #define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL |
27157 | //CP_PIPE_STATS_DOORBELL |
27158 | #define CP_PIPE_STATS_DOORBELL__DOORBELL_OFFSET__SHIFT 0x2 |
27159 | #define CP_PIPE_STATS_DOORBELL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
27160 | //CP_APPEND_DDID_CNT |
27161 | #define CP_APPEND_DDID_CNT__DATA__SHIFT 0x0 |
27162 | #define CP_APPEND_DDID_CNT__DATA_MASK 0x000000FFL |
27163 | //CP_APPEND_DATA_HI |
27164 | #define CP_APPEND_DATA_HI__DATA__SHIFT 0x0 |
27165 | #define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL |
27166 | //CP_APPEND_LAST_CS_FENCE_HI |
27167 | #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0 |
27168 | #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL |
27169 | //CP_APPEND_LAST_PS_FENCE_HI |
27170 | #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0 |
27171 | #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL |
27172 | //SCRATCH_UMSK |
27173 | #define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 |
27174 | #define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 |
27175 | #define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL |
27176 | #define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L |
27177 | //SCRATCH_ADDR |
27178 | #define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 |
27179 | #define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL |
27180 | //CP_PFP_ATOMIC_PREOP_LO |
27181 | #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 |
27182 | #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL |
27183 | //CP_PFP_ATOMIC_PREOP_HI |
27184 | #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 |
27185 | #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL |
27186 | //CP_PFP_GDS_ATOMIC0_PREOP_LO |
27187 | #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 |
27188 | #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
27189 | //CP_PFP_GDS_ATOMIC0_PREOP_HI |
27190 | #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 |
27191 | #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
27192 | //CP_PFP_GDS_ATOMIC1_PREOP_LO |
27193 | #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 |
27194 | #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
27195 | //CP_PFP_GDS_ATOMIC1_PREOP_HI |
27196 | #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 |
27197 | #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
27198 | //CP_APPEND_ADDR_LO |
27199 | #define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 |
27200 | #define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL |
27201 | //CP_APPEND_ADDR_HI |
27202 | #define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 |
27203 | #define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 |
27204 | #define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 |
27205 | #define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d |
27206 | #define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL |
27207 | #define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L |
27208 | #define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x06000000L |
27209 | #define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L |
27210 | //CP_APPEND_DATA |
27211 | #define CP_APPEND_DATA__DATA__SHIFT 0x0 |
27212 | #define CP_APPEND_DATA__DATA_MASK 0xFFFFFFFFL |
27213 | //CP_APPEND_DATA_LO |
27214 | #define CP_APPEND_DATA_LO__DATA__SHIFT 0x0 |
27215 | #define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL |
27216 | //CP_APPEND_LAST_CS_FENCE |
27217 | #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0 |
27218 | #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xFFFFFFFFL |
27219 | //CP_APPEND_LAST_CS_FENCE_LO |
27220 | #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0 |
27221 | #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL |
27222 | //CP_APPEND_LAST_PS_FENCE |
27223 | #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0 |
27224 | #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xFFFFFFFFL |
27225 | //CP_APPEND_LAST_PS_FENCE_LO |
27226 | #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0 |
27227 | #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL |
27228 | //CP_ATOMIC_PREOP_LO |
27229 | #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 |
27230 | #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL |
27231 | //CP_ME_ATOMIC_PREOP_LO |
27232 | #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 |
27233 | #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL |
27234 | //CP_ATOMIC_PREOP_HI |
27235 | #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 |
27236 | #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL |
27237 | //CP_ME_ATOMIC_PREOP_HI |
27238 | #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 |
27239 | #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL |
27240 | //CP_GDS_ATOMIC0_PREOP_LO |
27241 | #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 |
27242 | #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
27243 | //CP_ME_GDS_ATOMIC0_PREOP_LO |
27244 | #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 |
27245 | #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
27246 | //CP_GDS_ATOMIC0_PREOP_HI |
27247 | #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 |
27248 | #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
27249 | //CP_ME_GDS_ATOMIC0_PREOP_HI |
27250 | #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 |
27251 | #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
27252 | //CP_GDS_ATOMIC1_PREOP_LO |
27253 | #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 |
27254 | #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
27255 | //CP_ME_GDS_ATOMIC1_PREOP_LO |
27256 | #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 |
27257 | #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
27258 | //CP_GDS_ATOMIC1_PREOP_HI |
27259 | #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 |
27260 | #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
27261 | //CP_ME_GDS_ATOMIC1_PREOP_HI |
27262 | #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 |
27263 | #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
27264 | //CP_ME_MC_WADDR_LO |
27265 | #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 |
27266 | #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL |
27267 | //CP_ME_MC_WADDR_HI |
27268 | #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 |
27269 | #define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 |
27270 | #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL |
27271 | #define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00C00000L |
27272 | //CP_ME_MC_WDATA_LO |
27273 | #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 |
27274 | #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL |
27275 | //CP_ME_MC_WDATA_HI |
27276 | #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 |
27277 | #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL |
27278 | //CP_ME_MC_RADDR_LO |
27279 | #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 |
27280 | #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL |
27281 | //CP_ME_MC_RADDR_HI |
27282 | #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 |
27283 | #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 |
27284 | #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL |
27285 | #define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00C00000L |
27286 | //CP_SEM_WAIT_TIMER |
27287 | #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 |
27288 | #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL |
27289 | //CP_SIG_SEM_ADDR_LO |
27290 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 |
27291 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 |
27292 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L |
27293 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L |
27294 | //CP_SIG_SEM_ADDR_HI |
27295 | #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 |
27296 | #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 |
27297 | #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 |
27298 | #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 |
27299 | #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d |
27300 | #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL |
27301 | #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L |
27302 | #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L |
27303 | #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L |
27304 | #define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L |
27305 | //CP_WAIT_REG_MEM_TIMEOUT |
27306 | #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 |
27307 | #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL |
27308 | //CP_WAIT_SEM_ADDR_LO |
27309 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 |
27310 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 |
27311 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L |
27312 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L |
27313 | //CP_WAIT_SEM_ADDR_HI |
27314 | #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 |
27315 | #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 |
27316 | #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 |
27317 | #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 |
27318 | #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d |
27319 | #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL |
27320 | #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L |
27321 | #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L |
27322 | #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L |
27323 | #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L |
27324 | //CP_DMA_PFP_CONTROL |
27325 | #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa |
27326 | #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd |
27327 | #define CP_DMA_PFP_CONTROL__SRC_VOLATLE__SHIFT 0xf |
27328 | #define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 |
27329 | #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 |
27330 | #define CP_DMA_PFP_CONTROL__DST_VOLATLE__SHIFT 0x1b |
27331 | #define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d |
27332 | #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L |
27333 | #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00006000L |
27334 | #define CP_DMA_PFP_CONTROL__SRC_VOLATLE_MASK 0x00008000L |
27335 | #define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L |
27336 | #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x06000000L |
27337 | #define CP_DMA_PFP_CONTROL__DST_VOLATLE_MASK 0x08000000L |
27338 | #define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L |
27339 | //CP_DMA_ME_CONTROL |
27340 | #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa |
27341 | #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd |
27342 | #define CP_DMA_ME_CONTROL__SRC_VOLATLE__SHIFT 0xf |
27343 | #define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 |
27344 | #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 |
27345 | #define CP_DMA_ME_CONTROL__DST_VOLATLE__SHIFT 0x1b |
27346 | #define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d |
27347 | #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L |
27348 | #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00006000L |
27349 | #define CP_DMA_ME_CONTROL__SRC_VOLATLE_MASK 0x00008000L |
27350 | #define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L |
27351 | #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x06000000L |
27352 | #define CP_DMA_ME_CONTROL__DST_VOLATLE_MASK 0x08000000L |
27353 | #define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L |
27354 | //CP_COHER_BASE_HI |
27355 | #define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 |
27356 | #define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL |
27357 | //CP_COHER_START_DELAY |
27358 | #define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 |
27359 | #define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL |
27360 | //CP_COHER_CNTL |
27361 | #define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3 |
27362 | #define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4 |
27363 | #define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5 |
27364 | #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf |
27365 | #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 |
27366 | #define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 |
27367 | #define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 |
27368 | #define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 |
27369 | #define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a |
27370 | #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b |
27371 | #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c |
27372 | #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d |
27373 | #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e |
27374 | #define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L |
27375 | #define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L |
27376 | #define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L |
27377 | #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L |
27378 | #define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L |
27379 | #define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L |
27380 | #define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L |
27381 | #define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L |
27382 | #define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L |
27383 | #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L |
27384 | #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L |
27385 | #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L |
27386 | #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L |
27387 | //CP_COHER_SIZE |
27388 | #define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 |
27389 | #define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL |
27390 | //CP_COHER_BASE |
27391 | #define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 |
27392 | #define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL |
27393 | //CP_COHER_STATUS |
27394 | #define CP_COHER_STATUS__MEID__SHIFT 0x18 |
27395 | #define CP_COHER_STATUS__STATUS__SHIFT 0x1f |
27396 | #define CP_COHER_STATUS__MEID_MASK 0x03000000L |
27397 | #define CP_COHER_STATUS__STATUS_MASK 0x80000000L |
27398 | //CP_DMA_ME_SRC_ADDR |
27399 | #define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 |
27400 | #define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL |
27401 | //CP_DMA_ME_SRC_ADDR_HI |
27402 | #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 |
27403 | #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL |
27404 | //CP_DMA_ME_DST_ADDR |
27405 | #define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 |
27406 | #define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL |
27407 | //CP_DMA_ME_DST_ADDR_HI |
27408 | #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 |
27409 | #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL |
27410 | //CP_DMA_ME_COMMAND |
27411 | #define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 |
27412 | #define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a |
27413 | #define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b |
27414 | #define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c |
27415 | #define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d |
27416 | #define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e |
27417 | #define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f |
27418 | #define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL |
27419 | #define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L |
27420 | #define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L |
27421 | #define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L |
27422 | #define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L |
27423 | #define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L |
27424 | #define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L |
27425 | //CP_DMA_PFP_SRC_ADDR |
27426 | #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 |
27427 | #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL |
27428 | //CP_DMA_PFP_SRC_ADDR_HI |
27429 | #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 |
27430 | #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL |
27431 | //CP_DMA_PFP_DST_ADDR |
27432 | #define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 |
27433 | #define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL |
27434 | //CP_DMA_PFP_DST_ADDR_HI |
27435 | #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 |
27436 | #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL |
27437 | //CP_DMA_PFP_COMMAND |
27438 | #define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 |
27439 | #define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a |
27440 | #define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b |
27441 | #define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c |
27442 | #define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d |
27443 | #define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e |
27444 | #define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f |
27445 | #define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL |
27446 | #define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L |
27447 | #define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L |
27448 | #define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L |
27449 | #define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L |
27450 | #define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L |
27451 | #define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L |
27452 | //CP_DMA_CNTL |
27453 | #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0 |
27454 | #define CP_DMA_CNTL__WATCH_CONTROL__SHIFT 0x1 |
27455 | #define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 |
27456 | #define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 |
27457 | #define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c |
27458 | #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d |
27459 | #define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e |
27460 | #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L |
27461 | #define CP_DMA_CNTL__WATCH_CONTROL_MASK 0x00000002L |
27462 | #define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L |
27463 | #define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x01FF0000L |
27464 | #define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L |
27465 | #define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L |
27466 | #define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L |
27467 | //CP_DMA_READ_TAGS |
27468 | #define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 |
27469 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c |
27470 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL |
27471 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L |
27472 | //CP_COHER_SIZE_HI |
27473 | #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 |
27474 | #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL |
27475 | //CP_PFP_IB_CONTROL |
27476 | #define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 |
27477 | #define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL |
27478 | //CP_PFP_LOAD_CONTROL |
27479 | #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 |
27480 | #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 |
27481 | #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 |
27482 | #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 |
27483 | #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L |
27484 | #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L |
27485 | #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L |
27486 | #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L |
27487 | //CP_SCRATCH_INDEX |
27488 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 |
27489 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f |
27490 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL |
27491 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L |
27492 | //CP_SCRATCH_DATA |
27493 | #define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 |
27494 | #define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL |
27495 | //CP_RB_OFFSET |
27496 | #define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 |
27497 | #define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL |
27498 | //CP_IB1_OFFSET |
27499 | #define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 |
27500 | #define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL |
27501 | //CP_IB2_OFFSET |
27502 | #define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 |
27503 | #define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL |
27504 | //CP_IB1_PREAMBLE_BEGIN |
27505 | #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 |
27506 | #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL |
27507 | //CP_IB1_PREAMBLE_END |
27508 | #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 |
27509 | #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL |
27510 | //CP_IB2_PREAMBLE_BEGIN |
27511 | #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 |
27512 | #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL |
27513 | //CP_IB2_PREAMBLE_END |
27514 | #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 |
27515 | #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL |
27516 | //CP_CE_IB1_OFFSET |
27517 | #define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 |
27518 | #define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL |
27519 | //CP_CE_IB2_OFFSET |
27520 | #define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 |
27521 | #define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL |
27522 | //CP_CE_COUNTER |
27523 | #define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 |
27524 | #define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL |
27525 | //CP_DMA_ME_CMD_ADDR_LO |
27526 | #define CP_DMA_ME_CMD_ADDR_LO__RSVD__SHIFT 0x0 |
27527 | #define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 |
27528 | #define CP_DMA_ME_CMD_ADDR_LO__RSVD_MASK 0x00000003L |
27529 | #define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
27530 | //CP_DMA_ME_CMD_ADDR_HI |
27531 | #define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 |
27532 | #define CP_DMA_ME_CMD_ADDR_HI__RSVD__SHIFT 0x10 |
27533 | #define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
27534 | #define CP_DMA_ME_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L |
27535 | //CP_DMA_PFP_CMD_ADDR_LO |
27536 | #define CP_DMA_PFP_CMD_ADDR_LO__RSVD__SHIFT 0x0 |
27537 | #define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 |
27538 | #define CP_DMA_PFP_CMD_ADDR_LO__RSVD_MASK 0x00000003L |
27539 | #define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
27540 | //CP_DMA_PFP_CMD_ADDR_HI |
27541 | #define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 |
27542 | #define CP_DMA_PFP_CMD_ADDR_HI__RSVD__SHIFT 0x10 |
27543 | #define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
27544 | #define CP_DMA_PFP_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L |
27545 | //CP_APPEND_CMD_ADDR_LO |
27546 | #define CP_APPEND_CMD_ADDR_LO__RSVD__SHIFT 0x0 |
27547 | #define CP_APPEND_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 |
27548 | #define CP_APPEND_CMD_ADDR_LO__RSVD_MASK 0x00000003L |
27549 | #define CP_APPEND_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
27550 | //CP_APPEND_CMD_ADDR_HI |
27551 | #define CP_APPEND_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 |
27552 | #define CP_APPEND_CMD_ADDR_HI__RSVD__SHIFT 0x10 |
27553 | #define CP_APPEND_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
27554 | #define CP_APPEND_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L |
27555 | //CP_CE_INIT_CMD_BUFSZ |
27556 | #define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0 |
27557 | #define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL |
27558 | //CP_CE_IB1_CMD_BUFSZ |
27559 | #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 |
27560 | #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL |
27561 | //CP_CE_IB2_CMD_BUFSZ |
27562 | #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 |
27563 | #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL |
27564 | //CP_IB1_CMD_BUFSZ |
27565 | #define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 |
27566 | #define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL |
27567 | //CP_IB2_CMD_BUFSZ |
27568 | #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 |
27569 | #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL |
27570 | //CP_ST_CMD_BUFSZ |
27571 | #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0 |
27572 | #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL |
27573 | //CP_CE_INIT_BASE_LO |
27574 | #define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 |
27575 | #define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L |
27576 | //CP_CE_INIT_BASE_HI |
27577 | #define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 |
27578 | #define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL |
27579 | //CP_CE_INIT_BUFSZ |
27580 | #define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 |
27581 | #define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL |
27582 | //CP_CE_IB1_BASE_LO |
27583 | #define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 |
27584 | #define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL |
27585 | //CP_CE_IB1_BASE_HI |
27586 | #define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 |
27587 | #define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL |
27588 | //CP_CE_IB1_BUFSZ |
27589 | #define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 |
27590 | #define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL |
27591 | //CP_CE_IB2_BASE_LO |
27592 | #define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 |
27593 | #define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL |
27594 | //CP_CE_IB2_BASE_HI |
27595 | #define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 |
27596 | #define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL |
27597 | //CP_CE_IB2_BUFSZ |
27598 | #define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 |
27599 | #define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL |
27600 | //CP_IB1_BASE_LO |
27601 | #define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 |
27602 | #define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL |
27603 | //CP_IB1_BASE_HI |
27604 | #define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 |
27605 | #define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL |
27606 | //CP_IB1_BUFSZ |
27607 | #define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 |
27608 | #define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL |
27609 | //CP_IB2_BASE_LO |
27610 | #define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 |
27611 | #define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL |
27612 | //CP_IB2_BASE_HI |
27613 | #define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 |
27614 | #define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL |
27615 | //CP_IB2_BUFSZ |
27616 | #define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 |
27617 | #define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL |
27618 | //CP_ST_BASE_LO |
27619 | #define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 |
27620 | #define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL |
27621 | //CP_ST_BASE_HI |
27622 | #define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 |
27623 | #define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL |
27624 | //CP_ST_BUFSZ |
27625 | #define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 |
27626 | #define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL |
27627 | //CP_EOP_DONE_EVENT_CNTL |
27628 | #define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL__SHIFT 0xc |
27629 | #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19 |
27630 | #define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT 0x1b |
27631 | #define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c |
27632 | #define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL_MASK 0x00FFF000L |
27633 | #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x06000000L |
27634 | #define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK 0x08000000L |
27635 | #define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L |
27636 | //CP_EOP_DONE_DATA_CNTL |
27637 | #define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 |
27638 | #define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 |
27639 | #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d |
27640 | #define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L |
27641 | #define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L |
27642 | #define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L |
27643 | //CP_EOP_DONE_CNTX_ID |
27644 | #define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 |
27645 | #define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL |
27646 | //CP_DB_BASE_LO |
27647 | #define CP_DB_BASE_LO__DB_BASE_LO__SHIFT 0x2 |
27648 | #define CP_DB_BASE_LO__DB_BASE_LO_MASK 0xFFFFFFFCL |
27649 | //CP_DB_BASE_HI |
27650 | #define CP_DB_BASE_HI__DB_BASE_HI__SHIFT 0x0 |
27651 | #define CP_DB_BASE_HI__DB_BASE_HI_MASK 0x0000FFFFL |
27652 | //CP_DB_BUFSZ |
27653 | #define CP_DB_BUFSZ__DB_BUFSZ__SHIFT 0x0 |
27654 | #define CP_DB_BUFSZ__DB_BUFSZ_MASK 0x000FFFFFL |
27655 | //CP_DB_CMD_BUFSZ |
27656 | #define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT 0x0 |
27657 | #define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK 0x000FFFFFL |
27658 | //CP_CE_DB_BASE_LO |
27659 | #define CP_CE_DB_BASE_LO__DB_BASE_LO__SHIFT 0x2 |
27660 | #define CP_CE_DB_BASE_LO__DB_BASE_LO_MASK 0xFFFFFFFCL |
27661 | //CP_CE_DB_BASE_HI |
27662 | #define CP_CE_DB_BASE_HI__DB_BASE_HI__SHIFT 0x0 |
27663 | #define CP_CE_DB_BASE_HI__DB_BASE_HI_MASK 0x0000FFFFL |
27664 | //CP_CE_DB_BUFSZ |
27665 | #define CP_CE_DB_BUFSZ__DB_BUFSZ__SHIFT 0x0 |
27666 | #define CP_CE_DB_BUFSZ__DB_BUFSZ_MASK 0x000FFFFFL |
27667 | //CP_CE_DB_CMD_BUFSZ |
27668 | #define CP_CE_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT 0x0 |
27669 | #define CP_CE_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK 0x000FFFFFL |
27670 | //CP_PFP_COMPLETION_STATUS |
27671 | #define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 |
27672 | #define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L |
27673 | //CP_CE_COMPLETION_STATUS |
27674 | #define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0 |
27675 | #define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L |
27676 | //CP_PRED_NOT_VISIBLE |
27677 | #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 |
27678 | #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L |
27679 | //CP_PFP_METADATA_BASE_ADDR |
27680 | #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 |
27681 | #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
27682 | //CP_PFP_METADATA_BASE_ADDR_HI |
27683 | #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
27684 | #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
27685 | //CP_CE_METADATA_BASE_ADDR |
27686 | #define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 |
27687 | #define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
27688 | //CP_CE_METADATA_BASE_ADDR_HI |
27689 | #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
27690 | #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
27691 | //CP_DRAW_INDX_INDR_ADDR |
27692 | #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 |
27693 | #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
27694 | //CP_DRAW_INDX_INDR_ADDR_HI |
27695 | #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 |
27696 | #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
27697 | //CP_DISPATCH_INDR_ADDR |
27698 | #define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 |
27699 | #define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
27700 | //CP_DISPATCH_INDR_ADDR_HI |
27701 | #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 |
27702 | #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
27703 | //CP_INDEX_BASE_ADDR |
27704 | #define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 |
27705 | #define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
27706 | //CP_INDEX_BASE_ADDR_HI |
27707 | #define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
27708 | #define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
27709 | //CP_INDEX_TYPE |
27710 | #define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 |
27711 | #define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L |
27712 | //CP_GDS_BKUP_ADDR |
27713 | #define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 |
27714 | #define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
27715 | //CP_GDS_BKUP_ADDR_HI |
27716 | #define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 |
27717 | #define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
27718 | //CP_SAMPLE_STATUS |
27719 | #define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 |
27720 | #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 |
27721 | #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 |
27722 | #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 |
27723 | #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 |
27724 | #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 |
27725 | #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 |
27726 | #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 |
27727 | #define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L |
27728 | #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L |
27729 | #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L |
27730 | #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L |
27731 | #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L |
27732 | #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L |
27733 | #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L |
27734 | #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L |
27735 | //CP_ME_COHER_CNTL |
27736 | #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 |
27737 | #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 |
27738 | #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 |
27739 | #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 |
27740 | #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 |
27741 | #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 |
27742 | #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa |
27743 | #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb |
27744 | #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc |
27745 | #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd |
27746 | #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe |
27747 | #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 |
27748 | #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 |
27749 | #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L |
27750 | #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L |
27751 | #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L |
27752 | #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L |
27753 | #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L |
27754 | #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L |
27755 | #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L |
27756 | #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L |
27757 | #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L |
27758 | #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L |
27759 | #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L |
27760 | #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L |
27761 | #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L |
27762 | //CP_ME_COHER_SIZE |
27763 | #define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 |
27764 | #define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL |
27765 | //CP_ME_COHER_SIZE_HI |
27766 | #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 |
27767 | #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL |
27768 | //CP_ME_COHER_BASE |
27769 | #define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 |
27770 | #define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL |
27771 | //CP_ME_COHER_BASE_HI |
27772 | #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 |
27773 | #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL |
27774 | //CP_ME_COHER_STATUS |
27775 | #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 |
27776 | #define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f |
27777 | #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL |
27778 | #define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L |
27779 | //RLC_GPM_PERF_COUNT_0 |
27780 | #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 |
27781 | #define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 |
27782 | #define RLC_GPM_PERF_COUNT_0__SA_INDEX__SHIFT 0x8 |
27783 | #define RLC_GPM_PERF_COUNT_0__WGP_INDEX__SHIFT 0xc |
27784 | #define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 |
27785 | #define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 |
27786 | #define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 |
27787 | #define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 |
27788 | #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL |
27789 | #define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L |
27790 | #define RLC_GPM_PERF_COUNT_0__SA_INDEX_MASK 0x00000F00L |
27791 | #define RLC_GPM_PERF_COUNT_0__WGP_INDEX_MASK 0x0000F000L |
27792 | #define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L |
27793 | #define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L |
27794 | #define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L |
27795 | #define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L |
27796 | //RLC_GPM_PERF_COUNT_1 |
27797 | #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 |
27798 | #define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 |
27799 | #define RLC_GPM_PERF_COUNT_1__SA_INDEX__SHIFT 0x8 |
27800 | #define RLC_GPM_PERF_COUNT_1__WGP_INDEX__SHIFT 0xc |
27801 | #define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 |
27802 | #define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 |
27803 | #define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 |
27804 | #define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 |
27805 | #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL |
27806 | #define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L |
27807 | #define RLC_GPM_PERF_COUNT_1__SA_INDEX_MASK 0x00000F00L |
27808 | #define RLC_GPM_PERF_COUNT_1__WGP_INDEX_MASK 0x0000F000L |
27809 | #define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L |
27810 | #define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L |
27811 | #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L |
27812 | #define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L |
27813 | //GRBM_GFX_INDEX |
27814 | #define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 |
27815 | #define GRBM_GFX_INDEX__SA_INDEX__SHIFT 0x8 |
27816 | #define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 |
27817 | #define GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT 0x1d |
27818 | #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e |
27819 | #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f |
27820 | #define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL |
27821 | #define GRBM_GFX_INDEX__SA_INDEX_MASK 0x0000FF00L |
27822 | #define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L |
27823 | #define GRBM_GFX_INDEX__SA_BROADCAST_WRITES_MASK 0x20000000L |
27824 | #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L |
27825 | #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L |
27826 | //VGT_ESGS_RING_SIZE_UMD |
27827 | #define VGT_ESGS_RING_SIZE_UMD__MEM_SIZE__SHIFT 0x0 |
27828 | #define VGT_ESGS_RING_SIZE_UMD__MEM_SIZE_MASK 0xFFFFFFFFL |
27829 | //VGT_GSVS_RING_SIZE_UMD |
27830 | #define VGT_GSVS_RING_SIZE_UMD__MEM_SIZE__SHIFT 0x0 |
27831 | #define VGT_GSVS_RING_SIZE_UMD__MEM_SIZE_MASK 0xFFFFFFFFL |
27832 | //VGT_PRIMITIVE_TYPE |
27833 | #define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 |
27834 | #define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL |
27835 | //VGT_INDEX_TYPE |
27836 | #define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 |
27837 | #define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L |
27838 | //VGT_STRMOUT_BUFFER_FILLED_SIZE_0 |
27839 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 |
27840 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL |
27841 | //VGT_STRMOUT_BUFFER_FILLED_SIZE_1 |
27842 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 |
27843 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL |
27844 | //VGT_STRMOUT_BUFFER_FILLED_SIZE_2 |
27845 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 |
27846 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL |
27847 | //VGT_STRMOUT_BUFFER_FILLED_SIZE_3 |
27848 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 |
27849 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL |
27850 | //GE_MIN_VTX_INDX |
27851 | #define GE_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 |
27852 | #define GE_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL |
27853 | //GE_INDX_OFFSET |
27854 | #define GE_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 |
27855 | #define GE_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL |
27856 | //GE_MULTI_PRIM_IB_RESET_EN |
27857 | #define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 |
27858 | #define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 |
27859 | #define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L |
27860 | #define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L |
27861 | //VGT_NUM_INDICES |
27862 | #define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 |
27863 | #define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL |
27864 | //VGT_NUM_INSTANCES |
27865 | #define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 |
27866 | #define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL |
27867 | //VGT_TF_RING_SIZE_UMD |
27868 | #define VGT_TF_RING_SIZE_UMD__SIZE__SHIFT 0x0 |
27869 | #define VGT_TF_RING_SIZE_UMD__SIZE_MASK 0x0000FFFFL |
27870 | //VGT_HS_OFFCHIP_PARAM_UMD |
27871 | #define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_BUFFERING__SHIFT 0x0 |
27872 | #define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_GRANULARITY__SHIFT 0x9 |
27873 | #define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_BUFFERING_MASK 0x000001FFL |
27874 | #define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_GRANULARITY_MASK 0x00000600L |
27875 | //VGT_TF_MEMORY_BASE_UMD |
27876 | #define VGT_TF_MEMORY_BASE_UMD__BASE__SHIFT 0x0 |
27877 | #define VGT_TF_MEMORY_BASE_UMD__BASE_MASK 0xFFFFFFFFL |
27878 | //GE_DMA_FIRST_INDEX |
27879 | #define GE_DMA_FIRST_INDEX__FIRST_INDEX__SHIFT 0x0 |
27880 | #define GE_DMA_FIRST_INDEX__FIRST_INDEX_MASK 0xFFFFFFFFL |
27881 | //WD_POS_BUF_BASE |
27882 | #define WD_POS_BUF_BASE__BASE__SHIFT 0x0 |
27883 | #define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL |
27884 | //WD_POS_BUF_BASE_HI |
27885 | #define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0 |
27886 | #define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL |
27887 | //WD_CNTL_SB_BUF_BASE |
27888 | #define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0 |
27889 | #define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL |
27890 | //WD_CNTL_SB_BUF_BASE_HI |
27891 | #define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0 |
27892 | #define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL |
27893 | //WD_INDEX_BUF_BASE |
27894 | #define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0 |
27895 | #define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL |
27896 | //WD_INDEX_BUF_BASE_HI |
27897 | #define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0 |
27898 | #define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL |
27899 | //IA_MULTI_VGT_PARAM_PIPED |
27900 | #define IA_MULTI_VGT_PARAM_PIPED__PRIMGROUP_SIZE__SHIFT 0x0 |
27901 | #define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_VS_WAVE_ON__SHIFT 0x10 |
27902 | #define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOP__SHIFT 0x11 |
27903 | #define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_ES_WAVE_ON__SHIFT 0x12 |
27904 | #define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOI__SHIFT 0x13 |
27905 | #define IA_MULTI_VGT_PARAM_PIPED__WD_SWITCH_ON_EOP__SHIFT 0x14 |
27906 | #define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_BASIC__SHIFT 0x15 |
27907 | #define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_ADV__SHIFT 0x16 |
27908 | #define IA_MULTI_VGT_PARAM_PIPED__HW_USE_ONLY__SHIFT 0x17 |
27909 | #define IA_MULTI_VGT_PARAM_PIPED__PRIMGROUP_SIZE_MASK 0x0000FFFFL |
27910 | #define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_VS_WAVE_ON_MASK 0x00010000L |
27911 | #define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOP_MASK 0x00020000L |
27912 | #define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_ES_WAVE_ON_MASK 0x00040000L |
27913 | #define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOI_MASK 0x00080000L |
27914 | #define IA_MULTI_VGT_PARAM_PIPED__WD_SWITCH_ON_EOP_MASK 0x00100000L |
27915 | #define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_BASIC_MASK 0x00200000L |
27916 | #define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_ADV_MASK 0x00400000L |
27917 | #define IA_MULTI_VGT_PARAM_PIPED__HW_USE_ONLY_MASK 0x00800000L |
27918 | //GE_MAX_VTX_INDX |
27919 | #define GE_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 |
27920 | #define GE_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL |
27921 | //VGT_INSTANCE_BASE_ID |
27922 | #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 |
27923 | #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL |
27924 | //GE_CNTL |
27925 | #define GE_CNTL__PRIM_GRP_SIZE__SHIFT 0x0 |
27926 | #define GE_CNTL__VERT_GRP_SIZE__SHIFT 0x9 |
27927 | #define GE_CNTL__BREAK_WAVE_AT_EOI__SHIFT 0x12 |
27928 | #define GE_CNTL__PACKET_TO_ONE_PA__SHIFT 0x13 |
27929 | #define GE_CNTL__PRIM_GRP_SIZE_MASK 0x000001FFL |
27930 | #define GE_CNTL__VERT_GRP_SIZE_MASK 0x0003FE00L |
27931 | #define GE_CNTL__BREAK_WAVE_AT_EOI_MASK 0x00040000L |
27932 | #define GE_CNTL__PACKET_TO_ONE_PA_MASK 0x00080000L |
27933 | //GE_USER_VGPR1 |
27934 | #define GE_USER_VGPR1__DATA__SHIFT 0x0 |
27935 | #define GE_USER_VGPR1__DATA_MASK 0xFFFFFFFFL |
27936 | //GE_USER_VGPR2 |
27937 | #define GE_USER_VGPR2__DATA__SHIFT 0x0 |
27938 | #define GE_USER_VGPR2__DATA_MASK 0xFFFFFFFFL |
27939 | //GE_USER_VGPR3 |
27940 | #define GE_USER_VGPR3__DATA__SHIFT 0x0 |
27941 | #define GE_USER_VGPR3__DATA_MASK 0xFFFFFFFFL |
27942 | //GE_STEREO_CNTL |
27943 | #define GE_STEREO_CNTL__RT_SLICE__SHIFT 0x0 |
27944 | #define GE_STEREO_CNTL__VIEWPORT__SHIFT 0x3 |
27945 | #define GE_STEREO_CNTL__EN_STEREO__SHIFT 0x8 |
27946 | #define GE_STEREO_CNTL__RT_SLICE_MASK 0x00000007L |
27947 | #define GE_STEREO_CNTL__VIEWPORT_MASK 0x00000078L |
27948 | #define GE_STEREO_CNTL__EN_STEREO_MASK 0x00000100L |
27949 | //GE_PC_ALLOC |
27950 | #define GE_PC_ALLOC__OVERSUB_EN__SHIFT 0x0 |
27951 | #define GE_PC_ALLOC__NUM_PC_LINES__SHIFT 0x1 |
27952 | #define GE_PC_ALLOC__OVERSUB_EN_MASK 0x00000001L |
27953 | #define GE_PC_ALLOC__NUM_PC_LINES_MASK 0x000007FEL |
27954 | //VGT_TF_MEMORY_BASE_HI_UMD |
27955 | #define VGT_TF_MEMORY_BASE_HI_UMD__BASE_HI__SHIFT 0x0 |
27956 | #define VGT_TF_MEMORY_BASE_HI_UMD__BASE_HI_MASK 0x000000FFL |
27957 | //GE_USER_VGPR_EN |
27958 | #define GE_USER_VGPR_EN__EN_USER_VGPR1__SHIFT 0x0 |
27959 | #define GE_USER_VGPR_EN__EN_USER_VGPR2__SHIFT 0x1 |
27960 | #define GE_USER_VGPR_EN__EN_USER_VGPR3__SHIFT 0x2 |
27961 | #define GE_USER_VGPR_EN__EN_USER_VGPR1_MASK 0x00000001L |
27962 | #define GE_USER_VGPR_EN__EN_USER_VGPR2_MASK 0x00000002L |
27963 | #define GE_USER_VGPR_EN__EN_USER_VGPR3_MASK 0x00000004L |
27964 | //PA_SU_LINE_STIPPLE_VALUE |
27965 | #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 |
27966 | #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL |
27967 | //PA_SC_LINE_STIPPLE_STATE |
27968 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 |
27969 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 |
27970 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL |
27971 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L |
27972 | //PA_SC_SCREEN_EXTENT_MIN_0 |
27973 | #define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 |
27974 | #define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 |
27975 | #define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL |
27976 | #define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L |
27977 | //PA_SC_SCREEN_EXTENT_MAX_0 |
27978 | #define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 |
27979 | #define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 |
27980 | #define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL |
27981 | #define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L |
27982 | //PA_SC_SCREEN_EXTENT_MIN_1 |
27983 | #define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 |
27984 | #define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 |
27985 | #define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL |
27986 | #define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L |
27987 | //PA_SC_SCREEN_EXTENT_MAX_1 |
27988 | #define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 |
27989 | #define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 |
27990 | #define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL |
27991 | #define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L |
27992 | //PA_SC_P3D_TRAP_SCREEN_HV_EN |
27993 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 |
27994 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 |
27995 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L |
27996 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L |
27997 | //PA_SC_P3D_TRAP_SCREEN_H |
27998 | #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 |
27999 | #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL |
28000 | //PA_SC_P3D_TRAP_SCREEN_V |
28001 | #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 |
28002 | #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL |
28003 | //PA_SC_P3D_TRAP_SCREEN_OCCURRENCE |
28004 | #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 |
28005 | #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL |
28006 | //PA_SC_P3D_TRAP_SCREEN_COUNT |
28007 | #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 |
28008 | #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL |
28009 | //PA_SC_HP3D_TRAP_SCREEN_HV_EN |
28010 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 |
28011 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 |
28012 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L |
28013 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L |
28014 | //PA_SC_HP3D_TRAP_SCREEN_H |
28015 | #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 |
28016 | #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL |
28017 | //PA_SC_HP3D_TRAP_SCREEN_V |
28018 | #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 |
28019 | #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL |
28020 | //PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE |
28021 | #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 |
28022 | #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL |
28023 | //PA_SC_HP3D_TRAP_SCREEN_COUNT |
28024 | #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 |
28025 | #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL |
28026 | //PA_SC_TRAP_SCREEN_HV_EN |
28027 | #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 |
28028 | #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 |
28029 | #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L |
28030 | #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L |
28031 | //PA_SC_TRAP_SCREEN_H |
28032 | #define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 |
28033 | #define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL |
28034 | //PA_SC_TRAP_SCREEN_V |
28035 | #define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 |
28036 | #define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL |
28037 | //PA_SC_TRAP_SCREEN_OCCURRENCE |
28038 | #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 |
28039 | #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL |
28040 | //PA_SC_TRAP_SCREEN_COUNT |
28041 | #define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 |
28042 | #define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL |
28043 | //SQ_THREAD_TRACE_USERDATA_0 |
28044 | #define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 |
28045 | #define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL |
28046 | //SQ_THREAD_TRACE_USERDATA_1 |
28047 | #define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 |
28048 | #define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL |
28049 | //SQ_THREAD_TRACE_USERDATA_2 |
28050 | #define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 |
28051 | #define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL |
28052 | //SQ_THREAD_TRACE_USERDATA_3 |
28053 | #define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 |
28054 | #define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL |
28055 | //SQ_THREAD_TRACE_USERDATA_4 |
28056 | #define SQ_THREAD_TRACE_USERDATA_4__DATA__SHIFT 0x0 |
28057 | #define SQ_THREAD_TRACE_USERDATA_4__DATA_MASK 0xFFFFFFFFL |
28058 | //SQ_THREAD_TRACE_USERDATA_5 |
28059 | #define SQ_THREAD_TRACE_USERDATA_5__DATA__SHIFT 0x0 |
28060 | #define SQ_THREAD_TRACE_USERDATA_5__DATA_MASK 0xFFFFFFFFL |
28061 | //SQ_THREAD_TRACE_USERDATA_6 |
28062 | #define SQ_THREAD_TRACE_USERDATA_6__DATA__SHIFT 0x0 |
28063 | #define SQ_THREAD_TRACE_USERDATA_6__DATA_MASK 0xFFFFFFFFL |
28064 | //SQ_THREAD_TRACE_USERDATA_7 |
28065 | #define SQ_THREAD_TRACE_USERDATA_7__DATA__SHIFT 0x0 |
28066 | #define SQ_THREAD_TRACE_USERDATA_7__DATA_MASK 0xFFFFFFFFL |
28067 | //SQC_CACHES |
28068 | #define SQC_CACHES__TARGET_INST__SHIFT 0x0 |
28069 | #define SQC_CACHES__TARGET_DATA__SHIFT 0x1 |
28070 | #define SQC_CACHES__INVALIDATE__SHIFT 0x2 |
28071 | #define SQC_CACHES__WRITEBACK__SHIFT 0x3 |
28072 | #define SQC_CACHES__VOL__SHIFT 0x4 |
28073 | #define SQC_CACHES__COMPLETE__SHIFT 0x10 |
28074 | #define SQC_CACHES__L2_WB_POLICY__SHIFT 0x11 |
28075 | #define SQC_CACHES__TARGET_INST_MASK 0x00000001L |
28076 | #define SQC_CACHES__TARGET_DATA_MASK 0x00000002L |
28077 | #define SQC_CACHES__INVALIDATE_MASK 0x00000004L |
28078 | #define SQC_CACHES__WRITEBACK_MASK 0x00000008L |
28079 | #define SQC_CACHES__VOL_MASK 0x00000010L |
28080 | #define SQC_CACHES__COMPLETE_MASK 0x00010000L |
28081 | #define SQC_CACHES__L2_WB_POLICY_MASK 0x00060000L |
28082 | //SQC_WRITEBACK |
28083 | #define SQC_WRITEBACK__DWB__SHIFT 0x0 |
28084 | #define SQC_WRITEBACK__DIRTY__SHIFT 0x1 |
28085 | #define SQC_WRITEBACK__DWB_MASK 0x00000001L |
28086 | #define SQC_WRITEBACK__DIRTY_MASK 0x00000002L |
28087 | //TA_CS_BC_BASE_ADDR |
28088 | #define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 |
28089 | #define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL |
28090 | //TA_CS_BC_BASE_ADDR_HI |
28091 | #define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 |
28092 | #define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL |
28093 | //DB_OCCLUSION_COUNT0_LOW |
28094 | #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 |
28095 | #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
28096 | //DB_OCCLUSION_COUNT0_HI |
28097 | #define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 |
28098 | #define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL |
28099 | //DB_OCCLUSION_COUNT1_LOW |
28100 | #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 |
28101 | #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
28102 | //DB_OCCLUSION_COUNT1_HI |
28103 | #define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 |
28104 | #define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL |
28105 | //DB_OCCLUSION_COUNT2_LOW |
28106 | #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 |
28107 | #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
28108 | //DB_OCCLUSION_COUNT2_HI |
28109 | #define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 |
28110 | #define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL |
28111 | //DB_OCCLUSION_COUNT3_LOW |
28112 | #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 |
28113 | #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
28114 | //DB_OCCLUSION_COUNT3_HI |
28115 | #define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 |
28116 | #define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL |
28117 | //DB_ZPASS_COUNT_LOW |
28118 | #define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 |
28119 | #define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
28120 | //DB_ZPASS_COUNT_HI |
28121 | #define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 |
28122 | #define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL |
28123 | //GDS_RD_ADDR |
28124 | #define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 |
28125 | #define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL |
28126 | //GDS_RD_DATA |
28127 | #define GDS_RD_DATA__READ_DATA__SHIFT 0x0 |
28128 | #define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL |
28129 | //GDS_RD_BURST_ADDR |
28130 | #define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 |
28131 | #define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL |
28132 | //GDS_RD_BURST_COUNT |
28133 | #define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 |
28134 | #define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL |
28135 | //GDS_RD_BURST_DATA |
28136 | #define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 |
28137 | #define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL |
28138 | //GDS_WR_ADDR |
28139 | #define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 |
28140 | #define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL |
28141 | //GDS_WR_DATA |
28142 | #define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 |
28143 | #define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL |
28144 | //GDS_WR_BURST_ADDR |
28145 | #define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 |
28146 | #define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL |
28147 | //GDS_WR_BURST_DATA |
28148 | #define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 |
28149 | #define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL |
28150 | //GDS_WRITE_COMPLETE |
28151 | #define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 |
28152 | #define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL |
28153 | //GDS_ATOM_CNTL |
28154 | #define GDS_ATOM_CNTL__AINC__SHIFT 0x0 |
28155 | #define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 |
28156 | #define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 |
28157 | #define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa |
28158 | #define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL |
28159 | #define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L |
28160 | #define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L |
28161 | #define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L |
28162 | //GDS_ATOM_COMPLETE |
28163 | #define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 |
28164 | #define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 |
28165 | #define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L |
28166 | #define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL |
28167 | //GDS_ATOM_BASE |
28168 | #define GDS_ATOM_BASE__BASE__SHIFT 0x0 |
28169 | #define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 |
28170 | #define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL |
28171 | #define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L |
28172 | //GDS_ATOM_SIZE |
28173 | #define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 |
28174 | #define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 |
28175 | #define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL |
28176 | #define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L |
28177 | //GDS_ATOM_OFFSET0 |
28178 | #define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 |
28179 | #define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 |
28180 | #define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL |
28181 | #define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L |
28182 | //GDS_ATOM_OFFSET1 |
28183 | #define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 |
28184 | #define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 |
28185 | #define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL |
28186 | #define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L |
28187 | //GDS_ATOM_DST |
28188 | #define GDS_ATOM_DST__DST__SHIFT 0x0 |
28189 | #define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL |
28190 | //GDS_ATOM_OP |
28191 | #define GDS_ATOM_OP__OP__SHIFT 0x0 |
28192 | #define GDS_ATOM_OP__UNUSED__SHIFT 0x8 |
28193 | #define GDS_ATOM_OP__OP_MASK 0x000000FFL |
28194 | #define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L |
28195 | //GDS_ATOM_SRC0 |
28196 | #define GDS_ATOM_SRC0__DATA__SHIFT 0x0 |
28197 | #define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL |
28198 | //GDS_ATOM_SRC0_U |
28199 | #define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 |
28200 | #define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL |
28201 | //GDS_ATOM_SRC1 |
28202 | #define GDS_ATOM_SRC1__DATA__SHIFT 0x0 |
28203 | #define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL |
28204 | //GDS_ATOM_SRC1_U |
28205 | #define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 |
28206 | #define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL |
28207 | //GDS_ATOM_READ0 |
28208 | #define GDS_ATOM_READ0__DATA__SHIFT 0x0 |
28209 | #define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL |
28210 | //GDS_ATOM_READ0_U |
28211 | #define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 |
28212 | #define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL |
28213 | //GDS_ATOM_READ1 |
28214 | #define GDS_ATOM_READ1__DATA__SHIFT 0x0 |
28215 | #define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL |
28216 | //GDS_ATOM_READ1_U |
28217 | #define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 |
28218 | #define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL |
28219 | //GDS_GWS_RESOURCE_CNTL |
28220 | #define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 |
28221 | #define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 |
28222 | #define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL |
28223 | #define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L |
28224 | //GDS_GWS_RESOURCE |
28225 | #define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 |
28226 | #define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 |
28227 | #define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd |
28228 | #define GDS_GWS_RESOURCE__DED__SHIFT 0xe |
28229 | #define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf |
28230 | #define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 |
28231 | #define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b |
28232 | #define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c |
28233 | #define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1d |
28234 | #define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1e |
28235 | #define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L |
28236 | #define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL |
28237 | #define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L |
28238 | #define GDS_GWS_RESOURCE__DED_MASK 0x00004000L |
28239 | #define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L |
28240 | #define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x07FF0000L |
28241 | #define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x08000000L |
28242 | #define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000L |
28243 | #define GDS_GWS_RESOURCE__HALTED_MASK 0x20000000L |
28244 | #define GDS_GWS_RESOURCE__UNUSED1_MASK 0xC0000000L |
28245 | //GDS_GWS_RESOURCE_CNT |
28246 | #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 |
28247 | #define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 |
28248 | #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL |
28249 | #define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L |
28250 | //GDS_OA_CNTL |
28251 | #define GDS_OA_CNTL__INDEX__SHIFT 0x0 |
28252 | #define GDS_OA_CNTL__UNUSED__SHIFT 0x4 |
28253 | #define GDS_OA_CNTL__INDEX_MASK 0x0000000FL |
28254 | #define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L |
28255 | //GDS_OA_COUNTER |
28256 | #define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 |
28257 | #define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL |
28258 | //GDS_OA_ADDRESS |
28259 | #define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 |
28260 | #define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x10 |
28261 | #define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x14 |
28262 | #define GDS_OA_ADDRESS__UNUSED__SHIFT 0x18 |
28263 | #define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e |
28264 | #define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f |
28265 | #define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL |
28266 | #define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x000F0000L |
28267 | #define GDS_OA_ADDRESS__CRAWLER_MASK 0x00F00000L |
28268 | #define GDS_OA_ADDRESS__UNUSED_MASK 0x3F000000L |
28269 | #define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L |
28270 | #define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L |
28271 | //GDS_OA_INCDEC |
28272 | #define GDS_OA_INCDEC__VALUE__SHIFT 0x0 |
28273 | #define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f |
28274 | #define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL |
28275 | #define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L |
28276 | //GDS_OA_RING_SIZE |
28277 | #define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 |
28278 | #define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL |
28279 | //SPI_CONFIG_CNTL_REMAP |
28280 | #define SPI_CONFIG_CNTL_REMAP__RESERVED__SHIFT 0x0 |
28281 | #define SPI_CONFIG_CNTL_REMAP__RESERVED_MASK 0xFFFFFFFFL |
28282 | //SPI_CONFIG_CNTL_1_REMAP |
28283 | #define SPI_CONFIG_CNTL_1_REMAP__RESERVED__SHIFT 0x0 |
28284 | #define SPI_CONFIG_CNTL_1_REMAP__RESERVED_MASK 0xFFFFFFFFL |
28285 | //SPI_CONFIG_CNTL_2_REMAP |
28286 | #define SPI_CONFIG_CNTL_2_REMAP__RESERVED__SHIFT 0x0 |
28287 | #define SPI_CONFIG_CNTL_2_REMAP__RESERVED_MASK 0xFFFFFFFFL |
28288 | //SPI_WAVE_LIMIT_CNTL_REMAP |
28289 | #define SPI_WAVE_LIMIT_CNTL_REMAP__RESERVED__SHIFT 0x0 |
28290 | #define SPI_WAVE_LIMIT_CNTL_REMAP__RESERVED_MASK 0xFFFFFFFFL |
28291 | |
28292 | |
28293 | // addressBlock: gc_cprs64dec |
28294 | //CP_MES_PRGRM_CNTR_START |
28295 | #define CP_MES_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
28296 | #define CP_MES_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL |
28297 | //CP_MES_INTR_ROUTINE_START |
28298 | #define CP_MES_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
28299 | #define CP_MES_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL |
28300 | //CP_MES_MTVEC_LO |
28301 | #define CP_MES_MTVEC_LO__ADDR_LO__SHIFT 0x0 |
28302 | #define CP_MES_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL |
28303 | //CP_MES_MTVEC_HI |
28304 | #define CP_MES_MTVEC_HI__ADDR_LO__SHIFT 0x0 |
28305 | #define CP_MES_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL |
28306 | //CP_MES_CNTL |
28307 | #define CP_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT 0x4 |
28308 | #define CP_MES_CNTL__MES_PIPE0_RESET__SHIFT 0x10 |
28309 | #define CP_MES_CNTL__MES_PIPE1_RESET__SHIFT 0x11 |
28310 | #define CP_MES_CNTL__MES_PIPE2_RESET__SHIFT 0x12 |
28311 | #define CP_MES_CNTL__MES_PIPE3_RESET__SHIFT 0x13 |
28312 | #define CP_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT 0x1a |
28313 | #define CP_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT 0x1b |
28314 | #define CP_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT 0x1c |
28315 | #define CP_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT 0x1d |
28316 | #define CP_MES_CNTL__MES_HALT__SHIFT 0x1e |
28317 | #define CP_MES_CNTL__MES_STEP__SHIFT 0x1f |
28318 | #define CP_MES_CNTL__MES_INVALIDATE_ICACHE_MASK 0x00000010L |
28319 | #define CP_MES_CNTL__MES_PIPE0_RESET_MASK 0x00010000L |
28320 | #define CP_MES_CNTL__MES_PIPE1_RESET_MASK 0x00020000L |
28321 | #define CP_MES_CNTL__MES_PIPE2_RESET_MASK 0x00040000L |
28322 | #define CP_MES_CNTL__MES_PIPE3_RESET_MASK 0x00080000L |
28323 | #define CP_MES_CNTL__MES_PIPE0_ACTIVE_MASK 0x04000000L |
28324 | #define CP_MES_CNTL__MES_PIPE1_ACTIVE_MASK 0x08000000L |
28325 | #define CP_MES_CNTL__MES_PIPE2_ACTIVE_MASK 0x10000000L |
28326 | #define CP_MES_CNTL__MES_PIPE3_ACTIVE_MASK 0x20000000L |
28327 | #define CP_MES_CNTL__MES_HALT_MASK 0x40000000L |
28328 | #define CP_MES_CNTL__MES_STEP_MASK 0x80000000L |
28329 | //CP_MES_PIPE_PRIORITY_CNTS |
28330 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
28331 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
28332 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
28333 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
28334 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
28335 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
28336 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
28337 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
28338 | //CP_MES_PIPE0_PRIORITY |
28339 | #define CP_MES_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
28340 | #define CP_MES_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
28341 | //CP_MES_PIPE1_PRIORITY |
28342 | #define CP_MES_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
28343 | #define CP_MES_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
28344 | //CP_MES_PIPE2_PRIORITY |
28345 | #define CP_MES_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
28346 | #define CP_MES_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
28347 | //CP_MES_PIPE3_PRIORITY |
28348 | #define CP_MES_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 |
28349 | #define CP_MES_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L |
28350 | //CP_MES_HEADER_DUMP |
28351 | #define 0x0 |
28352 | #define 0xFFFFFFFFL |
28353 | //CP_MES_MIE_LO |
28354 | #define CP_MES_MIE_LO__MES_INT__SHIFT 0x0 |
28355 | #define CP_MES_MIE_LO__MES_INT_MASK 0xFFFFFFFFL |
28356 | //CP_MES_MIE_HI |
28357 | #define CP_MES_MIE_HI__MES_INT__SHIFT 0x0 |
28358 | #define CP_MES_MIE_HI__MES_INT_MASK 0xFFFFFFFFL |
28359 | //CP_MES_INTERRUPT |
28360 | #define CP_MES_INTERRUPT__MES_INT__SHIFT 0x0 |
28361 | #define CP_MES_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x10 |
28362 | #define CP_MES_INTERRUPT__MES_INT_MASK 0x0000FFFFL |
28363 | #define CP_MES_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFF0000L |
28364 | //CP_MES_SCRATCH_INDEX |
28365 | #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 |
28366 | #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f |
28367 | #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL |
28368 | #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L |
28369 | //CP_MES_SCRATCH_DATA |
28370 | #define CP_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 |
28371 | #define CP_MES_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL |
28372 | //CP_MES_INSTR_PNTR |
28373 | #define CP_MES_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
28374 | #define CP_MES_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL |
28375 | //CP_MES_MSCRATCH_HI |
28376 | #define CP_MES_MSCRATCH_HI__DATA__SHIFT 0x0 |
28377 | #define CP_MES_MSCRATCH_HI__DATA_MASK 0xFFFFFFFFL |
28378 | //CP_MES_MSCRATCH_LO |
28379 | #define CP_MES_MSCRATCH_LO__DATA__SHIFT 0x0 |
28380 | #define CP_MES_MSCRATCH_LO__DATA_MASK 0xFFFFFFFFL |
28381 | //CP_MES_MSTATUS_LO |
28382 | #define CP_MES_MSTATUS_LO__STATUS_LO__SHIFT 0x0 |
28383 | #define CP_MES_MSTATUS_LO__STATUS_LO_MASK 0xFFFFFFFFL |
28384 | //CP_MES_MSTATUS_HI |
28385 | #define CP_MES_MSTATUS_HI__STATUS_HI__SHIFT 0x0 |
28386 | #define CP_MES_MSTATUS_HI__STATUS_HI_MASK 0xFFFFFFFFL |
28387 | //CP_MES_MEPC_LO |
28388 | #define CP_MES_MEPC_LO__MEPC_LO__SHIFT 0x0 |
28389 | #define CP_MES_MEPC_LO__MEPC_LO_MASK 0xFFFFFFFFL |
28390 | //CP_MES_MEPC_HI |
28391 | #define CP_MES_MEPC_HI__MEPC_HI__SHIFT 0x0 |
28392 | #define CP_MES_MEPC_HI__MEPC_HI_MASK 0xFFFFFFFFL |
28393 | //CP_MES_MCAUSE_LO |
28394 | #define CP_MES_MCAUSE_LO__CAUSE_LO__SHIFT 0x0 |
28395 | #define CP_MES_MCAUSE_LO__CAUSE_LO_MASK 0xFFFFFFFFL |
28396 | //CP_MES_MCAUSE_HI |
28397 | #define CP_MES_MCAUSE_HI__CAUSE_HI__SHIFT 0x0 |
28398 | #define CP_MES_MCAUSE_HI__CAUSE_HI_MASK 0xFFFFFFFFL |
28399 | //CP_MES_MBADADDR_LO |
28400 | #define CP_MES_MBADADDR_LO__ADDR_LO__SHIFT 0x0 |
28401 | #define CP_MES_MBADADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL |
28402 | //CP_MES_MBADADDR_HI |
28403 | #define CP_MES_MBADADDR_HI__ADDR_HI__SHIFT 0x0 |
28404 | #define CP_MES_MBADADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL |
28405 | //CP_MES_MIP_LO |
28406 | #define CP_MES_MIP_LO__MIP_LO__SHIFT 0x0 |
28407 | #define CP_MES_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL |
28408 | //CP_MES_MIP_HI |
28409 | #define CP_MES_MIP_HI__MIP_HI__SHIFT 0x0 |
28410 | #define CP_MES_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL |
28411 | //CP_MES_MCYCLE_LO |
28412 | #define CP_MES_MCYCLE_LO__CYCLE_LO__SHIFT 0x0 |
28413 | #define CP_MES_MCYCLE_LO__CYCLE_LO_MASK 0xFFFFFFFFL |
28414 | //CP_MES_MCYCLE_HI |
28415 | #define CP_MES_MCYCLE_HI__CYCLE_HI__SHIFT 0x0 |
28416 | #define CP_MES_MCYCLE_HI__CYCLE_HI_MASK 0xFFFFFFFFL |
28417 | //CP_MES_MTIME_LO |
28418 | #define CP_MES_MTIME_LO__TIME_LO__SHIFT 0x0 |
28419 | #define CP_MES_MTIME_LO__TIME_LO_MASK 0xFFFFFFFFL |
28420 | //CP_MES_MTIME_HI |
28421 | #define CP_MES_MTIME_HI__TIME_HI__SHIFT 0x0 |
28422 | #define CP_MES_MTIME_HI__TIME_HI_MASK 0xFFFFFFFFL |
28423 | //CP_MES_MINSTRET_LO |
28424 | #define CP_MES_MINSTRET_LO__INSTRET_LO__SHIFT 0x0 |
28425 | #define CP_MES_MINSTRET_LO__INSTRET_LO_MASK 0xFFFFFFFFL |
28426 | //CP_MES_MINSTRET_HI |
28427 | #define CP_MES_MINSTRET_HI__INSTRET_HI__SHIFT 0x0 |
28428 | #define CP_MES_MINSTRET_HI__INSTRET_HI_MASK 0xFFFFFFFFL |
28429 | //CP_MES_MISA_LO |
28430 | #define CP_MES_MISA_LO__MISA_LO__SHIFT 0x0 |
28431 | #define CP_MES_MISA_LO__MISA_LO_MASK 0xFFFFFFFFL |
28432 | //CP_MES_MISA_HI |
28433 | #define CP_MES_MISA_HI__MISA_HI__SHIFT 0x0 |
28434 | #define CP_MES_MISA_HI__MISA_HI_MASK 0xFFFFFFFFL |
28435 | //CP_MES_MVENDORID_LO |
28436 | #define CP_MES_MVENDORID_LO__MVENDORID_LO__SHIFT 0x0 |
28437 | #define CP_MES_MVENDORID_LO__MVENDORID_LO_MASK 0xFFFFFFFFL |
28438 | //CP_MES_MVENDORID_HI |
28439 | #define CP_MES_MVENDORID_HI__MVENDORID_HI__SHIFT 0x0 |
28440 | #define CP_MES_MVENDORID_HI__MVENDORID_HI_MASK 0xFFFFFFFFL |
28441 | //CP_MES_MARCHID_LO |
28442 | #define CP_MES_MARCHID_LO__MARCHID_LO__SHIFT 0x0 |
28443 | #define CP_MES_MARCHID_LO__MARCHID_LO_MASK 0xFFFFFFFFL |
28444 | //CP_MES_MARCHID_HI |
28445 | #define CP_MES_MARCHID_HI__MARCHID_HI__SHIFT 0x0 |
28446 | #define CP_MES_MARCHID_HI__MARCHID_HI_MASK 0xFFFFFFFFL |
28447 | //CP_MES_MIMPID_LO |
28448 | #define CP_MES_MIMPID_LO__MIMPID_LO__SHIFT 0x0 |
28449 | #define CP_MES_MIMPID_LO__MIMPID_LO_MASK 0xFFFFFFFFL |
28450 | //CP_MES_MIMPID_HI |
28451 | #define CP_MES_MIMPID_HI__MIMPID_HI__SHIFT 0x0 |
28452 | #define CP_MES_MIMPID_HI__MIMPID_HI_MASK 0xFFFFFFFFL |
28453 | //CP_MES_MHARTID_LO |
28454 | #define CP_MES_MHARTID_LO__MHARTID_LO__SHIFT 0x0 |
28455 | #define CP_MES_MHARTID_LO__MHARTID_LO_MASK 0xFFFFFFFFL |
28456 | //CP_MES_MHARTID_HI |
28457 | #define CP_MES_MHARTID_HI__MHARTID_HI__SHIFT 0x0 |
28458 | #define CP_MES_MHARTID_HI__MHARTID_HI_MASK 0xFFFFFFFFL |
28459 | //CP_MES_DC_BASE_CNTL |
28460 | #define CP_MES_DC_BASE_CNTL__VMID__SHIFT 0x0 |
28461 | #define CP_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
28462 | #define CP_MES_DC_BASE_CNTL__VMID_MASK 0x0000000FL |
28463 | #define CP_MES_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
28464 | //CP_MES_DC_OP_CNTL |
28465 | #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 |
28466 | #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 |
28467 | #define CP_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 |
28468 | #define CP_MES_DC_OP_CNTL__BYPASS_UNCACHED__SHIFT 0x3 |
28469 | #define CP_MES_DC_OP_CNTL__PRIME_DCACHE__SHIFT 0x4 |
28470 | #define CP_MES_DC_OP_CNTL__DCACHE_PRIMED__SHIFT 0x5 |
28471 | #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L |
28472 | #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L |
28473 | #define CP_MES_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L |
28474 | #define CP_MES_DC_OP_CNTL__BYPASS_UNCACHED_MASK 0x00000008L |
28475 | #define CP_MES_DC_OP_CNTL__PRIME_DCACHE_MASK 0x00000010L |
28476 | #define CP_MES_DC_OP_CNTL__DCACHE_PRIMED_MASK 0x00000020L |
28477 | //CP_MES_MTIMECMP_LO |
28478 | #define CP_MES_MTIMECMP_LO__TIME_LO__SHIFT 0x0 |
28479 | #define CP_MES_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL |
28480 | //CP_MES_MTIMECMP_HI |
28481 | #define CP_MES_MTIMECMP_HI__TIME_HI__SHIFT 0x0 |
28482 | #define CP_MES_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL |
28483 | //CP_MES_PROCESS_QUANTUM_PIPE0 |
28484 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION__SHIFT 0x0 |
28485 | #define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED__SHIFT 0x1c |
28486 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE__SHIFT 0x1d |
28487 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN__SHIFT 0x1f |
28488 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION_MASK 0x0FFFFFFFL |
28489 | #define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED_MASK 0x10000000L |
28490 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE_MASK 0x60000000L |
28491 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN_MASK 0x80000000L |
28492 | //CP_MES_PROCESS_QUANTUM_PIPE1 |
28493 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION__SHIFT 0x0 |
28494 | #define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED__SHIFT 0x1c |
28495 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE__SHIFT 0x1d |
28496 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN__SHIFT 0x1f |
28497 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION_MASK 0x0FFFFFFFL |
28498 | #define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED_MASK 0x10000000L |
28499 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE_MASK 0x60000000L |
28500 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN_MASK 0x80000000L |
28501 | //CP_MES_DOORBELL_CONTROL1 |
28502 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT 0x2 |
28503 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT 0x1e |
28504 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT__SHIFT 0x1f |
28505 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
28506 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK 0x40000000L |
28507 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK 0x80000000L |
28508 | //CP_MES_DOORBELL_CONTROL2 |
28509 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT 0x2 |
28510 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT 0x1e |
28511 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT__SHIFT 0x1f |
28512 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
28513 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK 0x40000000L |
28514 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK 0x80000000L |
28515 | //CP_MES_DOORBELL_CONTROL3 |
28516 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT 0x2 |
28517 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT 0x1e |
28518 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT__SHIFT 0x1f |
28519 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
28520 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK 0x40000000L |
28521 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK 0x80000000L |
28522 | //CP_MES_DOORBELL_CONTROL4 |
28523 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT 0x2 |
28524 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT 0x1e |
28525 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT__SHIFT 0x1f |
28526 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
28527 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK 0x40000000L |
28528 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK 0x80000000L |
28529 | //CP_MES_DOORBELL_CONTROL5 |
28530 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT 0x2 |
28531 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT 0x1e |
28532 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT__SHIFT 0x1f |
28533 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
28534 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK 0x40000000L |
28535 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK 0x80000000L |
28536 | //CP_MES_DOORBELL_CONTROL6 |
28537 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET__SHIFT 0x2 |
28538 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN__SHIFT 0x1e |
28539 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT__SHIFT 0x1f |
28540 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
28541 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN_MASK 0x40000000L |
28542 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT_MASK 0x80000000L |
28543 | //CP_MES_GP0_LO |
28544 | #define CP_MES_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 |
28545 | #define CP_MES_GP0_LO__DATA__SHIFT 0x1 |
28546 | #define CP_MES_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L |
28547 | #define CP_MES_GP0_LO__DATA_MASK 0xFFFFFFFEL |
28548 | //CP_MES_GP0_HI |
28549 | #define CP_MES_GP0_HI__M_RET_ADDR__SHIFT 0x0 |
28550 | #define CP_MES_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL |
28551 | //CP_MES_GP1_LO |
28552 | #define CP_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 |
28553 | #define CP_MES_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL |
28554 | //CP_MES_GP1_HI |
28555 | #define CP_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 |
28556 | #define CP_MES_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL |
28557 | //CP_MES_GP2_LO |
28558 | #define CP_MES_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 |
28559 | #define CP_MES_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL |
28560 | //CP_MES_GP2_HI |
28561 | #define CP_MES_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 |
28562 | #define CP_MES_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL |
28563 | //CP_MES_GP3_LO |
28564 | #define CP_MES_GP3_LO__DATA__SHIFT 0x0 |
28565 | #define CP_MES_GP3_LO__DATA_MASK 0xFFFFFFFFL |
28566 | //CP_MES_GP3_HI |
28567 | #define CP_MES_GP3_HI__DATA__SHIFT 0x0 |
28568 | #define CP_MES_GP3_HI__DATA_MASK 0xFFFFFFFFL |
28569 | //CP_MES_GP4_LO |
28570 | #define CP_MES_GP4_LO__DATA__SHIFT 0x0 |
28571 | #define CP_MES_GP4_LO__DATA_MASK 0xFFFFFFFFL |
28572 | //CP_MES_GP4_HI |
28573 | #define CP_MES_GP4_HI__DATA__SHIFT 0x0 |
28574 | #define CP_MES_GP4_HI__DATA_MASK 0xFFFFFFFFL |
28575 | //CP_MES_GP5_LO |
28576 | #define CP_MES_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 |
28577 | #define CP_MES_GP5_LO__DATA__SHIFT 0x1 |
28578 | #define CP_MES_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L |
28579 | #define CP_MES_GP5_LO__DATA_MASK 0xFFFFFFFEL |
28580 | //CP_MES_GP5_HI |
28581 | #define CP_MES_GP5_HI__M_RET_ADDR__SHIFT 0x0 |
28582 | #define CP_MES_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL |
28583 | //CP_MES_GP6_LO |
28584 | #define CP_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 |
28585 | #define CP_MES_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL |
28586 | //CP_MES_GP6_HI |
28587 | #define CP_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 |
28588 | #define CP_MES_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL |
28589 | //CP_MES_GP7_LO |
28590 | #define CP_MES_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 |
28591 | #define CP_MES_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL |
28592 | //CP_MES_GP7_HI |
28593 | #define CP_MES_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 |
28594 | #define CP_MES_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL |
28595 | //CP_MES_GP8_LO |
28596 | #define CP_MES_GP8_LO__DATA__SHIFT 0x0 |
28597 | #define CP_MES_GP8_LO__DATA_MASK 0xFFFFFFFFL |
28598 | //CP_MES_GP8_HI |
28599 | #define CP_MES_GP8_HI__DATA__SHIFT 0x0 |
28600 | #define CP_MES_GP8_HI__DATA_MASK 0xFFFFFFFFL |
28601 | //CP_MES_GP9_LO |
28602 | #define CP_MES_GP9_LO__DATA__SHIFT 0x0 |
28603 | #define CP_MES_GP9_LO__DATA_MASK 0xFFFFFFFFL |
28604 | //CP_MES_GP9_HI |
28605 | #define CP_MES_GP9_HI__DATA__SHIFT 0x0 |
28606 | #define CP_MES_GP9_HI__DATA_MASK 0xFFFFFFFFL |
28607 | //CP_MES_DM_INDEX_ADDR |
28608 | #define CP_MES_DM_INDEX_ADDR__ADDR__SHIFT 0x0 |
28609 | #define CP_MES_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL |
28610 | //CP_MES_DM_INDEX_DATA |
28611 | #define CP_MES_DM_INDEX_DATA__DATA__SHIFT 0x0 |
28612 | #define CP_MES_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL |
28613 | //CP_MES_DMCONTROL |
28614 | #define CP_MES_DMCONTROL__CONTROL__SHIFT 0x0 |
28615 | #define CP_MES_DMCONTROL__CONTROL_MASK 0xFFFFFFFFL |
28616 | //CP_MES_DMINFO |
28617 | #define CP_MES_DMINFO__INFO__SHIFT 0x0 |
28618 | #define CP_MES_DMINFO__INFO_MASK 0xFFFFFFFFL |
28619 | //CP_MES_SETHALTNOTIFICATION |
28620 | #define CP_MES_SETHALTNOTIFICATION__SETHALT__SHIFT 0x0 |
28621 | #define CP_MES_SETHALTNOTIFICATION__SETHALT_MASK 0xFFFFFFFFL |
28622 | //CP_MES_TSELCT_LOW |
28623 | #define CP_MES_TSELCT_LOW__TSELECT__SHIFT 0x0 |
28624 | #define CP_MES_TSELCT_LOW__TSELECT_MASK 0xFFFFFFFFL |
28625 | //CP_MES_TSELCT_HIGH |
28626 | #define CP_MES_TSELCT_HIGH__TSELECT__SHIFT 0x0 |
28627 | #define CP_MES_TSELCT_HIGH__TSELECT_MASK 0xFFFFFFFFL |
28628 | //CP_MES_TDATA1_LOW |
28629 | #define CP_MES_TDATA1_LOW__DATA__SHIFT 0x0 |
28630 | #define CP_MES_TDATA1_LOW__DATA_MASK 0xFFFFFFFFL |
28631 | //CP_MES_TDATA1_HIGH |
28632 | #define CP_MES_TDATA1_HIGH__DATA__SHIFT 0x0 |
28633 | #define CP_MES_TDATA1_HIGH__DATA_MASK 0xFFFFFFFFL |
28634 | //CP_MES_TDATA2_LOW |
28635 | #define CP_MES_TDATA2_LOW__DATA__SHIFT 0x0 |
28636 | #define CP_MES_TDATA2_LOW__DATA_MASK 0xFFFFFFFFL |
28637 | //CP_MES_TDATA2_HIGH |
28638 | #define CP_MES_TDATA2_HIGH__DATA__SHIFT 0x0 |
28639 | #define CP_MES_TDATA2_HIGH__DATA_MASK 0xFFFFFFFFL |
28640 | //CP_MES_TDATA3_LOW |
28641 | #define CP_MES_TDATA3_LOW__DATA__SHIFT 0x0 |
28642 | #define CP_MES_TDATA3_LOW__DATA_MASK 0xFFFFFFFFL |
28643 | //CP_MES_TDATA3_HIH |
28644 | #define CP_MES_TDATA3_HIH__DATA__SHIFT 0x0 |
28645 | #define CP_MES_TDATA3_HIH__DATA_MASK 0xFFFFFFFFL |
28646 | //CP_MES_DCSR |
28647 | #define CP_MES_DCSR__CSR__SHIFT 0x0 |
28648 | #define CP_MES_DCSR__CSR_MASK 0xFFFFFFFFL |
28649 | //CP_MES_DPC_LOW |
28650 | #define CP_MES_DPC_LOW__INSTR_PNTR__SHIFT 0x0 |
28651 | #define CP_MES_DPC_LOW__INSTR_PNTR_MASK 0xFFFFFFFFL |
28652 | //CP_MES_DPC_HIGH |
28653 | #define CP_MES_DPC_HIGH__INSTR_PNTR__SHIFT 0x0 |
28654 | #define CP_MES_DPC_HIGH__INSTR_PNTR_MASK 0xFFFFFFFFL |
28655 | //CP_MES_DSCRATCH_LOW |
28656 | #define CP_MES_DSCRATCH_LOW__DATA__SHIFT 0x0 |
28657 | #define CP_MES_DSCRATCH_LOW__DATA_MASK 0xFFFFFFFFL |
28658 | //CP_MES_DSCRATCH_HIGH |
28659 | #define CP_MES_DSCRATCH_HIGH__DATA__SHIFT 0x0 |
28660 | #define CP_MES_DSCRATCH_HIGH__DATA_MASK 0xFFFFFFFFL |
28661 | //CP_MES_PERFCOUNT_CNTL |
28662 | #define CP_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 |
28663 | #define CP_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x00000007L |
28664 | |
28665 | |
28666 | // addressBlock: gc_gusdec |
28667 | //GUS_IO_RD_COMBINE_FLUSH |
28668 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
28669 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
28670 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
28671 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
28672 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10 |
28673 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14 |
28674 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
28675 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
28676 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
28677 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
28678 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L |
28679 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L |
28680 | //GUS_IO_WR_COMBINE_FLUSH |
28681 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
28682 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
28683 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
28684 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
28685 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10 |
28686 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14 |
28687 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
28688 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
28689 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
28690 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
28691 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L |
28692 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L |
28693 | //GUS_IO_RD_PRI_AGE_RATE |
28694 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0 |
28695 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3 |
28696 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6 |
28697 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9 |
28698 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc |
28699 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf |
28700 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L |
28701 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L |
28702 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L |
28703 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L |
28704 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L |
28705 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L |
28706 | //GUS_IO_WR_PRI_AGE_RATE |
28707 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0 |
28708 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3 |
28709 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6 |
28710 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9 |
28711 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc |
28712 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf |
28713 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L |
28714 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L |
28715 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L |
28716 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L |
28717 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L |
28718 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L |
28719 | //GUS_IO_RD_PRI_AGE_COEFF |
28720 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0 |
28721 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3 |
28722 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6 |
28723 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9 |
28724 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc |
28725 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf |
28726 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L |
28727 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L |
28728 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L |
28729 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L |
28730 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L |
28731 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L |
28732 | //GUS_IO_WR_PRI_AGE_COEFF |
28733 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0 |
28734 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3 |
28735 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6 |
28736 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9 |
28737 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc |
28738 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf |
28739 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L |
28740 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L |
28741 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L |
28742 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L |
28743 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L |
28744 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L |
28745 | //GUS_IO_RD_PRI_QUEUING |
28746 | #define GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
28747 | #define GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
28748 | #define GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
28749 | #define GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
28750 | #define GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc |
28751 | #define GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf |
28752 | #define GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
28753 | #define GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
28754 | #define GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
28755 | #define GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
28756 | #define GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L |
28757 | #define GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L |
28758 | //GUS_IO_WR_PRI_QUEUING |
28759 | #define GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
28760 | #define GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
28761 | #define GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
28762 | #define GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
28763 | #define GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc |
28764 | #define GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf |
28765 | #define GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
28766 | #define GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
28767 | #define GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
28768 | #define GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
28769 | #define GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L |
28770 | #define GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L |
28771 | //GUS_IO_RD_PRI_FIXED |
28772 | #define GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
28773 | #define GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
28774 | #define GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
28775 | #define GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
28776 | #define GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc |
28777 | #define GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf |
28778 | #define GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
28779 | #define GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
28780 | #define GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
28781 | #define GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
28782 | #define GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L |
28783 | #define GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L |
28784 | //GUS_IO_WR_PRI_FIXED |
28785 | #define GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
28786 | #define GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
28787 | #define GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
28788 | #define GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
28789 | #define GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc |
28790 | #define GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf |
28791 | #define GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
28792 | #define GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
28793 | #define GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
28794 | #define GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
28795 | #define GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L |
28796 | #define GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L |
28797 | //GUS_IO_RD_PRI_URGENCY_COEFF |
28798 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
28799 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
28800 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
28801 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
28802 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc |
28803 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf |
28804 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
28805 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
28806 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
28807 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
28808 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L |
28809 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L |
28810 | //GUS_IO_WR_PRI_URGENCY_COEFF |
28811 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
28812 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
28813 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
28814 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
28815 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc |
28816 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf |
28817 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
28818 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
28819 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
28820 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
28821 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L |
28822 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L |
28823 | //GUS_IO_RD_PRI_URGENCY_MODE |
28824 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0 |
28825 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1 |
28826 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2 |
28827 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3 |
28828 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4 |
28829 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5 |
28830 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L |
28831 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L |
28832 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L |
28833 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L |
28834 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L |
28835 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L |
28836 | //GUS_IO_WR_PRI_URGENCY_MODE |
28837 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0 |
28838 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1 |
28839 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2 |
28840 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3 |
28841 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4 |
28842 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5 |
28843 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L |
28844 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L |
28845 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L |
28846 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L |
28847 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L |
28848 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L |
28849 | //GUS_IO_RD_PRI_QUANT_PRI1 |
28850 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
28851 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
28852 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
28853 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
28854 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
28855 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
28856 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
28857 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
28858 | //GUS_IO_RD_PRI_QUANT_PRI2 |
28859 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
28860 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
28861 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
28862 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
28863 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
28864 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
28865 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
28866 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
28867 | //GUS_IO_RD_PRI_QUANT_PRI3 |
28868 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
28869 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
28870 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
28871 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
28872 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
28873 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
28874 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
28875 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
28876 | //GUS_IO_RD_PRI_QUANT_PRI4 |
28877 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0 |
28878 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8 |
28879 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10 |
28880 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18 |
28881 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL |
28882 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L |
28883 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L |
28884 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L |
28885 | //GUS_IO_WR_PRI_QUANT_PRI1 |
28886 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
28887 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
28888 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
28889 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
28890 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
28891 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
28892 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
28893 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
28894 | //GUS_IO_WR_PRI_QUANT_PRI2 |
28895 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
28896 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
28897 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
28898 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
28899 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
28900 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
28901 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
28902 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
28903 | //GUS_IO_WR_PRI_QUANT_PRI3 |
28904 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
28905 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
28906 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
28907 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
28908 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
28909 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
28910 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
28911 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
28912 | //GUS_IO_WR_PRI_QUANT_PRI4 |
28913 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0 |
28914 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8 |
28915 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10 |
28916 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18 |
28917 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL |
28918 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L |
28919 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L |
28920 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L |
28921 | //GUS_IO_RD_PRI_QUANT1_PRI1 |
28922 | #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0 |
28923 | #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8 |
28924 | #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL |
28925 | #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L |
28926 | //GUS_IO_RD_PRI_QUANT1_PRI2 |
28927 | #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0 |
28928 | #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8 |
28929 | #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL |
28930 | #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L |
28931 | //GUS_IO_RD_PRI_QUANT1_PRI3 |
28932 | #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0 |
28933 | #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8 |
28934 | #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL |
28935 | #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L |
28936 | //GUS_IO_RD_PRI_QUANT1_PRI4 |
28937 | #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0 |
28938 | #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8 |
28939 | #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL |
28940 | #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L |
28941 | //GUS_IO_WR_PRI_QUANT1_PRI1 |
28942 | #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0 |
28943 | #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8 |
28944 | #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL |
28945 | #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L |
28946 | //GUS_IO_WR_PRI_QUANT1_PRI2 |
28947 | #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0 |
28948 | #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8 |
28949 | #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL |
28950 | #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L |
28951 | //GUS_IO_WR_PRI_QUANT1_PRI3 |
28952 | #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0 |
28953 | #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8 |
28954 | #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL |
28955 | #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L |
28956 | //GUS_IO_WR_PRI_QUANT1_PRI4 |
28957 | #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0 |
28958 | #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8 |
28959 | #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL |
28960 | #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L |
28961 | //GUS_DRAM_COMBINE_FLUSH |
28962 | #define GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
28963 | #define GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
28964 | #define GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
28965 | #define GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
28966 | #define GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10 |
28967 | #define GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14 |
28968 | #define GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
28969 | #define GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
28970 | #define GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
28971 | #define GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
28972 | #define GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L |
28973 | #define GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L |
28974 | //GUS_DRAM_COMBINE_RD_WR_EN |
28975 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER__SHIFT 0x0 |
28976 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER__SHIFT 0x2 |
28977 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER__SHIFT 0x4 |
28978 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER__SHIFT 0x6 |
28979 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER__SHIFT 0x8 |
28980 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER__SHIFT 0xa |
28981 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER_MASK 0x00000003L |
28982 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER_MASK 0x0000000CL |
28983 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER_MASK 0x00000030L |
28984 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER_MASK 0x000000C0L |
28985 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER_MASK 0x00000300L |
28986 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER_MASK 0x00000C00L |
28987 | //GUS_DRAM_PRI_AGE_RATE |
28988 | #define GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0 |
28989 | #define GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3 |
28990 | #define GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6 |
28991 | #define GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9 |
28992 | #define GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc |
28993 | #define GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf |
28994 | #define GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L |
28995 | #define GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L |
28996 | #define GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L |
28997 | #define GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L |
28998 | #define GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L |
28999 | #define GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L |
29000 | //GUS_DRAM_PRI_AGE_COEFF |
29001 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0 |
29002 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3 |
29003 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6 |
29004 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9 |
29005 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc |
29006 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf |
29007 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L |
29008 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L |
29009 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L |
29010 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L |
29011 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L |
29012 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L |
29013 | //GUS_DRAM_PRI_QUEUING |
29014 | #define GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
29015 | #define GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
29016 | #define GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
29017 | #define GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
29018 | #define GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc |
29019 | #define GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf |
29020 | #define GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
29021 | #define GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
29022 | #define GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
29023 | #define GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
29024 | #define GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L |
29025 | #define GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L |
29026 | //GUS_DRAM_PRI_FIXED |
29027 | #define GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
29028 | #define GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
29029 | #define GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
29030 | #define GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
29031 | #define GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc |
29032 | #define GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf |
29033 | #define GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
29034 | #define GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
29035 | #define GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
29036 | #define GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
29037 | #define GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L |
29038 | #define GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L |
29039 | //GUS_DRAM_PRI_URGENCY_COEFF |
29040 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
29041 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
29042 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
29043 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
29044 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc |
29045 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf |
29046 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
29047 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
29048 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
29049 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
29050 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L |
29051 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L |
29052 | //GUS_DRAM_PRI_URGENCY_MODE |
29053 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0 |
29054 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1 |
29055 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2 |
29056 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3 |
29057 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4 |
29058 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5 |
29059 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L |
29060 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L |
29061 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L |
29062 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L |
29063 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L |
29064 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L |
29065 | //GUS_DRAM_PRI_QUANT_PRI1 |
29066 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
29067 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
29068 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
29069 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
29070 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
29071 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
29072 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
29073 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
29074 | //GUS_DRAM_PRI_QUANT_PRI2 |
29075 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
29076 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
29077 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
29078 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
29079 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
29080 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
29081 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
29082 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
29083 | //GUS_DRAM_PRI_QUANT_PRI3 |
29084 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
29085 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
29086 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
29087 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
29088 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
29089 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
29090 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
29091 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
29092 | //GUS_DRAM_PRI_QUANT_PRI4 |
29093 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0 |
29094 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8 |
29095 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10 |
29096 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18 |
29097 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL |
29098 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L |
29099 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L |
29100 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L |
29101 | //GUS_DRAM_PRI_QUANT_PRI5 |
29102 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD__SHIFT 0x0 |
29103 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD__SHIFT 0x8 |
29104 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD__SHIFT 0x10 |
29105 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD__SHIFT 0x18 |
29106 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD_MASK 0x000000FFL |
29107 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD_MASK 0x0000FF00L |
29108 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD_MASK 0x00FF0000L |
29109 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD_MASK 0xFF000000L |
29110 | //GUS_DRAM_PRI_QUANT1_PRI1 |
29111 | #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0 |
29112 | #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8 |
29113 | #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL |
29114 | #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L |
29115 | //GUS_DRAM_PRI_QUANT1_PRI2 |
29116 | #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0 |
29117 | #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8 |
29118 | #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL |
29119 | #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L |
29120 | //GUS_DRAM_PRI_QUANT1_PRI3 |
29121 | #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0 |
29122 | #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8 |
29123 | #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL |
29124 | #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L |
29125 | //GUS_DRAM_PRI_QUANT1_PRI4 |
29126 | #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0 |
29127 | #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8 |
29128 | #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL |
29129 | #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L |
29130 | //GUS_DRAM_PRI_QUANT1_PRI5 |
29131 | #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD__SHIFT 0x0 |
29132 | #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD__SHIFT 0x8 |
29133 | #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD_MASK 0x000000FFL |
29134 | #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD_MASK 0x0000FF00L |
29135 | //GUS_IO_GROUP_BURST |
29136 | #define GUS_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 |
29137 | #define GUS_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 |
29138 | #define GUS_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 |
29139 | #define GUS_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 |
29140 | #define GUS_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
29141 | #define GUS_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
29142 | #define GUS_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
29143 | #define GUS_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
29144 | //GUS_DRAM_GROUP_BURST |
29145 | #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO__SHIFT 0x0 |
29146 | #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI__SHIFT 0x8 |
29147 | #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO_MASK 0x000000FFL |
29148 | #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI_MASK 0x0000FF00L |
29149 | //GUS_SDP_ARB_FINAL |
29150 | #define GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT__SHIFT 0x0 |
29151 | #define GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x5 |
29152 | #define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa |
29153 | #define GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf |
29154 | #define GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x11 |
29155 | #define GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x12 |
29156 | #define GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT_MASK 0x0000001FL |
29157 | #define GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x000003E0L |
29158 | #define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L |
29159 | #define GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L |
29160 | #define GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x00020000L |
29161 | #define GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x00040000L |
29162 | //GUS_SDP_QOS_VC_PRIORITY |
29163 | #define GUS_SDP_QOS_VC_PRIORITY__VC2_IORD__SHIFT 0x0 |
29164 | #define GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR__SHIFT 0x4 |
29165 | #define GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM__SHIFT 0x8 |
29166 | #define GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM__SHIFT 0xc |
29167 | #define GUS_SDP_QOS_VC_PRIORITY__VC2_IORD_MASK 0x0000000FL |
29168 | #define GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR_MASK 0x000000F0L |
29169 | #define GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM_MASK 0x00000F00L |
29170 | #define GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM_MASK 0x0000F000L |
29171 | //GUS_SDP_CREDITS |
29172 | #define GUS_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 |
29173 | #define GUS_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 |
29174 | #define GUS_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 |
29175 | #define GUS_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL |
29176 | #define GUS_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L |
29177 | #define GUS_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L |
29178 | //GUS_SDP_TAG_RESERVE0 |
29179 | #define GUS_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 |
29180 | #define GUS_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 |
29181 | #define GUS_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 |
29182 | #define GUS_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 |
29183 | #define GUS_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL |
29184 | #define GUS_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L |
29185 | #define GUS_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L |
29186 | #define GUS_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L |
29187 | //GUS_SDP_TAG_RESERVE1 |
29188 | #define GUS_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 |
29189 | #define GUS_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 |
29190 | #define GUS_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 |
29191 | #define GUS_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 |
29192 | #define GUS_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL |
29193 | #define GUS_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L |
29194 | #define GUS_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L |
29195 | #define GUS_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L |
29196 | //GUS_SDP_VCC_RESERVE0 |
29197 | #define GUS_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
29198 | #define GUS_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
29199 | #define GUS_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc |
29200 | #define GUS_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
29201 | #define GUS_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
29202 | #define GUS_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
29203 | #define GUS_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
29204 | #define GUS_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
29205 | #define GUS_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
29206 | #define GUS_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
29207 | //GUS_SDP_VCC_RESERVE1 |
29208 | #define GUS_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
29209 | #define GUS_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
29210 | #define GUS_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc |
29211 | #define GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
29212 | #define GUS_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
29213 | #define GUS_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
29214 | #define GUS_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
29215 | #define GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
29216 | //GUS_SDP_VCD_RESERVE0 |
29217 | #define GUS_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
29218 | #define GUS_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
29219 | #define GUS_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc |
29220 | #define GUS_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
29221 | #define GUS_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
29222 | #define GUS_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
29223 | #define GUS_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
29224 | #define GUS_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
29225 | #define GUS_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
29226 | #define GUS_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
29227 | //GUS_SDP_VCD_RESERVE1 |
29228 | #define GUS_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
29229 | #define GUS_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
29230 | #define GUS_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc |
29231 | #define GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
29232 | #define GUS_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
29233 | #define GUS_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
29234 | #define GUS_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
29235 | #define GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
29236 | //GUS_SDP_REQ_CNTL |
29237 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 |
29238 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 |
29239 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 |
29240 | #define GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 |
29241 | #define GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 |
29242 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L |
29243 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L |
29244 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L |
29245 | #define GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L |
29246 | #define GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L |
29247 | //GUS_MISC |
29248 | #define GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB__SHIFT 0x0 |
29249 | #define GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x1 |
29250 | #define GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x2 |
29251 | #define GUS_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x3 |
29252 | #define GUS_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x4 |
29253 | #define GUS_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x6 |
29254 | #define GUS_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x8 |
29255 | #define GUS_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xa |
29256 | #define GUS_MISC__SEND0_IOWR_ONLY__SHIFT 0xf |
29257 | #define GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB_MASK 0x00000001L |
29258 | #define GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000002L |
29259 | #define GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000004L |
29260 | #define GUS_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000008L |
29261 | #define GUS_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000030L |
29262 | #define GUS_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x000000C0L |
29263 | #define GUS_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00000300L |
29264 | #define GUS_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x00007C00L |
29265 | #define GUS_MISC__SEND0_IOWR_ONLY_MASK 0x00008000L |
29266 | //GUS_LATENCY_SAMPLING |
29267 | #define GUS_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 |
29268 | #define GUS_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 |
29269 | #define GUS_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x2 |
29270 | #define GUS_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x3 |
29271 | #define GUS_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x4 |
29272 | #define GUS_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x5 |
29273 | #define GUS_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x6 |
29274 | #define GUS_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x7 |
29275 | #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0x8 |
29276 | #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0x9 |
29277 | #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xa |
29278 | #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xb |
29279 | #define GUS_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xc |
29280 | #define GUS_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x14 |
29281 | #define GUS_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L |
29282 | #define GUS_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L |
29283 | #define GUS_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000004L |
29284 | #define GUS_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000008L |
29285 | #define GUS_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000010L |
29286 | #define GUS_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000020L |
29287 | #define GUS_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000040L |
29288 | #define GUS_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000080L |
29289 | #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000100L |
29290 | #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000200L |
29291 | #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00000400L |
29292 | #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00000800L |
29293 | #define GUS_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x000FF000L |
29294 | #define GUS_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x0FF00000L |
29295 | //GUS_PERFCOUNTER_LO |
29296 | #define GUS_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
29297 | #define GUS_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
29298 | //GUS_PERFCOUNTER_HI |
29299 | #define GUS_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
29300 | #define GUS_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
29301 | #define GUS_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
29302 | #define GUS_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
29303 | //GUS_PERFCOUNTER0_CFG |
29304 | #define GUS_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
29305 | #define GUS_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
29306 | #define GUS_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
29307 | #define GUS_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
29308 | #define GUS_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
29309 | #define GUS_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
29310 | #define GUS_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29311 | #define GUS_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
29312 | #define GUS_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
29313 | #define GUS_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
29314 | //GUS_PERFCOUNTER1_CFG |
29315 | #define GUS_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
29316 | #define GUS_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
29317 | #define GUS_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
29318 | #define GUS_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
29319 | #define GUS_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
29320 | #define GUS_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
29321 | #define GUS_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
29322 | #define GUS_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
29323 | #define GUS_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
29324 | #define GUS_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
29325 | //GUS_PERFCOUNTER_RSLT_CNTL |
29326 | #define GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
29327 | #define GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
29328 | #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
29329 | #define GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
29330 | #define GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
29331 | #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
29332 | #define GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
29333 | #define GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
29334 | #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
29335 | #define GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
29336 | #define GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
29337 | #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
29338 | //GUS_ERR_STATUS |
29339 | #define GUS_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 |
29340 | #define GUS_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 |
29341 | #define GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 |
29342 | #define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa |
29343 | #define GUS_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb |
29344 | #define GUS_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc |
29345 | #define GUS_ERR_STATUS__FUE_FLAG__SHIFT 0xd |
29346 | #define GUS_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL |
29347 | #define GUS_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L |
29348 | #define GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L |
29349 | #define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L |
29350 | #define GUS_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L |
29351 | #define GUS_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L |
29352 | #define GUS_ERR_STATUS__FUE_FLAG_MASK 0x00002000L |
29353 | //GUS_MISC2 |
29354 | #define GUS_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0x0 |
29355 | #define GUS_MISC2__CH_L1_RO_MASK__SHIFT 0x1 |
29356 | #define GUS_MISC2__SA0_L1_RO_MASK__SHIFT 0x2 |
29357 | #define GUS_MISC2__SA1_L1_RO_MASK__SHIFT 0x3 |
29358 | #define GUS_MISC2__SA2_L1_RO_MASK__SHIFT 0x4 |
29359 | #define GUS_MISC2__SA3_L1_RO_MASK__SHIFT 0x5 |
29360 | #define GUS_MISC2__CH_L1_PERF_MASK__SHIFT 0x6 |
29361 | #define GUS_MISC2__SA0_L1_PERF_MASK__SHIFT 0x7 |
29362 | #define GUS_MISC2__SA1_L1_PERF_MASK__SHIFT 0x8 |
29363 | #define GUS_MISC2__SA2_L1_PERF_MASK__SHIFT 0x9 |
29364 | #define GUS_MISC2__SA3_L1_PERF_MASK__SHIFT 0xa |
29365 | #define GUS_MISC2__FP_ATOMICS_ENABLE__SHIFT 0xb |
29366 | #define GUS_MISC2__L1_RET_CLKEN__SHIFT 0xc |
29367 | #define GUS_MISC2__FGCLKEN_HIGH__SHIFT 0xd |
29368 | #define GUS_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00000001L |
29369 | #define GUS_MISC2__CH_L1_RO_MASK_MASK 0x00000002L |
29370 | #define GUS_MISC2__SA0_L1_RO_MASK_MASK 0x00000004L |
29371 | #define GUS_MISC2__SA1_L1_RO_MASK_MASK 0x00000008L |
29372 | #define GUS_MISC2__SA2_L1_RO_MASK_MASK 0x00000010L |
29373 | #define GUS_MISC2__SA3_L1_RO_MASK_MASK 0x00000020L |
29374 | #define GUS_MISC2__CH_L1_PERF_MASK_MASK 0x00000040L |
29375 | #define GUS_MISC2__SA0_L1_PERF_MASK_MASK 0x00000080L |
29376 | #define GUS_MISC2__SA1_L1_PERF_MASK_MASK 0x00000100L |
29377 | #define GUS_MISC2__SA2_L1_PERF_MASK_MASK 0x00000200L |
29378 | #define GUS_MISC2__SA3_L1_PERF_MASK_MASK 0x00000400L |
29379 | #define GUS_MISC2__FP_ATOMICS_ENABLE_MASK 0x00000800L |
29380 | #define GUS_MISC2__L1_RET_CLKEN_MASK 0x00001000L |
29381 | #define GUS_MISC2__FGCLKEN_HIGH_MASK 0x00002000L |
29382 | //GUS_SDP_BACKDOOR_CMDCREDITS0 |
29383 | #define GUS_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED__SHIFT 0x0 |
29384 | #define GUS_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL |
29385 | //GUS_SDP_BACKDOOR_CMDCREDITS1 |
29386 | #define GUS_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED__SHIFT 0x0 |
29387 | #define GUS_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL |
29388 | //GUS_SDP_BACKDOOR_DATACREDITS0 |
29389 | #define GUS_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED__SHIFT 0x0 |
29390 | #define GUS_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL |
29391 | //GUS_SDP_BACKDOOR_DATACREDITS1 |
29392 | #define GUS_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED__SHIFT 0x0 |
29393 | #define GUS_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL |
29394 | //GUS_SDP_BACKDOOR_MISCCREDITS |
29395 | #define GUS_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0 |
29396 | #define GUS_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8 |
29397 | #define GUS_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL |
29398 | #define GUS_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L |
29399 | //GUS_SDP_ENABLE |
29400 | #define GUS_SDP_ENABLE__ENABLE__SHIFT 0x0 |
29401 | #define GUS_SDP_ENABLE__ENABLE_MASK 0x00000001L |
29402 | //GUS_L1_CH0_CMD_IN |
29403 | #define GUS_L1_CH0_CMD_IN__COUNT__SHIFT 0x0 |
29404 | #define GUS_L1_CH0_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
29405 | //GUS_L1_CH0_CMD_OUT |
29406 | #define GUS_L1_CH0_CMD_OUT__COUNT__SHIFT 0x0 |
29407 | #define GUS_L1_CH0_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
29408 | //GUS_L1_CH0_DATA_IN |
29409 | #define GUS_L1_CH0_DATA_IN__COUNT__SHIFT 0x0 |
29410 | #define GUS_L1_CH0_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
29411 | //GUS_L1_CH0_DATA_OUT |
29412 | #define GUS_L1_CH0_DATA_OUT__COUNT__SHIFT 0x0 |
29413 | #define GUS_L1_CH0_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
29414 | //GUS_L1_CH1_CMD_IN |
29415 | #define GUS_L1_CH1_CMD_IN__COUNT__SHIFT 0x0 |
29416 | #define GUS_L1_CH1_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
29417 | //GUS_L1_CH1_CMD_OUT |
29418 | #define GUS_L1_CH1_CMD_OUT__COUNT__SHIFT 0x0 |
29419 | #define GUS_L1_CH1_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
29420 | //GUS_L1_CH1_DATA_IN |
29421 | #define GUS_L1_CH1_DATA_IN__COUNT__SHIFT 0x0 |
29422 | #define GUS_L1_CH1_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
29423 | //GUS_L1_CH1_DATA_OUT |
29424 | #define GUS_L1_CH1_DATA_OUT__COUNT__SHIFT 0x0 |
29425 | #define GUS_L1_CH1_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
29426 | //GUS_L1_SA0_CMD_IN |
29427 | #define GUS_L1_SA0_CMD_IN__COUNT__SHIFT 0x0 |
29428 | #define GUS_L1_SA0_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
29429 | //GUS_L1_SA0_CMD_OUT |
29430 | #define GUS_L1_SA0_CMD_OUT__COUNT__SHIFT 0x0 |
29431 | #define GUS_L1_SA0_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
29432 | //GUS_L1_SA0_DATA_IN |
29433 | #define GUS_L1_SA0_DATA_IN__COUNT__SHIFT 0x0 |
29434 | #define GUS_L1_SA0_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
29435 | //GUS_L1_SA0_DATA_OUT |
29436 | #define GUS_L1_SA0_DATA_OUT__COUNT__SHIFT 0x0 |
29437 | #define GUS_L1_SA0_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
29438 | //GUS_L1_SA0_DATA_U_IN |
29439 | #define GUS_L1_SA0_DATA_U_IN__COUNT__SHIFT 0x0 |
29440 | #define GUS_L1_SA0_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
29441 | //GUS_L1_SA0_DATA_U_OUT |
29442 | #define GUS_L1_SA0_DATA_U_OUT__COUNT__SHIFT 0x0 |
29443 | #define GUS_L1_SA0_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
29444 | //GUS_L1_SA1_CMD_IN |
29445 | #define GUS_L1_SA1_CMD_IN__COUNT__SHIFT 0x0 |
29446 | #define GUS_L1_SA1_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
29447 | //GUS_L1_SA1_CMD_OUT |
29448 | #define GUS_L1_SA1_CMD_OUT__COUNT__SHIFT 0x0 |
29449 | #define GUS_L1_SA1_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
29450 | //GUS_L1_SA1_DATA_IN |
29451 | #define GUS_L1_SA1_DATA_IN__COUNT__SHIFT 0x0 |
29452 | #define GUS_L1_SA1_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
29453 | //GUS_L1_SA1_DATA_OUT |
29454 | #define GUS_L1_SA1_DATA_OUT__COUNT__SHIFT 0x0 |
29455 | #define GUS_L1_SA1_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
29456 | //GUS_L1_SA1_DATA_U_IN |
29457 | #define GUS_L1_SA1_DATA_U_IN__COUNT__SHIFT 0x0 |
29458 | #define GUS_L1_SA1_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
29459 | //GUS_L1_SA1_DATA_U_OUT |
29460 | #define GUS_L1_SA1_DATA_U_OUT__COUNT__SHIFT 0x0 |
29461 | #define GUS_L1_SA1_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
29462 | //GUS_L1_SA2_CMD_IN |
29463 | #define GUS_L1_SA2_CMD_IN__COUNT__SHIFT 0x0 |
29464 | #define GUS_L1_SA2_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
29465 | //GUS_L1_SA2_CMD_OUT |
29466 | #define GUS_L1_SA2_CMD_OUT__COUNT__SHIFT 0x0 |
29467 | #define GUS_L1_SA2_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
29468 | //GUS_L1_SA2_DATA_IN |
29469 | #define GUS_L1_SA2_DATA_IN__COUNT__SHIFT 0x0 |
29470 | #define GUS_L1_SA2_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
29471 | //GUS_L1_SA2_DATA_OUT |
29472 | #define GUS_L1_SA2_DATA_OUT__COUNT__SHIFT 0x0 |
29473 | #define GUS_L1_SA2_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
29474 | //GUS_L1_SA2_DATA_U_IN |
29475 | #define GUS_L1_SA2_DATA_U_IN__COUNT__SHIFT 0x0 |
29476 | #define GUS_L1_SA2_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
29477 | //GUS_L1_SA2_DATA_U_OUT |
29478 | #define GUS_L1_SA2_DATA_U_OUT__COUNT__SHIFT 0x0 |
29479 | #define GUS_L1_SA2_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
29480 | //GUS_L1_SA3_CMD_IN |
29481 | #define GUS_L1_SA3_CMD_IN__COUNT__SHIFT 0x0 |
29482 | #define GUS_L1_SA3_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
29483 | //GUS_L1_SA3_CMD_OUT |
29484 | #define GUS_L1_SA3_CMD_OUT__COUNT__SHIFT 0x0 |
29485 | #define GUS_L1_SA3_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
29486 | //GUS_L1_SA3_DATA_IN |
29487 | #define GUS_L1_SA3_DATA_IN__COUNT__SHIFT 0x0 |
29488 | #define GUS_L1_SA3_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
29489 | //GUS_L1_SA3_DATA_OUT |
29490 | #define GUS_L1_SA3_DATA_OUT__COUNT__SHIFT 0x0 |
29491 | #define GUS_L1_SA3_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
29492 | //GUS_L1_SA3_DATA_U_IN |
29493 | #define GUS_L1_SA3_DATA_U_IN__COUNT__SHIFT 0x0 |
29494 | #define GUS_L1_SA3_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
29495 | //GUS_L1_SA3_DATA_U_OUT |
29496 | #define GUS_L1_SA3_DATA_U_OUT__COUNT__SHIFT 0x0 |
29497 | #define GUS_L1_SA3_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
29498 | //GUS_MISC3 |
29499 | //GUS_WRRSP_FIFO_CNTL |
29500 | #define GUS_WRRSP_FIFO_CNTL__THRESHOLD__SHIFT 0x0 |
29501 | #define GUS_WRRSP_FIFO_CNTL__THRESHOLD_MASK 0x0000003FL |
29502 | |
29503 | |
29504 | // addressBlock: gc_gl1dec |
29505 | //GL1_ARB_CTRL |
29506 | #define GL1_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0 |
29507 | #define GL1_ARB_CTRL__NUM_MEM_PIPES_MASK 0x00000007L |
29508 | //GL1_DRAM_BURST_MASK |
29509 | #define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 |
29510 | #define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL |
29511 | //GL1_ARB_STATUS |
29512 | #define GL1_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 |
29513 | #define GL1_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 |
29514 | #define GL1_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L |
29515 | #define GL1_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L |
29516 | //GL1_DRAM_BURST_CTRL |
29517 | #define GL1_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0 |
29518 | #define GL1_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 |
29519 | #define GL1_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT 0x4 |
29520 | #define GL1_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE__SHIFT 0x5 |
29521 | #define GL1_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L |
29522 | #define GL1_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L |
29523 | #define GL1_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK 0x00000010L |
29524 | #define GL1_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE_MASK 0x00000020L |
29525 | //GL1_PIPE_STEER |
29526 | #define GL1_PIPE_STEER__PIPE0__SHIFT 0x0 |
29527 | #define GL1_PIPE_STEER__PIPE1__SHIFT 0x2 |
29528 | #define GL1_PIPE_STEER__PIPE2__SHIFT 0x4 |
29529 | #define GL1_PIPE_STEER__PIPE3__SHIFT 0x6 |
29530 | #define GL1_PIPE_STEER__PIPE4__SHIFT 0x8 |
29531 | #define GL1_PIPE_STEER__PIPE5__SHIFT 0xa |
29532 | #define GL1_PIPE_STEER__PIPE6__SHIFT 0xc |
29533 | #define GL1_PIPE_STEER__PIPE7__SHIFT 0xe |
29534 | #define GL1_PIPE_STEER__PIPE8__SHIFT 0x10 |
29535 | #define GL1_PIPE_STEER__PIPE9__SHIFT 0x12 |
29536 | #define GL1_PIPE_STEER__PIPE10__SHIFT 0x14 |
29537 | #define GL1_PIPE_STEER__PIPE11__SHIFT 0x16 |
29538 | #define GL1_PIPE_STEER__PIPE12__SHIFT 0x18 |
29539 | #define GL1_PIPE_STEER__PIPE13__SHIFT 0x1a |
29540 | #define GL1_PIPE_STEER__PIPE14__SHIFT 0x1c |
29541 | #define GL1_PIPE_STEER__PIPE15__SHIFT 0x1e |
29542 | #define GL1_PIPE_STEER__PIPE0_MASK 0x00000003L |
29543 | #define GL1_PIPE_STEER__PIPE1_MASK 0x0000000CL |
29544 | #define GL1_PIPE_STEER__PIPE2_MASK 0x00000030L |
29545 | #define GL1_PIPE_STEER__PIPE3_MASK 0x000000C0L |
29546 | #define GL1_PIPE_STEER__PIPE4_MASK 0x00000300L |
29547 | #define GL1_PIPE_STEER__PIPE5_MASK 0x00000C00L |
29548 | #define GL1_PIPE_STEER__PIPE6_MASK 0x00003000L |
29549 | #define GL1_PIPE_STEER__PIPE7_MASK 0x0000C000L |
29550 | #define GL1_PIPE_STEER__PIPE8_MASK 0x00030000L |
29551 | #define GL1_PIPE_STEER__PIPE9_MASK 0x000C0000L |
29552 | #define GL1_PIPE_STEER__PIPE10_MASK 0x00300000L |
29553 | #define GL1_PIPE_STEER__PIPE11_MASK 0x00C00000L |
29554 | #define GL1_PIPE_STEER__PIPE12_MASK 0x03000000L |
29555 | #define GL1_PIPE_STEER__PIPE13_MASK 0x0C000000L |
29556 | #define GL1_PIPE_STEER__PIPE14_MASK 0x30000000L |
29557 | #define GL1_PIPE_STEER__PIPE15_MASK 0xC0000000L |
29558 | //GL1C_CTRL |
29559 | #define GL1C_CTRL__FORCE_MISS__SHIFT 0x0 |
29560 | #define GL1C_CTRL__FORCE_HIT__SHIFT 0x1 |
29561 | #define GL1C_CTRL__NOFILL_32B__SHIFT 0x2 |
29562 | #define GL1C_CTRL__NOFILL_64B__SHIFT 0x3 |
29563 | #define GL1C_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x4 |
29564 | #define GL1C_CTRL__ACK_QUEUE_DISABLE__SHIFT 0x8 |
29565 | #define GL1C_CTRL__RMI_META_READ_MISS_QUEUE_DISABLE__SHIFT 0x9 |
29566 | #define GL1C_CTRL__HIT_QUEUE_DISABLE__SHIFT 0xa |
29567 | #define GL1C_CTRL__FORCE_MISS_MASK 0x00000001L |
29568 | #define GL1C_CTRL__FORCE_HIT_MASK 0x00000002L |
29569 | #define GL1C_CTRL__NOFILL_32B_MASK 0x00000004L |
29570 | #define GL1C_CTRL__NOFILL_64B_MASK 0x00000008L |
29571 | #define GL1C_CTRL__LATENCY_FIFO_SIZE_MASK 0x000000F0L |
29572 | #define GL1C_CTRL__ACK_QUEUE_DISABLE_MASK 0x00000100L |
29573 | #define GL1C_CTRL__RMI_META_READ_MISS_QUEUE_DISABLE_MASK 0x00000200L |
29574 | #define GL1C_CTRL__HIT_QUEUE_DISABLE_MASK 0x00000400L |
29575 | //GL1C_STATUS |
29576 | #define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 |
29577 | #define GL1C_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 |
29578 | #define GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2 |
29579 | #define GL1C_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 |
29580 | #define GL1C_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 |
29581 | #define GL1C_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 |
29582 | #define GL1C_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 |
29583 | #define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 |
29584 | #define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 |
29585 | #define GL1C_STATUS__GL2_RH_BUSY__SHIFT 0x9 |
29586 | #define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa |
29587 | #define GL1C_STATUS__LATENCY_FIFO_FULL_STALL__SHIFT 0x14 |
29588 | #define GL1C_STATUS__TAG_STALL__SHIFT 0x15 |
29589 | #define GL1C_STATUS__TAG_BUSY__SHIFT 0x16 |
29590 | #define GL1C_STATUS__TAG_ACK_STALL__SHIFT 0x17 |
29591 | #define GL1C_STATUS__TAG_GCR_INV_STALL__SHIFT 0x18 |
29592 | #define GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL__SHIFT 0x19 |
29593 | #define GL1C_STATUS__TAG_EVICT__SHIFT 0x1a |
29594 | #define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION__SHIFT 0x1b |
29595 | #define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET__SHIFT 0x1f |
29596 | #define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L |
29597 | #define GL1C_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L |
29598 | #define GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L |
29599 | #define GL1C_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L |
29600 | #define GL1C_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L |
29601 | #define GL1C_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L |
29602 | #define GL1C_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L |
29603 | #define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L |
29604 | #define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L |
29605 | #define GL1C_STATUS__GL2_RH_BUSY_MASK 0x00000200L |
29606 | #define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L |
29607 | #define GL1C_STATUS__LATENCY_FIFO_FULL_STALL_MASK 0x00100000L |
29608 | #define GL1C_STATUS__TAG_STALL_MASK 0x00200000L |
29609 | #define GL1C_STATUS__TAG_BUSY_MASK 0x00400000L |
29610 | #define GL1C_STATUS__TAG_ACK_STALL_MASK 0x00800000L |
29611 | #define GL1C_STATUS__TAG_GCR_INV_STALL_MASK 0x01000000L |
29612 | #define GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL_MASK 0x02000000L |
29613 | #define GL1C_STATUS__TAG_EVICT_MASK 0x04000000L |
29614 | #define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION_MASK 0x78000000L |
29615 | #define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET_MASK 0x80000000L |
29616 | |
29617 | |
29618 | // addressBlock: gc_chdec |
29619 | //CH_ARB_CTRL |
29620 | #define CH_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0 |
29621 | #define CH_ARB_CTRL__UC_IO_WR_PATH__SHIFT 0x3 |
29622 | #define CH_ARB_CTRL__NUM_MEM_PIPES_MASK 0x00000007L |
29623 | #define CH_ARB_CTRL__UC_IO_WR_PATH_MASK 0x00000008L |
29624 | //CH_DRAM_BURST_MASK |
29625 | #define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 |
29626 | #define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL |
29627 | //CH_ARB_STATUS |
29628 | #define CH_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 |
29629 | #define CH_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 |
29630 | #define CH_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L |
29631 | #define CH_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L |
29632 | //CH_DRAM_BURST_CTRL |
29633 | #define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0 |
29634 | #define CH_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 |
29635 | #define CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT 0x4 |
29636 | #define CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE__SHIFT 0x5 |
29637 | #define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L |
29638 | #define CH_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L |
29639 | #define CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK 0x00000010L |
29640 | #define CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE_MASK 0x00000020L |
29641 | //CH_PIPE_STEER |
29642 | #define CH_PIPE_STEER__PIPE0__SHIFT 0x0 |
29643 | #define CH_PIPE_STEER__PIPE1__SHIFT 0x2 |
29644 | #define CH_PIPE_STEER__PIPE2__SHIFT 0x4 |
29645 | #define CH_PIPE_STEER__PIPE3__SHIFT 0x6 |
29646 | #define CH_PIPE_STEER__PIPE4__SHIFT 0x8 |
29647 | #define CH_PIPE_STEER__PIPE5__SHIFT 0xa |
29648 | #define CH_PIPE_STEER__PIPE6__SHIFT 0xc |
29649 | #define CH_PIPE_STEER__PIPE7__SHIFT 0xe |
29650 | #define CH_PIPE_STEER__PIPE8__SHIFT 0x10 |
29651 | #define CH_PIPE_STEER__PIPE9__SHIFT 0x12 |
29652 | #define CH_PIPE_STEER__PIPE10__SHIFT 0x14 |
29653 | #define CH_PIPE_STEER__PIPE11__SHIFT 0x16 |
29654 | #define CH_PIPE_STEER__PIPE12__SHIFT 0x18 |
29655 | #define CH_PIPE_STEER__PIPE13__SHIFT 0x1a |
29656 | #define CH_PIPE_STEER__PIPE14__SHIFT 0x1c |
29657 | #define CH_PIPE_STEER__PIPE15__SHIFT 0x1e |
29658 | #define CH_PIPE_STEER__PIPE0_MASK 0x00000003L |
29659 | #define CH_PIPE_STEER__PIPE1_MASK 0x0000000CL |
29660 | #define CH_PIPE_STEER__PIPE2_MASK 0x00000030L |
29661 | #define CH_PIPE_STEER__PIPE3_MASK 0x000000C0L |
29662 | #define CH_PIPE_STEER__PIPE4_MASK 0x00000300L |
29663 | #define CH_PIPE_STEER__PIPE5_MASK 0x00000C00L |
29664 | #define CH_PIPE_STEER__PIPE6_MASK 0x00003000L |
29665 | #define CH_PIPE_STEER__PIPE7_MASK 0x0000C000L |
29666 | #define CH_PIPE_STEER__PIPE8_MASK 0x00030000L |
29667 | #define CH_PIPE_STEER__PIPE9_MASK 0x000C0000L |
29668 | #define CH_PIPE_STEER__PIPE10_MASK 0x00300000L |
29669 | #define CH_PIPE_STEER__PIPE11_MASK 0x00C00000L |
29670 | #define CH_PIPE_STEER__PIPE12_MASK 0x03000000L |
29671 | #define CH_PIPE_STEER__PIPE13_MASK 0x0C000000L |
29672 | #define CH_PIPE_STEER__PIPE14_MASK 0x30000000L |
29673 | #define CH_PIPE_STEER__PIPE15_MASK 0xC0000000L |
29674 | //CH_VC5_ENABLE |
29675 | #define CH_VC5_ENABLE__UTCL2_VC5_ENABLE__SHIFT 0x1 |
29676 | #define CH_VC5_ENABLE__UTCL2_VC5_ENABLE_MASK 0x00000002L |
29677 | //CHC_CTRL |
29678 | #define CHC_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 |
29679 | #define CHC_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL |
29680 | //CHC_STATUS |
29681 | #define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 |
29682 | #define CHC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 |
29683 | #define CHC_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2 |
29684 | #define CHC_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 |
29685 | #define CHC_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 |
29686 | #define CHC_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 |
29687 | #define CHC_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 |
29688 | #define CHC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 |
29689 | #define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 |
29690 | #define CHC_STATUS__GL2_RH_BUSY__SHIFT 0x9 |
29691 | #define CHC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa |
29692 | #define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14 |
29693 | #define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15 |
29694 | #define CHC_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16 |
29695 | #define CHC_STATUS__BUFFER_FULL__SHIFT 0x17 |
29696 | #define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L |
29697 | #define CHC_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L |
29698 | #define CHC_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L |
29699 | #define CHC_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L |
29700 | #define CHC_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L |
29701 | #define CHC_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L |
29702 | #define CHC_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L |
29703 | #define CHC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L |
29704 | #define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L |
29705 | #define CHC_STATUS__GL2_RH_BUSY_MASK 0x00000200L |
29706 | #define CHC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L |
29707 | #define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L |
29708 | #define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L |
29709 | #define CHC_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L |
29710 | #define CHC_STATUS__BUFFER_FULL_MASK 0x00800000L |
29711 | //CHCG_CTRL |
29712 | #define CHCG_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 |
29713 | #define CHCG_CTRL__VC0_BUFFER_DEPTH_MAX__SHIFT 0x4 |
29714 | #define CHCG_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL |
29715 | #define CHCG_CTRL__VC0_BUFFER_DEPTH_MAX_MASK 0x000000F0L |
29716 | //CHCG_STATUS |
29717 | #define CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 |
29718 | #define CHCG_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 |
29719 | #define CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2 |
29720 | #define CHCG_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 |
29721 | #define CHCG_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 |
29722 | #define CHCG_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 |
29723 | #define CHCG_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 |
29724 | #define CHCG_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 |
29725 | #define CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 |
29726 | #define CHCG_STATUS__GL2_RH_BUSY__SHIFT 0x9 |
29727 | #define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa |
29728 | #define CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14 |
29729 | #define CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15 |
29730 | #define CHCG_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16 |
29731 | #define CHCG_STATUS__BUFFER_FULL__SHIFT 0x17 |
29732 | #define CHCG_STATUS__INPUT_BUFFER_VC1_BUSY__SHIFT 0x18 |
29733 | #define CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY__SHIFT 0x19 |
29734 | #define CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL__SHIFT 0x1a |
29735 | #define CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL__SHIFT 0x1b |
29736 | #define CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L |
29737 | #define CHCG_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L |
29738 | #define CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L |
29739 | #define CHCG_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L |
29740 | #define CHCG_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L |
29741 | #define CHCG_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L |
29742 | #define CHCG_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L |
29743 | #define CHCG_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L |
29744 | #define CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L |
29745 | #define CHCG_STATUS__GL2_RH_BUSY_MASK 0x00000200L |
29746 | #define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L |
29747 | #define CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L |
29748 | #define CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L |
29749 | #define CHCG_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L |
29750 | #define CHCG_STATUS__BUFFER_FULL_MASK 0x00800000L |
29751 | #define CHCG_STATUS__INPUT_BUFFER_VC1_BUSY_MASK 0x01000000L |
29752 | #define CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY_MASK 0x02000000L |
29753 | #define CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL_MASK 0x04000000L |
29754 | #define CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL_MASK 0x08000000L |
29755 | |
29756 | |
29757 | // addressBlock: gc_gl2dec |
29758 | //GL2C_CTRL |
29759 | #define GL2C_CTRL__CACHE_SIZE__SHIFT 0x0 |
29760 | #define GL2C_CTRL__RATE__SHIFT 0x2 |
29761 | #define GL2C_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 |
29762 | #define GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8 |
29763 | #define GL2C_CTRL__SRC_FIFO_SIZE__SHIFT 0xc |
29764 | #define GL2C_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 |
29765 | #define GL2C_CTRL__METADATA_TO_HI_PRIORITY__SHIFT 0x14 |
29766 | #define GL2C_CTRL__LINEAR_SET_HASH__SHIFT 0x15 |
29767 | #define GL2C_CTRL__FORCE_HIT_QUEUE_POP__SHIFT 0x16 |
29768 | #define GL2C_CTRL__MDC_SIZE__SHIFT 0x18 |
29769 | #define GL2C_CTRL__METADATA_TO_HIT_QUEUE__SHIFT 0x1a |
29770 | #define GL2C_CTRL__IGNORE_FULLY_WRITTEN__SHIFT 0x1b |
29771 | #define GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c |
29772 | #define GL2C_CTRL__CACHE_SIZE_MASK 0x00000003L |
29773 | #define GL2C_CTRL__RATE_MASK 0x0000000CL |
29774 | #define GL2C_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L |
29775 | #define GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L |
29776 | #define GL2C_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L |
29777 | #define GL2C_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L |
29778 | #define GL2C_CTRL__METADATA_TO_HI_PRIORITY_MASK 0x00100000L |
29779 | #define GL2C_CTRL__LINEAR_SET_HASH_MASK 0x00200000L |
29780 | #define GL2C_CTRL__FORCE_HIT_QUEUE_POP_MASK 0x00C00000L |
29781 | #define GL2C_CTRL__MDC_SIZE_MASK 0x03000000L |
29782 | #define GL2C_CTRL__METADATA_TO_HIT_QUEUE_MASK 0x04000000L |
29783 | #define GL2C_CTRL__IGNORE_FULLY_WRITTEN_MASK 0x08000000L |
29784 | #define GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L |
29785 | //GL2C_CTRL2 |
29786 | #define GL2C_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0 |
29787 | #define GL2C_CTRL2__ADDR_MATCH_DISABLE__SHIFT 0x4 |
29788 | #define GL2C_CTRL2__FILL_SIZE_32__SHIFT 0x5 |
29789 | #define GL2C_CTRL2__RB_TO_HI_PRIORITY__SHIFT 0x6 |
29790 | #define GL2C_CTRL2__HIT_UNDER_MISS_DISABLE__SHIFT 0x7 |
29791 | #define GL2C_CTRL2__RO_DISABLE__SHIFT 0x8 |
29792 | #define GL2C_CTRL2__FORCE_MDC_INV__SHIFT 0x9 |
29793 | #define GL2C_CTRL2__GCR_ARB_CTRL__SHIFT 0xa |
29794 | #define GL2C_CTRL2__GCR_ALL_SET__SHIFT 0xd |
29795 | #define GL2C_CTRL2__MDC_PF_BLOCK__SHIFT 0xe |
29796 | #define GL2C_CTRL2__MDC_PF_MAX_SIZE__SHIFT 0x10 |
29797 | #define GL2C_CTRL2__FILL_SIZE_64__SHIFT 0x11 |
29798 | #define GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT 0x12 |
29799 | #define GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE__SHIFT 0x13 |
29800 | #define GL2C_CTRL2__METADATA_VOLATILE_EN__SHIFT 0x14 |
29801 | #define GL2C_CTRL2__RB_VOLATILE_EN__SHIFT 0x15 |
29802 | #define GL2C_CTRL2__PROBE_UNSHARED_EN__SHIFT 0x16 |
29803 | #define GL2C_CTRL2__MAX_MIN_CTRL__SHIFT 0x17 |
29804 | #define GL2C_CTRL2__MDC_PF_LINEAR_METADATA__SHIFT 0x19 |
29805 | #define GL2C_CTRL2__MDC_UC_TO_C_RO_EN__SHIFT 0x1a |
29806 | #define GL2C_CTRL2__MDC_PF_MIN_PAGE_SIZE__SHIFT 0x1b |
29807 | #define GL2C_CTRL2__MDC_PF_DISABLE__SHIFT 0x1d |
29808 | #define GL2C_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL |
29809 | #define GL2C_CTRL2__ADDR_MATCH_DISABLE_MASK 0x00000010L |
29810 | #define GL2C_CTRL2__FILL_SIZE_32_MASK 0x00000020L |
29811 | #define GL2C_CTRL2__RB_TO_HI_PRIORITY_MASK 0x00000040L |
29812 | #define GL2C_CTRL2__HIT_UNDER_MISS_DISABLE_MASK 0x00000080L |
29813 | #define GL2C_CTRL2__RO_DISABLE_MASK 0x00000100L |
29814 | #define GL2C_CTRL2__FORCE_MDC_INV_MASK 0x00000200L |
29815 | #define GL2C_CTRL2__GCR_ARB_CTRL_MASK 0x00001C00L |
29816 | #define GL2C_CTRL2__GCR_ALL_SET_MASK 0x00002000L |
29817 | #define GL2C_CTRL2__MDC_PF_BLOCK_MASK 0x0000C000L |
29818 | #define GL2C_CTRL2__MDC_PF_MAX_SIZE_MASK 0x00010000L |
29819 | #define GL2C_CTRL2__FILL_SIZE_64_MASK 0x00020000L |
29820 | #define GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK 0x00040000L |
29821 | #define GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE_MASK 0x00080000L |
29822 | #define GL2C_CTRL2__METADATA_VOLATILE_EN_MASK 0x00100000L |
29823 | #define GL2C_CTRL2__RB_VOLATILE_EN_MASK 0x00200000L |
29824 | #define GL2C_CTRL2__PROBE_UNSHARED_EN_MASK 0x00400000L |
29825 | #define GL2C_CTRL2__MAX_MIN_CTRL_MASK 0x01800000L |
29826 | #define GL2C_CTRL2__MDC_PF_LINEAR_METADATA_MASK 0x02000000L |
29827 | #define GL2C_CTRL2__MDC_UC_TO_C_RO_EN_MASK 0x04000000L |
29828 | #define GL2C_CTRL2__MDC_PF_MIN_PAGE_SIZE_MASK 0x18000000L |
29829 | #define GL2C_CTRL2__MDC_PF_DISABLE_MASK 0xE0000000L |
29830 | //GL2C_STATUS |
29831 | #define GL2C_STATUS__NONCACHEABLE_FLOAT_ATOMIC__SHIFT 0x0 |
29832 | #define GL2C_STATUS__BC_COMPRESSED_WRITE_ATOMIC__SHIFT 0x1 |
29833 | #define GL2C_STATUS__COMPRESSED_GEN1_INVALID_SIZE__SHIFT 0x2 |
29834 | #define GL2C_STATUS__COMPRESSED_GEN0__SHIFT 0x3 |
29835 | #define GL2C_STATUS__NONCACHEABLE_FLOAT_ATOMIC_MASK 0x00000001L |
29836 | #define GL2C_STATUS__BC_COMPRESSED_WRITE_ATOMIC_MASK 0x00000002L |
29837 | #define GL2C_STATUS__COMPRESSED_GEN1_INVALID_SIZE_MASK 0x00000004L |
29838 | #define GL2C_STATUS__COMPRESSED_GEN0_MASK 0x00000008L |
29839 | //GL2C_ADDR_MATCH_MASK |
29840 | #define GL2C_ADDR_MATCH_MASK__ADDR_MASK__SHIFT 0x0 |
29841 | #define GL2C_ADDR_MATCH_MASK__ADDR_MASK_MASK 0xFFFFFFFFL |
29842 | //GL2C_ADDR_MATCH_SIZE |
29843 | #define GL2C_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT 0x0 |
29844 | #define GL2C_ADDR_MATCH_SIZE__MAX_COUNT_MASK 0x00000007L |
29845 | //GL2C_WBINVL2 |
29846 | #define GL2C_WBINVL2__DONE__SHIFT 0x4 |
29847 | #define GL2C_WBINVL2__DONE_MASK 0x00000010L |
29848 | //GL2C_SOFT_RESET |
29849 | #define GL2C_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0 |
29850 | #define GL2C_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L |
29851 | //GL2C_CM_CTRL0 |
29852 | #define GL2C_CM_CTRL0__HASH_MASK__SHIFT 0x0 |
29853 | #define GL2C_CM_CTRL0__HASH_MASK_MASK 0xFFFFFFFFL |
29854 | //GL2C_CM_CTRL1 |
29855 | #define GL2C_CM_CTRL1__HASH_MASK__SHIFT 0x0 |
29856 | #define GL2C_CM_CTRL1__BURST_TIMER__SHIFT 0x8 |
29857 | #define GL2C_CM_CTRL1__RVF_SIZE__SHIFT 0x10 |
29858 | #define GL2C_CM_CTRL1__WRITE_COH_MODE__SHIFT 0x17 |
29859 | #define GL2C_CM_CTRL1__MDC_ARB_MODE__SHIFT 0x19 |
29860 | #define GL2C_CM_CTRL1__READ_REQ_ONLY__SHIFT 0x1a |
29861 | #define GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN__SHIFT 0x1b |
29862 | #define GL2C_CM_CTRL1__COMP_TO_SINGLE_EN__SHIFT 0x1c |
29863 | #define GL2C_CM_CTRL1__BURST_MODE__SHIFT 0x1d |
29864 | #define GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER__SHIFT 0x1e |
29865 | #define GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE__SHIFT 0x1f |
29866 | #define GL2C_CM_CTRL1__HASH_MASK_MASK 0x0000000FL |
29867 | #define GL2C_CM_CTRL1__BURST_TIMER_MASK 0x0000FF00L |
29868 | #define GL2C_CM_CTRL1__RVF_SIZE_MASK 0x000F0000L |
29869 | #define GL2C_CM_CTRL1__WRITE_COH_MODE_MASK 0x01800000L |
29870 | #define GL2C_CM_CTRL1__MDC_ARB_MODE_MASK 0x02000000L |
29871 | #define GL2C_CM_CTRL1__READ_REQ_ONLY_MASK 0x04000000L |
29872 | #define GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN_MASK 0x08000000L |
29873 | #define GL2C_CM_CTRL1__COMP_TO_SINGLE_EN_MASK 0x10000000L |
29874 | #define GL2C_CM_CTRL1__BURST_MODE_MASK 0x20000000L |
29875 | #define GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER_MASK 0x40000000L |
29876 | #define GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE_MASK 0x80000000L |
29877 | //GL2C_CM_STALL |
29878 | #define GL2C_CM_STALL__QUEUE__SHIFT 0x0 |
29879 | #define GL2C_CM_STALL__QUEUE_MASK 0xFFFFFFFFL |
29880 | //GL2C_MDC_PF_FLAG_CTRL |
29881 | #define GL2C_MDC_PF_FLAG_CTRL__TIMER__SHIFT 0x0 |
29882 | #define GL2C_MDC_PF_FLAG_CTRL__TIMER_MASK 0xFFFFFFFFL |
29883 | //GL2C_CM_CTRL2 |
29884 | #define GL2C_CM_CTRL2__READ_BURST_TIMER__SHIFT 0x0 |
29885 | #define GL2C_CM_CTRL2__READ_BURST_TIMER_MASK 0x000000FFL |
29886 | //GL2C_CTRL3 |
29887 | #define GL2C_CTRL3__METADATA_MTYPE_COHERENCY__SHIFT 0x0 |
29888 | #define GL2C_CTRL3__MDC_PF_COLOR_USE_REQ_METADATA__SHIFT 0x2 |
29889 | #define GL2C_CTRL3__METADATA_NOFILL__SHIFT 0x3 |
29890 | #define GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH__SHIFT 0x4 |
29891 | #define GL2C_CTRL3__COMPRESSED_ATOMICS_AVOID_EA_READ__SHIFT 0x5 |
29892 | #define GL2C_CTRL3__HTILE_TO_HI_PRIORITY__SHIFT 0x6 |
29893 | #define GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE__SHIFT 0x7 |
29894 | #define GL2C_CTRL3__IO_CHANNEL_ENABLE__SHIFT 0x8 |
29895 | #define GL2C_CTRL3__FMASK_TO_HI_PRIORITY__SHIFT 0x9 |
29896 | #define GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY__SHIFT 0xa |
29897 | #define GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE__SHIFT 0xb |
29898 | #define GL2C_CTRL3__COMP_TO_CONST_CAM_CHECK_ENABLE__SHIFT 0xc |
29899 | #define GL2C_CTRL3__FGCG_OVERRIDE__SHIFT 0xf |
29900 | #define GL2C_CTRL3__SCRATCH__SHIFT 0x10 |
29901 | #define GL2C_CTRL3__METADATA_MTYPE_COHERENCY_MASK 0x00000003L |
29902 | #define GL2C_CTRL3__MDC_PF_COLOR_USE_REQ_METADATA_MASK 0x00000004L |
29903 | #define GL2C_CTRL3__METADATA_NOFILL_MASK 0x00000008L |
29904 | #define GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH_MASK 0x00000010L |
29905 | #define GL2C_CTRL3__COMPRESSED_ATOMICS_AVOID_EA_READ_MASK 0x00000020L |
29906 | #define GL2C_CTRL3__HTILE_TO_HI_PRIORITY_MASK 0x00000040L |
29907 | #define GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE_MASK 0x00000080L |
29908 | #define GL2C_CTRL3__IO_CHANNEL_ENABLE_MASK 0x00000100L |
29909 | #define GL2C_CTRL3__FMASK_TO_HI_PRIORITY_MASK 0x00000200L |
29910 | #define GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY_MASK 0x00000400L |
29911 | #define GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE_MASK 0x00000800L |
29912 | #define GL2C_CTRL3__COMP_TO_CONST_CAM_CHECK_ENABLE_MASK 0x00001000L |
29913 | #define GL2C_CTRL3__FGCG_OVERRIDE_MASK 0x00008000L |
29914 | #define GL2C_CTRL3__SCRATCH_MASK 0xFFFF0000L |
29915 | //GL2C_LB_CTR_CTRL |
29916 | #define GL2C_LB_CTR_CTRL__START__SHIFT 0x0 |
29917 | #define GL2C_LB_CTR_CTRL__LOAD__SHIFT 0x1 |
29918 | #define GL2C_LB_CTR_CTRL__CLEAR__SHIFT 0x2 |
29919 | #define GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x1f |
29920 | #define GL2C_LB_CTR_CTRL__START_MASK 0x00000001L |
29921 | #define GL2C_LB_CTR_CTRL__LOAD_MASK 0x00000002L |
29922 | #define GL2C_LB_CTR_CTRL__CLEAR_MASK 0x00000004L |
29923 | #define GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x80000000L |
29924 | //GL2C_LB_DATA0 |
29925 | #define GL2C_LB_DATA0__DATA__SHIFT 0x0 |
29926 | #define GL2C_LB_DATA0__DATA_MASK 0xFFFFFFFFL |
29927 | //GL2C_LB_DATA1 |
29928 | #define GL2C_LB_DATA1__DATA__SHIFT 0x0 |
29929 | #define GL2C_LB_DATA1__DATA_MASK 0xFFFFFFFFL |
29930 | //GL2C_LB_DATA2 |
29931 | #define GL2C_LB_DATA2__DATA__SHIFT 0x0 |
29932 | #define GL2C_LB_DATA2__DATA_MASK 0xFFFFFFFFL |
29933 | //GL2C_LB_DATA3 |
29934 | #define GL2C_LB_DATA3__DATA__SHIFT 0x0 |
29935 | #define GL2C_LB_DATA3__DATA_MASK 0xFFFFFFFFL |
29936 | //GL2C_LB_CTR_SEL0 |
29937 | #define GL2C_LB_CTR_SEL0__SEL0__SHIFT 0x0 |
29938 | #define GL2C_LB_CTR_SEL0__DIV0__SHIFT 0xf |
29939 | #define GL2C_LB_CTR_SEL0__SEL1__SHIFT 0x10 |
29940 | #define GL2C_LB_CTR_SEL0__DIV1__SHIFT 0x1f |
29941 | #define GL2C_LB_CTR_SEL0__SEL0_MASK 0x000000FFL |
29942 | #define GL2C_LB_CTR_SEL0__DIV0_MASK 0x00008000L |
29943 | #define GL2C_LB_CTR_SEL0__SEL1_MASK 0x00FF0000L |
29944 | #define GL2C_LB_CTR_SEL0__DIV1_MASK 0x80000000L |
29945 | //GL2C_LB_CTR_SEL1 |
29946 | #define GL2C_LB_CTR_SEL1__SEL2__SHIFT 0x0 |
29947 | #define GL2C_LB_CTR_SEL1__DIV2__SHIFT 0xf |
29948 | #define GL2C_LB_CTR_SEL1__SEL3__SHIFT 0x10 |
29949 | #define GL2C_LB_CTR_SEL1__DIV3__SHIFT 0x1f |
29950 | #define GL2C_LB_CTR_SEL1__SEL2_MASK 0x000000FFL |
29951 | #define GL2C_LB_CTR_SEL1__DIV2_MASK 0x00008000L |
29952 | #define GL2C_LB_CTR_SEL1__SEL3_MASK 0x00FF0000L |
29953 | #define GL2C_LB_CTR_SEL1__DIV3_MASK 0x80000000L |
29954 | //GL2A_ADDR_MATCH_CTRL |
29955 | #define GL2A_ADDR_MATCH_CTRL__DISABLE__SHIFT 0x0 |
29956 | #define GL2A_ADDR_MATCH_CTRL__DISABLE_MASK 0xFFFFFFFFL |
29957 | //GL2A_ADDR_MATCH_MASK |
29958 | #define GL2A_ADDR_MATCH_MASK__ADDR_MASK__SHIFT 0x0 |
29959 | #define GL2A_ADDR_MATCH_MASK__ADDR_MASK_MASK 0xFFFFFFFFL |
29960 | //GL2A_ADDR_MATCH_SIZE |
29961 | #define GL2A_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT 0x0 |
29962 | #define GL2A_ADDR_MATCH_SIZE__MAX_COUNT_MASK 0x00000007L |
29963 | //GL2A_PRIORITY_CTRL |
29964 | #define GL2A_PRIORITY_CTRL__DISABLE__SHIFT 0x0 |
29965 | #define GL2A_PRIORITY_CTRL__DISABLE_MASK 0xFFFFFFFFL |
29966 | //GL2A_CTRL |
29967 | #define GL2A_CTRL__RTN_ARB_TIMER_RESET_VALUE__SHIFT 0x0 |
29968 | #define GL2A_CTRL__STAY_ON_BURST__SHIFT 0x1 |
29969 | #define GL2A_CTRL__RTN_ARB_TIMER_RESET_VALUE_MASK 0x00000001L |
29970 | #define GL2A_CTRL__STAY_ON_BURST_MASK 0x00000002L |
29971 | //GL2_PIPE_STEER_0 |
29972 | #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0__SHIFT 0x0 |
29973 | #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0__SHIFT 0x4 |
29974 | #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0__SHIFT 0x8 |
29975 | #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0__SHIFT 0xc |
29976 | #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1__SHIFT 0x10 |
29977 | #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1__SHIFT 0x14 |
29978 | #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1__SHIFT 0x18 |
29979 | #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1__SHIFT 0x1c |
29980 | #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0_MASK 0x00000007L |
29981 | #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0_MASK 0x00000070L |
29982 | #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0_MASK 0x00000700L |
29983 | #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0_MASK 0x00007000L |
29984 | #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1_MASK 0x00070000L |
29985 | #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1_MASK 0x00700000L |
29986 | #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1_MASK 0x07000000L |
29987 | #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1_MASK 0x70000000L |
29988 | //GL2_PIPE_STEER_1 |
29989 | #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2__SHIFT 0x0 |
29990 | #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2__SHIFT 0x4 |
29991 | #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2__SHIFT 0x8 |
29992 | #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2__SHIFT 0xc |
29993 | #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3__SHIFT 0x10 |
29994 | #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3__SHIFT 0x14 |
29995 | #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3__SHIFT 0x18 |
29996 | #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3__SHIFT 0x1c |
29997 | #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2_MASK 0x00000007L |
29998 | #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2_MASK 0x00000070L |
29999 | #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2_MASK 0x00000700L |
30000 | #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2_MASK 0x00007000L |
30001 | #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3_MASK 0x00070000L |
30002 | #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3_MASK 0x00700000L |
30003 | #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3_MASK 0x07000000L |
30004 | #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3_MASK 0x70000000L |
30005 | |
30006 | |
30007 | // addressBlock: gc_perfddec |
30008 | //CPG_PERFCOUNTER1_LO |
30009 | #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30010 | #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30011 | //CPG_PERFCOUNTER1_HI |
30012 | #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30013 | #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30014 | //CPG_PERFCOUNTER0_LO |
30015 | #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30016 | #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30017 | //CPG_PERFCOUNTER0_HI |
30018 | #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30019 | #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30020 | //CPC_PERFCOUNTER1_LO |
30021 | #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30022 | #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30023 | //CPC_PERFCOUNTER1_HI |
30024 | #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30025 | #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30026 | //CPC_PERFCOUNTER0_LO |
30027 | #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30028 | #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30029 | //CPC_PERFCOUNTER0_HI |
30030 | #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30031 | #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30032 | //CPF_PERFCOUNTER1_LO |
30033 | #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30034 | #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30035 | //CPF_PERFCOUNTER1_HI |
30036 | #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30037 | #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30038 | //CPF_PERFCOUNTER0_LO |
30039 | #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30040 | #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30041 | //CPF_PERFCOUNTER0_HI |
30042 | #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30043 | #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30044 | //CPF_LATENCY_STATS_DATA |
30045 | #define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0 |
30046 | #define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL |
30047 | //CPG_LATENCY_STATS_DATA |
30048 | #define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0 |
30049 | #define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL |
30050 | //CPC_LATENCY_STATS_DATA |
30051 | #define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0 |
30052 | #define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL |
30053 | //GRBM_PERFCOUNTER0_LO |
30054 | #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30055 | #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30056 | //GRBM_PERFCOUNTER0_HI |
30057 | #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30058 | #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30059 | //GRBM_PERFCOUNTER1_LO |
30060 | #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30061 | #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30062 | //GRBM_PERFCOUNTER1_HI |
30063 | #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30064 | #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30065 | //GRBM_SE0_PERFCOUNTER_LO |
30066 | #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30067 | #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30068 | //GRBM_SE0_PERFCOUNTER_HI |
30069 | #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30070 | #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30071 | //GRBM_SE1_PERFCOUNTER_LO |
30072 | #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30073 | #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30074 | //GRBM_SE1_PERFCOUNTER_HI |
30075 | #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30076 | #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30077 | //GRBM_SE2_PERFCOUNTER_LO |
30078 | #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30079 | #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30080 | //GRBM_SE2_PERFCOUNTER_HI |
30081 | #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30082 | #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30083 | //GRBM_SE3_PERFCOUNTER_LO |
30084 | #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30085 | #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30086 | //GRBM_SE3_PERFCOUNTER_HI |
30087 | #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30088 | #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30089 | //GE_PERFCOUNTER0_LO |
30090 | #define GE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30091 | #define GE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30092 | //GE_PERFCOUNTER0_HI |
30093 | #define GE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30094 | #define GE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30095 | //GE_PERFCOUNTER1_LO |
30096 | #define GE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30097 | #define GE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30098 | //GE_PERFCOUNTER1_HI |
30099 | #define GE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30100 | #define GE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30101 | //GE_PERFCOUNTER2_LO |
30102 | #define GE_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30103 | #define GE_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30104 | //GE_PERFCOUNTER2_HI |
30105 | #define GE_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30106 | #define GE_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30107 | //GE_PERFCOUNTER3_LO |
30108 | #define GE_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30109 | #define GE_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30110 | //GE_PERFCOUNTER3_HI |
30111 | #define GE_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30112 | #define GE_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30113 | //GE_PERFCOUNTER4_LO |
30114 | #define GE_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30115 | #define GE_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30116 | //GE_PERFCOUNTER4_HI |
30117 | #define GE_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30118 | #define GE_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30119 | //GE_PERFCOUNTER5_LO |
30120 | #define GE_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30121 | #define GE_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30122 | //GE_PERFCOUNTER5_HI |
30123 | #define GE_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30124 | #define GE_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30125 | //GE_PERFCOUNTER6_LO |
30126 | #define GE_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30127 | #define GE_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30128 | //GE_PERFCOUNTER6_HI |
30129 | #define GE_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30130 | #define GE_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30131 | //GE_PERFCOUNTER7_LO |
30132 | #define GE_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30133 | #define GE_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30134 | //GE_PERFCOUNTER7_HI |
30135 | #define GE_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30136 | #define GE_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30137 | //GE_PERFCOUNTER8_LO |
30138 | #define GE_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30139 | #define GE_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30140 | //GE_PERFCOUNTER8_HI |
30141 | #define GE_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30142 | #define GE_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30143 | //GE_PERFCOUNTER9_LO |
30144 | #define GE_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30145 | #define GE_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30146 | //GE_PERFCOUNTER9_HI |
30147 | #define GE_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30148 | #define GE_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30149 | //GE_PERFCOUNTER10_LO |
30150 | #define GE_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30151 | #define GE_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30152 | //GE_PERFCOUNTER10_HI |
30153 | #define GE_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30154 | #define GE_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30155 | //GE_PERFCOUNTER11_LO |
30156 | #define GE_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30157 | #define GE_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30158 | //GE_PERFCOUNTER11_HI |
30159 | #define GE_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30160 | #define GE_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30161 | //PA_SU_PERFCOUNTER0_LO |
30162 | #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30163 | #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30164 | //PA_SU_PERFCOUNTER0_HI |
30165 | #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30166 | #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL |
30167 | //PA_SU_PERFCOUNTER1_LO |
30168 | #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30169 | #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30170 | //PA_SU_PERFCOUNTER1_HI |
30171 | #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30172 | #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL |
30173 | //PA_SU_PERFCOUNTER2_LO |
30174 | #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30175 | #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30176 | //PA_SU_PERFCOUNTER2_HI |
30177 | #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30178 | #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL |
30179 | //PA_SU_PERFCOUNTER3_LO |
30180 | #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30181 | #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30182 | //PA_SU_PERFCOUNTER3_HI |
30183 | #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30184 | #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL |
30185 | //PA_SC_PERFCOUNTER0_LO |
30186 | #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30187 | #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30188 | //PA_SC_PERFCOUNTER0_HI |
30189 | #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30190 | #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30191 | //PA_SC_PERFCOUNTER1_LO |
30192 | #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30193 | #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30194 | //PA_SC_PERFCOUNTER1_HI |
30195 | #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30196 | #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30197 | //PA_SC_PERFCOUNTER2_LO |
30198 | #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30199 | #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30200 | //PA_SC_PERFCOUNTER2_HI |
30201 | #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30202 | #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30203 | //PA_SC_PERFCOUNTER3_LO |
30204 | #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30205 | #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30206 | //PA_SC_PERFCOUNTER3_HI |
30207 | #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30208 | #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30209 | //PA_SC_PERFCOUNTER4_LO |
30210 | #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30211 | #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30212 | //PA_SC_PERFCOUNTER4_HI |
30213 | #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30214 | #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30215 | //PA_SC_PERFCOUNTER5_LO |
30216 | #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30217 | #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30218 | //PA_SC_PERFCOUNTER5_HI |
30219 | #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30220 | #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30221 | //PA_SC_PERFCOUNTER6_LO |
30222 | #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30223 | #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30224 | //PA_SC_PERFCOUNTER6_HI |
30225 | #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30226 | #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30227 | //PA_SC_PERFCOUNTER7_LO |
30228 | #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30229 | #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30230 | //PA_SC_PERFCOUNTER7_HI |
30231 | #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30232 | #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30233 | //SPI_PERFCOUNTER0_HI |
30234 | #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30235 | #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30236 | //SPI_PERFCOUNTER0_LO |
30237 | #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30238 | #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30239 | //SPI_PERFCOUNTER1_HI |
30240 | #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30241 | #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30242 | //SPI_PERFCOUNTER1_LO |
30243 | #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30244 | #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30245 | //SPI_PERFCOUNTER2_HI |
30246 | #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30247 | #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30248 | //SPI_PERFCOUNTER2_LO |
30249 | #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30250 | #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30251 | //SPI_PERFCOUNTER3_HI |
30252 | #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30253 | #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30254 | //SPI_PERFCOUNTER3_LO |
30255 | #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30256 | #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30257 | //SPI_PERFCOUNTER4_HI |
30258 | #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30259 | #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30260 | //SPI_PERFCOUNTER4_LO |
30261 | #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30262 | #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30263 | //SPI_PERFCOUNTER5_HI |
30264 | #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30265 | #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30266 | //SPI_PERFCOUNTER5_LO |
30267 | #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30268 | #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30269 | //SQ_PERFCOUNTER0_LO |
30270 | #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30271 | #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30272 | //SQ_PERFCOUNTER0_HI |
30273 | #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30274 | #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30275 | //SQ_PERFCOUNTER1_LO |
30276 | #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30277 | #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30278 | //SQ_PERFCOUNTER1_HI |
30279 | #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30280 | #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30281 | //SQ_PERFCOUNTER2_LO |
30282 | #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30283 | #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30284 | //SQ_PERFCOUNTER2_HI |
30285 | #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30286 | #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30287 | //SQ_PERFCOUNTER3_LO |
30288 | #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30289 | #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30290 | //SQ_PERFCOUNTER3_HI |
30291 | #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30292 | #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30293 | //SQ_PERFCOUNTER4_LO |
30294 | #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30295 | #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30296 | //SQ_PERFCOUNTER4_HI |
30297 | #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30298 | #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30299 | //SQ_PERFCOUNTER5_LO |
30300 | #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30301 | #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30302 | //SQ_PERFCOUNTER5_HI |
30303 | #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30304 | #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30305 | //SQ_PERFCOUNTER6_LO |
30306 | #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30307 | #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30308 | //SQ_PERFCOUNTER6_HI |
30309 | #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30310 | #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30311 | //SQ_PERFCOUNTER7_LO |
30312 | #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30313 | #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30314 | //SQ_PERFCOUNTER7_HI |
30315 | #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30316 | #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30317 | //SQ_PERFCOUNTER8_LO |
30318 | #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30319 | #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30320 | //SQ_PERFCOUNTER8_HI |
30321 | #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30322 | #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30323 | //SQ_PERFCOUNTER9_LO |
30324 | #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30325 | #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30326 | //SQ_PERFCOUNTER9_HI |
30327 | #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30328 | #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30329 | //SQ_PERFCOUNTER10_LO |
30330 | #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30331 | #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30332 | //SQ_PERFCOUNTER10_HI |
30333 | #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30334 | #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30335 | //SQ_PERFCOUNTER11_LO |
30336 | #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30337 | #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30338 | //SQ_PERFCOUNTER11_HI |
30339 | #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30340 | #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30341 | //SQ_PERFCOUNTER12_LO |
30342 | #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30343 | #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30344 | //SQ_PERFCOUNTER12_HI |
30345 | #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30346 | #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30347 | //SQ_PERFCOUNTER13_LO |
30348 | #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30349 | #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30350 | //SQ_PERFCOUNTER13_HI |
30351 | #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30352 | #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30353 | //SQ_PERFCOUNTER14_LO |
30354 | #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30355 | #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30356 | //SQ_PERFCOUNTER14_HI |
30357 | #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30358 | #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30359 | //SQ_PERFCOUNTER15_LO |
30360 | #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30361 | #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30362 | //SQ_PERFCOUNTER15_HI |
30363 | #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30364 | #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30365 | //SX_PERFCOUNTER0_LO |
30366 | #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30367 | #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30368 | //SX_PERFCOUNTER0_HI |
30369 | #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30370 | #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30371 | //SX_PERFCOUNTER1_LO |
30372 | #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30373 | #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30374 | //SX_PERFCOUNTER1_HI |
30375 | #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30376 | #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30377 | //SX_PERFCOUNTER2_LO |
30378 | #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30379 | #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30380 | //SX_PERFCOUNTER2_HI |
30381 | #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30382 | #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30383 | //SX_PERFCOUNTER3_LO |
30384 | #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30385 | #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30386 | //SX_PERFCOUNTER3_HI |
30387 | #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30388 | #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30389 | //GCEA_PERFCOUNTER2_LO |
30390 | #define GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30391 | #define GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30392 | //GCEA_PERFCOUNTER2_HI |
30393 | #define GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30394 | #define GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30395 | //GDS_PERFCOUNTER0_LO |
30396 | #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30397 | #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30398 | //GDS_PERFCOUNTER0_HI |
30399 | #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30400 | #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30401 | //GDS_PERFCOUNTER1_LO |
30402 | #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30403 | #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30404 | //GDS_PERFCOUNTER1_HI |
30405 | #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30406 | #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30407 | //GDS_PERFCOUNTER2_LO |
30408 | #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30409 | #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30410 | //GDS_PERFCOUNTER2_HI |
30411 | #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30412 | #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30413 | //GDS_PERFCOUNTER3_LO |
30414 | #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30415 | #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30416 | //GDS_PERFCOUNTER3_HI |
30417 | #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30418 | #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30419 | //TA_PERFCOUNTER0_LO |
30420 | #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30421 | #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30422 | //TA_PERFCOUNTER0_HI |
30423 | #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30424 | #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30425 | //TA_PERFCOUNTER1_LO |
30426 | #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30427 | #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30428 | //TA_PERFCOUNTER1_HI |
30429 | #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30430 | #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30431 | //TD_PERFCOUNTER0_LO |
30432 | #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30433 | #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30434 | //TD_PERFCOUNTER0_HI |
30435 | #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30436 | #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30437 | //TD_PERFCOUNTER1_LO |
30438 | #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30439 | #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30440 | //TD_PERFCOUNTER1_HI |
30441 | #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30442 | #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30443 | //TCP_PERFCOUNTER0_LO |
30444 | #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30445 | #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30446 | //TCP_PERFCOUNTER0_HI |
30447 | #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30448 | #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30449 | //TCP_PERFCOUNTER1_LO |
30450 | #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30451 | #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30452 | //TCP_PERFCOUNTER1_HI |
30453 | #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30454 | #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30455 | //TCP_PERFCOUNTER2_LO |
30456 | #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30457 | #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30458 | //TCP_PERFCOUNTER2_HI |
30459 | #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30460 | #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30461 | //TCP_PERFCOUNTER3_LO |
30462 | #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30463 | #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30464 | //TCP_PERFCOUNTER3_HI |
30465 | #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30466 | #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30467 | //GL2C_PERFCOUNTER0_LO |
30468 | #define GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30469 | #define GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30470 | //GL2C_PERFCOUNTER0_HI |
30471 | #define GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30472 | #define GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30473 | //GL2C_PERFCOUNTER1_LO |
30474 | #define GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30475 | #define GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30476 | //GL2C_PERFCOUNTER1_HI |
30477 | #define GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30478 | #define GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30479 | //GL2C_PERFCOUNTER2_LO |
30480 | #define GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30481 | #define GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30482 | //GL2C_PERFCOUNTER2_HI |
30483 | #define GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30484 | #define GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30485 | //GL2C_PERFCOUNTER3_LO |
30486 | #define GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30487 | #define GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30488 | //GL2C_PERFCOUNTER3_HI |
30489 | #define GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30490 | #define GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30491 | //GL2A_PERFCOUNTER0_LO |
30492 | #define GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30493 | #define GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30494 | //GL2A_PERFCOUNTER0_HI |
30495 | #define GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30496 | #define GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30497 | //GL2A_PERFCOUNTER1_LO |
30498 | #define GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30499 | #define GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30500 | //GL2A_PERFCOUNTER1_HI |
30501 | #define GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30502 | #define GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30503 | //GL2A_PERFCOUNTER2_LO |
30504 | #define GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30505 | #define GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30506 | //GL2A_PERFCOUNTER2_HI |
30507 | #define GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30508 | #define GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30509 | //GL2A_PERFCOUNTER3_LO |
30510 | #define GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30511 | #define GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30512 | //GL2A_PERFCOUNTER3_HI |
30513 | #define GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30514 | #define GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30515 | //GL1C_PERFCOUNTER0_LO |
30516 | #define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30517 | #define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30518 | //GL1C_PERFCOUNTER0_HI |
30519 | #define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30520 | #define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30521 | //GL1C_PERFCOUNTER1_LO |
30522 | #define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30523 | #define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30524 | //GL1C_PERFCOUNTER1_HI |
30525 | #define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30526 | #define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30527 | //GL1C_PERFCOUNTER2_LO |
30528 | #define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30529 | #define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30530 | //GL1C_PERFCOUNTER2_HI |
30531 | #define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30532 | #define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30533 | //GL1C_PERFCOUNTER3_LO |
30534 | #define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30535 | #define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30536 | //GL1C_PERFCOUNTER3_HI |
30537 | #define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30538 | #define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30539 | //CHC_PERFCOUNTER0_LO |
30540 | #define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30541 | #define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30542 | //CHC_PERFCOUNTER0_HI |
30543 | #define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30544 | #define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30545 | //CHC_PERFCOUNTER1_LO |
30546 | #define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30547 | #define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30548 | //CHC_PERFCOUNTER1_HI |
30549 | #define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30550 | #define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30551 | //CHC_PERFCOUNTER2_LO |
30552 | #define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30553 | #define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30554 | //CHC_PERFCOUNTER2_HI |
30555 | #define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30556 | #define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30557 | //CHC_PERFCOUNTER3_LO |
30558 | #define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30559 | #define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30560 | //CHC_PERFCOUNTER3_HI |
30561 | #define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30562 | #define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30563 | //CHCG_PERFCOUNTER0_LO |
30564 | #define CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30565 | #define CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30566 | //CHCG_PERFCOUNTER0_HI |
30567 | #define CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30568 | #define CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30569 | //CHCG_PERFCOUNTER1_LO |
30570 | #define CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30571 | #define CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30572 | //CHCG_PERFCOUNTER1_HI |
30573 | #define CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30574 | #define CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30575 | //CHCG_PERFCOUNTER2_LO |
30576 | #define CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30577 | #define CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30578 | //CHCG_PERFCOUNTER2_HI |
30579 | #define CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30580 | #define CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30581 | //CHCG_PERFCOUNTER3_LO |
30582 | #define CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30583 | #define CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30584 | //CHCG_PERFCOUNTER3_HI |
30585 | #define CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30586 | #define CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30587 | //CB_PERFCOUNTER0_LO |
30588 | #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30589 | #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30590 | //CB_PERFCOUNTER0_HI |
30591 | #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30592 | #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30593 | //CB_PERFCOUNTER1_LO |
30594 | #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30595 | #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30596 | //CB_PERFCOUNTER1_HI |
30597 | #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30598 | #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30599 | //CB_PERFCOUNTER2_LO |
30600 | #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30601 | #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30602 | //CB_PERFCOUNTER2_HI |
30603 | #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30604 | #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30605 | //CB_PERFCOUNTER3_LO |
30606 | #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30607 | #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30608 | //CB_PERFCOUNTER3_HI |
30609 | #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30610 | #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30611 | //DB_PERFCOUNTER0_LO |
30612 | #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30613 | #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30614 | //DB_PERFCOUNTER0_HI |
30615 | #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30616 | #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30617 | //DB_PERFCOUNTER1_LO |
30618 | #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30619 | #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30620 | //DB_PERFCOUNTER1_HI |
30621 | #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30622 | #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30623 | //DB_PERFCOUNTER2_LO |
30624 | #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30625 | #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30626 | //DB_PERFCOUNTER2_HI |
30627 | #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30628 | #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30629 | //DB_PERFCOUNTER3_LO |
30630 | #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30631 | #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30632 | //DB_PERFCOUNTER3_HI |
30633 | #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30634 | #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30635 | //RLC_PERFCOUNTER0_LO |
30636 | #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30637 | #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30638 | //RLC_PERFCOUNTER0_HI |
30639 | #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30640 | #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30641 | //RLC_PERFCOUNTER1_LO |
30642 | #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30643 | #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30644 | //RLC_PERFCOUNTER1_HI |
30645 | #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30646 | #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30647 | //RMI_PERFCOUNTER0_LO |
30648 | #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30649 | #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30650 | //RMI_PERFCOUNTER0_HI |
30651 | #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30652 | #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30653 | //RMI_PERFCOUNTER1_LO |
30654 | #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30655 | #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30656 | //RMI_PERFCOUNTER1_HI |
30657 | #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30658 | #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30659 | //RMI_PERFCOUNTER2_LO |
30660 | #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30661 | #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30662 | //RMI_PERFCOUNTER2_HI |
30663 | #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30664 | #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30665 | //RMI_PERFCOUNTER3_LO |
30666 | #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30667 | #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30668 | //RMI_PERFCOUNTER3_HI |
30669 | #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30670 | #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30671 | //UTCL1_PERFCOUNTER0_LO |
30672 | #define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30673 | #define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30674 | //UTCL1_PERFCOUNTER0_HI |
30675 | #define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30676 | #define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30677 | //UTCL1_PERFCOUNTER1_LO |
30678 | #define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30679 | #define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30680 | //UTCL1_PERFCOUNTER1_HI |
30681 | #define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30682 | #define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30683 | //GCR_PERFCOUNTER0_LO |
30684 | #define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30685 | #define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30686 | //GCR_PERFCOUNTER0_HI |
30687 | #define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30688 | #define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30689 | //GCR_PERFCOUNTER1_LO |
30690 | #define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30691 | #define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30692 | //GCR_PERFCOUNTER1_HI |
30693 | #define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30694 | #define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30695 | //PA_PH_PERFCOUNTER0_LO |
30696 | #define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30697 | #define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30698 | //PA_PH_PERFCOUNTER0_HI |
30699 | #define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30700 | #define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30701 | //PA_PH_PERFCOUNTER1_LO |
30702 | #define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30703 | #define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30704 | //PA_PH_PERFCOUNTER1_HI |
30705 | #define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30706 | #define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30707 | //PA_PH_PERFCOUNTER2_LO |
30708 | #define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30709 | #define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30710 | //PA_PH_PERFCOUNTER2_HI |
30711 | #define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30712 | #define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30713 | //PA_PH_PERFCOUNTER3_LO |
30714 | #define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30715 | #define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30716 | //PA_PH_PERFCOUNTER3_HI |
30717 | #define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30718 | #define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30719 | //PA_PH_PERFCOUNTER4_LO |
30720 | #define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30721 | #define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30722 | //PA_PH_PERFCOUNTER4_HI |
30723 | #define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30724 | #define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30725 | //PA_PH_PERFCOUNTER5_LO |
30726 | #define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30727 | #define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30728 | //PA_PH_PERFCOUNTER5_HI |
30729 | #define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30730 | #define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30731 | //PA_PH_PERFCOUNTER6_LO |
30732 | #define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30733 | #define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30734 | //PA_PH_PERFCOUNTER6_HI |
30735 | #define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30736 | #define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30737 | //PA_PH_PERFCOUNTER7_LO |
30738 | #define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30739 | #define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30740 | //PA_PH_PERFCOUNTER7_HI |
30741 | #define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30742 | #define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30743 | //GL1A_PERFCOUNTER0_LO |
30744 | #define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30745 | #define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30746 | //GL1A_PERFCOUNTER0_HI |
30747 | #define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30748 | #define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30749 | //GL1A_PERFCOUNTER1_LO |
30750 | #define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30751 | #define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30752 | //GL1A_PERFCOUNTER1_HI |
30753 | #define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30754 | #define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30755 | //GL1A_PERFCOUNTER2_LO |
30756 | #define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30757 | #define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30758 | //GL1A_PERFCOUNTER2_HI |
30759 | #define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30760 | #define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30761 | //GL1A_PERFCOUNTER3_LO |
30762 | #define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30763 | #define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30764 | //GL1A_PERFCOUNTER3_HI |
30765 | #define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30766 | #define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30767 | //CHA_PERFCOUNTER0_LO |
30768 | #define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30769 | #define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30770 | //CHA_PERFCOUNTER0_HI |
30771 | #define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30772 | #define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30773 | //CHA_PERFCOUNTER1_LO |
30774 | #define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30775 | #define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30776 | //CHA_PERFCOUNTER1_HI |
30777 | #define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30778 | #define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30779 | //CHA_PERFCOUNTER2_LO |
30780 | #define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30781 | #define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30782 | //CHA_PERFCOUNTER2_HI |
30783 | #define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30784 | #define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30785 | //CHA_PERFCOUNTER3_LO |
30786 | #define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30787 | #define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30788 | //CHA_PERFCOUNTER3_HI |
30789 | #define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30790 | #define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30791 | //GUS_PERFCOUNTER2_LO |
30792 | #define GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30793 | #define GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30794 | //GUS_PERFCOUNTER2_HI |
30795 | #define GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30796 | #define GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30797 | |
30798 | |
30799 | // addressBlock: gc_gcatcl2pfcntrdec |
30800 | //GC_ATC_L2_PERFCOUNTER_LO |
30801 | #define GC_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
30802 | #define GC_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
30803 | //GC_ATC_L2_PERFCOUNTER_HI |
30804 | #define GC_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
30805 | #define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
30806 | #define GC_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
30807 | #define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
30808 | |
30809 | |
30810 | // addressBlock: gc_gcvml2prdec |
30811 | //GCMC_VM_L2_PERFCOUNTER_LO |
30812 | #define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
30813 | #define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
30814 | //GCMC_VM_L2_PERFCOUNTER_HI |
30815 | #define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
30816 | #define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
30817 | #define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
30818 | #define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
30819 | |
30820 | |
30821 | // addressBlock: gc_gcvml2perfddec |
30822 | //GCVML2_PERFCOUNTER2_0_LO |
30823 | #define GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30824 | #define GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30825 | //GCVML2_PERFCOUNTER2_1_LO |
30826 | #define GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30827 | #define GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30828 | //GCVML2_PERFCOUNTER2_0_HI |
30829 | #define GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30830 | #define GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30831 | //GCVML2_PERFCOUNTER2_1_HI |
30832 | #define GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30833 | #define GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30834 | |
30835 | |
30836 | // addressBlock: gc_gcatcl2perfddec |
30837 | //GC_ATC_L2_PERFCOUNTER2_LO |
30838 | #define GC_ATC_L2_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
30839 | #define GC_ATC_L2_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
30840 | //GC_ATC_L2_PERFCOUNTER2_HI |
30841 | #define GC_ATC_L2_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
30842 | #define GC_ATC_L2_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
30843 | |
30844 | |
30845 | // addressBlock: gc_perfsdec |
30846 | //CPG_PERFCOUNTER1_SELECT |
30847 | #define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30848 | #define CPG_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
30849 | #define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
30850 | #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 |
30851 | #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c |
30852 | #define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
30853 | #define CPG_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30854 | #define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
30855 | #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L |
30856 | #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L |
30857 | //CPG_PERFCOUNTER0_SELECT1 |
30858 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30859 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30860 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 |
30861 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c |
30862 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30863 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30864 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L |
30865 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L |
30866 | //CPG_PERFCOUNTER0_SELECT |
30867 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30868 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30869 | #define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
30870 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 |
30871 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c |
30872 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
30873 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30874 | #define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
30875 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L |
30876 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L |
30877 | //CPC_PERFCOUNTER1_SELECT |
30878 | #define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30879 | #define CPC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
30880 | #define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
30881 | #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 |
30882 | #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c |
30883 | #define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
30884 | #define CPC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30885 | #define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
30886 | #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L |
30887 | #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L |
30888 | //CPC_PERFCOUNTER0_SELECT1 |
30889 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30890 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30891 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 |
30892 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c |
30893 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30894 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30895 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L |
30896 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L |
30897 | //CPF_PERFCOUNTER1_SELECT |
30898 | #define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30899 | #define CPF_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
30900 | #define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
30901 | #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 |
30902 | #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c |
30903 | #define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
30904 | #define CPF_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30905 | #define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
30906 | #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L |
30907 | #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L |
30908 | //CPF_PERFCOUNTER0_SELECT1 |
30909 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30910 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30911 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 |
30912 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c |
30913 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30914 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30915 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L |
30916 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L |
30917 | //CPF_PERFCOUNTER0_SELECT |
30918 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30919 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30920 | #define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
30921 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 |
30922 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c |
30923 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
30924 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30925 | #define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
30926 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L |
30927 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L |
30928 | //CP_PERFMON_CNTL |
30929 | #define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
30930 | #define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 |
30931 | #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 |
30932 | #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa |
30933 | #define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL |
30934 | #define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L |
30935 | #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L |
30936 | #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L |
30937 | //CPC_PERFCOUNTER0_SELECT |
30938 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30939 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30940 | #define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
30941 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 |
30942 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c |
30943 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
30944 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30945 | #define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
30946 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L |
30947 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L |
30948 | //CPF_TC_PERF_COUNTER_WINDOW_SELECT |
30949 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 |
30950 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e |
30951 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f |
30952 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L |
30953 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L |
30954 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L |
30955 | //CPG_TC_PERF_COUNTER_WINDOW_SELECT |
30956 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 |
30957 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e |
30958 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f |
30959 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL |
30960 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L |
30961 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L |
30962 | //CPF_LATENCY_STATS_SELECT |
30963 | #define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 |
30964 | #define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e |
30965 | #define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f |
30966 | #define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL |
30967 | #define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L |
30968 | #define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L |
30969 | //CPG_LATENCY_STATS_SELECT |
30970 | #define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 |
30971 | #define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e |
30972 | #define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f |
30973 | #define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL |
30974 | #define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L |
30975 | #define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L |
30976 | //CPC_LATENCY_STATS_SELECT |
30977 | #define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 |
30978 | #define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e |
30979 | #define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f |
30980 | #define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL |
30981 | #define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L |
30982 | #define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L |
30983 | //CP_DRAW_OBJECT |
30984 | #define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 |
30985 | #define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL |
30986 | //CP_DRAW_OBJECT_COUNTER |
30987 | #define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 |
30988 | #define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL |
30989 | //CP_DRAW_WINDOW_MASK_HI |
30990 | #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 |
30991 | #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL |
30992 | //CP_DRAW_WINDOW_HI |
30993 | #define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 |
30994 | #define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL |
30995 | //CP_DRAW_WINDOW_LO |
30996 | #define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 |
30997 | #define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 |
30998 | #define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL |
30999 | #define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L |
31000 | //CP_DRAW_WINDOW_CNTL |
31001 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 |
31002 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 |
31003 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 |
31004 | #define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 |
31005 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L |
31006 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L |
31007 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L |
31008 | #define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L |
31009 | //GRBM_PERFCOUNTER0_SELECT |
31010 | #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31011 | #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
31012 | #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
31013 | #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
31014 | #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe |
31015 | #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
31016 | #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
31017 | #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
31018 | #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 |
31019 | #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
31020 | #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
31021 | #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
31022 | #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
31023 | #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
31024 | #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a |
31025 | #define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b |
31026 | #define GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c |
31027 | #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d |
31028 | #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e |
31029 | #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f |
31030 | #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL |
31031 | #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
31032 | #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
31033 | #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
31034 | #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L |
31035 | #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
31036 | #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
31037 | #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
31038 | #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L |
31039 | #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
31040 | #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
31041 | #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
31042 | #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
31043 | #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
31044 | #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L |
31045 | #define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L |
31046 | #define GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L |
31047 | #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L |
31048 | #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L |
31049 | #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L |
31050 | //GRBM_PERFCOUNTER1_SELECT |
31051 | #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31052 | #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
31053 | #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
31054 | #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
31055 | #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe |
31056 | #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
31057 | #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
31058 | #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
31059 | #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 |
31060 | #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
31061 | #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
31062 | #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
31063 | #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
31064 | #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
31065 | #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a |
31066 | #define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b |
31067 | #define GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c |
31068 | #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d |
31069 | #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e |
31070 | #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f |
31071 | #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL |
31072 | #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
31073 | #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
31074 | #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
31075 | #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L |
31076 | #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
31077 | #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
31078 | #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
31079 | #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L |
31080 | #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
31081 | #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
31082 | #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
31083 | #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
31084 | #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
31085 | #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L |
31086 | #define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L |
31087 | #define GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L |
31088 | #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L |
31089 | #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L |
31090 | #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L |
31091 | //GRBM_SE0_PERFCOUNTER_SELECT |
31092 | #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
31093 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
31094 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
31095 | #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
31096 | #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
31097 | #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
31098 | #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
31099 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
31100 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
31101 | #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
31102 | #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
31103 | #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
31104 | #define GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 |
31105 | #define GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
31106 | #define GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
31107 | #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
31108 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
31109 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
31110 | #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
31111 | #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
31112 | #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
31113 | #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
31114 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
31115 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
31116 | #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
31117 | #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
31118 | #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
31119 | #define GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L |
31120 | #define GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
31121 | #define GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
31122 | //GRBM_SE1_PERFCOUNTER_SELECT |
31123 | #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
31124 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
31125 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
31126 | #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
31127 | #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
31128 | #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
31129 | #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
31130 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
31131 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
31132 | #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
31133 | #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
31134 | #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
31135 | #define GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 |
31136 | #define GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
31137 | #define GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
31138 | #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
31139 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
31140 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
31141 | #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
31142 | #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
31143 | #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
31144 | #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
31145 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
31146 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
31147 | #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
31148 | #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
31149 | #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
31150 | #define GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L |
31151 | #define GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
31152 | #define GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
31153 | //GRBM_SE2_PERFCOUNTER_SELECT |
31154 | #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
31155 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
31156 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
31157 | #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
31158 | #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
31159 | #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
31160 | #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
31161 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
31162 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
31163 | #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
31164 | #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
31165 | #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
31166 | #define GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 |
31167 | #define GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
31168 | #define GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
31169 | #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
31170 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
31171 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
31172 | #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
31173 | #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
31174 | #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
31175 | #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
31176 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
31177 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
31178 | #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
31179 | #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
31180 | #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
31181 | #define GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L |
31182 | #define GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
31183 | #define GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
31184 | //GRBM_SE3_PERFCOUNTER_SELECT |
31185 | #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
31186 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
31187 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
31188 | #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
31189 | #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
31190 | #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
31191 | #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
31192 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
31193 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
31194 | #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
31195 | #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
31196 | #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
31197 | #define GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 |
31198 | #define GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
31199 | #define GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
31200 | #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
31201 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
31202 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
31203 | #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
31204 | #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
31205 | #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
31206 | #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
31207 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
31208 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
31209 | #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
31210 | #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
31211 | #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
31212 | #define GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L |
31213 | #define GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
31214 | #define GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
31215 | //GRBM_PERFCOUNTER0_SELECT_HI |
31216 | #define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1 |
31217 | #define GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT 0x2 |
31218 | #define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT 0x3 |
31219 | #define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT 0x4 |
31220 | #define GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT 0x5 |
31221 | #define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT 0x6 |
31222 | #define GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT 0x7 |
31223 | #define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x8 |
31224 | #define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00000002L |
31225 | #define GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK 0x00000004L |
31226 | #define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK 0x00000008L |
31227 | #define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK 0x00000010L |
31228 | #define GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK 0x00000020L |
31229 | #define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK 0x00000040L |
31230 | #define GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK 0x00000080L |
31231 | #define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000100L |
31232 | //GRBM_PERFCOUNTER1_SELECT_HI |
31233 | #define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1 |
31234 | #define GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT 0x2 |
31235 | #define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT 0x3 |
31236 | #define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT 0x4 |
31237 | #define GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT 0x5 |
31238 | #define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT 0x6 |
31239 | #define GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT 0x7 |
31240 | #define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x8 |
31241 | #define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00000002L |
31242 | #define GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK 0x00000004L |
31243 | #define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK 0x00000008L |
31244 | #define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK 0x00000010L |
31245 | #define GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK 0x00000020L |
31246 | #define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK 0x00000040L |
31247 | #define GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK 0x00000080L |
31248 | #define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000100L |
31249 | //GE_PERFCOUNTER0_SELECT |
31250 | #define GE_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 |
31251 | #define GE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31252 | #define GE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31253 | #define GE_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x18 |
31254 | #define GE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x1c |
31255 | #define GE_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL |
31256 | #define GE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31257 | #define GE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31258 | #define GE_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0x0F000000L |
31259 | #define GE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xF0000000L |
31260 | //GE_PERFCOUNTER0_SELECT1 |
31261 | #define GE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31262 | #define GE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31263 | #define GE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
31264 | #define GE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
31265 | #define GE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31266 | #define GE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31267 | #define GE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
31268 | #define GE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
31269 | //GE_PERFCOUNTER1_SELECT |
31270 | #define GE_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 |
31271 | #define GE_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
31272 | #define GE_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
31273 | #define GE_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x18 |
31274 | #define GE_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x1c |
31275 | #define GE_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL |
31276 | #define GE_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31277 | #define GE_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31278 | #define GE_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0x0F000000L |
31279 | #define GE_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xF0000000L |
31280 | //GE_PERFCOUNTER1_SELECT1 |
31281 | #define GE_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
31282 | #define GE_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
31283 | #define GE_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 |
31284 | #define GE_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c |
31285 | #define GE_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31286 | #define GE_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31287 | #define GE_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L |
31288 | #define GE_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L |
31289 | //GE_PERFCOUNTER2_SELECT |
31290 | #define GE_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 |
31291 | #define GE_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
31292 | #define GE_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
31293 | #define GE_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x18 |
31294 | #define GE_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x1c |
31295 | #define GE_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL |
31296 | #define GE_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31297 | #define GE_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
31298 | #define GE_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0x0F000000L |
31299 | #define GE_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xF0000000L |
31300 | //GE_PERFCOUNTER2_SELECT1 |
31301 | #define GE_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
31302 | #define GE_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
31303 | #define GE_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x18 |
31304 | #define GE_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x1c |
31305 | #define GE_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31306 | #define GE_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31307 | #define GE_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0x0F000000L |
31308 | #define GE_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0xF0000000L |
31309 | //GE_PERFCOUNTER3_SELECT |
31310 | #define GE_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 |
31311 | #define GE_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
31312 | #define GE_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
31313 | #define GE_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x18 |
31314 | #define GE_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x1c |
31315 | #define GE_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL |
31316 | #define GE_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31317 | #define GE_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
31318 | #define GE_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0x0F000000L |
31319 | #define GE_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xF0000000L |
31320 | //GE_PERFCOUNTER3_SELECT1 |
31321 | #define GE_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
31322 | #define GE_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
31323 | #define GE_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x18 |
31324 | #define GE_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x1c |
31325 | #define GE_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31326 | #define GE_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31327 | #define GE_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0x0F000000L |
31328 | #define GE_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0xF0000000L |
31329 | //GE_PERFCOUNTER4_SELECT |
31330 | #define GE_PERFCOUNTER4_SELECT__PERF_SEL0__SHIFT 0x0 |
31331 | #define GE_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c |
31332 | #define GE_PERFCOUNTER4_SELECT__PERF_SEL0_MASK 0x000003FFL |
31333 | #define GE_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L |
31334 | //GE_PERFCOUNTER5_SELECT |
31335 | #define GE_PERFCOUNTER5_SELECT__PERF_SEL0__SHIFT 0x0 |
31336 | #define GE_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c |
31337 | #define GE_PERFCOUNTER5_SELECT__PERF_SEL0_MASK 0x000003FFL |
31338 | #define GE_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L |
31339 | //GE_PERFCOUNTER6_SELECT |
31340 | #define GE_PERFCOUNTER6_SELECT__PERF_SEL0__SHIFT 0x0 |
31341 | #define GE_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c |
31342 | #define GE_PERFCOUNTER6_SELECT__PERF_SEL0_MASK 0x000003FFL |
31343 | #define GE_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L |
31344 | //GE_PERFCOUNTER7_SELECT |
31345 | #define GE_PERFCOUNTER7_SELECT__PERF_SEL0__SHIFT 0x0 |
31346 | #define GE_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c |
31347 | #define GE_PERFCOUNTER7_SELECT__PERF_SEL0_MASK 0x000003FFL |
31348 | #define GE_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L |
31349 | //GE_PERFCOUNTER8_SELECT |
31350 | #define GE_PERFCOUNTER8_SELECT__PERF_SEL0__SHIFT 0x0 |
31351 | #define GE_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c |
31352 | #define GE_PERFCOUNTER8_SELECT__PERF_SEL0_MASK 0x000003FFL |
31353 | #define GE_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L |
31354 | //GE_PERFCOUNTER9_SELECT |
31355 | #define GE_PERFCOUNTER9_SELECT__PERF_SEL0__SHIFT 0x0 |
31356 | #define GE_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c |
31357 | #define GE_PERFCOUNTER9_SELECT__PERF_SEL0_MASK 0x000003FFL |
31358 | #define GE_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L |
31359 | //GE_PERFCOUNTER10_SELECT |
31360 | #define GE_PERFCOUNTER10_SELECT__PERF_SEL0__SHIFT 0x0 |
31361 | #define GE_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c |
31362 | #define GE_PERFCOUNTER10_SELECT__PERF_SEL0_MASK 0x000003FFL |
31363 | #define GE_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L |
31364 | //GE_PERFCOUNTER11_SELECT |
31365 | #define GE_PERFCOUNTER11_SELECT__PERF_SEL0__SHIFT 0x0 |
31366 | #define GE_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c |
31367 | #define GE_PERFCOUNTER11_SELECT__PERF_SEL0_MASK 0x000003FFL |
31368 | #define GE_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L |
31369 | //PA_SU_PERFCOUNTER0_SELECT |
31370 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31371 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31372 | #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31373 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31374 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31375 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
31376 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31377 | #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31378 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31379 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31380 | //PA_SU_PERFCOUNTER0_SELECT1 |
31381 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31382 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31383 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
31384 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
31385 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31386 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31387 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31388 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31389 | //PA_SU_PERFCOUNTER1_SELECT |
31390 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31391 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
31392 | #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
31393 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
31394 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
31395 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
31396 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31397 | #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31398 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
31399 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
31400 | //PA_SU_PERFCOUNTER1_SELECT1 |
31401 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
31402 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
31403 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
31404 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
31405 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31406 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31407 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31408 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31409 | //PA_SU_PERFCOUNTER2_SELECT |
31410 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
31411 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
31412 | #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
31413 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
31414 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
31415 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
31416 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31417 | #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
31418 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
31419 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
31420 | //PA_SU_PERFCOUNTER2_SELECT1 |
31421 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
31422 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
31423 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
31424 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
31425 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31426 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31427 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31428 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31429 | //PA_SU_PERFCOUNTER3_SELECT |
31430 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
31431 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
31432 | #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
31433 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
31434 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
31435 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
31436 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31437 | #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
31438 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
31439 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
31440 | //PA_SU_PERFCOUNTER3_SELECT1 |
31441 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
31442 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
31443 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
31444 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
31445 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31446 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31447 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31448 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31449 | //PA_SC_PERFCOUNTER0_SELECT |
31450 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31451 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31452 | #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31453 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31454 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31455 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
31456 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31457 | #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31458 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31459 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31460 | //PA_SC_PERFCOUNTER0_SELECT1 |
31461 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31462 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31463 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
31464 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
31465 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31466 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31467 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31468 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31469 | //PA_SC_PERFCOUNTER1_SELECT |
31470 | #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31471 | #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
31472 | //PA_SC_PERFCOUNTER2_SELECT |
31473 | #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
31474 | #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
31475 | //PA_SC_PERFCOUNTER3_SELECT |
31476 | #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
31477 | #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
31478 | //PA_SC_PERFCOUNTER4_SELECT |
31479 | #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
31480 | #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL |
31481 | //PA_SC_PERFCOUNTER5_SELECT |
31482 | #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
31483 | #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL |
31484 | //PA_SC_PERFCOUNTER6_SELECT |
31485 | #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 |
31486 | #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL |
31487 | //PA_SC_PERFCOUNTER7_SELECT |
31488 | #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 |
31489 | #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL |
31490 | //SPI_PERFCOUNTER0_SELECT |
31491 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31492 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31493 | #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31494 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31495 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31496 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
31497 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31498 | #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31499 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31500 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31501 | //SPI_PERFCOUNTER1_SELECT |
31502 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31503 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
31504 | #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
31505 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
31506 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
31507 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
31508 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31509 | #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31510 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
31511 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
31512 | //SPI_PERFCOUNTER2_SELECT |
31513 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
31514 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
31515 | #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
31516 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
31517 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
31518 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
31519 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31520 | #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
31521 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
31522 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
31523 | //SPI_PERFCOUNTER3_SELECT |
31524 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
31525 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
31526 | #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
31527 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
31528 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
31529 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
31530 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31531 | #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
31532 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
31533 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
31534 | //SPI_PERFCOUNTER0_SELECT1 |
31535 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31536 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31537 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
31538 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
31539 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31540 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31541 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31542 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31543 | //SPI_PERFCOUNTER1_SELECT1 |
31544 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
31545 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
31546 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
31547 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
31548 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31549 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31550 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31551 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31552 | //SPI_PERFCOUNTER2_SELECT1 |
31553 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
31554 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
31555 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
31556 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
31557 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31558 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31559 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31560 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31561 | //SPI_PERFCOUNTER3_SELECT1 |
31562 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
31563 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
31564 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
31565 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
31566 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31567 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31568 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31569 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31570 | //SPI_PERFCOUNTER4_SELECT |
31571 | #define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
31572 | #define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL |
31573 | //SPI_PERFCOUNTER5_SELECT |
31574 | #define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
31575 | #define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL |
31576 | //SPI_PERFCOUNTER_BINS |
31577 | #define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 |
31578 | #define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 |
31579 | #define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 |
31580 | #define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc |
31581 | #define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 |
31582 | #define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 |
31583 | #define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 |
31584 | #define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c |
31585 | #define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL |
31586 | #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L |
31587 | #define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L |
31588 | #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L |
31589 | #define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L |
31590 | #define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L |
31591 | #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L |
31592 | #define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L |
31593 | //SQ_PERFCOUNTER0_SELECT |
31594 | #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31595 | #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31596 | #define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
31597 | #define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31598 | #define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL |
31599 | #define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31600 | #define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
31601 | #define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31602 | //SQ_PERFCOUNTER1_SELECT |
31603 | #define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31604 | #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31605 | #define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
31606 | #define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
31607 | #define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL |
31608 | #define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31609 | #define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
31610 | #define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
31611 | //SQ_PERFCOUNTER2_SELECT |
31612 | #define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
31613 | #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31614 | #define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 |
31615 | #define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
31616 | #define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL |
31617 | #define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31618 | #define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L |
31619 | #define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
31620 | //SQ_PERFCOUNTER3_SELECT |
31621 | #define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
31622 | #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31623 | #define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 |
31624 | #define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
31625 | #define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL |
31626 | #define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31627 | #define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L |
31628 | #define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
31629 | //SQ_PERFCOUNTER4_SELECT |
31630 | #define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
31631 | #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31632 | #define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 |
31633 | #define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c |
31634 | #define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL |
31635 | #define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31636 | #define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L |
31637 | #define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L |
31638 | //SQ_PERFCOUNTER5_SELECT |
31639 | #define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
31640 | #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31641 | #define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 |
31642 | #define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c |
31643 | #define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL |
31644 | #define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31645 | #define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L |
31646 | #define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L |
31647 | //SQ_PERFCOUNTER6_SELECT |
31648 | #define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 |
31649 | #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31650 | #define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 |
31651 | #define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c |
31652 | #define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL |
31653 | #define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31654 | #define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L |
31655 | #define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L |
31656 | //SQ_PERFCOUNTER7_SELECT |
31657 | #define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 |
31658 | #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31659 | #define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 |
31660 | #define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c |
31661 | #define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL |
31662 | #define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31663 | #define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L |
31664 | #define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L |
31665 | //SQ_PERFCOUNTER8_SELECT |
31666 | #define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 |
31667 | #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31668 | #define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 |
31669 | #define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c |
31670 | #define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL |
31671 | #define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31672 | #define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L |
31673 | #define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L |
31674 | //SQ_PERFCOUNTER9_SELECT |
31675 | #define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 |
31676 | #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31677 | #define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 |
31678 | #define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c |
31679 | #define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL |
31680 | #define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31681 | #define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L |
31682 | #define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L |
31683 | //SQ_PERFCOUNTER10_SELECT |
31684 | #define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 |
31685 | #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31686 | #define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 |
31687 | #define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c |
31688 | #define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL |
31689 | #define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31690 | #define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L |
31691 | #define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L |
31692 | //SQ_PERFCOUNTER11_SELECT |
31693 | #define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 |
31694 | #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31695 | #define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 |
31696 | #define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c |
31697 | #define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL |
31698 | #define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31699 | #define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L |
31700 | #define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L |
31701 | //SQ_PERFCOUNTER12_SELECT |
31702 | #define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 |
31703 | #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31704 | #define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 |
31705 | #define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c |
31706 | #define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL |
31707 | #define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31708 | #define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L |
31709 | #define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L |
31710 | //SQ_PERFCOUNTER13_SELECT |
31711 | #define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 |
31712 | #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31713 | #define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 |
31714 | #define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c |
31715 | #define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL |
31716 | #define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31717 | #define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L |
31718 | #define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L |
31719 | //SQ_PERFCOUNTER14_SELECT |
31720 | #define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 |
31721 | #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31722 | #define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 |
31723 | #define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c |
31724 | #define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL |
31725 | #define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31726 | #define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L |
31727 | #define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L |
31728 | //SQ_PERFCOUNTER15_SELECT |
31729 | #define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 |
31730 | #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc |
31731 | #define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 |
31732 | #define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c |
31733 | #define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL |
31734 | #define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L |
31735 | #define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L |
31736 | #define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L |
31737 | //SQ_PERFCOUNTER_CTRL |
31738 | #define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 |
31739 | #define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 |
31740 | #define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 |
31741 | #define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 |
31742 | #define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 |
31743 | #define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 |
31744 | #define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 |
31745 | #define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 |
31746 | #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd |
31747 | #define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L |
31748 | #define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L |
31749 | #define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L |
31750 | #define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L |
31751 | #define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L |
31752 | #define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L |
31753 | #define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L |
31754 | #define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00000300L |
31755 | #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L |
31756 | //SQ_PERFCOUNTER_CTRL2 |
31757 | #define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 |
31758 | #define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L |
31759 | //GCEA_PERFCOUNTER2_SELECT |
31760 | #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
31761 | #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
31762 | #define GCEA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
31763 | #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
31764 | #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
31765 | #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
31766 | #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31767 | #define GCEA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
31768 | #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
31769 | #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
31770 | //GCEA_PERFCOUNTER2_SELECT1 |
31771 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
31772 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
31773 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
31774 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
31775 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31776 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31777 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31778 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31779 | //GCEA_PERFCOUNTER2_MODE |
31780 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT 0x0 |
31781 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT 0x2 |
31782 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT 0x4 |
31783 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT 0x6 |
31784 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT 0x8 |
31785 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT 0xc |
31786 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT 0x10 |
31787 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT 0x14 |
31788 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK 0x00000003L |
31789 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK 0x0000000CL |
31790 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK 0x00000030L |
31791 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK 0x000000C0L |
31792 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK 0x00000F00L |
31793 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK 0x0000F000L |
31794 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK 0x000F0000L |
31795 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK 0x00F00000L |
31796 | //SX_PERFCOUNTER0_SELECT |
31797 | #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 |
31798 | #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa |
31799 | #define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31800 | #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL |
31801 | #define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L |
31802 | #define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31803 | //SX_PERFCOUNTER1_SELECT |
31804 | #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 |
31805 | #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa |
31806 | #define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
31807 | #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL |
31808 | #define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L |
31809 | #define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31810 | //SX_PERFCOUNTER2_SELECT |
31811 | #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 |
31812 | #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa |
31813 | #define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
31814 | #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL |
31815 | #define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L |
31816 | #define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
31817 | //SX_PERFCOUNTER3_SELECT |
31818 | #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 |
31819 | #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa |
31820 | #define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
31821 | #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL |
31822 | #define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L |
31823 | #define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
31824 | //SX_PERFCOUNTER0_SELECT1 |
31825 | #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 |
31826 | #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa |
31827 | #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL |
31828 | #define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L |
31829 | //SX_PERFCOUNTER1_SELECT1 |
31830 | #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 |
31831 | #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa |
31832 | #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL |
31833 | #define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L |
31834 | //GDS_PERFCOUNTER0_SELECT |
31835 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31836 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31837 | #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31838 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31839 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31840 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
31841 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31842 | #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31843 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31844 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31845 | //GDS_PERFCOUNTER1_SELECT |
31846 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31847 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
31848 | #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
31849 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
31850 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
31851 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
31852 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31853 | #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31854 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
31855 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
31856 | //GDS_PERFCOUNTER2_SELECT |
31857 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
31858 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
31859 | #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
31860 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
31861 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
31862 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
31863 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31864 | #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
31865 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
31866 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
31867 | //GDS_PERFCOUNTER3_SELECT |
31868 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
31869 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
31870 | #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
31871 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
31872 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
31873 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
31874 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31875 | #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
31876 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
31877 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
31878 | //GDS_PERFCOUNTER0_SELECT1 |
31879 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31880 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31881 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
31882 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
31883 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31884 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31885 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31886 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31887 | //TA_PERFCOUNTER0_SELECT |
31888 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31889 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31890 | #define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31891 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31892 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31893 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL |
31894 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L |
31895 | #define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31896 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31897 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31898 | //TA_PERFCOUNTER0_SELECT1 |
31899 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31900 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31901 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
31902 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
31903 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL |
31904 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L |
31905 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31906 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31907 | //TA_PERFCOUNTER1_SELECT |
31908 | #define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31909 | #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
31910 | #define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
31911 | #define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL |
31912 | #define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31913 | #define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
31914 | //TD_PERFCOUNTER0_SELECT |
31915 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31916 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31917 | #define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31918 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31919 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31920 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL |
31921 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L |
31922 | #define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31923 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31924 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31925 | //TD_PERFCOUNTER0_SELECT1 |
31926 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31927 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31928 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
31929 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
31930 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL |
31931 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L |
31932 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31933 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31934 | //TD_PERFCOUNTER1_SELECT |
31935 | #define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31936 | #define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
31937 | #define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
31938 | #define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL |
31939 | #define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31940 | #define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
31941 | //TCP_PERFCOUNTER0_SELECT |
31942 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31943 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31944 | #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31945 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31946 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31947 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
31948 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31949 | #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31950 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31951 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31952 | //TCP_PERFCOUNTER0_SELECT1 |
31953 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31954 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31955 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
31956 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
31957 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31958 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31959 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31960 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31961 | //TCP_PERFCOUNTER1_SELECT |
31962 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31963 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
31964 | #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
31965 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
31966 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
31967 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
31968 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31969 | #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31970 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
31971 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
31972 | //TCP_PERFCOUNTER1_SELECT1 |
31973 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
31974 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
31975 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
31976 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
31977 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31978 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31979 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31980 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31981 | //TCP_PERFCOUNTER2_SELECT |
31982 | #define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
31983 | #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
31984 | #define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
31985 | #define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
31986 | #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
31987 | #define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
31988 | //TCP_PERFCOUNTER3_SELECT |
31989 | #define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
31990 | #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
31991 | #define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
31992 | #define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
31993 | #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
31994 | #define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
31995 | //GL2C_PERFCOUNTER0_SELECT |
31996 | #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31997 | #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31998 | #define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31999 | #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
32000 | #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
32001 | #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
32002 | #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32003 | #define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
32004 | #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
32005 | #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
32006 | //GL2C_PERFCOUNTER0_SELECT1 |
32007 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
32008 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
32009 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
32010 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
32011 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32012 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32013 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
32014 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
32015 | //GL2C_PERFCOUNTER1_SELECT |
32016 | #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
32017 | #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
32018 | #define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
32019 | #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
32020 | #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
32021 | #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
32022 | #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32023 | #define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
32024 | #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
32025 | #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
32026 | //GL2C_PERFCOUNTER1_SELECT1 |
32027 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
32028 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
32029 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 |
32030 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c |
32031 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32032 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32033 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L |
32034 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L |
32035 | //GL2C_PERFCOUNTER2_SELECT |
32036 | #define GL2C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
32037 | #define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
32038 | #define GL2C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
32039 | #define GL2C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
32040 | #define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
32041 | #define GL2C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
32042 | //GL2C_PERFCOUNTER3_SELECT |
32043 | #define GL2C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
32044 | #define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
32045 | #define GL2C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
32046 | #define GL2C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
32047 | #define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
32048 | #define GL2C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
32049 | //GL2A_PERFCOUNTER0_SELECT |
32050 | #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
32051 | #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
32052 | #define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
32053 | #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
32054 | #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
32055 | #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
32056 | #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32057 | #define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
32058 | #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
32059 | #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
32060 | //GL2A_PERFCOUNTER0_SELECT1 |
32061 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
32062 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
32063 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
32064 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
32065 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32066 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32067 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
32068 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
32069 | //GL2A_PERFCOUNTER1_SELECT |
32070 | #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
32071 | #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
32072 | #define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
32073 | #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
32074 | #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
32075 | #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
32076 | #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32077 | #define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
32078 | #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
32079 | #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
32080 | //GL2A_PERFCOUNTER1_SELECT1 |
32081 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
32082 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
32083 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 |
32084 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c |
32085 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32086 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32087 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L |
32088 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L |
32089 | //GL2A_PERFCOUNTER2_SELECT |
32090 | #define GL2A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
32091 | #define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
32092 | #define GL2A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
32093 | #define GL2A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
32094 | #define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
32095 | #define GL2A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
32096 | //GL2A_PERFCOUNTER3_SELECT |
32097 | #define GL2A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
32098 | #define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
32099 | #define GL2A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
32100 | #define GL2A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
32101 | #define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
32102 | #define GL2A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
32103 | //GL1C_PERFCOUNTER0_SELECT |
32104 | #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
32105 | #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
32106 | #define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
32107 | #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
32108 | #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
32109 | #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
32110 | #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32111 | #define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
32112 | #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
32113 | #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
32114 | //GL1C_PERFCOUNTER0_SELECT1 |
32115 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
32116 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
32117 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
32118 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
32119 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32120 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32121 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
32122 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
32123 | //GL1C_PERFCOUNTER1_SELECT |
32124 | #define GL1C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
32125 | #define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
32126 | #define GL1C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
32127 | #define GL1C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
32128 | #define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
32129 | #define GL1C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
32130 | //GL1C_PERFCOUNTER2_SELECT |
32131 | #define GL1C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
32132 | #define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
32133 | #define GL1C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
32134 | #define GL1C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
32135 | #define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
32136 | #define GL1C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
32137 | //GL1C_PERFCOUNTER3_SELECT |
32138 | #define GL1C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
32139 | #define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
32140 | #define GL1C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
32141 | #define GL1C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
32142 | #define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
32143 | #define GL1C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
32144 | //CHC_PERFCOUNTER0_SELECT |
32145 | #define CHC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
32146 | #define CHC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
32147 | #define CHC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
32148 | #define CHC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
32149 | #define CHC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
32150 | #define CHC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
32151 | #define CHC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32152 | #define CHC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
32153 | #define CHC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
32154 | #define CHC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
32155 | //CHC_PERFCOUNTER0_SELECT1 |
32156 | #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
32157 | #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
32158 | #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
32159 | #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
32160 | #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32161 | #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32162 | #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
32163 | #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
32164 | //CHC_PERFCOUNTER1_SELECT |
32165 | #define CHC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
32166 | #define CHC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
32167 | #define CHC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
32168 | #define CHC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
32169 | #define CHC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
32170 | #define CHC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
32171 | //CHC_PERFCOUNTER2_SELECT |
32172 | #define CHC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
32173 | #define CHC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
32174 | #define CHC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
32175 | #define CHC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
32176 | #define CHC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
32177 | #define CHC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
32178 | //CHC_PERFCOUNTER3_SELECT |
32179 | #define CHC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
32180 | #define CHC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
32181 | #define CHC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
32182 | #define CHC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
32183 | #define CHC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
32184 | #define CHC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
32185 | //CHCG_PERFCOUNTER0_SELECT |
32186 | #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
32187 | #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
32188 | #define CHCG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
32189 | #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
32190 | #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
32191 | #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
32192 | #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32193 | #define CHCG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
32194 | #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
32195 | #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
32196 | //CHCG_PERFCOUNTER0_SELECT1 |
32197 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
32198 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
32199 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
32200 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
32201 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32202 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32203 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
32204 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
32205 | //CHCG_PERFCOUNTER1_SELECT |
32206 | #define CHCG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
32207 | #define CHCG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
32208 | #define CHCG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
32209 | #define CHCG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
32210 | #define CHCG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
32211 | #define CHCG_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
32212 | //CHCG_PERFCOUNTER2_SELECT |
32213 | #define CHCG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
32214 | #define CHCG_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
32215 | #define CHCG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
32216 | #define CHCG_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
32217 | #define CHCG_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
32218 | #define CHCG_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
32219 | //CHCG_PERFCOUNTER3_SELECT |
32220 | #define CHCG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
32221 | #define CHCG_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
32222 | #define CHCG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
32223 | #define CHCG_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
32224 | #define CHCG_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
32225 | #define CHCG_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
32226 | //CB_PERFCOUNTER_FILTER |
32227 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 |
32228 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 |
32229 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 |
32230 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 |
32231 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa |
32232 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb |
32233 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc |
32234 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd |
32235 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 |
32236 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 |
32237 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 |
32238 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 |
32239 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L |
32240 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL |
32241 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L |
32242 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L |
32243 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L |
32244 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L |
32245 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L |
32246 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L |
32247 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L |
32248 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L |
32249 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L |
32250 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L |
32251 | //CB_PERFCOUNTER0_SELECT |
32252 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
32253 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
32254 | #define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
32255 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
32256 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
32257 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL |
32258 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L |
32259 | #define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
32260 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
32261 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
32262 | //CB_PERFCOUNTER0_SELECT1 |
32263 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
32264 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
32265 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
32266 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
32267 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL |
32268 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L |
32269 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
32270 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
32271 | //CB_PERFCOUNTER1_SELECT |
32272 | #define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
32273 | #define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
32274 | #define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL |
32275 | #define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
32276 | //CB_PERFCOUNTER2_SELECT |
32277 | #define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
32278 | #define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
32279 | #define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL |
32280 | #define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
32281 | //CB_PERFCOUNTER3_SELECT |
32282 | #define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
32283 | #define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
32284 | #define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL |
32285 | #define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
32286 | //DB_PERFCOUNTER0_SELECT |
32287 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
32288 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
32289 | #define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
32290 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
32291 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
32292 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
32293 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32294 | #define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
32295 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
32296 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
32297 | //DB_PERFCOUNTER0_SELECT1 |
32298 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
32299 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
32300 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
32301 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
32302 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32303 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32304 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
32305 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
32306 | //DB_PERFCOUNTER1_SELECT |
32307 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
32308 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
32309 | #define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
32310 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
32311 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
32312 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
32313 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32314 | #define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
32315 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
32316 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
32317 | //DB_PERFCOUNTER1_SELECT1 |
32318 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
32319 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
32320 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
32321 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
32322 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32323 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32324 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
32325 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
32326 | //DB_PERFCOUNTER2_SELECT |
32327 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
32328 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
32329 | #define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
32330 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
32331 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
32332 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
32333 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32334 | #define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
32335 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
32336 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
32337 | //DB_PERFCOUNTER3_SELECT |
32338 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
32339 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
32340 | #define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
32341 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
32342 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
32343 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
32344 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32345 | #define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
32346 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
32347 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
32348 | //RLC_SPM_PERFMON_CNTL |
32349 | #define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 |
32350 | #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc |
32351 | #define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe |
32352 | #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 |
32353 | #define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFFL |
32354 | #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L |
32355 | #define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L |
32356 | #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L |
32357 | //RLC_SPM_PERFMON_RING_BASE_LO |
32358 | #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 |
32359 | #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL |
32360 | //RLC_SPM_PERFMON_RING_BASE_HI |
32361 | #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 |
32362 | #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 |
32363 | #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL |
32364 | #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L |
32365 | //RLC_SPM_PERFMON_RING_SIZE |
32366 | #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 |
32367 | #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL |
32368 | //RLC_SPM_PERFMON_SEGMENT_SIZE |
32369 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 |
32370 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 |
32371 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb |
32372 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 |
32373 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 |
32374 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a |
32375 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f |
32376 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL |
32377 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L |
32378 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L |
32379 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L |
32380 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L |
32381 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L |
32382 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L |
32383 | //RLC_SPM_RING_RDPTR |
32384 | #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 |
32385 | #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL |
32386 | //RLC_SPM_SEGMENT_THRESHOLD |
32387 | #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 |
32388 | #define RLC_SPM_SEGMENT_THRESHOLD__RESERVED__SHIFT 0x8 |
32389 | #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0x000000FFL |
32390 | #define RLC_SPM_SEGMENT_THRESHOLD__RESERVED_MASK 0xFFFFFF00L |
32391 | //RLC_SPM_SE_MUXSEL_ADDR |
32392 | #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 |
32393 | #define RLC_SPM_SE_MUXSEL_ADDR__RESERVED__SHIFT 0x9 |
32394 | #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0x000001FFL |
32395 | #define RLC_SPM_SE_MUXSEL_ADDR__RESERVED_MASK 0xFFFFFE00L |
32396 | //RLC_SPM_SE_MUXSEL_DATA |
32397 | #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 |
32398 | #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL |
32399 | //RLC_SPM_GLOBAL_MUXSEL_ADDR |
32400 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 |
32401 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED__SHIFT 0x8 |
32402 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0x000000FFL |
32403 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED_MASK 0xFFFFFF00L |
32404 | //RLC_SPM_GLOBAL_MUXSEL_DATA |
32405 | #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 |
32406 | #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL |
32407 | //RLC_SPM_DESER_START_SKEW |
32408 | #define RLC_SPM_DESER_START_SKEW__DESER_START_SKEW__SHIFT 0x0 |
32409 | #define RLC_SPM_DESER_START_SKEW__RESERVED__SHIFT 0x7 |
32410 | #define RLC_SPM_DESER_START_SKEW__DESER_START_SKEW_MASK 0x0000007FL |
32411 | #define RLC_SPM_DESER_START_SKEW__RESERVED_MASK 0xFFFFFF80L |
32412 | //RLC_SPM_GLOBALS_SAMPLE_SKEW |
32413 | #define RLC_SPM_GLOBALS_SAMPLE_SKEW__GLOBALS_SAMPLE_SKEW__SHIFT 0x0 |
32414 | #define RLC_SPM_GLOBALS_SAMPLE_SKEW__RESERVED__SHIFT 0x7 |
32415 | #define RLC_SPM_GLOBALS_SAMPLE_SKEW__GLOBALS_SAMPLE_SKEW_MASK 0x0000007FL |
32416 | #define RLC_SPM_GLOBALS_SAMPLE_SKEW__RESERVED_MASK 0xFFFFFF80L |
32417 | //RLC_SPM_GLOBALS_MUXSEL_SKEW |
32418 | #define RLC_SPM_GLOBALS_MUXSEL_SKEW__GLOBALS_MUXSEL_SKEW__SHIFT 0x0 |
32419 | #define RLC_SPM_GLOBALS_MUXSEL_SKEW__RESERVED__SHIFT 0x7 |
32420 | #define RLC_SPM_GLOBALS_MUXSEL_SKEW__GLOBALS_MUXSEL_SKEW_MASK 0x0000007FL |
32421 | #define RLC_SPM_GLOBALS_MUXSEL_SKEW__RESERVED_MASK 0xFFFFFF80L |
32422 | //RLC_SPM_SE_SAMPLE_SKEW |
32423 | #define RLC_SPM_SE_SAMPLE_SKEW__SE_SAMPLE_SKEW__SHIFT 0x0 |
32424 | #define RLC_SPM_SE_SAMPLE_SKEW__RESERVED__SHIFT 0x7 |
32425 | #define RLC_SPM_SE_SAMPLE_SKEW__SE_SAMPLE_SKEW_MASK 0x0000007FL |
32426 | #define RLC_SPM_SE_SAMPLE_SKEW__RESERVED_MASK 0xFFFFFF80L |
32427 | //RLC_SPM_SE_MUXSEL_SKEW |
32428 | #define RLC_SPM_SE_MUXSEL_SKEW__SE_MUXSEL_SKEW__SHIFT 0x0 |
32429 | #define RLC_SPM_SE_MUXSEL_SKEW__RESERVED__SHIFT 0x7 |
32430 | #define RLC_SPM_SE_MUXSEL_SKEW__SE_MUXSEL_SKEW_MASK 0x0000007FL |
32431 | #define RLC_SPM_SE_MUXSEL_SKEW__RESERVED_MASK 0xFFFFFF80L |
32432 | //RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR |
32433 | #define RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR__GLB_SAMPLEDELAY_INDEX__SHIFT 0x0 |
32434 | #define RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR__GLB_SAMPLEDELAY_INDEX_MASK 0xFFFFFFFFL |
32435 | //RLC_SPM_GLB_SAMPLEDELAY_IND_DATA |
32436 | #define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__data__SHIFT 0x0 |
32437 | #define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__RESERVED__SHIFT 0x7 |
32438 | #define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__data_MASK 0x0000007FL |
32439 | #define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__RESERVED_MASK 0xFFFFFF80L |
32440 | //RLC_SPM_SE_SAMPLEDELAY_IND_ADDR |
32441 | #define RLC_SPM_SE_SAMPLEDELAY_IND_ADDR__SE_SAMPLEDELAY_INDEX__SHIFT 0x0 |
32442 | #define RLC_SPM_SE_SAMPLEDELAY_IND_ADDR__SE_SAMPLEDELAY_INDEX_MASK 0xFFFFFFFFL |
32443 | //RLC_SPM_SE_SAMPLEDELAY_IND_DATA |
32444 | #define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__data__SHIFT 0x0 |
32445 | #define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__RESERVED__SHIFT 0x7 |
32446 | #define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__data_MASK 0x0000007FL |
32447 | #define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__RESERVED_MASK 0xFFFFFF80L |
32448 | //RLC_SPM_RING_WRPTR |
32449 | #define RLC_SPM_RING_WRPTR__RESERVED__SHIFT 0x0 |
32450 | #define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR__SHIFT 0x5 |
32451 | #define RLC_SPM_RING_WRPTR__RESERVED_MASK 0x0000001FL |
32452 | #define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR_MASK 0xFFFFFFE0L |
32453 | //RLC_SPM_ACCUM_DATARAM_ADDR |
32454 | #define RLC_SPM_ACCUM_DATARAM_ADDR__addr__SHIFT 0x0 |
32455 | #define RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED__SHIFT 0x7 |
32456 | #define RLC_SPM_ACCUM_DATARAM_ADDR__addr_MASK 0x0000007FL |
32457 | #define RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED_MASK 0xFFFFFF80L |
32458 | //RLC_SPM_ACCUM_DATARAM_DATA |
32459 | #define RLC_SPM_ACCUM_DATARAM_DATA__data__SHIFT 0x0 |
32460 | #define RLC_SPM_ACCUM_DATARAM_DATA__data_MASK 0xFFFFFFFFL |
32461 | //RLC_SPM_ACCUM_CTRLRAM_ADDR |
32462 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR__addr__SHIFT 0x0 |
32463 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED__SHIFT 0x9 |
32464 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR__addr_MASK 0x000001FFL |
32465 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED_MASK 0xFFFFFE00L |
32466 | //RLC_SPM_ACCUM_CTRLRAM_DATA |
32467 | #define RLC_SPM_ACCUM_CTRLRAM_DATA__data__SHIFT 0x0 |
32468 | #define RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED__SHIFT 0x8 |
32469 | #define RLC_SPM_ACCUM_CTRLRAM_DATA__data_MASK 0x000000FFL |
32470 | #define RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED_MASK 0xFFFFFF00L |
32471 | //RLC_SPM_ACCUM_STATUS |
32472 | #define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted__SHIFT 0x0 |
32473 | #define RLC_SPM_ACCUM_STATUS__AccumDone__SHIFT 0x8 |
32474 | #define RLC_SPM_ACCUM_STATUS__SpmDone__SHIFT 0x9 |
32475 | #define RLC_SPM_ACCUM_STATUS__AccumOverflow__SHIFT 0xa |
32476 | #define RLC_SPM_ACCUM_STATUS__AccumArmed__SHIFT 0xb |
32477 | #define RLC_SPM_ACCUM_STATUS__SequenceInProgress__SHIFT 0xc |
32478 | #define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress__SHIFT 0xd |
32479 | #define RLC_SPM_ACCUM_STATUS__AllFifosEmpty__SHIFT 0xe |
32480 | #define RLC_SPM_ACCUM_STATUS__FSMIsIdle__SHIFT 0xf |
32481 | #define RLC_SPM_ACCUM_STATUS__RESERVED__SHIFT 0x10 |
32482 | #define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted_MASK 0x000000FFL |
32483 | #define RLC_SPM_ACCUM_STATUS__AccumDone_MASK 0x00000100L |
32484 | #define RLC_SPM_ACCUM_STATUS__SpmDone_MASK 0x00000200L |
32485 | #define RLC_SPM_ACCUM_STATUS__AccumOverflow_MASK 0x00000400L |
32486 | #define RLC_SPM_ACCUM_STATUS__AccumArmed_MASK 0x00000800L |
32487 | #define RLC_SPM_ACCUM_STATUS__SequenceInProgress_MASK 0x00001000L |
32488 | #define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress_MASK 0x00002000L |
32489 | #define RLC_SPM_ACCUM_STATUS__AllFifosEmpty_MASK 0x00004000L |
32490 | #define RLC_SPM_ACCUM_STATUS__FSMIsIdle_MASK 0x00008000L |
32491 | #define RLC_SPM_ACCUM_STATUS__RESERVED_MASK 0xFFFF0000L |
32492 | //RLC_SPM_ACCUM_CTRL |
32493 | #define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors__SHIFT 0x0 |
32494 | #define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation__SHIFT 0x1 |
32495 | #define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum__SHIFT 0x2 |
32496 | #define RLC_SPM_ACCUM_CTRL__StrobeSpmDoneInt__SHIFT 0x3 |
32497 | #define RLC_SPM_ACCUM_CTRL__StrobeAccumDoneInt__SHIFT 0x4 |
32498 | #define RLC_SPM_ACCUM_CTRL__StrobeResetAccum__SHIFT 0x5 |
32499 | #define RLC_SPM_ACCUM_CTRL__StrobeStartSpm__SHIFT 0x6 |
32500 | #define RLC_SPM_ACCUM_CTRL__RESERVED__SHIFT 0xa |
32501 | #define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors_MASK 0x00000001L |
32502 | #define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation_MASK 0x00000002L |
32503 | #define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum_MASK 0x00000004L |
32504 | #define RLC_SPM_ACCUM_CTRL__StrobeSpmDoneInt_MASK 0x00000008L |
32505 | #define RLC_SPM_ACCUM_CTRL__StrobeAccumDoneInt_MASK 0x00000010L |
32506 | #define RLC_SPM_ACCUM_CTRL__StrobeResetAccum_MASK 0x00000020L |
32507 | #define RLC_SPM_ACCUM_CTRL__StrobeStartSpm_MASK 0x000003C0L |
32508 | #define RLC_SPM_ACCUM_CTRL__RESERVED_MASK 0xFFFFFC00L |
32509 | //RLC_SPM_ACCUM_MODE |
32510 | #define RLC_SPM_ACCUM_MODE__EnableAccum__SHIFT 0x0 |
32511 | #define RLC_SPM_ACCUM_MODE__AutoAccumEn__SHIFT 0x1 |
32512 | #define RLC_SPM_ACCUM_MODE__AutoSpmEn__SHIFT 0x2 |
32513 | #define RLC_SPM_ACCUM_MODE__Globals_LoadOverride__SHIFT 0x3 |
32514 | #define RLC_SPM_ACCUM_MODE__SE0_LoadOverride__SHIFT 0x4 |
32515 | #define RLC_SPM_ACCUM_MODE__SE1_LoadOverride__SHIFT 0x5 |
32516 | #define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable__SHIFT 0x6 |
32517 | #define RLC_SPM_ACCUM_MODE__RESERVED__SHIFT 0x7 |
32518 | #define RLC_SPM_ACCUM_MODE__EnableAccum_MASK 0x00000001L |
32519 | #define RLC_SPM_ACCUM_MODE__AutoAccumEn_MASK 0x00000002L |
32520 | #define RLC_SPM_ACCUM_MODE__AutoSpmEn_MASK 0x00000004L |
32521 | #define RLC_SPM_ACCUM_MODE__Globals_LoadOverride_MASK 0x00000008L |
32522 | #define RLC_SPM_ACCUM_MODE__SE0_LoadOverride_MASK 0x00000010L |
32523 | #define RLC_SPM_ACCUM_MODE__SE1_LoadOverride_MASK 0x00000020L |
32524 | #define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable_MASK 0x00000040L |
32525 | #define RLC_SPM_ACCUM_MODE__RESERVED_MASK 0xFFFFFF80L |
32526 | //RLC_SPM_ACCUM_THRESHOLD |
32527 | #define RLC_SPM_ACCUM_THRESHOLD__Threshold__SHIFT 0x0 |
32528 | #define RLC_SPM_ACCUM_THRESHOLD__RESERVED__SHIFT 0x10 |
32529 | #define RLC_SPM_ACCUM_THRESHOLD__Threshold_MASK 0x0000FFFFL |
32530 | #define RLC_SPM_ACCUM_THRESHOLD__RESERVED_MASK 0xFFFF0000L |
32531 | //RLC_SPM_ACCUM_SAMPLES_REQUESTED |
32532 | #define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested__SHIFT 0x0 |
32533 | #define RLC_SPM_ACCUM_SAMPLES_REQUESTED__RESERVED__SHIFT 0x8 |
32534 | #define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested_MASK 0x000000FFL |
32535 | #define RLC_SPM_ACCUM_SAMPLES_REQUESTED__RESERVED_MASK 0xFFFFFF00L |
32536 | //RLC_SPM_ACCUM_DATARAM_WRCOUNT |
32537 | #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount__SHIFT 0x0 |
32538 | #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED__SHIFT 0x13 |
32539 | #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount_MASK 0x0007FFFFL |
32540 | #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED_MASK 0xFFF80000L |
32541 | //RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE |
32542 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x0 |
32543 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x8 |
32544 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x10 |
32545 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE__SHIFT 0x18 |
32546 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x000000FFL |
32547 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x0000FF00L |
32548 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x00FF0000L |
32549 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE_MASK 0xFF000000L |
32550 | //RLC_SPM_PERFMON_GLB_SEGMENT_SIZE |
32551 | #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 |
32552 | #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0x8 |
32553 | #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__RESERVED__SHIFT 0x10 |
32554 | #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL |
32555 | #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000FF00L |
32556 | #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__RESERVED_MASK 0xFFFF0000L |
32557 | //RLC_SPM_VIRT_CTRL |
32558 | #define RLC_SPM_VIRT_CTRL__PauseSpmSamplingRequest__SHIFT 0x0 |
32559 | #define RLC_SPM_VIRT_CTRL__PauseSpmSamplingRequest_MASK 0x00000001L |
32560 | //RLC_SPM_VIRT_STATUS |
32561 | #define RLC_SPM_VIRT_STATUS__SpmSamplingPaused__SHIFT 0x0 |
32562 | #define RLC_SPM_VIRT_STATUS__SpmSamplingPaused_MASK 0x00000001L |
32563 | //RLC_PERFMON_CNTL |
32564 | #define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
32565 | #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa |
32566 | #define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L |
32567 | #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L |
32568 | //RLC_PERFCOUNTER0_SELECT |
32569 | #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 |
32570 | #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000FFL |
32571 | //RLC_PERFCOUNTER1_SELECT |
32572 | #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 |
32573 | #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000FFL |
32574 | //RLC_GPU_IOV_PERF_CNT_CNTL |
32575 | #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0 |
32576 | #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1 |
32577 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2 |
32578 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3 |
32579 | #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L |
32580 | #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L |
32581 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L |
32582 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L |
32583 | //RLC_GPU_IOV_PERF_CNT_WR_ADDR |
32584 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0 |
32585 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4 |
32586 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6 |
32587 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL |
32588 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L |
32589 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L |
32590 | //RLC_GPU_IOV_PERF_CNT_WR_DATA |
32591 | #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0 |
32592 | #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0xFFFFFFFFL |
32593 | //RLC_GPU_IOV_PERF_CNT_RD_ADDR |
32594 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0 |
32595 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4 |
32596 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6 |
32597 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL |
32598 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L |
32599 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L |
32600 | //RLC_GPU_IOV_PERF_CNT_RD_DATA |
32601 | #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0 |
32602 | #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0xFFFFFFFFL |
32603 | //RLC_PERFMON_CLK_CNTL |
32604 | #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0 |
32605 | #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L |
32606 | //RLC_PERFMON_CLK_CNTL_UCODE |
32607 | #define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT 0x0 |
32608 | #define RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK 0x00000001L |
32609 | //RMI_PERFCOUNTER0_SELECT |
32610 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
32611 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
32612 | #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
32613 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
32614 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
32615 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL |
32616 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L |
32617 | #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
32618 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
32619 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
32620 | //RMI_PERFCOUNTER0_SELECT1 |
32621 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
32622 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
32623 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
32624 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
32625 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL |
32626 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L |
32627 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
32628 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
32629 | //RMI_PERFCOUNTER1_SELECT |
32630 | #define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
32631 | #define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
32632 | #define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL |
32633 | #define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
32634 | //RMI_PERFCOUNTER2_SELECT |
32635 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
32636 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
32637 | #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
32638 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
32639 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
32640 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL |
32641 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L |
32642 | #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
32643 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
32644 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
32645 | //RMI_PERFCOUNTER2_SELECT1 |
32646 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
32647 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
32648 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
32649 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
32650 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL |
32651 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L |
32652 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
32653 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
32654 | //RMI_PERFCOUNTER3_SELECT |
32655 | #define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
32656 | #define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
32657 | #define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL |
32658 | #define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
32659 | //RMI_PERF_COUNTER_CNTL |
32660 | #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0 |
32661 | #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2 |
32662 | #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4 |
32663 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6 |
32664 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8 |
32665 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa |
32666 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe |
32667 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13 |
32668 | #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19 |
32669 | #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a |
32670 | #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L |
32671 | #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL |
32672 | #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L |
32673 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L |
32674 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L |
32675 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L |
32676 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L |
32677 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L |
32678 | #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L |
32679 | #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L |
32680 | //GCR_PERFCOUNTER0_SELECT |
32681 | #define GCR_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
32682 | #define GCR_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
32683 | #define GCR_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
32684 | #define GCR_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
32685 | #define GCR_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
32686 | #define GCR_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL |
32687 | #define GCR_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L |
32688 | #define GCR_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
32689 | #define GCR_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
32690 | #define GCR_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
32691 | //GCR_PERFCOUNTER0_SELECT1 |
32692 | #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
32693 | #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
32694 | #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
32695 | #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
32696 | #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL |
32697 | #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L |
32698 | #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
32699 | #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
32700 | //GCR_PERFCOUNTER1_SELECT |
32701 | #define GCR_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
32702 | #define GCR_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x18 |
32703 | #define GCR_PERFCOUNTER1_SELECT__CNTL_MODE__SHIFT 0x1c |
32704 | #define GCR_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL |
32705 | #define GCR_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0x0F000000L |
32706 | #define GCR_PERFCOUNTER1_SELECT__CNTL_MODE_MASK 0xF0000000L |
32707 | //UTCL1_PERFCOUNTER0_SELECT |
32708 | #define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
32709 | #define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE__SHIFT 0x1c |
32710 | #define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
32711 | #define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE_MASK 0xF0000000L |
32712 | //UTCL1_PERFCOUNTER1_SELECT |
32713 | #define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
32714 | #define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT 0x1c |
32715 | #define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
32716 | #define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK 0xF0000000L |
32717 | //PA_PH_PERFCOUNTER0_SELECT |
32718 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
32719 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
32720 | #define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
32721 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
32722 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
32723 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
32724 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32725 | #define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
32726 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
32727 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
32728 | //PA_PH_PERFCOUNTER0_SELECT1 |
32729 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
32730 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
32731 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
32732 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
32733 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32734 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32735 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
32736 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
32737 | //PA_PH_PERFCOUNTER1_SELECT |
32738 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
32739 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
32740 | #define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
32741 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
32742 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
32743 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
32744 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32745 | #define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
32746 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
32747 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
32748 | //PA_PH_PERFCOUNTER2_SELECT |
32749 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
32750 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
32751 | #define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
32752 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
32753 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
32754 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
32755 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32756 | #define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
32757 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
32758 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
32759 | //PA_PH_PERFCOUNTER3_SELECT |
32760 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
32761 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
32762 | #define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
32763 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
32764 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
32765 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
32766 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32767 | #define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
32768 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
32769 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
32770 | //PA_PH_PERFCOUNTER4_SELECT |
32771 | #define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
32772 | #define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL |
32773 | //PA_PH_PERFCOUNTER5_SELECT |
32774 | #define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
32775 | #define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL |
32776 | //PA_PH_PERFCOUNTER6_SELECT |
32777 | #define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 |
32778 | #define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL |
32779 | //PA_PH_PERFCOUNTER7_SELECT |
32780 | #define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 |
32781 | #define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL |
32782 | //PA_PH_PERFCOUNTER1_SELECT1 |
32783 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
32784 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
32785 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
32786 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
32787 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32788 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32789 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
32790 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
32791 | //PA_PH_PERFCOUNTER2_SELECT1 |
32792 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
32793 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
32794 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
32795 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
32796 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32797 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32798 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
32799 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
32800 | //PA_PH_PERFCOUNTER3_SELECT1 |
32801 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
32802 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
32803 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
32804 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
32805 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32806 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32807 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
32808 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
32809 | //GL1A_PERFCOUNTER0_SELECT |
32810 | #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
32811 | #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
32812 | #define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
32813 | #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
32814 | #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
32815 | #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
32816 | #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32817 | #define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
32818 | #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
32819 | #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
32820 | //GL1A_PERFCOUNTER0_SELECT1 |
32821 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
32822 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
32823 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
32824 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
32825 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32826 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32827 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
32828 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
32829 | //GL1A_PERFCOUNTER1_SELECT |
32830 | #define GL1A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
32831 | #define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
32832 | #define GL1A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
32833 | #define GL1A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
32834 | #define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
32835 | #define GL1A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
32836 | //GL1A_PERFCOUNTER2_SELECT |
32837 | #define GL1A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
32838 | #define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
32839 | #define GL1A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
32840 | #define GL1A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
32841 | #define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
32842 | #define GL1A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
32843 | //GL1A_PERFCOUNTER3_SELECT |
32844 | #define GL1A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
32845 | #define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
32846 | #define GL1A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
32847 | #define GL1A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
32848 | #define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
32849 | #define GL1A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
32850 | //CHA_PERFCOUNTER0_SELECT |
32851 | #define CHA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
32852 | #define CHA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
32853 | #define CHA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
32854 | #define CHA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
32855 | #define CHA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
32856 | #define CHA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
32857 | #define CHA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32858 | #define CHA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
32859 | #define CHA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
32860 | #define CHA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
32861 | //CHA_PERFCOUNTER0_SELECT1 |
32862 | #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
32863 | #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
32864 | #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
32865 | #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
32866 | #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32867 | #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32868 | #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
32869 | #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
32870 | //CHA_PERFCOUNTER1_SELECT |
32871 | #define CHA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
32872 | #define CHA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
32873 | #define CHA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
32874 | #define CHA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
32875 | #define CHA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
32876 | #define CHA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
32877 | //CHA_PERFCOUNTER2_SELECT |
32878 | #define CHA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
32879 | #define CHA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
32880 | #define CHA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
32881 | #define CHA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
32882 | #define CHA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
32883 | #define CHA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
32884 | //CHA_PERFCOUNTER3_SELECT |
32885 | #define CHA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
32886 | #define CHA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
32887 | #define CHA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
32888 | #define CHA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
32889 | #define CHA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
32890 | #define CHA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
32891 | //GUS_PERFCOUNTER2_SELECT |
32892 | #define GUS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
32893 | #define GUS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
32894 | #define GUS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
32895 | #define GUS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
32896 | #define GUS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
32897 | #define GUS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
32898 | #define GUS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32899 | #define GUS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
32900 | #define GUS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
32901 | #define GUS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
32902 | //GUS_PERFCOUNTER2_SELECT1 |
32903 | #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
32904 | #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
32905 | #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
32906 | #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
32907 | #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32908 | #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32909 | #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
32910 | #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
32911 | //GUS_PERFCOUNTER2_MODE |
32912 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT 0x0 |
32913 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT 0x2 |
32914 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT 0x4 |
32915 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT 0x6 |
32916 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT 0x8 |
32917 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT 0xc |
32918 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT 0x10 |
32919 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT 0x14 |
32920 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK 0x00000003L |
32921 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK 0x0000000CL |
32922 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK 0x00000030L |
32923 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK 0x000000C0L |
32924 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK 0x00000F00L |
32925 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK 0x0000F000L |
32926 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK 0x000F0000L |
32927 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK 0x00F00000L |
32928 | |
32929 | |
32930 | // addressBlock: gc_gcatcl2pfcntldec |
32931 | //GC_ATC_L2_PERFCOUNTER0_CFG |
32932 | #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
32933 | #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
32934 | #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
32935 | #define GC_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
32936 | #define GC_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
32937 | #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
32938 | #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
32939 | #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
32940 | #define GC_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
32941 | #define GC_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
32942 | //GC_ATC_L2_PERFCOUNTER1_CFG |
32943 | #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
32944 | #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
32945 | #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
32946 | #define GC_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
32947 | #define GC_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
32948 | #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
32949 | #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
32950 | #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
32951 | #define GC_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
32952 | #define GC_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
32953 | //GC_ATC_L2_PERFCOUNTER_RSLT_CNTL |
32954 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
32955 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
32956 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
32957 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
32958 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
32959 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
32960 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
32961 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
32962 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
32963 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
32964 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
32965 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
32966 | |
32967 | |
32968 | // addressBlock: gc_gcvml2pldec |
32969 | //GCMC_VM_L2_PERFCOUNTER0_CFG |
32970 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
32971 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
32972 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
32973 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
32974 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
32975 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
32976 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
32977 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
32978 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
32979 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
32980 | //GCMC_VM_L2_PERFCOUNTER1_CFG |
32981 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
32982 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
32983 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
32984 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
32985 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
32986 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
32987 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
32988 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
32989 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
32990 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
32991 | //GCMC_VM_L2_PERFCOUNTER2_CFG |
32992 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
32993 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
32994 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
32995 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
32996 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
32997 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
32998 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
32999 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
33000 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
33001 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
33002 | //GCMC_VM_L2_PERFCOUNTER3_CFG |
33003 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 |
33004 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 |
33005 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 |
33006 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c |
33007 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d |
33008 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL |
33009 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L |
33010 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L |
33011 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L |
33012 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L |
33013 | //GCMC_VM_L2_PERFCOUNTER4_CFG |
33014 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 |
33015 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 |
33016 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 |
33017 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c |
33018 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d |
33019 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL |
33020 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L |
33021 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L |
33022 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L |
33023 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L |
33024 | //GCMC_VM_L2_PERFCOUNTER5_CFG |
33025 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 |
33026 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 |
33027 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 |
33028 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c |
33029 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d |
33030 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL |
33031 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L |
33032 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L |
33033 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L |
33034 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L |
33035 | //GCMC_VM_L2_PERFCOUNTER6_CFG |
33036 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 |
33037 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 |
33038 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 |
33039 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c |
33040 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d |
33041 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL |
33042 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L |
33043 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L |
33044 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L |
33045 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L |
33046 | //GCMC_VM_L2_PERFCOUNTER7_CFG |
33047 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 |
33048 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 |
33049 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 |
33050 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c |
33051 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d |
33052 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL |
33053 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L |
33054 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L |
33055 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L |
33056 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L |
33057 | //GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL |
33058 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
33059 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
33060 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
33061 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
33062 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
33063 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
33064 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
33065 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
33066 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
33067 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
33068 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
33069 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
33070 | |
33071 | |
33072 | // addressBlock: gc_gcvml2perfsdec |
33073 | //GCVML2_PERFCOUNTER2_0_SELECT |
33074 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL__SHIFT 0x0 |
33075 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1__SHIFT 0xa |
33076 | #define GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE__SHIFT 0x14 |
33077 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1__SHIFT 0x18 |
33078 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE__SHIFT 0x1c |
33079 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL_MASK 0x000003FFL |
33080 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
33081 | #define GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE_MASK 0x00F00000L |
33082 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1_MASK 0x0F000000L |
33083 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE_MASK 0xF0000000L |
33084 | //GCVML2_PERFCOUNTER2_1_SELECT |
33085 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL__SHIFT 0x0 |
33086 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1__SHIFT 0xa |
33087 | #define GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE__SHIFT 0x14 |
33088 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1__SHIFT 0x18 |
33089 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE__SHIFT 0x1c |
33090 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL_MASK 0x000003FFL |
33091 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
33092 | #define GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE_MASK 0x00F00000L |
33093 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1_MASK 0x0F000000L |
33094 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE_MASK 0xF0000000L |
33095 | //GCVML2_PERFCOUNTER2_0_SELECT1 |
33096 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2__SHIFT 0x0 |
33097 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3__SHIFT 0xa |
33098 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3__SHIFT 0x18 |
33099 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2__SHIFT 0x1c |
33100 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
33101 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
33102 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
33103 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
33104 | //GCVML2_PERFCOUNTER2_1_SELECT1 |
33105 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2__SHIFT 0x0 |
33106 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3__SHIFT 0xa |
33107 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3__SHIFT 0x18 |
33108 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2__SHIFT 0x1c |
33109 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
33110 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
33111 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
33112 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
33113 | //GCVML2_PERFCOUNTER2_0_MODE |
33114 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0__SHIFT 0x0 |
33115 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1__SHIFT 0x2 |
33116 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2__SHIFT 0x4 |
33117 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3__SHIFT 0x6 |
33118 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0__SHIFT 0x8 |
33119 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1__SHIFT 0xc |
33120 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2__SHIFT 0x10 |
33121 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3__SHIFT 0x14 |
33122 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0_MASK 0x00000003L |
33123 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1_MASK 0x0000000CL |
33124 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2_MASK 0x00000030L |
33125 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3_MASK 0x000000C0L |
33126 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0_MASK 0x00000F00L |
33127 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1_MASK 0x0000F000L |
33128 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2_MASK 0x000F0000L |
33129 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3_MASK 0x00F00000L |
33130 | //GCVML2_PERFCOUNTER2_1_MODE |
33131 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0__SHIFT 0x0 |
33132 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1__SHIFT 0x2 |
33133 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2__SHIFT 0x4 |
33134 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3__SHIFT 0x6 |
33135 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0__SHIFT 0x8 |
33136 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1__SHIFT 0xc |
33137 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2__SHIFT 0x10 |
33138 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3__SHIFT 0x14 |
33139 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0_MASK 0x00000003L |
33140 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1_MASK 0x0000000CL |
33141 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2_MASK 0x00000030L |
33142 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3_MASK 0x000000C0L |
33143 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0_MASK 0x00000F00L |
33144 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1_MASK 0x0000F000L |
33145 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2_MASK 0x000F0000L |
33146 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3_MASK 0x00F00000L |
33147 | |
33148 | |
33149 | // addressBlock: gc_gcatcl2perfsdec |
33150 | //GC_ATC_L2_PERFCOUNTER2_SELECT |
33151 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
33152 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
33153 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
33154 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
33155 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
33156 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
33157 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
33158 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
33159 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
33160 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
33161 | //GC_ATC_L2_PERFCOUNTER2_SELECT1 |
33162 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
33163 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
33164 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
33165 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
33166 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
33167 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
33168 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
33169 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
33170 | //GC_ATC_L2_PERFCOUNTER2_MODE |
33171 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT 0x0 |
33172 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT 0x2 |
33173 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT 0x4 |
33174 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT 0x6 |
33175 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT 0x8 |
33176 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT 0xc |
33177 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT 0x10 |
33178 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT 0x14 |
33179 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK 0x00000003L |
33180 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK 0x0000000CL |
33181 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK 0x00000030L |
33182 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK 0x000000C0L |
33183 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK 0x00000F00L |
33184 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK 0x0000F000L |
33185 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK 0x000F0000L |
33186 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK 0x00F00000L |
33187 | |
33188 | |
33189 | // addressBlock: gc_rlcdec |
33190 | //RLC_CNTL |
33191 | #define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 |
33192 | #define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 |
33193 | #define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 |
33194 | #define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 |
33195 | #define RLC_CNTL__RESERVED__SHIFT 0x4 |
33196 | #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L |
33197 | #define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L |
33198 | #define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L |
33199 | #define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L |
33200 | #define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L |
33201 | //RLC_F32_UCODE_VERSION |
33202 | #define RLC_F32_UCODE_VERSION__THREAD0_VERSION__SHIFT 0x0 |
33203 | #define RLC_F32_UCODE_VERSION__THREAD1_VERSION__SHIFT 0xa |
33204 | #define RLC_F32_UCODE_VERSION__THREAD2_VERSION__SHIFT 0x14 |
33205 | #define RLC_F32_UCODE_VERSION__THREAD0_VERSION_MASK 0x000003FFL |
33206 | #define RLC_F32_UCODE_VERSION__THREAD1_VERSION_MASK 0x000FFC00L |
33207 | #define RLC_F32_UCODE_VERSION__THREAD2_VERSION_MASK 0x3FF00000L |
33208 | //RLC_STAT |
33209 | #define RLC_STAT__RLC_BUSY__SHIFT 0x0 |
33210 | #define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x1 |
33211 | #define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x2 |
33212 | #define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x3 |
33213 | #define RLC_STAT__MC_BUSY__SHIFT 0x4 |
33214 | #define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5 |
33215 | #define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6 |
33216 | #define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7 |
33217 | #define RLC_STAT__RESERVED__SHIFT 0x8 |
33218 | #define RLC_STAT__RLC_BUSY_MASK 0x00000001L |
33219 | #define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000002L |
33220 | #define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000004L |
33221 | #define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000008L |
33222 | #define RLC_STAT__MC_BUSY_MASK 0x00000010L |
33223 | #define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L |
33224 | #define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L |
33225 | #define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L |
33226 | #define RLC_STAT__RESERVED_MASK 0xFFFFFF00L |
33227 | //RLC_SAFE_MODE |
33228 | #define RLC_SAFE_MODE__CMD__SHIFT 0x0 |
33229 | #define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 |
33230 | #define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 |
33231 | #define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 |
33232 | #define RLC_SAFE_MODE__RESERVED__SHIFT 0xc |
33233 | #define RLC_SAFE_MODE__CMD_MASK 0x00000001L |
33234 | #define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL |
33235 | #define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L |
33236 | #define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L |
33237 | #define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L |
33238 | //RLC_MEM_SLP_CNTL |
33239 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 |
33240 | #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 |
33241 | #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 |
33242 | #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 |
33243 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 |
33244 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 |
33245 | #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 |
33246 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L |
33247 | #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L |
33248 | #define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL |
33249 | #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L |
33250 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L |
33251 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L |
33252 | #define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L |
33253 | //SMU_RLC_RESPONSE |
33254 | #define SMU_RLC_RESPONSE__RESP__SHIFT 0x0 |
33255 | #define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL |
33256 | //RLC_RLCV_SAFE_MODE |
33257 | #define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 |
33258 | #define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 |
33259 | #define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 |
33260 | #define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 |
33261 | #define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc |
33262 | #define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L |
33263 | #define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL |
33264 | #define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L |
33265 | #define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L |
33266 | #define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L |
33267 | //RLC_SMU_SAFE_MODE |
33268 | #define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 |
33269 | #define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 |
33270 | #define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 |
33271 | #define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 |
33272 | #define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc |
33273 | #define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L |
33274 | #define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL |
33275 | #define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L |
33276 | #define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L |
33277 | #define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L |
33278 | //RLC_RLCV_COMMAND |
33279 | #define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 |
33280 | #define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 |
33281 | #define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL |
33282 | #define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L |
33283 | //RLC_REFCLOCK_TIMESTAMP_LSB |
33284 | #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0 |
33285 | #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL |
33286 | //RLC_REFCLOCK_TIMESTAMP_MSB |
33287 | #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0 |
33288 | #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL |
33289 | //RLC_GPM_TIMER_INT_0 |
33290 | #define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0 |
33291 | #define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL |
33292 | //RLC_GPM_TIMER_INT_1 |
33293 | #define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0 |
33294 | #define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL |
33295 | //RLC_GPM_TIMER_INT_2 |
33296 | #define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0 |
33297 | #define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL |
33298 | //RLC_GPM_TIMER_CTRL |
33299 | #define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 |
33300 | #define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 |
33301 | #define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2 |
33302 | #define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3 |
33303 | #define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x4 |
33304 | #define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x5 |
33305 | #define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM__SHIFT 0x6 |
33306 | #define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM__SHIFT 0x7 |
33307 | #define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x8 |
33308 | #define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x9 |
33309 | #define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR__SHIFT 0xa |
33310 | #define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR__SHIFT 0xb |
33311 | #define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0xc |
33312 | #define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L |
33313 | #define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L |
33314 | #define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L |
33315 | #define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L |
33316 | #define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000010L |
33317 | #define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000020L |
33318 | #define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM_MASK 0x00000040L |
33319 | #define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM_MASK 0x00000080L |
33320 | #define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00000100L |
33321 | #define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00000200L |
33322 | #define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR_MASK 0x00000400L |
33323 | #define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR_MASK 0x00000800L |
33324 | #define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFF000L |
33325 | //RLC_LB_CNTR_MAX_1 |
33326 | #define RLC_LB_CNTR_MAX_1__LB_CNTR_MAX__SHIFT 0x0 |
33327 | #define RLC_LB_CNTR_MAX_1__LB_CNTR_MAX_MASK 0xFFFFFFFFL |
33328 | //RLC_GPM_TIMER_STAT |
33329 | #define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 |
33330 | #define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 |
33331 | #define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2 |
33332 | #define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3 |
33333 | #define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 |
33334 | #define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 |
33335 | #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa |
33336 | #define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT 0xb |
33337 | #define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xc |
33338 | #define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0xd |
33339 | #define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC__SHIFT 0xe |
33340 | #define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC__SHIFT 0xf |
33341 | #define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x10 |
33342 | #define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L |
33343 | #define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L |
33344 | #define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L |
33345 | #define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L |
33346 | #define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L |
33347 | #define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L |
33348 | #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK 0x00000400L |
33349 | #define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK 0x00000800L |
33350 | #define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00001000L |
33351 | #define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00002000L |
33352 | #define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC_MASK 0x00004000L |
33353 | #define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC_MASK 0x00008000L |
33354 | #define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFF0000L |
33355 | //RLC_GPM_TIMER_INT_3 |
33356 | #define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0 |
33357 | #define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL |
33358 | //RLC_INT_STAT |
33359 | #define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0 |
33360 | #define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8 |
33361 | #define RLC_INT_STAT__RESERVED__SHIFT 0x9 |
33362 | #define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL |
33363 | #define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L |
33364 | #define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L |
33365 | //RLC_LB_CNTL |
33366 | #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 |
33367 | #define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 |
33368 | #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 |
33369 | #define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 |
33370 | #define RLC_LB_CNTL__RESERVED__SHIFT 0x4 |
33371 | #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L |
33372 | #define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L |
33373 | #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L |
33374 | #define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L |
33375 | #define RLC_LB_CNTL__RESERVED_MASK 0xFFFFFFF0L |
33376 | //RLC_MGCG_CTRL |
33377 | #define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 |
33378 | #define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 |
33379 | #define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 |
33380 | #define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 |
33381 | #define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 |
33382 | #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf |
33383 | #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10 |
33384 | #define RLC_MGCG_CTRL__SPARE__SHIFT 0x11 |
33385 | #define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L |
33386 | #define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L |
33387 | #define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L |
33388 | #define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L |
33389 | #define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L |
33390 | #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L |
33391 | #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L |
33392 | #define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L |
33393 | //RLC_LB_CNTR_INIT_1 |
33394 | #define RLC_LB_CNTR_INIT_1__LB_CNTR_INIT__SHIFT 0x0 |
33395 | #define RLC_LB_CNTR_INIT_1__LB_CNTR_INIT_MASK 0xFFFFFFFFL |
33396 | //RLC_LB_CNTR_1 |
33397 | #define RLC_LB_CNTR_1__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 |
33398 | #define RLC_LB_CNTR_1__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL |
33399 | //RLC_JUMP_TABLE_RESTORE |
33400 | #define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 |
33401 | #define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL |
33402 | //RLC_PG_DELAY_2 |
33403 | #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 |
33404 | #define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 |
33405 | #define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE__SHIFT 0x10 |
33406 | #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL |
33407 | #define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L |
33408 | #define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE_MASK 0xFFFF0000L |
33409 | //RLC_GPU_CLOCK_COUNT_LSB |
33410 | #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 |
33411 | #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
33412 | //RLC_GPU_CLOCK_COUNT_MSB |
33413 | #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 |
33414 | #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
33415 | //RLC_CAPTURE_GPU_CLOCK_COUNT |
33416 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 |
33417 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 |
33418 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L |
33419 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL |
33420 | //RLC_UCODE_CNTL |
33421 | #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 |
33422 | #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL |
33423 | //RLC_GPM_THREAD_RESET |
33424 | #define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 |
33425 | #define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 |
33426 | #define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 |
33427 | #define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 |
33428 | #define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 |
33429 | #define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L |
33430 | #define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L |
33431 | #define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L |
33432 | #define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L |
33433 | #define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L |
33434 | //RLC_GPM_CP_DMA_COMPLETE_T0 |
33435 | #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0 |
33436 | #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1 |
33437 | #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L |
33438 | #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL |
33439 | //RLC_GPM_CP_DMA_COMPLETE_T1 |
33440 | #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0 |
33441 | #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1 |
33442 | #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L |
33443 | #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL |
33444 | //RLC_LB_CNTR_INIT_2 |
33445 | #define RLC_LB_CNTR_INIT_2__LB_CNTR_INIT__SHIFT 0x0 |
33446 | #define RLC_LB_CNTR_INIT_2__LB_CNTR_INIT_MASK 0xFFFFFFFFL |
33447 | //RLC_LB_CNTR_MAX_2 |
33448 | #define RLC_LB_CNTR_MAX_2__LB_CNTR_MAX__SHIFT 0x0 |
33449 | #define RLC_LB_CNTR_MAX_2__LB_CNTR_MAX_MASK 0xFFFFFFFFL |
33450 | //RLC_LB_CONFIG_5 |
33451 | #define RLC_LB_CONFIG_5__DATA__SHIFT 0x0 |
33452 | #define RLC_LB_CONFIG_5__DATA_MASK 0xFFFFFFFFL |
33453 | //RLC_CLK_COUNT_GFXCLK_LSB |
33454 | #define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT 0x0 |
33455 | #define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK 0xFFFFFFFFL |
33456 | //RLC_CLK_COUNT_GFXCLK_MSB |
33457 | #define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT 0x0 |
33458 | #define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK 0xFFFFFFFFL |
33459 | //RLC_CLK_COUNT_REFCLK_LSB |
33460 | #define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT 0x0 |
33461 | #define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK 0xFFFFFFFFL |
33462 | //RLC_CLK_COUNT_REFCLK_MSB |
33463 | #define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT 0x0 |
33464 | #define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK 0xFFFFFFFFL |
33465 | //RLC_CLK_COUNT_CTRL |
33466 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT 0x0 |
33467 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT 0x1 |
33468 | #define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT 0x2 |
33469 | #define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT 0x3 |
33470 | #define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT 0x4 |
33471 | #define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT 0x5 |
33472 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK 0x00000001L |
33473 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK 0x00000002L |
33474 | #define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK 0x00000004L |
33475 | #define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK 0x00000008L |
33476 | #define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK 0x00000010L |
33477 | #define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK 0x00000020L |
33478 | //RLC_CLK_COUNT_STAT |
33479 | #define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT 0x0 |
33480 | #define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT 0x1 |
33481 | #define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT 0x2 |
33482 | #define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT 0x3 |
33483 | #define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT 0x4 |
33484 | #define RLC_CLK_COUNT_STAT__RESERVED__SHIFT 0x5 |
33485 | #define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK 0x00000001L |
33486 | #define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK 0x00000002L |
33487 | #define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK 0x00000004L |
33488 | #define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK 0x00000008L |
33489 | #define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK 0x00000010L |
33490 | #define RLC_CLK_COUNT_STAT__RESERVED_MASK 0xFFFFFFE0L |
33491 | //RLC_GPU_CLOCK_32_RES_SEL |
33492 | #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 |
33493 | #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 |
33494 | #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL |
33495 | #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L |
33496 | //RLC_GPU_CLOCK_32 |
33497 | #define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 |
33498 | #define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL |
33499 | //RLC_PG_CNTL |
33500 | #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 |
33501 | #define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 |
33502 | #define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE__SHIFT 0x2 |
33503 | #define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE__SHIFT 0x3 |
33504 | #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 |
33505 | #define RLC_PG_CNTL__RESERVED__SHIFT 0x5 |
33506 | #define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe |
33507 | #define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf |
33508 | #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 |
33509 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 |
33510 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 |
33511 | #define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13 |
33512 | #define RLC_PG_CNTL__RESERVED1__SHIFT 0x14 |
33513 | #define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT 0x15 |
33514 | #define RLC_PG_CNTL__RESERVED2__SHIFT 0x16 |
33515 | #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L |
33516 | #define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L |
33517 | #define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE_MASK 0x00000004L |
33518 | #define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE_MASK 0x00000008L |
33519 | #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L |
33520 | #define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L |
33521 | #define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L |
33522 | #define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L |
33523 | #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L |
33524 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L |
33525 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L |
33526 | #define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x00080000L |
33527 | #define RLC_PG_CNTL__RESERVED1_MASK 0x00100000L |
33528 | #define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK 0x00200000L |
33529 | #define RLC_PG_CNTL__RESERVED2_MASK 0x00C00000L |
33530 | //RLC_GPM_THREAD_PRIORITY |
33531 | #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 |
33532 | #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 |
33533 | #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 |
33534 | #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 |
33535 | #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL |
33536 | #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L |
33537 | #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L |
33538 | #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L |
33539 | //RLC_GPM_THREAD_ENABLE |
33540 | #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 |
33541 | #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 |
33542 | #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 |
33543 | #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 |
33544 | #define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 |
33545 | #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L |
33546 | #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L |
33547 | #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L |
33548 | #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L |
33549 | #define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L |
33550 | //RLC_CGTT_MGCG_OVERRIDE |
33551 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0__SHIFT 0x0 |
33552 | #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1 |
33553 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2 |
33554 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3 |
33555 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4 |
33556 | #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5 |
33557 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6 |
33558 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7 |
33559 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT 0x8 |
33560 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_9__SHIFT 0x9 |
33561 | #define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY__SHIFT 0x10 |
33562 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17__SHIFT 0x11 |
33563 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0_MASK 0x00000001L |
33564 | #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L |
33565 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L |
33566 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L |
33567 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L |
33568 | #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L |
33569 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L |
33570 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L |
33571 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK 0x00000100L |
33572 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_9_MASK 0x0000FE00L |
33573 | #define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK 0x00010000L |
33574 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17_MASK 0xFFFE0000L |
33575 | //RLC_CGCG_CGLS_CTRL |
33576 | #define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 |
33577 | #define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 |
33578 | #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 |
33579 | #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 |
33580 | #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b |
33581 | #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c |
33582 | #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d |
33583 | #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f |
33584 | #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L |
33585 | #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L |
33586 | #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL |
33587 | #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L |
33588 | #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L |
33589 | #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L |
33590 | #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L |
33591 | #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L |
33592 | //RLC_CGCG_RAMP_CTRL |
33593 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 |
33594 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 |
33595 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 |
33596 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc |
33597 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 |
33598 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c |
33599 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL |
33600 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L |
33601 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L |
33602 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L |
33603 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L |
33604 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L |
33605 | //RLC_DYN_PG_STATUS |
33606 | #define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT 0x0 |
33607 | #define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK_MASK 0xFFFFFFFFL |
33608 | //RLC_DYN_PG_REQUEST |
33609 | #define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK__SHIFT 0x0 |
33610 | #define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK_MASK 0xFFFFFFFFL |
33611 | //RLC_PG_DELAY |
33612 | #define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 |
33613 | #define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 |
33614 | #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 |
33615 | #define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 |
33616 | #define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL |
33617 | #define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L |
33618 | #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L |
33619 | #define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L |
33620 | //RLC_WGP_STATUS |
33621 | #define RLC_WGP_STATUS__WORK_PENDING__SHIFT 0x0 |
33622 | #define RLC_WGP_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL |
33623 | //RLC_LB_INIT_WGP_MASK |
33624 | #define RLC_LB_INIT_WGP_MASK__INIT_WGP_MASK__SHIFT 0x0 |
33625 | #define RLC_LB_INIT_WGP_MASK__INIT_WGP_MASK_MASK 0xFFFFFFFFL |
33626 | //RLC_LB_ALWAYS_ACTIVE_WGP_MASK |
33627 | #define RLC_LB_ALWAYS_ACTIVE_WGP_MASK__ALWAYS_ACTIVE_WGP_MASK__SHIFT 0x0 |
33628 | #define RLC_LB_ALWAYS_ACTIVE_WGP_MASK__ALWAYS_ACTIVE_WGP_MASK_MASK 0xFFFFFFFFL |
33629 | //RLC_LB_PARAMS |
33630 | #define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 |
33631 | #define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 |
33632 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 |
33633 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 |
33634 | #define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L |
33635 | #define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL |
33636 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L |
33637 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L |
33638 | //RLC_LB_DELAY |
33639 | #define RLC_LB_DELAY__WGP_IDLE_DELAY__SHIFT 0x0 |
33640 | #define RLC_LB_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 |
33641 | #define RLC_LB_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 |
33642 | #define RLC_LB_DELAY__SPARE__SHIFT 0x18 |
33643 | #define RLC_LB_DELAY__WGP_IDLE_DELAY_MASK 0x000000FFL |
33644 | #define RLC_LB_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L |
33645 | #define RLC_LB_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L |
33646 | #define RLC_LB_DELAY__SPARE_MASK 0xFF000000L |
33647 | //RLC_PG_ALWAYS_ON_WGP_MASK |
33648 | #define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK__SHIFT 0x0 |
33649 | #define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK 0xFFFFFFFFL |
33650 | //RLC_MAX_PG_WGP |
33651 | #define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP__SHIFT 0x0 |
33652 | #define RLC_MAX_PG_WGP__SPARE__SHIFT 0x8 |
33653 | #define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP_MASK 0x000000FFL |
33654 | #define RLC_MAX_PG_WGP__SPARE_MASK 0xFFFFFF00L |
33655 | //RLC_AUTO_PG_CTRL |
33656 | #define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 |
33657 | #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 |
33658 | #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 |
33659 | #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 |
33660 | #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 |
33661 | #define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L |
33662 | #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L |
33663 | #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L |
33664 | #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L |
33665 | #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L |
33666 | //RLC_SMU_GRBM_REG_SAVE_CTRL |
33667 | #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 |
33668 | #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 |
33669 | #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L |
33670 | #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xFFFFFFFEL |
33671 | //RLC_SERDES_RD_INDEX |
33672 | #define RLC_SERDES_RD_INDEX__DATA_REG_ID__SHIFT 0x0 |
33673 | #define RLC_SERDES_RD_INDEX__SPARE__SHIFT 0x2 |
33674 | #define RLC_SERDES_RD_INDEX__DATA_REG_ID_MASK 0x00000003L |
33675 | #define RLC_SERDES_RD_INDEX__SPARE_MASK 0xFFFFFFFCL |
33676 | //RLC_SERDES_RD_DATA_0 |
33677 | #define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 |
33678 | #define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL |
33679 | //RLC_SERDES_RD_DATA_1 |
33680 | #define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 |
33681 | #define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL |
33682 | //RLC_SERDES_RD_DATA_2 |
33683 | #define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 |
33684 | #define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL |
33685 | //RLC_SERDES_RD_DATA_3 |
33686 | #define RLC_SERDES_RD_DATA_3__DATA__SHIFT 0x0 |
33687 | #define RLC_SERDES_RD_DATA_3__DATA_MASK 0xFFFFFFFFL |
33688 | //RLC_SERDES_MASK |
33689 | #define RLC_SERDES_MASK__GC_CENTER_HUB_0__SHIFT 0x0 |
33690 | #define RLC_SERDES_MASK__GC_CENTER_HUB_1__SHIFT 0x1 |
33691 | #define RLC_SERDES_MASK__RESERVED__SHIFT 0x2 |
33692 | #define RLC_SERDES_MASK__GC_SE_0__SHIFT 0x10 |
33693 | #define RLC_SERDES_MASK__GC_SE_1__SHIFT 0x11 |
33694 | #define RLC_SERDES_MASK__GC_SE_2__SHIFT 0x12 |
33695 | #define RLC_SERDES_MASK__GC_SE_3__SHIFT 0x13 |
33696 | #define RLC_SERDES_MASK__RESERVED_1__SHIFT 0x14 |
33697 | #define RLC_SERDES_MASK__GC_CENTER_HUB_0_MASK 0x00000001L |
33698 | #define RLC_SERDES_MASK__GC_CENTER_HUB_1_MASK 0x00000002L |
33699 | #define RLC_SERDES_MASK__RESERVED_MASK 0x0000FFFCL |
33700 | #define RLC_SERDES_MASK__GC_SE_0_MASK 0x00010000L |
33701 | #define RLC_SERDES_MASK__GC_SE_1_MASK 0x00020000L |
33702 | #define RLC_SERDES_MASK__GC_SE_2_MASK 0x00040000L |
33703 | #define RLC_SERDES_MASK__GC_SE_3_MASK 0x00080000L |
33704 | #define RLC_SERDES_MASK__RESERVED_1_MASK 0xFFF00000L |
33705 | //RLC_SERDES_CTRL |
33706 | #define RLC_SERDES_CTRL__BPM_BROADCAST__SHIFT 0x0 |
33707 | #define RLC_SERDES_CTRL__BPM_REG_WRITE__SHIFT 0x1 |
33708 | #define RLC_SERDES_CTRL__BPM_LONG_CMD__SHIFT 0x2 |
33709 | #define RLC_SERDES_CTRL__BPM_ADDR__SHIFT 0x3 |
33710 | #define RLC_SERDES_CTRL__REG_ADDR__SHIFT 0x10 |
33711 | #define RLC_SERDES_CTRL__BPM_BROADCAST_MASK 0x000001L |
33712 | #define RLC_SERDES_CTRL__BPM_REG_WRITE_MASK 0x000002L |
33713 | #define RLC_SERDES_CTRL__BPM_LONG_CMD_MASK 0x000004L |
33714 | #define RLC_SERDES_CTRL__BPM_ADDR_MASK 0x00FFF8L |
33715 | #define RLC_SERDES_CTRL__REG_ADDR_MASK 0xFF0000L |
33716 | //RLC_SERDES_DATA |
33717 | #define RLC_SERDES_DATA__DATA__SHIFT 0x0 |
33718 | #define RLC_SERDES_DATA__DATA_MASK 0xFFFFFFFFL |
33719 | //RLC_SERDES_BUSY |
33720 | #define RLC_SERDES_BUSY__GC_CENTER_HUB_0__SHIFT 0x0 |
33721 | #define RLC_SERDES_BUSY__GC_CENTER_HUB_1__SHIFT 0x1 |
33722 | #define RLC_SERDES_BUSY__RESERVED__SHIFT 0x2 |
33723 | #define RLC_SERDES_BUSY__GC_SE_0__SHIFT 0x10 |
33724 | #define RLC_SERDES_BUSY__GC_SE_1__SHIFT 0x11 |
33725 | #define RLC_SERDES_BUSY__GC_SE_2__SHIFT 0x12 |
33726 | #define RLC_SERDES_BUSY__GC_SE_3__SHIFT 0x13 |
33727 | #define RLC_SERDES_BUSY__RESERVED_29_20__SHIFT 0x14 |
33728 | #define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY__SHIFT 0x1e |
33729 | #define RLC_SERDES_BUSY__RD_PENDING__SHIFT 0x1f |
33730 | #define RLC_SERDES_BUSY__GC_CENTER_HUB_0_MASK 0x00000001L |
33731 | #define RLC_SERDES_BUSY__GC_CENTER_HUB_1_MASK 0x00000002L |
33732 | #define RLC_SERDES_BUSY__RESERVED_MASK 0x0000FFFCL |
33733 | #define RLC_SERDES_BUSY__GC_SE_0_MASK 0x00010000L |
33734 | #define RLC_SERDES_BUSY__GC_SE_1_MASK 0x00020000L |
33735 | #define RLC_SERDES_BUSY__GC_SE_2_MASK 0x00040000L |
33736 | #define RLC_SERDES_BUSY__GC_SE_3_MASK 0x00080000L |
33737 | #define RLC_SERDES_BUSY__RESERVED_29_20_MASK 0x3FF00000L |
33738 | #define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY_MASK 0x40000000L |
33739 | #define RLC_SERDES_BUSY__RD_PENDING_MASK 0x80000000L |
33740 | //RLC_GPM_GENERAL_0 |
33741 | #define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 |
33742 | #define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL |
33743 | //RLC_GPM_GENERAL_1 |
33744 | #define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 |
33745 | #define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL |
33746 | //RLC_GPM_GENERAL_2 |
33747 | #define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 |
33748 | #define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL |
33749 | //RLC_GPM_GENERAL_3 |
33750 | #define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 |
33751 | #define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL |
33752 | //RLC_GPM_GENERAL_4 |
33753 | #define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 |
33754 | #define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL |
33755 | //RLC_GPM_GENERAL_5 |
33756 | #define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 |
33757 | #define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL |
33758 | //RLC_GPM_GENERAL_6 |
33759 | #define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 |
33760 | #define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL |
33761 | //RLC_GPM_GENERAL_7 |
33762 | #define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 |
33763 | #define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL |
33764 | //RLC_STATIC_PG_STATUS |
33765 | #define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT 0x0 |
33766 | #define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK_MASK 0xFFFFFFFFL |
33767 | //RLC_SPM_INT_INFO_1 |
33768 | #define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 |
33769 | #define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL |
33770 | //RLC_SPM_INT_INFO_2 |
33771 | #define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 |
33772 | #define RLC_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 |
33773 | #define RLC_SPM_INT_INFO_2__RESERVED__SHIFT 0x18 |
33774 | #define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL |
33775 | #define RLC_SPM_INT_INFO_2__INTERRUPT_ID_MASK 0x00FF0000L |
33776 | #define RLC_SPM_INT_INFO_2__RESERVED_MASK 0xFF000000L |
33777 | //RLC_SPM_MC_CNTL |
33778 | #define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0 |
33779 | #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4 |
33780 | #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x6 |
33781 | #define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x7 |
33782 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x8 |
33783 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x9 |
33784 | #define RLC_SPM_MC_CNTL__RLC_SPM_BC__SHIFT 0xc |
33785 | #define RLC_SPM_MC_CNTL__RESERVED_2__SHIFT 0xd |
33786 | #define RLC_SPM_MC_CNTL__RLC_SPM_VOL__SHIFT 0xe |
33787 | #define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL__SHIFT 0xf |
33788 | #define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0x10 |
33789 | #define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL |
33790 | #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000030L |
33791 | #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000040L |
33792 | #define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000080L |
33793 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000100L |
33794 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000E00L |
33795 | #define RLC_SPM_MC_CNTL__RLC_SPM_BC_MASK 0x00001000L |
33796 | #define RLC_SPM_MC_CNTL__RESERVED_2_MASK 0x00002000L |
33797 | #define RLC_SPM_MC_CNTL__RLC_SPM_VOL_MASK 0x00004000L |
33798 | #define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL_MASK 0x00008000L |
33799 | #define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFF0000L |
33800 | //RLC_SPM_INT_CNTL |
33801 | #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 |
33802 | #define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 |
33803 | #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L |
33804 | #define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL |
33805 | //RLC_SPM_INT_STATUS |
33806 | #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 |
33807 | #define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 |
33808 | #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L |
33809 | #define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL |
33810 | //RLC_SMU_MESSAGE |
33811 | #define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 |
33812 | #define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL |
33813 | //RLC_GPM_LOG_SIZE |
33814 | #define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 |
33815 | #define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL |
33816 | //RLC_PG_DELAY_3 |
33817 | #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 |
33818 | #define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 |
33819 | #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL |
33820 | #define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L |
33821 | //RLC_GPR_REG1 |
33822 | #define RLC_GPR_REG1__DATA__SHIFT 0x0 |
33823 | #define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL |
33824 | //RLC_GPR_REG2 |
33825 | #define RLC_GPR_REG2__DATA__SHIFT 0x0 |
33826 | #define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL |
33827 | //RLC_GPM_LOG_CONT |
33828 | #define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 |
33829 | #define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL |
33830 | //RLC_GPM_INT_DISABLE_TH0 |
33831 | #define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0 |
33832 | #define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL |
33833 | //RLC_GPM_INT_FORCE_TH0 |
33834 | #define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0 |
33835 | #define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL |
33836 | //RLC_SRM_CNTL |
33837 | #define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 |
33838 | #define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 |
33839 | #define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 |
33840 | #define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L |
33841 | #define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L |
33842 | #define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL |
33843 | //RLC_SRM_GPM_COMMAND |
33844 | #define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 |
33845 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 |
33846 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 |
33847 | #define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 |
33848 | #define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11 |
33849 | #define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d |
33850 | #define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f |
33851 | #define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L |
33852 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L |
33853 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL |
33854 | #define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0001FFE0L |
33855 | #define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L |
33856 | #define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000L |
33857 | #define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L |
33858 | //RLC_SRM_GPM_COMMAND_STATUS |
33859 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 |
33860 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 |
33861 | #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 |
33862 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L |
33863 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L |
33864 | #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL |
33865 | //RLC_SRM_RLCV_COMMAND |
33866 | #define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0 |
33867 | #define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1 |
33868 | #define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4 |
33869 | #define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10 |
33870 | #define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c |
33871 | #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f |
33872 | #define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L |
33873 | #define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL |
33874 | #define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L |
33875 | #define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L |
33876 | #define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L |
33877 | #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L |
33878 | //RLC_SRM_RLCV_COMMAND_STATUS |
33879 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 |
33880 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 |
33881 | #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2 |
33882 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L |
33883 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L |
33884 | #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL |
33885 | //RLC_SRM_INDEX_CNTL_ADDR_0 |
33886 | #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 |
33887 | #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10 |
33888 | #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL |
33889 | #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L |
33890 | //RLC_SRM_INDEX_CNTL_ADDR_1 |
33891 | #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 |
33892 | #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10 |
33893 | #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL |
33894 | #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L |
33895 | //RLC_SRM_INDEX_CNTL_ADDR_2 |
33896 | #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 |
33897 | #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10 |
33898 | #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL |
33899 | #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L |
33900 | //RLC_SRM_INDEX_CNTL_ADDR_3 |
33901 | #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 |
33902 | #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10 |
33903 | #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL |
33904 | #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L |
33905 | //RLC_SRM_INDEX_CNTL_ADDR_4 |
33906 | #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 |
33907 | #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10 |
33908 | #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL |
33909 | #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L |
33910 | //RLC_SRM_INDEX_CNTL_ADDR_5 |
33911 | #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 |
33912 | #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10 |
33913 | #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL |
33914 | #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L |
33915 | //RLC_SRM_INDEX_CNTL_ADDR_6 |
33916 | #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 |
33917 | #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10 |
33918 | #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL |
33919 | #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L |
33920 | //RLC_SRM_INDEX_CNTL_ADDR_7 |
33921 | #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 |
33922 | #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10 |
33923 | #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL |
33924 | #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L |
33925 | //RLC_SRM_INDEX_CNTL_DATA_0 |
33926 | #define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 |
33927 | #define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL |
33928 | //RLC_SRM_INDEX_CNTL_DATA_1 |
33929 | #define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 |
33930 | #define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL |
33931 | //RLC_SRM_INDEX_CNTL_DATA_2 |
33932 | #define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 |
33933 | #define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL |
33934 | //RLC_SRM_INDEX_CNTL_DATA_3 |
33935 | #define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 |
33936 | #define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL |
33937 | //RLC_SRM_INDEX_CNTL_DATA_4 |
33938 | #define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 |
33939 | #define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL |
33940 | //RLC_SRM_INDEX_CNTL_DATA_5 |
33941 | #define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 |
33942 | #define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL |
33943 | //RLC_SRM_INDEX_CNTL_DATA_6 |
33944 | #define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 |
33945 | #define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL |
33946 | //RLC_SRM_INDEX_CNTL_DATA_7 |
33947 | #define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 |
33948 | #define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL |
33949 | //RLC_SRM_STAT |
33950 | #define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0 |
33951 | #define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1 |
33952 | #define RLC_SRM_STAT__RESERVED__SHIFT 0x2 |
33953 | #define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L |
33954 | #define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L |
33955 | #define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL |
33956 | //RLC_SRM_GPM_ABORT |
33957 | #define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 |
33958 | #define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 |
33959 | #define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L |
33960 | #define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL |
33961 | //RLC_CSIB_ADDR_LO |
33962 | #define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 |
33963 | #define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL |
33964 | //RLC_CSIB_ADDR_HI |
33965 | #define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 |
33966 | #define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL |
33967 | //RLC_CSIB_LENGTH |
33968 | #define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 |
33969 | #define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL |
33970 | //RLC_PACE_INT_STAT |
33971 | #define RLC_PACE_INT_STAT__STATUS__SHIFT 0x0 |
33972 | #define RLC_PACE_INT_STAT__STATUS_MASK 0xFFFFFFFFL |
33973 | //RLC_SMU_COMMAND |
33974 | #define RLC_SMU_COMMAND__CMD__SHIFT 0x0 |
33975 | #define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL |
33976 | //RLC_CP_SCHEDULERS |
33977 | #define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 |
33978 | #define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 |
33979 | #define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10 |
33980 | #define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18 |
33981 | #define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL |
33982 | #define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L |
33983 | #define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L |
33984 | #define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L |
33985 | //RLC_SMU_ARGUMENT_1 |
33986 | #define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0 |
33987 | #define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL |
33988 | //RLC_SMU_ARGUMENT_2 |
33989 | #define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0 |
33990 | #define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL |
33991 | //RLC_GPM_GENERAL_8 |
33992 | #define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 |
33993 | #define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL |
33994 | //RLC_GPM_GENERAL_9 |
33995 | #define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 |
33996 | #define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL |
33997 | //RLC_GPM_GENERAL_10 |
33998 | #define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 |
33999 | #define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL |
34000 | //RLC_GPM_GENERAL_11 |
34001 | #define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 |
34002 | #define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL |
34003 | //RLC_GPM_GENERAL_12 |
34004 | #define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 |
34005 | #define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL |
34006 | //RLC_GPM_UTCL1_CNTL_0 |
34007 | #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
34008 | #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18 |
34009 | #define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19 |
34010 | #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a |
34011 | #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b |
34012 | #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c |
34013 | #define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e |
34014 | #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
34015 | #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L |
34016 | #define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L |
34017 | #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L |
34018 | #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L |
34019 | #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L |
34020 | #define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L |
34021 | //RLC_GPM_UTCL1_CNTL_1 |
34022 | #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
34023 | #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18 |
34024 | #define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19 |
34025 | #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a |
34026 | #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b |
34027 | #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c |
34028 | #define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e |
34029 | #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
34030 | #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L |
34031 | #define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L |
34032 | #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L |
34033 | #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L |
34034 | #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L |
34035 | #define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L |
34036 | //RLC_GPM_UTCL1_CNTL_2 |
34037 | #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
34038 | #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18 |
34039 | #define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19 |
34040 | #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a |
34041 | #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b |
34042 | #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c |
34043 | #define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e |
34044 | #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
34045 | #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L |
34046 | #define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L |
34047 | #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L |
34048 | #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L |
34049 | #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L |
34050 | #define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L |
34051 | //RLC_SPM_UTCL1_CNTL |
34052 | #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
34053 | #define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
34054 | #define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
34055 | #define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
34056 | #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
34057 | #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
34058 | #define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e |
34059 | #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
34060 | #define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
34061 | #define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
34062 | #define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
34063 | #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
34064 | #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
34065 | #define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L |
34066 | //RLC_UTCL1_STATUS_2 |
34067 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0 |
34068 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1 |
34069 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2 |
34070 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3 |
34071 | #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4 |
34072 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5 |
34073 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6 |
34074 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7 |
34075 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8 |
34076 | #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9 |
34077 | #define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa |
34078 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L |
34079 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L |
34080 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L |
34081 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L |
34082 | #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L |
34083 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L |
34084 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L |
34085 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L |
34086 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L |
34087 | #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L |
34088 | #define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L |
34089 | //RLC_LB_CONFIG_2 |
34090 | #define RLC_LB_CONFIG_2__DATA__SHIFT 0x0 |
34091 | #define RLC_LB_CONFIG_2__DATA_MASK 0xFFFFFFFFL |
34092 | //RLC_LB_CONFIG_3 |
34093 | #define RLC_LB_CONFIG_3__DATA__SHIFT 0x0 |
34094 | #define RLC_LB_CONFIG_3__DATA_MASK 0xFFFFFFFFL |
34095 | //RLC_LB_CONFIG_4 |
34096 | #define RLC_LB_CONFIG_4__DATA__SHIFT 0x0 |
34097 | #define RLC_LB_CONFIG_4__DATA_MASK 0xFFFFFFFFL |
34098 | //RLC_SPM_UTCL1_ERROR_1 |
34099 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 |
34100 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
34101 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
34102 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L |
34103 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
34104 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
34105 | //RLC_SPM_UTCL1_ERROR_2 |
34106 | #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
34107 | #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
34108 | //RLC_GPM_UTCL1_TH0_ERROR_1 |
34109 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0 |
34110 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
34111 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
34112 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L |
34113 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
34114 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
34115 | //RLC_LB_CONFIG_1 |
34116 | #define RLC_LB_CONFIG_1__DATA__SHIFT 0x0 |
34117 | #define RLC_LB_CONFIG_1__DATA_MASK 0xFFFFFFFFL |
34118 | //RLC_GPM_UTCL1_TH0_ERROR_2 |
34119 | #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
34120 | #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
34121 | //RLC_GPM_UTCL1_TH1_ERROR_1 |
34122 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0 |
34123 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
34124 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
34125 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L |
34126 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
34127 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
34128 | //RLC_GPM_UTCL1_TH1_ERROR_2 |
34129 | #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
34130 | #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
34131 | //RLC_GPM_UTCL1_TH2_ERROR_1 |
34132 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0 |
34133 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
34134 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
34135 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L |
34136 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
34137 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
34138 | //RLC_GPM_UTCL1_TH2_ERROR_2 |
34139 | #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
34140 | #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
34141 | //RLC_CGCG_CGLS_CTRL_3D |
34142 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0 |
34143 | #define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1 |
34144 | #define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 |
34145 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 |
34146 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b |
34147 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c |
34148 | #define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d |
34149 | #define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f |
34150 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L |
34151 | #define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L |
34152 | #define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL |
34153 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L |
34154 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L |
34155 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L |
34156 | #define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L |
34157 | #define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L |
34158 | //RLC_CGCG_RAMP_CTRL_3D |
34159 | #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0 |
34160 | #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4 |
34161 | #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8 |
34162 | #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc |
34163 | #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10 |
34164 | #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c |
34165 | #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL |
34166 | #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L |
34167 | #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L |
34168 | #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L |
34169 | #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L |
34170 | #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L |
34171 | //RLC_SEMAPHORE_0 |
34172 | #define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 |
34173 | #define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5 |
34174 | #define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL |
34175 | #define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L |
34176 | //RLC_SEMAPHORE_1 |
34177 | #define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 |
34178 | #define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5 |
34179 | #define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL |
34180 | #define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L |
34181 | //RLC_CP_EOF_INT |
34182 | #define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0 |
34183 | #define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1 |
34184 | #define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L |
34185 | #define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL |
34186 | //RLC_CP_EOF_INT_CNT |
34187 | #define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0 |
34188 | #define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL |
34189 | //RLC_SPARE_INT |
34190 | #define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0 |
34191 | #define RLC_SPARE_INT__RESERVED__SHIFT 0x1 |
34192 | #define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L |
34193 | #define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL |
34194 | //RLC_PREWALKER_UTCL1_CNTL |
34195 | #define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
34196 | #define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
34197 | #define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
34198 | #define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
34199 | #define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
34200 | #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
34201 | #define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e |
34202 | #define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
34203 | #define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
34204 | #define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
34205 | #define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
34206 | #define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
34207 | #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
34208 | #define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L |
34209 | //RLC_PREWALKER_UTCL1_TRIG |
34210 | #define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0 |
34211 | #define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1 |
34212 | #define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5 |
34213 | #define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6 |
34214 | #define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7 |
34215 | #define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8 |
34216 | #define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9 |
34217 | #define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f |
34218 | #define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L |
34219 | #define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL |
34220 | #define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L |
34221 | #define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L |
34222 | #define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L |
34223 | #define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L |
34224 | #define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L |
34225 | #define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L |
34226 | //RLC_PREWALKER_UTCL1_ADDR_LSB |
34227 | #define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0 |
34228 | #define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL |
34229 | //RLC_PREWALKER_UTCL1_ADDR_MSB |
34230 | #define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0 |
34231 | #define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL |
34232 | //RLC_PREWALKER_UTCL1_SIZE_LSB |
34233 | #define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0 |
34234 | #define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL |
34235 | //RLC_PREWALKER_UTCL1_SIZE_MSB |
34236 | #define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0 |
34237 | #define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L |
34238 | //RLC_UTCL1_STATUS |
34239 | #define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
34240 | #define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
34241 | #define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
34242 | #define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3 |
34243 | #define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
34244 | #define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe |
34245 | #define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
34246 | #define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16 |
34247 | #define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
34248 | #define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e |
34249 | #define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
34250 | #define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
34251 | #define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
34252 | #define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L |
34253 | #define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
34254 | #define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L |
34255 | #define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
34256 | #define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L |
34257 | #define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
34258 | #define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L |
34259 | //RLC_R2I_CNTL_0 |
34260 | #define RLC_R2I_CNTL_0__Data__SHIFT 0x0 |
34261 | #define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL |
34262 | //RLC_R2I_CNTL_1 |
34263 | #define RLC_R2I_CNTL_1__Data__SHIFT 0x0 |
34264 | #define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL |
34265 | //RLC_R2I_CNTL_2 |
34266 | #define RLC_R2I_CNTL_2__Data__SHIFT 0x0 |
34267 | #define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL |
34268 | //RLC_R2I_CNTL_3 |
34269 | #define RLC_R2I_CNTL_3__Data__SHIFT 0x0 |
34270 | #define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL |
34271 | //RLC_LB_WGP_STAT |
34272 | #define RLC_LB_WGP_STAT__MAX_WGP__SHIFT 0x0 |
34273 | #define RLC_LB_WGP_STAT__ON_WGP__SHIFT 0x10 |
34274 | #define RLC_LB_WGP_STAT__MAX_WGP_MASK 0x0000FFFFL |
34275 | #define RLC_LB_WGP_STAT__ON_WGP_MASK 0xFFFF0000L |
34276 | //RLC_GPM_INT_STAT_TH0 |
34277 | #define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT 0x0 |
34278 | #define RLC_GPM_INT_STAT_TH0__STATUS_MASK 0xFFFFFFFFL |
34279 | //RLC_GPM_GENERAL_13 |
34280 | #define RLC_GPM_GENERAL_13__DATA__SHIFT 0x0 |
34281 | #define RLC_GPM_GENERAL_13__DATA_MASK 0xFFFFFFFFL |
34282 | //RLC_GPM_GENERAL_14 |
34283 | #define RLC_GPM_GENERAL_14__DATA__SHIFT 0x0 |
34284 | #define RLC_GPM_GENERAL_14__DATA_MASK 0xFFFFFFFFL |
34285 | //RLC_GPM_GENERAL_15 |
34286 | #define RLC_GPM_GENERAL_15__DATA__SHIFT 0x0 |
34287 | #define RLC_GPM_GENERAL_15__DATA_MASK 0xFFFFFFFFL |
34288 | //RLC_SPARE_INT_1 |
34289 | #define RLC_SPARE_INT_1__INTERRUPT__SHIFT 0x0 |
34290 | #define RLC_SPARE_INT_1__RESERVED__SHIFT 0x1 |
34291 | #define RLC_SPARE_INT_1__INTERRUPT_MASK 0x00000001L |
34292 | #define RLC_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL |
34293 | //RLC_RLCV_SPARE_INT_1 |
34294 | #define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT 0x0 |
34295 | #define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT 0x1 |
34296 | #define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK 0x00000001L |
34297 | #define RLC_RLCV_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL |
34298 | //RLC_PACE_SPARE_INT_1 |
34299 | #define RLC_PACE_SPARE_INT_1__INTERRUPT__SHIFT 0x0 |
34300 | #define RLC_PACE_SPARE_INT_1__RESERVED__SHIFT 0x1 |
34301 | #define RLC_PACE_SPARE_INT_1__INTERRUPT_MASK 0x00000001L |
34302 | #define RLC_PACE_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL |
34303 | //RLC_SEMAPHORE_2 |
34304 | #define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 |
34305 | #define RLC_SEMAPHORE_2__RESERVED__SHIFT 0x5 |
34306 | #define RLC_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL |
34307 | #define RLC_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L |
34308 | //RLC_SEMAPHORE_3 |
34309 | #define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 |
34310 | #define RLC_SEMAPHORE_3__RESERVED__SHIFT 0x5 |
34311 | #define RLC_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL |
34312 | #define RLC_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L |
34313 | //RLC_SMU_ARGUMENT_3 |
34314 | #define RLC_SMU_ARGUMENT_3__ARG__SHIFT 0x0 |
34315 | #define RLC_SMU_ARGUMENT_3__ARG_MASK 0xFFFFFFFFL |
34316 | //RLC_SMU_ARGUMENT_4 |
34317 | #define RLC_SMU_ARGUMENT_4__ARG__SHIFT 0x0 |
34318 | #define RLC_SMU_ARGUMENT_4__ARG_MASK 0xFFFFFFFFL |
34319 | //RLC_GPU_CLOCK_COUNT_LSB_1 |
34320 | #define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT 0x0 |
34321 | #define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
34322 | //RLC_GPU_CLOCK_COUNT_MSB_1 |
34323 | #define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT 0x0 |
34324 | #define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
34325 | //RLC_CAPTURE_GPU_CLOCK_COUNT_1 |
34326 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT 0x0 |
34327 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT 0x1 |
34328 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK 0x00000001L |
34329 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK 0xFFFFFFFEL |
34330 | //RLC_GPU_CLOCK_COUNT_LSB_2 |
34331 | #define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT 0x0 |
34332 | #define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
34333 | //RLC_GPU_CLOCK_COUNT_MSB_2 |
34334 | #define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT 0x0 |
34335 | #define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
34336 | //RLC_PACE_INT_DISABLE |
34337 | #define RLC_PACE_INT_DISABLE__DISABLE__SHIFT 0x0 |
34338 | #define RLC_PACE_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL |
34339 | //RLC_CAPTURE_GPU_CLOCK_COUNT_2 |
34340 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT 0x0 |
34341 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT 0x1 |
34342 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK 0x00000001L |
34343 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK 0xFFFFFFFEL |
34344 | //RLC_RLCV_SPARE_INT |
34345 | #define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 |
34346 | #define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 |
34347 | #define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L |
34348 | #define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL |
34349 | //RLC_PACE_TIMER_INT_0 |
34350 | #define RLC_PACE_TIMER_INT_0__TIMER__SHIFT 0x0 |
34351 | #define RLC_PACE_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL |
34352 | //RLC_PACE_TIMER_CTRL |
34353 | #define RLC_PACE_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 |
34354 | #define RLC_PACE_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 |
34355 | #define RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x2 |
34356 | #define RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x3 |
34357 | #define RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x4 |
34358 | #define RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x5 |
34359 | #define RLC_PACE_TIMER_CTRL__RESERVED__SHIFT 0x6 |
34360 | #define RLC_PACE_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L |
34361 | #define RLC_PACE_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L |
34362 | #define RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000004L |
34363 | #define RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000008L |
34364 | #define RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00000010L |
34365 | #define RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00000020L |
34366 | #define RLC_PACE_TIMER_CTRL__RESERVED_MASK 0xFFFFFFC0L |
34367 | //RLC_PACE_TIMER_INT_1 |
34368 | #define RLC_PACE_TIMER_INT_1__TIMER__SHIFT 0x0 |
34369 | #define RLC_PACE_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL |
34370 | //RLC_PACE_SPARE_INT |
34371 | #define RLC_PACE_SPARE_INT__INTERRUPT__SHIFT 0x0 |
34372 | #define RLC_PACE_SPARE_INT__RESERVED__SHIFT 0x1 |
34373 | #define RLC_PACE_SPARE_INT__INTERRUPT_MASK 0x00000001L |
34374 | #define RLC_PACE_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL |
34375 | //RLC_SMU_CLK_REQ |
34376 | #define RLC_SMU_CLK_REQ__VALID__SHIFT 0x0 |
34377 | #define RLC_SMU_CLK_REQ__VALID_MASK 0x00000001L |
34378 | //RLC_CP_STAT_INVAL_STAT |
34379 | #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND__SHIFT 0x0 |
34380 | #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND__SHIFT 0x1 |
34381 | #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND__SHIFT 0x2 |
34382 | #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED__SHIFT 0x3 |
34383 | #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED__SHIFT 0x4 |
34384 | #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED__SHIFT 0x5 |
34385 | #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_MASK 0x00000001L |
34386 | #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_MASK 0x00000002L |
34387 | #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_MASK 0x00000004L |
34388 | #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED_MASK 0x00000008L |
34389 | #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED_MASK 0x00000010L |
34390 | #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED_MASK 0x00000020L |
34391 | //RLC_CP_STAT_INVAL_CTRL |
34392 | #define RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN__SHIFT 0x0 |
34393 | #define RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN__SHIFT 0x1 |
34394 | #define RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN__SHIFT 0x2 |
34395 | #define RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN_MASK 0x00000001L |
34396 | #define RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN_MASK 0x00000002L |
34397 | #define RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN_MASK 0x00000004L |
34398 | //RLC_SPP_CTRL |
34399 | #define RLC_SPP_CTRL__ENABLE__SHIFT 0x0 |
34400 | #define RLC_SPP_CTRL__ENABLE_PPROF__SHIFT 0x1 |
34401 | #define RLC_SPP_CTRL__ENABLE_PWR_OPT__SHIFT 0x2 |
34402 | #define RLC_SPP_CTRL__PAUSE__SHIFT 0x3 |
34403 | #define RLC_SPP_CTRL__ENABLE_MASK 0x00000001L |
34404 | #define RLC_SPP_CTRL__ENABLE_PPROF_MASK 0x00000002L |
34405 | #define RLC_SPP_CTRL__ENABLE_PWR_OPT_MASK 0x00000004L |
34406 | #define RLC_SPP_CTRL__PAUSE_MASK 0x00000008L |
34407 | //RLC_SPP_SHADER_PROFILE_EN |
34408 | #define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE__SHIFT 0x0 |
34409 | #define RLC_SPP_SHADER_PROFILE_EN__VS_ENABLE__SHIFT 0x1 |
34410 | #define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE__SHIFT 0x2 |
34411 | #define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE__SHIFT 0x3 |
34412 | #define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE__SHIFT 0x4 |
34413 | #define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE__SHIFT 0x5 |
34414 | #define RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION__SHIFT 0x6 |
34415 | #define RLC_SPP_SHADER_PROFILE_EN__VS_STOP_CONDITION__SHIFT 0x7 |
34416 | #define RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION__SHIFT 0x8 |
34417 | #define RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION__SHIFT 0x9 |
34418 | #define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION__SHIFT 0xa |
34419 | #define RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION__SHIFT 0xb |
34420 | #define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION__SHIFT 0xc |
34421 | #define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION__SHIFT 0xd |
34422 | #define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS__SHIFT 0xe |
34423 | #define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED__SHIFT 0xf |
34424 | #define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK__SHIFT 0x10 |
34425 | #define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE_MASK 0x00000001L |
34426 | #define RLC_SPP_SHADER_PROFILE_EN__VS_ENABLE_MASK 0x00000002L |
34427 | #define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE_MASK 0x00000004L |
34428 | #define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE_MASK 0x00000008L |
34429 | #define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE_MASK 0x00000010L |
34430 | #define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE_MASK 0x00000020L |
34431 | #define RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION_MASK 0x00000040L |
34432 | #define RLC_SPP_SHADER_PROFILE_EN__VS_STOP_CONDITION_MASK 0x00000080L |
34433 | #define RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION_MASK 0x00000100L |
34434 | #define RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION_MASK 0x00000200L |
34435 | #define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION_MASK 0x00000400L |
34436 | #define RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION_MASK 0x00000800L |
34437 | #define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION_MASK 0x00001000L |
34438 | #define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION_MASK 0x00002000L |
34439 | #define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS_MASK 0x00004000L |
34440 | #define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED_MASK 0x00008000L |
34441 | #define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK_MASK 0x00010000L |
34442 | //RLC_SPP_SSF_CAPTURE_EN |
34443 | #define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE__SHIFT 0x0 |
34444 | #define RLC_SPP_SSF_CAPTURE_EN__VS_ENABLE__SHIFT 0x1 |
34445 | #define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE__SHIFT 0x2 |
34446 | #define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE__SHIFT 0x3 |
34447 | #define RLC_SPP_SSF_CAPTURE_EN__CGS_ENABLE__SHIFT 0x4 |
34448 | #define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE__SHIFT 0x5 |
34449 | #define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE_MASK 0x00000001L |
34450 | #define RLC_SPP_SSF_CAPTURE_EN__VS_ENABLE_MASK 0x00000002L |
34451 | #define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE_MASK 0x00000004L |
34452 | #define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE_MASK 0x00000008L |
34453 | #define RLC_SPP_SSF_CAPTURE_EN__CGS_ENABLE_MASK 0x00000010L |
34454 | #define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE_MASK 0x00000020L |
34455 | //RLC_SPP_SSF_THRESHOLD_0 |
34456 | #define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD__SHIFT 0x0 |
34457 | #define RLC_SPP_SSF_THRESHOLD_0__VS_THRESHOLD__SHIFT 0x10 |
34458 | #define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD_MASK 0x0000FFFFL |
34459 | #define RLC_SPP_SSF_THRESHOLD_0__VS_THRESHOLD_MASK 0xFFFF0000L |
34460 | //RLC_SPP_SSF_THRESHOLD_1 |
34461 | #define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD__SHIFT 0x0 |
34462 | #define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD__SHIFT 0x10 |
34463 | #define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD_MASK 0x0000FFFFL |
34464 | #define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD_MASK 0xFFFF0000L |
34465 | //RLC_SPP_SSF_THRESHOLD_2 |
34466 | #define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD__SHIFT 0x0 |
34467 | #define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD__SHIFT 0x10 |
34468 | #define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD_MASK 0x0000FFFFL |
34469 | #define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD_MASK 0xFFFF0000L |
34470 | //RLC_SPP_INFLIGHT_RD_ADDR |
34471 | #define RLC_SPP_INFLIGHT_RD_ADDR__ADDR__SHIFT 0x0 |
34472 | #define RLC_SPP_INFLIGHT_RD_ADDR__ADDR_MASK 0x0000001FL |
34473 | //RLC_SPP_INFLIGHT_RD_DATA |
34474 | #define RLC_SPP_INFLIGHT_RD_DATA__DATA__SHIFT 0x0 |
34475 | #define RLC_SPP_INFLIGHT_RD_DATA__DATA_MASK 0xFFFFFFFFL |
34476 | //RLC_SPP_PROF_INFO_1 |
34477 | #define RLC_SPP_PROF_INFO_1__SH_ID__SHIFT 0x0 |
34478 | #define RLC_SPP_PROF_INFO_1__SH_ID_MASK 0xFFFFFFFFL |
34479 | //RLC_SPP_PROF_INFO_2 |
34480 | #define RLC_SPP_PROF_INFO_2__SH_TYPE__SHIFT 0x0 |
34481 | #define RLC_SPP_PROF_INFO_2__CAM_HIT__SHIFT 0x4 |
34482 | #define RLC_SPP_PROF_INFO_2__CAM_LOCK__SHIFT 0x5 |
34483 | #define RLC_SPP_PROF_INFO_2__CAM_CONFLICT__SHIFT 0x6 |
34484 | #define RLC_SPP_PROF_INFO_2__SH_TYPE_MASK 0x0000000FL |
34485 | #define RLC_SPP_PROF_INFO_2__CAM_HIT_MASK 0x00000010L |
34486 | #define RLC_SPP_PROF_INFO_2__CAM_LOCK_MASK 0x00000020L |
34487 | #define RLC_SPP_PROF_INFO_2__CAM_CONFLICT_MASK 0x00000040L |
34488 | //RLC_SPP_GLOBAL_SH_ID |
34489 | #define RLC_SPP_GLOBAL_SH_ID__SH_ID__SHIFT 0x0 |
34490 | #define RLC_SPP_GLOBAL_SH_ID__SH_ID_MASK 0xFFFFFFFFL |
34491 | //RLC_SPP_GLOBAL_SH_ID_VALID |
34492 | #define RLC_SPP_GLOBAL_SH_ID_VALID__VALID__SHIFT 0x0 |
34493 | #define RLC_SPP_GLOBAL_SH_ID_VALID__VALID_MASK 0x00000001L |
34494 | //RLC_SPP_STATUS |
34495 | #define RLC_SPP_STATUS__RESERVED_0__SHIFT 0x0 |
34496 | #define RLC_SPP_STATUS__SSF_BUSY__SHIFT 0x1 |
34497 | #define RLC_SPP_STATUS__EVENT_ARB_BUSY__SHIFT 0x2 |
34498 | #define RLC_SPP_STATUS__SPP_BUSY__SHIFT 0x1f |
34499 | #define RLC_SPP_STATUS__RESERVED_0_MASK 0x00000001L |
34500 | #define RLC_SPP_STATUS__SSF_BUSY_MASK 0x00000002L |
34501 | #define RLC_SPP_STATUS__EVENT_ARB_BUSY_MASK 0x00000004L |
34502 | #define RLC_SPP_STATUS__SPP_BUSY_MASK 0x80000000L |
34503 | //RLC_SPP_PVT_STAT_0 |
34504 | #define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER__SHIFT 0x0 |
34505 | #define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER__SHIFT 0x6 |
34506 | #define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER__SHIFT 0xc |
34507 | #define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER__SHIFT 0x12 |
34508 | #define RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER__SHIFT 0x18 |
34509 | #define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER_MASK 0x0000003FL |
34510 | #define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER_MASK 0x00000FC0L |
34511 | #define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER_MASK 0x0003F000L |
34512 | #define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER_MASK 0x00FC0000L |
34513 | #define RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER_MASK 0x7F000000L |
34514 | //RLC_SPP_PVT_STAT_1 |
34515 | #define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER__SHIFT 0x0 |
34516 | #define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER__SHIFT 0x6 |
34517 | #define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER__SHIFT 0xc |
34518 | #define RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER__SHIFT 0x12 |
34519 | #define RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER__SHIFT 0x18 |
34520 | #define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER_MASK 0x0000003FL |
34521 | #define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER_MASK 0x00000FC0L |
34522 | #define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER_MASK 0x0003F000L |
34523 | #define RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER_MASK 0x00FC0000L |
34524 | #define RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER_MASK 0x7F000000L |
34525 | //RLC_SPP_PVT_STAT_2 |
34526 | #define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER__SHIFT 0x0 |
34527 | #define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER__SHIFT 0x6 |
34528 | #define RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER__SHIFT 0xc |
34529 | #define RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER__SHIFT 0x12 |
34530 | #define RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER__SHIFT 0x18 |
34531 | #define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER_MASK 0x0000003FL |
34532 | #define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER_MASK 0x00000FC0L |
34533 | #define RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER_MASK 0x0003F000L |
34534 | #define RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER_MASK 0x00FC0000L |
34535 | #define RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER_MASK 0x7F000000L |
34536 | //RLC_SPP_PVT_STAT_3 |
34537 | #define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER__SHIFT 0x0 |
34538 | #define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER_MASK 0x0000003FL |
34539 | //RLC_SPP_PVT_LEVEL_MAX |
34540 | #define RLC_SPP_PVT_LEVEL_MAX__LEVEL__SHIFT 0x0 |
34541 | #define RLC_SPP_PVT_LEVEL_MAX__LEVEL_MASK 0x0000000FL |
34542 | //RLC_SPP_STALL_STATE_UPDATE |
34543 | #define RLC_SPP_STALL_STATE_UPDATE__STALL__SHIFT 0x0 |
34544 | #define RLC_SPP_STALL_STATE_UPDATE__ENABLE__SHIFT 0x1 |
34545 | #define RLC_SPP_STALL_STATE_UPDATE__STALL_MASK 0x00000001L |
34546 | #define RLC_SPP_STALL_STATE_UPDATE__ENABLE_MASK 0x00000002L |
34547 | //RLC_SPP_PBB_INFO |
34548 | #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE__SHIFT 0x0 |
34549 | #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID__SHIFT 0x1 |
34550 | #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE__SHIFT 0x2 |
34551 | #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID__SHIFT 0x3 |
34552 | #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_MASK 0x00000001L |
34553 | #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID_MASK 0x00000002L |
34554 | #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_MASK 0x00000004L |
34555 | #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID_MASK 0x00000008L |
34556 | //RLC_SPP_RESET |
34557 | #define RLC_SPP_RESET__SSF_RESET__SHIFT 0x0 |
34558 | #define RLC_SPP_RESET__EVENT_ARB_RESET__SHIFT 0x1 |
34559 | #define RLC_SPP_RESET__CAM_RESET__SHIFT 0x2 |
34560 | #define RLC_SPP_RESET__PVT_RESET__SHIFT 0x3 |
34561 | #define RLC_SPP_RESET__SSF_RESET_MASK 0x00000001L |
34562 | #define RLC_SPP_RESET__EVENT_ARB_RESET_MASK 0x00000002L |
34563 | #define RLC_SPP_RESET__CAM_RESET_MASK 0x00000004L |
34564 | #define RLC_SPP_RESET__PVT_RESET_MASK 0x00000008L |
34565 | //RLC_SPM_SAMPLE_CNT |
34566 | #define RLC_SPM_SAMPLE_CNT__COUNT__SHIFT 0x0 |
34567 | #define RLC_SPM_SAMPLE_CNT__COUNT_MASK 0xFFFFFFFFL |
34568 | //RLC_PCC_STRETCH_HYSTERESIS_CNTL |
34569 | #define RLC_PCC_STRETCH_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT 0x0 |
34570 | #define RLC_PCC_STRETCH_HYSTERESIS_CNTL__HYSTERESIS_CNT__SHIFT 0x8 |
34571 | #define RLC_PCC_STRETCH_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK 0x000000FFL |
34572 | #define RLC_PCC_STRETCH_HYSTERESIS_CNTL__HYSTERESIS_CNT_MASK 0x0000FF00L |
34573 | //RLC_GPU_CLOCK_COUNT_SPM_LSB |
34574 | #define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 |
34575 | #define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
34576 | //RLC_GPU_CLOCK_COUNT_SPM_MSB |
34577 | #define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 |
34578 | #define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
34579 | //RLC_SPM_THREAD_TRACE_CTRL |
34580 | #define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN__SHIFT 0x0 |
34581 | #define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN_MASK 0x00000001L |
34582 | //RLC_LB_CNTR_2 |
34583 | #define RLC_LB_CNTR_2__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 |
34584 | #define RLC_LB_CNTR_2__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL |
34585 | //RLC_CPAXI_DOORBELL_MON_CTRL |
34586 | #define RLC_CPAXI_DOORBELL_MON_CTRL__EN__SHIFT 0x0 |
34587 | #define RLC_CPAXI_DOORBELL_MON_CTRL__ID__SHIFT 0x1 |
34588 | #define RLC_CPAXI_DOORBELL_MON_CTRL__EN_MASK 0x00000001L |
34589 | #define RLC_CPAXI_DOORBELL_MON_CTRL__ID_MASK 0x0000003EL |
34590 | //RLC_CPAXI_DOORBELL_MON_STAT |
34591 | #define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH__SHIFT 0x0 |
34592 | #define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR__SHIFT 0x1 |
34593 | #define RLC_CPAXI_DOORBELL_MON_STAT__ADDR__SHIFT 0x2 |
34594 | #define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH_MASK 0x00000001L |
34595 | #define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR_MASK 0x00000002L |
34596 | #define RLC_CPAXI_DOORBELL_MON_STAT__ADDR_MASK 0x0FFFFFFCL |
34597 | //RLC_CPAXI_DOORBELL_MON_DATA_LSB |
34598 | #define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA__SHIFT 0x0 |
34599 | #define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA_MASK 0xFFFFFFFFL |
34600 | //RLC_CPAXI_DOORBELL_MON_DATA_MSB |
34601 | #define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA__SHIFT 0x0 |
34602 | #define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA_MASK 0xFFFFFFFFL |
34603 | |
34604 | |
34605 | // addressBlock: gc_rlcrdec |
34606 | //RLC_SPP_CAM_ADDR |
34607 | #define RLC_SPP_CAM_ADDR__ADDR__SHIFT 0x0 |
34608 | #define RLC_SPP_CAM_ADDR__ADDR_MASK 0x000000FFL |
34609 | //RLC_SPP_CAM_DATA |
34610 | #define RLC_SPP_CAM_DATA__DATA__SHIFT 0x0 |
34611 | #define RLC_SPP_CAM_DATA__TAG__SHIFT 0x8 |
34612 | #define RLC_SPP_CAM_DATA__DATA_MASK 0x000000FFL |
34613 | #define RLC_SPP_CAM_DATA__TAG_MASK 0xFFFFFF00L |
34614 | //RLC_SPP_CAM_EXT_ADDR |
34615 | #define RLC_SPP_CAM_EXT_ADDR__ADDR__SHIFT 0x0 |
34616 | #define RLC_SPP_CAM_EXT_ADDR__ADDR_MASK 0x000000FFL |
34617 | //RLC_SPP_CAM_EXT_DATA |
34618 | #define RLC_SPP_CAM_EXT_DATA__VALID__SHIFT 0x0 |
34619 | #define RLC_SPP_CAM_EXT_DATA__LOCK__SHIFT 0x1 |
34620 | #define RLC_SPP_CAM_EXT_DATA__VALID_MASK 0x00000001L |
34621 | #define RLC_SPP_CAM_EXT_DATA__LOCK_MASK 0x00000002L |
34622 | //RLC_PACE_SCRATCH_ADDR |
34623 | #define RLC_PACE_SCRATCH_ADDR__ADDR__SHIFT 0x0 |
34624 | #define RLC_PACE_SCRATCH_ADDR__ADDR_MASK 0xFFFFFFFFL |
34625 | //RLC_PACE_SCRATCH_DATA |
34626 | #define RLC_PACE_SCRATCH_DATA__DATA__SHIFT 0x0 |
34627 | #define RLC_PACE_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL |
34628 | |
34629 | |
34630 | // addressBlock: gc_rlcsdec |
34631 | //RLC_RLCS_DEC_START |
34632 | //RLC_RLCS_DEC_DUMP_ADDR |
34633 | //RLC_RLCS_EXCEPTION_REG_1 |
34634 | #define RLC_RLCS_EXCEPTION_REG_1__ADDR__SHIFT 0x0 |
34635 | #define RLC_RLCS_EXCEPTION_REG_1__RESERVED__SHIFT 0x12 |
34636 | #define RLC_RLCS_EXCEPTION_REG_1__ADDR_MASK 0x0003FFFFL |
34637 | #define RLC_RLCS_EXCEPTION_REG_1__RESERVED_MASK 0xFFFC0000L |
34638 | //RLC_RLCS_EXCEPTION_REG_2 |
34639 | #define RLC_RLCS_EXCEPTION_REG_2__ADDR__SHIFT 0x0 |
34640 | #define RLC_RLCS_EXCEPTION_REG_2__RESERVED__SHIFT 0x12 |
34641 | #define RLC_RLCS_EXCEPTION_REG_2__ADDR_MASK 0x0003FFFFL |
34642 | #define RLC_RLCS_EXCEPTION_REG_2__RESERVED_MASK 0xFFFC0000L |
34643 | //RLC_RLCS_EXCEPTION_REG_3 |
34644 | #define RLC_RLCS_EXCEPTION_REG_3__ADDR__SHIFT 0x0 |
34645 | #define RLC_RLCS_EXCEPTION_REG_3__RESERVED__SHIFT 0x12 |
34646 | #define RLC_RLCS_EXCEPTION_REG_3__ADDR_MASK 0x0003FFFFL |
34647 | #define RLC_RLCS_EXCEPTION_REG_3__RESERVED_MASK 0xFFFC0000L |
34648 | //RLC_RLCS_EXCEPTION_REG_4 |
34649 | #define RLC_RLCS_EXCEPTION_REG_4__ADDR__SHIFT 0x0 |
34650 | #define RLC_RLCS_EXCEPTION_REG_4__RESERVED__SHIFT 0x12 |
34651 | #define RLC_RLCS_EXCEPTION_REG_4__ADDR_MASK 0x0003FFFFL |
34652 | #define RLC_RLCS_EXCEPTION_REG_4__RESERVED_MASK 0xFFFC0000L |
34653 | //RLC_RLCS_GENERAL_6 |
34654 | #define RLC_RLCS_GENERAL_6__DATA__SHIFT 0x0 |
34655 | #define RLC_RLCS_GENERAL_6__DATA_MASK 0xFFFFFFFFL |
34656 | //RLC_RLCS_GENERAL_7 |
34657 | #define RLC_RLCS_GENERAL_7__DATA__SHIFT 0x0 |
34658 | #define RLC_RLCS_GENERAL_7__DATA_MASK 0xFFFFFFFFL |
34659 | //RLC_RLCS_CGCG_REQUEST |
34660 | #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST__SHIFT 0x0 |
34661 | #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D__SHIFT 0x1 |
34662 | #define RLC_RLCS_CGCG_REQUEST__RESERVED__SHIFT 0x2 |
34663 | #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_MASK 0x00000001L |
34664 | #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D_MASK 0x00000002L |
34665 | #define RLC_RLCS_CGCG_REQUEST__RESERVED_MASK 0xFFFFFFFCL |
34666 | //RLC_RLCS_CGCG_STATUS |
34667 | #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS__SHIFT 0x0 |
34668 | #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS__SHIFT 0x2 |
34669 | #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D__SHIFT 0x3 |
34670 | #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D__SHIFT 0x5 |
34671 | #define RLC_RLCS_CGCG_STATUS__RESERVED__SHIFT 0x6 |
34672 | #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_MASK 0x00000003L |
34673 | #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_MASK 0x00000004L |
34674 | #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D_MASK 0x00000018L |
34675 | #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D_MASK 0x00000020L |
34676 | #define RLC_RLCS_CGCG_STATUS__RESERVED_MASK 0xFFFFFFC0L |
34677 | //RLC_RLCS_SMU_GFXCLK_STATUS |
34678 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_DONETOG__SHIFT 0x0 |
34679 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXMUX_CUR_VALUE__SHIFT 0x1 |
34680 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_STRETCH_PCC__SHIFT 0x2 |
34681 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_PCC_CTRL__SHIFT 0x3 |
34682 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_DONETOG_MASK 0x00000001L |
34683 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXMUX_CUR_VALUE_MASK 0x00000002L |
34684 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_STRETCH_PCC_MASK 0x00000004L |
34685 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_PCC_CTRL_MASK 0x00000008L |
34686 | //RLC_RLCS_SMU_GFXCLK_CONTROL |
34687 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_CHGTOG__SHIFT 0x0 |
34688 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_DIVIDER__SHIFT 0x1 |
34689 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXMUX_SEL__SHIFT 0x8 |
34690 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__RESERVED__SHIFT 0x9 |
34691 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_CHGTOG_MASK 0x00000001L |
34692 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_DIVIDER_MASK 0x000000FEL |
34693 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXMUX_SEL_MASK 0x00000100L |
34694 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__RESERVED_MASK 0xFFFFFE00L |
34695 | //RLC_RLCS_SOC_DS_CNTL |
34696 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW__SHIFT 0x0 |
34697 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x1 |
34698 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x2 |
34699 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK__SHIFT 0x3 |
34700 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK__SHIFT 0x4 |
34701 | #define RLC_RLCS_SOC_DS_CNTL__RESERVED_5__SHIFT 0x5 |
34702 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT 0x6 |
34703 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT 0x7 |
34704 | #define RLC_RLCS_SOC_DS_CNTL__RESERVED__SHIFT 0x8 |
34705 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW_MASK 0x00000001L |
34706 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00000002L |
34707 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00000004L |
34708 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK_MASK 0x00000008L |
34709 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK_MASK 0x00000010L |
34710 | #define RLC_RLCS_SOC_DS_CNTL__RESERVED_5_MASK 0x00000020L |
34711 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK_MASK 0x00000040L |
34712 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK_MASK 0x00000080L |
34713 | #define RLC_RLCS_SOC_DS_CNTL__RESERVED_MASK 0xFFFFFF00L |
34714 | //RLC_RLCS_GFX_DS_CNTL |
34715 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW__SHIFT 0x0 |
34716 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x1 |
34717 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x2 |
34718 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK__SHIFT 0x3 |
34719 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK__SHIFT 0x4 |
34720 | #define RLC_RLCS_GFX_DS_CNTL__RESERVED_5__SHIFT 0x5 |
34721 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT 0x6 |
34722 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT 0x7 |
34723 | #define RLC_RLCS_GFX_DS_CNTL__RESERVED__SHIFT 0x8 |
34724 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW_MASK 0x00000001L |
34725 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000002L |
34726 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000004L |
34727 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK_MASK 0x00000008L |
34728 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK_MASK 0x00000010L |
34729 | #define RLC_RLCS_GFX_DS_CNTL__RESERVED_5_MASK 0x00000020L |
34730 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK_MASK 0x00000040L |
34731 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK_MASK 0x00000080L |
34732 | #define RLC_RLCS_GFX_DS_CNTL__RESERVED_MASK 0xFFFFFF00L |
34733 | //RLC_GPM_STAT |
34734 | #define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 |
34735 | #define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 |
34736 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 |
34737 | #define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 |
34738 | #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 |
34739 | #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 |
34740 | #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 |
34741 | #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 |
34742 | #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 |
34743 | #define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 |
34744 | #define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa |
34745 | #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb |
34746 | #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc |
34747 | #define RLC_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT 0xd |
34748 | #define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT 0xe |
34749 | #define RLC_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT 0xf |
34750 | #define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT 0x10 |
34751 | #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 |
34752 | #define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12 |
34753 | #define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13 |
34754 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14 |
34755 | #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 |
34756 | #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 |
34757 | #define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 |
34758 | #define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 |
34759 | #define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L |
34760 | #define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L |
34761 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L |
34762 | #define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L |
34763 | #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L |
34764 | #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L |
34765 | #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L |
34766 | #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L |
34767 | #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L |
34768 | #define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L |
34769 | #define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L |
34770 | #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L |
34771 | #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L |
34772 | #define RLC_GPM_STAT__STATIC_WGP_POWERING_UP_MASK 0x00002000L |
34773 | #define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK 0x00004000L |
34774 | #define RLC_GPM_STAT__DYN_WGP_POWERING_UP_MASK 0x00008000L |
34775 | #define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK 0x00010000L |
34776 | #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L |
34777 | #define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L |
34778 | #define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L |
34779 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L |
34780 | #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L |
34781 | #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L |
34782 | #define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L |
34783 | #define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L |
34784 | //RLC_RLCS_GPM_STAT |
34785 | #define RLC_RLCS_GPM_STAT__RLC_BUSY__SHIFT 0x0 |
34786 | #define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 |
34787 | #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 |
34788 | #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 |
34789 | #define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 |
34790 | #define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 |
34791 | #define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 |
34792 | #define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 |
34793 | #define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 |
34794 | #define RLC_RLCS_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 |
34795 | #define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa |
34796 | #define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb |
34797 | #define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc |
34798 | #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT 0xd |
34799 | #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT 0xe |
34800 | #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT 0xf |
34801 | #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT 0x10 |
34802 | #define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 |
34803 | #define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS__SHIFT 0x12 |
34804 | #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13 |
34805 | #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14 |
34806 | #define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 |
34807 | #define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 |
34808 | #define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 |
34809 | #define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 |
34810 | #define RLC_RLCS_GPM_STAT__RLC_BUSY_MASK 0x00000001L |
34811 | #define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L |
34812 | #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L |
34813 | #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L |
34814 | #define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L |
34815 | #define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L |
34816 | #define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L |
34817 | #define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L |
34818 | #define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L |
34819 | #define RLC_RLCS_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L |
34820 | #define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L |
34821 | #define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L |
34822 | #define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L |
34823 | #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP_MASK 0x00002000L |
34824 | #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK 0x00004000L |
34825 | #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP_MASK 0x00008000L |
34826 | #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK 0x00010000L |
34827 | #define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L |
34828 | #define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS_MASK 0x00040000L |
34829 | #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L |
34830 | #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L |
34831 | #define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L |
34832 | #define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L |
34833 | #define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L |
34834 | #define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L |
34835 | //RLC_RLCS_ABORTED_PD_SEQUENCE |
34836 | #define RLC_RLCS_ABORTED_PD_SEQUENCE__APS__SHIFT 0x0 |
34837 | #define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED__SHIFT 0x10 |
34838 | #define RLC_RLCS_ABORTED_PD_SEQUENCE__APS_MASK 0x0000FFFFL |
34839 | #define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED_MASK 0xFFFF0000L |
34840 | //RLC_RLCS_DIDT_FORCE_STALL |
34841 | #define RLC_RLCS_DIDT_FORCE_STALL__DFS__SHIFT 0x0 |
34842 | #define RLC_RLCS_DIDT_FORCE_STALL__RESERVED__SHIFT 0x3 |
34843 | #define RLC_RLCS_DIDT_FORCE_STALL__DFS_MASK 0x00000007L |
34844 | #define RLC_RLCS_DIDT_FORCE_STALL__RESERVED_MASK 0xFFFFFFF8L |
34845 | //RLC_RLCS_IOV_CMD_STATUS |
34846 | #define RLC_RLCS_IOV_CMD_STATUS__DATA__SHIFT 0x0 |
34847 | #define RLC_RLCS_IOV_CMD_STATUS__DATA_MASK 0xFFFFFFFFL |
34848 | //RLC_RLCS_IOV_CNTX_LOC_SIZE |
34849 | #define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA__SHIFT 0x0 |
34850 | #define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED__SHIFT 0x8 |
34851 | #define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA_MASK 0x000000FFL |
34852 | #define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED_MASK 0xFFFFFF00L |
34853 | //RLC_RLCS_IOV_SCH_BLOCK |
34854 | #define RLC_RLCS_IOV_SCH_BLOCK__DATA__SHIFT 0x0 |
34855 | #define RLC_RLCS_IOV_SCH_BLOCK__DATA_MASK 0xFFFFFFFFL |
34856 | //RLC_RLCS_IOV_VM_BUSY_STATUS |
34857 | #define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA__SHIFT 0x0 |
34858 | #define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA_MASK 0xFFFFFFFFL |
34859 | //RLC_RLCS_GPM_STAT_2 |
34860 | #define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR__SHIFT 0x0 |
34861 | #define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED__SHIFT 0x1 |
34862 | #define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS__SHIFT 0x2 |
34863 | #define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS__SHIFT 0x3 |
34864 | #define RLC_RLCS_GPM_STAT_2__RESERVED__SHIFT 0x4 |
34865 | #define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR_MASK 0x00000001L |
34866 | #define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED_MASK 0x00000002L |
34867 | #define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS_MASK 0x00000004L |
34868 | #define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS_MASK 0x00000008L |
34869 | #define RLC_RLCS_GPM_STAT_2__RESERVED_MASK 0xFFFFFFF0L |
34870 | //RLC_RLCS_GRBM_SOFT_RESET |
34871 | #define RLC_RLCS_GRBM_SOFT_RESET__RESET__SHIFT 0x0 |
34872 | #define RLC_RLCS_GRBM_SOFT_RESET__RESERVED__SHIFT 0x1 |
34873 | #define RLC_RLCS_GRBM_SOFT_RESET__RESET_MASK 0x00000001L |
34874 | #define RLC_RLCS_GRBM_SOFT_RESET__RESERVED_MASK 0xFFFFFFFEL |
34875 | //RLC_RLCS_PG_CHANGE_STATUS |
34876 | #define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED__SHIFT 0x0 |
34877 | #define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED__SHIFT 0x1 |
34878 | #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED__SHIFT 0x2 |
34879 | #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED__SHIFT 0x3 |
34880 | #define RLC_RLCS_PG_CHANGE_STATUS__RESERVED__SHIFT 0x4 |
34881 | #define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED_MASK 0x00000001L |
34882 | #define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED_MASK 0x00000002L |
34883 | #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED_MASK 0x00000004L |
34884 | #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED_MASK 0x00000008L |
34885 | #define RLC_RLCS_PG_CHANGE_STATUS__RESERVED_MASK 0xFFFFFFF0L |
34886 | //RLC_RLCS_PG_CHANGE_READ |
34887 | #define RLC_RLCS_PG_CHANGE_READ__PG_CNTL_CHANGED__SHIFT 0x0 |
34888 | #define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED__SHIFT 0x1 |
34889 | #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED__SHIFT 0x2 |
34890 | #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED__SHIFT 0x3 |
34891 | #define RLC_RLCS_PG_CHANGE_READ__RESERVED__SHIFT 0x4 |
34892 | #define RLC_RLCS_PG_CHANGE_READ__PG_CNTL_CHANGED_MASK 0x00000001L |
34893 | #define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED_MASK 0x00000002L |
34894 | #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED_MASK 0x00000004L |
34895 | #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED_MASK 0x00000008L |
34896 | #define RLC_RLCS_PG_CHANGE_READ__RESERVED_MASK 0xFFFFFFF0L |
34897 | //RLC_RLCS_LB_STATUS |
34898 | #define RLC_RLCS_LB_STATUS__LB_CNTR_START__SHIFT 0x0 |
34899 | #define RLC_RLCS_LB_STATUS__LB_CNTR_STOP__SHIFT 0x1 |
34900 | #define RLC_RLCS_LB_STATUS__LB_CNTR_1_MAX_FLAG__SHIFT 0x2 |
34901 | #define RLC_RLCS_LB_STATUS__LB_CNTR_2_MAX_FLAG__SHIFT 0x3 |
34902 | #define RLC_RLCS_LB_STATUS__LBPW_DISABLE_FLAG__SHIFT 0x4 |
34903 | #define RLC_RLCS_LB_STATUS__RESERVED__SHIFT 0x5 |
34904 | #define RLC_RLCS_LB_STATUS__LB_CNTR_START_MASK 0x00000001L |
34905 | #define RLC_RLCS_LB_STATUS__LB_CNTR_STOP_MASK 0x00000002L |
34906 | #define RLC_RLCS_LB_STATUS__LB_CNTR_1_MAX_FLAG_MASK 0x00000004L |
34907 | #define RLC_RLCS_LB_STATUS__LB_CNTR_2_MAX_FLAG_MASK 0x00000008L |
34908 | #define RLC_RLCS_LB_STATUS__LBPW_DISABLE_FLAG_MASK 0x00000010L |
34909 | #define RLC_RLCS_LB_STATUS__RESERVED_MASK 0xFFFFFFE0L |
34910 | //RLC_RLCS_LB_READ |
34911 | #define RLC_RLCS_LB_READ__LB_CNTR_START__SHIFT 0x0 |
34912 | #define RLC_RLCS_LB_READ__LB_CNTR_STOP__SHIFT 0x1 |
34913 | #define RLC_RLCS_LB_READ__LB_CNTR_1_MAX_FLAG__SHIFT 0x2 |
34914 | #define RLC_RLCS_LB_READ__LB_CNTR_2_MAX_FLAG__SHIFT 0x3 |
34915 | #define RLC_RLCS_LB_READ__LBPW_DISABLE_FLAG__SHIFT 0x4 |
34916 | #define RLC_RLCS_LB_READ__RESERVED__SHIFT 0x5 |
34917 | #define RLC_RLCS_LB_READ__LB_CNTR_START_MASK 0x00000001L |
34918 | #define RLC_RLCS_LB_READ__LB_CNTR_STOP_MASK 0x00000002L |
34919 | #define RLC_RLCS_LB_READ__LB_CNTR_1_MAX_FLAG_MASK 0x00000004L |
34920 | #define RLC_RLCS_LB_READ__LB_CNTR_2_MAX_FLAG_MASK 0x00000008L |
34921 | #define RLC_RLCS_LB_READ__LBPW_DISABLE_FLAG_MASK 0x00000010L |
34922 | #define RLC_RLCS_LB_READ__RESERVED_MASK 0xFFFFFFE0L |
34923 | //RLC_RLCS_LB_CONTROL |
34924 | #define RLC_RLCS_LB_CONTROL__NEW_LBPW_REQ__SHIFT 0x0 |
34925 | #define RLC_RLCS_LB_CONTROL__LB_CNTR_INC_CP_BUSY__SHIFT 0x1 |
34926 | #define RLC_RLCS_LB_CONTROL__RESERVED__SHIFT 0x2 |
34927 | #define RLC_RLCS_LB_CONTROL__NEW_LBPW_REQ_MASK 0x00000001L |
34928 | #define RLC_RLCS_LB_CONTROL__LB_CNTR_INC_CP_BUSY_MASK 0x00000002L |
34929 | #define RLC_RLCS_LB_CONTROL__RESERVED_MASK 0xFFFFFFFCL |
34930 | //RLC_RLCS_IH_SEMAPHORE |
34931 | #define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID__SHIFT 0x0 |
34932 | #define RLC_RLCS_IH_SEMAPHORE__RESERVED__SHIFT 0x5 |
34933 | #define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID_MASK 0x0000001FL |
34934 | #define RLC_RLCS_IH_SEMAPHORE__RESERVED_MASK 0xFFFFFFE0L |
34935 | //RLC_RLCS_IH_COOKIE_SEMAPHORE |
34936 | #define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID__SHIFT 0x0 |
34937 | #define RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED__SHIFT 0x5 |
34938 | #define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID_MASK 0x0000001FL |
34939 | #define RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED_MASK 0xFFFFFFE0L |
34940 | //RLC_RLCS_IH_CTRL_1 |
34941 | #define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1__SHIFT 0x0 |
34942 | #define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1_MASK 0xFFFFFFFFL |
34943 | //RLC_RLCS_IH_CTRL_2 |
34944 | #define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2__SHIFT 0x0 |
34945 | #define RLC_RLCS_IH_CTRL_2__IH_RING_ID__SHIFT 0x8 |
34946 | #define RLC_RLCS_IH_CTRL_2__IH_VM_ID__SHIFT 0x10 |
34947 | #define RLC_RLCS_IH_CTRL_2__RESERVED__SHIFT 0x14 |
34948 | #define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2_MASK 0x000000FFL |
34949 | #define RLC_RLCS_IH_CTRL_2__IH_RING_ID_MASK 0x0000FF00L |
34950 | #define RLC_RLCS_IH_CTRL_2__IH_VM_ID_MASK 0x000F0000L |
34951 | #define RLC_RLCS_IH_CTRL_2__RESERVED_MASK 0xFFF00000L |
34952 | //RLC_RLCS_IH_CTRL_3 |
34953 | #define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID__SHIFT 0x0 |
34954 | #define RLC_RLCS_IH_CTRL_3__IH_VF_ID__SHIFT 0x8 |
34955 | #define RLC_RLCS_IH_CTRL_3__IH_VF__SHIFT 0xd |
34956 | #define RLC_RLCS_IH_CTRL_3__RESERVED__SHIFT 0xe |
34957 | #define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID_MASK 0x000000FFL |
34958 | #define RLC_RLCS_IH_CTRL_3__IH_VF_ID_MASK 0x00001F00L |
34959 | #define RLC_RLCS_IH_CTRL_3__IH_VF_MASK 0x00002000L |
34960 | #define RLC_RLCS_IH_CTRL_3__RESERVED_MASK 0xFFFFC000L |
34961 | //RLC_RLCS_IH_STATUS |
34962 | #define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT__SHIFT 0x0 |
34963 | #define RLC_RLCS_IH_STATUS__IH_BUSY__SHIFT 0x6 |
34964 | #define RLC_RLCS_IH_STATUS__RESERVED__SHIFT 0x7 |
34965 | #define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT_MASK 0x0000003FL |
34966 | #define RLC_RLCS_IH_STATUS__IH_BUSY_MASK 0x00000040L |
34967 | #define RLC_RLCS_IH_STATUS__RESERVED_MASK 0xFFFFFF80L |
34968 | //RLC_RLCS_WGP_STATUS |
34969 | #define RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE__SHIFT 0x0 |
34970 | #define RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED__SHIFT 0x1 |
34971 | #define RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED__SHIFT 0x2 |
34972 | #define RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE__SHIFT 0x3 |
34973 | #define RLC_RLCS_WGP_STATUS__RESERVED__SHIFT 0x4 |
34974 | #define RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE_MASK 0x00000001L |
34975 | #define RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED_MASK 0x00000002L |
34976 | #define RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED_MASK 0x00000004L |
34977 | #define RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE_MASK 0x00000008L |
34978 | #define RLC_RLCS_WGP_STATUS__RESERVED_MASK 0xFFFFFFF0L |
34979 | //RLC_RLCS_WGP_READ |
34980 | #define RLC_RLCS_WGP_READ__CS_WORK_ACTIVE__SHIFT 0x0 |
34981 | #define RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED__SHIFT 0x1 |
34982 | #define RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED__SHIFT 0x2 |
34983 | #define RLC_RLCS_WGP_READ__RESERVED__SHIFT 0x3 |
34984 | #define RLC_RLCS_WGP_READ__CS_WORK_ACTIVE_MASK 0x00000001L |
34985 | #define RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED_MASK 0x00000002L |
34986 | #define RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED_MASK 0x00000004L |
34987 | #define RLC_RLCS_WGP_READ__RESERVED_MASK 0xFFFFFFF8L |
34988 | //RLC_RLCS_CP_INT_CTRL_1 |
34989 | #define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK__SHIFT 0x0 |
34990 | #define RLC_RLCS_CP_INT_CTRL_1__RESERVED__SHIFT 0x1 |
34991 | #define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK_MASK 0x00000001L |
34992 | #define RLC_RLCS_CP_INT_CTRL_1__RESERVED_MASK 0xFFFFFFFEL |
34993 | //RLC_RLCS_CP_INT_CTRL_2 |
34994 | #define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN__SHIFT 0x0 |
34995 | #define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN__SHIFT 0x1 |
34996 | #define RLC_RLCS_CP_INT_CTRL_2__RESERVED__SHIFT 0x2 |
34997 | #define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN_MASK 0x00000001L |
34998 | #define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN_MASK 0x00000002L |
34999 | #define RLC_RLCS_CP_INT_CTRL_2__RESERVED_MASK 0xFFFFFFFCL |
35000 | //RLC_RLCS_CP_INT_INFO_1 |
35001 | #define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 |
35002 | #define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL |
35003 | //RLC_RLCS_CP_INT_INFO_2 |
35004 | #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 |
35005 | #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 |
35006 | #define RLC_RLCS_CP_INT_INFO_2__RESERVED__SHIFT 0x19 |
35007 | #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL |
35008 | #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID_MASK 0x01FF0000L |
35009 | #define RLC_RLCS_CP_INT_INFO_2__RESERVED_MASK 0xFE000000L |
35010 | //RLC_RLCS_SPM_INT_CTRL |
35011 | #define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK__SHIFT 0x0 |
35012 | #define RLC_RLCS_SPM_INT_CTRL__RESERVED__SHIFT 0x1 |
35013 | #define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK_MASK 0x00000001L |
35014 | #define RLC_RLCS_SPM_INT_CTRL__RESERVED_MASK 0xFFFFFFFEL |
35015 | //RLC_RLCS_SPM_INT_INFO_1 |
35016 | #define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 |
35017 | #define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL |
35018 | //RLC_RLCS_SPM_INT_INFO_2 |
35019 | #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 |
35020 | #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 |
35021 | #define RLC_RLCS_SPM_INT_INFO_2__RESERVED__SHIFT 0x19 |
35022 | #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL |
35023 | #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID_MASK 0x01FF0000L |
35024 | #define RLC_RLCS_SPM_INT_INFO_2__RESERVED_MASK 0xFE000000L |
35025 | //RLC_RLCS_DSM_TRIG |
35026 | #define RLC_RLCS_DSM_TRIG__START__SHIFT 0x0 |
35027 | #define RLC_RLCS_DSM_TRIG__RESERVED__SHIFT 0x1 |
35028 | #define RLC_RLCS_DSM_TRIG__START_MASK 0x00000001L |
35029 | #define RLC_RLCS_DSM_TRIG__RESERVED_MASK 0xFFFFFFFEL |
35030 | //RLC_RLCS_GE_FAST_CLOCK |
35031 | #define RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS_CHANGED__SHIFT 0x0 |
35032 | #define RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS__SHIFT 0x1 |
35033 | #define RLC_RLCS_GE_FAST_CLOCK__INT_CLEAR__SHIFT 0x2 |
35034 | #define RLC_RLCS_GE_FAST_CLOCK__RESERVED__SHIFT 0x3 |
35035 | #define RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS_CHANGED_MASK 0x00000001L |
35036 | #define RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS_MASK 0x00000002L |
35037 | #define RLC_RLCS_GE_FAST_CLOCK__INT_CLEAR_MASK 0x00000004L |
35038 | #define RLC_RLCS_GE_FAST_CLOCK__RESERVED_MASK 0xFFFFFFF8L |
35039 | //RLC_RLCS_BOOTLOAD_STATUS |
35040 | #define RLC_RLCS_BOOTLOAD_STATUS__RLC_RLCG_IRAM_LOADED__SHIFT 0x0 |
35041 | #define RLC_RLCS_BOOTLOAD_STATUS__RESERVED__SHIFT 0x1 |
35042 | #define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE__SHIFT 0x1f |
35043 | #define RLC_RLCS_BOOTLOAD_STATUS__RLC_RLCG_IRAM_LOADED_MASK 0x00000001L |
35044 | #define RLC_RLCS_BOOTLOAD_STATUS__RESERVED_MASK 0x7FFFFFFEL |
35045 | #define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE_MASK 0x80000000L |
35046 | //RLC_RLCS_POWER_BRAKE_CNTL |
35047 | #define RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE__SHIFT 0x0 |
35048 | #define RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR__SHIFT 0x1 |
35049 | #define RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS__SHIFT 0x2 |
35050 | #define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT__SHIFT 0xa |
35051 | #define RLC_RLCS_POWER_BRAKE_CNTL__RESERVED__SHIFT 0x12 |
35052 | #define RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE_MASK 0x00000001L |
35053 | #define RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR_MASK 0x00000002L |
35054 | #define RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS_MASK 0x000003FCL |
35055 | #define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT_MASK 0x0003FC00L |
35056 | #define RLC_RLCS_POWER_BRAKE_CNTL__RESERVED_MASK 0xFFFC0000L |
35057 | //RLC_RLCS_GENERAL_0 |
35058 | #define RLC_RLCS_GENERAL_0__DATA__SHIFT 0x0 |
35059 | #define RLC_RLCS_GENERAL_0__DATA_MASK 0xFFFFFFFFL |
35060 | //RLC_RLCS_GENERAL_1 |
35061 | #define RLC_RLCS_GENERAL_1__DATA__SHIFT 0x0 |
35062 | #define RLC_RLCS_GENERAL_1__DATA_MASK 0xFFFFFFFFL |
35063 | //RLC_RLCS_GENERAL_2 |
35064 | #define RLC_RLCS_GENERAL_2__DATA__SHIFT 0x0 |
35065 | #define RLC_RLCS_GENERAL_2__DATA_MASK 0xFFFFFFFFL |
35066 | //RLC_RLCS_GENERAL_3 |
35067 | #define RLC_RLCS_GENERAL_3__DATA__SHIFT 0x0 |
35068 | #define RLC_RLCS_GENERAL_3__DATA_MASK 0xFFFFFFFFL |
35069 | //RLC_RLCS_GENERAL_4 |
35070 | #define RLC_RLCS_GENERAL_4__DATA__SHIFT 0x0 |
35071 | #define RLC_RLCS_GENERAL_4__DATA_MASK 0xFFFFFFFFL |
35072 | //RLC_RLCS_GENERAL_5 |
35073 | #define RLC_RLCS_GENERAL_5__DATA__SHIFT 0x0 |
35074 | #define RLC_RLCS_GENERAL_5__DATA_MASK 0xFFFFFFFFL |
35075 | //RLC_RLCS_GRBM_IDLE_BUSY_STAT |
35076 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_gc_stat_idle__SHIFT 0x0 |
35077 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY__SHIFT 0x2 |
35078 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY__SHIFT 0x3 |
35079 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_4__SHIFT 0x4 |
35080 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED__SHIFT 0x5 |
35081 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED__SHIFT 0x6 |
35082 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_7__SHIFT 0x7 |
35083 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED__SHIFT 0x8 |
35084 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_gc_stat_idle_MASK 0x00000003L |
35085 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_MASK 0x00000004L |
35086 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_MASK 0x00000008L |
35087 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_4_MASK 0x00000010L |
35088 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED_MASK 0x00000020L |
35089 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED_MASK 0x00000040L |
35090 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_7_MASK 0x00000080L |
35091 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_MASK 0xFFFFFF00L |
35092 | //RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL |
35093 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR__SHIFT 0x0 |
35094 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR__SHIFT 0x1 |
35095 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__RESERVED_2__SHIFT 0x2 |
35096 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR_MASK 0x00000001L |
35097 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR_MASK 0x00000002L |
35098 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__RESERVED_2_MASK 0x00000004L |
35099 | //RLC_RLCS_CMP_IDLE_CNTL |
35100 | #define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR__SHIFT 0x0 |
35101 | #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST__SHIFT 0x1 |
35102 | #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE__SHIFT 0x2 |
35103 | #define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS__SHIFT 0x3 |
35104 | #define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT__SHIFT 0xb |
35105 | #define RLC_RLCS_CMP_IDLE_CNTL__RESERVED__SHIFT 0x13 |
35106 | #define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR_MASK 0x00000001L |
35107 | #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST_MASK 0x00000002L |
35108 | #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_MASK 0x00000004L |
35109 | #define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS_MASK 0x000007F8L |
35110 | #define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT_MASK 0x0007F800L |
35111 | #define RLC_RLCS_CMP_IDLE_CNTL__RESERVED_MASK 0xFFF80000L |
35112 | //RLC_RLCS_POWER_BRAKE_CNTL_TH1 |
35113 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE__SHIFT 0x0 |
35114 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR__SHIFT 0x1 |
35115 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS__SHIFT 0x2 |
35116 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT__SHIFT 0xa |
35117 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED__SHIFT 0x12 |
35118 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE_MASK 0x00000001L |
35119 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR_MASK 0x00000002L |
35120 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS_MASK 0x000003FCL |
35121 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT_MASK 0x0003FC00L |
35122 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED_MASK 0xFFFC0000L |
35123 | //RLC_RLCS_AUXILIARY_REG_1 |
35124 | #define RLC_RLCS_AUXILIARY_REG_1__ADDR__SHIFT 0x0 |
35125 | #define RLC_RLCS_AUXILIARY_REG_1__RESERVED__SHIFT 0x12 |
35126 | #define RLC_RLCS_AUXILIARY_REG_1__ADDR_MASK 0x0003FFFFL |
35127 | #define RLC_RLCS_AUXILIARY_REG_1__RESERVED_MASK 0xFFFC0000L |
35128 | //RLC_RLCS_AUXILIARY_REG_2 |
35129 | #define RLC_RLCS_AUXILIARY_REG_2__ADDR__SHIFT 0x0 |
35130 | #define RLC_RLCS_AUXILIARY_REG_2__RESERVED__SHIFT 0x12 |
35131 | #define RLC_RLCS_AUXILIARY_REG_2__ADDR_MASK 0x0003FFFFL |
35132 | #define RLC_RLCS_AUXILIARY_REG_2__RESERVED_MASK 0xFFFC0000L |
35133 | //RLC_RLCS_AUXILIARY_REG_3 |
35134 | #define RLC_RLCS_AUXILIARY_REG_3__ADDR__SHIFT 0x0 |
35135 | #define RLC_RLCS_AUXILIARY_REG_3__RESERVED__SHIFT 0x12 |
35136 | #define RLC_RLCS_AUXILIARY_REG_3__ADDR_MASK 0x0003FFFFL |
35137 | #define RLC_RLCS_AUXILIARY_REG_3__RESERVED_MASK 0xFFFC0000L |
35138 | //RLC_RLCS_AUXILIARY_REG_4 |
35139 | #define RLC_RLCS_AUXILIARY_REG_4__ADDR__SHIFT 0x0 |
35140 | #define RLC_RLCS_AUXILIARY_REG_4__RESERVED__SHIFT 0x12 |
35141 | #define RLC_RLCS_AUXILIARY_REG_4__ADDR_MASK 0x0003FFFFL |
35142 | #define RLC_RLCS_AUXILIARY_REG_4__RESERVED_MASK 0xFFFC0000L |
35143 | //RLC_RLCS_SPM_SQTT_MODE |
35144 | #define RLC_RLCS_SPM_SQTT_MODE__MODE__SHIFT 0x0 |
35145 | #define RLC_RLCS_SPM_SQTT_MODE__MODE_MASK 0x00000001L |
35146 | //RLC_RLCS_CP_DMA_SRCID_OVER |
35147 | #define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE__SHIFT 0x0 |
35148 | #define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE_MASK 0x00000001L |
35149 | //RLC_RLCS_UTCL2_CNTL |
35150 | #define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0 |
35151 | #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE__SHIFT 0x1 |
35152 | #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE__SHIFT 0x2 |
35153 | #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE__SHIFT 0x3 |
35154 | #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE__SHIFT 0x5 |
35155 | #define RLC_RLCS_UTCL2_CNTL__RESERVED__SHIFT 0x6 |
35156 | #define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L |
35157 | #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_MASK 0x00000002L |
35158 | #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_MASK 0x00000004L |
35159 | #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE_MASK 0x00000018L |
35160 | #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE_MASK 0x00000020L |
35161 | #define RLC_RLCS_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFC0L |
35162 | //RLC_RLCS_MP1_RLC_DOORBELL_CTRL |
35163 | #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__INT_CLEAR__SHIFT 0x0 |
35164 | #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__DOORBELL__SHIFT 0x1 |
35165 | #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__RESERVED__SHIFT 0x2 |
35166 | #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__INT_CLEAR_MASK 0x00000001L |
35167 | #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__DOORBELL_MASK 0x00000002L |
35168 | #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__RESERVED_MASK 0xFFFFFFFCL |
35169 | //RLC_RLCS_BOOTLOAD_ID_STATUS1 |
35170 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED__SHIFT 0x0 |
35171 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED__SHIFT 0x1 |
35172 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED__SHIFT 0x2 |
35173 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED__SHIFT 0x3 |
35174 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED__SHIFT 0x4 |
35175 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED__SHIFT 0x5 |
35176 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED__SHIFT 0x6 |
35177 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED__SHIFT 0x7 |
35178 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED__SHIFT 0x8 |
35179 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED__SHIFT 0x9 |
35180 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED__SHIFT 0xa |
35181 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED__SHIFT 0xb |
35182 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED__SHIFT 0xc |
35183 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED__SHIFT 0xd |
35184 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED__SHIFT 0xe |
35185 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED__SHIFT 0xf |
35186 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED__SHIFT 0x10 |
35187 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED__SHIFT 0x11 |
35188 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED__SHIFT 0x12 |
35189 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED__SHIFT 0x13 |
35190 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED__SHIFT 0x14 |
35191 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED__SHIFT 0x15 |
35192 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED__SHIFT 0x16 |
35193 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED__SHIFT 0x17 |
35194 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED__SHIFT 0x18 |
35195 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED__SHIFT 0x19 |
35196 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED__SHIFT 0x1a |
35197 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED__SHIFT 0x1b |
35198 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED__SHIFT 0x1c |
35199 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED__SHIFT 0x1d |
35200 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED__SHIFT 0x1e |
35201 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED__SHIFT 0x1f |
35202 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED_MASK 0x00000001L |
35203 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED_MASK 0x00000002L |
35204 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED_MASK 0x00000004L |
35205 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED_MASK 0x00000008L |
35206 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED_MASK 0x00000010L |
35207 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED_MASK 0x00000020L |
35208 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED_MASK 0x00000040L |
35209 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED_MASK 0x00000080L |
35210 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED_MASK 0x00000100L |
35211 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED_MASK 0x00000200L |
35212 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED_MASK 0x00000400L |
35213 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED_MASK 0x00000800L |
35214 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED_MASK 0x00001000L |
35215 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED_MASK 0x00002000L |
35216 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED_MASK 0x00004000L |
35217 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED_MASK 0x00008000L |
35218 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED_MASK 0x00010000L |
35219 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED_MASK 0x00020000L |
35220 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED_MASK 0x00040000L |
35221 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED_MASK 0x00080000L |
35222 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED_MASK 0x00100000L |
35223 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED_MASK 0x00200000L |
35224 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED_MASK 0x00400000L |
35225 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED_MASK 0x00800000L |
35226 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED_MASK 0x01000000L |
35227 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED_MASK 0x02000000L |
35228 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED_MASK 0x04000000L |
35229 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED_MASK 0x08000000L |
35230 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED_MASK 0x10000000L |
35231 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED_MASK 0x20000000L |
35232 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED_MASK 0x40000000L |
35233 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED_MASK 0x80000000L |
35234 | //RLC_RLCS_BOOTLOAD_ID_STATUS2 |
35235 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED__SHIFT 0x0 |
35236 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED__SHIFT 0x1 |
35237 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED__SHIFT 0x2 |
35238 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED__SHIFT 0x3 |
35239 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED__SHIFT 0x4 |
35240 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED__SHIFT 0x5 |
35241 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED__SHIFT 0x6 |
35242 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED__SHIFT 0x7 |
35243 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED__SHIFT 0x8 |
35244 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED__SHIFT 0x9 |
35245 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED__SHIFT 0xa |
35246 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED__SHIFT 0xb |
35247 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED__SHIFT 0xc |
35248 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED__SHIFT 0xd |
35249 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED__SHIFT 0xe |
35250 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED__SHIFT 0xf |
35251 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED__SHIFT 0x10 |
35252 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED__SHIFT 0x11 |
35253 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED__SHIFT 0x12 |
35254 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED__SHIFT 0x13 |
35255 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED__SHIFT 0x14 |
35256 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED__SHIFT 0x15 |
35257 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED__SHIFT 0x16 |
35258 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED__SHIFT 0x17 |
35259 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED__SHIFT 0x18 |
35260 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED__SHIFT 0x19 |
35261 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED__SHIFT 0x1a |
35262 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED__SHIFT 0x1b |
35263 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED__SHIFT 0x1c |
35264 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED__SHIFT 0x1d |
35265 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED__SHIFT 0x1e |
35266 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED__SHIFT 0x1f |
35267 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED_MASK 0x00000001L |
35268 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED_MASK 0x00000002L |
35269 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED_MASK 0x00000004L |
35270 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED_MASK 0x00000008L |
35271 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED_MASK 0x00000010L |
35272 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED_MASK 0x00000020L |
35273 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED_MASK 0x00000040L |
35274 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED_MASK 0x00000080L |
35275 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED_MASK 0x00000100L |
35276 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED_MASK 0x00000200L |
35277 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED_MASK 0x00000400L |
35278 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED_MASK 0x00000800L |
35279 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED_MASK 0x00001000L |
35280 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED_MASK 0x00002000L |
35281 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED_MASK 0x00004000L |
35282 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED_MASK 0x00008000L |
35283 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED_MASK 0x00010000L |
35284 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED_MASK 0x00020000L |
35285 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED_MASK 0x00040000L |
35286 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED_MASK 0x00080000L |
35287 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED_MASK 0x00100000L |
35288 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED_MASK 0x00200000L |
35289 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED_MASK 0x00400000L |
35290 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED_MASK 0x00800000L |
35291 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED_MASK 0x01000000L |
35292 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED_MASK 0x02000000L |
35293 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED_MASK 0x04000000L |
35294 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED_MASK 0x08000000L |
35295 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED_MASK 0x10000000L |
35296 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED_MASK 0x20000000L |
35297 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED_MASK 0x40000000L |
35298 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED_MASK 0x80000000L |
35299 | //RLC_RLCS_EDC_INT_CNTL |
35300 | #define RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR__SHIFT 0x0 |
35301 | #define RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR_MASK 0x00000001L |
35302 | //RLC_RLCS_DEC_END |
35303 | |
35304 | |
35305 | // addressBlock: gc_pwrdec |
35306 | //CGTS_SA0_QUAD0_SM_CTRL_REG |
35307 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 |
35308 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 |
35309 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__MASK_OVERRIDE__SHIFT 0xf |
35310 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 |
35311 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT 0x11 |
35312 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 |
35313 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 |
35314 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 |
35315 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_MGCG_EN__SHIFT 0x17 |
35316 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_CLKEN_MODE__SHIFT 0x18 |
35317 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_SW_CLKEN__SHIFT 0x19 |
35318 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_CLKEN_DELAY__SHIFT 0x1a |
35319 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL |
35320 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L |
35321 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__MASK_OVERRIDE_MASK 0x00008000L |
35322 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L |
35323 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L |
35324 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L |
35325 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L |
35326 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L |
35327 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_MGCG_EN_MASK 0x00800000L |
35328 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_CLKEN_MODE_MASK 0x01000000L |
35329 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_SW_CLKEN_MASK 0x02000000L |
35330 | #define CGTS_SA0_QUAD0_SM_CTRL_REG__CGTS_CLKEN_DELAY_MASK 0xFC000000L |
35331 | //CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG |
35332 | #define CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY__SHIFT 0x0 |
35333 | #define CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT 0xa |
35334 | #define CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY_MASK 0x000003FFL |
35335 | #define CGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY_MASK 0x0007FC00L |
35336 | //CGTS_SA0_QUAD1_SM_CTRL_REG |
35337 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 |
35338 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 |
35339 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__MASK_OVERRIDE__SHIFT 0xf |
35340 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 |
35341 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__SM_MODE__SHIFT 0x11 |
35342 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 |
35343 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 |
35344 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 |
35345 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_MGCG_EN__SHIFT 0x17 |
35346 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_CLKEN_MODE__SHIFT 0x18 |
35347 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_SW_CLKEN__SHIFT 0x19 |
35348 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_CLKEN_DELAY__SHIFT 0x1a |
35349 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL |
35350 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L |
35351 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__MASK_OVERRIDE_MASK 0x00008000L |
35352 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L |
35353 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L |
35354 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L |
35355 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L |
35356 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L |
35357 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_MGCG_EN_MASK 0x00800000L |
35358 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_CLKEN_MODE_MASK 0x01000000L |
35359 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_SW_CLKEN_MASK 0x02000000L |
35360 | #define CGTS_SA0_QUAD1_SM_CTRL_REG__CGTS_CLKEN_DELAY_MASK 0xFC000000L |
35361 | //CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG |
35362 | #define CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY__SHIFT 0x0 |
35363 | #define CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT 0xa |
35364 | #define CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY_MASK 0x000003FFL |
35365 | #define CGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY_MASK 0x0007FC00L |
35366 | //CGTS_SA1_QUAD0_SM_CTRL_REG |
35367 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 |
35368 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 |
35369 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__MASK_OVERRIDE__SHIFT 0xf |
35370 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 |
35371 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT 0x11 |
35372 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 |
35373 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 |
35374 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 |
35375 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_MGCG_EN__SHIFT 0x17 |
35376 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_CLKEN_MODE__SHIFT 0x18 |
35377 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_SW_CLKEN__SHIFT 0x19 |
35378 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_CLKEN_DELAY__SHIFT 0x1a |
35379 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL |
35380 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L |
35381 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__MASK_OVERRIDE_MASK 0x00008000L |
35382 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L |
35383 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L |
35384 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L |
35385 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L |
35386 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L |
35387 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_MGCG_EN_MASK 0x00800000L |
35388 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_CLKEN_MODE_MASK 0x01000000L |
35389 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_SW_CLKEN_MASK 0x02000000L |
35390 | #define CGTS_SA1_QUAD0_SM_CTRL_REG__CGTS_CLKEN_DELAY_MASK 0xFC000000L |
35391 | //CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG |
35392 | #define CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY__SHIFT 0x0 |
35393 | #define CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT 0xa |
35394 | #define CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY_MASK 0x000003FFL |
35395 | #define CGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY_MASK 0x0007FC00L |
35396 | //CGTS_SA1_QUAD1_SM_CTRL_REG |
35397 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 |
35398 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 |
35399 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__MASK_OVERRIDE__SHIFT 0xf |
35400 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 |
35401 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__SM_MODE__SHIFT 0x11 |
35402 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 |
35403 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 |
35404 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 |
35405 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_MGCG_EN__SHIFT 0x17 |
35406 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_CLKEN_MODE__SHIFT 0x18 |
35407 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_SW_CLKEN__SHIFT 0x19 |
35408 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_CLKEN_DELAY__SHIFT 0x1a |
35409 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL |
35410 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L |
35411 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__MASK_OVERRIDE_MASK 0x00008000L |
35412 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L |
35413 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L |
35414 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L |
35415 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L |
35416 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L |
35417 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_MGCG_EN_MASK 0x00800000L |
35418 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_CLKEN_MODE_MASK 0x01000000L |
35419 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_SW_CLKEN_MASK 0x02000000L |
35420 | #define CGTS_SA1_QUAD1_SM_CTRL_REG__CGTS_CLKEN_DELAY_MASK 0xFC000000L |
35421 | //CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG |
35422 | #define CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY__SHIFT 0x0 |
35423 | #define CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY__SHIFT 0xa |
35424 | #define CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG__OFF_MONITOR_DELAY_MASK 0x000003FFL |
35425 | #define CGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG__ON_MONITOR_DELAY_MASK 0x0007FC00L |
35426 | //CGTS_RD_CTRL_REG |
35427 | #define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 |
35428 | #define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x4 |
35429 | #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000000FL |
35430 | #define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x000000F0L |
35431 | //CGTS_RD_REG |
35432 | #define CGTS_RD_REG__READ_DATA__SHIFT 0x0 |
35433 | #define CGTS_RD_REG__READ_DATA_MASK 0xFFFFFFFFL |
35434 | //CGTS_TCC_DISABLE |
35435 | #define CGTS_TCC_DISABLE__HI_TCC_DISABLE__SHIFT 0x8 |
35436 | #define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 |
35437 | #define CGTS_TCC_DISABLE__HI_TCC_DISABLE_MASK 0x0000FF00L |
35438 | #define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L |
35439 | //CGTS_USER_TCC_DISABLE |
35440 | #define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE__SHIFT 0x8 |
35441 | #define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 |
35442 | #define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE_MASK 0x0000FF00L |
35443 | #define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L |
35444 | //CGTS_STATUS_REG |
35445 | #define CGTS_STATUS_REG__SA0_QUAD0_MGCG_ENABLED__SHIFT 0x0 |
35446 | #define CGTS_STATUS_REG__SA0_QUAD0_CG_STATUS__SHIFT 0x1 |
35447 | #define CGTS_STATUS_REG__SA0_QUAD1_MGCG_ENABLED__SHIFT 0x4 |
35448 | #define CGTS_STATUS_REG__SA0_QUAD1_CG_STATUS__SHIFT 0x5 |
35449 | #define CGTS_STATUS_REG__SA1_QUAD0_MGCG_ENABLED__SHIFT 0x8 |
35450 | #define CGTS_STATUS_REG__SA1_QUAD0_CG_STATUS__SHIFT 0x9 |
35451 | #define CGTS_STATUS_REG__SA1_QUAD1_MGCG_ENABLED__SHIFT 0xc |
35452 | #define CGTS_STATUS_REG__SA1_QUAD1_CG_STATUS__SHIFT 0xd |
35453 | #define CGTS_STATUS_REG__SA0_QUAD0_MGCG_ENABLED_MASK 0x00000001L |
35454 | #define CGTS_STATUS_REG__SA0_QUAD0_CG_STATUS_MASK 0x00000006L |
35455 | #define CGTS_STATUS_REG__SA0_QUAD1_MGCG_ENABLED_MASK 0x00000010L |
35456 | #define CGTS_STATUS_REG__SA0_QUAD1_CG_STATUS_MASK 0x00000060L |
35457 | #define CGTS_STATUS_REG__SA1_QUAD0_MGCG_ENABLED_MASK 0x00000100L |
35458 | #define CGTS_STATUS_REG__SA1_QUAD0_CG_STATUS_MASK 0x00000600L |
35459 | #define CGTS_STATUS_REG__SA1_QUAD1_MGCG_ENABLED_MASK 0x00001000L |
35460 | #define CGTS_STATUS_REG__SA1_QUAD1_CG_STATUS_MASK 0x00006000L |
35461 | //CGTT_SPI_CGTSSM_CLK_CTRL |
35462 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b |
35463 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c |
35464 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d |
35465 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e |
35466 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L |
35467 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L |
35468 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L |
35469 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L |
35470 | //CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG |
35471 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
35472 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
35473 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
35474 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
35475 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35476 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
35477 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
35478 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
35479 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
35480 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35481 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14 |
35482 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18 |
35483 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19 |
35484 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b |
35485 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
35486 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
35487 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
35488 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
35489 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
35490 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35491 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
35492 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
35493 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
35494 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
35495 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35496 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L |
35497 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L |
35498 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L |
35499 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L |
35500 | #define CGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
35501 | //CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG |
35502 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
35503 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
35504 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
35505 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
35506 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35507 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
35508 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
35509 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
35510 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
35511 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35512 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14 |
35513 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18 |
35514 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19 |
35515 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b |
35516 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
35517 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
35518 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
35519 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
35520 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
35521 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35522 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
35523 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
35524 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
35525 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
35526 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35527 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L |
35528 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L |
35529 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L |
35530 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L |
35531 | #define CGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
35532 | //CGTS_SA0_WGP00_CU0_TATD_CTRL_REG |
35533 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA__SHIFT 0x0 |
35534 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
35535 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
35536 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
35537 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35538 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD__SHIFT 0xa |
35539 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
35540 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
35541 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
35542 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35543 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL |
35544 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
35545 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
35546 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
35547 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35548 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L |
35549 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
35550 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
35551 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
35552 | #define CGTS_SA0_WGP00_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35553 | //CGTS_SA0_WGP00_CU0_TCP_CTRL_REG |
35554 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
35555 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
35556 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
35557 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
35558 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35559 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa |
35560 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
35561 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
35562 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
35563 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35564 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
35565 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
35566 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
35567 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
35568 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35569 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
35570 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
35571 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
35572 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
35573 | #define CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35574 | //CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG |
35575 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
35576 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
35577 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
35578 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
35579 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35580 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
35581 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
35582 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
35583 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
35584 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35585 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
35586 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
35587 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
35588 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
35589 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35590 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
35591 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
35592 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
35593 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
35594 | #define CGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35595 | //CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG |
35596 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
35597 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
35598 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
35599 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
35600 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35601 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
35602 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
35603 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
35604 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
35605 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35606 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
35607 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
35608 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
35609 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
35610 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35611 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
35612 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
35613 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
35614 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
35615 | #define CGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35616 | //CGTS_SA0_WGP00_CU1_TATD_CTRL_REG |
35617 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA__SHIFT 0x0 |
35618 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
35619 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
35620 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
35621 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35622 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD__SHIFT 0xa |
35623 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
35624 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
35625 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
35626 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35627 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL |
35628 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
35629 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
35630 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
35631 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35632 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L |
35633 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
35634 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
35635 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
35636 | #define CGTS_SA0_WGP00_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35637 | //CGTS_SA0_WGP00_CU1_TCP_CTRL_REG |
35638 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
35639 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
35640 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
35641 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
35642 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35643 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa |
35644 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
35645 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
35646 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
35647 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35648 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
35649 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
35650 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
35651 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
35652 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35653 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
35654 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
35655 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
35656 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
35657 | #define CGTS_SA0_WGP00_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35658 | //CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG |
35659 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
35660 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
35661 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
35662 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
35663 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35664 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
35665 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
35666 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
35667 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
35668 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35669 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14 |
35670 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18 |
35671 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19 |
35672 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b |
35673 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
35674 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
35675 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
35676 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
35677 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
35678 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35679 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
35680 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
35681 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
35682 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
35683 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35684 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L |
35685 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L |
35686 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L |
35687 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L |
35688 | #define CGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
35689 | //CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG |
35690 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
35691 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
35692 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
35693 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
35694 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35695 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
35696 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
35697 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
35698 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
35699 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35700 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14 |
35701 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18 |
35702 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19 |
35703 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b |
35704 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
35705 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
35706 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
35707 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
35708 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
35709 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35710 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
35711 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
35712 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
35713 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
35714 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35715 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L |
35716 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L |
35717 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L |
35718 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L |
35719 | #define CGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
35720 | //CGTS_SA0_WGP01_CU0_TATD_CTRL_REG |
35721 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA__SHIFT 0x0 |
35722 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
35723 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
35724 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
35725 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35726 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD__SHIFT 0xa |
35727 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
35728 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
35729 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
35730 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35731 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL |
35732 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
35733 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
35734 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
35735 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35736 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L |
35737 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
35738 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
35739 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
35740 | #define CGTS_SA0_WGP01_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35741 | //CGTS_SA0_WGP01_CU0_TCP_CTRL_REG |
35742 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
35743 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
35744 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
35745 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
35746 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35747 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa |
35748 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
35749 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
35750 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
35751 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35752 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
35753 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
35754 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
35755 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
35756 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35757 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
35758 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
35759 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
35760 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
35761 | #define CGTS_SA0_WGP01_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35762 | //CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG |
35763 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
35764 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
35765 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
35766 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
35767 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35768 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
35769 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
35770 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
35771 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
35772 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35773 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
35774 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
35775 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
35776 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
35777 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35778 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
35779 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
35780 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
35781 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
35782 | #define CGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35783 | //CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG |
35784 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
35785 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
35786 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
35787 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
35788 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35789 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
35790 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
35791 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
35792 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
35793 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35794 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
35795 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
35796 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
35797 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
35798 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35799 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
35800 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
35801 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
35802 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
35803 | #define CGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35804 | //CGTS_SA0_WGP01_CU1_TATD_CTRL_REG |
35805 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA__SHIFT 0x0 |
35806 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
35807 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
35808 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
35809 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35810 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD__SHIFT 0xa |
35811 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
35812 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
35813 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
35814 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35815 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL |
35816 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
35817 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
35818 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
35819 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35820 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L |
35821 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
35822 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
35823 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
35824 | #define CGTS_SA0_WGP01_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35825 | //CGTS_SA0_WGP01_CU1_TCP_CTRL_REG |
35826 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
35827 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
35828 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
35829 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
35830 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35831 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa |
35832 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
35833 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
35834 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
35835 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35836 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
35837 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
35838 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
35839 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
35840 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35841 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
35842 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
35843 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
35844 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
35845 | #define CGTS_SA0_WGP01_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35846 | //CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG |
35847 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
35848 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
35849 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
35850 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
35851 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35852 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
35853 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
35854 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
35855 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
35856 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35857 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14 |
35858 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18 |
35859 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19 |
35860 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b |
35861 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
35862 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
35863 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
35864 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
35865 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
35866 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35867 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
35868 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
35869 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
35870 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
35871 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35872 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L |
35873 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L |
35874 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L |
35875 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L |
35876 | #define CGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
35877 | //CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG |
35878 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
35879 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
35880 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
35881 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
35882 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35883 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
35884 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
35885 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
35886 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
35887 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35888 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14 |
35889 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18 |
35890 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19 |
35891 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b |
35892 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
35893 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
35894 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
35895 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
35896 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
35897 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35898 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
35899 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
35900 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
35901 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
35902 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35903 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L |
35904 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L |
35905 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L |
35906 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L |
35907 | #define CGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
35908 | //CGTS_SA0_WGP02_CU0_TATD_CTRL_REG |
35909 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA__SHIFT 0x0 |
35910 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
35911 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
35912 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
35913 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35914 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD__SHIFT 0xa |
35915 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
35916 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
35917 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
35918 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35919 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL |
35920 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
35921 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
35922 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
35923 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35924 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L |
35925 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
35926 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
35927 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
35928 | #define CGTS_SA0_WGP02_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35929 | //CGTS_SA0_WGP02_CU0_TCP_CTRL_REG |
35930 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
35931 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
35932 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
35933 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
35934 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35935 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa |
35936 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
35937 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
35938 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
35939 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35940 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
35941 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
35942 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
35943 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
35944 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35945 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
35946 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
35947 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
35948 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
35949 | #define CGTS_SA0_WGP02_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35950 | //CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG |
35951 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
35952 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
35953 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
35954 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
35955 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35956 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
35957 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
35958 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
35959 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
35960 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35961 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
35962 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
35963 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
35964 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
35965 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35966 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
35967 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
35968 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
35969 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
35970 | #define CGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35971 | //CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG |
35972 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
35973 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
35974 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
35975 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
35976 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35977 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
35978 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
35979 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
35980 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
35981 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
35982 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
35983 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
35984 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
35985 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
35986 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
35987 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
35988 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
35989 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
35990 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
35991 | #define CGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
35992 | //CGTS_SA0_WGP02_CU1_TATD_CTRL_REG |
35993 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA__SHIFT 0x0 |
35994 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
35995 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
35996 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
35997 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
35998 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD__SHIFT 0xa |
35999 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
36000 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
36001 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
36002 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36003 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL |
36004 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
36005 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
36006 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
36007 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36008 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L |
36009 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
36010 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
36011 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
36012 | #define CGTS_SA0_WGP02_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36013 | //CGTS_SA0_WGP02_CU1_TCP_CTRL_REG |
36014 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
36015 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
36016 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
36017 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
36018 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36019 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa |
36020 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
36021 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
36022 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
36023 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36024 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
36025 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
36026 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
36027 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
36028 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36029 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
36030 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
36031 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
36032 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
36033 | #define CGTS_SA0_WGP02_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36034 | //CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG |
36035 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
36036 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
36037 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
36038 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
36039 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36040 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
36041 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
36042 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
36043 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
36044 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36045 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14 |
36046 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18 |
36047 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19 |
36048 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b |
36049 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
36050 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
36051 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
36052 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
36053 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
36054 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36055 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
36056 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
36057 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
36058 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
36059 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36060 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L |
36061 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L |
36062 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L |
36063 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L |
36064 | #define CGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
36065 | //CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG |
36066 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
36067 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
36068 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
36069 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
36070 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36071 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
36072 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
36073 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
36074 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
36075 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36076 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14 |
36077 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18 |
36078 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19 |
36079 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b |
36080 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
36081 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
36082 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
36083 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
36084 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
36085 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36086 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
36087 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
36088 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
36089 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
36090 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36091 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L |
36092 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L |
36093 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L |
36094 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L |
36095 | #define CGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
36096 | //CGTS_SA0_WGP10_CU0_TATD_CTRL_REG |
36097 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA__SHIFT 0x0 |
36098 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
36099 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
36100 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
36101 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36102 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD__SHIFT 0xa |
36103 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
36104 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
36105 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
36106 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36107 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL |
36108 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
36109 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
36110 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
36111 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36112 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L |
36113 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
36114 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
36115 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
36116 | #define CGTS_SA0_WGP10_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36117 | //CGTS_SA0_WGP10_CU0_TCP_CTRL_REG |
36118 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
36119 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
36120 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
36121 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
36122 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36123 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa |
36124 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
36125 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
36126 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
36127 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36128 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
36129 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
36130 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
36131 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
36132 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36133 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
36134 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
36135 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
36136 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
36137 | #define CGTS_SA0_WGP10_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36138 | //CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG |
36139 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
36140 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
36141 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
36142 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
36143 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36144 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
36145 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
36146 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
36147 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
36148 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36149 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
36150 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
36151 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
36152 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
36153 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36154 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
36155 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
36156 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
36157 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
36158 | #define CGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36159 | //CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG |
36160 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
36161 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
36162 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
36163 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
36164 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36165 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
36166 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
36167 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
36168 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
36169 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36170 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
36171 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
36172 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
36173 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
36174 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36175 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
36176 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
36177 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
36178 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
36179 | #define CGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36180 | //CGTS_SA0_WGP10_CU1_TATD_CTRL_REG |
36181 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA__SHIFT 0x0 |
36182 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
36183 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
36184 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
36185 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36186 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD__SHIFT 0xa |
36187 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
36188 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
36189 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
36190 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36191 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL |
36192 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
36193 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
36194 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
36195 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36196 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L |
36197 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
36198 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
36199 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
36200 | #define CGTS_SA0_WGP10_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36201 | //CGTS_SA0_WGP10_CU1_TCP_CTRL_REG |
36202 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
36203 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
36204 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
36205 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
36206 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36207 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa |
36208 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
36209 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
36210 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
36211 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36212 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
36213 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
36214 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
36215 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
36216 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36217 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
36218 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
36219 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
36220 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
36221 | #define CGTS_SA0_WGP10_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36222 | //CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG |
36223 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
36224 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
36225 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
36226 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
36227 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36228 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
36229 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
36230 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
36231 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
36232 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36233 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14 |
36234 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18 |
36235 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19 |
36236 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b |
36237 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
36238 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
36239 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
36240 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
36241 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
36242 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36243 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
36244 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
36245 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
36246 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
36247 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36248 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L |
36249 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L |
36250 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L |
36251 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L |
36252 | #define CGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
36253 | //CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG |
36254 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
36255 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
36256 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
36257 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
36258 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36259 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
36260 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
36261 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
36262 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
36263 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36264 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14 |
36265 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18 |
36266 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19 |
36267 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b |
36268 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
36269 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
36270 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
36271 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
36272 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
36273 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36274 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
36275 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
36276 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
36277 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
36278 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36279 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L |
36280 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L |
36281 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L |
36282 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L |
36283 | #define CGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
36284 | //CGTS_SA0_WGP11_CU0_TATD_CTRL_REG |
36285 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA__SHIFT 0x0 |
36286 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
36287 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
36288 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
36289 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36290 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD__SHIFT 0xa |
36291 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
36292 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
36293 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
36294 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36295 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL |
36296 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
36297 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
36298 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
36299 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36300 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L |
36301 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
36302 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
36303 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
36304 | #define CGTS_SA0_WGP11_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36305 | //CGTS_SA0_WGP11_CU0_TCP_CTRL_REG |
36306 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
36307 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
36308 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
36309 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
36310 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36311 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa |
36312 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
36313 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
36314 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
36315 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36316 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
36317 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
36318 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
36319 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
36320 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36321 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
36322 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
36323 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
36324 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
36325 | #define CGTS_SA0_WGP11_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36326 | //CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG |
36327 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
36328 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
36329 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
36330 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
36331 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36332 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
36333 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
36334 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
36335 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
36336 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36337 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
36338 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
36339 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
36340 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
36341 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36342 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
36343 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
36344 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
36345 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
36346 | #define CGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36347 | //CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG |
36348 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
36349 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
36350 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
36351 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
36352 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36353 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
36354 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
36355 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
36356 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
36357 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36358 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
36359 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
36360 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
36361 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
36362 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36363 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
36364 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
36365 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
36366 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
36367 | #define CGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36368 | //CGTS_SA0_WGP11_CU1_TATD_CTRL_REG |
36369 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA__SHIFT 0x0 |
36370 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
36371 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
36372 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
36373 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36374 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD__SHIFT 0xa |
36375 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
36376 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
36377 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
36378 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36379 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL |
36380 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
36381 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
36382 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
36383 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36384 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L |
36385 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
36386 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
36387 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
36388 | #define CGTS_SA0_WGP11_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36389 | //CGTS_SA0_WGP11_CU1_TCP_CTRL_REG |
36390 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
36391 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
36392 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
36393 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
36394 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36395 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa |
36396 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
36397 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
36398 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
36399 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36400 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
36401 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
36402 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
36403 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
36404 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36405 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
36406 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
36407 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
36408 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
36409 | #define CGTS_SA0_WGP11_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36410 | //CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG |
36411 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
36412 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
36413 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
36414 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
36415 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36416 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
36417 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
36418 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
36419 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
36420 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36421 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14 |
36422 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18 |
36423 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19 |
36424 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b |
36425 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
36426 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
36427 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
36428 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
36429 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
36430 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36431 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
36432 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
36433 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
36434 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
36435 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36436 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L |
36437 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L |
36438 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L |
36439 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L |
36440 | #define CGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
36441 | //CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG |
36442 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
36443 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
36444 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
36445 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
36446 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36447 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
36448 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
36449 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
36450 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
36451 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36452 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14 |
36453 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18 |
36454 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19 |
36455 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b |
36456 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
36457 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
36458 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
36459 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
36460 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
36461 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36462 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
36463 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
36464 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
36465 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
36466 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36467 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L |
36468 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L |
36469 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L |
36470 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L |
36471 | #define CGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
36472 | //CGTS_SA1_WGP00_CU0_TATD_CTRL_REG |
36473 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA__SHIFT 0x0 |
36474 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
36475 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
36476 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
36477 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36478 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD__SHIFT 0xa |
36479 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
36480 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
36481 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
36482 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36483 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL |
36484 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
36485 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
36486 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
36487 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36488 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L |
36489 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
36490 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
36491 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
36492 | #define CGTS_SA1_WGP00_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36493 | //CGTS_SA1_WGP00_CU0_TCP_CTRL_REG |
36494 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
36495 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
36496 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
36497 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
36498 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36499 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa |
36500 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
36501 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
36502 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
36503 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36504 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
36505 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
36506 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
36507 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
36508 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36509 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
36510 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
36511 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
36512 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
36513 | #define CGTS_SA1_WGP00_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36514 | //CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG |
36515 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
36516 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
36517 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
36518 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
36519 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36520 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
36521 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
36522 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
36523 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
36524 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36525 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
36526 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
36527 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
36528 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
36529 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36530 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
36531 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
36532 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
36533 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
36534 | #define CGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36535 | //CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG |
36536 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
36537 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
36538 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
36539 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
36540 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36541 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
36542 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
36543 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
36544 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
36545 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36546 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
36547 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
36548 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
36549 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
36550 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36551 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
36552 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
36553 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
36554 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
36555 | #define CGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36556 | //CGTS_SA1_WGP00_CU1_TATD_CTRL_REG |
36557 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA__SHIFT 0x0 |
36558 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
36559 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
36560 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
36561 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36562 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD__SHIFT 0xa |
36563 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
36564 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
36565 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
36566 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36567 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL |
36568 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
36569 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
36570 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
36571 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36572 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L |
36573 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
36574 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
36575 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
36576 | #define CGTS_SA1_WGP00_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36577 | //CGTS_SA1_WGP00_CU1_TCP_CTRL_REG |
36578 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
36579 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
36580 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
36581 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
36582 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36583 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa |
36584 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
36585 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
36586 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
36587 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36588 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
36589 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
36590 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
36591 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
36592 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36593 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
36594 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
36595 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
36596 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
36597 | #define CGTS_SA1_WGP00_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36598 | //CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG |
36599 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
36600 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
36601 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
36602 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
36603 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36604 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
36605 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
36606 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
36607 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
36608 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36609 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14 |
36610 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18 |
36611 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19 |
36612 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b |
36613 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
36614 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
36615 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
36616 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
36617 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
36618 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36619 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
36620 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
36621 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
36622 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
36623 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36624 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L |
36625 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L |
36626 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L |
36627 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L |
36628 | #define CGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
36629 | //CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG |
36630 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
36631 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
36632 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
36633 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
36634 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36635 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
36636 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
36637 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
36638 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
36639 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36640 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14 |
36641 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18 |
36642 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19 |
36643 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b |
36644 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
36645 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
36646 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
36647 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
36648 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
36649 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36650 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
36651 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
36652 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
36653 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
36654 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36655 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L |
36656 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L |
36657 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L |
36658 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L |
36659 | #define CGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
36660 | //CGTS_SA1_WGP01_CU0_TATD_CTRL_REG |
36661 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA__SHIFT 0x0 |
36662 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
36663 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
36664 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
36665 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36666 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD__SHIFT 0xa |
36667 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
36668 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
36669 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
36670 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36671 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL |
36672 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
36673 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
36674 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
36675 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36676 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L |
36677 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
36678 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
36679 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
36680 | #define CGTS_SA1_WGP01_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36681 | //CGTS_SA1_WGP01_CU0_TCP_CTRL_REG |
36682 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
36683 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
36684 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
36685 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
36686 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36687 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa |
36688 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
36689 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
36690 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
36691 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36692 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
36693 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
36694 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
36695 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
36696 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36697 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
36698 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
36699 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
36700 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
36701 | #define CGTS_SA1_WGP01_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36702 | //CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG |
36703 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
36704 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
36705 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
36706 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
36707 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36708 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
36709 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
36710 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
36711 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
36712 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36713 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
36714 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
36715 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
36716 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
36717 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36718 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
36719 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
36720 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
36721 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
36722 | #define CGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36723 | //CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG |
36724 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
36725 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
36726 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
36727 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
36728 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36729 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
36730 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
36731 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
36732 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
36733 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36734 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
36735 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
36736 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
36737 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
36738 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36739 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
36740 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
36741 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
36742 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
36743 | #define CGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36744 | //CGTS_SA1_WGP01_CU1_TATD_CTRL_REG |
36745 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA__SHIFT 0x0 |
36746 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
36747 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
36748 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
36749 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36750 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD__SHIFT 0xa |
36751 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
36752 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
36753 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
36754 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36755 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL |
36756 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
36757 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
36758 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
36759 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36760 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L |
36761 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
36762 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
36763 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
36764 | #define CGTS_SA1_WGP01_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36765 | //CGTS_SA1_WGP01_CU1_TCP_CTRL_REG |
36766 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
36767 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
36768 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
36769 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
36770 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36771 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa |
36772 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
36773 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
36774 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
36775 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36776 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
36777 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
36778 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
36779 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
36780 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36781 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
36782 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
36783 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
36784 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
36785 | #define CGTS_SA1_WGP01_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36786 | //CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG |
36787 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
36788 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
36789 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
36790 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
36791 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36792 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
36793 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
36794 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
36795 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
36796 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36797 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14 |
36798 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18 |
36799 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19 |
36800 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b |
36801 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
36802 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
36803 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
36804 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
36805 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
36806 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36807 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
36808 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
36809 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
36810 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
36811 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36812 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L |
36813 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L |
36814 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L |
36815 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L |
36816 | #define CGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
36817 | //CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG |
36818 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
36819 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
36820 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
36821 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
36822 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36823 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
36824 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
36825 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
36826 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
36827 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36828 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14 |
36829 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18 |
36830 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19 |
36831 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b |
36832 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
36833 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
36834 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
36835 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
36836 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
36837 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36838 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
36839 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
36840 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
36841 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
36842 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36843 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L |
36844 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L |
36845 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L |
36846 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L |
36847 | #define CGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
36848 | //CGTS_SA1_WGP02_CU0_TATD_CTRL_REG |
36849 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA__SHIFT 0x0 |
36850 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
36851 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
36852 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
36853 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36854 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD__SHIFT 0xa |
36855 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
36856 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
36857 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
36858 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36859 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL |
36860 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
36861 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
36862 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
36863 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36864 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L |
36865 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
36866 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
36867 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
36868 | #define CGTS_SA1_WGP02_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36869 | //CGTS_SA1_WGP02_CU0_TCP_CTRL_REG |
36870 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
36871 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
36872 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
36873 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
36874 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36875 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa |
36876 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
36877 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
36878 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
36879 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36880 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
36881 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
36882 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
36883 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
36884 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36885 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
36886 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
36887 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
36888 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
36889 | #define CGTS_SA1_WGP02_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36890 | //CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG |
36891 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
36892 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
36893 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
36894 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
36895 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36896 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
36897 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
36898 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
36899 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
36900 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36901 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
36902 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
36903 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
36904 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
36905 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36906 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
36907 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
36908 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
36909 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
36910 | #define CGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36911 | //CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG |
36912 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
36913 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
36914 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
36915 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
36916 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36917 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
36918 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
36919 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
36920 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
36921 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36922 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
36923 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
36924 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
36925 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
36926 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36927 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
36928 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
36929 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
36930 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
36931 | #define CGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36932 | //CGTS_SA1_WGP02_CU1_TATD_CTRL_REG |
36933 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA__SHIFT 0x0 |
36934 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
36935 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
36936 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
36937 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36938 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD__SHIFT 0xa |
36939 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
36940 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
36941 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
36942 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36943 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL |
36944 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
36945 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
36946 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
36947 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36948 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L |
36949 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
36950 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
36951 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
36952 | #define CGTS_SA1_WGP02_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36953 | //CGTS_SA1_WGP02_CU1_TCP_CTRL_REG |
36954 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
36955 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
36956 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
36957 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
36958 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36959 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa |
36960 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
36961 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
36962 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
36963 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36964 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
36965 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
36966 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
36967 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
36968 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36969 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
36970 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
36971 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
36972 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
36973 | #define CGTS_SA1_WGP02_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
36974 | //CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG |
36975 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
36976 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
36977 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
36978 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
36979 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
36980 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
36981 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
36982 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
36983 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
36984 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
36985 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14 |
36986 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18 |
36987 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19 |
36988 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b |
36989 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
36990 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
36991 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
36992 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
36993 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
36994 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
36995 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
36996 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
36997 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
36998 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
36999 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37000 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L |
37001 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L |
37002 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L |
37003 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L |
37004 | #define CGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
37005 | //CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG |
37006 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
37007 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
37008 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
37009 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
37010 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37011 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
37012 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
37013 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
37014 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
37015 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37016 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14 |
37017 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18 |
37018 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19 |
37019 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b |
37020 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
37021 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
37022 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
37023 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
37024 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
37025 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37026 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
37027 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
37028 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
37029 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
37030 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37031 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L |
37032 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L |
37033 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L |
37034 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L |
37035 | #define CGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
37036 | //CGTS_SA1_WGP10_CU0_TATD_CTRL_REG |
37037 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA__SHIFT 0x0 |
37038 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
37039 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
37040 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
37041 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37042 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD__SHIFT 0xa |
37043 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
37044 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
37045 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
37046 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37047 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL |
37048 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
37049 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
37050 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
37051 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37052 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L |
37053 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
37054 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
37055 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
37056 | #define CGTS_SA1_WGP10_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37057 | //CGTS_SA1_WGP10_CU0_TCP_CTRL_REG |
37058 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
37059 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
37060 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
37061 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
37062 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37063 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa |
37064 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
37065 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
37066 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
37067 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37068 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
37069 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
37070 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
37071 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
37072 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37073 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
37074 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
37075 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
37076 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
37077 | #define CGTS_SA1_WGP10_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37078 | //CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG |
37079 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
37080 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
37081 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
37082 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
37083 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37084 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
37085 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
37086 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
37087 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
37088 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37089 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
37090 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
37091 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
37092 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
37093 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37094 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
37095 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
37096 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
37097 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
37098 | #define CGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37099 | //CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG |
37100 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
37101 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
37102 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
37103 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
37104 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37105 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
37106 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
37107 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
37108 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
37109 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37110 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
37111 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
37112 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
37113 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
37114 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37115 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
37116 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
37117 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
37118 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
37119 | #define CGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37120 | //CGTS_SA1_WGP10_CU1_TATD_CTRL_REG |
37121 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA__SHIFT 0x0 |
37122 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
37123 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
37124 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
37125 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37126 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD__SHIFT 0xa |
37127 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
37128 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
37129 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
37130 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37131 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL |
37132 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
37133 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
37134 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
37135 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37136 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L |
37137 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
37138 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
37139 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
37140 | #define CGTS_SA1_WGP10_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37141 | //CGTS_SA1_WGP10_CU1_TCP_CTRL_REG |
37142 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
37143 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
37144 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
37145 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
37146 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37147 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa |
37148 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
37149 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
37150 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
37151 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37152 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
37153 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
37154 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
37155 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
37156 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37157 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
37158 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
37159 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
37160 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
37161 | #define CGTS_SA1_WGP10_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37162 | //CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG |
37163 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
37164 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
37165 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
37166 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
37167 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37168 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
37169 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
37170 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
37171 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
37172 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37173 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14 |
37174 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18 |
37175 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19 |
37176 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b |
37177 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
37178 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
37179 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
37180 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
37181 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
37182 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37183 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
37184 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
37185 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
37186 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
37187 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37188 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L |
37189 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L |
37190 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L |
37191 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L |
37192 | #define CGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
37193 | //CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG |
37194 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
37195 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
37196 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
37197 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
37198 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37199 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
37200 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
37201 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
37202 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
37203 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37204 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14 |
37205 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18 |
37206 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19 |
37207 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b |
37208 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
37209 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
37210 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
37211 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
37212 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
37213 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37214 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
37215 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
37216 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
37217 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
37218 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37219 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L |
37220 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L |
37221 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L |
37222 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L |
37223 | #define CGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
37224 | //CGTS_SA1_WGP11_CU0_TATD_CTRL_REG |
37225 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA__SHIFT 0x0 |
37226 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
37227 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
37228 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
37229 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37230 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD__SHIFT 0xa |
37231 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
37232 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
37233 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
37234 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37235 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL |
37236 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
37237 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
37238 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
37239 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37240 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L |
37241 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
37242 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
37243 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
37244 | #define CGTS_SA1_WGP11_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37245 | //CGTS_SA1_WGP11_CU0_TCP_CTRL_REG |
37246 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
37247 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
37248 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
37249 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
37250 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37251 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa |
37252 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
37253 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
37254 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
37255 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37256 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
37257 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
37258 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
37259 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
37260 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37261 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
37262 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
37263 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
37264 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
37265 | #define CGTS_SA1_WGP11_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37266 | //CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG |
37267 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
37268 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
37269 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
37270 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
37271 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37272 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
37273 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
37274 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
37275 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
37276 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37277 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
37278 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
37279 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
37280 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
37281 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37282 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
37283 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
37284 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
37285 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
37286 | #define CGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37287 | //CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG |
37288 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
37289 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
37290 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
37291 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
37292 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37293 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
37294 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
37295 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
37296 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
37297 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37298 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
37299 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
37300 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
37301 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
37302 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37303 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
37304 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
37305 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
37306 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
37307 | #define CGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37308 | //CGTS_SA1_WGP11_CU1_TATD_CTRL_REG |
37309 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA__SHIFT 0x0 |
37310 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
37311 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
37312 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
37313 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37314 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD__SHIFT 0xa |
37315 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
37316 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
37317 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
37318 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37319 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL |
37320 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
37321 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
37322 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
37323 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37324 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L |
37325 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
37326 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
37327 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
37328 | #define CGTS_SA1_WGP11_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37329 | //CGTS_SA1_WGP11_CU1_TCP_CTRL_REG |
37330 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
37331 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
37332 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
37333 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
37334 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37335 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa |
37336 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
37337 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
37338 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
37339 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37340 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
37341 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
37342 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
37343 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
37344 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37345 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
37346 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
37347 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
37348 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
37349 | #define CGTS_SA1_WGP11_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37350 | //CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG |
37351 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
37352 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
37353 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
37354 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
37355 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37356 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
37357 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
37358 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
37359 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
37360 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37361 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14 |
37362 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18 |
37363 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19 |
37364 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b |
37365 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
37366 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
37367 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
37368 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
37369 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
37370 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37371 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
37372 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
37373 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
37374 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
37375 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37376 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L |
37377 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L |
37378 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L |
37379 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L |
37380 | #define CGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
37381 | //CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG |
37382 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
37383 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
37384 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
37385 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
37386 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37387 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
37388 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
37389 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
37390 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
37391 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37392 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14 |
37393 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18 |
37394 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19 |
37395 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b |
37396 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
37397 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
37398 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
37399 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
37400 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
37401 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37402 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
37403 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
37404 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
37405 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
37406 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37407 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L |
37408 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L |
37409 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L |
37410 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L |
37411 | #define CGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
37412 | //CGTS_SA0_WGP12_CU0_TATD_CTRL_REG |
37413 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA__SHIFT 0x0 |
37414 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
37415 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
37416 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
37417 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37418 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD__SHIFT 0xa |
37419 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
37420 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
37421 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
37422 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37423 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL |
37424 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
37425 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
37426 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
37427 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37428 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L |
37429 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
37430 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
37431 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
37432 | #define CGTS_SA0_WGP12_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37433 | //CGTS_SA0_WGP12_CU0_TCP_CTRL_REG |
37434 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
37435 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
37436 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
37437 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
37438 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37439 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa |
37440 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
37441 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
37442 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
37443 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37444 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
37445 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
37446 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
37447 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
37448 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37449 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
37450 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
37451 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
37452 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
37453 | #define CGTS_SA0_WGP12_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37454 | //CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG |
37455 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
37456 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
37457 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
37458 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
37459 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37460 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
37461 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
37462 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
37463 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
37464 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37465 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
37466 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
37467 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
37468 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
37469 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37470 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
37471 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
37472 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
37473 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
37474 | #define CGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37475 | //CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG |
37476 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
37477 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
37478 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
37479 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
37480 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37481 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
37482 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
37483 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
37484 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
37485 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37486 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
37487 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
37488 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
37489 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
37490 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37491 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
37492 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
37493 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
37494 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
37495 | #define CGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37496 | //CGTS_SA0_WGP12_CU1_TATD_CTRL_REG |
37497 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA__SHIFT 0x0 |
37498 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
37499 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
37500 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
37501 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37502 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD__SHIFT 0xa |
37503 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
37504 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
37505 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
37506 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37507 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL |
37508 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
37509 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
37510 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
37511 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37512 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L |
37513 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
37514 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
37515 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
37516 | #define CGTS_SA0_WGP12_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37517 | //CGTS_SA0_WGP12_CU1_TCP_CTRL_REG |
37518 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
37519 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
37520 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
37521 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
37522 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37523 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa |
37524 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
37525 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
37526 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
37527 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37528 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
37529 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
37530 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
37531 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
37532 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37533 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
37534 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
37535 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
37536 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
37537 | #define CGTS_SA0_WGP12_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37538 | //CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG |
37539 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
37540 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
37541 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
37542 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
37543 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37544 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
37545 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
37546 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
37547 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
37548 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37549 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC__SHIFT 0x14 |
37550 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE__SHIFT 0x18 |
37551 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x19 |
37552 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1b |
37553 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
37554 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
37555 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
37556 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
37557 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
37558 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37559 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
37560 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
37561 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
37562 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
37563 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37564 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_MASK 0x00F00000L |
37565 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_OVERRIDE_MASK 0x01000000L |
37566 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x06000000L |
37567 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x08000000L |
37568 | #define CGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
37569 | //CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG |
37570 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
37571 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
37572 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
37573 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
37574 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37575 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
37576 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
37577 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
37578 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
37579 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37580 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS__SHIFT 0x14 |
37581 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE__SHIFT 0x18 |
37582 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x19 |
37583 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0x1b |
37584 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0x1c |
37585 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
37586 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
37587 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
37588 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
37589 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37590 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
37591 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
37592 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
37593 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
37594 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37595 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_MASK 0x00F00000L |
37596 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_OVERRIDE_MASK 0x01000000L |
37597 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x06000000L |
37598 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x08000000L |
37599 | #define CGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x10000000L |
37600 | //CGTS_SA1_WGP12_CU0_TATD_CTRL_REG |
37601 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA__SHIFT 0x0 |
37602 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
37603 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
37604 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
37605 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37606 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD__SHIFT 0xa |
37607 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
37608 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
37609 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
37610 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37611 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_MASK 0x0000000FL |
37612 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
37613 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
37614 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
37615 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37616 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_MASK 0x00003C00L |
37617 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
37618 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
37619 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
37620 | #define CGTS_SA1_WGP12_CU0_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37621 | //CGTS_SA1_WGP12_CU0_TCP_CTRL_REG |
37622 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
37623 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
37624 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
37625 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
37626 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37627 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI__SHIFT 0xa |
37628 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
37629 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
37630 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
37631 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37632 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
37633 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
37634 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
37635 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
37636 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37637 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
37638 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
37639 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
37640 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
37641 | #define CGTS_SA1_WGP12_CU0_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37642 | //CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG |
37643 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0__SHIFT 0x0 |
37644 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE__SHIFT 0x4 |
37645 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE__SHIFT 0x5 |
37646 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE__SHIFT 0x7 |
37647 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37648 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0__SHIFT 0xa |
37649 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE__SHIFT 0xe |
37650 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE__SHIFT 0xf |
37651 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE__SHIFT 0x11 |
37652 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37653 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_MASK 0x0000000FL |
37654 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_OVERRIDE_MASK 0x00000010L |
37655 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_BUSY_OVERRIDE_MASK 0x00000060L |
37656 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_LS_OVERRIDE_MASK 0x00000080L |
37657 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SIMD0_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37658 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_MASK 0x00003C00L |
37659 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_OVERRIDE_MASK 0x00004000L |
37660 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_BUSY_OVERRIDE_MASK 0x00018000L |
37661 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_LS_OVERRIDE_MASK 0x00020000L |
37662 | #define CGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG__SQ0_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37663 | //CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG |
37664 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1__SHIFT 0x0 |
37665 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE__SHIFT 0x4 |
37666 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE__SHIFT 0x5 |
37667 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE__SHIFT 0x7 |
37668 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37669 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1__SHIFT 0xa |
37670 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE__SHIFT 0xe |
37671 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE__SHIFT 0xf |
37672 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE__SHIFT 0x11 |
37673 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37674 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_MASK 0x0000000FL |
37675 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_OVERRIDE_MASK 0x00000010L |
37676 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_BUSY_OVERRIDE_MASK 0x00000060L |
37677 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_LS_OVERRIDE_MASK 0x00000080L |
37678 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SIMD1_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37679 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_MASK 0x00003C00L |
37680 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_OVERRIDE_MASK 0x00004000L |
37681 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_BUSY_OVERRIDE_MASK 0x00018000L |
37682 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_LS_OVERRIDE_MASK 0x00020000L |
37683 | #define CGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG__SQ1_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37684 | //CGTS_SA1_WGP12_CU1_TATD_CTRL_REG |
37685 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA__SHIFT 0x0 |
37686 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_OVERRIDE__SHIFT 0x4 |
37687 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x5 |
37688 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0x7 |
37689 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37690 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD__SHIFT 0xa |
37691 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_OVERRIDE__SHIFT 0xe |
37692 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0xf |
37693 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0x11 |
37694 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37695 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_MASK 0x0000000FL |
37696 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_OVERRIDE_MASK 0x00000010L |
37697 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000060L |
37698 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000080L |
37699 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37700 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_MASK 0x00003C00L |
37701 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_OVERRIDE_MASK 0x00004000L |
37702 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00018000L |
37703 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00020000L |
37704 | #define CGTS_SA1_WGP12_CU1_TATD_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37705 | //CGTS_SA1_WGP12_CU1_TCP_CTRL_REG |
37706 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF__SHIFT 0x0 |
37707 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x4 |
37708 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x5 |
37709 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x7 |
37710 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x8 |
37711 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI__SHIFT 0xa |
37712 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_OVERRIDE__SHIFT 0xe |
37713 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0xf |
37714 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0x11 |
37715 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0x12 |
37716 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_MASK 0x0000000FL |
37717 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00000010L |
37718 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x00000060L |
37719 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x00000080L |
37720 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x00000100L |
37721 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_MASK 0x00003C00L |
37722 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_OVERRIDE_MASK 0x00004000L |
37723 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00018000L |
37724 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00020000L |
37725 | #define CGTS_SA1_WGP12_CU1_TCP_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00040000L |
37726 | //CGTT_SPI_PS_CLK_CTRL |
37727 | #define CGTT_SPI_PS_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
37728 | #define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
37729 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 |
37730 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 |
37731 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 |
37732 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 |
37733 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
37734 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
37735 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
37736 | #define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 |
37737 | #define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 |
37738 | #define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a |
37739 | #define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b |
37740 | #define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c |
37741 | #define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d |
37742 | #define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e |
37743 | #define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
37744 | #define CGTT_SPI_PS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
37745 | #define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
37746 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L |
37747 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L |
37748 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L |
37749 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L |
37750 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
37751 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
37752 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
37753 | #define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L |
37754 | #define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L |
37755 | #define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L |
37756 | #define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L |
37757 | #define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L |
37758 | #define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L |
37759 | #define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L |
37760 | #define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
37761 | //CGTT_SPIS_CLK_CTRL |
37762 | #define CGTT_SPIS_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
37763 | #define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
37764 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 |
37765 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 |
37766 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 |
37767 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 |
37768 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
37769 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
37770 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
37771 | #define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 |
37772 | #define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 |
37773 | #define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a |
37774 | #define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b |
37775 | #define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c |
37776 | #define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d |
37777 | #define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e |
37778 | #define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
37779 | #define CGTT_SPIS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
37780 | #define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
37781 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L |
37782 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L |
37783 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L |
37784 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L |
37785 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
37786 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
37787 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
37788 | #define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L |
37789 | #define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L |
37790 | #define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L |
37791 | #define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L |
37792 | #define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L |
37793 | #define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L |
37794 | #define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L |
37795 | #define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
37796 | //CGTT_SPI_CLK_CTRL |
37797 | #define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
37798 | #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
37799 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 |
37800 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 |
37801 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 |
37802 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 |
37803 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
37804 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
37805 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
37806 | #define CGTT_SPI_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 |
37807 | #define CGTT_SPI_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 |
37808 | #define CGTT_SPI_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a |
37809 | #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b |
37810 | #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c |
37811 | #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d |
37812 | #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e |
37813 | #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
37814 | #define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
37815 | #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
37816 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L |
37817 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L |
37818 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L |
37819 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L |
37820 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
37821 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
37822 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
37823 | #define CGTT_SPI_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L |
37824 | #define CGTT_SPI_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L |
37825 | #define CGTT_SPI_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L |
37826 | #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L |
37827 | #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L |
37828 | #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L |
37829 | #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L |
37830 | #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
37831 | //CGTT_PC_CLK_CTRL |
37832 | #define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
37833 | #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
37834 | #define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE__SHIFT 0x11 |
37835 | #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 |
37836 | #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 |
37837 | #define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19 |
37838 | #define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a |
37839 | #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b |
37840 | #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c |
37841 | #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d |
37842 | #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e |
37843 | #define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
37844 | #define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
37845 | #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
37846 | #define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE_MASK 0x00020000L |
37847 | #define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L |
37848 | #define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L |
37849 | #define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L |
37850 | #define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L |
37851 | #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L |
37852 | #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L |
37853 | #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L |
37854 | #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L |
37855 | #define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
37856 | //CGTT_BCI_CLK_CTRL |
37857 | #define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
37858 | #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
37859 | #define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc |
37860 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
37861 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
37862 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
37863 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
37864 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
37865 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
37866 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
37867 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
37868 | #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 |
37869 | #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 |
37870 | #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a |
37871 | #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b |
37872 | #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c |
37873 | #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d |
37874 | #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e |
37875 | #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
37876 | #define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
37877 | #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
37878 | #define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L |
37879 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
37880 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
37881 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
37882 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
37883 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
37884 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
37885 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
37886 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
37887 | #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L |
37888 | #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L |
37889 | #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L |
37890 | #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L |
37891 | #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L |
37892 | #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L |
37893 | #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L |
37894 | #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
37895 | //CGTT_VGT_CLK_CTRL |
37896 | #define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
37897 | #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
37898 | #define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf |
37899 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
37900 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
37901 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
37902 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
37903 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
37904 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
37905 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
37906 | #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT 0x18 |
37907 | #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19 |
37908 | #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a |
37909 | #define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b |
37910 | #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c |
37911 | #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d |
37912 | #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e |
37913 | #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
37914 | #define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
37915 | #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
37916 | #define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L |
37917 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
37918 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
37919 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
37920 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
37921 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
37922 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
37923 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
37924 | #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK 0x01000000L |
37925 | #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L |
37926 | #define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L |
37927 | #define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L |
37928 | #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L |
37929 | #define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L |
37930 | #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L |
37931 | #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
37932 | //CGTT_IA_CLK_CTRL |
37933 | #define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
37934 | #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
37935 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
37936 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
37937 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
37938 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
37939 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
37940 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
37941 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
37942 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
37943 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
37944 | #define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 |
37945 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
37946 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
37947 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
37948 | #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e |
37949 | #define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
37950 | #define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
37951 | #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
37952 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
37953 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
37954 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
37955 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
37956 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
37957 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
37958 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
37959 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
37960 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
37961 | #define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L |
37962 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
37963 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
37964 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
37965 | #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L |
37966 | #define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
37967 | //CGTT_WD_CLK_CTRL |
37968 | #define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
37969 | #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
37970 | #define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf |
37971 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
37972 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
37973 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
37974 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
37975 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
37976 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
37977 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
37978 | #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19 |
37979 | #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a |
37980 | #define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b |
37981 | #define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c |
37982 | #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d |
37983 | #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e |
37984 | #define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
37985 | #define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
37986 | #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
37987 | #define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L |
37988 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
37989 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
37990 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
37991 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
37992 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
37993 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
37994 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
37995 | #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L |
37996 | #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L |
37997 | #define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L |
37998 | #define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L |
37999 | #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L |
38000 | #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L |
38001 | #define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
38002 | //CGTT_GS_NGG_CLK_CTRL |
38003 | #define CGTT_GS_NGG_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
38004 | #define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38005 | #define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE__SHIFT 0xf |
38006 | #define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 |
38007 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38008 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38009 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38010 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38011 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38012 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38013 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38014 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
38015 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
38016 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
38017 | #define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b |
38018 | #define CGTT_GS_NGG_CLK_CTRL__GS1_OVERRIDE__SHIFT 0x1c |
38019 | #define CGTT_GS_NGG_CLK_CTRL__GS0_OVERRIDE__SHIFT 0x1d |
38020 | #define CGTT_GS_NGG_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e |
38021 | #define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
38022 | #define CGTT_GS_NGG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38023 | #define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38024 | #define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L |
38025 | #define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L |
38026 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38027 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38028 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38029 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38030 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38031 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38032 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38033 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
38034 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
38035 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
38036 | #define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L |
38037 | #define CGTT_GS_NGG_CLK_CTRL__GS1_OVERRIDE_MASK 0x10000000L |
38038 | #define CGTT_GS_NGG_CLK_CTRL__GS0_OVERRIDE_MASK 0x20000000L |
38039 | #define CGTT_GS_NGG_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L |
38040 | #define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
38041 | //CGTT_PA_CLK_CTRL |
38042 | #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
38043 | #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38044 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38045 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38046 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38047 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38048 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38049 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38050 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38051 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
38052 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
38053 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
38054 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
38055 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
38056 | #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d |
38057 | #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e |
38058 | #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f |
38059 | #define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38060 | #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38061 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38062 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38063 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38064 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38065 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38066 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38067 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38068 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
38069 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
38070 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
38071 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
38072 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
38073 | #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L |
38074 | #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L |
38075 | #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L |
38076 | //CGTT_SC_CLK_CTRL0 |
38077 | #define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0 |
38078 | #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 |
38079 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10 |
38080 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11 |
38081 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12 |
38082 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13 |
38083 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
38084 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
38085 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
38086 | #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17 |
38087 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18 |
38088 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19 |
38089 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a |
38090 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b |
38091 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c |
38092 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d |
38093 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e |
38094 | #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f |
38095 | #define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL |
38096 | #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L |
38097 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L |
38098 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L |
38099 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L |
38100 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L |
38101 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
38102 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
38103 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
38104 | #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L |
38105 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L |
38106 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L |
38107 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L |
38108 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L |
38109 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L |
38110 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L |
38111 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L |
38112 | #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L |
38113 | //CGTT_SC_CLK_CTRL1 |
38114 | #define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0 |
38115 | #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 |
38116 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0__SHIFT 0x10 |
38117 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11 |
38118 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12 |
38119 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13 |
38120 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14 |
38121 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15 |
38122 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16 |
38123 | #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE__SHIFT 0x17 |
38124 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0__SHIFT 0x18 |
38125 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19 |
38126 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a |
38127 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b |
38128 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c |
38129 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d |
38130 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e |
38131 | #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE__SHIFT 0x1f |
38132 | #define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL |
38133 | #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L |
38134 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0_MASK 0x00010000L |
38135 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L |
38136 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L |
38137 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L |
38138 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L |
38139 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L |
38140 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L |
38141 | #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE_MASK 0x00800000L |
38142 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0_MASK 0x01000000L |
38143 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L |
38144 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L |
38145 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L |
38146 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L |
38147 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L |
38148 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L |
38149 | #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE_MASK 0x80000000L |
38150 | //CGTT_SC_CLK_CTRL2 |
38151 | #define CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT 0x0 |
38152 | #define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 |
38153 | #define CGTT_SC_CLK_CTRL2__DBR_CLK_OVERRIDE__SHIFT 0x1a |
38154 | #define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT 0x1b |
38155 | #define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT 0x1c |
38156 | #define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT 0x1d |
38157 | #define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT 0x1e |
38158 | #define CGTT_SC_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL |
38159 | #define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L |
38160 | #define CGTT_SC_CLK_CTRL2__DBR_CLK_OVERRIDE_MASK 0x04000000L |
38161 | #define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK 0x08000000L |
38162 | #define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK 0x10000000L |
38163 | #define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK 0x20000000L |
38164 | #define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK 0x40000000L |
38165 | //CGTT_SQ_CLK_CTRL |
38166 | #define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
38167 | #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38168 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38169 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38170 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38171 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38172 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38173 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38174 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38175 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38176 | #define CGTT_SQ_CLK_CTRL__WCLK2DCLK_OVERRIDE__SHIFT 0x1b |
38177 | #define CGTT_SQ_CLK_CTRL__WCLK_OVERRIDE__SHIFT 0x1c |
38178 | #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d |
38179 | #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e |
38180 | #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
38181 | #define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38182 | #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38183 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38184 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38185 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38186 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38187 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38188 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38189 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38190 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38191 | #define CGTT_SQ_CLK_CTRL__WCLK2DCLK_OVERRIDE_MASK 0x08000000L |
38192 | #define CGTT_SQ_CLK_CTRL__WCLK_OVERRIDE_MASK 0x10000000L |
38193 | #define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L |
38194 | #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L |
38195 | #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
38196 | //CGTT_SQG_CLK_CTRL |
38197 | #define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
38198 | #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38199 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38200 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38201 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38202 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38203 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38204 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38205 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38206 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38207 | #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c |
38208 | #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d |
38209 | #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e |
38210 | #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
38211 | #define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38212 | #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38213 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38214 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38215 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38216 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38217 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38218 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38219 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38220 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38221 | #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L |
38222 | #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L |
38223 | #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L |
38224 | #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
38225 | //SQ_ALU_CLK_CTRL |
38226 | #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 |
38227 | #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 |
38228 | #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL |
38229 | #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L |
38230 | //SQ_TEX_CLK_CTRL |
38231 | #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 |
38232 | #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 |
38233 | #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL |
38234 | #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L |
38235 | //SQ_LDS_CLK_CTRL |
38236 | #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 |
38237 | #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 |
38238 | #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL |
38239 | #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L |
38240 | //CGTT_SX_CLK_CTRL0 |
38241 | #define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 |
38242 | #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 |
38243 | #define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc |
38244 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38245 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38246 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38247 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38248 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38249 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38250 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38251 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38252 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 |
38253 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 |
38254 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a |
38255 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b |
38256 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c |
38257 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d |
38258 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e |
38259 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f |
38260 | #define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL |
38261 | #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L |
38262 | #define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L |
38263 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38264 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38265 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38266 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38267 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38268 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38269 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38270 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38271 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L |
38272 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L |
38273 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L |
38274 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L |
38275 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L |
38276 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L |
38277 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L |
38278 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L |
38279 | //CGTT_SX_CLK_CTRL1 |
38280 | #define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 |
38281 | #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 |
38282 | #define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc |
38283 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38284 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38285 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38286 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38287 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38288 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38289 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38290 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38291 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 |
38292 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a |
38293 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b |
38294 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c |
38295 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d |
38296 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e |
38297 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f |
38298 | #define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL |
38299 | #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L |
38300 | #define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L |
38301 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38302 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38303 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38304 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38305 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38306 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38307 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38308 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38309 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L |
38310 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L |
38311 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L |
38312 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L |
38313 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L |
38314 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L |
38315 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L |
38316 | //CGTT_SX_CLK_CTRL2 |
38317 | #define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 |
38318 | #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 |
38319 | #define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd |
38320 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38321 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38322 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38323 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38324 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38325 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38326 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38327 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38328 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 |
38329 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a |
38330 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b |
38331 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c |
38332 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d |
38333 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e |
38334 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f |
38335 | #define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL |
38336 | #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L |
38337 | #define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L |
38338 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38339 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38340 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38341 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38342 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38343 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38344 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38345 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38346 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L |
38347 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L |
38348 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L |
38349 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L |
38350 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L |
38351 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L |
38352 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L |
38353 | //CGTT_SX_CLK_CTRL3 |
38354 | #define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 |
38355 | #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 |
38356 | #define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd |
38357 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38358 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38359 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38360 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38361 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38362 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38363 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38364 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38365 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 |
38366 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a |
38367 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b |
38368 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c |
38369 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d |
38370 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e |
38371 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f |
38372 | #define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL |
38373 | #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L |
38374 | #define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L |
38375 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38376 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38377 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38378 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38379 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38380 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38381 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38382 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38383 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L |
38384 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L |
38385 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L |
38386 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L |
38387 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L |
38388 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L |
38389 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L |
38390 | //CGTT_SX_CLK_CTRL4 |
38391 | #define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 |
38392 | #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 |
38393 | #define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc |
38394 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38395 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38396 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38397 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38398 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38399 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38400 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38401 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38402 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 |
38403 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a |
38404 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b |
38405 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c |
38406 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d |
38407 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e |
38408 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f |
38409 | #define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL |
38410 | #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L |
38411 | #define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L |
38412 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38413 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38414 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38415 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38416 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38417 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38418 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38419 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38420 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L |
38421 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L |
38422 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L |
38423 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L |
38424 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L |
38425 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L |
38426 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L |
38427 | //TD_CGTT_CTRL |
38428 | #define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 |
38429 | #define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38430 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38431 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38432 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38433 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38434 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38435 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38436 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38437 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38438 | #define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
38439 | #define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
38440 | #define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
38441 | #define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
38442 | #define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
38443 | #define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
38444 | #define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
38445 | #define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
38446 | #define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL |
38447 | #define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38448 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38449 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38450 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38451 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38452 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38453 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38454 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38455 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38456 | #define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
38457 | #define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
38458 | #define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
38459 | #define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
38460 | #define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
38461 | #define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
38462 | #define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
38463 | #define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
38464 | //TA_CGTT_CTRL |
38465 | #define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 |
38466 | #define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38467 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38468 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38469 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38470 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38471 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38472 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38473 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38474 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38475 | #define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
38476 | #define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
38477 | #define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
38478 | #define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
38479 | #define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
38480 | #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
38481 | #define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
38482 | #define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
38483 | #define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL |
38484 | #define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38485 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38486 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38487 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38488 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38489 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38490 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38491 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38492 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38493 | #define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
38494 | #define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
38495 | #define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
38496 | #define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
38497 | #define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
38498 | #define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
38499 | #define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
38500 | #define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
38501 | //CGTT_TCPI_CLK_CTRL |
38502 | #define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
38503 | #define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38504 | #define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0xc |
38505 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38506 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38507 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38508 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38509 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38510 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38511 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38512 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38513 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
38514 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
38515 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
38516 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
38517 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
38518 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
38519 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
38520 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
38521 | #define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38522 | #define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38523 | #define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x0000F000L |
38524 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38525 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38526 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38527 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38528 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38529 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38530 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38531 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38532 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
38533 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
38534 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
38535 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
38536 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
38537 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
38538 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
38539 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
38540 | //CGTT_TCI_CLK_CTRL |
38541 | #define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
38542 | #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38543 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38544 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38545 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38546 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38547 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38548 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38549 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38550 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38551 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
38552 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
38553 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
38554 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
38555 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
38556 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
38557 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
38558 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
38559 | #define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38560 | #define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38561 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38562 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38563 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38564 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38565 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38566 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38567 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38568 | #define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38569 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
38570 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
38571 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
38572 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
38573 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
38574 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
38575 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
38576 | #define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
38577 | //CGTT_GDS_CLK_CTRL |
38578 | #define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
38579 | #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38580 | #define CGTT_GDS_CLK_CTRL__UNUSED__SHIFT 0xc |
38581 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38582 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38583 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38584 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38585 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38586 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38587 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38588 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38589 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
38590 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
38591 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
38592 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
38593 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
38594 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
38595 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
38596 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
38597 | #define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38598 | #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38599 | #define CGTT_GDS_CLK_CTRL__UNUSED_MASK 0x0000F000L |
38600 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38601 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38602 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38603 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38604 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38605 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38606 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38607 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38608 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
38609 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
38610 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
38611 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
38612 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
38613 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
38614 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
38615 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
38616 | //DB_CGTT_CLK_CTRL_0 |
38617 | #define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 |
38618 | #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 |
38619 | #define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc |
38620 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38621 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38622 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38623 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38624 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38625 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38626 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38627 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38628 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 |
38629 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 |
38630 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a |
38631 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b |
38632 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c |
38633 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d |
38634 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e |
38635 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f |
38636 | #define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL |
38637 | #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L |
38638 | #define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L |
38639 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38640 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38641 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38642 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38643 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38644 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38645 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38646 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38647 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L |
38648 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L |
38649 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L |
38650 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L |
38651 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L |
38652 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L |
38653 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L |
38654 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L |
38655 | //CB_CGTT_SCLK_CTRL |
38656 | #define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 |
38657 | #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38658 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38659 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38660 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38661 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38662 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38663 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38664 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38665 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38666 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
38667 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
38668 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
38669 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
38670 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
38671 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
38672 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
38673 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
38674 | #define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38675 | #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38676 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38677 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38678 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38679 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38680 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38681 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38682 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38683 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38684 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
38685 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
38686 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
38687 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
38688 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
38689 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
38690 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
38691 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
38692 | //GL2C_CGTT_SCLK_CTRL |
38693 | #define GL2C_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 |
38694 | #define GL2C_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38695 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38696 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38697 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38698 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38699 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38700 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38701 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38702 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38703 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
38704 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
38705 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
38706 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
38707 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
38708 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
38709 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
38710 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
38711 | #define GL2C_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38712 | #define GL2C_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38713 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38714 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38715 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38716 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38717 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38718 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38719 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38720 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38721 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
38722 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
38723 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
38724 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
38725 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
38726 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
38727 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
38728 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
38729 | //GL2A_CGTT_SCLK_CTRL |
38730 | #define GL2A_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 |
38731 | #define GL2A_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38732 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38733 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38734 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38735 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38736 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38737 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38738 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38739 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38740 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
38741 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
38742 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
38743 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
38744 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
38745 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
38746 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
38747 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
38748 | #define GL2A_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38749 | #define GL2A_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38750 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38751 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38752 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38753 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38754 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38755 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38756 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38757 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38758 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
38759 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
38760 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
38761 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
38762 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
38763 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
38764 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
38765 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
38766 | //GL2A_CGTT_SCLK_CTRL_1 |
38767 | #define GL2A_CGTT_SCLK_CTRL_1__ON_DELAY__SHIFT 0x0 |
38768 | #define GL2A_CGTT_SCLK_CTRL_1__OFF_HYSTERESIS__SHIFT 0x4 |
38769 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38770 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38771 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38772 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38773 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38774 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38775 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38776 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38777 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE7__SHIFT 0x18 |
38778 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE6__SHIFT 0x19 |
38779 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE5__SHIFT 0x1a |
38780 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE4__SHIFT 0x1b |
38781 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE3__SHIFT 0x1c |
38782 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE2__SHIFT 0x1d |
38783 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE1__SHIFT 0x1e |
38784 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE0__SHIFT 0x1f |
38785 | #define GL2A_CGTT_SCLK_CTRL_1__ON_DELAY_MASK 0x0000000FL |
38786 | #define GL2A_CGTT_SCLK_CTRL_1__OFF_HYSTERESIS_MASK 0x00000FF0L |
38787 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38788 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38789 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38790 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38791 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38792 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38793 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38794 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38795 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE7_MASK 0x01000000L |
38796 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE6_MASK 0x02000000L |
38797 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE5_MASK 0x04000000L |
38798 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE4_MASK 0x08000000L |
38799 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE3_MASK 0x10000000L |
38800 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE2_MASK 0x20000000L |
38801 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE1_MASK 0x40000000L |
38802 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE0_MASK 0x80000000L |
38803 | //CGTT_CP_CLK_CTRL |
38804 | #define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
38805 | #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38806 | #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
38807 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38808 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38809 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38810 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38811 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38812 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38813 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38814 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38815 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d |
38816 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
38817 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
38818 | #define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38819 | #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38820 | #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
38821 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38822 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38823 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38824 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38825 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38826 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38827 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38828 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38829 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L |
38830 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
38831 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
38832 | //CGTT_CPF_CLK_CTRL |
38833 | #define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
38834 | #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38835 | #define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
38836 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38837 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38838 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38839 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38840 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38841 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38842 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38843 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38844 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1a |
38845 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT__SHIFT 0x1b |
38846 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP__SHIFT 0x1c |
38847 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX__SHIFT 0x1d |
38848 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
38849 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
38850 | #define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38851 | #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38852 | #define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
38853 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38854 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38855 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38856 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38857 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38858 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38859 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38860 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38861 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x04000000L |
38862 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT_MASK 0x08000000L |
38863 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP_MASK 0x10000000L |
38864 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX_MASK 0x20000000L |
38865 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
38866 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
38867 | //CGTT_CPC_CLK_CTRL |
38868 | #define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
38869 | #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38870 | #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
38871 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38872 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38873 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38874 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38875 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38876 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38877 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38878 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38879 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d |
38880 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
38881 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
38882 | #define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38883 | #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38884 | #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
38885 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38886 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38887 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38888 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38889 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38890 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38891 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38892 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38893 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L |
38894 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
38895 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
38896 | //CGTT_RLC_CLK_CTRL |
38897 | #define CGTT_RLC_CLK_CTRL__RESERVED__SHIFT 0x0 |
38898 | #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38899 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38900 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38901 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38902 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38903 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38904 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38905 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38906 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38907 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
38908 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
38909 | #define CGTT_RLC_CLK_CTRL__RESERVED_MASK 0x0000000FL |
38910 | #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38911 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38912 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38913 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38914 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38915 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38916 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38917 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38918 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38919 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
38920 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
38921 | //RLC_GFX_RM_CNTL |
38922 | #define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0 |
38923 | #define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1 |
38924 | #define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L |
38925 | #define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL |
38926 | //RMI_CGTT_SCLK_CTRL |
38927 | #define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 |
38928 | #define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38929 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38930 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38931 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38932 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38933 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38934 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38935 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38936 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38937 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
38938 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
38939 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
38940 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
38941 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
38942 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
38943 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
38944 | #define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38945 | #define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38946 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38947 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38948 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38949 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38950 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38951 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38952 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38953 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38954 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
38955 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
38956 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
38957 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
38958 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
38959 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
38960 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
38961 | //CGTT_TCPF_CLK_CTRL |
38962 | #define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
38963 | #define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38964 | #define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0xc |
38965 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
38966 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
38967 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
38968 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
38969 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
38970 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
38971 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
38972 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
38973 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
38974 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
38975 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
38976 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
38977 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
38978 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
38979 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
38980 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
38981 | #define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38982 | #define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38983 | #define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x0000F000L |
38984 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
38985 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
38986 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
38987 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
38988 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
38989 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
38990 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
38991 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
38992 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
38993 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
38994 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
38995 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
38996 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
38997 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
38998 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
38999 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
39000 | //GCR_CGTT_SCLK_CTRL |
39001 | #define GCR_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 |
39002 | #define GCR_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
39003 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
39004 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
39005 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
39006 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
39007 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
39008 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
39009 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
39010 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
39011 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
39012 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
39013 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
39014 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
39015 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
39016 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
39017 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
39018 | #define GCR_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL |
39019 | #define GCR_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
39020 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
39021 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
39022 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
39023 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
39024 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
39025 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
39026 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
39027 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
39028 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
39029 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
39030 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
39031 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
39032 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
39033 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
39034 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
39035 | //UTCL1_CGTT_CLK_CTRL |
39036 | #define UTCL1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
39037 | #define UTCL1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
39038 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
39039 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
39040 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
39041 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
39042 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
39043 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
39044 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
39045 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
39046 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
39047 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
39048 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
39049 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
39050 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
39051 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
39052 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
39053 | #define UTCL1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
39054 | #define UTCL1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
39055 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
39056 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
39057 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
39058 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
39059 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
39060 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
39061 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
39062 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
39063 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
39064 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
39065 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
39066 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
39067 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
39068 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
39069 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
39070 | //GCEA_CGTT_CLK_CTRL |
39071 | #define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
39072 | #define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
39073 | #define GCEA_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc |
39074 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 |
39075 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 |
39076 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 |
39077 | #define GCEA_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 |
39078 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c |
39079 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d |
39080 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e |
39081 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f |
39082 | #define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
39083 | #define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
39084 | #define GCEA_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L |
39085 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L |
39086 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L |
39087 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L |
39088 | #define GCEA_CGTT_CLK_CTRL__SPARE1_MASK 0x0F800000L |
39089 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L |
39090 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L |
39091 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L |
39092 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L |
39093 | //SE_CAC_CGTT_CLK_CTRL |
39094 | #define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
39095 | #define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
39096 | #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
39097 | #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
39098 | #define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
39099 | #define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
39100 | #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
39101 | #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
39102 | //GC_CAC_CGTT_CLK_CTRL |
39103 | #define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
39104 | #define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
39105 | #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
39106 | #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
39107 | #define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
39108 | #define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
39109 | #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
39110 | #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
39111 | //GRBM_CGTT_CLK_CNTL |
39112 | #define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0 |
39113 | #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4 |
39114 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
39115 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
39116 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
39117 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
39118 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
39119 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
39120 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
39121 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
39122 | #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
39123 | #define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL |
39124 | #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L |
39125 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
39126 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
39127 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
39128 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
39129 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
39130 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
39131 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
39132 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
39133 | #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
39134 | //CGTT_GL1C_CLK_CTRL |
39135 | #define CGTT_GL1C_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
39136 | #define CGTT_GL1C_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
39137 | #define CGTT_GL1C_CLK_CTRL__RESERVED__SHIFT 0xc |
39138 | #define CGTT_GL1C_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
39139 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
39140 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
39141 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
39142 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
39143 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
39144 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
39145 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
39146 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
39147 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
39148 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
39149 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
39150 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
39151 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
39152 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
39153 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
39154 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
39155 | #define CGTT_GL1C_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
39156 | #define CGTT_GL1C_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
39157 | #define CGTT_GL1C_CLK_CTRL__RESERVED_MASK 0x00007000L |
39158 | #define CGTT_GL1C_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
39159 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
39160 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
39161 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
39162 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
39163 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
39164 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
39165 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
39166 | #define CGTT_GL1C_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
39167 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
39168 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
39169 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
39170 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
39171 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
39172 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
39173 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
39174 | #define CGTT_GL1C_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
39175 | //CGTT_CHC_CLK_CTRL |
39176 | #define CGTT_CHC_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
39177 | #define CGTT_CHC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
39178 | #define CGTT_CHC_CLK_CTRL__RESERVED__SHIFT 0xc |
39179 | #define CGTT_CHC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
39180 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
39181 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
39182 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
39183 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
39184 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
39185 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
39186 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
39187 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
39188 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
39189 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
39190 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
39191 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
39192 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
39193 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
39194 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
39195 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
39196 | #define CGTT_CHC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
39197 | #define CGTT_CHC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
39198 | #define CGTT_CHC_CLK_CTRL__RESERVED_MASK 0x00007000L |
39199 | #define CGTT_CHC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
39200 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
39201 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
39202 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
39203 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
39204 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
39205 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
39206 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
39207 | #define CGTT_CHC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
39208 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
39209 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
39210 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
39211 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
39212 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
39213 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
39214 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
39215 | #define CGTT_CHC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
39216 | //CGTT_CHCG_CLK_CTRL |
39217 | #define CGTT_CHCG_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
39218 | #define CGTT_CHCG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
39219 | #define CGTT_CHCG_CLK_CTRL__RESERVED__SHIFT 0xc |
39220 | #define CGTT_CHCG_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
39221 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
39222 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
39223 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
39224 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
39225 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
39226 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
39227 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
39228 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
39229 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
39230 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
39231 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
39232 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
39233 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
39234 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
39235 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
39236 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
39237 | #define CGTT_CHCG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
39238 | #define CGTT_CHCG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
39239 | #define CGTT_CHCG_CLK_CTRL__RESERVED_MASK 0x00007000L |
39240 | #define CGTT_CHCG_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
39241 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
39242 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
39243 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
39244 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
39245 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
39246 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
39247 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
39248 | #define CGTT_CHCG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
39249 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
39250 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
39251 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
39252 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
39253 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
39254 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
39255 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
39256 | #define CGTT_CHCG_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
39257 | //CGTT_GL1A_CLK_CTRL |
39258 | #define CGTT_GL1A_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
39259 | #define CGTT_GL1A_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
39260 | #define CGTT_GL1A_CLK_CTRL__RESERVED__SHIFT 0xc |
39261 | #define CGTT_GL1A_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
39262 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
39263 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
39264 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
39265 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
39266 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
39267 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
39268 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
39269 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
39270 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
39271 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
39272 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
39273 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
39274 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
39275 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
39276 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
39277 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
39278 | #define CGTT_GL1A_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
39279 | #define CGTT_GL1A_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
39280 | #define CGTT_GL1A_CLK_CTRL__RESERVED_MASK 0x00007000L |
39281 | #define CGTT_GL1A_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
39282 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
39283 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
39284 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
39285 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
39286 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
39287 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
39288 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
39289 | #define CGTT_GL1A_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
39290 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
39291 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
39292 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
39293 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
39294 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
39295 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
39296 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
39297 | #define CGTT_GL1A_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
39298 | //CGTT_CHA_CLK_CTRL |
39299 | #define CGTT_CHA_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
39300 | #define CGTT_CHA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
39301 | #define CGTT_CHA_CLK_CTRL__RESERVED__SHIFT 0xc |
39302 | #define CGTT_CHA_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
39303 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
39304 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
39305 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
39306 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
39307 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
39308 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
39309 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
39310 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
39311 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
39312 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
39313 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
39314 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
39315 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
39316 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
39317 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
39318 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
39319 | #define CGTT_CHA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
39320 | #define CGTT_CHA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
39321 | #define CGTT_CHA_CLK_CTRL__RESERVED_MASK 0x00007000L |
39322 | #define CGTT_CHA_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
39323 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
39324 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
39325 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
39326 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
39327 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
39328 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
39329 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
39330 | #define CGTT_CHA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
39331 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
39332 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
39333 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
39334 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
39335 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
39336 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
39337 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
39338 | #define CGTT_CHA_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
39339 | //GUS_CGTT_CLK_CTRL |
39340 | #define GUS_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
39341 | #define GUS_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
39342 | #define GUS_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc |
39343 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_DRAM__SHIFT 0x13 |
39344 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 |
39345 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 |
39346 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 |
39347 | #define GUS_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 |
39348 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_DRAM__SHIFT 0x1b |
39349 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c |
39350 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d |
39351 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e |
39352 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f |
39353 | #define GUS_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
39354 | #define GUS_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
39355 | #define GUS_CGTT_CLK_CTRL__SPARE0_MASK 0x0007F000L |
39356 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_DRAM_MASK 0x00080000L |
39357 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L |
39358 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L |
39359 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L |
39360 | #define GUS_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L |
39361 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_DRAM_MASK 0x08000000L |
39362 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L |
39363 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L |
39364 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L |
39365 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L |
39366 | //CGTT_PH_CLK_CTRL0 |
39367 | #define CGTT_PH_CLK_CTRL0__ON_DELAY__SHIFT 0x0 |
39368 | #define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 |
39369 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
39370 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
39371 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
39372 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
39373 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
39374 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
39375 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
39376 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 |
39377 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 |
39378 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a |
39379 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b |
39380 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c |
39381 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d |
39382 | #define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE__SHIFT 0x1e |
39383 | #define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f |
39384 | #define CGTT_PH_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL |
39385 | #define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L |
39386 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
39387 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
39388 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
39389 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
39390 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
39391 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
39392 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
39393 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L |
39394 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L |
39395 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L |
39396 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L |
39397 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L |
39398 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L |
39399 | #define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE_MASK 0x40000000L |
39400 | #define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L |
39401 | //CGTT_PH_CLK_CTRL1 |
39402 | #define CGTT_PH_CLK_CTRL1__ON_DELAY__SHIFT 0x0 |
39403 | #define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 |
39404 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18 |
39405 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 |
39406 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a |
39407 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b |
39408 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c |
39409 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d |
39410 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e |
39411 | #define CGTT_PH_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL |
39412 | #define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L |
39413 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x01000000L |
39414 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L |
39415 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L |
39416 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L |
39417 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L |
39418 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L |
39419 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L |
39420 | //CGTT_PH_CLK_CTRL2 |
39421 | #define CGTT_PH_CLK_CTRL2__ON_DELAY__SHIFT 0x0 |
39422 | #define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 |
39423 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18 |
39424 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 |
39425 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a |
39426 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b |
39427 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c |
39428 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d |
39429 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e |
39430 | #define CGTT_PH_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL |
39431 | #define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L |
39432 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x01000000L |
39433 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L |
39434 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L |
39435 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L |
39436 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L |
39437 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L |
39438 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L |
39439 | //CGTT_PH_CLK_CTRL3 |
39440 | #define CGTT_PH_CLK_CTRL3__ON_DELAY__SHIFT 0x0 |
39441 | #define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 |
39442 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18 |
39443 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 |
39444 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a |
39445 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b |
39446 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c |
39447 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d |
39448 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e |
39449 | #define CGTT_PH_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL |
39450 | #define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L |
39451 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L |
39452 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L |
39453 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L |
39454 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L |
39455 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L |
39456 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L |
39457 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L |
39458 | |
39459 | |
39460 | // addressBlock: gc_hypdec |
39461 | //CP_PFP_UCODE_ADDR |
39462 | #define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
39463 | #define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
39464 | //CP_PFP_UCODE_DATA |
39465 | #define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
39466 | #define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
39467 | //CP_ME_RAM_RADDR |
39468 | #define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 |
39469 | #define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000FFFFFL |
39470 | //CP_ME_RAM_WADDR |
39471 | #define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 |
39472 | #define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x001FFFFFL |
39473 | //CP_ME_RAM_DATA |
39474 | #define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 |
39475 | #define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL |
39476 | //CP_CE_UCODE_ADDR |
39477 | #define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
39478 | #define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
39479 | //CP_CE_UCODE_DATA |
39480 | #define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
39481 | #define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
39482 | //CP_MEC_ME1_UCODE_ADDR |
39483 | #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
39484 | #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
39485 | //CP_MEC_ME1_UCODE_DATA |
39486 | #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
39487 | #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
39488 | //CP_MEC_ME2_UCODE_ADDR |
39489 | #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
39490 | #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
39491 | //CP_MEC_ME2_UCODE_DATA |
39492 | #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
39493 | #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
39494 | //CP_PFP_IC_BASE_LO |
39495 | #define CP_PFP_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
39496 | #define CP_PFP_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
39497 | //CP_PFP_IC_BASE_HI |
39498 | #define CP_PFP_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
39499 | #define CP_PFP_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
39500 | //CP_PFP_IC_BASE_CNTL |
39501 | #define CP_PFP_IC_BASE_CNTL__VMID__SHIFT 0x0 |
39502 | #define CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4 |
39503 | #define CP_PFP_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
39504 | #define CP_PFP_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
39505 | #define CP_PFP_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
39506 | #define CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L |
39507 | #define CP_PFP_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
39508 | #define CP_PFP_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
39509 | //CP_PFP_IC_OP_CNTL |
39510 | #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
39511 | #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 |
39512 | #define CP_PFP_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
39513 | #define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
39514 | #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
39515 | #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L |
39516 | #define CP_PFP_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
39517 | #define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
39518 | //CP_ME_IC_BASE_LO |
39519 | #define CP_ME_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
39520 | #define CP_ME_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
39521 | //CP_ME_IC_BASE_HI |
39522 | #define CP_ME_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
39523 | #define CP_ME_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
39524 | //CP_ME_IC_BASE_CNTL |
39525 | #define CP_ME_IC_BASE_CNTL__VMID__SHIFT 0x0 |
39526 | #define CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4 |
39527 | #define CP_ME_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
39528 | #define CP_ME_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
39529 | #define CP_ME_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
39530 | #define CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L |
39531 | #define CP_ME_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
39532 | #define CP_ME_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
39533 | //CP_ME_IC_OP_CNTL |
39534 | #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
39535 | #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 |
39536 | #define CP_ME_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
39537 | #define CP_ME_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
39538 | #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
39539 | #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L |
39540 | #define CP_ME_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
39541 | #define CP_ME_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
39542 | //CP_CE_IC_BASE_LO |
39543 | #define CP_CE_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
39544 | #define CP_CE_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
39545 | //CP_CE_IC_BASE_HI |
39546 | #define CP_CE_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
39547 | #define CP_CE_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
39548 | //CP_CE_IC_BASE_CNTL |
39549 | #define CP_CE_IC_BASE_CNTL__VMID__SHIFT 0x0 |
39550 | #define CP_CE_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4 |
39551 | #define CP_CE_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
39552 | #define CP_CE_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
39553 | #define CP_CE_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
39554 | #define CP_CE_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L |
39555 | #define CP_CE_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
39556 | #define CP_CE_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
39557 | //CP_CE_IC_OP_CNTL |
39558 | #define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
39559 | #define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 |
39560 | #define CP_CE_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
39561 | #define CP_CE_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
39562 | #define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
39563 | #define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L |
39564 | #define CP_CE_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
39565 | #define CP_CE_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
39566 | //CP_CPC_IC_BASE_LO |
39567 | #define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
39568 | #define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
39569 | //CP_CPC_IC_BASE_HI |
39570 | #define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
39571 | #define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
39572 | //CP_CPC_IC_BASE_CNTL |
39573 | #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 |
39574 | #define CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4 |
39575 | #define CP_CPC_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
39576 | #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
39577 | #define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
39578 | #define CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L |
39579 | #define CP_CPC_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
39580 | #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
39581 | //CP_CPC_IC_OP_CNTL |
39582 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
39583 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 |
39584 | #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
39585 | #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
39586 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
39587 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L |
39588 | #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
39589 | #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
39590 | //CP_MES_IC_BASE_LO |
39591 | #define CP_MES_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
39592 | #define CP_MES_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
39593 | //CP_MES_MIBASE_LO |
39594 | #define CP_MES_MIBASE_LO__IC_BASE_LO__SHIFT 0xc |
39595 | #define CP_MES_MIBASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
39596 | //CP_MES_IC_BASE_HI |
39597 | #define CP_MES_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
39598 | #define CP_MES_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
39599 | //CP_MES_MIBASE_HI |
39600 | #define CP_MES_MIBASE_HI__IC_BASE_HI__SHIFT 0x0 |
39601 | #define CP_MES_MIBASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
39602 | //CP_MES_IC_BASE_CNTL |
39603 | #define CP_MES_IC_BASE_CNTL__VMID__SHIFT 0x0 |
39604 | #define CP_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
39605 | #define CP_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
39606 | #define CP_MES_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
39607 | #define CP_MES_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
39608 | #define CP_MES_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
39609 | //CP_MES_IC_OP_CNTL |
39610 | #define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
39611 | #define CP_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
39612 | #define CP_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
39613 | #define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
39614 | #define CP_MES_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
39615 | #define CP_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
39616 | //CP_MES_DC_BASE_LO |
39617 | #define CP_MES_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 |
39618 | #define CP_MES_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L |
39619 | //CP_MES_MDBASE_LO |
39620 | #define CP_MES_MDBASE_LO__BASE_LO__SHIFT 0x10 |
39621 | #define CP_MES_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L |
39622 | //CP_MES_DC_BASE_HI |
39623 | #define CP_MES_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 |
39624 | #define CP_MES_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL |
39625 | //CP_MES_MDBASE_HI |
39626 | #define CP_MES_MDBASE_HI__BASE_HI__SHIFT 0x0 |
39627 | #define CP_MES_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL |
39628 | //CP_MES_LOCAL_BASE0_LO |
39629 | #define CP_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 |
39630 | #define CP_MES_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L |
39631 | //CP_MES_LOCAL_BASE0_HI |
39632 | #define CP_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 |
39633 | #define CP_MES_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL |
39634 | //CP_MES_LOCAL_MASK0_LO |
39635 | #define CP_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 |
39636 | #define CP_MES_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L |
39637 | //CP_MES_LOCAL_MASK0_HI |
39638 | #define CP_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 |
39639 | #define CP_MES_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL |
39640 | //CP_MES_LOCAL_APERTURE |
39641 | #define CP_MES_LOCAL_APERTURE__APERTURE__SHIFT 0x0 |
39642 | #define CP_MES_LOCAL_APERTURE__APERTURE_MASK 0x00000003L |
39643 | //CP_MES_MIBOUND_LO |
39644 | #define CP_MES_MIBOUND_LO__BOUND_LO__SHIFT 0x0 |
39645 | #define CP_MES_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL |
39646 | //CP_MES_MIBOUND_HI |
39647 | #define CP_MES_MIBOUND_HI__BOUND_HI__SHIFT 0x0 |
39648 | #define CP_MES_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL |
39649 | //CP_MES_MDBOUND_LO |
39650 | #define CP_MES_MDBOUND_LO__BOUND_LO__SHIFT 0x0 |
39651 | #define CP_MES_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL |
39652 | //CP_MES_MDBOUND_HI |
39653 | #define CP_MES_MDBOUND_HI__BOUND_HI__SHIFT 0x0 |
39654 | #define CP_MES_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL |
39655 | //GFX_PIPE_PRIORITY |
39656 | #define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0 |
39657 | #define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x00000001L |
39658 | //GRBM_GFX_INDEX_SR_SELECT |
39659 | #define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0 |
39660 | #define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L |
39661 | //GRBM_GFX_INDEX_SR_DATA |
39662 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0 |
39663 | #define GRBM_GFX_INDEX_SR_DATA__SA_INDEX__SHIFT 0x8 |
39664 | #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10 |
39665 | #define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES__SHIFT 0x1d |
39666 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e |
39667 | #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f |
39668 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL |
39669 | #define GRBM_GFX_INDEX_SR_DATA__SA_INDEX_MASK 0x0000FF00L |
39670 | #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L |
39671 | #define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES_MASK 0x20000000L |
39672 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L |
39673 | #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L |
39674 | //GRBM_GFX_CNTL_SR_SELECT |
39675 | #define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0 |
39676 | #define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L |
39677 | //GRBM_GFX_CNTL_SR_DATA |
39678 | #define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0 |
39679 | #define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2 |
39680 | #define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4 |
39681 | #define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8 |
39682 | #define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L |
39683 | #define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL |
39684 | #define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L |
39685 | #define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L |
39686 | //GRBM_CAM_INDEX |
39687 | #define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 |
39688 | #define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x0000000FL |
39689 | //GRBM_HYP_CAM_INDEX |
39690 | #define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 |
39691 | #define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x0000000FL |
39692 | //GRBM_CAM_DATA |
39693 | #define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 |
39694 | #define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 |
39695 | #define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL |
39696 | #define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L |
39697 | //GRBM_HYP_CAM_DATA |
39698 | #define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 |
39699 | #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 |
39700 | #define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL |
39701 | #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L |
39702 | //GRBM_CAM_DATA_UPPER |
39703 | #define GRBM_CAM_DATA_UPPER__CAM_ADDR__SHIFT 0x0 |
39704 | #define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT 0x10 |
39705 | #define GRBM_CAM_DATA_UPPER__CAM_ADDR_MASK 0x00000003L |
39706 | #define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR_MASK 0x00030000L |
39707 | //GRBM_HYP_CAM_DATA_UPPER |
39708 | #define GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR__SHIFT 0x0 |
39709 | #define GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT 0x10 |
39710 | #define GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR_MASK 0x00000003L |
39711 | #define GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR_MASK 0x00030000L |
39712 | //GC_IH_COOKIE_0_PTR |
39713 | #define GC_IH_COOKIE_0_PTR__ADDR__SHIFT 0x0 |
39714 | #define GC_IH_COOKIE_0_PTR__ADDR_MASK 0x000FFFFFL |
39715 | //RLC_GPU_IOV_VF_ENABLE |
39716 | #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 |
39717 | #define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 |
39718 | #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 |
39719 | #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L |
39720 | #define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL |
39721 | #define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L |
39722 | //RLC_GPU_IOV_CFG_REG6 |
39723 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 |
39724 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 |
39725 | #define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 |
39726 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa |
39727 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL |
39728 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L |
39729 | #define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L |
39730 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L |
39731 | //RLC_GPU_IOV_CFG_REG8 |
39732 | #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 |
39733 | #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
39734 | //RLC_RLCV_TIMER_INT_0 |
39735 | #define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0 |
39736 | #define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL |
39737 | //RLC_RLCV_TIMER_CTRL |
39738 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 |
39739 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 |
39740 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x2 |
39741 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x3 |
39742 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x4 |
39743 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x5 |
39744 | #define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x6 |
39745 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L |
39746 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L |
39747 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000004L |
39748 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000008L |
39749 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00000010L |
39750 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00000020L |
39751 | #define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFC0L |
39752 | //RLC_RLCV_TIMER_STAT |
39753 | #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 |
39754 | #define RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 |
39755 | #define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x2 |
39756 | #define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 |
39757 | #define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 |
39758 | #define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xa |
39759 | #define RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0xb |
39760 | #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L |
39761 | #define RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L |
39762 | #define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0x000000FCL |
39763 | #define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L |
39764 | #define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L |
39765 | #define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00000400L |
39766 | #define RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00000800L |
39767 | //RLC_GPU_IOV_VF_DOORBELL_STATUS |
39768 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0 |
39769 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f |
39770 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x7FFFFFFFL |
39771 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L |
39772 | //RLC_GPU_IOV_VF_DOORBELL_STATUS_SET |
39773 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0 |
39774 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f |
39775 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x7FFFFFFFL |
39776 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L |
39777 | //RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR |
39778 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0 |
39779 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f |
39780 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x7FFFFFFFL |
39781 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L |
39782 | //RLC_GPU_IOV_VF_MASK |
39783 | #define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0 |
39784 | #define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x7FFFFFFFL |
39785 | //RLC_HYP_SEMAPHORE_0 |
39786 | #define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 |
39787 | #define RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT 0x5 |
39788 | #define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL |
39789 | #define RLC_HYP_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L |
39790 | //RLC_HYP_SEMAPHORE_1 |
39791 | #define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 |
39792 | #define RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT 0x5 |
39793 | #define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL |
39794 | #define RLC_HYP_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L |
39795 | //RLC_BUSY_CLK_CNTL |
39796 | #define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY__SHIFT 0x0 |
39797 | #define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY_MASK 0x0000003FL |
39798 | //RLC_CLK_CNTL |
39799 | #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0 |
39800 | #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x2 |
39801 | #define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT 0x4 |
39802 | #define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT 0x5 |
39803 | #define RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT 0x6 |
39804 | #define RLC_CLK_CNTL__RESERVED_7__SHIFT 0x7 |
39805 | #define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT 0x8 |
39806 | #define RLC_CLK_CNTL__RESERVED_9__SHIFT 0x9 |
39807 | #define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT 0xa |
39808 | #define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT 0xc |
39809 | #define RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL__SHIFT 0xd |
39810 | #define RLC_CLK_CNTL__RESERVED_15__SHIFT 0xf |
39811 | #define RLC_CLK_CNTL__RESERVED__SHIFT 0x12 |
39812 | #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000003L |
39813 | #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x0000000CL |
39814 | #define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK 0x00000010L |
39815 | #define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK 0x00000020L |
39816 | #define RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK 0x00000040L |
39817 | #define RLC_CLK_CNTL__RESERVED_7_MASK 0x00000080L |
39818 | #define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK 0x00000100L |
39819 | #define RLC_CLK_CNTL__RESERVED_9_MASK 0x00000200L |
39820 | #define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK 0x00000C00L |
39821 | #define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK 0x00001000L |
39822 | #define RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL_MASK 0x00002000L |
39823 | #define RLC_CLK_CNTL__RESERVED_15_MASK 0x00008000L |
39824 | #define RLC_CLK_CNTL__RESERVED_MASK 0xFFFC0000L |
39825 | //RLC_PACE_TIMER_STAT |
39826 | #define RLC_PACE_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 |
39827 | #define RLC_PACE_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 |
39828 | #define RLC_PACE_TIMER_STAT__RESERVED__SHIFT 0x2 |
39829 | #define RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 |
39830 | #define RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 |
39831 | #define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xa |
39832 | #define RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0xb |
39833 | #define RLC_PACE_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L |
39834 | #define RLC_PACE_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L |
39835 | #define RLC_PACE_TIMER_STAT__RESERVED_MASK 0x000000FCL |
39836 | #define RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L |
39837 | #define RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L |
39838 | #define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00000400L |
39839 | #define RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00000800L |
39840 | //RLC_GPU_IOV_SCH_BLOCK |
39841 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0 |
39842 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4 |
39843 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8 |
39844 | #define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10 |
39845 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL |
39846 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L |
39847 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L |
39848 | #define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L |
39849 | //RLC_GPU_IOV_CFG_REG1 |
39850 | #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 |
39851 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 |
39852 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 |
39853 | #define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 |
39854 | #define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 |
39855 | #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 |
39856 | #define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 |
39857 | #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL |
39858 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L |
39859 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L |
39860 | #define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L |
39861 | #define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L |
39862 | #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L |
39863 | #define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L |
39864 | //RLC_GPU_IOV_CFG_REG2 |
39865 | #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 |
39866 | #define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4 |
39867 | #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL |
39868 | #define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L |
39869 | //RLC_GPU_IOV_VM_BUSY_STATUS |
39870 | #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
39871 | #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
39872 | //RLC_GPU_IOV_SCH_0 |
39873 | #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0 |
39874 | #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL |
39875 | //RLC_GPU_IOV_ACTIVE_FCN_ID |
39876 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 |
39877 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x5 |
39878 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f |
39879 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000001FL |
39880 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFE0L |
39881 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L |
39882 | //RLC_GPU_IOV_SCH_3 |
39883 | #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0 |
39884 | #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL |
39885 | //RLC_GPU_IOV_SCH_1 |
39886 | #define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 |
39887 | #define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL |
39888 | //RLC_GPU_IOV_SCH_2 |
39889 | #define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 |
39890 | #define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL |
39891 | //RLC_PACE_INT_FORCE |
39892 | #define RLC_PACE_INT_FORCE__FORCE__SHIFT 0x0 |
39893 | #define RLC_PACE_INT_FORCE__FORCE_MASK 0xFFFFFFFFL |
39894 | //RLC_GPU_IOV_INT_STAT |
39895 | #define RLC_GPU_IOV_INT_STAT__STATUS__SHIFT 0x0 |
39896 | #define RLC_GPU_IOV_INT_STAT__STATUS_MASK 0xFFFFFFFFL |
39897 | //RLC_RLCV_TIMER_INT_1 |
39898 | #define RLC_RLCV_TIMER_INT_1__TIMER__SHIFT 0x0 |
39899 | #define RLC_RLCV_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL |
39900 | //RLC_IH_COOKIE |
39901 | #define RLC_IH_COOKIE__DATA__SHIFT 0x0 |
39902 | #define RLC_IH_COOKIE__DATA_MASK 0xFFFFFFFFL |
39903 | //RLC_IH_COOKIE_CNTL |
39904 | #define RLC_IH_COOKIE_CNTL__CREDIT__SHIFT 0x0 |
39905 | #define RLC_IH_COOKIE_CNTL__RESET_COUNTER__SHIFT 0x2 |
39906 | #define RLC_IH_COOKIE_CNTL__CREDIT_MASK 0x00000003L |
39907 | #define RLC_IH_COOKIE_CNTL__RESET_COUNTER_MASK 0x00000004L |
39908 | //RLC_HYP_RLCG_UCODE_CHKSUM |
39909 | #define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 |
39910 | #define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL |
39911 | //RLC_HYP_RLCP_UCODE_CHKSUM |
39912 | #define RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 |
39913 | #define RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL |
39914 | //RLC_HYP_RLCV_UCODE_CHKSUM |
39915 | #define RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 |
39916 | #define RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL |
39917 | //RLC_GPU_IOV_F32_CNTL |
39918 | #define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0 |
39919 | #define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L |
39920 | //RLC_GPU_IOV_F32_RESET |
39921 | #define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0 |
39922 | #define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L |
39923 | //RLC_GPU_IOV_SDMA0_STATUS |
39924 | #define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0 |
39925 | #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_7_1__SHIFT 0x1 |
39926 | #define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8 |
39927 | #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_11_9__SHIFT 0x9 |
39928 | #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc |
39929 | #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_31_13__SHIFT 0xd |
39930 | #define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L |
39931 | #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_7_1_MASK 0x000000FEL |
39932 | #define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L |
39933 | #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_11_9_MASK 0x00000E00L |
39934 | #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L |
39935 | #define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_31_13_MASK 0xFFFFE000L |
39936 | //RLC_GPU_IOV_SDMA1_STATUS |
39937 | #define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0 |
39938 | #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_7_1__SHIFT 0x1 |
39939 | #define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8 |
39940 | #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_11_9__SHIFT 0x9 |
39941 | #define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc |
39942 | #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_31_13__SHIFT 0xd |
39943 | #define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L |
39944 | #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_7_1_MASK 0x000000FEL |
39945 | #define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L |
39946 | #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_11_9_MASK 0x00000E00L |
39947 | #define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L |
39948 | #define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_31_13_MASK 0xFFFFE000L |
39949 | //RLC_GPU_IOV_SMU_RESPONSE |
39950 | #define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0 |
39951 | #define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL |
39952 | //RLC_GPU_IOV_VIRT_RESET_REQ |
39953 | #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 |
39954 | #define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10 |
39955 | #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f |
39956 | #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL |
39957 | #define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L |
39958 | #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L |
39959 | //RLC_GPU_IOV_RLC_RESPONSE |
39960 | #define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 |
39961 | #define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL |
39962 | //RLC_GPU_IOV_INT_DISABLE |
39963 | #define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0 |
39964 | #define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL |
39965 | //RLC_GPU_IOV_INT_FORCE |
39966 | #define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0 |
39967 | #define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL |
39968 | //RLC_GPU_IOV_SDMA0_BUSY_STATUS |
39969 | #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
39970 | #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
39971 | //RLC_GPU_IOV_SDMA1_BUSY_STATUS |
39972 | #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
39973 | #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
39974 | //RLC_HYP_SEMAPHORE_2 |
39975 | #define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 |
39976 | #define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5 |
39977 | #define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL |
39978 | #define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L |
39979 | //RLC_HYP_SEMAPHORE_3 |
39980 | #define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 |
39981 | #define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5 |
39982 | #define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL |
39983 | #define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L |
39984 | //RLC_HYP_RESET_VECTOR |
39985 | #define RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT__SHIFT 0x0 |
39986 | #define RLC_HYP_RESET_VECTOR__VDDGFX_EXIT__SHIFT 0x1 |
39987 | #define RLC_HYP_RESET_VECTOR__WARM_RESET_EXIT__SHIFT 0x2 |
39988 | #define RLC_HYP_RESET_VECTOR__VF_FLR_EXIT__SHIFT 0x3 |
39989 | #define RLC_HYP_RESET_VECTOR__RESERVED_4__SHIFT 0x4 |
39990 | #define RLC_HYP_RESET_VECTOR__RESERVED_5__SHIFT 0x5 |
39991 | #define RLC_HYP_RESET_VECTOR__RESERVED_6__SHIFT 0x6 |
39992 | #define RLC_HYP_RESET_VECTOR__RESERVED_7__SHIFT 0x7 |
39993 | #define RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK 0x00000001L |
39994 | #define RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK 0x00000002L |
39995 | #define RLC_HYP_RESET_VECTOR__WARM_RESET_EXIT_MASK 0x00000004L |
39996 | #define RLC_HYP_RESET_VECTOR__VF_FLR_EXIT_MASK 0x00000008L |
39997 | #define RLC_HYP_RESET_VECTOR__RESERVED_4_MASK 0x00000010L |
39998 | #define RLC_HYP_RESET_VECTOR__RESERVED_5_MASK 0x00000020L |
39999 | #define RLC_HYP_RESET_VECTOR__RESERVED_6_MASK 0x00000040L |
40000 | #define RLC_HYP_RESET_VECTOR__RESERVED_7_MASK 0x00000080L |
40001 | //RLC_HYP_BOOTLOAD_SIZE |
40002 | #define RLC_HYP_BOOTLOAD_SIZE__SIZE__SHIFT 0x0 |
40003 | #define RLC_HYP_BOOTLOAD_SIZE__SIZE_MASK 0x03FFFFFFL |
40004 | //RLC_HYP_BOOTLOAD_ADDR_LO |
40005 | #define RLC_HYP_BOOTLOAD_ADDR_LO__ADDR_LO__SHIFT 0x0 |
40006 | #define RLC_HYP_BOOTLOAD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL |
40007 | //RLC_HYP_BOOTLOAD_ADDR_HI |
40008 | #define RLC_HYP_BOOTLOAD_ADDR_HI__ADDR_HI__SHIFT 0x0 |
40009 | #define RLC_HYP_BOOTLOAD_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL |
40010 | //RLC_GPM_IRAM_ADDR |
40011 | #define RLC_GPM_IRAM_ADDR__ADDR__SHIFT 0x0 |
40012 | #define RLC_GPM_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL |
40013 | //RLC_GPM_IRAM_DATA |
40014 | #define RLC_GPM_IRAM_DATA__DATA__SHIFT 0x0 |
40015 | #define RLC_GPM_IRAM_DATA__DATA_MASK 0xFFFFFFFFL |
40016 | //RLC_GPM_UCODE_ADDR |
40017 | #define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
40018 | #define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe |
40019 | #define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL |
40020 | #define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L |
40021 | //RLC_GPM_UCODE_DATA |
40022 | #define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
40023 | #define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
40024 | //RLC_PACE_UCODE_ADDR |
40025 | #define RLC_PACE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
40026 | #define RLC_PACE_UCODE_ADDR__RESERVED__SHIFT 0xc |
40027 | #define RLC_PACE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL |
40028 | #define RLC_PACE_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L |
40029 | //RLC_PACE_UCODE_DATA |
40030 | #define RLC_PACE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
40031 | #define RLC_PACE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
40032 | //RLC_GPU_IOV_UCODE_ADDR |
40033 | #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
40034 | #define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc |
40035 | #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL |
40036 | #define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L |
40037 | //RLC_GPU_IOV_UCODE_DATA |
40038 | #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
40039 | #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
40040 | //RLC_GPU_IOV_SCRATCH_ADDR |
40041 | #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0 |
40042 | #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0xFFFFFFFFL |
40043 | //RLC_GPU_IOV_SCRATCH_DATA |
40044 | #define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0 |
40045 | #define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL |
40046 | //RLC_RLCV_IRAM_ADDR |
40047 | #define RLC_RLCV_IRAM_ADDR__ADDR__SHIFT 0x0 |
40048 | #define RLC_RLCV_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL |
40049 | //RLC_RLCV_IRAM_DATA |
40050 | #define RLC_RLCV_IRAM_DATA__DATA__SHIFT 0x0 |
40051 | #define RLC_RLCV_IRAM_DATA__DATA_MASK 0xFFFFFFFFL |
40052 | //RLC_RLCP_IRAM_ADDR |
40053 | #define RLC_RLCP_IRAM_ADDR__ADDR__SHIFT 0x0 |
40054 | #define RLC_RLCP_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL |
40055 | //RLC_RLCP_IRAM_DATA |
40056 | #define RLC_RLCP_IRAM_DATA__DATA__SHIFT 0x0 |
40057 | #define RLC_RLCP_IRAM_DATA__DATA_MASK 0xFFFFFFFFL |
40058 | //RLC_SRM_DRAM_ADDR |
40059 | #define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 |
40060 | #define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc |
40061 | #define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL |
40062 | #define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L |
40063 | //RLC_SRM_DRAM_DATA |
40064 | #define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 |
40065 | #define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL |
40066 | //RLC_SRM_ARAM_ADDR |
40067 | #define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 |
40068 | #define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc |
40069 | #define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL |
40070 | #define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L |
40071 | //RLC_SRM_ARAM_DATA |
40072 | #define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 |
40073 | #define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL |
40074 | //RLC_GPM_SCRATCH_ADDR |
40075 | #define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 |
40076 | #define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0xFFFFFFFFL |
40077 | //RLC_GPM_SCRATCH_DATA |
40078 | #define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 |
40079 | #define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL |
40080 | //RLC_GTS_OFFSET_LSB |
40081 | #define RLC_GTS_OFFSET_LSB__DATA__SHIFT 0x0 |
40082 | #define RLC_GTS_OFFSET_LSB__DATA_MASK 0xFFFFFFFFL |
40083 | //RLC_GTS_OFFSET_MSB |
40084 | #define RLC_GTS_OFFSET_MSB__DATA__SHIFT 0x0 |
40085 | #define RLC_GTS_OFFSET_MSB__DATA_MASK 0xFFFFFFFFL |
40086 | |
40087 | |
40088 | // addressBlock: gc_sdma0_sdma0hypdec |
40089 | //SDMA0_UCODE_ADDR |
40090 | #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 |
40091 | #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00003FFFL |
40092 | //SDMA0_UCODE_DATA |
40093 | #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 |
40094 | #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL |
40095 | //SDMA0_VM_CTX_LO |
40096 | #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 |
40097 | #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL |
40098 | //SDMA0_VM_CTX_HI |
40099 | #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 |
40100 | #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL |
40101 | //SDMA0_ACTIVE_FCN_ID |
40102 | #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
40103 | #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x5 |
40104 | #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f |
40105 | #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL |
40106 | #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFE0L |
40107 | #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L |
40108 | //SDMA0_VM_CTX_CNTL |
40109 | #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 |
40110 | #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 |
40111 | #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L |
40112 | #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L |
40113 | //SDMA0_VIRT_RESET_REQ |
40114 | #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 |
40115 | #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f |
40116 | #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL |
40117 | #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L |
40118 | //SDMA0_VF_ENABLE |
40119 | #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 |
40120 | #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L |
40121 | //SDMA0_CONTEXT_REG_TYPE0 |
40122 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 |
40123 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 |
40124 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 |
40125 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 |
40126 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 |
40127 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 |
40128 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 |
40129 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 |
40130 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 |
40131 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 |
40132 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa |
40133 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb |
40134 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc |
40135 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd |
40136 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe |
40137 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf |
40138 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 |
40139 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 |
40140 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 |
40141 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 |
40142 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L |
40143 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L |
40144 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L |
40145 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L |
40146 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L |
40147 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L |
40148 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L |
40149 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L |
40150 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L |
40151 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L |
40152 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L |
40153 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L |
40154 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L |
40155 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L |
40156 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L |
40157 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L |
40158 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L |
40159 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L |
40160 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L |
40161 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L |
40162 | //SDMA0_CONTEXT_REG_TYPE1 |
40163 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 |
40164 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa |
40165 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb |
40166 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc |
40167 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd |
40168 | #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe |
40169 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf |
40170 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 |
40171 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 |
40172 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 |
40173 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 |
40174 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 |
40175 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 |
40176 | #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x18 |
40177 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L |
40178 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L |
40179 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L |
40180 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L |
40181 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L |
40182 | #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L |
40183 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L |
40184 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L |
40185 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L |
40186 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L |
40187 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L |
40188 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L |
40189 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L |
40190 | #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFF000000L |
40191 | //SDMA0_CONTEXT_REG_TYPE2 |
40192 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 |
40193 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 |
40194 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 |
40195 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 |
40196 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 |
40197 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 |
40198 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 |
40199 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 |
40200 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 |
40201 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 |
40202 | #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa |
40203 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L |
40204 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L |
40205 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L |
40206 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L |
40207 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L |
40208 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L |
40209 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L |
40210 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L |
40211 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L |
40212 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L |
40213 | #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L |
40214 | //SDMA0_CONTEXT_REG_TYPE3 |
40215 | #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 |
40216 | #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL |
40217 | //SDMA0_VM_CNTL |
40218 | #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 |
40219 | #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL |
40220 | |
40221 | |
40222 | // addressBlock: gc_sdma1_sdma1hypdec |
40223 | //SDMA1_UCODE_ADDR |
40224 | #define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 |
40225 | #define SDMA1_UCODE_ADDR__VALUE_MASK 0x00003FFFL |
40226 | //SDMA1_UCODE_DATA |
40227 | #define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 |
40228 | #define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL |
40229 | //SDMA1_VM_CTX_LO |
40230 | #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 |
40231 | #define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL |
40232 | //SDMA1_VM_CTX_HI |
40233 | #define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 |
40234 | #define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL |
40235 | //SDMA1_ACTIVE_FCN_ID |
40236 | #define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
40237 | #define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x5 |
40238 | #define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f |
40239 | #define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL |
40240 | #define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFE0L |
40241 | #define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L |
40242 | //SDMA1_VM_CTX_CNTL |
40243 | #define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 |
40244 | #define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 |
40245 | #define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L |
40246 | #define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L |
40247 | //SDMA1_VIRT_RESET_REQ |
40248 | #define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 |
40249 | #define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f |
40250 | #define SDMA1_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL |
40251 | #define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L |
40252 | //SDMA1_VF_ENABLE |
40253 | #define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 |
40254 | #define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L |
40255 | //SDMA1_CONTEXT_REG_TYPE0 |
40256 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 |
40257 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 |
40258 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 |
40259 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 |
40260 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 |
40261 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 |
40262 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 |
40263 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 |
40264 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 |
40265 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 |
40266 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa |
40267 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb |
40268 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc |
40269 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd |
40270 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe |
40271 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf |
40272 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 |
40273 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 |
40274 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 |
40275 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 |
40276 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L |
40277 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L |
40278 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L |
40279 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L |
40280 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L |
40281 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L |
40282 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L |
40283 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L |
40284 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L |
40285 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L |
40286 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L |
40287 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L |
40288 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L |
40289 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L |
40290 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L |
40291 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L |
40292 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L |
40293 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L |
40294 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L |
40295 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L |
40296 | //SDMA1_CONTEXT_REG_TYPE1 |
40297 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 |
40298 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa |
40299 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb |
40300 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc |
40301 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd |
40302 | #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe |
40303 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf |
40304 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 |
40305 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 |
40306 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 |
40307 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 |
40308 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 |
40309 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 |
40310 | #define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x18 |
40311 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L |
40312 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L |
40313 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L |
40314 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L |
40315 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L |
40316 | #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L |
40317 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L |
40318 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L |
40319 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L |
40320 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L |
40321 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L |
40322 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L |
40323 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L |
40324 | #define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFF000000L |
40325 | //SDMA1_CONTEXT_REG_TYPE2 |
40326 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 |
40327 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 |
40328 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 |
40329 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 |
40330 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 |
40331 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 |
40332 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 |
40333 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 |
40334 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 |
40335 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 |
40336 | #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa |
40337 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L |
40338 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L |
40339 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L |
40340 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L |
40341 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L |
40342 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L |
40343 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L |
40344 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L |
40345 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L |
40346 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L |
40347 | #define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L |
40348 | //SDMA1_CONTEXT_REG_TYPE3 |
40349 | #define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 |
40350 | #define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL |
40351 | //SDMA1_VM_CNTL |
40352 | #define SDMA1_VM_CNTL__CMD__SHIFT 0x0 |
40353 | #define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL |
40354 | |
40355 | |
40356 | // addressBlock: gc_gcvmsharedhvdec |
40357 | //GCMC_VM_FB_SIZE_OFFSET_VF0 |
40358 | #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 |
40359 | #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 |
40360 | #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL |
40361 | #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L |
40362 | //GCMC_VM_FB_SIZE_OFFSET_VF1 |
40363 | #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 |
40364 | #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 |
40365 | #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL |
40366 | #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L |
40367 | //GCMC_VM_FB_SIZE_OFFSET_VF2 |
40368 | #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 |
40369 | #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 |
40370 | #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL |
40371 | #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L |
40372 | //GCMC_VM_FB_SIZE_OFFSET_VF3 |
40373 | #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 |
40374 | #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 |
40375 | #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL |
40376 | #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L |
40377 | //GCMC_VM_FB_SIZE_OFFSET_VF4 |
40378 | #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 |
40379 | #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 |
40380 | #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL |
40381 | #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L |
40382 | //GCMC_VM_FB_SIZE_OFFSET_VF5 |
40383 | #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 |
40384 | #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 |
40385 | #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL |
40386 | #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L |
40387 | //GCMC_VM_FB_SIZE_OFFSET_VF6 |
40388 | #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 |
40389 | #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 |
40390 | #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL |
40391 | #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L |
40392 | //GCMC_VM_FB_SIZE_OFFSET_VF7 |
40393 | #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 |
40394 | #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 |
40395 | #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL |
40396 | #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L |
40397 | //GCMC_VM_FB_SIZE_OFFSET_VF8 |
40398 | #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 |
40399 | #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 |
40400 | #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL |
40401 | #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L |
40402 | //GCMC_VM_FB_SIZE_OFFSET_VF9 |
40403 | #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 |
40404 | #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 |
40405 | #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL |
40406 | #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L |
40407 | //GCMC_VM_FB_SIZE_OFFSET_VF10 |
40408 | #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 |
40409 | #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 |
40410 | #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL |
40411 | #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L |
40412 | //GCMC_VM_FB_SIZE_OFFSET_VF11 |
40413 | #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 |
40414 | #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 |
40415 | #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL |
40416 | #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L |
40417 | //GCMC_VM_FB_SIZE_OFFSET_VF12 |
40418 | #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 |
40419 | #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 |
40420 | #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL |
40421 | #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L |
40422 | //GCMC_VM_FB_SIZE_OFFSET_VF13 |
40423 | #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 |
40424 | #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 |
40425 | #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL |
40426 | #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L |
40427 | //GCMC_VM_FB_SIZE_OFFSET_VF14 |
40428 | #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 |
40429 | #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 |
40430 | #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL |
40431 | #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L |
40432 | //GCMC_VM_FB_SIZE_OFFSET_VF15 |
40433 | #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 |
40434 | #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 |
40435 | #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL |
40436 | #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L |
40437 | //GCMC_VM_FB_SIZE_OFFSET_VF16 |
40438 | #define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE__SHIFT 0x0 |
40439 | #define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET__SHIFT 0x10 |
40440 | #define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE_MASK 0x0000FFFFL |
40441 | #define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET_MASK 0xFFFF0000L |
40442 | //GCMC_VM_FB_SIZE_OFFSET_VF17 |
40443 | #define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE__SHIFT 0x0 |
40444 | #define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET__SHIFT 0x10 |
40445 | #define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE_MASK 0x0000FFFFL |
40446 | #define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET_MASK 0xFFFF0000L |
40447 | //GCMC_VM_FB_SIZE_OFFSET_VF18 |
40448 | #define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE__SHIFT 0x0 |
40449 | #define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET__SHIFT 0x10 |
40450 | #define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE_MASK 0x0000FFFFL |
40451 | #define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET_MASK 0xFFFF0000L |
40452 | //GCMC_VM_FB_SIZE_OFFSET_VF19 |
40453 | #define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE__SHIFT 0x0 |
40454 | #define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET__SHIFT 0x10 |
40455 | #define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE_MASK 0x0000FFFFL |
40456 | #define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET_MASK 0xFFFF0000L |
40457 | //GCMC_VM_FB_SIZE_OFFSET_VF20 |
40458 | #define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE__SHIFT 0x0 |
40459 | #define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET__SHIFT 0x10 |
40460 | #define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE_MASK 0x0000FFFFL |
40461 | #define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET_MASK 0xFFFF0000L |
40462 | //GCMC_VM_FB_SIZE_OFFSET_VF21 |
40463 | #define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE__SHIFT 0x0 |
40464 | #define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET__SHIFT 0x10 |
40465 | #define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE_MASK 0x0000FFFFL |
40466 | #define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET_MASK 0xFFFF0000L |
40467 | //GCMC_VM_FB_SIZE_OFFSET_VF22 |
40468 | #define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE__SHIFT 0x0 |
40469 | #define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET__SHIFT 0x10 |
40470 | #define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE_MASK 0x0000FFFFL |
40471 | #define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET_MASK 0xFFFF0000L |
40472 | //GCMC_VM_FB_SIZE_OFFSET_VF23 |
40473 | #define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE__SHIFT 0x0 |
40474 | #define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET__SHIFT 0x10 |
40475 | #define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE_MASK 0x0000FFFFL |
40476 | #define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET_MASK 0xFFFF0000L |
40477 | //GCMC_VM_FB_SIZE_OFFSET_VF24 |
40478 | #define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE__SHIFT 0x0 |
40479 | #define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET__SHIFT 0x10 |
40480 | #define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE_MASK 0x0000FFFFL |
40481 | #define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET_MASK 0xFFFF0000L |
40482 | //GCMC_VM_FB_SIZE_OFFSET_VF25 |
40483 | #define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE__SHIFT 0x0 |
40484 | #define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET__SHIFT 0x10 |
40485 | #define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE_MASK 0x0000FFFFL |
40486 | #define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET_MASK 0xFFFF0000L |
40487 | //GCMC_VM_FB_SIZE_OFFSET_VF26 |
40488 | #define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE__SHIFT 0x0 |
40489 | #define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET__SHIFT 0x10 |
40490 | #define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE_MASK 0x0000FFFFL |
40491 | #define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET_MASK 0xFFFF0000L |
40492 | //GCMC_VM_FB_SIZE_OFFSET_VF27 |
40493 | #define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE__SHIFT 0x0 |
40494 | #define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET__SHIFT 0x10 |
40495 | #define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE_MASK 0x0000FFFFL |
40496 | #define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET_MASK 0xFFFF0000L |
40497 | //GCMC_VM_FB_SIZE_OFFSET_VF28 |
40498 | #define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE__SHIFT 0x0 |
40499 | #define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET__SHIFT 0x10 |
40500 | #define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE_MASK 0x0000FFFFL |
40501 | #define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET_MASK 0xFFFF0000L |
40502 | //GCMC_VM_FB_SIZE_OFFSET_VF29 |
40503 | #define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE__SHIFT 0x0 |
40504 | #define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET__SHIFT 0x10 |
40505 | #define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE_MASK 0x0000FFFFL |
40506 | #define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET_MASK 0xFFFF0000L |
40507 | //GCMC_VM_FB_SIZE_OFFSET_VF30 |
40508 | #define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE__SHIFT 0x0 |
40509 | #define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET__SHIFT 0x10 |
40510 | #define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE_MASK 0x0000FFFFL |
40511 | #define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET_MASK 0xFFFF0000L |
40512 | //GCMC_VM_FB_SIZE_OFFSET_VF31 |
40513 | #define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE__SHIFT 0x0 |
40514 | #define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET__SHIFT 0x10 |
40515 | #define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE_MASK 0x0000FFFFL |
40516 | #define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET_MASK 0xFFFF0000L |
40517 | //GCVM_IOMMU_MMIO_CNTRL_1 |
40518 | #define GCVM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 |
40519 | #define GCVM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L |
40520 | //GCMC_VM_MARC_BASE_LO_0 |
40521 | #define GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc |
40522 | #define GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L |
40523 | //GCMC_VM_MARC_BASE_LO_1 |
40524 | #define GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc |
40525 | #define GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L |
40526 | //GCMC_VM_MARC_BASE_LO_2 |
40527 | #define GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc |
40528 | #define GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L |
40529 | //GCMC_VM_MARC_BASE_LO_3 |
40530 | #define GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc |
40531 | #define GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L |
40532 | //GCMC_VM_MARC_BASE_HI_0 |
40533 | #define GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 |
40534 | #define GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL |
40535 | //GCMC_VM_MARC_BASE_HI_1 |
40536 | #define GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 |
40537 | #define GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL |
40538 | //GCMC_VM_MARC_BASE_HI_2 |
40539 | #define GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 |
40540 | #define GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL |
40541 | //GCMC_VM_MARC_BASE_HI_3 |
40542 | #define GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 |
40543 | #define GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL |
40544 | //GCMC_VM_MARC_RELOC_LO_0 |
40545 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 |
40546 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 |
40547 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc |
40548 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L |
40549 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L |
40550 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L |
40551 | //GCMC_VM_MARC_RELOC_LO_1 |
40552 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 |
40553 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 |
40554 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc |
40555 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L |
40556 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L |
40557 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L |
40558 | //GCMC_VM_MARC_RELOC_LO_2 |
40559 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 |
40560 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 |
40561 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc |
40562 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L |
40563 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L |
40564 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L |
40565 | //GCMC_VM_MARC_RELOC_LO_3 |
40566 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 |
40567 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 |
40568 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc |
40569 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L |
40570 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L |
40571 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L |
40572 | //GCMC_VM_MARC_RELOC_HI_0 |
40573 | #define GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 |
40574 | #define GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL |
40575 | //GCMC_VM_MARC_RELOC_HI_1 |
40576 | #define GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 |
40577 | #define GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL |
40578 | //GCMC_VM_MARC_RELOC_HI_2 |
40579 | #define GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 |
40580 | #define GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL |
40581 | //GCMC_VM_MARC_RELOC_HI_3 |
40582 | #define GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 |
40583 | #define GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL |
40584 | //GCMC_VM_MARC_LEN_LO_0 |
40585 | #define GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc |
40586 | #define GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L |
40587 | //GCMC_VM_MARC_LEN_LO_1 |
40588 | #define GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc |
40589 | #define GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L |
40590 | //GCMC_VM_MARC_LEN_LO_2 |
40591 | #define GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc |
40592 | #define GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L |
40593 | //GCMC_VM_MARC_LEN_LO_3 |
40594 | #define GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc |
40595 | #define GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L |
40596 | //GCMC_VM_MARC_LEN_HI_0 |
40597 | #define GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 |
40598 | #define GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL |
40599 | //GCMC_VM_MARC_LEN_HI_1 |
40600 | #define GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 |
40601 | #define GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL |
40602 | //GCMC_VM_MARC_LEN_HI_2 |
40603 | #define GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 |
40604 | #define GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL |
40605 | //GCMC_VM_MARC_LEN_HI_3 |
40606 | #define GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 |
40607 | #define GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL |
40608 | //GCVM_IOMMU_CONTROL_REGISTER |
40609 | #define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 |
40610 | #define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L |
40611 | //GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER |
40612 | #define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd |
40613 | #define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L |
40614 | //GCVM_PCIE_ATS_CNTL |
40615 | #define GCVM_PCIE_ATS_CNTL__STU__SHIFT 0x10 |
40616 | #define GCVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f |
40617 | #define GCVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L |
40618 | #define GCVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L |
40619 | //GCVM_PCIE_ATS_CNTL_VF_0 |
40620 | #define GCVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f |
40621 | #define GCVM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L |
40622 | //GCVM_PCIE_ATS_CNTL_VF_1 |
40623 | #define GCVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f |
40624 | #define GCVM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L |
40625 | //GCVM_PCIE_ATS_CNTL_VF_2 |
40626 | #define GCVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f |
40627 | #define GCVM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L |
40628 | //GCVM_PCIE_ATS_CNTL_VF_3 |
40629 | #define GCVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f |
40630 | #define GCVM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L |
40631 | //GCVM_PCIE_ATS_CNTL_VF_4 |
40632 | #define GCVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f |
40633 | #define GCVM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L |
40634 | //GCVM_PCIE_ATS_CNTL_VF_5 |
40635 | #define GCVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f |
40636 | #define GCVM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L |
40637 | //GCVM_PCIE_ATS_CNTL_VF_6 |
40638 | #define GCVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f |
40639 | #define GCVM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L |
40640 | //GCVM_PCIE_ATS_CNTL_VF_7 |
40641 | #define GCVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f |
40642 | #define GCVM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L |
40643 | //GCVM_PCIE_ATS_CNTL_VF_8 |
40644 | #define GCVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f |
40645 | #define GCVM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L |
40646 | //GCVM_PCIE_ATS_CNTL_VF_9 |
40647 | #define GCVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f |
40648 | #define GCVM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L |
40649 | //GCVM_PCIE_ATS_CNTL_VF_10 |
40650 | #define GCVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f |
40651 | #define GCVM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L |
40652 | //GCVM_PCIE_ATS_CNTL_VF_11 |
40653 | #define GCVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f |
40654 | #define GCVM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L |
40655 | //GCVM_PCIE_ATS_CNTL_VF_12 |
40656 | #define GCVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f |
40657 | #define GCVM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L |
40658 | //GCVM_PCIE_ATS_CNTL_VF_13 |
40659 | #define GCVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f |
40660 | #define GCVM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L |
40661 | //GCVM_PCIE_ATS_CNTL_VF_14 |
40662 | #define GCVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f |
40663 | #define GCVM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L |
40664 | //GCVM_PCIE_ATS_CNTL_VF_15 |
40665 | #define GCVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f |
40666 | #define GCVM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L |
40667 | //GCVM_PCIE_ATS_CNTL_VF_16 |
40668 | #define GCVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE__SHIFT 0x1f |
40669 | #define GCVM_PCIE_ATS_CNTL_VF_16__ATC_ENABLE_MASK 0x80000000L |
40670 | //GCVM_PCIE_ATS_CNTL_VF_17 |
40671 | #define GCVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE__SHIFT 0x1f |
40672 | #define GCVM_PCIE_ATS_CNTL_VF_17__ATC_ENABLE_MASK 0x80000000L |
40673 | //GCVM_PCIE_ATS_CNTL_VF_18 |
40674 | #define GCVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE__SHIFT 0x1f |
40675 | #define GCVM_PCIE_ATS_CNTL_VF_18__ATC_ENABLE_MASK 0x80000000L |
40676 | //GCVM_PCIE_ATS_CNTL_VF_19 |
40677 | #define GCVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE__SHIFT 0x1f |
40678 | #define GCVM_PCIE_ATS_CNTL_VF_19__ATC_ENABLE_MASK 0x80000000L |
40679 | //GCVM_PCIE_ATS_CNTL_VF_20 |
40680 | #define GCVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE__SHIFT 0x1f |
40681 | #define GCVM_PCIE_ATS_CNTL_VF_20__ATC_ENABLE_MASK 0x80000000L |
40682 | //GCVM_PCIE_ATS_CNTL_VF_21 |
40683 | #define GCVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE__SHIFT 0x1f |
40684 | #define GCVM_PCIE_ATS_CNTL_VF_21__ATC_ENABLE_MASK 0x80000000L |
40685 | //GCVM_PCIE_ATS_CNTL_VF_22 |
40686 | #define GCVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE__SHIFT 0x1f |
40687 | #define GCVM_PCIE_ATS_CNTL_VF_22__ATC_ENABLE_MASK 0x80000000L |
40688 | //GCVM_PCIE_ATS_CNTL_VF_23 |
40689 | #define GCVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE__SHIFT 0x1f |
40690 | #define GCVM_PCIE_ATS_CNTL_VF_23__ATC_ENABLE_MASK 0x80000000L |
40691 | //GCVM_PCIE_ATS_CNTL_VF_24 |
40692 | #define GCVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE__SHIFT 0x1f |
40693 | #define GCVM_PCIE_ATS_CNTL_VF_24__ATC_ENABLE_MASK 0x80000000L |
40694 | //GCVM_PCIE_ATS_CNTL_VF_25 |
40695 | #define GCVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE__SHIFT 0x1f |
40696 | #define GCVM_PCIE_ATS_CNTL_VF_25__ATC_ENABLE_MASK 0x80000000L |
40697 | //GCVM_PCIE_ATS_CNTL_VF_26 |
40698 | #define GCVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE__SHIFT 0x1f |
40699 | #define GCVM_PCIE_ATS_CNTL_VF_26__ATC_ENABLE_MASK 0x80000000L |
40700 | //GCVM_PCIE_ATS_CNTL_VF_27 |
40701 | #define GCVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE__SHIFT 0x1f |
40702 | #define GCVM_PCIE_ATS_CNTL_VF_27__ATC_ENABLE_MASK 0x80000000L |
40703 | //GCVM_PCIE_ATS_CNTL_VF_28 |
40704 | #define GCVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE__SHIFT 0x1f |
40705 | #define GCVM_PCIE_ATS_CNTL_VF_28__ATC_ENABLE_MASK 0x80000000L |
40706 | //GCVM_PCIE_ATS_CNTL_VF_29 |
40707 | #define GCVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE__SHIFT 0x1f |
40708 | #define GCVM_PCIE_ATS_CNTL_VF_29__ATC_ENABLE_MASK 0x80000000L |
40709 | //GCVM_PCIE_ATS_CNTL_VF_30 |
40710 | #define GCVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE__SHIFT 0x1f |
40711 | #define GCVM_PCIE_ATS_CNTL_VF_30__ATC_ENABLE_MASK 0x80000000L |
40712 | //GCVM_PCIE_ATS_CNTL_VF_31 |
40713 | #define GCVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE__SHIFT 0x1f |
40714 | #define GCVM_PCIE_ATS_CNTL_VF_31__ATC_ENABLE_MASK 0x80000000L |
40715 | //GCUTCL2_CGTT_CLK_CTRL |
40716 | #define GCUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
40717 | #define GCUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
40718 | #define 0xc |
40719 | #define GCUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
40720 | #define GCUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 |
40721 | #define GCUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 |
40722 | #define GCUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
40723 | #define GCUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
40724 | #define 0x00007000L |
40725 | #define GCUTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
40726 | #define GCUTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L |
40727 | #define GCUTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L |
40728 | //GCMC_SHARED_ACTIVE_FCN_ID |
40729 | #define GCMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
40730 | #define GCMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f |
40731 | #define GCMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL |
40732 | #define GCMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L |
40733 | |
40734 | |
40735 | // addressBlock: gccacind |
40736 | //PCC_STALL_PATTERN_CTRL |
40737 | #define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL__SHIFT 0x0 |
40738 | #define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP__SHIFT 0xa |
40739 | #define PCC_STALL_PATTERN_CTRL__PCC_END_STEP__SHIFT 0xf |
40740 | #define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14 |
40741 | #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR__SHIFT 0x18 |
40742 | #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR__SHIFT 0x19 |
40743 | #define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE__SHIFT 0x1a |
40744 | #define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL_MASK 0x000003FFL |
40745 | #define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP_MASK 0x00007C00L |
40746 | #define PCC_STALL_PATTERN_CTRL__PCC_END_STEP_MASK 0x000F8000L |
40747 | #define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L |
40748 | #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR_MASK 0x01000000L |
40749 | #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR_MASK 0x02000000L |
40750 | #define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE_MASK 0x04000000L |
40751 | //PWRBRK_STALL_PATTERN_CTRL |
40752 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT 0x0 |
40753 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT 0xa |
40754 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT 0xf |
40755 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14 |
40756 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK 0x000003FFL |
40757 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK 0x00007C00L |
40758 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK 0x000F8000L |
40759 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L |
40760 | //PCC_STALL_PATTERN_1_2 |
40761 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT 0x0 |
40762 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT 0x10 |
40763 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK 0x00007FFFL |
40764 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK 0x7FFF0000L |
40765 | //PCC_STALL_PATTERN_3_4 |
40766 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT 0x0 |
40767 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT 0x10 |
40768 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK 0x00007FFFL |
40769 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK 0x7FFF0000L |
40770 | //PCC_STALL_PATTERN_5_6 |
40771 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT 0x0 |
40772 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT 0x10 |
40773 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK 0x00007FFFL |
40774 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK 0x7FFF0000L |
40775 | //PCC_STALL_PATTERN_7 |
40776 | #define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT 0x0 |
40777 | #define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK 0x00007FFFL |
40778 | //PWRBRK_STALL_PATTERN_1_2 |
40779 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT 0x0 |
40780 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT 0x10 |
40781 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK 0x00007FFFL |
40782 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK 0x7FFF0000L |
40783 | //PWRBRK_STALL_PATTERN_3_4 |
40784 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT 0x0 |
40785 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT 0x10 |
40786 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK 0x00007FFFL |
40787 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK 0x7FFF0000L |
40788 | //PWRBRK_STALL_PATTERN_5_6 |
40789 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT 0x0 |
40790 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT 0x10 |
40791 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK 0x00007FFFL |
40792 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK 0x7FFF0000L |
40793 | //PWRBRK_STALL_PATTERN_7 |
40794 | #define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT 0x0 |
40795 | #define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK 0x00007FFFL |
40796 | //GC_CAC_ID |
40797 | #define GC_CAC_ID__CAC_BLOCK_ID__SHIFT 0x0 |
40798 | #define GC_CAC_ID__CAC_SIGNAL_ID__SHIFT 0x6 |
40799 | #define GC_CAC_ID__UNUSED_0__SHIFT 0xe |
40800 | #define GC_CAC_ID__CAC_BLOCK_ID_MASK 0x0000003FL |
40801 | #define GC_CAC_ID__CAC_SIGNAL_ID_MASK 0x00003FC0L |
40802 | #define GC_CAC_ID__UNUSED_0_MASK 0xFFFFC000L |
40803 | //GC_CAC_CNTL |
40804 | #define GC_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0 |
40805 | #define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 |
40806 | #define GC_CAC_CNTL__UNUSED_0__SHIFT 0x11 |
40807 | #define GC_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L |
40808 | #define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL |
40809 | #define GC_CAC_CNTL__UNUSED_0_MASK 0xFFFE0000L |
40810 | //GC_CAC_OVR_SEL |
40811 | #define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 |
40812 | #define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL |
40813 | //GC_CAC_OVR_VAL |
40814 | #define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 |
40815 | #define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL |
40816 | //GC_CAC_WEIGHT_BCI_0 |
40817 | #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0 |
40818 | #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10 |
40819 | #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL |
40820 | #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L |
40821 | //GC_CAC_WEIGHT_CB_0 |
40822 | #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0 |
40823 | #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10 |
40824 | #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL |
40825 | #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L |
40826 | //GC_CAC_WEIGHT_CB_1 |
40827 | #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0 |
40828 | #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10 |
40829 | #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL |
40830 | #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L |
40831 | //GC_CAC_WEIGHT_CBR_0 |
40832 | #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0__SHIFT 0x0 |
40833 | #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1__SHIFT 0x10 |
40834 | #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG0_MASK 0x0000FFFFL |
40835 | #define GC_CAC_WEIGHT_CBR_0__WEIGHT_CBR_SIG1_MASK 0xFFFF0000L |
40836 | //GC_CAC_WEIGHT_CBR_1 |
40837 | #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2__SHIFT 0x0 |
40838 | #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3__SHIFT 0x10 |
40839 | #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG2_MASK 0x0000FFFFL |
40840 | #define GC_CAC_WEIGHT_CBR_1__WEIGHT_CBR_SIG3_MASK 0xFFFF0000L |
40841 | //GC_CAC_WEIGHT_CP_0 |
40842 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0 |
40843 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10 |
40844 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL |
40845 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L |
40846 | //GC_CAC_WEIGHT_CP_1 |
40847 | #define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0 |
40848 | #define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT 0x10 |
40849 | #define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL |
40850 | #define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK 0xFFFF0000L |
40851 | //GC_CAC_WEIGHT_DB_0 |
40852 | #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0 |
40853 | #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10 |
40854 | #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL |
40855 | #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L |
40856 | //GC_CAC_WEIGHT_DB_1 |
40857 | #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0 |
40858 | #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10 |
40859 | #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL |
40860 | #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L |
40861 | //GC_CAC_WEIGHT_DBR_0 |
40862 | #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0__SHIFT 0x0 |
40863 | #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1__SHIFT 0x10 |
40864 | #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG0_MASK 0x0000FFFFL |
40865 | #define GC_CAC_WEIGHT_DBR_0__WEIGHT_DBR_SIG1_MASK 0xFFFF0000L |
40866 | //GC_CAC_WEIGHT_DBR_1 |
40867 | #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2__SHIFT 0x0 |
40868 | #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3__SHIFT 0x10 |
40869 | #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG2_MASK 0x0000FFFFL |
40870 | #define GC_CAC_WEIGHT_DBR_1__WEIGHT_DBR_SIG3_MASK 0xFFFF0000L |
40871 | //GC_CAC_WEIGHT_GDS_0 |
40872 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0 |
40873 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10 |
40874 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL |
40875 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L |
40876 | //GC_CAC_WEIGHT_GDS_1 |
40877 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0 |
40878 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10 |
40879 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL |
40880 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L |
40881 | //GC_CAC_WEIGHT_LDS_0 |
40882 | #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0 |
40883 | #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10 |
40884 | #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL |
40885 | #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L |
40886 | //GC_CAC_WEIGHT_LDS_1 |
40887 | #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0 |
40888 | #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10 |
40889 | #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL |
40890 | #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L |
40891 | //GC_CAC_WEIGHT_PA_0 |
40892 | #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0 |
40893 | #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10 |
40894 | #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL |
40895 | #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L |
40896 | //GC_CAC_WEIGHT_PC_0 |
40897 | #define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0 |
40898 | #define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT 0x10 |
40899 | #define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL |
40900 | #define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK 0xFFFF0000L |
40901 | //GC_CAC_WEIGHT_SC_0 |
40902 | #define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0 |
40903 | #define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT 0x10 |
40904 | #define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL |
40905 | #define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK 0xFFFF0000L |
40906 | //GC_CAC_WEIGHT_SPI_0 |
40907 | #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0 |
40908 | #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10 |
40909 | #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL |
40910 | #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L |
40911 | //GC_CAC_WEIGHT_SPI_1 |
40912 | #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0 |
40913 | #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10 |
40914 | #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL |
40915 | #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L |
40916 | //GC_CAC_WEIGHT_SPI_2 |
40917 | #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0 |
40918 | #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10 |
40919 | #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL |
40920 | #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L |
40921 | //GC_CAC_WEIGHT_SQ_0 |
40922 | #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0 |
40923 | #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10 |
40924 | #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL |
40925 | #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L |
40926 | //GC_CAC_WEIGHT_SQ_1 |
40927 | #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0 |
40928 | #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10 |
40929 | #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL |
40930 | #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L |
40931 | //GC_CAC_WEIGHT_SQ_2 |
40932 | #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0 |
40933 | #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10 |
40934 | #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL |
40935 | #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L |
40936 | //GC_CAC_WEIGHT_SX_0 |
40937 | #define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0 |
40938 | #define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT 0x10 |
40939 | #define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL |
40940 | #define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK 0xFFFF0000L |
40941 | //GC_CAC_WEIGHT_SXRB_0 |
40942 | #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0 |
40943 | #define GC_CAC_WEIGHT_SXRB_0__UNUSED_0__SHIFT 0x10 |
40944 | #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL |
40945 | #define GC_CAC_WEIGHT_SXRB_0__UNUSED_0_MASK 0xFFFF0000L |
40946 | //GC_CAC_WEIGHT_TA_0 |
40947 | #define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0 |
40948 | #define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT 0x10 |
40949 | #define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL |
40950 | #define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK 0xFFFF0000L |
40951 | //GC_CAC_WEIGHT_TCP_0 |
40952 | #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0 |
40953 | #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10 |
40954 | #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL |
40955 | #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L |
40956 | //GC_CAC_WEIGHT_TCP_1 |
40957 | #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0 |
40958 | #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10 |
40959 | #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL |
40960 | #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L |
40961 | //GC_CAC_WEIGHT_TCP_2 |
40962 | #define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0 |
40963 | #define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT 0x10 |
40964 | #define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL |
40965 | #define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK 0xFFFF0000L |
40966 | //GC_CAC_WEIGHT_TD_0 |
40967 | #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0 |
40968 | #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10 |
40969 | #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL |
40970 | #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L |
40971 | //GC_CAC_WEIGHT_TD_1 |
40972 | #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0 |
40973 | #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10 |
40974 | #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL |
40975 | #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L |
40976 | //GC_CAC_WEIGHT_TD_2 |
40977 | #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0 |
40978 | #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10 |
40979 | #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL |
40980 | #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L |
40981 | //GC_CAC_WEIGHT_TD_3 |
40982 | #define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6__SHIFT 0x0 |
40983 | #define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7__SHIFT 0x10 |
40984 | #define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6_MASK 0x0000FFFFL |
40985 | #define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7_MASK 0xFFFF0000L |
40986 | //GC_CAC_WEIGHT_TD_4 |
40987 | #define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8__SHIFT 0x0 |
40988 | #define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9__SHIFT 0x10 |
40989 | #define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8_MASK 0x0000FFFFL |
40990 | #define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9_MASK 0xFFFF0000L |
40991 | //GC_CAC_WEIGHT_RMI_0 |
40992 | #define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0 |
40993 | #define GC_CAC_WEIGHT_RMI_0__UNUSED_0__SHIFT 0x10 |
40994 | #define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL |
40995 | #define GC_CAC_WEIGHT_RMI_0__UNUSED_0_MASK 0xFFFF0000L |
40996 | //GC_CAC_WEIGHT_EA_0 |
40997 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0 |
40998 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10 |
40999 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL |
41000 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L |
41001 | //GC_CAC_WEIGHT_EA_1 |
41002 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0 |
41003 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10 |
41004 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL |
41005 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L |
41006 | //GC_CAC_WEIGHT_EA_2 |
41007 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0 |
41008 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10 |
41009 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL |
41010 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L |
41011 | //GC_CAC_WEIGHT_UTCL2_ATCL2_0 |
41012 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0 |
41013 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10 |
41014 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL |
41015 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L |
41016 | //GC_CAC_WEIGHT_UTCL2_ATCL2_1 |
41017 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0 |
41018 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10 |
41019 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL |
41020 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L |
41021 | //GC_CAC_WEIGHT_UTCL2_ATCL2_2 |
41022 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0 |
41023 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__UNUSED_0__SHIFT 0x10 |
41024 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL |
41025 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__UNUSED_0_MASK 0xFFFF0000L |
41026 | //GC_CAC_WEIGHT_UTCL2_ROUTER_0 |
41027 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0 |
41028 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10 |
41029 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL |
41030 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L |
41031 | //GC_CAC_WEIGHT_UTCL2_ROUTER_1 |
41032 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0 |
41033 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10 |
41034 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL |
41035 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L |
41036 | //GC_CAC_WEIGHT_UTCL2_ROUTER_2 |
41037 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0 |
41038 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10 |
41039 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL |
41040 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L |
41041 | //GC_CAC_WEIGHT_UTCL2_ROUTER_3 |
41042 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0 |
41043 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10 |
41044 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL |
41045 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L |
41046 | //GC_CAC_WEIGHT_UTCL2_ROUTER_4 |
41047 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0 |
41048 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10 |
41049 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL |
41050 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L |
41051 | //GC_CAC_WEIGHT_UTCL2_VML2_0 |
41052 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0 |
41053 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10 |
41054 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL |
41055 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L |
41056 | //GC_CAC_WEIGHT_UTCL2_VML2_1 |
41057 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0 |
41058 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10 |
41059 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL |
41060 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L |
41061 | //GC_CAC_WEIGHT_UTCL2_VML2_2 |
41062 | #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0 |
41063 | #define GC_CAC_WEIGHT_UTCL2_VML2_2__UNUSED_0__SHIFT 0x10 |
41064 | #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL |
41065 | #define GC_CAC_WEIGHT_UTCL2_VML2_2__UNUSED_0_MASK 0xFFFF0000L |
41066 | //GC_CAC_WEIGHT_UTCL2_WALKER_0 |
41067 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0 |
41068 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10 |
41069 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL |
41070 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L |
41071 | //GC_CAC_WEIGHT_UTCL2_WALKER_1 |
41072 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0 |
41073 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10 |
41074 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL |
41075 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L |
41076 | //GC_CAC_WEIGHT_UTCL2_WALKER_2 |
41077 | #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0 |
41078 | #define GC_CAC_WEIGHT_UTCL2_WALKER_2__UNUSED_0__SHIFT 0x10 |
41079 | #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL |
41080 | #define GC_CAC_WEIGHT_UTCL2_WALKER_2__UNUSED_0_MASK 0xFFFF0000L |
41081 | //GC_CAC_WEIGHT_CU_0 |
41082 | #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 |
41083 | #define GC_CAC_WEIGHT_CU_0__UNUSED_0__SHIFT 0x10 |
41084 | #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL |
41085 | #define GC_CAC_WEIGHT_CU_0__UNUSED_0_MASK 0xFFFF0000L |
41086 | //GC_CAC_WEIGHT_UTCL1_0 |
41087 | #define GC_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0__SHIFT 0x0 |
41088 | #define GC_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0_MASK 0x0000FFFFL |
41089 | //GC_CAC_WEIGHT_GE_0 |
41090 | #define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0__SHIFT 0x0 |
41091 | #define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0_MASK 0x0000FFFFL |
41092 | //GC_CAC_WEIGHT_PMM_0 |
41093 | #define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0__SHIFT 0x0 |
41094 | #define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0_MASK 0x0000FFFFL |
41095 | //GC_CAC_WEIGHT_GL2C_0 |
41096 | #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0__SHIFT 0x0 |
41097 | #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1__SHIFT 0x10 |
41098 | #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0_MASK 0x0000FFFFL |
41099 | #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1_MASK 0xFFFF0000L |
41100 | //GC_CAC_WEIGHT_GL2C_1 |
41101 | #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2__SHIFT 0x0 |
41102 | #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3__SHIFT 0x10 |
41103 | #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2_MASK 0x0000FFFFL |
41104 | #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3_MASK 0xFFFF0000L |
41105 | //GC_CAC_WEIGHT_GL2C_2 |
41106 | #define GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4__SHIFT 0x0 |
41107 | #define GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4_MASK 0x0000FFFFL |
41108 | //GC_CAC_WEIGHT_GUS_0 |
41109 | #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0__SHIFT 0x0 |
41110 | #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1__SHIFT 0x10 |
41111 | #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0_MASK 0x0000FFFFL |
41112 | #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1_MASK 0xFFFF0000L |
41113 | //GC_CAC_WEIGHT_GUS_1 |
41114 | #define GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2__SHIFT 0x0 |
41115 | #define GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2_MASK 0x0000FFFFL |
41116 | //GC_CAC_WEIGHT_PH_0 |
41117 | #define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0__SHIFT 0x0 |
41118 | #define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0_MASK 0x0000FFFFL |
41119 | //GC_CAC_ACC_BCI0 |
41120 | #define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0 |
41121 | #define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41122 | //GC_CAC_ACC_BCI1 |
41123 | #define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0 |
41124 | #define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41125 | //GC_CAC_ACC_CB0 |
41126 | #define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0 |
41127 | #define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41128 | //GC_CAC_ACC_CB1 |
41129 | #define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0 |
41130 | #define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41131 | //GC_CAC_ACC_CB2 |
41132 | #define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0 |
41133 | #define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41134 | //GC_CAC_ACC_CB3 |
41135 | #define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0 |
41136 | #define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41137 | //GC_CAC_ACC_CBR0 |
41138 | #define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0__SHIFT 0x0 |
41139 | #define GC_CAC_ACC_CBR0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41140 | //GC_CAC_ACC_CBR1 |
41141 | #define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0__SHIFT 0x0 |
41142 | #define GC_CAC_ACC_CBR1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41143 | //GC_CAC_ACC_CBR2 |
41144 | #define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0__SHIFT 0x0 |
41145 | #define GC_CAC_ACC_CBR2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41146 | //GC_CAC_ACC_CBR3 |
41147 | #define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0__SHIFT 0x0 |
41148 | #define GC_CAC_ACC_CBR3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41149 | //GC_CAC_ACC_CP0 |
41150 | #define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0 |
41151 | #define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41152 | //GC_CAC_ACC_CP1 |
41153 | #define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0 |
41154 | #define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41155 | //GC_CAC_ACC_CP2 |
41156 | #define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0 |
41157 | #define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41158 | //GC_CAC_ACC_DB0 |
41159 | #define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0 |
41160 | #define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41161 | //GC_CAC_ACC_DB1 |
41162 | #define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0 |
41163 | #define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41164 | //GC_CAC_ACC_DB2 |
41165 | #define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0 |
41166 | #define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41167 | //GC_CAC_ACC_DB3 |
41168 | #define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0 |
41169 | #define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41170 | //GC_CAC_ACC_DBR0 |
41171 | #define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0__SHIFT 0x0 |
41172 | #define GC_CAC_ACC_DBR0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41173 | //GC_CAC_ACC_DBR1 |
41174 | #define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0__SHIFT 0x0 |
41175 | #define GC_CAC_ACC_DBR1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41176 | //GC_CAC_ACC_DBR2 |
41177 | #define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0__SHIFT 0x0 |
41178 | #define GC_CAC_ACC_DBR2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41179 | //GC_CAC_ACC_DBR3 |
41180 | #define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0__SHIFT 0x0 |
41181 | #define GC_CAC_ACC_DBR3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41182 | //GC_CAC_ACC_GDS0 |
41183 | #define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0 |
41184 | #define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41185 | //GC_CAC_ACC_GDS1 |
41186 | #define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0 |
41187 | #define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41188 | //GC_CAC_ACC_GDS2 |
41189 | #define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0 |
41190 | #define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41191 | //GC_CAC_ACC_GDS3 |
41192 | #define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0 |
41193 | #define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41194 | //GC_CAC_ACC_LDS0 |
41195 | #define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0 |
41196 | #define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41197 | //GC_CAC_ACC_LDS1 |
41198 | #define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0 |
41199 | #define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41200 | //GC_CAC_ACC_LDS2 |
41201 | #define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0 |
41202 | #define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41203 | //GC_CAC_ACC_LDS3 |
41204 | #define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0 |
41205 | #define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41206 | //GC_CAC_ACC_PA0 |
41207 | #define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0 |
41208 | #define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41209 | //GC_CAC_ACC_PA1 |
41210 | #define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0 |
41211 | #define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41212 | //GC_CAC_ACC_PC0 |
41213 | #define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0 |
41214 | #define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41215 | //GC_CAC_ACC_SC0 |
41216 | #define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0 |
41217 | #define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41218 | //GC_CAC_ACC_SPI0 |
41219 | #define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0 |
41220 | #define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41221 | //GC_CAC_ACC_SPI1 |
41222 | #define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0 |
41223 | #define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41224 | //GC_CAC_ACC_SPI2 |
41225 | #define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0 |
41226 | #define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41227 | //GC_CAC_ACC_SPI3 |
41228 | #define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0 |
41229 | #define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41230 | //GC_CAC_ACC_SPI4 |
41231 | #define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0 |
41232 | #define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41233 | //GC_CAC_ACC_SPI5 |
41234 | #define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0 |
41235 | #define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41236 | //GC_CAC_ACC_SQ0_LOWER |
41237 | #define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
41238 | #define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41239 | //GC_CAC_ACC_SQ0_UPPER |
41240 | #define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
41241 | #define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT 0x8 |
41242 | #define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
41243 | #define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
41244 | //GC_CAC_ACC_SQ1_LOWER |
41245 | #define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
41246 | #define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41247 | //GC_CAC_ACC_SQ1_UPPER |
41248 | #define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
41249 | #define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT 0x8 |
41250 | #define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
41251 | #define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
41252 | //GC_CAC_ACC_SQ2_LOWER |
41253 | #define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
41254 | #define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41255 | //GC_CAC_ACC_SQ2_UPPER |
41256 | #define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
41257 | #define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT 0x8 |
41258 | #define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
41259 | #define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
41260 | //GC_CAC_ACC_SQ3_LOWER |
41261 | #define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
41262 | #define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41263 | //GC_CAC_ACC_SQ3_UPPER |
41264 | #define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
41265 | #define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT 0x8 |
41266 | #define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
41267 | #define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
41268 | //GC_CAC_ACC_SQ4_LOWER |
41269 | #define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
41270 | #define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41271 | //GC_CAC_ACC_SQ4_UPPER |
41272 | #define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
41273 | #define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT 0x8 |
41274 | #define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
41275 | #define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
41276 | //GC_CAC_ACC_SQ5_LOWER |
41277 | #define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
41278 | #define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41279 | //GC_CAC_ACC_SQ5_UPPER |
41280 | #define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
41281 | #define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT 0x8 |
41282 | #define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
41283 | #define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
41284 | //GC_CAC_ACC_SQ6_LOWER |
41285 | #define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
41286 | #define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41287 | //GC_CAC_ACC_SQ6_UPPER |
41288 | #define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
41289 | #define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT 0x8 |
41290 | #define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
41291 | #define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
41292 | //GC_CAC_ACC_SQ7_LOWER |
41293 | #define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
41294 | #define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41295 | //GC_CAC_ACC_SQ7_UPPER |
41296 | #define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
41297 | #define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT 0x8 |
41298 | #define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
41299 | #define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
41300 | //GC_CAC_ACC_SQ8_LOWER |
41301 | #define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
41302 | #define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41303 | //GC_CAC_ACC_SQ8_UPPER |
41304 | #define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
41305 | #define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT 0x8 |
41306 | #define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
41307 | #define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
41308 | //GC_CAC_ACC_SX0 |
41309 | #define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0 |
41310 | #define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41311 | //GC_CAC_ACC_SXRB0 |
41312 | #define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0 |
41313 | #define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41314 | //GC_CAC_ACC_TA0 |
41315 | #define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0 |
41316 | #define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41317 | //GC_CAC_ACC_TCP0 |
41318 | #define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0 |
41319 | #define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41320 | //GC_CAC_ACC_TCP1 |
41321 | #define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0 |
41322 | #define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41323 | //GC_CAC_ACC_TCP2 |
41324 | #define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0 |
41325 | #define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41326 | //GC_CAC_ACC_TCP3 |
41327 | #define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0 |
41328 | #define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41329 | //GC_CAC_ACC_TCP4 |
41330 | #define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0 |
41331 | #define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41332 | //GC_CAC_ACC_TD0 |
41333 | #define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0 |
41334 | #define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41335 | //GC_CAC_ACC_TD1 |
41336 | #define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0 |
41337 | #define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41338 | //GC_CAC_ACC_TD2 |
41339 | #define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0 |
41340 | #define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41341 | //GC_CAC_ACC_TD3 |
41342 | #define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0 |
41343 | #define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41344 | //GC_CAC_ACC_TD4 |
41345 | #define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0 |
41346 | #define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41347 | //GC_CAC_ACC_TD5 |
41348 | #define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0 |
41349 | #define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41350 | //GC_CAC_ACC_TD6 |
41351 | #define GC_CAC_ACC_TD6__ACCUMULATOR_31_0__SHIFT 0x0 |
41352 | #define GC_CAC_ACC_TD6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41353 | //GC_CAC_ACC_TD7 |
41354 | #define GC_CAC_ACC_TD7__ACCUMULATOR_31_0__SHIFT 0x0 |
41355 | #define GC_CAC_ACC_TD7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41356 | //GC_CAC_ACC_TD8 |
41357 | #define GC_CAC_ACC_TD8__ACCUMULATOR_31_0__SHIFT 0x0 |
41358 | #define GC_CAC_ACC_TD8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41359 | //GC_CAC_ACC_TD9 |
41360 | #define GC_CAC_ACC_TD9__ACCUMULATOR_31_0__SHIFT 0x0 |
41361 | #define GC_CAC_ACC_TD9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41362 | //GC_CAC_ACC_RMI0 |
41363 | #define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0 |
41364 | #define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41365 | //GC_CAC_ACC_EA0 |
41366 | #define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0 |
41367 | #define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41368 | //GC_CAC_ACC_EA1 |
41369 | #define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0 |
41370 | #define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41371 | //GC_CAC_ACC_EA2 |
41372 | #define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0 |
41373 | #define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41374 | //GC_CAC_ACC_EA3 |
41375 | #define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0 |
41376 | #define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41377 | //GC_CAC_ACC_EA4 |
41378 | #define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0 |
41379 | #define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41380 | //GC_CAC_ACC_EA5 |
41381 | #define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0 |
41382 | #define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41383 | //GC_CAC_ACC_UTCL2_ATCL20 |
41384 | #define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0 |
41385 | #define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41386 | //GC_CAC_ACC_UTCL2_ATCL21 |
41387 | #define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0 |
41388 | #define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41389 | //GC_CAC_ACC_UTCL2_ATCL22 |
41390 | #define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0 |
41391 | #define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41392 | //GC_CAC_ACC_UTCL2_ATCL23 |
41393 | #define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0 |
41394 | #define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41395 | //GC_CAC_ACC_UTCL2_ATCL24 |
41396 | #define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0 |
41397 | #define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41398 | //GC_CAC_ACC_UTCL2_ROUTER0 |
41399 | #define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0 |
41400 | #define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41401 | //GC_CAC_ACC_UTCL2_ROUTER1 |
41402 | #define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0 |
41403 | #define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41404 | //GC_CAC_ACC_UTCL2_ROUTER2 |
41405 | #define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0 |
41406 | #define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41407 | //GC_CAC_ACC_UTCL2_ROUTER3 |
41408 | #define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0 |
41409 | #define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41410 | //GC_CAC_ACC_UTCL2_ROUTER4 |
41411 | #define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0 |
41412 | #define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41413 | //GC_CAC_ACC_UTCL2_ROUTER5 |
41414 | #define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0 |
41415 | #define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41416 | //GC_CAC_ACC_UTCL2_ROUTER6 |
41417 | #define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0 |
41418 | #define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41419 | //GC_CAC_ACC_UTCL2_ROUTER7 |
41420 | #define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0 |
41421 | #define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41422 | //GC_CAC_ACC_UTCL2_ROUTER8 |
41423 | #define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0 |
41424 | #define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41425 | //GC_CAC_ACC_UTCL2_ROUTER9 |
41426 | #define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0 |
41427 | #define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41428 | //GC_CAC_ACC_UTCL2_VML20 |
41429 | #define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0 |
41430 | #define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41431 | //GC_CAC_ACC_UTCL2_VML21 |
41432 | #define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0 |
41433 | #define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41434 | //GC_CAC_ACC_UTCL2_VML22 |
41435 | #define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0 |
41436 | #define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41437 | //GC_CAC_ACC_UTCL2_VML23 |
41438 | #define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0 |
41439 | #define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41440 | //GC_CAC_ACC_UTCL2_VML24 |
41441 | #define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0 |
41442 | #define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41443 | //GC_CAC_ACC_UTCL2_WALKER0 |
41444 | #define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0 |
41445 | #define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41446 | //GC_CAC_ACC_UTCL2_WALKER1 |
41447 | #define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0 |
41448 | #define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41449 | //GC_CAC_ACC_UTCL2_WALKER2 |
41450 | #define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0 |
41451 | #define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41452 | //GC_CAC_ACC_UTCL2_WALKER3 |
41453 | #define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0 |
41454 | #define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41455 | //GC_CAC_ACC_UTCL2_WALKER4 |
41456 | #define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0 |
41457 | #define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41458 | //GC_CAC_ACC_CU0 |
41459 | #define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0 |
41460 | #define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41461 | //GC_CAC_ACC_UTCL10 |
41462 | #define GC_CAC_ACC_UTCL10__ACCUMULATOR_31_0__SHIFT 0x0 |
41463 | #define GC_CAC_ACC_UTCL10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41464 | //GC_CAC_ACC_CH0 |
41465 | #define GC_CAC_ACC_CH0__ACCUMULATOR_31_0__SHIFT 0x0 |
41466 | #define GC_CAC_ACC_CH0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41467 | //GC_CAC_ACC_GE0 |
41468 | #define GC_CAC_ACC_GE0__ACCUMULATOR_31_0__SHIFT 0x0 |
41469 | #define GC_CAC_ACC_GE0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41470 | //GC_CAC_ACC_PMM0 |
41471 | #define GC_CAC_ACC_PMM0__ACCUMULATOR_31_0__SHIFT 0x0 |
41472 | #define GC_CAC_ACC_PMM0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41473 | //GC_CAC_ACC_GL2C0 |
41474 | #define GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0__SHIFT 0x0 |
41475 | #define GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41476 | //GC_CAC_ACC_GL2C1 |
41477 | #define GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0__SHIFT 0x0 |
41478 | #define GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41479 | //GC_CAC_ACC_GL2C2 |
41480 | #define GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0__SHIFT 0x0 |
41481 | #define GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41482 | //GC_CAC_ACC_GL2C3 |
41483 | #define GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0__SHIFT 0x0 |
41484 | #define GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41485 | //GC_CAC_ACC_GL2C4 |
41486 | #define GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0__SHIFT 0x0 |
41487 | #define GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41488 | //GC_CAC_ACC_GUS0 |
41489 | #define GC_CAC_ACC_GUS0__ACCUMULATOR_31_0__SHIFT 0x0 |
41490 | #define GC_CAC_ACC_GUS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41491 | //GC_CAC_ACC_GUS1 |
41492 | #define GC_CAC_ACC_GUS1__ACCUMULATOR_31_0__SHIFT 0x0 |
41493 | #define GC_CAC_ACC_GUS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41494 | //GC_CAC_ACC_GUS2 |
41495 | #define GC_CAC_ACC_GUS2__ACCUMULATOR_31_0__SHIFT 0x0 |
41496 | #define GC_CAC_ACC_GUS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41497 | //GC_CAC_ACC_PH0 |
41498 | #define GC_CAC_ACC_PH0__ACCUMULATOR_31_0__SHIFT 0x0 |
41499 | #define GC_CAC_ACC_PH0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
41500 | //GC_CAC_OVRD_BCI |
41501 | #define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0 |
41502 | #define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2 |
41503 | #define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L |
41504 | #define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL |
41505 | //GC_CAC_OVRD_CB |
41506 | #define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0 |
41507 | #define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4 |
41508 | #define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL |
41509 | #define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L |
41510 | //GC_CAC_OVRD_CBR |
41511 | #define GC_CAC_OVRD_CBR__OVRRD_SELECT__SHIFT 0x0 |
41512 | #define GC_CAC_OVRD_CBR__OVRRD_VALUE__SHIFT 0x4 |
41513 | #define GC_CAC_OVRD_CBR__OVRRD_SELECT_MASK 0x0000000FL |
41514 | #define GC_CAC_OVRD_CBR__OVRRD_VALUE_MASK 0x000000F0L |
41515 | //GC_CAC_OVRD_CP |
41516 | #define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0 |
41517 | #define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3 |
41518 | #define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L |
41519 | #define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L |
41520 | //GC_CAC_OVRD_DB |
41521 | #define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0 |
41522 | #define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4 |
41523 | #define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL |
41524 | #define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L |
41525 | //GC_CAC_OVRD_DBR |
41526 | #define GC_CAC_OVRD_DBR__OVRRD_SELECT__SHIFT 0x0 |
41527 | #define GC_CAC_OVRD_DBR__OVRRD_VALUE__SHIFT 0x4 |
41528 | #define GC_CAC_OVRD_DBR__OVRRD_SELECT_MASK 0x0000000FL |
41529 | #define GC_CAC_OVRD_DBR__OVRRD_VALUE_MASK 0x000000F0L |
41530 | //GC_CAC_OVRD_GDS |
41531 | #define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0 |
41532 | #define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4 |
41533 | #define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL |
41534 | #define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L |
41535 | //GC_CAC_OVRD_LDS |
41536 | #define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0 |
41537 | #define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4 |
41538 | #define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL |
41539 | #define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L |
41540 | //GC_CAC_OVRD_PA |
41541 | #define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0 |
41542 | #define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2 |
41543 | #define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L |
41544 | #define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL |
41545 | //GC_CAC_OVRD_PC |
41546 | #define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0 |
41547 | #define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1 |
41548 | #define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L |
41549 | #define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L |
41550 | //GC_CAC_OVRD_SC |
41551 | #define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0 |
41552 | #define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1 |
41553 | #define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L |
41554 | #define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L |
41555 | //GC_CAC_OVRD_SPI |
41556 | #define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0 |
41557 | #define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6 |
41558 | #define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL |
41559 | #define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L |
41560 | //GC_CAC_OVRD_CU |
41561 | #define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0 |
41562 | #define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1 |
41563 | #define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L |
41564 | #define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L |
41565 | //GC_CAC_OVRD_SQ |
41566 | #define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0 |
41567 | #define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x6 |
41568 | #define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x0000003FL |
41569 | #define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x00000FC0L |
41570 | //GC_CAC_OVRD_SX |
41571 | #define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0 |
41572 | #define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1 |
41573 | #define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L |
41574 | #define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L |
41575 | //GC_CAC_OVRD_SXRB |
41576 | #define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0 |
41577 | #define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1 |
41578 | #define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L |
41579 | #define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L |
41580 | //GC_CAC_OVRD_TA |
41581 | #define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0 |
41582 | #define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1 |
41583 | #define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L |
41584 | #define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L |
41585 | //GC_CAC_OVRD_TCP |
41586 | #define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0 |
41587 | #define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5 |
41588 | #define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL |
41589 | #define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L |
41590 | //GC_CAC_OVRD_TD |
41591 | #define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0 |
41592 | #define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0xa |
41593 | #define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x000003FFL |
41594 | #define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x000FFC00L |
41595 | //GC_CAC_OVRD_RMI |
41596 | #define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0 |
41597 | #define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1 |
41598 | #define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L |
41599 | #define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L |
41600 | //GC_CAC_OVRD_EA |
41601 | #define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0 |
41602 | #define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6 |
41603 | #define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL |
41604 | #define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L |
41605 | //GC_CAC_OVRD_UTCL2_ATCL2 |
41606 | #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0 |
41607 | #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5 |
41608 | #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL |
41609 | #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L |
41610 | //GC_CAC_OVRD_UTCL2_ROUTER |
41611 | #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0 |
41612 | #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa |
41613 | #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL |
41614 | #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L |
41615 | //GC_CAC_OVRD_UTCL2_VML2 |
41616 | #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0 |
41617 | #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5 |
41618 | #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL |
41619 | #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L |
41620 | //GC_CAC_OVRD_UTCL2_WALKER |
41621 | #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0 |
41622 | #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5 |
41623 | #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL |
41624 | #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L |
41625 | //GC_CAC_OVRD_UTCL1 |
41626 | #define GC_CAC_OVRD_UTCL1__OVRRD_SELECT__SHIFT 0x0 |
41627 | #define GC_CAC_OVRD_UTCL1__OVRRD_VALUE__SHIFT 0x1 |
41628 | #define GC_CAC_OVRD_UTCL1__OVRRD_SELECT_MASK 0x00000001L |
41629 | #define GC_CAC_OVRD_UTCL1__OVRRD_VALUE_MASK 0x00000002L |
41630 | //GC_CAC_OVRD_GE |
41631 | #define GC_CAC_OVRD_GE__OVRRD_SELECT__SHIFT 0x0 |
41632 | #define GC_CAC_OVRD_GE__OVRRD_VALUE__SHIFT 0x1 |
41633 | #define GC_CAC_OVRD_GE__OVRRD_SELECT_MASK 0x00000001L |
41634 | #define GC_CAC_OVRD_GE__OVRRD_VALUE_MASK 0x00000002L |
41635 | //GC_CAC_OVRD_PMM |
41636 | #define GC_CAC_OVRD_PMM__OVRRD_SELECT__SHIFT 0x0 |
41637 | #define GC_CAC_OVRD_PMM__OVRRD_VALUE__SHIFT 0x1 |
41638 | #define GC_CAC_OVRD_PMM__OVRRD_SELECT_MASK 0x00000001L |
41639 | #define GC_CAC_OVRD_PMM__OVRRD_VALUE_MASK 0x00000002L |
41640 | //GC_CAC_OVRD_GL2C |
41641 | #define GC_CAC_OVRD_GL2C__OVRRD_SELECT__SHIFT 0x0 |
41642 | #define GC_CAC_OVRD_GL2C__OVRRD_VALUE__SHIFT 0x5 |
41643 | #define GC_CAC_OVRD_GL2C__OVRRD_SELECT_MASK 0x0000001FL |
41644 | #define GC_CAC_OVRD_GL2C__OVRRD_VALUE_MASK 0x000003E0L |
41645 | //GC_CAC_OVRD_GUS |
41646 | #define GC_CAC_OVRD_GUS__OVRRD_SELECT__SHIFT 0x0 |
41647 | #define GC_CAC_OVRD_GUS__OVRRD_VALUE__SHIFT 0x3 |
41648 | #define GC_CAC_OVRD_GUS__OVRRD_SELECT_MASK 0x00000007L |
41649 | #define GC_CAC_OVRD_GUS__OVRRD_VALUE_MASK 0x00000038L |
41650 | //GC_CAC_OVRD_PH |
41651 | #define GC_CAC_OVRD_PH__OVRRD_SELECT__SHIFT 0x0 |
41652 | #define GC_CAC_OVRD_PH__OVRRD_VALUE__SHIFT 0x1 |
41653 | #define GC_CAC_OVRD_PH__OVRRD_SELECT_MASK 0x00000001L |
41654 | #define GC_CAC_OVRD_PH__OVRRD_VALUE_MASK 0x00000002L |
41655 | //RELEASE_TO_STALL_LUT_1_8 |
41656 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT 0x0 |
41657 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT 0x4 |
41658 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT 0x8 |
41659 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT 0xc |
41660 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT 0x10 |
41661 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT 0x14 |
41662 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT 0x18 |
41663 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT 0x1c |
41664 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK 0x00000007L |
41665 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK 0x00000070L |
41666 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK 0x00000700L |
41667 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK 0x00007000L |
41668 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK 0x00070000L |
41669 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK 0x00700000L |
41670 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK 0x07000000L |
41671 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK 0x70000000L |
41672 | //RELEASE_TO_STALL_LUT_9_16 |
41673 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT 0x0 |
41674 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT 0x4 |
41675 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT 0x8 |
41676 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT 0xc |
41677 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT 0x10 |
41678 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT 0x14 |
41679 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT 0x18 |
41680 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT 0x1c |
41681 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK 0x00000007L |
41682 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK 0x00000070L |
41683 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK 0x00000700L |
41684 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK 0x00007000L |
41685 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK 0x00070000L |
41686 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK 0x00700000L |
41687 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK 0x07000000L |
41688 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK 0x70000000L |
41689 | //RELEASE_TO_STALL_LUT_17_20 |
41690 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT 0x0 |
41691 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT 0x4 |
41692 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT 0x8 |
41693 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT 0xc |
41694 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK 0x00000007L |
41695 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK 0x00000070L |
41696 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK 0x00000700L |
41697 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK 0x00007000L |
41698 | //STALL_TO_RELEASE_LUT_1_4 |
41699 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0 |
41700 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8 |
41701 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10 |
41702 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18 |
41703 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK 0x0000001FL |
41704 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK 0x00001F00L |
41705 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK 0x001F0000L |
41706 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK 0x1F000000L |
41707 | //STALL_TO_RELEASE_LUT_5_7 |
41708 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0 |
41709 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8 |
41710 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10 |
41711 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK 0x0000001FL |
41712 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK 0x00001F00L |
41713 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK 0x001F0000L |
41714 | //STALL_TO_PWRBRK_LUT_1_4 |
41715 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0 |
41716 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8 |
41717 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10 |
41718 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18 |
41719 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1_MASK 0x00000007L |
41720 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2_MASK 0x00000700L |
41721 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3_MASK 0x00070000L |
41722 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4_MASK 0x07000000L |
41723 | //STALL_TO_PWRBRK_LUT_5_7 |
41724 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0 |
41725 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8 |
41726 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10 |
41727 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5_MASK 0x00000007L |
41728 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6_MASK 0x00000700L |
41729 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7_MASK 0x00070000L |
41730 | //PWRBRK_STALL_TO_RELEASE_LUT_1_4 |
41731 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0 |
41732 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8 |
41733 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10 |
41734 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18 |
41735 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK 0x0000001FL |
41736 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK 0x00001F00L |
41737 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK 0x001F0000L |
41738 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK 0x1F000000L |
41739 | //PWRBRK_STALL_TO_RELEASE_LUT_5_7 |
41740 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0 |
41741 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8 |
41742 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10 |
41743 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK 0x0000001FL |
41744 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK 0x00001F00L |
41745 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK 0x001F0000L |
41746 | //PWRBRK_RELEASE_TO_STALL_LUT_1_8 |
41747 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT 0x0 |
41748 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT 0x4 |
41749 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT 0x8 |
41750 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT 0xc |
41751 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT 0x10 |
41752 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT 0x14 |
41753 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT 0x18 |
41754 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT 0x1c |
41755 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK 0x00000007L |
41756 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK 0x00000070L |
41757 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK 0x00000700L |
41758 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK 0x00007000L |
41759 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK 0x00070000L |
41760 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK 0x00700000L |
41761 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK 0x07000000L |
41762 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK 0x70000000L |
41763 | //PWRBRK_RELEASE_TO_STALL_LUT_9_16 |
41764 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT 0x0 |
41765 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT 0x4 |
41766 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT 0x8 |
41767 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT 0xc |
41768 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT 0x10 |
41769 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT 0x14 |
41770 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT 0x18 |
41771 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT 0x1c |
41772 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK 0x00000007L |
41773 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK 0x00000070L |
41774 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK 0x00000700L |
41775 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK 0x00007000L |
41776 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK 0x00070000L |
41777 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK 0x00700000L |
41778 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK 0x07000000L |
41779 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK 0x70000000L |
41780 | //PWRBRK_RELEASE_TO_STALL_LUT_17_20 |
41781 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT 0x0 |
41782 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT 0x4 |
41783 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT 0x8 |
41784 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT 0xc |
41785 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK 0x00000007L |
41786 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK 0x00000070L |
41787 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK 0x00000700L |
41788 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK 0x00007000L |
41789 | //FIXED_PATTERN_PERF_COUNTER_1 |
41790 | #define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER__SHIFT 0x0 |
41791 | #define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER_MASK 0x0001FFFFL |
41792 | //FIXED_PATTERN_PERF_COUNTER_2 |
41793 | #define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER__SHIFT 0x0 |
41794 | #define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER_MASK 0x0001FFFFL |
41795 | //FIXED_PATTERN_PERF_COUNTER_3 |
41796 | #define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER__SHIFT 0x0 |
41797 | #define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER_MASK 0x0001FFFFL |
41798 | //FIXED_PATTERN_PERF_COUNTER_4 |
41799 | #define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER__SHIFT 0x0 |
41800 | #define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER_MASK 0x0001FFFFL |
41801 | //FIXED_PATTERN_PERF_COUNTER_5 |
41802 | #define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER__SHIFT 0x0 |
41803 | #define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER_MASK 0x0001FFFFL |
41804 | //FIXED_PATTERN_PERF_COUNTER_6 |
41805 | #define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER__SHIFT 0x0 |
41806 | #define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER_MASK 0x0001FFFFL |
41807 | //FIXED_PATTERN_PERF_COUNTER_7 |
41808 | #define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER__SHIFT 0x0 |
41809 | #define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER_MASK 0x0001FFFFL |
41810 | //FIXED_PATTERN_PERF_COUNTER_8 |
41811 | #define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER__SHIFT 0x0 |
41812 | #define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER_MASK 0x0001FFFFL |
41813 | //FIXED_PATTERN_PERF_COUNTER_9 |
41814 | #define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER__SHIFT 0x0 |
41815 | #define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER_MASK 0x0001FFFFL |
41816 | //FIXED_PATTERN_PERF_COUNTER_10 |
41817 | #define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER__SHIFT 0x0 |
41818 | #define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER_MASK 0x0001FFFFL |
41819 | //HW_LUT_UPDATE_STATUS |
41820 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE__SHIFT 0x0 |
41821 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR__SHIFT 0x1 |
41822 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP__SHIFT 0x2 |
41823 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE__SHIFT 0x5 |
41824 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR__SHIFT 0x6 |
41825 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP__SHIFT 0x7 |
41826 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE__SHIFT 0xa |
41827 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR__SHIFT 0xb |
41828 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP__SHIFT 0xc |
41829 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE__SHIFT 0x11 |
41830 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR__SHIFT 0x12 |
41831 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP__SHIFT 0x13 |
41832 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE__SHIFT 0x16 |
41833 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR__SHIFT 0x17 |
41834 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP__SHIFT 0x18 |
41835 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE_MASK 0x00000001L |
41836 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_MASK 0x00000002L |
41837 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP_MASK 0x0000001CL |
41838 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE_MASK 0x00000020L |
41839 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_MASK 0x00000040L |
41840 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP_MASK 0x00000380L |
41841 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE_MASK 0x00000400L |
41842 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_MASK 0x00000800L |
41843 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP_MASK 0x0001F000L |
41844 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE_MASK 0x00020000L |
41845 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_MASK 0x00040000L |
41846 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP_MASK 0x00380000L |
41847 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE_MASK 0x00400000L |
41848 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_MASK 0x00800000L |
41849 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP_MASK 0x1F000000L |
41850 | |
41851 | |
41852 | // addressBlock: secacind |
41853 | //SE_CAC_ID |
41854 | #define SE_CAC_ID__CAC_BLOCK_ID__SHIFT 0x0 |
41855 | #define SE_CAC_ID__CAC_SIGNAL_ID__SHIFT 0x6 |
41856 | #define SE_CAC_ID__UNUSED_0__SHIFT 0xe |
41857 | #define SE_CAC_ID__CAC_BLOCK_ID_MASK 0x0000003FL |
41858 | #define SE_CAC_ID__CAC_SIGNAL_ID_MASK 0x00003FC0L |
41859 | #define SE_CAC_ID__UNUSED_0_MASK 0xFFFFC000L |
41860 | //SE_CAC_CNTL |
41861 | #define SE_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0 |
41862 | #define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 |
41863 | #define SE_CAC_CNTL__UNUSED_0__SHIFT 0x11 |
41864 | #define SE_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L |
41865 | #define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL |
41866 | #define SE_CAC_CNTL__UNUSED_0_MASK 0xFFFE0000L |
41867 | //SE_CAC_OVR_SEL |
41868 | #define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 |
41869 | #define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL |
41870 | //SE_CAC_OVR_VAL |
41871 | #define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 |
41872 | #define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL |
41873 | |
41874 | |
41875 | // addressBlock: spmglbind |
41876 | //GLB_CPG_SAMPLEDELAY |
41877 | #define GLB_CPG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41878 | #define GLB_CPG_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41879 | #define GLB_CPG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41880 | #define GLB_CPG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41881 | //GLB_CPC_SAMPLEDELAY |
41882 | #define GLB_CPC_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41883 | #define GLB_CPC_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41884 | #define GLB_CPC_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41885 | #define GLB_CPC_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41886 | //GLB_CPF_SAMPLEDELAY |
41887 | #define GLB_CPF_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41888 | #define GLB_CPF_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41889 | #define GLB_CPF_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41890 | #define GLB_CPF_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41891 | //GLB_GDS_SAMPLEDELAY |
41892 | #define GLB_GDS_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41893 | #define GLB_GDS_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41894 | #define GLB_GDS_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41895 | #define GLB_GDS_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41896 | //GLB_GCR_SAMPLEDELAY |
41897 | #define GLB_GCR_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41898 | #define GLB_GCR_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41899 | #define GLB_GCR_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41900 | #define GLB_GCR_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41901 | //GLB_PH_SAMPLEDELAY |
41902 | #define GLB_PH_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41903 | #define GLB_PH_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41904 | #define GLB_PH_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41905 | #define GLB_PH_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41906 | //GLB_GE_SAMPLEDELAY |
41907 | #define GLB_GE_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41908 | #define GLB_GE_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41909 | #define GLB_GE_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41910 | #define GLB_GE_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41911 | //GLB_GUS_SAMPLEDELAY |
41912 | #define GLB_GUS_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41913 | #define GLB_GUS_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41914 | #define GLB_GUS_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41915 | #define GLB_GUS_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41916 | //GLB_CHA_SAMPLEDELAY |
41917 | #define GLB_CHA_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41918 | #define GLB_CHA_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41919 | #define GLB_CHA_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41920 | #define GLB_CHA_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41921 | //GLB_CHCG_SAMPLEDELAY |
41922 | #define GLB_CHCG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41923 | #define GLB_CHCG_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41924 | #define GLB_CHCG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41925 | #define GLB_CHCG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41926 | //GLB_ATCL2_SAMPLEDELAY |
41927 | #define GLB_ATCL2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41928 | #define GLB_ATCL2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41929 | #define GLB_ATCL2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41930 | #define GLB_ATCL2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41931 | //GLB_VML2_SAMPLEDELAY |
41932 | #define GLB_VML2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41933 | #define GLB_VML2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41934 | #define GLB_VML2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41935 | #define GLB_VML2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41936 | //GLB_SDMA0_SAMPLEDELAY |
41937 | #define GLB_SDMA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41938 | #define GLB_SDMA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41939 | #define GLB_SDMA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41940 | #define GLB_SDMA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41941 | //GLB_SDMA1_SAMPLEDELAY |
41942 | #define GLB_SDMA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41943 | #define GLB_SDMA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41944 | #define GLB_SDMA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41945 | #define GLB_SDMA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41946 | //GLB_GL2A0_SAMPLEDELAY |
41947 | #define GLB_GL2A0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41948 | #define GLB_GL2A0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41949 | #define GLB_GL2A0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41950 | #define GLB_GL2A0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41951 | //GLB_GL2A1_SAMPLEDELAY |
41952 | #define GLB_GL2A1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41953 | #define GLB_GL2A1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41954 | #define GLB_GL2A1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41955 | #define GLB_GL2A1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41956 | //GLB_GL2A2_SAMPLEDELAY |
41957 | #define GLB_GL2A2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41958 | #define GLB_GL2A2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41959 | #define GLB_GL2A2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41960 | #define GLB_GL2A2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41961 | //GLB_GL2A3_SAMPLEDELAY |
41962 | #define GLB_GL2A3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41963 | #define GLB_GL2A3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41964 | #define GLB_GL2A3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41965 | #define GLB_GL2A3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41966 | //GLB_GL2C0_SAMPLEDELAY |
41967 | #define GLB_GL2C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41968 | #define GLB_GL2C0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41969 | #define GLB_GL2C0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41970 | #define GLB_GL2C0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41971 | //GLB_GL2C1_SAMPLEDELAY |
41972 | #define GLB_GL2C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41973 | #define GLB_GL2C1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41974 | #define GLB_GL2C1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41975 | #define GLB_GL2C1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41976 | //GLB_GL2C2_SAMPLEDELAY |
41977 | #define GLB_GL2C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41978 | #define GLB_GL2C2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41979 | #define GLB_GL2C2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41980 | #define GLB_GL2C2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41981 | //GLB_GL2C3_SAMPLEDELAY |
41982 | #define GLB_GL2C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41983 | #define GLB_GL2C3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41984 | #define GLB_GL2C3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41985 | #define GLB_GL2C3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41986 | //GLB_GL2C4_SAMPLEDELAY |
41987 | #define GLB_GL2C4_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41988 | #define GLB_GL2C4_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41989 | #define GLB_GL2C4_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41990 | #define GLB_GL2C4_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41991 | //GLB_GL2C5_SAMPLEDELAY |
41992 | #define GLB_GL2C5_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41993 | #define GLB_GL2C5_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41994 | #define GLB_GL2C5_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
41995 | #define GLB_GL2C5_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
41996 | //GLB_GL2C6_SAMPLEDELAY |
41997 | #define GLB_GL2C6_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
41998 | #define GLB_GL2C6_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
41999 | #define GLB_GL2C6_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42000 | #define GLB_GL2C6_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42001 | //GLB_GL2C7_SAMPLEDELAY |
42002 | #define GLB_GL2C7_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42003 | #define GLB_GL2C7_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42004 | #define GLB_GL2C7_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42005 | #define GLB_GL2C7_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42006 | //GLB_GL2C8_SAMPLEDELAY |
42007 | #define GLB_GL2C8_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42008 | #define GLB_GL2C8_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42009 | #define GLB_GL2C8_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42010 | #define GLB_GL2C8_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42011 | //GLB_GL2C9_SAMPLEDELAY |
42012 | #define GLB_GL2C9_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42013 | #define GLB_GL2C9_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42014 | #define GLB_GL2C9_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42015 | #define GLB_GL2C9_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42016 | //GLB_GL2C10_SAMPLEDELAY |
42017 | #define GLB_GL2C10_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42018 | #define GLB_GL2C10_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42019 | #define GLB_GL2C10_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42020 | #define GLB_GL2C10_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42021 | //GLB_GL2C11_SAMPLEDELAY |
42022 | #define GLB_GL2C11_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42023 | #define GLB_GL2C11_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42024 | #define GLB_GL2C11_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42025 | #define GLB_GL2C11_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42026 | //GLB_GL2C12_SAMPLEDELAY |
42027 | #define GLB_GL2C12_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42028 | #define GLB_GL2C12_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42029 | #define GLB_GL2C12_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42030 | #define GLB_GL2C12_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42031 | //GLB_GL2C13_SAMPLEDELAY |
42032 | #define GLB_GL2C13_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42033 | #define GLB_GL2C13_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42034 | #define GLB_GL2C13_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42035 | #define GLB_GL2C13_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42036 | //GLB_GL2C14_SAMPLEDELAY |
42037 | #define GLB_GL2C14_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42038 | #define GLB_GL2C14_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42039 | #define GLB_GL2C14_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42040 | #define GLB_GL2C14_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42041 | //GLB_GL2C15_SAMPLEDELAY |
42042 | #define GLB_GL2C15_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42043 | #define GLB_GL2C15_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42044 | #define GLB_GL2C15_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42045 | #define GLB_GL2C15_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42046 | //GLB_EA0_SAMPLEDELAY |
42047 | #define GLB_EA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42048 | #define GLB_EA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42049 | #define GLB_EA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42050 | #define GLB_EA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42051 | //GLB_EA1_SAMPLEDELAY |
42052 | #define GLB_EA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42053 | #define GLB_EA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42054 | #define GLB_EA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42055 | #define GLB_EA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42056 | //GLB_EA2_SAMPLEDELAY |
42057 | #define GLB_EA2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42058 | #define GLB_EA2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42059 | #define GLB_EA2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42060 | #define GLB_EA2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42061 | //GLB_EA3_SAMPLEDELAY |
42062 | #define GLB_EA3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42063 | #define GLB_EA3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42064 | #define GLB_EA3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42065 | #define GLB_EA3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42066 | //GLB_EA4_SAMPLEDELAY |
42067 | #define GLB_EA4_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42068 | #define GLB_EA4_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42069 | #define GLB_EA4_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42070 | #define GLB_EA4_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42071 | //GLB_EA5_SAMPLEDELAY |
42072 | #define GLB_EA5_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42073 | #define GLB_EA5_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42074 | #define GLB_EA5_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42075 | #define GLB_EA5_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42076 | //GLB_EA6_SAMPLEDELAY |
42077 | #define GLB_EA6_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42078 | #define GLB_EA6_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42079 | #define GLB_EA6_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42080 | #define GLB_EA6_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42081 | //GLB_EA7_SAMPLEDELAY |
42082 | #define GLB_EA7_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42083 | #define GLB_EA7_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42084 | #define GLB_EA7_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42085 | #define GLB_EA7_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42086 | //GLB_EA8_SAMPLEDELAY |
42087 | #define GLB_EA8_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42088 | #define GLB_EA8_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42089 | #define GLB_EA8_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42090 | #define GLB_EA8_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42091 | //GLB_EA9_SAMPLEDELAY |
42092 | #define GLB_EA9_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42093 | #define GLB_EA9_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42094 | #define GLB_EA9_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42095 | #define GLB_EA9_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42096 | //GLB_EA10_SAMPLEDELAY |
42097 | #define GLB_EA10_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42098 | #define GLB_EA10_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42099 | #define GLB_EA10_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42100 | #define GLB_EA10_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42101 | //GLB_EA11_SAMPLEDELAY |
42102 | #define GLB_EA11_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42103 | #define GLB_EA11_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42104 | #define GLB_EA11_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42105 | #define GLB_EA11_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42106 | //GLB_EA12_SAMPLEDELAY |
42107 | #define GLB_EA12_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42108 | #define GLB_EA12_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42109 | #define GLB_EA12_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42110 | #define GLB_EA12_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42111 | //GLB_EA13_SAMPLEDELAY |
42112 | #define GLB_EA13_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42113 | #define GLB_EA13_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42114 | #define GLB_EA13_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42115 | #define GLB_EA13_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42116 | //GLB_EA14_SAMPLEDELAY |
42117 | #define GLB_EA14_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42118 | #define GLB_EA14_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42119 | #define GLB_EA14_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42120 | #define GLB_EA14_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42121 | //GLB_EA15_SAMPLEDELAY |
42122 | #define GLB_EA15_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42123 | #define GLB_EA15_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42124 | #define GLB_EA15_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42125 | #define GLB_EA15_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42126 | //GLB_CHC0_SAMPLEDELAY |
42127 | #define GLB_CHC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42128 | #define GLB_CHC0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42129 | #define GLB_CHC0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42130 | #define GLB_CHC0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42131 | //GLB_CHC1_SAMPLEDELAY |
42132 | #define GLB_CHC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42133 | #define GLB_CHC1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42134 | #define GLB_CHC1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42135 | #define GLB_CHC1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42136 | //GLB_CHC2_SAMPLEDELAY |
42137 | #define GLB_CHC2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42138 | #define GLB_CHC2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42139 | #define GLB_CHC2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42140 | #define GLB_CHC2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42141 | //GLB_CHC3_SAMPLEDELAY |
42142 | #define GLB_CHC3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42143 | #define GLB_CHC3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42144 | #define GLB_CHC3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42145 | #define GLB_CHC3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42146 | |
42147 | |
42148 | // addressBlock: spmind |
42149 | //SE_SPI_SAMPLEDELAY |
42150 | #define SE_SPI_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42151 | #define SE_SPI_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42152 | #define SE_SPI_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42153 | #define SE_SPI_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42154 | //SE_SQG_SAMPLEDELAY |
42155 | #define SE_SQG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42156 | #define SE_SQG_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42157 | #define SE_SQG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42158 | #define SE_SQG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42159 | //SE_CBR_SAMPLEDELAY |
42160 | #define SE_CBR_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42161 | #define SE_CBR_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42162 | #define SE_CBR_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42163 | #define SE_CBR_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42164 | //SE_DBR_SAMPLEDELAY |
42165 | #define SE_DBR_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42166 | #define SE_DBR_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42167 | #define SE_DBR_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42168 | #define SE_DBR_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42169 | //SE_SA0SX_SAMPLEDELAY |
42170 | #define SE_SA0SX_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42171 | #define SE_SA0SX_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42172 | #define SE_SA0SX_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42173 | #define SE_SA0SX_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42174 | //SE_SA0PA_SAMPLEDELAY |
42175 | #define SE_SA0PA_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42176 | #define SE_SA0PA_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42177 | #define SE_SA0PA_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42178 | #define SE_SA0PA_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42179 | //SE_SA0GL1A_SAMPLEDELAY |
42180 | #define SE_SA0GL1A_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42181 | #define SE_SA0GL1A_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42182 | #define SE_SA0GL1A_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42183 | #define SE_SA0GL1A_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42184 | //SE_SA0GL1CG_SAMPLEDELAY |
42185 | #define SE_SA0GL1CG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42186 | #define SE_SA0GL1CG_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42187 | #define SE_SA0GL1CG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42188 | #define SE_SA0GL1CG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42189 | //SE_SA0CB0_SAMPLEDELAY |
42190 | #define SE_SA0CB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42191 | #define SE_SA0CB0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42192 | #define SE_SA0CB0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42193 | #define SE_SA0CB0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42194 | //SE_SA0CB1_SAMPLEDELAY |
42195 | #define SE_SA0CB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42196 | #define SE_SA0CB1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42197 | #define SE_SA0CB1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42198 | #define SE_SA0CB1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42199 | //SE_SA0CB2_SAMPLEDELAY |
42200 | #define SE_SA0CB2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42201 | #define SE_SA0CB2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42202 | #define SE_SA0CB2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42203 | #define SE_SA0CB2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42204 | //SE_SA0CB3_SAMPLEDELAY |
42205 | #define SE_SA0CB3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42206 | #define SE_SA0CB3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42207 | #define SE_SA0CB3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42208 | #define SE_SA0CB3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42209 | //SE_SA0DB0_SAMPLEDELAY |
42210 | #define SE_SA0DB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42211 | #define SE_SA0DB0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42212 | #define SE_SA0DB0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42213 | #define SE_SA0DB0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42214 | //SE_SA0DB1_SAMPLEDELAY |
42215 | #define SE_SA0DB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42216 | #define SE_SA0DB1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42217 | #define SE_SA0DB1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42218 | #define SE_SA0DB1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42219 | //SE_SA0DB2_SAMPLEDELAY |
42220 | #define SE_SA0DB2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42221 | #define SE_SA0DB2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42222 | #define SE_SA0DB2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42223 | #define SE_SA0DB2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42224 | //SE_SA0DB3_SAMPLEDELAY |
42225 | #define SE_SA0DB3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42226 | #define SE_SA0DB3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42227 | #define SE_SA0DB3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42228 | #define SE_SA0DB3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42229 | //SE_SA0SC0_SAMPLEDELAY |
42230 | #define SE_SA0SC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42231 | #define SE_SA0SC0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42232 | #define SE_SA0SC0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42233 | #define SE_SA0SC0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42234 | //SE_SA0SC1_SAMPLEDELAY |
42235 | #define SE_SA0SC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42236 | #define SE_SA0SC1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42237 | #define SE_SA0SC1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42238 | #define SE_SA0SC1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42239 | //SE_SA0RMI0_SAMPLEDELAY |
42240 | #define SE_SA0RMI0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42241 | #define SE_SA0RMI0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42242 | #define SE_SA0RMI0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42243 | #define SE_SA0RMI0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42244 | //SE_SA0RMI1_SAMPLEDELAY |
42245 | #define SE_SA0RMI1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42246 | #define SE_SA0RMI1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42247 | #define SE_SA0RMI1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42248 | #define SE_SA0RMI1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42249 | //SE_SA0GL1C0_SAMPLEDELAY |
42250 | #define SE_SA0GL1C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42251 | #define SE_SA0GL1C0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42252 | #define SE_SA0GL1C0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42253 | #define SE_SA0GL1C0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42254 | //SE_SA0GL1C1_SAMPLEDELAY |
42255 | #define SE_SA0GL1C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42256 | #define SE_SA0GL1C1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42257 | #define SE_SA0GL1C1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42258 | #define SE_SA0GL1C1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42259 | //SE_SA0GL1C2_SAMPLEDELAY |
42260 | #define SE_SA0GL1C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42261 | #define SE_SA0GL1C2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42262 | #define SE_SA0GL1C2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42263 | #define SE_SA0GL1C2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42264 | //SE_SA0GL1C3_SAMPLEDELAY |
42265 | #define SE_SA0GL1C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42266 | #define SE_SA0GL1C3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42267 | #define SE_SA0GL1C3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42268 | #define SE_SA0GL1C3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42269 | //SE_SA0WGP00TA0_SAMPLEDELAY |
42270 | #define SE_SA0WGP00TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42271 | #define SE_SA0WGP00TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42272 | #define SE_SA0WGP00TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42273 | #define SE_SA0WGP00TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42274 | //SE_SA0WGP00TA1_SAMPLEDELAY |
42275 | #define SE_SA0WGP00TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42276 | #define SE_SA0WGP00TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42277 | #define SE_SA0WGP00TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42278 | #define SE_SA0WGP00TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42279 | //SE_SA0WGP00TD0_SAMPLEDELAY |
42280 | #define SE_SA0WGP00TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42281 | #define SE_SA0WGP00TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42282 | #define SE_SA0WGP00TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42283 | #define SE_SA0WGP00TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42284 | //SE_SA0WGP00TD1_SAMPLEDELAY |
42285 | #define SE_SA0WGP00TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42286 | #define SE_SA0WGP00TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42287 | #define SE_SA0WGP00TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42288 | #define SE_SA0WGP00TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42289 | //SE_SA0WGP00TCP0_SAMPLEDELAY |
42290 | #define SE_SA0WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42291 | #define SE_SA0WGP00TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42292 | #define SE_SA0WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42293 | #define SE_SA0WGP00TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42294 | //SE_SA0WGP00TCP1_SAMPLEDELAY |
42295 | #define SE_SA0WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42296 | #define SE_SA0WGP00TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42297 | #define SE_SA0WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42298 | #define SE_SA0WGP00TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42299 | //SE_SA0WGP01TA0_SAMPLEDELAY |
42300 | #define SE_SA0WGP01TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42301 | #define SE_SA0WGP01TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42302 | #define SE_SA0WGP01TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42303 | #define SE_SA0WGP01TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42304 | //SE_SA0WGP01TA1_SAMPLEDELAY |
42305 | #define SE_SA0WGP01TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42306 | #define SE_SA0WGP01TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42307 | #define SE_SA0WGP01TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42308 | #define SE_SA0WGP01TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42309 | //SE_SA0WGP01TD0_SAMPLEDELAY |
42310 | #define SE_SA0WGP01TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42311 | #define SE_SA0WGP01TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42312 | #define SE_SA0WGP01TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42313 | #define SE_SA0WGP01TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42314 | //SE_SA0WGP01TD1_SAMPLEDELAY |
42315 | #define SE_SA0WGP01TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42316 | #define SE_SA0WGP01TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42317 | #define SE_SA0WGP01TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42318 | #define SE_SA0WGP01TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42319 | //SE_SA0WGP01TCP0_SAMPLEDELAY |
42320 | #define SE_SA0WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42321 | #define SE_SA0WGP01TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42322 | #define SE_SA0WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42323 | #define SE_SA0WGP01TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42324 | //SE_SA0WGP01TCP1_SAMPLEDELAY |
42325 | #define SE_SA0WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42326 | #define SE_SA0WGP01TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42327 | #define SE_SA0WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42328 | #define SE_SA0WGP01TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42329 | //SE_SA0WGP02TA0_SAMPLEDELAY |
42330 | #define SE_SA0WGP02TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42331 | #define SE_SA0WGP02TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42332 | #define SE_SA0WGP02TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42333 | #define SE_SA0WGP02TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42334 | //SE_SA0WGP02TA1_SAMPLEDELAY |
42335 | #define SE_SA0WGP02TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42336 | #define SE_SA0WGP02TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42337 | #define SE_SA0WGP02TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42338 | #define SE_SA0WGP02TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42339 | //SE_SA0WGP02TD0_SAMPLEDELAY |
42340 | #define SE_SA0WGP02TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42341 | #define SE_SA0WGP02TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42342 | #define SE_SA0WGP02TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42343 | #define SE_SA0WGP02TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42344 | //SE_SA0WGP02TD1_SAMPLEDELAY |
42345 | #define SE_SA0WGP02TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42346 | #define SE_SA0WGP02TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42347 | #define SE_SA0WGP02TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42348 | #define SE_SA0WGP02TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42349 | //SE_SA0WGP02TCP0_SAMPLEDELAY |
42350 | #define SE_SA0WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42351 | #define SE_SA0WGP02TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42352 | #define SE_SA0WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42353 | #define SE_SA0WGP02TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42354 | //SE_SA0WGP02TCP1_SAMPLEDELAY |
42355 | #define SE_SA0WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42356 | #define SE_SA0WGP02TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42357 | #define SE_SA0WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42358 | #define SE_SA0WGP02TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42359 | //SE_SA0WGP10TA0_SAMPLEDELAY |
42360 | #define SE_SA0WGP10TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42361 | #define SE_SA0WGP10TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42362 | #define SE_SA0WGP10TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42363 | #define SE_SA0WGP10TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42364 | //SE_SA0WGP10TA1_SAMPLEDELAY |
42365 | #define SE_SA0WGP10TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42366 | #define SE_SA0WGP10TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42367 | #define SE_SA0WGP10TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42368 | #define SE_SA0WGP10TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42369 | //SE_SA0WGP10TD0_SAMPLEDELAY |
42370 | #define SE_SA0WGP10TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42371 | #define SE_SA0WGP10TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42372 | #define SE_SA0WGP10TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42373 | #define SE_SA0WGP10TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42374 | //SE_SA0WGP10TD1_SAMPLEDELAY |
42375 | #define SE_SA0WGP10TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42376 | #define SE_SA0WGP10TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42377 | #define SE_SA0WGP10TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42378 | #define SE_SA0WGP10TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42379 | //SE_SA0WGP10TCP0_SAMPLEDELAY |
42380 | #define SE_SA0WGP10TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42381 | #define SE_SA0WGP10TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42382 | #define SE_SA0WGP10TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42383 | #define SE_SA0WGP10TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42384 | //SE_SA0WGP10TCP1_SAMPLEDELAY |
42385 | #define SE_SA0WGP10TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42386 | #define SE_SA0WGP10TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42387 | #define SE_SA0WGP10TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42388 | #define SE_SA0WGP10TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42389 | //SE_SA0WGP11TA0_SAMPLEDELAY |
42390 | #define SE_SA0WGP11TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42391 | #define SE_SA0WGP11TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42392 | #define SE_SA0WGP11TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42393 | #define SE_SA0WGP11TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42394 | //SE_SA0WGP11TA1_SAMPLEDELAY |
42395 | #define SE_SA0WGP11TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42396 | #define SE_SA0WGP11TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42397 | #define SE_SA0WGP11TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42398 | #define SE_SA0WGP11TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42399 | //SE_SA0WGP11TD0_SAMPLEDELAY |
42400 | #define SE_SA0WGP11TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42401 | #define SE_SA0WGP11TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42402 | #define SE_SA0WGP11TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42403 | #define SE_SA0WGP11TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42404 | //SE_SA0WGP11TD1_SAMPLEDELAY |
42405 | #define SE_SA0WGP11TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42406 | #define SE_SA0WGP11TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42407 | #define SE_SA0WGP11TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42408 | #define SE_SA0WGP11TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42409 | //SE_SA0WGP11TCP0_SAMPLEDELAY |
42410 | #define SE_SA0WGP11TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42411 | #define SE_SA0WGP11TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42412 | #define SE_SA0WGP11TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42413 | #define SE_SA0WGP11TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42414 | //SE_SA0WGP11TCP1_SAMPLEDELAY |
42415 | #define SE_SA0WGP11TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42416 | #define SE_SA0WGP11TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42417 | #define SE_SA0WGP11TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42418 | #define SE_SA0WGP11TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42419 | //SE_SA1SX_SAMPLEDELAY |
42420 | #define SE_SA1SX_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42421 | #define SE_SA1SX_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42422 | #define SE_SA1SX_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42423 | #define SE_SA1SX_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42424 | //SE_SA1PA_SAMPLEDELAY |
42425 | #define SE_SA1PA_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42426 | #define SE_SA1PA_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42427 | #define SE_SA1PA_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42428 | #define SE_SA1PA_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42429 | //SE_SA1GL1A_SAMPLEDELAY |
42430 | #define SE_SA1GL1A_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42431 | #define SE_SA1GL1A_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42432 | #define SE_SA1GL1A_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42433 | #define SE_SA1GL1A_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42434 | //SE_SA1GL1CG_SAMPLEDELAY |
42435 | #define SE_SA1GL1CG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42436 | #define SE_SA1GL1CG_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42437 | #define SE_SA1GL1CG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42438 | #define SE_SA1GL1CG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42439 | //SE_SA1CB0_SAMPLEDELAY |
42440 | #define SE_SA1CB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42441 | #define SE_SA1CB0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42442 | #define SE_SA1CB0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42443 | #define SE_SA1CB0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42444 | //SE_SA1CB1_SAMPLEDELAY |
42445 | #define SE_SA1CB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42446 | #define SE_SA1CB1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42447 | #define SE_SA1CB1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42448 | #define SE_SA1CB1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42449 | //SE_SA1CB2_SAMPLEDELAY |
42450 | #define SE_SA1CB2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42451 | #define SE_SA1CB2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42452 | #define SE_SA1CB2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42453 | #define SE_SA1CB2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42454 | //SE_SA1CB3_SAMPLEDELAY |
42455 | #define SE_SA1CB3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42456 | #define SE_SA1CB3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42457 | #define SE_SA1CB3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42458 | #define SE_SA1CB3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42459 | //SE_SA1DB0_SAMPLEDELAY |
42460 | #define SE_SA1DB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42461 | #define SE_SA1DB0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42462 | #define SE_SA1DB0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42463 | #define SE_SA1DB0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42464 | //SE_SA1DB1_SAMPLEDELAY |
42465 | #define SE_SA1DB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42466 | #define SE_SA1DB1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42467 | #define SE_SA1DB1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42468 | #define SE_SA1DB1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42469 | //SE_SA1DB2_SAMPLEDELAY |
42470 | #define SE_SA1DB2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42471 | #define SE_SA1DB2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42472 | #define SE_SA1DB2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42473 | #define SE_SA1DB2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42474 | //SE_SA1DB3_SAMPLEDELAY |
42475 | #define SE_SA1DB3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42476 | #define SE_SA1DB3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42477 | #define SE_SA1DB3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42478 | #define SE_SA1DB3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42479 | //SE_SA1SC0_SAMPLEDELAY |
42480 | #define SE_SA1SC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42481 | #define SE_SA1SC0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42482 | #define SE_SA1SC0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42483 | #define SE_SA1SC0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42484 | //SE_SA1SC1_SAMPLEDELAY |
42485 | #define SE_SA1SC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42486 | #define SE_SA1SC1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42487 | #define SE_SA1SC1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42488 | #define SE_SA1SC1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42489 | //SE_SA1RMI0_SAMPLEDELAY |
42490 | #define SE_SA1RMI0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42491 | #define SE_SA1RMI0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42492 | #define SE_SA1RMI0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42493 | #define SE_SA1RMI0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42494 | //SE_SA1RMI1_SAMPLEDELAY |
42495 | #define SE_SA1RMI1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42496 | #define SE_SA1RMI1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42497 | #define SE_SA1RMI1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42498 | #define SE_SA1RMI1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42499 | //SE_SA1GL1C0_SAMPLEDELAY |
42500 | #define SE_SA1GL1C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42501 | #define SE_SA1GL1C0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42502 | #define SE_SA1GL1C0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42503 | #define SE_SA1GL1C0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42504 | //SE_SA1GL1C1_SAMPLEDELAY |
42505 | #define SE_SA1GL1C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42506 | #define SE_SA1GL1C1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42507 | #define SE_SA1GL1C1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42508 | #define SE_SA1GL1C1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42509 | //SE_SA1GL1C2_SAMPLEDELAY |
42510 | #define SE_SA1GL1C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42511 | #define SE_SA1GL1C2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42512 | #define SE_SA1GL1C2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42513 | #define SE_SA1GL1C2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42514 | //SE_SA1GL1C3_SAMPLEDELAY |
42515 | #define SE_SA1GL1C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42516 | #define SE_SA1GL1C3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42517 | #define SE_SA1GL1C3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42518 | #define SE_SA1GL1C3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42519 | //SE_SA1WGP00TA0_SAMPLEDELAY |
42520 | #define SE_SA1WGP00TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42521 | #define SE_SA1WGP00TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42522 | #define SE_SA1WGP00TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42523 | #define SE_SA1WGP00TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42524 | //SE_SA1WGP00TA1_SAMPLEDELAY |
42525 | #define SE_SA1WGP00TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42526 | #define SE_SA1WGP00TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42527 | #define SE_SA1WGP00TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42528 | #define SE_SA1WGP00TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42529 | //SE_SA1WGP00TD0_SAMPLEDELAY |
42530 | #define SE_SA1WGP00TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42531 | #define SE_SA1WGP00TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42532 | #define SE_SA1WGP00TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42533 | #define SE_SA1WGP00TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42534 | //SE_SA1WGP00TD1_SAMPLEDELAY |
42535 | #define SE_SA1WGP00TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42536 | #define SE_SA1WGP00TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42537 | #define SE_SA1WGP00TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42538 | #define SE_SA1WGP00TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42539 | //SE_SA1WGP00TCP0_SAMPLEDELAY |
42540 | #define SE_SA1WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42541 | #define SE_SA1WGP00TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42542 | #define SE_SA1WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42543 | #define SE_SA1WGP00TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42544 | //SE_SA1WGP00TCP1_SAMPLEDELAY |
42545 | #define SE_SA1WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42546 | #define SE_SA1WGP00TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42547 | #define SE_SA1WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42548 | #define SE_SA1WGP00TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42549 | //SE_SA1WGP01TA0_SAMPLEDELAY |
42550 | #define SE_SA1WGP01TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42551 | #define SE_SA1WGP01TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42552 | #define SE_SA1WGP01TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42553 | #define SE_SA1WGP01TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42554 | //SE_SA1WGP01TA1_SAMPLEDELAY |
42555 | #define SE_SA1WGP01TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42556 | #define SE_SA1WGP01TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42557 | #define SE_SA1WGP01TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42558 | #define SE_SA1WGP01TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42559 | //SE_SA1WGP01TD0_SAMPLEDELAY |
42560 | #define SE_SA1WGP01TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42561 | #define SE_SA1WGP01TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42562 | #define SE_SA1WGP01TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42563 | #define SE_SA1WGP01TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42564 | //SE_SA1WGP01TD1_SAMPLEDELAY |
42565 | #define SE_SA1WGP01TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42566 | #define SE_SA1WGP01TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42567 | #define SE_SA1WGP01TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42568 | #define SE_SA1WGP01TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42569 | //SE_SA1WGP01TCP0_SAMPLEDELAY |
42570 | #define SE_SA1WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42571 | #define SE_SA1WGP01TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42572 | #define SE_SA1WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42573 | #define SE_SA1WGP01TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42574 | //SE_SA1WGP01TCP1_SAMPLEDELAY |
42575 | #define SE_SA1WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42576 | #define SE_SA1WGP01TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42577 | #define SE_SA1WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42578 | #define SE_SA1WGP01TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42579 | //SE_SA1WGP02TA0_SAMPLEDELAY |
42580 | #define SE_SA1WGP02TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42581 | #define SE_SA1WGP02TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42582 | #define SE_SA1WGP02TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42583 | #define SE_SA1WGP02TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42584 | //SE_SA1WGP02TA1_SAMPLEDELAY |
42585 | #define SE_SA1WGP02TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42586 | #define SE_SA1WGP02TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42587 | #define SE_SA1WGP02TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42588 | #define SE_SA1WGP02TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42589 | //SE_SA1WGP02TD0_SAMPLEDELAY |
42590 | #define SE_SA1WGP02TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42591 | #define SE_SA1WGP02TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42592 | #define SE_SA1WGP02TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42593 | #define SE_SA1WGP02TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42594 | //SE_SA1WGP02TD1_SAMPLEDELAY |
42595 | #define SE_SA1WGP02TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42596 | #define SE_SA1WGP02TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42597 | #define SE_SA1WGP02TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42598 | #define SE_SA1WGP02TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42599 | //SE_SA1WGP02TCP0_SAMPLEDELAY |
42600 | #define SE_SA1WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42601 | #define SE_SA1WGP02TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42602 | #define SE_SA1WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42603 | #define SE_SA1WGP02TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42604 | //SE_SA1WGP02TCP1_SAMPLEDELAY |
42605 | #define SE_SA1WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42606 | #define SE_SA1WGP02TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42607 | #define SE_SA1WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42608 | #define SE_SA1WGP02TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42609 | //SE_SA1WGP10TA0_SAMPLEDELAY |
42610 | #define SE_SA1WGP10TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42611 | #define SE_SA1WGP10TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42612 | #define SE_SA1WGP10TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42613 | #define SE_SA1WGP10TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42614 | //SE_SA1WGP10TA1_SAMPLEDELAY |
42615 | #define SE_SA1WGP10TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42616 | #define SE_SA1WGP10TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42617 | #define SE_SA1WGP10TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42618 | #define SE_SA1WGP10TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42619 | //SE_SA1WGP10TD0_SAMPLEDELAY |
42620 | #define SE_SA1WGP10TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42621 | #define SE_SA1WGP10TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42622 | #define SE_SA1WGP10TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42623 | #define SE_SA1WGP10TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42624 | //SE_SA1WGP10TD1_SAMPLEDELAY |
42625 | #define SE_SA1WGP10TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42626 | #define SE_SA1WGP10TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42627 | #define SE_SA1WGP10TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42628 | #define SE_SA1WGP10TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42629 | //SE_SA1WGP10TCP0_SAMPLEDELAY |
42630 | #define SE_SA1WGP10TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42631 | #define SE_SA1WGP10TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42632 | #define SE_SA1WGP10TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42633 | #define SE_SA1WGP10TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42634 | //SE_SA1WGP10TCP1_SAMPLEDELAY |
42635 | #define SE_SA1WGP10TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42636 | #define SE_SA1WGP10TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42637 | #define SE_SA1WGP10TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42638 | #define SE_SA1WGP10TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42639 | //SE_SA1WGP11TA0_SAMPLEDELAY |
42640 | #define SE_SA1WGP11TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42641 | #define SE_SA1WGP11TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42642 | #define SE_SA1WGP11TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42643 | #define SE_SA1WGP11TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42644 | //SE_SA1WGP11TA1_SAMPLEDELAY |
42645 | #define SE_SA1WGP11TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42646 | #define SE_SA1WGP11TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42647 | #define SE_SA1WGP11TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42648 | #define SE_SA1WGP11TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42649 | //SE_SA1WGP11TD0_SAMPLEDELAY |
42650 | #define SE_SA1WGP11TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42651 | #define SE_SA1WGP11TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42652 | #define SE_SA1WGP11TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42653 | #define SE_SA1WGP11TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42654 | //SE_SA1WGP11TD1_SAMPLEDELAY |
42655 | #define SE_SA1WGP11TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42656 | #define SE_SA1WGP11TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42657 | #define SE_SA1WGP11TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42658 | #define SE_SA1WGP11TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42659 | //SE_SA1WGP11TCP0_SAMPLEDELAY |
42660 | #define SE_SA1WGP11TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42661 | #define SE_SA1WGP11TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42662 | #define SE_SA1WGP11TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42663 | #define SE_SA1WGP11TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42664 | //SE_SA1WGP11TCP1_SAMPLEDELAY |
42665 | #define SE_SA1WGP11TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
42666 | #define SE_SA1WGP11TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
42667 | #define SE_SA1WGP11TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
42668 | #define SE_SA1WGP11TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
42669 | |
42670 | |
42671 | // addressBlock: sqind |
42672 | //SQ_DEBUG_STS_GLOBAL |
42673 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL |
42674 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 |
42675 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L |
42676 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 |
42677 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE_MASK 0xff0000L |
42678 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE__SHIFT 0x00000010 |
42679 | #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L |
42680 | #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 |
42681 | #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L |
42682 | #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 |
42683 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0x0000fff0L |
42684 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x00000004 |
42685 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0fff0000L |
42686 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT 0x00000010 |
42687 | |
42688 | //SQ_DEBUG_STS_LOCAL |
42689 | #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L |
42690 | #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000 |
42691 | #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L |
42692 | #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004 |
42693 | #define SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK 0x00001000L |
42694 | #define SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT 0x0000000C |
42695 | #define SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK 0x00002000L |
42696 | #define SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT 0x0000000D |
42697 | #define SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK 0x00004000L |
42698 | #define SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT 0x0000000E |
42699 | #define SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK 0x00008000L |
42700 | #define SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT 0x0000000F |
42701 | #define SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK 0x00010000L |
42702 | #define SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT 0x00000010 |
42703 | #define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK 0x00020000L |
42704 | #define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT 0x00000011 |
42705 | #define SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK 0x00040000L |
42706 | #define SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT 0x00000018 |
42707 | |
42708 | //SQ_WAVE_MODE |
42709 | #define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 |
42710 | #define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 |
42711 | #define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 |
42712 | #define SQ_WAVE_MODE__IEEE__SHIFT 0x9 |
42713 | #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa |
42714 | #define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc |
42715 | #define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17 |
42716 | #define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1b |
42717 | #define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c |
42718 | #define SQ_WAVE_MODE__CSP__SHIFT 0x1d |
42719 | #define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL |
42720 | #define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L |
42721 | #define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L |
42722 | #define SQ_WAVE_MODE__IEEE_MASK 0x00000200L |
42723 | #define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L |
42724 | #define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L |
42725 | #define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L |
42726 | #define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x08000000L |
42727 | #define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L |
42728 | #define SQ_WAVE_MODE__CSP_MASK 0xE0000000L |
42729 | //SQ_WAVE_STATUS |
42730 | #define SQ_WAVE_STATUS__SCC__SHIFT 0x0 |
42731 | #define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 |
42732 | #define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 |
42733 | #define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 |
42734 | #define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 |
42735 | #define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 |
42736 | #define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 |
42737 | #define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 |
42738 | #define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa |
42739 | #define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb |
42740 | #define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc |
42741 | #define SQ_WAVE_STATUS__HALT__SHIFT 0xd |
42742 | #define SQ_WAVE_STATUS__TRAP__SHIFT 0xe |
42743 | #define SQ_WAVE_STATUS__TTRACE_SIMD_EN__SHIFT 0xf |
42744 | #define SQ_WAVE_STATUS__VALID__SHIFT 0x10 |
42745 | #define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 |
42746 | #define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 |
42747 | #define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 |
42748 | #define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17 |
42749 | #define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b |
42750 | #define SQ_WAVE_STATUS__SCC_MASK 0x00000001L |
42751 | #define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L |
42752 | #define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L |
42753 | #define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L |
42754 | #define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L |
42755 | #define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L |
42756 | #define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L |
42757 | #define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L |
42758 | #define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L |
42759 | #define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L |
42760 | #define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L |
42761 | #define SQ_WAVE_STATUS__HALT_MASK 0x00002000L |
42762 | #define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L |
42763 | #define SQ_WAVE_STATUS__TTRACE_SIMD_EN_MASK 0x00008000L |
42764 | #define SQ_WAVE_STATUS__VALID_MASK 0x00010000L |
42765 | #define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L |
42766 | #define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L |
42767 | #define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L |
42768 | #define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L |
42769 | #define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L |
42770 | //SQ_WAVE_TRAPSTS |
42771 | #define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 |
42772 | #define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa |
42773 | #define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb |
42774 | #define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc |
42775 | #define SQ_WAVE_TRAPSTS__BUFFER_OOB__SHIFT 0xf |
42776 | #define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 |
42777 | #define SQ_WAVE_TRAPSTS__EXCP_GROUP_MASK__SHIFT 0x14 |
42778 | #define SQ_WAVE_TRAPSTS__EXCP_WAVE64HI__SHIFT 0x18 |
42779 | #define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c |
42780 | #define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d |
42781 | #define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL |
42782 | #define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L |
42783 | #define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L |
42784 | #define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L |
42785 | #define SQ_WAVE_TRAPSTS__BUFFER_OOB_MASK 0x00008000L |
42786 | #define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x000F0000L |
42787 | #define SQ_WAVE_TRAPSTS__EXCP_GROUP_MASK_MASK 0x00F00000L |
42788 | #define SQ_WAVE_TRAPSTS__EXCP_WAVE64HI_MASK 0x01000000L |
42789 | #define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L |
42790 | #define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L |
42791 | //SQ_WAVE_HW_ID_LEGACY |
42792 | #define SQ_WAVE_HW_ID_LEGACY__WAVE_ID__SHIFT 0x0 |
42793 | #define SQ_WAVE_HW_ID_LEGACY__SIMD_ID__SHIFT 0x4 |
42794 | #define SQ_WAVE_HW_ID_LEGACY__PIPE_ID__SHIFT 0x6 |
42795 | #define SQ_WAVE_HW_ID_LEGACY__CU_ID__SHIFT 0x8 |
42796 | #define SQ_WAVE_HW_ID_LEGACY__SH_ID__SHIFT 0xc |
42797 | #define SQ_WAVE_HW_ID_LEGACY__SE_ID__SHIFT 0xd |
42798 | #define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MSB__SHIFT 0xf |
42799 | #define SQ_WAVE_HW_ID_LEGACY__TG_ID__SHIFT 0x10 |
42800 | #define SQ_WAVE_HW_ID_LEGACY__VM_ID__SHIFT 0x14 |
42801 | #define SQ_WAVE_HW_ID_LEGACY__QUEUE_ID__SHIFT 0x18 |
42802 | #define SQ_WAVE_HW_ID_LEGACY__STATE_ID__SHIFT 0x1b |
42803 | #define SQ_WAVE_HW_ID_LEGACY__ME_ID__SHIFT 0x1e |
42804 | #define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MASK 0x0000000FL |
42805 | #define SQ_WAVE_HW_ID_LEGACY__SIMD_ID_MASK 0x00000030L |
42806 | #define SQ_WAVE_HW_ID_LEGACY__PIPE_ID_MASK 0x000000C0L |
42807 | #define SQ_WAVE_HW_ID_LEGACY__CU_ID_MASK 0x00000F00L |
42808 | #define SQ_WAVE_HW_ID_LEGACY__SH_ID_MASK 0x00001000L |
42809 | #define SQ_WAVE_HW_ID_LEGACY__SE_ID_MASK 0x00006000L |
42810 | #define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MSB_MASK 0x00008000L |
42811 | #define SQ_WAVE_HW_ID_LEGACY__TG_ID_MASK 0x000F0000L |
42812 | #define SQ_WAVE_HW_ID_LEGACY__VM_ID_MASK 0x00F00000L |
42813 | #define SQ_WAVE_HW_ID_LEGACY__QUEUE_ID_MASK 0x07000000L |
42814 | #define SQ_WAVE_HW_ID_LEGACY__STATE_ID_MASK 0x38000000L |
42815 | #define SQ_WAVE_HW_ID_LEGACY__ME_ID_MASK 0xC0000000L |
42816 | //SQ_WAVE_GPR_ALLOC |
42817 | #define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 |
42818 | #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8 |
42819 | #define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10 |
42820 | #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 |
42821 | #define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x000000FFL |
42822 | #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x0000FF00L |
42823 | #define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x00FF0000L |
42824 | #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L |
42825 | //SQ_WAVE_LDS_ALLOC |
42826 | #define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 |
42827 | #define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc |
42828 | #define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE__SHIFT 0x18 |
42829 | #define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000001FFL |
42830 | #define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L |
42831 | #define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE_MASK 0x0F000000L |
42832 | //SQ_WAVE_IB_STS |
42833 | #define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 |
42834 | #define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 |
42835 | #define SQ_WAVE_IB_STS__LGKM_CNT_BIT4__SHIFT 0x7 |
42836 | #define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 |
42837 | #define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc |
42838 | #define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf |
42839 | #define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10 |
42840 | #define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16 |
42841 | #define SQ_WAVE_IB_STS__LGKM_CNT_BIT5__SHIFT 0x18 |
42842 | #define SQ_WAVE_IB_STS__REPLAY_W64H__SHIFT 0x19 |
42843 | #define SQ_WAVE_IB_STS__VS_CNT__SHIFT 0x1a |
42844 | #define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL |
42845 | #define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L |
42846 | #define SQ_WAVE_IB_STS__LGKM_CNT_BIT4_MASK 0x00000080L |
42847 | #define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L |
42848 | #define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L |
42849 | #define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L |
42850 | #define SQ_WAVE_IB_STS__RCNT_MASK 0x003F0000L |
42851 | #define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L |
42852 | #define SQ_WAVE_IB_STS__LGKM_CNT_BIT5_MASK 0x01000000L |
42853 | #define SQ_WAVE_IB_STS__REPLAY_W64H_MASK 0x02000000L |
42854 | #define SQ_WAVE_IB_STS__VS_CNT_MASK 0xFC000000L |
42855 | //SQ_WAVE_PC_LO |
42856 | #define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 |
42857 | #define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL |
42858 | //SQ_WAVE_PC_HI |
42859 | #define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 |
42860 | #define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL |
42861 | //SQ_WAVE_INST_DW0 |
42862 | #define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 |
42863 | #define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL |
42864 | //SQ_WAVE_IB_DBG1 |
42865 | #define SQ_WAVE_IB_DBG1__XNACK_ERROR__SHIFT 0x0 |
42866 | #define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1 |
42867 | #define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2 |
42868 | #define SQ_WAVE_IB_DBG1__XNACK_OVERRIDE__SHIFT 0x3 |
42869 | #define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4 |
42870 | #define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb |
42871 | #define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12 |
42872 | #define SQ_WAVE_IB_DBG1__WAVE_IDLE__SHIFT 0x18 |
42873 | #define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19 |
42874 | #define SQ_WAVE_IB_DBG1__XNACK_ERROR_MASK 0x00000001L |
42875 | #define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L |
42876 | #define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L |
42877 | #define SQ_WAVE_IB_DBG1__XNACK_OVERRIDE_MASK 0x00000008L |
42878 | #define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000003F0L |
42879 | #define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0001F800L |
42880 | #define SQ_WAVE_IB_DBG1__RCNT_MASK 0x00FC0000L |
42881 | #define SQ_WAVE_IB_DBG1__WAVE_IDLE_MASK 0x01000000L |
42882 | #define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L |
42883 | //SQ_WAVE_FLUSH_IB |
42884 | #define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0 |
42885 | #define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL |
42886 | //SQ_WAVE_HW_ID1 |
42887 | #define SQ_WAVE_HW_ID1__WAVE_ID__SHIFT 0x0 |
42888 | #define SQ_WAVE_HW_ID1__SIMD_ID__SHIFT 0x8 |
42889 | #define SQ_WAVE_HW_ID1__WGP_ID__SHIFT 0xa |
42890 | #define SQ_WAVE_HW_ID1__SA_ID__SHIFT 0x10 |
42891 | #define SQ_WAVE_HW_ID1__SE_ID__SHIFT 0x12 |
42892 | #define SQ_WAVE_HW_ID1__WAVE_ID_MASK 0x0000001FL |
42893 | #define SQ_WAVE_HW_ID1__SIMD_ID_MASK 0x00000300L |
42894 | #define SQ_WAVE_HW_ID1__WGP_ID_MASK 0x00003C00L |
42895 | #define SQ_WAVE_HW_ID1__SA_ID_MASK 0x00010000L |
42896 | #define SQ_WAVE_HW_ID1__SE_ID_MASK 0x000C0000L |
42897 | //SQ_WAVE_HW_ID2 |
42898 | #define SQ_WAVE_HW_ID2__QUEUE_ID__SHIFT 0x0 |
42899 | #define SQ_WAVE_HW_ID2__PIPE_ID__SHIFT 0x4 |
42900 | #define SQ_WAVE_HW_ID2__ME_ID__SHIFT 0x8 |
42901 | #define SQ_WAVE_HW_ID2__STATE_ID__SHIFT 0xc |
42902 | #define SQ_WAVE_HW_ID2__WG_ID__SHIFT 0x10 |
42903 | #define SQ_WAVE_HW_ID2__VM_ID__SHIFT 0x18 |
42904 | #define SQ_WAVE_HW_ID2__COMPAT_LEVEL__SHIFT 0x1d |
42905 | #define SQ_WAVE_HW_ID2__QUEUE_ID_MASK 0x0000000FL |
42906 | #define SQ_WAVE_HW_ID2__PIPE_ID_MASK 0x00000030L |
42907 | #define SQ_WAVE_HW_ID2__ME_ID_MASK 0x00000300L |
42908 | #define SQ_WAVE_HW_ID2__STATE_ID_MASK 0x00007000L |
42909 | #define SQ_WAVE_HW_ID2__WG_ID_MASK 0x001F0000L |
42910 | #define SQ_WAVE_HW_ID2__VM_ID_MASK 0x0F000000L |
42911 | #define SQ_WAVE_HW_ID2__COMPAT_LEVEL_MASK 0x60000000L |
42912 | //SQ_WAVE_POPS_PACKER |
42913 | #define SQ_WAVE_POPS_PACKER__POPS_EN__SHIFT 0x0 |
42914 | #define SQ_WAVE_POPS_PACKER__POPS_PACKER_ID__SHIFT 0x1 |
42915 | #define SQ_WAVE_POPS_PACKER__POPS_EN_MASK 0x00000001L |
42916 | #define SQ_WAVE_POPS_PACKER__POPS_PACKER_ID_MASK 0x00000006L |
42917 | //SQ_WAVE_SCHED_MODE |
42918 | #define SQ_WAVE_SCHED_MODE__DEP_MODE__SHIFT 0x0 |
42919 | #define SQ_WAVE_SCHED_MODE__DEP_MODE_MASK 0x00000003L |
42920 | //SQ_WAVE_VGPR_OFFSET |
42921 | #define SQ_WAVE_VGPR_OFFSET__SRC0__SHIFT 0x0 |
42922 | #define SQ_WAVE_VGPR_OFFSET__SRC1__SHIFT 0x6 |
42923 | #define SQ_WAVE_VGPR_OFFSET__SRC2__SHIFT 0xc |
42924 | #define SQ_WAVE_VGPR_OFFSET__DST__SHIFT 0x12 |
42925 | #define SQ_WAVE_VGPR_OFFSET__SRC0_MASK 0x0000003FL |
42926 | #define SQ_WAVE_VGPR_OFFSET__SRC1_MASK 0x00000FC0L |
42927 | #define SQ_WAVE_VGPR_OFFSET__SRC2_MASK 0x0003F000L |
42928 | #define SQ_WAVE_VGPR_OFFSET__DST_MASK 0x00FC0000L |
42929 | //SQ_WAVE_IB_STS2 |
42930 | #define SQ_WAVE_IB_STS2__INST_PREFETCH__SHIFT 0x0 |
42931 | #define SQ_WAVE_IB_STS2__RESOURCE_OVERRIDE__SHIFT 0x7 |
42932 | #define SQ_WAVE_IB_STS2__MEM_ORDER__SHIFT 0x8 |
42933 | #define SQ_WAVE_IB_STS2__FWD_PROGRESS__SHIFT 0xa |
42934 | #define SQ_WAVE_IB_STS2__WAVE64__SHIFT 0xb |
42935 | #define SQ_WAVE_IB_STS2__WAVE64HI__SHIFT 0xc |
42936 | #define SQ_WAVE_IB_STS2__SUBV_LOOP__SHIFT 0xd |
42937 | #define SQ_WAVE_IB_STS2__INST_PREFETCH_MASK 0x00000003L |
42938 | #define SQ_WAVE_IB_STS2__RESOURCE_OVERRIDE_MASK 0x00000080L |
42939 | #define SQ_WAVE_IB_STS2__MEM_ORDER_MASK 0x00000300L |
42940 | #define SQ_WAVE_IB_STS2__FWD_PROGRESS_MASK 0x00000400L |
42941 | #define SQ_WAVE_IB_STS2__WAVE64_MASK 0x00000800L |
42942 | #define SQ_WAVE_IB_STS2__WAVE64HI_MASK 0x00001000L |
42943 | #define SQ_WAVE_IB_STS2__SUBV_LOOP_MASK 0x00002000L |
42944 | //SQ_WAVE_TTMP0 |
42945 | #define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 |
42946 | #define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL |
42947 | //SQ_WAVE_TTMP1 |
42948 | #define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 |
42949 | #define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL |
42950 | //SQ_WAVE_TTMP2 |
42951 | #define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 |
42952 | #define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL |
42953 | //SQ_WAVE_TTMP3 |
42954 | #define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 |
42955 | #define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL |
42956 | //SQ_WAVE_TTMP4 |
42957 | #define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 |
42958 | #define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL |
42959 | //SQ_WAVE_TTMP5 |
42960 | #define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 |
42961 | #define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL |
42962 | //SQ_WAVE_TTMP6 |
42963 | #define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 |
42964 | #define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL |
42965 | //SQ_WAVE_TTMP7 |
42966 | #define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 |
42967 | #define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL |
42968 | //SQ_WAVE_TTMP8 |
42969 | #define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 |
42970 | #define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL |
42971 | //SQ_WAVE_TTMP9 |
42972 | #define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 |
42973 | #define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL |
42974 | //SQ_WAVE_TTMP10 |
42975 | #define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 |
42976 | #define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL |
42977 | //SQ_WAVE_TTMP11 |
42978 | #define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 |
42979 | #define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL |
42980 | //SQ_WAVE_TTMP12 |
42981 | #define SQ_WAVE_TTMP12__DATA__SHIFT 0x0 |
42982 | #define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL |
42983 | //SQ_WAVE_TTMP13 |
42984 | #define SQ_WAVE_TTMP13__DATA__SHIFT 0x0 |
42985 | #define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL |
42986 | //SQ_WAVE_TTMP14 |
42987 | #define SQ_WAVE_TTMP14__DATA__SHIFT 0x0 |
42988 | #define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL |
42989 | //SQ_WAVE_TTMP15 |
42990 | #define SQ_WAVE_TTMP15__DATA__SHIFT 0x0 |
42991 | #define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL |
42992 | //SQ_WAVE_M0 |
42993 | #define SQ_WAVE_M0__M0__SHIFT 0x0 |
42994 | #define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL |
42995 | //SQ_WAVE_EXEC_LO |
42996 | #define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 |
42997 | #define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL |
42998 | //SQ_WAVE_EXEC_HI |
42999 | #define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 |
43000 | #define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL |
43001 | //SQ_WAVE_FLAT_SCRATCH_LO |
43002 | #define SQ_WAVE_FLAT_SCRATCH_LO__DATA__SHIFT 0x0 |
43003 | #define SQ_WAVE_FLAT_SCRATCH_LO__DATA_MASK 0xFFFFFFFFL |
43004 | //SQ_WAVE_FLAT_SCRATCH_HI |
43005 | #define SQ_WAVE_FLAT_SCRATCH_HI__DATA__SHIFT 0x0 |
43006 | #define SQ_WAVE_FLAT_SCRATCH_HI__DATA_MASK 0xFFFFFFFFL |
43007 | //SQ_WAVE_FLAT_XNACK_MASK |
43008 | #define SQ_WAVE_FLAT_XNACK_MASK__MASK__SHIFT 0x0 |
43009 | #define SQ_WAVE_FLAT_XNACK_MASK__MASK_MASK 0xFFFFFFFFL |
43010 | //SQ_INTERRUPT_WORD_AUTO |
43011 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0 |
43012 | #define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1 |
43013 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF0_FULL__SHIFT 0x2 |
43014 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF1_FULL__SHIFT 0x3 |
43015 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 |
43016 | #define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x24 |
43017 | #define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x26 |
43018 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x0000000001L |
43019 | #define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x0000000002L |
43020 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF0_FULL_MASK 0x0000000004L |
43021 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF1_FULL_MASK 0x0000000008L |
43022 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_UTC_ERROR_MASK 0x0000000100L |
43023 | #define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000000L |
43024 | #define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xC000000000L |
43025 | //SQ_INTERRUPT_WORD_ERROR |
43026 | #define SQ_INTERRUPT_WORD_ERROR__ERR_DETAIL__SHIFT 0x0 |
43027 | #define SQ_INTERRUPT_WORD_ERROR__ERR_TYPE__SHIFT 0x13 |
43028 | #define SQ_INTERRUPT_WORD_ERROR__SA_ID__SHIFT 0x17 |
43029 | #define SQ_INTERRUPT_WORD_ERROR__PRIV__SHIFT 0x18 |
43030 | #define SQ_INTERRUPT_WORD_ERROR__WAVE_ID__SHIFT 0x19 |
43031 | #define SQ_INTERRUPT_WORD_ERROR__SIMD_ID__SHIFT 0x1e |
43032 | #define SQ_INTERRUPT_WORD_ERROR__WGP_ID__SHIFT 0x20 |
43033 | #define SQ_INTERRUPT_WORD_ERROR__SE_ID__SHIFT 0x24 |
43034 | #define SQ_INTERRUPT_WORD_ERROR__ENCODING__SHIFT 0x26 |
43035 | #define SQ_INTERRUPT_WORD_ERROR__ERR_DETAIL_MASK 0x000007FFFFL |
43036 | #define SQ_INTERRUPT_WORD_ERROR__ERR_TYPE_MASK 0x0000780000L |
43037 | #define SQ_INTERRUPT_WORD_ERROR__SA_ID_MASK 0x0000800000L |
43038 | #define SQ_INTERRUPT_WORD_ERROR__PRIV_MASK 0x0001000000L |
43039 | #define SQ_INTERRUPT_WORD_ERROR__WAVE_ID_MASK 0x003E000000L |
43040 | #define SQ_INTERRUPT_WORD_ERROR__SIMD_ID_MASK 0x00C0000000L |
43041 | #define SQ_INTERRUPT_WORD_ERROR__WGP_ID_MASK 0x0F00000000L |
43042 | #define SQ_INTERRUPT_WORD_ERROR__SE_ID_MASK 0x3000000000L |
43043 | #define SQ_INTERRUPT_WORD_ERROR__ENCODING_MASK 0xC000000000L |
43044 | //SQ_INTERRUPT_WORD_WAVE |
43045 | #define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0 |
43046 | #define SQ_INTERRUPT_WORD_WAVE__SA_ID__SHIFT 0x17 |
43047 | #define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x18 |
43048 | #define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0x19 |
43049 | #define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x1e |
43050 | #define SQ_INTERRUPT_WORD_WAVE__WGP_ID__SHIFT 0x20 |
43051 | #define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x24 |
43052 | #define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x26 |
43053 | #define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0x00007FFFFFL |
43054 | #define SQ_INTERRUPT_WORD_WAVE__SA_ID_MASK 0x0000800000L |
43055 | #define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x0001000000L |
43056 | #define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x003E000000L |
43057 | #define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0x00C0000000L |
43058 | #define SQ_INTERRUPT_WORD_WAVE__WGP_ID_MASK 0x0F00000000L |
43059 | #define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000000L |
43060 | #define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xC000000000L |
43061 | |
43062 | |
43063 | |
43064 | |
43065 | |
43066 | |
43067 | // addressBlock: didtind |
43068 | //DIDT_SQ_CTRL0 |
43069 | #define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 |
43070 | #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1 |
43071 | #define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 |
43072 | #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 |
43073 | #define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 |
43074 | #define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 |
43075 | #define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 |
43076 | #define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 |
43077 | #define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 |
43078 | #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 |
43079 | #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a |
43080 | #define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b |
43081 | #define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c |
43082 | #define DIDT_SQ_CTRL0__DIDT_THROTTLE_MODE__SHIFT 0x1d |
43083 | #define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L |
43084 | #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L |
43085 | #define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L |
43086 | #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L |
43087 | #define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L |
43088 | #define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L |
43089 | #define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L |
43090 | #define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L |
43091 | #define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L |
43092 | #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L |
43093 | #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L |
43094 | #define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L |
43095 | #define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L |
43096 | #define DIDT_SQ_CTRL0__DIDT_THROTTLE_MODE_MASK 0x20000000L |
43097 | //DIDT_SQ_CTRL1 |
43098 | #define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 |
43099 | #define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 |
43100 | #define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL |
43101 | #define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L |
43102 | //DIDT_SQ_CTRL2 |
43103 | #define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 |
43104 | #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
43105 | #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
43106 | #define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL |
43107 | #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
43108 | #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
43109 | //DIDT_SQ_CTRL_OCP |
43110 | #define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x0 |
43111 | #define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK 0x0000FFFFL |
43112 | //DIDT_SQ_STALL_CTRL |
43113 | #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 |
43114 | #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 |
43115 | #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc |
43116 | #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 |
43117 | #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL |
43118 | #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L |
43119 | #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L |
43120 | #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L |
43121 | //DIDT_SQ_TUNING_CTRL |
43122 | #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 |
43123 | #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe |
43124 | #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL |
43125 | #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L |
43126 | //DIDT_SQ_STALL_AUTO_RELEASE_CTRL |
43127 | #define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 |
43128 | #define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL |
43129 | //DIDT_SQ_CTRL3 |
43130 | #define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 |
43131 | #define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 |
43132 | #define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2 |
43133 | #define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
43134 | #define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 |
43135 | #define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe |
43136 | #define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 |
43137 | #define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 |
43138 | #define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 |
43139 | #define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 |
43140 | #define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b |
43141 | #define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c |
43142 | #define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L |
43143 | #define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L |
43144 | #define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL |
43145 | #define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
43146 | #define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L |
43147 | #define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L |
43148 | #define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L |
43149 | #define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L |
43150 | #define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L |
43151 | #define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L |
43152 | #define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L |
43153 | #define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L |
43154 | //DIDT_SQ_STALL_PATTERN_1_2 |
43155 | #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 |
43156 | #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 |
43157 | #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL |
43158 | #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L |
43159 | //DIDT_SQ_STALL_PATTERN_3_4 |
43160 | #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 |
43161 | #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 |
43162 | #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL |
43163 | #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L |
43164 | //DIDT_SQ_STALL_PATTERN_5_6 |
43165 | #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 |
43166 | #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 |
43167 | #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL |
43168 | #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L |
43169 | //DIDT_SQ_STALL_PATTERN_7 |
43170 | #define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 |
43171 | #define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL |
43172 | //DIDT_SQ_MPD_SCALE_FACTOR |
43173 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 |
43174 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 |
43175 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 |
43176 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc |
43177 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 |
43178 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 |
43179 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 |
43180 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c |
43181 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL |
43182 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L |
43183 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L |
43184 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L |
43185 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L |
43186 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L |
43187 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L |
43188 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L |
43189 | //DIDT_SQ_STALL_RELEASE_CNTL0 |
43190 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT 0x0 |
43191 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 |
43192 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 |
43193 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd |
43194 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK 0x00000001L |
43195 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L |
43196 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL |
43197 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L |
43198 | //DIDT_SQ_STALL_RELEASE_CNTL1 |
43199 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 |
43200 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 |
43201 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa |
43202 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf |
43203 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL |
43204 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L |
43205 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L |
43206 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L |
43207 | //DIDT_SQ_STALL_RELEASE_CNTL_STATUS |
43208 | #define DIDT_SQ_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT 0x0 |
43209 | #define DIDT_SQ_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK 0x00000003L |
43210 | //DIDT_SQ_WEIGHT0_3 |
43211 | #define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 |
43212 | #define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 |
43213 | #define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 |
43214 | #define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 |
43215 | #define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL |
43216 | #define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L |
43217 | #define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L |
43218 | #define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L |
43219 | //DIDT_SQ_WEIGHT4_7 |
43220 | #define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 |
43221 | #define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 |
43222 | #define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 |
43223 | #define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 |
43224 | #define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL |
43225 | #define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L |
43226 | #define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L |
43227 | #define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L |
43228 | //DIDT_SQ_WEIGHT8_11 |
43229 | #define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 |
43230 | #define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 |
43231 | #define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 |
43232 | #define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 |
43233 | #define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL |
43234 | #define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L |
43235 | #define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L |
43236 | #define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L |
43237 | //DIDT_SQ_EDC_CTRL |
43238 | #define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0 |
43239 | #define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
43240 | #define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
43241 | #define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
43242 | #define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
43243 | #define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 |
43244 | #define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 |
43245 | #define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 |
43246 | #define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 |
43247 | #define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 |
43248 | #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 |
43249 | #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 |
43250 | #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT 0x18 |
43251 | #define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L |
43252 | #define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
43253 | #define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
43254 | #define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
43255 | #define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
43256 | #define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L |
43257 | #define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L |
43258 | #define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L |
43259 | #define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L |
43260 | #define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L |
43261 | #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L |
43262 | #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L |
43263 | #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK 0x01000000L |
43264 | //DIDT_SQ_EDC_THRESHOLD |
43265 | #define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
43266 | #define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
43267 | //DIDT_SQ_EDC_STALL_PATTERN_1_2 |
43268 | #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 |
43269 | #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 |
43270 | #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL |
43271 | #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L |
43272 | //DIDT_SQ_EDC_STALL_PATTERN_3_4 |
43273 | #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 |
43274 | #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 |
43275 | #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL |
43276 | #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L |
43277 | //DIDT_SQ_EDC_STALL_PATTERN_5_6 |
43278 | #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 |
43279 | #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 |
43280 | #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL |
43281 | #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L |
43282 | //DIDT_SQ_EDC_STALL_PATTERN_7 |
43283 | #define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 |
43284 | #define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL |
43285 | //DIDT_SQ_EDC_TIMER_PERIOD |
43286 | #define DIDT_SQ_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT 0x0 |
43287 | #define DIDT_SQ_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK 0x00003FFFL |
43288 | //DIDT_SQ_THROTTLE_CTRL |
43289 | #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 |
43290 | #define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 |
43291 | #define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
43292 | #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 |
43293 | #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L |
43294 | #define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L |
43295 | #define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
43296 | #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L |
43297 | //DIDT_SQ_EDC_STALL_DELAY_1 |
43298 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0 |
43299 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x6 |
43300 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0xc |
43301 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x12 |
43302 | #define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 |
43303 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x0000003FL |
43304 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x00000FC0L |
43305 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x0003F000L |
43306 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0x00FC0000L |
43307 | #define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L |
43308 | //DIDT_SQ_EDC_STALL_DELAY_2 |
43309 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0 |
43310 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x6 |
43311 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0xc |
43312 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x12 |
43313 | #define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 |
43314 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x0000003FL |
43315 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x00000FC0L |
43316 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x0003F000L |
43317 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0x00FC0000L |
43318 | #define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L |
43319 | //DIDT_SQ_EDC_STALL_DELAY_3 |
43320 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x0 |
43321 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x6 |
43322 | #define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED__SHIFT 0xc |
43323 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x0000003FL |
43324 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x00000FC0L |
43325 | #define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFFF000L |
43326 | //DIDT_SQ_EDC_STATUS |
43327 | #define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 |
43328 | #define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 |
43329 | #define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L |
43330 | #define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL |
43331 | //DIDT_SQ_EDC_OVERFLOW |
43332 | #define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
43333 | #define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
43334 | #define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
43335 | #define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
43336 | //DIDT_SQ_EDC_ROLLING_POWER_DELTA |
43337 | #define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
43338 | #define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
43339 | //DIDT_SQ_EDC_PCC_PERF_COUNTER |
43340 | #define DIDT_SQ_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT 0x0 |
43341 | #define DIDT_SQ_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK 0xFFFFFFFFL |
43342 | //DIDT_DB_CTRL0 |
43343 | #define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 |
43344 | #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1 |
43345 | #define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 |
43346 | #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 |
43347 | #define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 |
43348 | #define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 |
43349 | #define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 |
43350 | #define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 |
43351 | #define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 |
43352 | #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 |
43353 | #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a |
43354 | #define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b |
43355 | #define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c |
43356 | #define DIDT_DB_CTRL0__DIDT_THROTTLE_MODE__SHIFT 0x1d |
43357 | #define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L |
43358 | #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L |
43359 | #define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L |
43360 | #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L |
43361 | #define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L |
43362 | #define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L |
43363 | #define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L |
43364 | #define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L |
43365 | #define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L |
43366 | #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L |
43367 | #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L |
43368 | #define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L |
43369 | #define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L |
43370 | #define DIDT_DB_CTRL0__DIDT_THROTTLE_MODE_MASK 0x20000000L |
43371 | //DIDT_DB_CTRL1 |
43372 | #define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 |
43373 | #define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 |
43374 | #define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL |
43375 | #define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L |
43376 | //DIDT_DB_CTRL2 |
43377 | #define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 |
43378 | #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
43379 | #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
43380 | #define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL |
43381 | #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
43382 | #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
43383 | //DIDT_DB_CTRL_OCP |
43384 | #define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x0 |
43385 | #define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK 0x0000FFFFL |
43386 | //DIDT_DB_STALL_CTRL |
43387 | #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 |
43388 | #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 |
43389 | #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc |
43390 | #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 |
43391 | #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL |
43392 | #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L |
43393 | #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L |
43394 | #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L |
43395 | //DIDT_DB_TUNING_CTRL |
43396 | #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 |
43397 | #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe |
43398 | #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL |
43399 | #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L |
43400 | //DIDT_DB_STALL_AUTO_RELEASE_CTRL |
43401 | #define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 |
43402 | #define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL |
43403 | //DIDT_DB_CTRL3 |
43404 | #define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 |
43405 | #define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 |
43406 | #define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2 |
43407 | #define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
43408 | #define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 |
43409 | #define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe |
43410 | #define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 |
43411 | #define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 |
43412 | #define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 |
43413 | #define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 |
43414 | #define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b |
43415 | #define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c |
43416 | #define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L |
43417 | #define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L |
43418 | #define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL |
43419 | #define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
43420 | #define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L |
43421 | #define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L |
43422 | #define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L |
43423 | #define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L |
43424 | #define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L |
43425 | #define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L |
43426 | #define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L |
43427 | #define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L |
43428 | //DIDT_DB_STALL_PATTERN_1_2 |
43429 | #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 |
43430 | #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 |
43431 | #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL |
43432 | #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L |
43433 | //DIDT_DB_STALL_PATTERN_3_4 |
43434 | #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 |
43435 | #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 |
43436 | #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL |
43437 | #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L |
43438 | //DIDT_DB_STALL_PATTERN_5_6 |
43439 | #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 |
43440 | #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 |
43441 | #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL |
43442 | #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L |
43443 | //DIDT_DB_STALL_PATTERN_7 |
43444 | #define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 |
43445 | #define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL |
43446 | //DIDT_DB_MPD_SCALE_FACTOR |
43447 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 |
43448 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 |
43449 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 |
43450 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc |
43451 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 |
43452 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 |
43453 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 |
43454 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c |
43455 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL |
43456 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L |
43457 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L |
43458 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L |
43459 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L |
43460 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L |
43461 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L |
43462 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L |
43463 | //DIDT_DB_STALL_RELEASE_CNTL0 |
43464 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT 0x0 |
43465 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 |
43466 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 |
43467 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd |
43468 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK 0x00000001L |
43469 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L |
43470 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL |
43471 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L |
43472 | //DIDT_DB_STALL_RELEASE_CNTL1 |
43473 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 |
43474 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 |
43475 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa |
43476 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf |
43477 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL |
43478 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L |
43479 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L |
43480 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L |
43481 | //DIDT_DB_STALL_RELEASE_CNTL_STATUS |
43482 | #define DIDT_DB_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT 0x0 |
43483 | #define DIDT_DB_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK 0x00000003L |
43484 | //DIDT_DB_WEIGHT0_3 |
43485 | #define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 |
43486 | #define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 |
43487 | #define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 |
43488 | #define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 |
43489 | #define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL |
43490 | #define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L |
43491 | #define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L |
43492 | #define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L |
43493 | //DIDT_DB_WEIGHT4_7 |
43494 | #define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 |
43495 | #define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 |
43496 | #define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 |
43497 | #define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 |
43498 | #define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL |
43499 | #define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L |
43500 | #define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L |
43501 | #define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L |
43502 | //DIDT_DB_WEIGHT8_11 |
43503 | #define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 |
43504 | #define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 |
43505 | #define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 |
43506 | #define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 |
43507 | #define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL |
43508 | #define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L |
43509 | #define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L |
43510 | #define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L |
43511 | //DIDT_DB_EDC_CTRL |
43512 | #define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0 |
43513 | #define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
43514 | #define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
43515 | #define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
43516 | #define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
43517 | #define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 |
43518 | #define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 |
43519 | #define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 |
43520 | #define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 |
43521 | #define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 |
43522 | #define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 |
43523 | #define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 |
43524 | #define DIDT_DB_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT 0x18 |
43525 | #define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L |
43526 | #define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
43527 | #define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
43528 | #define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
43529 | #define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
43530 | #define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L |
43531 | #define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L |
43532 | #define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L |
43533 | #define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L |
43534 | #define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L |
43535 | #define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L |
43536 | #define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L |
43537 | #define DIDT_DB_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK 0x01000000L |
43538 | //DIDT_DB_EDC_THRESHOLD |
43539 | #define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
43540 | #define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
43541 | //DIDT_DB_EDC_STALL_PATTERN_1_2 |
43542 | #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 |
43543 | #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 |
43544 | #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL |
43545 | #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L |
43546 | //DIDT_DB_EDC_STALL_PATTERN_3_4 |
43547 | #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 |
43548 | #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 |
43549 | #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL |
43550 | #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L |
43551 | //DIDT_DB_EDC_STALL_PATTERN_5_6 |
43552 | #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 |
43553 | #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 |
43554 | #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL |
43555 | #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L |
43556 | //DIDT_DB_EDC_STALL_PATTERN_7 |
43557 | #define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 |
43558 | #define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL |
43559 | //DIDT_DB_EDC_TIMER_PERIOD |
43560 | #define DIDT_DB_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT 0x0 |
43561 | #define DIDT_DB_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK 0x00003FFFL |
43562 | //DIDT_DB_THROTTLE_CTRL |
43563 | #define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 |
43564 | #define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 |
43565 | #define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
43566 | #define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 |
43567 | #define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L |
43568 | #define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L |
43569 | #define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
43570 | #define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L |
43571 | //DIDT_DB_EDC_STALL_DELAY_1 |
43572 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0 |
43573 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x5 |
43574 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2__SHIFT 0xa |
43575 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3__SHIFT 0xf |
43576 | #define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x14 |
43577 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x0000001FL |
43578 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x000003E0L |
43579 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB2_MASK 0x00007C00L |
43580 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB3_MASK 0x000F8000L |
43581 | #define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFF00000L |
43582 | //DIDT_DB_EDC_STATUS |
43583 | #define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 |
43584 | #define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 |
43585 | #define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L |
43586 | #define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL |
43587 | //DIDT_DB_EDC_OVERFLOW |
43588 | #define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
43589 | #define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
43590 | #define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
43591 | #define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
43592 | //DIDT_DB_EDC_ROLLING_POWER_DELTA |
43593 | #define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
43594 | #define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
43595 | //DIDT_DB_EDC_PCC_PERF_COUNTER |
43596 | #define DIDT_DB_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT 0x0 |
43597 | #define DIDT_DB_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK 0xFFFFFFFFL |
43598 | //DIDT_TD_CTRL0 |
43599 | #define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 |
43600 | #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1 |
43601 | #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 |
43602 | #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 |
43603 | #define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 |
43604 | #define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 |
43605 | #define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 |
43606 | #define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 |
43607 | #define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 |
43608 | #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 |
43609 | #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a |
43610 | #define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b |
43611 | #define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c |
43612 | #define DIDT_TD_CTRL0__DIDT_THROTTLE_MODE__SHIFT 0x1d |
43613 | #define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L |
43614 | #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L |
43615 | #define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L |
43616 | #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L |
43617 | #define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L |
43618 | #define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L |
43619 | #define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L |
43620 | #define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L |
43621 | #define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L |
43622 | #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L |
43623 | #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L |
43624 | #define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L |
43625 | #define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L |
43626 | #define DIDT_TD_CTRL0__DIDT_THROTTLE_MODE_MASK 0x20000000L |
43627 | //DIDT_TD_CTRL1 |
43628 | #define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 |
43629 | #define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 |
43630 | #define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL |
43631 | #define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L |
43632 | //DIDT_TD_CTRL2 |
43633 | #define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 |
43634 | #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
43635 | #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
43636 | #define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL |
43637 | #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
43638 | #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
43639 | //DIDT_TD_CTRL_OCP |
43640 | #define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x0 |
43641 | #define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK 0x0000FFFFL |
43642 | //DIDT_TD_STALL_CTRL |
43643 | #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 |
43644 | #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 |
43645 | #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc |
43646 | #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 |
43647 | #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL |
43648 | #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L |
43649 | #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L |
43650 | #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L |
43651 | //DIDT_TD_TUNING_CTRL |
43652 | #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 |
43653 | #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe |
43654 | #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL |
43655 | #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L |
43656 | //DIDT_TD_STALL_AUTO_RELEASE_CTRL |
43657 | #define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 |
43658 | #define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL |
43659 | //DIDT_TD_CTRL3 |
43660 | #define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 |
43661 | #define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 |
43662 | #define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2 |
43663 | #define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
43664 | #define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 |
43665 | #define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe |
43666 | #define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 |
43667 | #define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 |
43668 | #define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 |
43669 | #define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 |
43670 | #define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b |
43671 | #define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c |
43672 | #define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L |
43673 | #define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L |
43674 | #define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL |
43675 | #define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
43676 | #define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L |
43677 | #define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L |
43678 | #define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L |
43679 | #define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L |
43680 | #define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L |
43681 | #define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L |
43682 | #define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L |
43683 | #define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L |
43684 | //DIDT_TD_STALL_PATTERN_1_2 |
43685 | #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 |
43686 | #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 |
43687 | #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL |
43688 | #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L |
43689 | //DIDT_TD_STALL_PATTERN_3_4 |
43690 | #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 |
43691 | #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 |
43692 | #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL |
43693 | #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L |
43694 | //DIDT_TD_STALL_PATTERN_5_6 |
43695 | #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 |
43696 | #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 |
43697 | #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL |
43698 | #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L |
43699 | //DIDT_TD_STALL_PATTERN_7 |
43700 | #define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 |
43701 | #define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL |
43702 | //DIDT_TD_MPD_SCALE_FACTOR |
43703 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 |
43704 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 |
43705 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 |
43706 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc |
43707 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 |
43708 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 |
43709 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 |
43710 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c |
43711 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL |
43712 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L |
43713 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L |
43714 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L |
43715 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L |
43716 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L |
43717 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L |
43718 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L |
43719 | //DIDT_TD_STALL_RELEASE_CNTL0 |
43720 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT 0x0 |
43721 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 |
43722 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 |
43723 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd |
43724 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK 0x00000001L |
43725 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L |
43726 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL |
43727 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L |
43728 | //DIDT_TD_STALL_RELEASE_CNTL1 |
43729 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 |
43730 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 |
43731 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa |
43732 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf |
43733 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL |
43734 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L |
43735 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L |
43736 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L |
43737 | //DIDT_TD_STALL_RELEASE_CNTL_STATUS |
43738 | #define DIDT_TD_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT 0x0 |
43739 | #define DIDT_TD_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK 0x00000003L |
43740 | //DIDT_TD_WEIGHT0_3 |
43741 | #define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 |
43742 | #define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 |
43743 | #define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 |
43744 | #define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 |
43745 | #define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL |
43746 | #define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L |
43747 | #define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L |
43748 | #define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L |
43749 | //DIDT_TD_WEIGHT4_7 |
43750 | #define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 |
43751 | #define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 |
43752 | #define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 |
43753 | #define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 |
43754 | #define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL |
43755 | #define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L |
43756 | #define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L |
43757 | #define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L |
43758 | //DIDT_TD_WEIGHT8_11 |
43759 | #define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 |
43760 | #define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 |
43761 | #define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 |
43762 | #define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 |
43763 | #define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL |
43764 | #define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L |
43765 | #define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L |
43766 | #define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L |
43767 | //DIDT_TD_EDC_CTRL |
43768 | #define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0 |
43769 | #define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
43770 | #define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
43771 | #define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
43772 | #define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
43773 | #define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 |
43774 | #define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 |
43775 | #define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 |
43776 | #define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 |
43777 | #define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 |
43778 | #define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 |
43779 | #define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 |
43780 | #define DIDT_TD_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT 0x18 |
43781 | #define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L |
43782 | #define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
43783 | #define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
43784 | #define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
43785 | #define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
43786 | #define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L |
43787 | #define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L |
43788 | #define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L |
43789 | #define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L |
43790 | #define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L |
43791 | #define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L |
43792 | #define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L |
43793 | #define DIDT_TD_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK 0x01000000L |
43794 | //DIDT_TD_EDC_THRESHOLD |
43795 | #define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
43796 | #define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
43797 | //DIDT_TD_EDC_STALL_PATTERN_1_2 |
43798 | #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 |
43799 | #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 |
43800 | #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL |
43801 | #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L |
43802 | //DIDT_TD_EDC_STALL_PATTERN_3_4 |
43803 | #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 |
43804 | #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 |
43805 | #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL |
43806 | #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L |
43807 | //DIDT_TD_EDC_STALL_PATTERN_5_6 |
43808 | #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 |
43809 | #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 |
43810 | #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL |
43811 | #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L |
43812 | //DIDT_TD_EDC_STALL_PATTERN_7 |
43813 | #define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 |
43814 | #define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL |
43815 | //DIDT_TD_EDC_TIMER_PERIOD |
43816 | #define DIDT_TD_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT 0x0 |
43817 | #define DIDT_TD_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK 0x00003FFFL |
43818 | //DIDT_TD_THROTTLE_CTRL |
43819 | #define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 |
43820 | #define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 |
43821 | #define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
43822 | #define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 |
43823 | #define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L |
43824 | #define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L |
43825 | #define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
43826 | #define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L |
43827 | //DIDT_TD_EDC_STALL_DELAY_1 |
43828 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0 |
43829 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x6 |
43830 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0xc |
43831 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x12 |
43832 | #define DIDT_TD_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 |
43833 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x0000003FL |
43834 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x00000FC0L |
43835 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x0003F000L |
43836 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0x00FC0000L |
43837 | #define DIDT_TD_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L |
43838 | //DIDT_TD_EDC_STALL_DELAY_2 |
43839 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0 |
43840 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x6 |
43841 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0xc |
43842 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x12 |
43843 | #define DIDT_TD_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 |
43844 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x0000003FL |
43845 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x00000FC0L |
43846 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x0003F000L |
43847 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0x00FC0000L |
43848 | #define DIDT_TD_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L |
43849 | //DIDT_TD_EDC_STALL_DELAY_3 |
43850 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x0 |
43851 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x6 |
43852 | #define DIDT_TD_EDC_STALL_DELAY_3__UNUSED__SHIFT 0xc |
43853 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x0000003FL |
43854 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x00000FC0L |
43855 | #define DIDT_TD_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFFF000L |
43856 | //DIDT_TD_EDC_STATUS |
43857 | #define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 |
43858 | #define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 |
43859 | #define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L |
43860 | #define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL |
43861 | //DIDT_TD_EDC_OVERFLOW |
43862 | #define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
43863 | #define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
43864 | #define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
43865 | #define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
43866 | //DIDT_TD_EDC_ROLLING_POWER_DELTA |
43867 | #define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
43868 | #define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
43869 | //DIDT_TD_EDC_PCC_PERF_COUNTER |
43870 | #define DIDT_TD_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT 0x0 |
43871 | #define DIDT_TD_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK 0xFFFFFFFFL |
43872 | //DIDT_TCP_CTRL0 |
43873 | #define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 |
43874 | #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1 |
43875 | #define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 |
43876 | #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 |
43877 | #define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 |
43878 | #define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 |
43879 | #define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 |
43880 | #define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 |
43881 | #define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 |
43882 | #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 |
43883 | #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a |
43884 | #define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b |
43885 | #define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c |
43886 | #define DIDT_TCP_CTRL0__DIDT_THROTTLE_MODE__SHIFT 0x1d |
43887 | #define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L |
43888 | #define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L |
43889 | #define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L |
43890 | #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L |
43891 | #define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L |
43892 | #define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L |
43893 | #define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L |
43894 | #define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L |
43895 | #define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L |
43896 | #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L |
43897 | #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L |
43898 | #define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L |
43899 | #define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L |
43900 | #define DIDT_TCP_CTRL0__DIDT_THROTTLE_MODE_MASK 0x20000000L |
43901 | //DIDT_TCP_CTRL1 |
43902 | #define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 |
43903 | #define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 |
43904 | #define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL |
43905 | #define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L |
43906 | //DIDT_TCP_CTRL2 |
43907 | #define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 |
43908 | #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
43909 | #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
43910 | #define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL |
43911 | #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
43912 | #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
43913 | //DIDT_TCP_CTRL_OCP |
43914 | #define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x0 |
43915 | #define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK 0x0000FFFFL |
43916 | //DIDT_TCP_STALL_CTRL |
43917 | #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 |
43918 | #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 |
43919 | #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc |
43920 | #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 |
43921 | #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL |
43922 | #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L |
43923 | #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L |
43924 | #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L |
43925 | //DIDT_TCP_TUNING_CTRL |
43926 | #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 |
43927 | #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe |
43928 | #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL |
43929 | #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L |
43930 | //DIDT_TCP_STALL_AUTO_RELEASE_CTRL |
43931 | #define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 |
43932 | #define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL |
43933 | //DIDT_TCP_CTRL3 |
43934 | #define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 |
43935 | #define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 |
43936 | #define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2 |
43937 | #define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
43938 | #define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 |
43939 | #define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe |
43940 | #define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 |
43941 | #define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 |
43942 | #define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 |
43943 | #define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 |
43944 | #define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b |
43945 | #define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c |
43946 | #define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L |
43947 | #define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L |
43948 | #define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL |
43949 | #define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
43950 | #define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L |
43951 | #define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L |
43952 | #define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L |
43953 | #define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L |
43954 | #define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L |
43955 | #define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L |
43956 | #define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L |
43957 | #define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L |
43958 | //DIDT_TCP_STALL_PATTERN_1_2 |
43959 | #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 |
43960 | #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 |
43961 | #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL |
43962 | #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L |
43963 | //DIDT_TCP_STALL_PATTERN_3_4 |
43964 | #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 |
43965 | #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 |
43966 | #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL |
43967 | #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L |
43968 | //DIDT_TCP_STALL_PATTERN_5_6 |
43969 | #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 |
43970 | #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 |
43971 | #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL |
43972 | #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L |
43973 | //DIDT_TCP_STALL_PATTERN_7 |
43974 | #define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 |
43975 | #define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL |
43976 | //DIDT_TCP_MPD_SCALE_FACTOR |
43977 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 |
43978 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 |
43979 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 |
43980 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc |
43981 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 |
43982 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 |
43983 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 |
43984 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c |
43985 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL |
43986 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L |
43987 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L |
43988 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L |
43989 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L |
43990 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L |
43991 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L |
43992 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L |
43993 | //DIDT_TCP_STALL_RELEASE_CNTL0 |
43994 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT 0x0 |
43995 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 |
43996 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 |
43997 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd |
43998 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK 0x00000001L |
43999 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L |
44000 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL |
44001 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L |
44002 | //DIDT_TCP_STALL_RELEASE_CNTL1 |
44003 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 |
44004 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 |
44005 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa |
44006 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf |
44007 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL |
44008 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L |
44009 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L |
44010 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L |
44011 | //DIDT_TCP_STALL_RELEASE_CNTL_STATUS |
44012 | #define DIDT_TCP_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT 0x0 |
44013 | #define DIDT_TCP_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK 0x00000003L |
44014 | //DIDT_TCP_WEIGHT0_3 |
44015 | #define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 |
44016 | #define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 |
44017 | #define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 |
44018 | #define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 |
44019 | #define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL |
44020 | #define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L |
44021 | #define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L |
44022 | #define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L |
44023 | //DIDT_TCP_WEIGHT4_7 |
44024 | #define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 |
44025 | #define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 |
44026 | #define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 |
44027 | #define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 |
44028 | #define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL |
44029 | #define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L |
44030 | #define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L |
44031 | #define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L |
44032 | //DIDT_TCP_WEIGHT8_11 |
44033 | #define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 |
44034 | #define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 |
44035 | #define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 |
44036 | #define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 |
44037 | #define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL |
44038 | #define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L |
44039 | #define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L |
44040 | #define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L |
44041 | //DIDT_TCP_EDC_CTRL |
44042 | #define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0 |
44043 | #define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
44044 | #define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
44045 | #define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
44046 | #define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
44047 | #define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 |
44048 | #define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 |
44049 | #define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 |
44050 | #define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 |
44051 | #define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 |
44052 | #define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 |
44053 | #define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 |
44054 | #define DIDT_TCP_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT 0x18 |
44055 | #define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L |
44056 | #define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
44057 | #define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
44058 | #define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
44059 | #define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
44060 | #define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L |
44061 | #define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L |
44062 | #define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L |
44063 | #define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L |
44064 | #define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L |
44065 | #define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L |
44066 | #define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L |
44067 | #define DIDT_TCP_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK 0x01000000L |
44068 | //DIDT_TCP_EDC_THRESHOLD |
44069 | #define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
44070 | #define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
44071 | //DIDT_TCP_EDC_STALL_PATTERN_1_2 |
44072 | #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 |
44073 | #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 |
44074 | #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL |
44075 | #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L |
44076 | //DIDT_TCP_EDC_STALL_PATTERN_3_4 |
44077 | #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 |
44078 | #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 |
44079 | #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL |
44080 | #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L |
44081 | //DIDT_TCP_EDC_STALL_PATTERN_5_6 |
44082 | #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 |
44083 | #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 |
44084 | #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL |
44085 | #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L |
44086 | //DIDT_TCP_EDC_STALL_PATTERN_7 |
44087 | #define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 |
44088 | #define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL |
44089 | //DIDT_TCP_EDC_TIMER_PERIOD |
44090 | #define DIDT_TCP_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT 0x0 |
44091 | #define DIDT_TCP_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK 0x00003FFFL |
44092 | //DIDT_TCP_THROTTLE_CTRL |
44093 | #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 |
44094 | #define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 |
44095 | #define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
44096 | #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 |
44097 | #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L |
44098 | #define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L |
44099 | #define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
44100 | #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L |
44101 | //DIDT_TCP_EDC_STALL_DELAY_1 |
44102 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0 |
44103 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x6 |
44104 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0xc |
44105 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x12 |
44106 | #define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 |
44107 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x0000003FL |
44108 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x00000FC0L |
44109 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x0003F000L |
44110 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0x00FC0000L |
44111 | #define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L |
44112 | //DIDT_TCP_EDC_STALL_DELAY_2 |
44113 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0 |
44114 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x6 |
44115 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0xc |
44116 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x12 |
44117 | #define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 |
44118 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x0000003FL |
44119 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x00000FC0L |
44120 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x0003F000L |
44121 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0x00FC0000L |
44122 | #define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L |
44123 | //DIDT_TCP_EDC_STALL_DELAY_3 |
44124 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x0 |
44125 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x6 |
44126 | #define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED__SHIFT 0xc |
44127 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x0000003FL |
44128 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x00000FC0L |
44129 | #define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFFF000L |
44130 | //DIDT_TCP_EDC_STATUS |
44131 | #define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 |
44132 | #define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 |
44133 | #define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L |
44134 | #define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL |
44135 | //DIDT_TCP_EDC_OVERFLOW |
44136 | #define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
44137 | #define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
44138 | #define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
44139 | #define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
44140 | //DIDT_TCP_EDC_ROLLING_POWER_DELTA |
44141 | #define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
44142 | #define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
44143 | //DIDT_TCP_EDC_PCC_PERF_COUNTER |
44144 | #define DIDT_TCP_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT 0x0 |
44145 | #define DIDT_TCP_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK 0xFFFFFFFFL |
44146 | //DIDT_SQ_STALL_EVENT_COUNTER |
44147 | #define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 |
44148 | #define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL |
44149 | //DIDT_DB_STALL_EVENT_COUNTER |
44150 | #define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 |
44151 | #define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL |
44152 | //DIDT_TD_STALL_EVENT_COUNTER |
44153 | #define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 |
44154 | #define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL |
44155 | //DIDT_TCP_STALL_EVENT_COUNTER |
44156 | #define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 |
44157 | #define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL |
44158 | |
44159 | |
44160 | |
44161 | |
44162 | |
44163 | |
44164 | |
44165 | #endif |
44166 | |