1 | /* |
2 | * Copyright (C) 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | */ |
21 | |
22 | #ifndef _gc_10_3_0_SH_MASK_HEADER |
23 | #define |
24 | |
25 | |
26 | // addressBlock: gc_sdma0_sdma0dec |
27 | //SDMA0_DEC_START |
28 | #define SDMA0_DEC_START__START__SHIFT 0x0 |
29 | #define SDMA0_DEC_START__START_MASK 0xFFFFFFFFL |
30 | //SDMA0_GLOBAL_TIMESTAMP_LO |
31 | #define SDMA0_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 |
32 | #define SDMA0_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL |
33 | //SDMA0_GLOBAL_TIMESTAMP_HI |
34 | #define SDMA0_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 |
35 | #define SDMA0_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL |
36 | //SDMA0_PG_CNTL |
37 | #define SDMA0_PG_CNTL__CMD__SHIFT 0x0 |
38 | #define SDMA0_PG_CNTL__STATUS__SHIFT 0x10 |
39 | #define SDMA0_PG_CNTL__CMD_MASK 0x0000000FL |
40 | #define SDMA0_PG_CNTL__STATUS_MASK 0x000F0000L |
41 | //SDMA0_PG_CTX_LO |
42 | #define SDMA0_PG_CTX_LO__ADDR__SHIFT 0x0 |
43 | #define SDMA0_PG_CTX_LO__ADDR_MASK 0xFFFFFFFFL |
44 | //SDMA0_PG_CTX_HI |
45 | #define SDMA0_PG_CTX_HI__ADDR__SHIFT 0x0 |
46 | #define SDMA0_PG_CTX_HI__ADDR_MASK 0xFFFFFFFFL |
47 | //SDMA0_PG_CTX_CNTL |
48 | #define SDMA0_PG_CTX_CNTL__VMID__SHIFT 0x0 |
49 | #define SDMA0_PG_CTX_CNTL__VMID_MASK 0x0000000FL |
50 | //SDMA0_POWER_CNTL |
51 | #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 |
52 | #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 |
53 | #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 |
54 | #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 |
55 | #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 |
56 | #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a |
57 | #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L |
58 | #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L |
59 | #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L |
60 | #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L |
61 | #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L |
62 | #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L |
63 | //SDMA0_CLK_CTRL |
64 | #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
65 | #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
66 | #define SDMA0_CLK_CTRL__RESERVED_24_12__SHIFT 0xc |
67 | #define SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE__SHIFT 0x19 |
68 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1a |
69 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1b |
70 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1c |
71 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1d |
72 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1e |
73 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG__SHIFT 0x1f |
74 | #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
75 | #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
76 | #define SDMA0_CLK_CTRL__RESERVED_24_12_MASK 0x01FFF000L |
77 | #define SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK 0x02000000L |
78 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x04000000L |
79 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x08000000L |
80 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x10000000L |
81 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x20000000L |
82 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x40000000L |
83 | #define SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK 0x80000000L |
84 | //SDMA0_CNTL |
85 | #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 |
86 | #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 |
87 | #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 |
88 | #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 |
89 | #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 |
90 | #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 |
91 | #define SDMA0_CNTL__PAGE_INT_ENABLE__SHIFT 0x7 |
92 | #define SDMA0_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10 |
93 | #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 |
94 | #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 |
95 | #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c |
96 | #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d |
97 | #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e |
98 | #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L |
99 | #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L |
100 | #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L |
101 | #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L |
102 | #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L |
103 | #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L |
104 | #define SDMA0_CNTL__PAGE_INT_ENABLE_MASK 0x00000080L |
105 | #define SDMA0_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L |
106 | #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L |
107 | #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L |
108 | #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L |
109 | #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L |
110 | #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L |
111 | //SDMA0_CHICKEN_BITS |
112 | #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 |
113 | #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 |
114 | #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 |
115 | #define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_DCGE__SHIFT 0x4 |
116 | #define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG__SHIFT 0x5 |
117 | #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 |
118 | #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa |
119 | #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 |
120 | #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 |
121 | #define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 |
122 | #define SDMA0_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT 0x13 |
123 | #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 |
124 | #define SDMA0_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT 0x15 |
125 | #define SDMA0_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE__SHIFT 0x16 |
126 | #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 |
127 | #define SDMA0_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT 0x18 |
128 | #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 |
129 | #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a |
130 | #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c |
131 | #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e |
132 | #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L |
133 | #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L |
134 | #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L |
135 | #define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_DCGE_MASK 0x00000010L |
136 | #define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG_MASK 0x00000020L |
137 | #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L |
138 | #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L |
139 | #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L |
140 | #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L |
141 | #define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L |
142 | #define SDMA0_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK 0x00080000L |
143 | #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L |
144 | #define SDMA0_CHICKEN_BITS__CH_FGCG_ENABLE_MASK 0x00200000L |
145 | #define SDMA0_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE_MASK 0x00400000L |
146 | #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L |
147 | #define SDMA0_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK 0x01000000L |
148 | #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L |
149 | #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L |
150 | #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L |
151 | #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L |
152 | //SDMA0_GB_ADDR_CONFIG |
153 | #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
154 | #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
155 | #define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
156 | #define SDMA0_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 |
157 | #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
158 | #define SDMA0_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a |
159 | #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
160 | #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
161 | #define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
162 | #define SDMA0_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L |
163 | #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
164 | #define SDMA0_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L |
165 | //SDMA0_GB_ADDR_CONFIG_READ |
166 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 |
167 | #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
168 | #define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
169 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 |
170 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 |
171 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a |
172 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L |
173 | #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
174 | #define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
175 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L |
176 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L |
177 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L |
178 | //SDMA0_RB_RPTR_FETCH_HI |
179 | #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 |
180 | #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL |
181 | //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL |
182 | #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 |
183 | #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL |
184 | //SDMA0_RB_RPTR_FETCH |
185 | #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 |
186 | #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL |
187 | //SDMA0_IB_OFFSET_FETCH |
188 | #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 |
189 | #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL |
190 | //SDMA0_PROGRAM |
191 | #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 |
192 | #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL |
193 | //SDMA0_STATUS_REG |
194 | #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 |
195 | #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 |
196 | #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 |
197 | #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 |
198 | #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 |
199 | #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 |
200 | #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 |
201 | #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 |
202 | #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 |
203 | #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 |
204 | #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa |
205 | #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb |
206 | #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc |
207 | #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd |
208 | #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe |
209 | #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf |
210 | #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 |
211 | #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 |
212 | #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 |
213 | #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 |
214 | #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 |
215 | #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 |
216 | #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 |
217 | #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 |
218 | #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a |
219 | #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b |
220 | #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c |
221 | #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e |
222 | #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f |
223 | #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L |
224 | #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L |
225 | #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L |
226 | #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L |
227 | #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L |
228 | #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L |
229 | #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L |
230 | #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L |
231 | #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L |
232 | #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L |
233 | #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L |
234 | #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L |
235 | #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L |
236 | #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L |
237 | #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L |
238 | #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L |
239 | #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L |
240 | #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L |
241 | #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L |
242 | #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L |
243 | #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L |
244 | #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L |
245 | #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L |
246 | #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L |
247 | #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L |
248 | #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L |
249 | #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L |
250 | #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L |
251 | #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L |
252 | //SDMA0_STATUS1_REG |
253 | #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 |
254 | #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 |
255 | #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 |
256 | #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 |
257 | #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 |
258 | #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 |
259 | #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 |
260 | #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 |
261 | #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa |
262 | #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd |
263 | #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe |
264 | #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf |
265 | #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 |
266 | #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 |
267 | #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L |
268 | #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L |
269 | #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L |
270 | #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L |
271 | #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L |
272 | #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L |
273 | #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L |
274 | #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L |
275 | #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L |
276 | #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L |
277 | #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L |
278 | #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L |
279 | #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L |
280 | #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L |
281 | //SDMA0_RD_BURST_CNTL |
282 | #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 |
283 | #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L |
284 | //SDMA0_HBM_PAGE_CONFIG |
285 | #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 |
286 | #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L |
287 | //SDMA0_UCODE_CHECKSUM |
288 | #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 |
289 | #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL |
290 | //SDMA0_F32_CNTL |
291 | #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 |
292 | #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 |
293 | #define SDMA0_F32_CNTL__CHECKSUM_CLR__SHIFT 0x8 |
294 | #define SDMA0_F32_CNTL__RESET__SHIFT 0x9 |
295 | #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L |
296 | #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L |
297 | #define SDMA0_F32_CNTL__CHECKSUM_CLR_MASK 0x00000100L |
298 | #define SDMA0_F32_CNTL__RESET_MASK 0x00000200L |
299 | //SDMA0_FREEZE |
300 | #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 |
301 | #define SDMA0_FREEZE__FORCE_PREEMPT__SHIFT 0x1 |
302 | #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 |
303 | #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 |
304 | #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 |
305 | #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L |
306 | #define SDMA0_FREEZE__FORCE_PREEMPT_MASK 0x00000002L |
307 | #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L |
308 | #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L |
309 | #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L |
310 | //SDMA0_PHASE0_QUANTUM |
311 | #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 |
312 | #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 |
313 | #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e |
314 | #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL |
315 | #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L |
316 | #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L |
317 | //SDMA0_PHASE1_QUANTUM |
318 | #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 |
319 | #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 |
320 | #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e |
321 | #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL |
322 | #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L |
323 | #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L |
324 | //SDMA0_EDC_CONFIG |
325 | #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 |
326 | #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 |
327 | #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L |
328 | #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L |
329 | //SDMA0_BA_THRESHOLD |
330 | #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 |
331 | #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 |
332 | #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL |
333 | #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L |
334 | //SDMA0_ID |
335 | #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 |
336 | #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL |
337 | //SDMA0_VERSION |
338 | #define SDMA0_VERSION__MINVER__SHIFT 0x0 |
339 | #define SDMA0_VERSION__MAJVER__SHIFT 0x8 |
340 | #define SDMA0_VERSION__REV__SHIFT 0x10 |
341 | #define SDMA0_VERSION__MINVER_MASK 0x0000007FL |
342 | #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L |
343 | #define SDMA0_VERSION__REV_MASK 0x003F0000L |
344 | //SDMA0_EDC_COUNTER |
345 | #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 |
346 | #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 |
347 | #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 |
348 | #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 |
349 | #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 |
350 | #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 |
351 | #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 |
352 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 |
353 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 |
354 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 |
355 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa |
356 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb |
357 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc |
358 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd |
359 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe |
360 | #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf |
361 | #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 |
362 | #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L |
363 | #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L |
364 | #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L |
365 | #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L |
366 | #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L |
367 | #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L |
368 | #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L |
369 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L |
370 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L |
371 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L |
372 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L |
373 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L |
374 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L |
375 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L |
376 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L |
377 | #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L |
378 | #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L |
379 | //SDMA0_EDC_COUNTER_CLEAR |
380 | #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 |
381 | #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L |
382 | //SDMA0_STATUS2_REG |
383 | #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 |
384 | #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 |
385 | #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 |
386 | #define SDMA0_STATUS2_REG__ID_MASK 0x00000003L |
387 | #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFFCL |
388 | #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L |
389 | //SDMA0_ATOMIC_CNTL |
390 | #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 |
391 | #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f |
392 | #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL |
393 | #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L |
394 | //SDMA0_ATOMIC_PREOP_LO |
395 | #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 |
396 | #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL |
397 | //SDMA0_ATOMIC_PREOP_HI |
398 | #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 |
399 | #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL |
400 | //SDMA0_UTCL1_CNTL |
401 | #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 |
402 | #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 |
403 | #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0x6 |
404 | #define SDMA0_UTCL1_CNTL__RESP_MODE__SHIFT 0x9 |
405 | #define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe |
406 | #define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xf |
407 | #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x10 |
408 | #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 |
409 | #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d |
410 | #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L |
411 | #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x0000003EL |
412 | #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x000001C0L |
413 | #define SDMA0_UTCL1_CNTL__RESP_MODE_MASK 0x00000E00L |
414 | #define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00004000L |
415 | #define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00008000L |
416 | #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FF0000L |
417 | #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L |
418 | #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L |
419 | //SDMA0_UTCL1_WATERMK |
420 | #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 |
421 | #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa |
422 | #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 |
423 | #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a |
424 | #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL |
425 | #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L |
426 | #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L |
427 | #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L |
428 | //SDMA0_UTCL1_RD_STATUS |
429 | #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 |
430 | #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1 |
431 | #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2 |
432 | #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3 |
433 | #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4 |
434 | #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5 |
435 | #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6 |
436 | #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7 |
437 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8 |
438 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9 |
439 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa |
440 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb |
441 | #define SDMA0_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT 0xc |
442 | #define SDMA0_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT 0xd |
443 | #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0xe |
444 | #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0xf |
445 | #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x10 |
446 | #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x11 |
447 | #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x15 |
448 | #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x18 |
449 | #define SDMA0_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT 0x19 |
450 | #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT 0x1a |
451 | #define SDMA0_UTCL1_RD_STATUS__HIT_CACHE__SHIFT 0x1b |
452 | #define SDMA0_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT 0x1c |
453 | #define SDMA0_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT 0x1d |
454 | #define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT 0x1e |
455 | #define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT 0x1f |
456 | #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L |
457 | #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L |
458 | #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L |
459 | #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L |
460 | #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L |
461 | #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L |
462 | #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L |
463 | #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L |
464 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L |
465 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L |
466 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L |
467 | #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L |
468 | #define SDMA0_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L |
469 | #define SDMA0_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK 0x00002000L |
470 | #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00004000L |
471 | #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00008000L |
472 | #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00010000L |
473 | #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x001E0000L |
474 | #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x00E00000L |
475 | #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x01000000L |
476 | #define SDMA0_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK 0x02000000L |
477 | #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK 0x04000000L |
478 | #define SDMA0_UTCL1_RD_STATUS__HIT_CACHE_MASK 0x08000000L |
479 | #define SDMA0_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK 0x10000000L |
480 | #define SDMA0_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK 0x20000000L |
481 | #define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK 0x40000000L |
482 | #define SDMA0_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK 0x80000000L |
483 | //SDMA0_UTCL1_WR_STATUS |
484 | #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 |
485 | #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1 |
486 | #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2 |
487 | #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3 |
488 | #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4 |
489 | #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5 |
490 | #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6 |
491 | #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7 |
492 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8 |
493 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9 |
494 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa |
495 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb |
496 | #define SDMA0_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT 0xc |
497 | #define SDMA0_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT 0xd |
498 | #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0xe |
499 | #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0xf |
500 | #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x10 |
501 | #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x11 |
502 | #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x15 |
503 | #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x18 |
504 | #define SDMA0_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT 0x19 |
505 | #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT 0x1a |
506 | #define SDMA0_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT 0x1b |
507 | #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c |
508 | #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d |
509 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e |
510 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f |
511 | #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L |
512 | #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L |
513 | #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L |
514 | #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L |
515 | #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L |
516 | #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L |
517 | #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L |
518 | #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L |
519 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L |
520 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L |
521 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L |
522 | #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L |
523 | #define SDMA0_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L |
524 | #define SDMA0_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK 0x00002000L |
525 | #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00004000L |
526 | #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00008000L |
527 | #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00010000L |
528 | #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x001E0000L |
529 | #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x00E00000L |
530 | #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x01000000L |
531 | #define SDMA0_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK 0x02000000L |
532 | #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK 0x04000000L |
533 | #define SDMA0_UTCL1_WR_STATUS__ATOMIC_OP_MASK 0x08000000L |
534 | #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L |
535 | #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L |
536 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L |
537 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L |
538 | //SDMA0_UTCL1_INV0 |
539 | #define SDMA0_UTCL1_INV0__CPF_INVREQ_EN__SHIFT 0x0 |
540 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT 0x1 |
541 | #define SDMA0_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT 0x2 |
542 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT 0x3 |
543 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT 0x4 |
544 | #define SDMA0_UTCL1_INV0__INVREQ_SIZE__SHIFT 0x5 |
545 | #define SDMA0_UTCL1_INV0__INVREQ_IDLE__SHIFT 0xb |
546 | #define SDMA0_UTCL1_INV0__VMINV_PEND_CNT__SHIFT 0xc |
547 | #define SDMA0_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT 0x10 |
548 | #define SDMA0_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT 0x14 |
549 | #define SDMA0_UTCL1_INV0__GPUVM_INV_MODE__SHIFT 0x18 |
550 | #define SDMA0_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT 0x1a |
551 | #define SDMA0_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT 0x1b |
552 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT 0x1c |
553 | #define SDMA0_UTCL1_INV0__CPF_INVREQ_EN_MASK 0x00000001L |
554 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_EN_MASK 0x00000002L |
555 | #define SDMA0_UTCL1_INV0__CPF_GPA_INVREQ_MASK 0x00000004L |
556 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK 0x00000008L |
557 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK 0x00000010L |
558 | #define SDMA0_UTCL1_INV0__INVREQ_SIZE_MASK 0x000007E0L |
559 | #define SDMA0_UTCL1_INV0__INVREQ_IDLE_MASK 0x00000800L |
560 | #define SDMA0_UTCL1_INV0__VMINV_PEND_CNT_MASK 0x0000F000L |
561 | #define SDMA0_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK 0x000F0000L |
562 | #define SDMA0_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK 0x00F00000L |
563 | #define SDMA0_UTCL1_INV0__GPUVM_INV_MODE_MASK 0x03000000L |
564 | #define SDMA0_UTCL1_INV0__INVREQ_IS_HEAVY_MASK 0x04000000L |
565 | #define SDMA0_UTCL1_INV0__INVREQ_FROM_CPF_MASK 0x08000000L |
566 | #define SDMA0_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK 0xF0000000L |
567 | //SDMA0_UTCL1_INV1 |
568 | #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 |
569 | #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL |
570 | //SDMA0_UTCL1_INV2 |
571 | #define SDMA0_UTCL1_INV2__INV_VMID_VEC__SHIFT 0x0 |
572 | #define SDMA0_UTCL1_INV2__RESERVED__SHIFT 0x10 |
573 | #define SDMA0_UTCL1_INV2__INV_VMID_VEC_MASK 0x0000FFFFL |
574 | #define SDMA0_UTCL1_INV2__RESERVED_MASK 0xFFFF0000L |
575 | //SDMA0_UTCL1_RD_XNACK0 |
576 | #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 |
577 | #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL |
578 | //SDMA0_UTCL1_RD_XNACK1 |
579 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 |
580 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 |
581 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 |
582 | #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a |
583 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL |
584 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L |
585 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L |
586 | #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L |
587 | //SDMA0_UTCL1_WR_XNACK0 |
588 | #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 |
589 | #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL |
590 | //SDMA0_UTCL1_WR_XNACK1 |
591 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 |
592 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 |
593 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 |
594 | #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a |
595 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL |
596 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L |
597 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L |
598 | #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L |
599 | //SDMA0_UTCL1_TIMEOUT |
600 | #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 |
601 | #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 |
602 | #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL |
603 | #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L |
604 | //SDMA0_UTCL1_PAGE |
605 | #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 |
606 | #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 |
607 | #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 |
608 | #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa |
609 | #define SDMA0_UTCL1_PAGE__USE_IO__SHIFT 0xb |
610 | #define SDMA0_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc |
611 | #define SDMA0_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe |
612 | #define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT 0x10 |
613 | #define SDMA0_UTCL1_PAGE__USE_BC__SHIFT 0x16 |
614 | #define SDMA0_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17 |
615 | #define SDMA0_UTCL1_PAGE__LLC_NOALLOC__SHIFT 0x18 |
616 | #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L |
617 | #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL |
618 | #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000003C0L |
619 | #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L |
620 | #define SDMA0_UTCL1_PAGE__USE_IO_MASK 0x00000800L |
621 | #define SDMA0_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L |
622 | #define SDMA0_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L |
623 | #define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE_MASK 0x003F0000L |
624 | #define SDMA0_UTCL1_PAGE__USE_BC_MASK 0x00400000L |
625 | #define SDMA0_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L |
626 | #define SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK 0x01000000L |
627 | //SDMA0_RELAX_ORDERING_LUT |
628 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 |
629 | #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 |
630 | #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 |
631 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 |
632 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 |
633 | #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 |
634 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 |
635 | #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 |
636 | #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 |
637 | #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa |
638 | #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb |
639 | #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc |
640 | #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd |
641 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe |
642 | #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b |
643 | #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c |
644 | #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d |
645 | #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e |
646 | #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f |
647 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L |
648 | #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L |
649 | #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L |
650 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L |
651 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L |
652 | #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L |
653 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L |
654 | #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L |
655 | #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L |
656 | #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L |
657 | #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L |
658 | #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L |
659 | #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L |
660 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L |
661 | #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L |
662 | #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L |
663 | #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L |
664 | #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L |
665 | #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L |
666 | //SDMA0_CHICKEN_BITS_2 |
667 | #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 |
668 | #define SDMA0_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT 0x4 |
669 | #define SDMA0_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE__SHIFT 0x5 |
670 | #define SDMA0_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT 0x6 |
671 | #define SDMA0_CHICKEN_BITS_2__RESERVED0__SHIFT 0x7 |
672 | #define SDMA0_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN__SHIFT 0xb |
673 | #define SDMA0_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR__SHIFT 0xf |
674 | #define SDMA0_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT 0x10 |
675 | #define SDMA0_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT 0x12 |
676 | #define SDMA0_CHICKEN_BITS_2__REPEATER_FGCG_EN__SHIFT 0x14 |
677 | #define SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x15 |
678 | #define SDMA0_CHICKEN_BITS_2__RESERVED__SHIFT 0x16 |
679 | #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL |
680 | #define SDMA0_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK 0x00000010L |
681 | #define SDMA0_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE_MASK 0x00000020L |
682 | #define SDMA0_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK 0x00000040L |
683 | #define SDMA0_CHICKEN_BITS_2__RESERVED0_MASK 0x00000780L |
684 | #define SDMA0_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN_MASK 0x00007800L |
685 | #define SDMA0_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR_MASK 0x00008000L |
686 | #define SDMA0_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK 0x00030000L |
687 | #define SDMA0_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK 0x000C0000L |
688 | #define SDMA0_CHICKEN_BITS_2__REPEATER_FGCG_EN_MASK 0x00100000L |
689 | #define SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00200000L |
690 | #define SDMA0_CHICKEN_BITS_2__RESERVED_MASK 0xFFC00000L |
691 | //SDMA0_STATUS3_REG |
692 | #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 |
693 | #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 |
694 | #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 |
695 | #define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15 |
696 | #define SDMA0_STATUS3_REG__TLBI_IDLE__SHIFT 0x16 |
697 | #define SDMA0_STATUS3_REG__GCR_IDLE__SHIFT 0x17 |
698 | #define SDMA0_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18 |
699 | #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19 |
700 | #define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a |
701 | #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL |
702 | #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L |
703 | #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L |
704 | #define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L |
705 | #define SDMA0_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L |
706 | #define SDMA0_STATUS3_REG__GCR_IDLE_MASK 0x00800000L |
707 | #define SDMA0_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L |
708 | #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L |
709 | #define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L |
710 | //SDMA0_PHYSICAL_ADDR_LO |
711 | #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 |
712 | #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 |
713 | #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 |
714 | #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc |
715 | #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L |
716 | #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L |
717 | #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L |
718 | #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L |
719 | //SDMA0_PHYSICAL_ADDR_HI |
720 | #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 |
721 | #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL |
722 | //SDMA0_PHASE2_QUANTUM |
723 | #define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 |
724 | #define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 |
725 | #define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e |
726 | #define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL |
727 | #define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L |
728 | #define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L |
729 | //SDMA0_ERROR_LOG |
730 | #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 |
731 | #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 |
732 | #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL |
733 | #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L |
734 | //SDMA0_PUB_DUMMY_REG0 |
735 | #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 |
736 | #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL |
737 | //SDMA0_PUB_DUMMY_REG1 |
738 | #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 |
739 | #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL |
740 | //SDMA0_PUB_DUMMY_REG2 |
741 | #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 |
742 | #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL |
743 | //SDMA0_PUB_DUMMY_REG3 |
744 | #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 |
745 | #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL |
746 | //SDMA0_F32_COUNTER |
747 | #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 |
748 | #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL |
749 | //SDMA0_CRD_CNTL |
750 | #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 |
751 | #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd |
752 | #define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13 |
753 | #define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19 |
754 | #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L |
755 | #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L |
756 | #define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L |
757 | #define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L |
758 | //SDMA0_AQL_STATUS |
759 | #define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0 |
760 | #define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1 |
761 | #define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L |
762 | #define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L |
763 | //SDMA0_EA_DBIT_ADDR_DATA |
764 | #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 |
765 | #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL |
766 | //SDMA0_EA_DBIT_ADDR_INDEX |
767 | #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 |
768 | #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L |
769 | //SDMA0_TLBI_GCR_CNTL |
770 | #define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0 |
771 | #define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4 |
772 | #define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT 0x8 |
773 | #define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10 |
774 | #define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18 |
775 | #define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL |
776 | #define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L |
777 | #define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK 0x00000F00L |
778 | #define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L |
779 | #define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L |
780 | //SDMA0_TILING_CONFIG |
781 | #define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
782 | #define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L |
783 | //SDMA0_INT_STATUS |
784 | #define SDMA0_INT_STATUS__DATA__SHIFT 0x0 |
785 | #define SDMA0_INT_STATUS__DATA_MASK 0xFFFFFFFFL |
786 | //SDMA0_HOLE_ADDR_LO |
787 | #define SDMA0_HOLE_ADDR_LO__VALUE__SHIFT 0x0 |
788 | #define SDMA0_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL |
789 | //SDMA0_HOLE_ADDR_HI |
790 | #define SDMA0_HOLE_ADDR_HI__VALUE__SHIFT 0x0 |
791 | #define SDMA0_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL |
792 | //SDMA0_CLOCK_GATING_REG |
793 | #define SDMA0_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS__SHIFT 0x0 |
794 | #define SDMA0_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS__SHIFT 0x1 |
795 | #define SDMA0_CLOCK_GATING_REG__CE_CLK_GATE_STATUS__SHIFT 0x2 |
796 | #define SDMA0_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS__SHIFT 0x3 |
797 | #define SDMA0_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS__SHIFT 0x4 |
798 | #define SDMA0_CLOCK_GATING_REG__REG_CLK_GATE_STATUS__SHIFT 0x5 |
799 | #define SDMA0_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS_MASK 0x00000001L |
800 | #define SDMA0_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS_MASK 0x00000002L |
801 | #define SDMA0_CLOCK_GATING_REG__CE_CLK_GATE_STATUS_MASK 0x00000004L |
802 | #define SDMA0_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS_MASK 0x00000008L |
803 | #define SDMA0_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS_MASK 0x00000010L |
804 | #define SDMA0_CLOCK_GATING_REG__REG_CLK_GATE_STATUS_MASK 0x00000020L |
805 | //SDMA0_STATUS4_REG |
806 | #define SDMA0_STATUS4_REG__IDLE__SHIFT 0x0 |
807 | #define SDMA0_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 |
808 | #define SDMA0_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 |
809 | #define SDMA0_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT 0x4 |
810 | #define SDMA0_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT 0x5 |
811 | #define SDMA0_STATUS4_REG__GCR_OUTSTANDING__SHIFT 0x6 |
812 | #define SDMA0_STATUS4_REG__TLBI_OUTSTANDING__SHIFT 0x7 |
813 | #define SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x8 |
814 | #define SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x9 |
815 | #define SDMA0_STATUS4_REG__REG_POLLING__SHIFT 0xa |
816 | #define SDMA0_STATUS4_REG__MEM_POLLING__SHIFT 0xb |
817 | #define SDMA0_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xc |
818 | #define SDMA0_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xe |
819 | #define SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 |
820 | #define SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x14 |
821 | #define SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x15 |
822 | #define SDMA0_STATUS4_REG__IDLE_MASK 0x00000001L |
823 | #define SDMA0_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L |
824 | #define SDMA0_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L |
825 | #define SDMA0_STATUS4_REG__CH_RD_OUTSTANDING_MASK 0x00000010L |
826 | #define SDMA0_STATUS4_REG__CH_WR_OUTSTANDING_MASK 0x00000020L |
827 | #define SDMA0_STATUS4_REG__GCR_OUTSTANDING_MASK 0x00000040L |
828 | #define SDMA0_STATUS4_REG__TLBI_OUTSTANDING_MASK 0x00000080L |
829 | #define SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000100L |
830 | #define SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000200L |
831 | #define SDMA0_STATUS4_REG__REG_POLLING_MASK 0x00000400L |
832 | #define SDMA0_STATUS4_REG__MEM_POLLING_MASK 0x00000800L |
833 | #define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00003000L |
834 | #define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x0000C000L |
835 | #define SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L |
836 | #define SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00100000L |
837 | #define SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00200000L |
838 | //SDMA0_SCRATCH_RAM_DATA |
839 | #define SDMA0_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 |
840 | #define SDMA0_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL |
841 | //SDMA0_SCRATCH_RAM_ADDR |
842 | #define SDMA0_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 |
843 | #define SDMA0_SCRATCH_RAM_ADDR__ADDR_MASK 0x000003FFL |
844 | //SDMA0_TIMESTAMP_CNTL |
845 | #define SDMA0_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 |
846 | #define SDMA0_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L |
847 | //SDMA0_STATUS5_REG |
848 | #define SDMA0_STATUS5_REG__GFX_RB_ENABLE_STATUS__SHIFT 0x0 |
849 | #define SDMA0_STATUS5_REG__PAGE_RB_ENABLE_STATUS__SHIFT 0x1 |
850 | #define SDMA0_STATUS5_REG__RLC0_RB_ENABLE_STATUS__SHIFT 0x2 |
851 | #define SDMA0_STATUS5_REG__RLC1_RB_ENABLE_STATUS__SHIFT 0x3 |
852 | #define SDMA0_STATUS5_REG__RLC2_RB_ENABLE_STATUS__SHIFT 0x4 |
853 | #define SDMA0_STATUS5_REG__RLC3_RB_ENABLE_STATUS__SHIFT 0x5 |
854 | #define SDMA0_STATUS5_REG__RLC4_RB_ENABLE_STATUS__SHIFT 0x6 |
855 | #define SDMA0_STATUS5_REG__RLC5_RB_ENABLE_STATUS__SHIFT 0x7 |
856 | #define SDMA0_STATUS5_REG__RLC6_RB_ENABLE_STATUS__SHIFT 0x8 |
857 | #define SDMA0_STATUS5_REG__RLC7_RB_ENABLE_STATUS__SHIFT 0x9 |
858 | #define SDMA0_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 |
859 | #define SDMA0_STATUS5_REG__GFX_RB_ENABLE_STATUS_MASK 0x00000001L |
860 | #define SDMA0_STATUS5_REG__PAGE_RB_ENABLE_STATUS_MASK 0x00000002L |
861 | #define SDMA0_STATUS5_REG__RLC0_RB_ENABLE_STATUS_MASK 0x00000004L |
862 | #define SDMA0_STATUS5_REG__RLC1_RB_ENABLE_STATUS_MASK 0x00000008L |
863 | #define SDMA0_STATUS5_REG__RLC2_RB_ENABLE_STATUS_MASK 0x00000010L |
864 | #define SDMA0_STATUS5_REG__RLC3_RB_ENABLE_STATUS_MASK 0x00000020L |
865 | #define SDMA0_STATUS5_REG__RLC4_RB_ENABLE_STATUS_MASK 0x00000040L |
866 | #define SDMA0_STATUS5_REG__RLC5_RB_ENABLE_STATUS_MASK 0x00000080L |
867 | #define SDMA0_STATUS5_REG__RLC6_RB_ENABLE_STATUS_MASK 0x00000100L |
868 | #define SDMA0_STATUS5_REG__RLC7_RB_ENABLE_STATUS_MASK 0x00000200L |
869 | #define SDMA0_STATUS5_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L |
870 | //SDMA0_QUEUE_RESET_REQ |
871 | #define SDMA0_QUEUE_RESET_REQ__GFX_QUEUE_RESET__SHIFT 0x0 |
872 | #define SDMA0_QUEUE_RESET_REQ__PAGE_QUEUE_RESET__SHIFT 0x1 |
873 | #define SDMA0_QUEUE_RESET_REQ__RLC0_QUEUE_RESET__SHIFT 0x2 |
874 | #define SDMA0_QUEUE_RESET_REQ__RLC1_QUEUE_RESET__SHIFT 0x3 |
875 | #define SDMA0_QUEUE_RESET_REQ__RLC2_QUEUE_RESET__SHIFT 0x4 |
876 | #define SDMA0_QUEUE_RESET_REQ__RLC3_QUEUE_RESET__SHIFT 0x5 |
877 | #define SDMA0_QUEUE_RESET_REQ__RLC4_QUEUE_RESET__SHIFT 0x6 |
878 | #define SDMA0_QUEUE_RESET_REQ__RLC5_QUEUE_RESET__SHIFT 0x7 |
879 | #define SDMA0_QUEUE_RESET_REQ__RLC6_QUEUE_RESET__SHIFT 0x8 |
880 | #define SDMA0_QUEUE_RESET_REQ__RLC7_QUEUE_RESET__SHIFT 0x9 |
881 | #define SDMA0_QUEUE_RESET_REQ__RESERVED__SHIFT 0xa |
882 | #define SDMA0_QUEUE_RESET_REQ__GFX_QUEUE_RESET_MASK 0x00000001L |
883 | #define SDMA0_QUEUE_RESET_REQ__PAGE_QUEUE_RESET_MASK 0x00000002L |
884 | #define SDMA0_QUEUE_RESET_REQ__RLC0_QUEUE_RESET_MASK 0x00000004L |
885 | #define SDMA0_QUEUE_RESET_REQ__RLC1_QUEUE_RESET_MASK 0x00000008L |
886 | #define SDMA0_QUEUE_RESET_REQ__RLC2_QUEUE_RESET_MASK 0x00000010L |
887 | #define SDMA0_QUEUE_RESET_REQ__RLC3_QUEUE_RESET_MASK 0x00000020L |
888 | #define SDMA0_QUEUE_RESET_REQ__RLC4_QUEUE_RESET_MASK 0x00000040L |
889 | #define SDMA0_QUEUE_RESET_REQ__RLC5_QUEUE_RESET_MASK 0x00000080L |
890 | #define SDMA0_QUEUE_RESET_REQ__RLC6_QUEUE_RESET_MASK 0x00000100L |
891 | #define SDMA0_QUEUE_RESET_REQ__RLC7_QUEUE_RESET_MASK 0x00000200L |
892 | #define SDMA0_QUEUE_RESET_REQ__RESERVED_MASK 0xFFFFFC00L |
893 | //SDMA0_GFX_RB_CNTL |
894 | #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
895 | #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 |
896 | #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
897 | #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
898 | #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
899 | #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
900 | #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 |
901 | #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 |
902 | #define SDMA0_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
903 | #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
904 | #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
905 | #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
906 | #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
907 | #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
908 | #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
909 | #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L |
910 | #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L |
911 | #define SDMA0_GFX_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
912 | //SDMA0_GFX_RB_BASE |
913 | #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 |
914 | #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
915 | //SDMA0_GFX_RB_BASE_HI |
916 | #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 |
917 | #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
918 | //SDMA0_GFX_RB_RPTR |
919 | #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 |
920 | #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
921 | //SDMA0_GFX_RB_RPTR_HI |
922 | #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
923 | #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
924 | //SDMA0_GFX_RB_WPTR |
925 | #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 |
926 | #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
927 | //SDMA0_GFX_RB_WPTR_HI |
928 | #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
929 | #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
930 | //SDMA0_GFX_RB_WPTR_POLL_CNTL |
931 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
932 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
933 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
934 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
935 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
936 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
937 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
938 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
939 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
940 | #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
941 | //SDMA0_GFX_RB_RPTR_ADDR_HI |
942 | #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
943 | #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
944 | //SDMA0_GFX_RB_RPTR_ADDR_LO |
945 | #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
946 | #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
947 | //SDMA0_GFX_IB_CNTL |
948 | #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
949 | #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
950 | #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
951 | #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 |
952 | #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
953 | #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
954 | #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
955 | #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
956 | //SDMA0_GFX_IB_RPTR |
957 | #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 |
958 | #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
959 | //SDMA0_GFX_IB_OFFSET |
960 | #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 |
961 | #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
962 | //SDMA0_GFX_IB_BASE_LO |
963 | #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 |
964 | #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
965 | //SDMA0_GFX_IB_BASE_HI |
966 | #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 |
967 | #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
968 | //SDMA0_GFX_IB_SIZE |
969 | #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 |
970 | #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL |
971 | //SDMA0_GFX_SKIP_CNTL |
972 | #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
973 | #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
974 | //SDMA0_GFX_CONTEXT_STATUS |
975 | #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
976 | #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
977 | #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
978 | #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
979 | #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
980 | #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
981 | #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
982 | #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
983 | #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
984 | #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
985 | #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
986 | #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
987 | #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
988 | #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
989 | #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
990 | #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
991 | //SDMA0_GFX_DOORBELL |
992 | #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c |
993 | #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e |
994 | #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L |
995 | #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L |
996 | //SDMA0_GFX_CONTEXT_CNTL |
997 | #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 |
998 | #define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 |
999 | #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L |
1000 | #define SDMA0_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L |
1001 | //SDMA0_GFX_STATUS |
1002 | #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
1003 | #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
1004 | #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
1005 | #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
1006 | //SDMA0_GFX_DOORBELL_LOG |
1007 | #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
1008 | #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 |
1009 | #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
1010 | #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
1011 | //SDMA0_GFX_WATERMARK |
1012 | #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
1013 | #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
1014 | #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
1015 | #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
1016 | //SDMA0_GFX_DOORBELL_OFFSET |
1017 | #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1018 | #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1019 | //SDMA0_GFX_CSA_ADDR_LO |
1020 | #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1021 | #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1022 | //SDMA0_GFX_CSA_ADDR_HI |
1023 | #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1024 | #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1025 | //SDMA0_GFX_IB_SUB_REMAIN |
1026 | #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1027 | #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1028 | //SDMA0_GFX_PREEMPT |
1029 | #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1030 | #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1031 | //SDMA0_GFX_DUMMY_REG |
1032 | #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 |
1033 | #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1034 | //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI |
1035 | #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1036 | #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1037 | //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO |
1038 | #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1039 | #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1040 | //SDMA0_GFX_RB_AQL_CNTL |
1041 | #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1042 | #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1043 | #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1044 | #define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1045 | #define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1046 | #define SDMA0_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1047 | #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1048 | #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1049 | #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1050 | #define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1051 | #define SDMA0_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1052 | #define SDMA0_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1053 | //SDMA0_GFX_MINOR_PTR_UPDATE |
1054 | #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1055 | #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1056 | //SDMA0_GFX_MIDCMD_DATA0 |
1057 | #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1058 | #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1059 | //SDMA0_GFX_MIDCMD_DATA1 |
1060 | #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1061 | #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1062 | //SDMA0_GFX_MIDCMD_DATA2 |
1063 | #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1064 | #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1065 | //SDMA0_GFX_MIDCMD_DATA3 |
1066 | #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1067 | #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1068 | //SDMA0_GFX_MIDCMD_DATA4 |
1069 | #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1070 | #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1071 | //SDMA0_GFX_MIDCMD_DATA5 |
1072 | #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1073 | #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1074 | //SDMA0_GFX_MIDCMD_DATA6 |
1075 | #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1076 | #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1077 | //SDMA0_GFX_MIDCMD_DATA7 |
1078 | #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
1079 | #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
1080 | //SDMA0_GFX_MIDCMD_DATA8 |
1081 | #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
1082 | #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
1083 | //SDMA0_GFX_MIDCMD_DATA9 |
1084 | #define SDMA0_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
1085 | #define SDMA0_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
1086 | //SDMA0_GFX_MIDCMD_DATA10 |
1087 | #define SDMA0_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
1088 | #define SDMA0_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
1089 | //SDMA0_GFX_MIDCMD_CNTL |
1090 | #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
1091 | #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
1092 | #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
1093 | #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
1094 | #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
1095 | #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
1096 | #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
1097 | #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
1098 | //SDMA0_PAGE_RB_CNTL |
1099 | #define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1100 | #define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1101 | #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1102 | #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1103 | #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1104 | #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1105 | #define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1106 | #define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 |
1107 | #define SDMA0_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
1108 | #define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1109 | #define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1110 | #define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1111 | #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1112 | #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1113 | #define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1114 | #define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1115 | #define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1116 | #define SDMA0_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
1117 | //SDMA0_PAGE_RB_BASE |
1118 | #define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 |
1119 | #define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1120 | //SDMA0_PAGE_RB_BASE_HI |
1121 | #define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 |
1122 | #define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1123 | //SDMA0_PAGE_RB_RPTR |
1124 | #define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 |
1125 | #define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1126 | //SDMA0_PAGE_RB_RPTR_HI |
1127 | #define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1128 | #define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1129 | //SDMA0_PAGE_RB_WPTR |
1130 | #define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 |
1131 | #define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1132 | //SDMA0_PAGE_RB_WPTR_HI |
1133 | #define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1134 | #define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1135 | //SDMA0_PAGE_RB_WPTR_POLL_CNTL |
1136 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
1137 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
1138 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
1139 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
1140 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
1141 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
1142 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
1143 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
1144 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
1145 | #define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
1146 | //SDMA0_PAGE_RB_RPTR_ADDR_HI |
1147 | #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1148 | #define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1149 | //SDMA0_PAGE_RB_RPTR_ADDR_LO |
1150 | #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1151 | #define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1152 | //SDMA0_PAGE_IB_CNTL |
1153 | #define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1154 | #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1155 | #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1156 | #define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1157 | #define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1158 | #define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1159 | #define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1160 | #define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1161 | //SDMA0_PAGE_IB_RPTR |
1162 | #define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 |
1163 | #define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1164 | //SDMA0_PAGE_IB_OFFSET |
1165 | #define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 |
1166 | #define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1167 | //SDMA0_PAGE_IB_BASE_LO |
1168 | #define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 |
1169 | #define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1170 | //SDMA0_PAGE_IB_BASE_HI |
1171 | #define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 |
1172 | #define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1173 | //SDMA0_PAGE_IB_SIZE |
1174 | #define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 |
1175 | #define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1176 | //SDMA0_PAGE_SKIP_CNTL |
1177 | #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1178 | #define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1179 | //SDMA0_PAGE_CONTEXT_STATUS |
1180 | #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1181 | #define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1182 | #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1183 | #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1184 | #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1185 | #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
1186 | #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
1187 | #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1188 | #define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1189 | #define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1190 | #define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1191 | #define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1192 | #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1193 | #define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
1194 | #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
1195 | #define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1196 | //SDMA0_PAGE_DOORBELL |
1197 | #define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c |
1198 | #define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e |
1199 | #define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L |
1200 | #define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L |
1201 | //SDMA0_PAGE_STATUS |
1202 | #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
1203 | #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
1204 | #define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
1205 | #define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
1206 | //SDMA0_PAGE_DOORBELL_LOG |
1207 | #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
1208 | #define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 |
1209 | #define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
1210 | #define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
1211 | //SDMA0_PAGE_WATERMARK |
1212 | #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
1213 | #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
1214 | #define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
1215 | #define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
1216 | //SDMA0_PAGE_DOORBELL_OFFSET |
1217 | #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1218 | #define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1219 | //SDMA0_PAGE_CSA_ADDR_LO |
1220 | #define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1221 | #define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1222 | //SDMA0_PAGE_CSA_ADDR_HI |
1223 | #define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1224 | #define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1225 | //SDMA0_PAGE_IB_SUB_REMAIN |
1226 | #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1227 | #define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1228 | //SDMA0_PAGE_PREEMPT |
1229 | #define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1230 | #define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1231 | //SDMA0_PAGE_DUMMY_REG |
1232 | #define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 |
1233 | #define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1234 | //SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI |
1235 | #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1236 | #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1237 | //SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO |
1238 | #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1239 | #define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1240 | //SDMA0_PAGE_RB_AQL_CNTL |
1241 | #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1242 | #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1243 | #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1244 | #define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1245 | #define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1246 | #define SDMA0_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1247 | #define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1248 | #define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1249 | #define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1250 | #define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1251 | #define SDMA0_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1252 | #define SDMA0_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1253 | //SDMA0_PAGE_MINOR_PTR_UPDATE |
1254 | #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1255 | #define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1256 | //SDMA0_PAGE_MIDCMD_DATA0 |
1257 | #define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1258 | #define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1259 | //SDMA0_PAGE_MIDCMD_DATA1 |
1260 | #define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1261 | #define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1262 | //SDMA0_PAGE_MIDCMD_DATA2 |
1263 | #define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1264 | #define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1265 | //SDMA0_PAGE_MIDCMD_DATA3 |
1266 | #define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1267 | #define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1268 | //SDMA0_PAGE_MIDCMD_DATA4 |
1269 | #define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1270 | #define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1271 | //SDMA0_PAGE_MIDCMD_DATA5 |
1272 | #define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1273 | #define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1274 | //SDMA0_PAGE_MIDCMD_DATA6 |
1275 | #define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1276 | #define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1277 | //SDMA0_PAGE_MIDCMD_DATA7 |
1278 | #define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
1279 | #define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
1280 | //SDMA0_PAGE_MIDCMD_DATA8 |
1281 | #define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
1282 | #define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
1283 | //SDMA0_PAGE_MIDCMD_DATA9 |
1284 | #define SDMA0_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
1285 | #define SDMA0_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
1286 | //SDMA0_PAGE_MIDCMD_DATA10 |
1287 | #define SDMA0_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
1288 | #define SDMA0_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
1289 | //SDMA0_PAGE_MIDCMD_CNTL |
1290 | #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
1291 | #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
1292 | #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
1293 | #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
1294 | #define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
1295 | #define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
1296 | #define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
1297 | #define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
1298 | //SDMA0_RLC0_RB_CNTL |
1299 | #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1300 | #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1301 | #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1302 | #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1303 | #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1304 | #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1305 | #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1306 | #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 |
1307 | #define SDMA0_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
1308 | #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1309 | #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1310 | #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1311 | #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1312 | #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1313 | #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1314 | #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1315 | #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1316 | #define SDMA0_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
1317 | //SDMA0_RLC0_RB_BASE |
1318 | #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 |
1319 | #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1320 | //SDMA0_RLC0_RB_BASE_HI |
1321 | #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 |
1322 | #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1323 | //SDMA0_RLC0_RB_RPTR |
1324 | #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 |
1325 | #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1326 | //SDMA0_RLC0_RB_RPTR_HI |
1327 | #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1328 | #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1329 | //SDMA0_RLC0_RB_WPTR |
1330 | #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 |
1331 | #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1332 | //SDMA0_RLC0_RB_WPTR_HI |
1333 | #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1334 | #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1335 | //SDMA0_RLC0_RB_WPTR_POLL_CNTL |
1336 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
1337 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
1338 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
1339 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
1340 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
1341 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
1342 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
1343 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
1344 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
1345 | #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
1346 | //SDMA0_RLC0_RB_RPTR_ADDR_HI |
1347 | #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1348 | #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1349 | //SDMA0_RLC0_RB_RPTR_ADDR_LO |
1350 | #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1351 | #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1352 | //SDMA0_RLC0_IB_CNTL |
1353 | #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1354 | #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1355 | #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1356 | #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1357 | #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1358 | #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1359 | #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1360 | #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1361 | //SDMA0_RLC0_IB_RPTR |
1362 | #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 |
1363 | #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1364 | //SDMA0_RLC0_IB_OFFSET |
1365 | #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 |
1366 | #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1367 | //SDMA0_RLC0_IB_BASE_LO |
1368 | #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 |
1369 | #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1370 | //SDMA0_RLC0_IB_BASE_HI |
1371 | #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 |
1372 | #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1373 | //SDMA0_RLC0_IB_SIZE |
1374 | #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 |
1375 | #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1376 | //SDMA0_RLC0_SKIP_CNTL |
1377 | #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1378 | #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1379 | //SDMA0_RLC0_CONTEXT_STATUS |
1380 | #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1381 | #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1382 | #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1383 | #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1384 | #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1385 | #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
1386 | #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
1387 | #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1388 | #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1389 | #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1390 | #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1391 | #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1392 | #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1393 | #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
1394 | #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
1395 | #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1396 | //SDMA0_RLC0_DOORBELL |
1397 | #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c |
1398 | #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e |
1399 | #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L |
1400 | #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L |
1401 | //SDMA0_RLC0_STATUS |
1402 | #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
1403 | #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
1404 | #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
1405 | #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
1406 | //SDMA0_RLC0_DOORBELL_LOG |
1407 | #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
1408 | #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 |
1409 | #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
1410 | #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
1411 | //SDMA0_RLC0_WATERMARK |
1412 | #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
1413 | #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
1414 | #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
1415 | #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
1416 | //SDMA0_RLC0_DOORBELL_OFFSET |
1417 | #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1418 | #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1419 | //SDMA0_RLC0_CSA_ADDR_LO |
1420 | #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1421 | #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1422 | //SDMA0_RLC0_CSA_ADDR_HI |
1423 | #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1424 | #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1425 | //SDMA0_RLC0_IB_SUB_REMAIN |
1426 | #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1427 | #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1428 | //SDMA0_RLC0_PREEMPT |
1429 | #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1430 | #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1431 | //SDMA0_RLC0_DUMMY_REG |
1432 | #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 |
1433 | #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1434 | //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI |
1435 | #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1436 | #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1437 | //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO |
1438 | #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1439 | #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1440 | //SDMA0_RLC0_RB_AQL_CNTL |
1441 | #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1442 | #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1443 | #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1444 | #define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1445 | #define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1446 | #define SDMA0_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1447 | #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1448 | #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1449 | #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1450 | #define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1451 | #define SDMA0_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1452 | #define SDMA0_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1453 | //SDMA0_RLC0_MINOR_PTR_UPDATE |
1454 | #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1455 | #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1456 | //SDMA0_RLC0_MIDCMD_DATA0 |
1457 | #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1458 | #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1459 | //SDMA0_RLC0_MIDCMD_DATA1 |
1460 | #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1461 | #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1462 | //SDMA0_RLC0_MIDCMD_DATA2 |
1463 | #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1464 | #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1465 | //SDMA0_RLC0_MIDCMD_DATA3 |
1466 | #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1467 | #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1468 | //SDMA0_RLC0_MIDCMD_DATA4 |
1469 | #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1470 | #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1471 | //SDMA0_RLC0_MIDCMD_DATA5 |
1472 | #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1473 | #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1474 | //SDMA0_RLC0_MIDCMD_DATA6 |
1475 | #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1476 | #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1477 | //SDMA0_RLC0_MIDCMD_DATA7 |
1478 | #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
1479 | #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
1480 | //SDMA0_RLC0_MIDCMD_DATA8 |
1481 | #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
1482 | #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
1483 | //SDMA0_RLC0_MIDCMD_DATA9 |
1484 | #define SDMA0_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
1485 | #define SDMA0_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
1486 | //SDMA0_RLC0_MIDCMD_DATA10 |
1487 | #define SDMA0_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
1488 | #define SDMA0_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
1489 | //SDMA0_RLC0_MIDCMD_CNTL |
1490 | #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
1491 | #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
1492 | #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
1493 | #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
1494 | #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
1495 | #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
1496 | #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
1497 | #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
1498 | //SDMA0_RLC1_RB_CNTL |
1499 | #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1500 | #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1501 | #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1502 | #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1503 | #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1504 | #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1505 | #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1506 | #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 |
1507 | #define SDMA0_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
1508 | #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1509 | #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1510 | #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1511 | #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1512 | #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1513 | #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1514 | #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1515 | #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1516 | #define SDMA0_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
1517 | //SDMA0_RLC1_RB_BASE |
1518 | #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 |
1519 | #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1520 | //SDMA0_RLC1_RB_BASE_HI |
1521 | #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 |
1522 | #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1523 | //SDMA0_RLC1_RB_RPTR |
1524 | #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 |
1525 | #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1526 | //SDMA0_RLC1_RB_RPTR_HI |
1527 | #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1528 | #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1529 | //SDMA0_RLC1_RB_WPTR |
1530 | #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 |
1531 | #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1532 | //SDMA0_RLC1_RB_WPTR_HI |
1533 | #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1534 | #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1535 | //SDMA0_RLC1_RB_WPTR_POLL_CNTL |
1536 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
1537 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
1538 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
1539 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
1540 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
1541 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
1542 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
1543 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
1544 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
1545 | #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
1546 | //SDMA0_RLC1_RB_RPTR_ADDR_HI |
1547 | #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1548 | #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1549 | //SDMA0_RLC1_RB_RPTR_ADDR_LO |
1550 | #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1551 | #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1552 | //SDMA0_RLC1_IB_CNTL |
1553 | #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1554 | #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1555 | #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1556 | #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1557 | #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1558 | #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1559 | #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1560 | #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1561 | //SDMA0_RLC1_IB_RPTR |
1562 | #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 |
1563 | #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1564 | //SDMA0_RLC1_IB_OFFSET |
1565 | #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 |
1566 | #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1567 | //SDMA0_RLC1_IB_BASE_LO |
1568 | #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 |
1569 | #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1570 | //SDMA0_RLC1_IB_BASE_HI |
1571 | #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 |
1572 | #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1573 | //SDMA0_RLC1_IB_SIZE |
1574 | #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 |
1575 | #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1576 | //SDMA0_RLC1_SKIP_CNTL |
1577 | #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1578 | #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1579 | //SDMA0_RLC1_CONTEXT_STATUS |
1580 | #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1581 | #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1582 | #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1583 | #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1584 | #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1585 | #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
1586 | #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
1587 | #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1588 | #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1589 | #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1590 | #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1591 | #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1592 | #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1593 | #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
1594 | #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
1595 | #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1596 | //SDMA0_RLC1_DOORBELL |
1597 | #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c |
1598 | #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e |
1599 | #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L |
1600 | #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L |
1601 | //SDMA0_RLC1_STATUS |
1602 | #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
1603 | #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
1604 | #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
1605 | #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
1606 | //SDMA0_RLC1_DOORBELL_LOG |
1607 | #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
1608 | #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 |
1609 | #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
1610 | #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
1611 | //SDMA0_RLC1_WATERMARK |
1612 | #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
1613 | #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
1614 | #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
1615 | #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
1616 | //SDMA0_RLC1_DOORBELL_OFFSET |
1617 | #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1618 | #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1619 | //SDMA0_RLC1_CSA_ADDR_LO |
1620 | #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1621 | #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1622 | //SDMA0_RLC1_CSA_ADDR_HI |
1623 | #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1624 | #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1625 | //SDMA0_RLC1_IB_SUB_REMAIN |
1626 | #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1627 | #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1628 | //SDMA0_RLC1_PREEMPT |
1629 | #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1630 | #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1631 | //SDMA0_RLC1_DUMMY_REG |
1632 | #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 |
1633 | #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1634 | //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI |
1635 | #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1636 | #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1637 | //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO |
1638 | #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1639 | #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1640 | //SDMA0_RLC1_RB_AQL_CNTL |
1641 | #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1642 | #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1643 | #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1644 | #define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1645 | #define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1646 | #define SDMA0_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1647 | #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1648 | #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1649 | #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1650 | #define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1651 | #define SDMA0_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1652 | #define SDMA0_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1653 | //SDMA0_RLC1_MINOR_PTR_UPDATE |
1654 | #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1655 | #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1656 | //SDMA0_RLC1_MIDCMD_DATA0 |
1657 | #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1658 | #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1659 | //SDMA0_RLC1_MIDCMD_DATA1 |
1660 | #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1661 | #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1662 | //SDMA0_RLC1_MIDCMD_DATA2 |
1663 | #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1664 | #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1665 | //SDMA0_RLC1_MIDCMD_DATA3 |
1666 | #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1667 | #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1668 | //SDMA0_RLC1_MIDCMD_DATA4 |
1669 | #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1670 | #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1671 | //SDMA0_RLC1_MIDCMD_DATA5 |
1672 | #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1673 | #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1674 | //SDMA0_RLC1_MIDCMD_DATA6 |
1675 | #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1676 | #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1677 | //SDMA0_RLC1_MIDCMD_DATA7 |
1678 | #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
1679 | #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
1680 | //SDMA0_RLC1_MIDCMD_DATA8 |
1681 | #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
1682 | #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
1683 | //SDMA0_RLC1_MIDCMD_DATA9 |
1684 | #define SDMA0_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
1685 | #define SDMA0_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
1686 | //SDMA0_RLC1_MIDCMD_DATA10 |
1687 | #define SDMA0_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
1688 | #define SDMA0_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
1689 | //SDMA0_RLC1_MIDCMD_CNTL |
1690 | #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
1691 | #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
1692 | #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
1693 | #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
1694 | #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
1695 | #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
1696 | #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
1697 | #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
1698 | //SDMA0_RLC2_RB_CNTL |
1699 | #define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1700 | #define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1701 | #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1702 | #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1703 | #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1704 | #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1705 | #define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1706 | #define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 |
1707 | #define SDMA0_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
1708 | #define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1709 | #define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1710 | #define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1711 | #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1712 | #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1713 | #define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1714 | #define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1715 | #define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1716 | #define SDMA0_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
1717 | //SDMA0_RLC2_RB_BASE |
1718 | #define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0 |
1719 | #define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1720 | //SDMA0_RLC2_RB_BASE_HI |
1721 | #define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 |
1722 | #define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1723 | //SDMA0_RLC2_RB_RPTR |
1724 | #define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 |
1725 | #define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1726 | //SDMA0_RLC2_RB_RPTR_HI |
1727 | #define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1728 | #define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1729 | //SDMA0_RLC2_RB_WPTR |
1730 | #define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 |
1731 | #define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1732 | //SDMA0_RLC2_RB_WPTR_HI |
1733 | #define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1734 | #define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1735 | //SDMA0_RLC2_RB_WPTR_POLL_CNTL |
1736 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
1737 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
1738 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
1739 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
1740 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
1741 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
1742 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
1743 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
1744 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
1745 | #define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
1746 | //SDMA0_RLC2_RB_RPTR_ADDR_HI |
1747 | #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1748 | #define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1749 | //SDMA0_RLC2_RB_RPTR_ADDR_LO |
1750 | #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1751 | #define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1752 | //SDMA0_RLC2_IB_CNTL |
1753 | #define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1754 | #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1755 | #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1756 | #define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1757 | #define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1758 | #define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1759 | #define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1760 | #define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1761 | //SDMA0_RLC2_IB_RPTR |
1762 | #define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 |
1763 | #define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1764 | //SDMA0_RLC2_IB_OFFSET |
1765 | #define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 |
1766 | #define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1767 | //SDMA0_RLC2_IB_BASE_LO |
1768 | #define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 |
1769 | #define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1770 | //SDMA0_RLC2_IB_BASE_HI |
1771 | #define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 |
1772 | #define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1773 | //SDMA0_RLC2_IB_SIZE |
1774 | #define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0 |
1775 | #define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1776 | //SDMA0_RLC2_SKIP_CNTL |
1777 | #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1778 | #define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1779 | //SDMA0_RLC2_CONTEXT_STATUS |
1780 | #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1781 | #define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1782 | #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1783 | #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1784 | #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1785 | #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
1786 | #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
1787 | #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1788 | #define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1789 | #define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1790 | #define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1791 | #define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1792 | #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1793 | #define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
1794 | #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
1795 | #define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1796 | //SDMA0_RLC2_DOORBELL |
1797 | #define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c |
1798 | #define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e |
1799 | #define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L |
1800 | #define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L |
1801 | //SDMA0_RLC2_STATUS |
1802 | #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
1803 | #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
1804 | #define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
1805 | #define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
1806 | //SDMA0_RLC2_DOORBELL_LOG |
1807 | #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
1808 | #define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 |
1809 | #define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
1810 | #define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
1811 | //SDMA0_RLC2_WATERMARK |
1812 | #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
1813 | #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
1814 | #define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
1815 | #define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
1816 | //SDMA0_RLC2_DOORBELL_OFFSET |
1817 | #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1818 | #define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1819 | //SDMA0_RLC2_CSA_ADDR_LO |
1820 | #define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1821 | #define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1822 | //SDMA0_RLC2_CSA_ADDR_HI |
1823 | #define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1824 | #define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1825 | //SDMA0_RLC2_IB_SUB_REMAIN |
1826 | #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1827 | #define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1828 | //SDMA0_RLC2_PREEMPT |
1829 | #define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1830 | #define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1831 | //SDMA0_RLC2_DUMMY_REG |
1832 | #define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 |
1833 | #define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1834 | //SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI |
1835 | #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1836 | #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1837 | //SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO |
1838 | #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1839 | #define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1840 | //SDMA0_RLC2_RB_AQL_CNTL |
1841 | #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1842 | #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1843 | #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1844 | #define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1845 | #define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1846 | #define SDMA0_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1847 | #define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1848 | #define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1849 | #define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1850 | #define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1851 | #define SDMA0_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1852 | #define SDMA0_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1853 | //SDMA0_RLC2_MINOR_PTR_UPDATE |
1854 | #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1855 | #define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1856 | //SDMA0_RLC2_MIDCMD_DATA0 |
1857 | #define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1858 | #define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1859 | //SDMA0_RLC2_MIDCMD_DATA1 |
1860 | #define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1861 | #define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1862 | //SDMA0_RLC2_MIDCMD_DATA2 |
1863 | #define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1864 | #define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1865 | //SDMA0_RLC2_MIDCMD_DATA3 |
1866 | #define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1867 | #define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1868 | //SDMA0_RLC2_MIDCMD_DATA4 |
1869 | #define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1870 | #define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1871 | //SDMA0_RLC2_MIDCMD_DATA5 |
1872 | #define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1873 | #define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1874 | //SDMA0_RLC2_MIDCMD_DATA6 |
1875 | #define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1876 | #define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1877 | //SDMA0_RLC2_MIDCMD_DATA7 |
1878 | #define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
1879 | #define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
1880 | //SDMA0_RLC2_MIDCMD_DATA8 |
1881 | #define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
1882 | #define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
1883 | //SDMA0_RLC2_MIDCMD_DATA9 |
1884 | #define SDMA0_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
1885 | #define SDMA0_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
1886 | //SDMA0_RLC2_MIDCMD_DATA10 |
1887 | #define SDMA0_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
1888 | #define SDMA0_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
1889 | //SDMA0_RLC2_MIDCMD_CNTL |
1890 | #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
1891 | #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
1892 | #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
1893 | #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
1894 | #define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
1895 | #define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
1896 | #define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
1897 | #define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
1898 | //SDMA0_RLC3_RB_CNTL |
1899 | #define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1900 | #define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1901 | #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1902 | #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1903 | #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1904 | #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1905 | #define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1906 | #define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 |
1907 | #define SDMA0_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
1908 | #define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1909 | #define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1910 | #define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1911 | #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1912 | #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1913 | #define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1914 | #define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1915 | #define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1916 | #define SDMA0_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
1917 | //SDMA0_RLC3_RB_BASE |
1918 | #define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0 |
1919 | #define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1920 | //SDMA0_RLC3_RB_BASE_HI |
1921 | #define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 |
1922 | #define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1923 | //SDMA0_RLC3_RB_RPTR |
1924 | #define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 |
1925 | #define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1926 | //SDMA0_RLC3_RB_RPTR_HI |
1927 | #define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1928 | #define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1929 | //SDMA0_RLC3_RB_WPTR |
1930 | #define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 |
1931 | #define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1932 | //SDMA0_RLC3_RB_WPTR_HI |
1933 | #define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1934 | #define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1935 | //SDMA0_RLC3_RB_WPTR_POLL_CNTL |
1936 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
1937 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
1938 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
1939 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
1940 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
1941 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
1942 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
1943 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
1944 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
1945 | #define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
1946 | //SDMA0_RLC3_RB_RPTR_ADDR_HI |
1947 | #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1948 | #define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1949 | //SDMA0_RLC3_RB_RPTR_ADDR_LO |
1950 | #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1951 | #define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1952 | //SDMA0_RLC3_IB_CNTL |
1953 | #define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1954 | #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1955 | #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1956 | #define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1957 | #define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1958 | #define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1959 | #define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1960 | #define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1961 | //SDMA0_RLC3_IB_RPTR |
1962 | #define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 |
1963 | #define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1964 | //SDMA0_RLC3_IB_OFFSET |
1965 | #define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 |
1966 | #define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1967 | //SDMA0_RLC3_IB_BASE_LO |
1968 | #define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 |
1969 | #define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1970 | //SDMA0_RLC3_IB_BASE_HI |
1971 | #define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 |
1972 | #define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1973 | //SDMA0_RLC3_IB_SIZE |
1974 | #define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0 |
1975 | #define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1976 | //SDMA0_RLC3_SKIP_CNTL |
1977 | #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1978 | #define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1979 | //SDMA0_RLC3_CONTEXT_STATUS |
1980 | #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1981 | #define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1982 | #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1983 | #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1984 | #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1985 | #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
1986 | #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
1987 | #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1988 | #define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1989 | #define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1990 | #define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1991 | #define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1992 | #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1993 | #define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
1994 | #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
1995 | #define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1996 | //SDMA0_RLC3_DOORBELL |
1997 | #define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c |
1998 | #define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e |
1999 | #define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L |
2000 | #define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L |
2001 | //SDMA0_RLC3_STATUS |
2002 | #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
2003 | #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
2004 | #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
2005 | #define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
2006 | //SDMA0_RLC3_DOORBELL_LOG |
2007 | #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
2008 | #define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 |
2009 | #define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
2010 | #define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
2011 | //SDMA0_RLC3_WATERMARK |
2012 | #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
2013 | #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
2014 | #define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
2015 | #define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
2016 | //SDMA0_RLC3_DOORBELL_OFFSET |
2017 | #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
2018 | #define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
2019 | //SDMA0_RLC3_CSA_ADDR_LO |
2020 | #define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
2021 | #define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2022 | //SDMA0_RLC3_CSA_ADDR_HI |
2023 | #define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
2024 | #define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2025 | //SDMA0_RLC3_IB_SUB_REMAIN |
2026 | #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
2027 | #define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
2028 | //SDMA0_RLC3_PREEMPT |
2029 | #define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
2030 | #define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
2031 | //SDMA0_RLC3_DUMMY_REG |
2032 | #define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 |
2033 | #define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
2034 | //SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI |
2035 | #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
2036 | #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2037 | //SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO |
2038 | #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
2039 | #define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2040 | //SDMA0_RLC3_RB_AQL_CNTL |
2041 | #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
2042 | #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
2043 | #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
2044 | #define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
2045 | #define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
2046 | #define SDMA0_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
2047 | #define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
2048 | #define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
2049 | #define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
2050 | #define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
2051 | #define SDMA0_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
2052 | #define SDMA0_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
2053 | //SDMA0_RLC3_MINOR_PTR_UPDATE |
2054 | #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
2055 | #define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
2056 | //SDMA0_RLC3_MIDCMD_DATA0 |
2057 | #define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
2058 | #define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
2059 | //SDMA0_RLC3_MIDCMD_DATA1 |
2060 | #define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
2061 | #define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
2062 | //SDMA0_RLC3_MIDCMD_DATA2 |
2063 | #define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
2064 | #define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
2065 | //SDMA0_RLC3_MIDCMD_DATA3 |
2066 | #define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
2067 | #define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
2068 | //SDMA0_RLC3_MIDCMD_DATA4 |
2069 | #define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
2070 | #define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
2071 | //SDMA0_RLC3_MIDCMD_DATA5 |
2072 | #define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
2073 | #define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
2074 | //SDMA0_RLC3_MIDCMD_DATA6 |
2075 | #define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
2076 | #define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
2077 | //SDMA0_RLC3_MIDCMD_DATA7 |
2078 | #define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
2079 | #define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
2080 | //SDMA0_RLC3_MIDCMD_DATA8 |
2081 | #define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
2082 | #define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
2083 | //SDMA0_RLC3_MIDCMD_DATA9 |
2084 | #define SDMA0_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
2085 | #define SDMA0_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
2086 | //SDMA0_RLC3_MIDCMD_DATA10 |
2087 | #define SDMA0_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
2088 | #define SDMA0_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
2089 | //SDMA0_RLC3_MIDCMD_CNTL |
2090 | #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
2091 | #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
2092 | #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
2093 | #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
2094 | #define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
2095 | #define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
2096 | #define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
2097 | #define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
2098 | //SDMA0_RLC4_RB_CNTL |
2099 | #define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
2100 | #define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 |
2101 | #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
2102 | #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
2103 | #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
2104 | #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
2105 | #define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 |
2106 | #define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 |
2107 | #define SDMA0_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
2108 | #define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
2109 | #define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
2110 | #define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
2111 | #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
2112 | #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
2113 | #define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
2114 | #define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L |
2115 | #define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L |
2116 | #define SDMA0_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
2117 | //SDMA0_RLC4_RB_BASE |
2118 | #define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0 |
2119 | #define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
2120 | //SDMA0_RLC4_RB_BASE_HI |
2121 | #define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 |
2122 | #define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
2123 | //SDMA0_RLC4_RB_RPTR |
2124 | #define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 |
2125 | #define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
2126 | //SDMA0_RLC4_RB_RPTR_HI |
2127 | #define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
2128 | #define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2129 | //SDMA0_RLC4_RB_WPTR |
2130 | #define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 |
2131 | #define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
2132 | //SDMA0_RLC4_RB_WPTR_HI |
2133 | #define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
2134 | #define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2135 | //SDMA0_RLC4_RB_WPTR_POLL_CNTL |
2136 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
2137 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
2138 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
2139 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
2140 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
2141 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
2142 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
2143 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
2144 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
2145 | #define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
2146 | //SDMA0_RLC4_RB_RPTR_ADDR_HI |
2147 | #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
2148 | #define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2149 | //SDMA0_RLC4_RB_RPTR_ADDR_LO |
2150 | #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
2151 | #define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2152 | //SDMA0_RLC4_IB_CNTL |
2153 | #define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
2154 | #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
2155 | #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
2156 | #define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 |
2157 | #define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
2158 | #define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
2159 | #define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
2160 | #define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
2161 | //SDMA0_RLC4_IB_RPTR |
2162 | #define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 |
2163 | #define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
2164 | //SDMA0_RLC4_IB_OFFSET |
2165 | #define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 |
2166 | #define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
2167 | //SDMA0_RLC4_IB_BASE_LO |
2168 | #define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 |
2169 | #define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
2170 | //SDMA0_RLC4_IB_BASE_HI |
2171 | #define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 |
2172 | #define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
2173 | //SDMA0_RLC4_IB_SIZE |
2174 | #define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0 |
2175 | #define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL |
2176 | //SDMA0_RLC4_SKIP_CNTL |
2177 | #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
2178 | #define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
2179 | //SDMA0_RLC4_CONTEXT_STATUS |
2180 | #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
2181 | #define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
2182 | #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
2183 | #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
2184 | #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
2185 | #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
2186 | #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
2187 | #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
2188 | #define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
2189 | #define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
2190 | #define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
2191 | #define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
2192 | #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
2193 | #define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
2194 | #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
2195 | #define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
2196 | //SDMA0_RLC4_DOORBELL |
2197 | #define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c |
2198 | #define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e |
2199 | #define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L |
2200 | #define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L |
2201 | //SDMA0_RLC4_STATUS |
2202 | #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
2203 | #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
2204 | #define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
2205 | #define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
2206 | //SDMA0_RLC4_DOORBELL_LOG |
2207 | #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
2208 | #define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 |
2209 | #define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
2210 | #define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
2211 | //SDMA0_RLC4_WATERMARK |
2212 | #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
2213 | #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
2214 | #define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
2215 | #define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
2216 | //SDMA0_RLC4_DOORBELL_OFFSET |
2217 | #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
2218 | #define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
2219 | //SDMA0_RLC4_CSA_ADDR_LO |
2220 | #define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
2221 | #define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2222 | //SDMA0_RLC4_CSA_ADDR_HI |
2223 | #define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
2224 | #define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2225 | //SDMA0_RLC4_IB_SUB_REMAIN |
2226 | #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
2227 | #define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
2228 | //SDMA0_RLC4_PREEMPT |
2229 | #define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
2230 | #define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
2231 | //SDMA0_RLC4_DUMMY_REG |
2232 | #define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 |
2233 | #define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
2234 | //SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI |
2235 | #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
2236 | #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2237 | //SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO |
2238 | #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
2239 | #define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2240 | //SDMA0_RLC4_RB_AQL_CNTL |
2241 | #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
2242 | #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
2243 | #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
2244 | #define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
2245 | #define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
2246 | #define SDMA0_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
2247 | #define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
2248 | #define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
2249 | #define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
2250 | #define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
2251 | #define SDMA0_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
2252 | #define SDMA0_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
2253 | //SDMA0_RLC4_MINOR_PTR_UPDATE |
2254 | #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
2255 | #define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
2256 | //SDMA0_RLC4_MIDCMD_DATA0 |
2257 | #define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
2258 | #define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
2259 | //SDMA0_RLC4_MIDCMD_DATA1 |
2260 | #define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
2261 | #define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
2262 | //SDMA0_RLC4_MIDCMD_DATA2 |
2263 | #define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
2264 | #define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
2265 | //SDMA0_RLC4_MIDCMD_DATA3 |
2266 | #define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
2267 | #define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
2268 | //SDMA0_RLC4_MIDCMD_DATA4 |
2269 | #define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
2270 | #define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
2271 | //SDMA0_RLC4_MIDCMD_DATA5 |
2272 | #define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
2273 | #define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
2274 | //SDMA0_RLC4_MIDCMD_DATA6 |
2275 | #define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
2276 | #define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
2277 | //SDMA0_RLC4_MIDCMD_DATA7 |
2278 | #define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
2279 | #define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
2280 | //SDMA0_RLC4_MIDCMD_DATA8 |
2281 | #define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
2282 | #define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
2283 | //SDMA0_RLC4_MIDCMD_DATA9 |
2284 | #define SDMA0_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
2285 | #define SDMA0_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
2286 | //SDMA0_RLC4_MIDCMD_DATA10 |
2287 | #define SDMA0_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
2288 | #define SDMA0_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
2289 | //SDMA0_RLC4_MIDCMD_CNTL |
2290 | #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
2291 | #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
2292 | #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
2293 | #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
2294 | #define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
2295 | #define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
2296 | #define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
2297 | #define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
2298 | //SDMA0_RLC5_RB_CNTL |
2299 | #define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
2300 | #define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 |
2301 | #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
2302 | #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
2303 | #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
2304 | #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
2305 | #define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 |
2306 | #define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 |
2307 | #define SDMA0_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
2308 | #define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
2309 | #define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
2310 | #define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
2311 | #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
2312 | #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
2313 | #define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
2314 | #define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L |
2315 | #define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L |
2316 | #define SDMA0_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
2317 | //SDMA0_RLC5_RB_BASE |
2318 | #define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0 |
2319 | #define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
2320 | //SDMA0_RLC5_RB_BASE_HI |
2321 | #define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 |
2322 | #define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
2323 | //SDMA0_RLC5_RB_RPTR |
2324 | #define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 |
2325 | #define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
2326 | //SDMA0_RLC5_RB_RPTR_HI |
2327 | #define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
2328 | #define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2329 | //SDMA0_RLC5_RB_WPTR |
2330 | #define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 |
2331 | #define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
2332 | //SDMA0_RLC5_RB_WPTR_HI |
2333 | #define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
2334 | #define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2335 | //SDMA0_RLC5_RB_WPTR_POLL_CNTL |
2336 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
2337 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
2338 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
2339 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
2340 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
2341 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
2342 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
2343 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
2344 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
2345 | #define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
2346 | //SDMA0_RLC5_RB_RPTR_ADDR_HI |
2347 | #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
2348 | #define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2349 | //SDMA0_RLC5_RB_RPTR_ADDR_LO |
2350 | #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
2351 | #define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2352 | //SDMA0_RLC5_IB_CNTL |
2353 | #define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
2354 | #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
2355 | #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
2356 | #define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 |
2357 | #define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
2358 | #define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
2359 | #define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
2360 | #define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
2361 | //SDMA0_RLC5_IB_RPTR |
2362 | #define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 |
2363 | #define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
2364 | //SDMA0_RLC5_IB_OFFSET |
2365 | #define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 |
2366 | #define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
2367 | //SDMA0_RLC5_IB_BASE_LO |
2368 | #define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 |
2369 | #define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
2370 | //SDMA0_RLC5_IB_BASE_HI |
2371 | #define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 |
2372 | #define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
2373 | //SDMA0_RLC5_IB_SIZE |
2374 | #define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0 |
2375 | #define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL |
2376 | //SDMA0_RLC5_SKIP_CNTL |
2377 | #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
2378 | #define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
2379 | //SDMA0_RLC5_CONTEXT_STATUS |
2380 | #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
2381 | #define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
2382 | #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
2383 | #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
2384 | #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
2385 | #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
2386 | #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
2387 | #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
2388 | #define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
2389 | #define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
2390 | #define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
2391 | #define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
2392 | #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
2393 | #define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
2394 | #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
2395 | #define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
2396 | //SDMA0_RLC5_DOORBELL |
2397 | #define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c |
2398 | #define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e |
2399 | #define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L |
2400 | #define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L |
2401 | //SDMA0_RLC5_STATUS |
2402 | #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
2403 | #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
2404 | #define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
2405 | #define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
2406 | //SDMA0_RLC5_DOORBELL_LOG |
2407 | #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
2408 | #define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 |
2409 | #define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
2410 | #define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
2411 | //SDMA0_RLC5_WATERMARK |
2412 | #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
2413 | #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
2414 | #define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
2415 | #define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
2416 | //SDMA0_RLC5_DOORBELL_OFFSET |
2417 | #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
2418 | #define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
2419 | //SDMA0_RLC5_CSA_ADDR_LO |
2420 | #define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
2421 | #define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2422 | //SDMA0_RLC5_CSA_ADDR_HI |
2423 | #define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
2424 | #define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2425 | //SDMA0_RLC5_IB_SUB_REMAIN |
2426 | #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
2427 | #define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
2428 | //SDMA0_RLC5_PREEMPT |
2429 | #define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
2430 | #define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
2431 | //SDMA0_RLC5_DUMMY_REG |
2432 | #define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 |
2433 | #define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
2434 | //SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI |
2435 | #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
2436 | #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2437 | //SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO |
2438 | #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
2439 | #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2440 | //SDMA0_RLC5_RB_AQL_CNTL |
2441 | #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
2442 | #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
2443 | #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
2444 | #define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
2445 | #define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
2446 | #define SDMA0_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
2447 | #define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
2448 | #define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
2449 | #define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
2450 | #define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
2451 | #define SDMA0_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
2452 | #define SDMA0_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
2453 | //SDMA0_RLC5_MINOR_PTR_UPDATE |
2454 | #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
2455 | #define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
2456 | //SDMA0_RLC5_MIDCMD_DATA0 |
2457 | #define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
2458 | #define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
2459 | //SDMA0_RLC5_MIDCMD_DATA1 |
2460 | #define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
2461 | #define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
2462 | //SDMA0_RLC5_MIDCMD_DATA2 |
2463 | #define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
2464 | #define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
2465 | //SDMA0_RLC5_MIDCMD_DATA3 |
2466 | #define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
2467 | #define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
2468 | //SDMA0_RLC5_MIDCMD_DATA4 |
2469 | #define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
2470 | #define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
2471 | //SDMA0_RLC5_MIDCMD_DATA5 |
2472 | #define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
2473 | #define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
2474 | //SDMA0_RLC5_MIDCMD_DATA6 |
2475 | #define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
2476 | #define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
2477 | //SDMA0_RLC5_MIDCMD_DATA7 |
2478 | #define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
2479 | #define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
2480 | //SDMA0_RLC5_MIDCMD_DATA8 |
2481 | #define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
2482 | #define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
2483 | //SDMA0_RLC5_MIDCMD_DATA9 |
2484 | #define SDMA0_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
2485 | #define SDMA0_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
2486 | //SDMA0_RLC5_MIDCMD_DATA10 |
2487 | #define SDMA0_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
2488 | #define SDMA0_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
2489 | //SDMA0_RLC5_MIDCMD_CNTL |
2490 | #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
2491 | #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
2492 | #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
2493 | #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
2494 | #define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
2495 | #define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
2496 | #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
2497 | #define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
2498 | //SDMA0_RLC6_RB_CNTL |
2499 | #define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
2500 | #define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 |
2501 | #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
2502 | #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
2503 | #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
2504 | #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
2505 | #define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 |
2506 | #define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 |
2507 | #define SDMA0_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
2508 | #define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
2509 | #define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
2510 | #define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
2511 | #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
2512 | #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
2513 | #define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
2514 | #define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L |
2515 | #define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L |
2516 | #define SDMA0_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
2517 | //SDMA0_RLC6_RB_BASE |
2518 | #define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0 |
2519 | #define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
2520 | //SDMA0_RLC6_RB_BASE_HI |
2521 | #define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 |
2522 | #define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
2523 | //SDMA0_RLC6_RB_RPTR |
2524 | #define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 |
2525 | #define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
2526 | //SDMA0_RLC6_RB_RPTR_HI |
2527 | #define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
2528 | #define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2529 | //SDMA0_RLC6_RB_WPTR |
2530 | #define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 |
2531 | #define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
2532 | //SDMA0_RLC6_RB_WPTR_HI |
2533 | #define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
2534 | #define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2535 | //SDMA0_RLC6_RB_WPTR_POLL_CNTL |
2536 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
2537 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
2538 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
2539 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
2540 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
2541 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
2542 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
2543 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
2544 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
2545 | #define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
2546 | //SDMA0_RLC6_RB_RPTR_ADDR_HI |
2547 | #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
2548 | #define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2549 | //SDMA0_RLC6_RB_RPTR_ADDR_LO |
2550 | #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
2551 | #define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2552 | //SDMA0_RLC6_IB_CNTL |
2553 | #define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
2554 | #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
2555 | #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
2556 | #define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 |
2557 | #define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
2558 | #define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
2559 | #define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
2560 | #define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
2561 | //SDMA0_RLC6_IB_RPTR |
2562 | #define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 |
2563 | #define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
2564 | //SDMA0_RLC6_IB_OFFSET |
2565 | #define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 |
2566 | #define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
2567 | //SDMA0_RLC6_IB_BASE_LO |
2568 | #define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 |
2569 | #define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
2570 | //SDMA0_RLC6_IB_BASE_HI |
2571 | #define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 |
2572 | #define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
2573 | //SDMA0_RLC6_IB_SIZE |
2574 | #define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0 |
2575 | #define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL |
2576 | //SDMA0_RLC6_SKIP_CNTL |
2577 | #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
2578 | #define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
2579 | //SDMA0_RLC6_CONTEXT_STATUS |
2580 | #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
2581 | #define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
2582 | #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
2583 | #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
2584 | #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
2585 | #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
2586 | #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
2587 | #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
2588 | #define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
2589 | #define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
2590 | #define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
2591 | #define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
2592 | #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
2593 | #define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
2594 | #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
2595 | #define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
2596 | //SDMA0_RLC6_DOORBELL |
2597 | #define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c |
2598 | #define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e |
2599 | #define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L |
2600 | #define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L |
2601 | //SDMA0_RLC6_STATUS |
2602 | #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
2603 | #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
2604 | #define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
2605 | #define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
2606 | //SDMA0_RLC6_DOORBELL_LOG |
2607 | #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
2608 | #define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 |
2609 | #define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
2610 | #define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
2611 | //SDMA0_RLC6_WATERMARK |
2612 | #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
2613 | #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
2614 | #define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
2615 | #define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
2616 | //SDMA0_RLC6_DOORBELL_OFFSET |
2617 | #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
2618 | #define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
2619 | //SDMA0_RLC6_CSA_ADDR_LO |
2620 | #define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
2621 | #define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2622 | //SDMA0_RLC6_CSA_ADDR_HI |
2623 | #define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
2624 | #define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2625 | //SDMA0_RLC6_IB_SUB_REMAIN |
2626 | #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
2627 | #define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
2628 | //SDMA0_RLC6_PREEMPT |
2629 | #define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
2630 | #define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
2631 | //SDMA0_RLC6_DUMMY_REG |
2632 | #define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 |
2633 | #define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
2634 | //SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI |
2635 | #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
2636 | #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2637 | //SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO |
2638 | #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
2639 | #define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2640 | //SDMA0_RLC6_RB_AQL_CNTL |
2641 | #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
2642 | #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
2643 | #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
2644 | #define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
2645 | #define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
2646 | #define SDMA0_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
2647 | #define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
2648 | #define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
2649 | #define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
2650 | #define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
2651 | #define SDMA0_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
2652 | #define SDMA0_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
2653 | //SDMA0_RLC6_MINOR_PTR_UPDATE |
2654 | #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
2655 | #define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
2656 | //SDMA0_RLC6_MIDCMD_DATA0 |
2657 | #define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
2658 | #define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
2659 | //SDMA0_RLC6_MIDCMD_DATA1 |
2660 | #define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
2661 | #define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
2662 | //SDMA0_RLC6_MIDCMD_DATA2 |
2663 | #define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
2664 | #define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
2665 | //SDMA0_RLC6_MIDCMD_DATA3 |
2666 | #define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
2667 | #define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
2668 | //SDMA0_RLC6_MIDCMD_DATA4 |
2669 | #define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
2670 | #define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
2671 | //SDMA0_RLC6_MIDCMD_DATA5 |
2672 | #define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
2673 | #define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
2674 | //SDMA0_RLC6_MIDCMD_DATA6 |
2675 | #define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
2676 | #define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
2677 | //SDMA0_RLC6_MIDCMD_DATA7 |
2678 | #define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
2679 | #define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
2680 | //SDMA0_RLC6_MIDCMD_DATA8 |
2681 | #define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
2682 | #define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
2683 | //SDMA0_RLC6_MIDCMD_DATA9 |
2684 | #define SDMA0_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
2685 | #define SDMA0_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
2686 | //SDMA0_RLC6_MIDCMD_DATA10 |
2687 | #define SDMA0_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
2688 | #define SDMA0_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
2689 | //SDMA0_RLC6_MIDCMD_CNTL |
2690 | #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
2691 | #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
2692 | #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
2693 | #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
2694 | #define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
2695 | #define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
2696 | #define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
2697 | #define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
2698 | //SDMA0_RLC7_RB_CNTL |
2699 | #define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
2700 | #define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 |
2701 | #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
2702 | #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
2703 | #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
2704 | #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
2705 | #define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 |
2706 | #define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 |
2707 | #define SDMA0_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
2708 | #define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
2709 | #define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
2710 | #define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
2711 | #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
2712 | #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
2713 | #define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
2714 | #define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L |
2715 | #define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L |
2716 | #define SDMA0_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
2717 | //SDMA0_RLC7_RB_BASE |
2718 | #define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0 |
2719 | #define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
2720 | //SDMA0_RLC7_RB_BASE_HI |
2721 | #define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 |
2722 | #define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
2723 | //SDMA0_RLC7_RB_RPTR |
2724 | #define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 |
2725 | #define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
2726 | //SDMA0_RLC7_RB_RPTR_HI |
2727 | #define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
2728 | #define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2729 | //SDMA0_RLC7_RB_WPTR |
2730 | #define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 |
2731 | #define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
2732 | //SDMA0_RLC7_RB_WPTR_HI |
2733 | #define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
2734 | #define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2735 | //SDMA0_RLC7_RB_WPTR_POLL_CNTL |
2736 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
2737 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
2738 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
2739 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
2740 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
2741 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
2742 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
2743 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
2744 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
2745 | #define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
2746 | //SDMA0_RLC7_RB_RPTR_ADDR_HI |
2747 | #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
2748 | #define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2749 | //SDMA0_RLC7_RB_RPTR_ADDR_LO |
2750 | #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
2751 | #define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2752 | //SDMA0_RLC7_IB_CNTL |
2753 | #define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
2754 | #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
2755 | #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
2756 | #define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 |
2757 | #define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
2758 | #define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
2759 | #define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
2760 | #define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
2761 | //SDMA0_RLC7_IB_RPTR |
2762 | #define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 |
2763 | #define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
2764 | //SDMA0_RLC7_IB_OFFSET |
2765 | #define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 |
2766 | #define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
2767 | //SDMA0_RLC7_IB_BASE_LO |
2768 | #define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 |
2769 | #define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
2770 | //SDMA0_RLC7_IB_BASE_HI |
2771 | #define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 |
2772 | #define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
2773 | //SDMA0_RLC7_IB_SIZE |
2774 | #define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0 |
2775 | #define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL |
2776 | //SDMA0_RLC7_SKIP_CNTL |
2777 | #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
2778 | #define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
2779 | //SDMA0_RLC7_CONTEXT_STATUS |
2780 | #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
2781 | #define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
2782 | #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
2783 | #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
2784 | #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
2785 | #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
2786 | #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
2787 | #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
2788 | #define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
2789 | #define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
2790 | #define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
2791 | #define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
2792 | #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
2793 | #define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
2794 | #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
2795 | #define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
2796 | //SDMA0_RLC7_DOORBELL |
2797 | #define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c |
2798 | #define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e |
2799 | #define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L |
2800 | #define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L |
2801 | //SDMA0_RLC7_STATUS |
2802 | #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
2803 | #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
2804 | #define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
2805 | #define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
2806 | //SDMA0_RLC7_DOORBELL_LOG |
2807 | #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
2808 | #define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 |
2809 | #define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
2810 | #define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
2811 | //SDMA0_RLC7_WATERMARK |
2812 | #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
2813 | #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
2814 | #define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
2815 | #define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
2816 | //SDMA0_RLC7_DOORBELL_OFFSET |
2817 | #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
2818 | #define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
2819 | //SDMA0_RLC7_CSA_ADDR_LO |
2820 | #define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
2821 | #define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2822 | //SDMA0_RLC7_CSA_ADDR_HI |
2823 | #define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
2824 | #define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2825 | //SDMA0_RLC7_IB_SUB_REMAIN |
2826 | #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
2827 | #define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
2828 | //SDMA0_RLC7_PREEMPT |
2829 | #define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
2830 | #define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
2831 | //SDMA0_RLC7_DUMMY_REG |
2832 | #define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 |
2833 | #define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
2834 | //SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI |
2835 | #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
2836 | #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2837 | //SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO |
2838 | #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
2839 | #define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2840 | //SDMA0_RLC7_RB_AQL_CNTL |
2841 | #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
2842 | #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
2843 | #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
2844 | #define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
2845 | #define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
2846 | #define SDMA0_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
2847 | #define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
2848 | #define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
2849 | #define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
2850 | #define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
2851 | #define SDMA0_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
2852 | #define SDMA0_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
2853 | //SDMA0_RLC7_MINOR_PTR_UPDATE |
2854 | #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
2855 | #define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
2856 | //SDMA0_RLC7_MIDCMD_DATA0 |
2857 | #define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
2858 | #define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
2859 | //SDMA0_RLC7_MIDCMD_DATA1 |
2860 | #define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
2861 | #define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
2862 | //SDMA0_RLC7_MIDCMD_DATA2 |
2863 | #define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
2864 | #define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
2865 | //SDMA0_RLC7_MIDCMD_DATA3 |
2866 | #define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
2867 | #define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
2868 | //SDMA0_RLC7_MIDCMD_DATA4 |
2869 | #define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
2870 | #define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
2871 | //SDMA0_RLC7_MIDCMD_DATA5 |
2872 | #define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
2873 | #define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
2874 | //SDMA0_RLC7_MIDCMD_DATA6 |
2875 | #define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
2876 | #define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
2877 | //SDMA0_RLC7_MIDCMD_DATA7 |
2878 | #define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
2879 | #define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
2880 | //SDMA0_RLC7_MIDCMD_DATA8 |
2881 | #define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
2882 | #define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
2883 | //SDMA0_RLC7_MIDCMD_DATA9 |
2884 | #define SDMA0_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
2885 | #define SDMA0_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
2886 | //SDMA0_RLC7_MIDCMD_DATA10 |
2887 | #define SDMA0_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
2888 | #define SDMA0_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
2889 | //SDMA0_RLC7_MIDCMD_CNTL |
2890 | #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
2891 | #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
2892 | #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
2893 | #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
2894 | #define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
2895 | #define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
2896 | #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
2897 | #define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
2898 | |
2899 | |
2900 | // addressBlock: gc_sdma1_sdma1dec |
2901 | //SDMA1_DEC_START |
2902 | #define SDMA1_DEC_START__START__SHIFT 0x0 |
2903 | #define SDMA1_DEC_START__START_MASK 0xFFFFFFFFL |
2904 | //SDMA1_GLOBAL_TIMESTAMP_LO |
2905 | #define SDMA1_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 |
2906 | #define SDMA1_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL |
2907 | //SDMA1_GLOBAL_TIMESTAMP_HI |
2908 | #define SDMA1_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 |
2909 | #define SDMA1_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL |
2910 | //SDMA1_PG_CNTL |
2911 | #define SDMA1_PG_CNTL__CMD__SHIFT 0x0 |
2912 | #define SDMA1_PG_CNTL__STATUS__SHIFT 0x10 |
2913 | #define SDMA1_PG_CNTL__CMD_MASK 0x0000000FL |
2914 | #define SDMA1_PG_CNTL__STATUS_MASK 0x000F0000L |
2915 | //SDMA1_PG_CTX_LO |
2916 | #define SDMA1_PG_CTX_LO__ADDR__SHIFT 0x0 |
2917 | #define SDMA1_PG_CTX_LO__ADDR_MASK 0xFFFFFFFFL |
2918 | //SDMA1_PG_CTX_HI |
2919 | #define SDMA1_PG_CTX_HI__ADDR__SHIFT 0x0 |
2920 | #define SDMA1_PG_CTX_HI__ADDR_MASK 0xFFFFFFFFL |
2921 | //SDMA1_PG_CTX_CNTL |
2922 | #define SDMA1_PG_CTX_CNTL__VMID__SHIFT 0x4 |
2923 | #define SDMA1_PG_CTX_CNTL__VMID_MASK 0x000000F0L |
2924 | //SDMA1_POWER_CNTL |
2925 | #define SDMA1_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 |
2926 | #define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 |
2927 | #define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 |
2928 | #define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 |
2929 | #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 |
2930 | #define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a |
2931 | #define SDMA1_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L |
2932 | #define SDMA1_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L |
2933 | #define SDMA1_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L |
2934 | #define SDMA1_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L |
2935 | #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L |
2936 | #define SDMA1_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L |
2937 | //SDMA1_CLK_CTRL |
2938 | #define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
2939 | #define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
2940 | #define SDMA1_CLK_CTRL__RESERVED_24_12__SHIFT 0xc |
2941 | #define SDMA1_CLK_CTRL__CGCG_EN_OVERRIDE__SHIFT 0x19 |
2942 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1a |
2943 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1b |
2944 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1c |
2945 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1d |
2946 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1e |
2947 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDER_REG__SHIFT 0x1f |
2948 | #define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
2949 | #define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
2950 | #define SDMA1_CLK_CTRL__RESERVED_24_12_MASK 0x01FFF000L |
2951 | #define SDMA1_CLK_CTRL__CGCG_EN_OVERRIDE_MASK 0x02000000L |
2952 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x04000000L |
2953 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x08000000L |
2954 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x10000000L |
2955 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x20000000L |
2956 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x40000000L |
2957 | #define SDMA1_CLK_CTRL__SOFT_OVERRIDER_REG_MASK 0x80000000L |
2958 | //SDMA1_CNTL |
2959 | #define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 |
2960 | #define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 |
2961 | #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 |
2962 | #define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 |
2963 | #define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 |
2964 | #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 |
2965 | #define SDMA1_CNTL__PAGE_INT_ENABLE__SHIFT 0x7 |
2966 | #define SDMA1_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10 |
2967 | #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 |
2968 | #define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 |
2969 | #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c |
2970 | #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d |
2971 | #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e |
2972 | #define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L |
2973 | #define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L |
2974 | #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L |
2975 | #define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L |
2976 | #define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L |
2977 | #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L |
2978 | #define SDMA1_CNTL__PAGE_INT_ENABLE_MASK 0x00000080L |
2979 | #define SDMA1_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L |
2980 | #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L |
2981 | #define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L |
2982 | #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L |
2983 | #define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L |
2984 | #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L |
2985 | //SDMA1_CHICKEN_BITS |
2986 | #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 |
2987 | #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 |
2988 | #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 |
2989 | #define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_DCGE__SHIFT 0x4 |
2990 | #define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG__SHIFT 0x5 |
2991 | #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 |
2992 | #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa |
2993 | #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 |
2994 | #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 |
2995 | #define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 |
2996 | #define SDMA1_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT 0x13 |
2997 | #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 |
2998 | #define SDMA1_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT 0x15 |
2999 | #define SDMA1_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE__SHIFT 0x16 |
3000 | #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 |
3001 | #define SDMA1_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT 0x18 |
3002 | #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 |
3003 | #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a |
3004 | #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c |
3005 | #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e |
3006 | #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L |
3007 | #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L |
3008 | #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L |
3009 | #define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_DCGE_MASK 0x00000010L |
3010 | #define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG_MASK 0x00000020L |
3011 | #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L |
3012 | #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L |
3013 | #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L |
3014 | #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L |
3015 | #define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L |
3016 | #define SDMA1_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK 0x00080000L |
3017 | #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L |
3018 | #define SDMA1_CHICKEN_BITS__CH_FGCG_ENABLE_MASK 0x00200000L |
3019 | #define SDMA1_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE_MASK 0x00400000L |
3020 | #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L |
3021 | #define SDMA1_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK 0x01000000L |
3022 | #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L |
3023 | #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L |
3024 | #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L |
3025 | #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L |
3026 | //SDMA1_GB_ADDR_CONFIG |
3027 | #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
3028 | #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
3029 | #define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
3030 | #define SDMA1_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 |
3031 | #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
3032 | #define SDMA1_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a |
3033 | #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
3034 | #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
3035 | #define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
3036 | #define SDMA1_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L |
3037 | #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
3038 | #define SDMA1_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L |
3039 | //SDMA1_GB_ADDR_CONFIG_READ |
3040 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 |
3041 | #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
3042 | #define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
3043 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 |
3044 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 |
3045 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a |
3046 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L |
3047 | #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
3048 | #define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
3049 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L |
3050 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L |
3051 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L |
3052 | //SDMA1_RB_RPTR_FETCH_HI |
3053 | #define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 |
3054 | #define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL |
3055 | //SDMA1_SEM_WAIT_FAIL_TIMER_CNTL |
3056 | #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 |
3057 | #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL |
3058 | //SDMA1_RB_RPTR_FETCH |
3059 | #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 |
3060 | #define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL |
3061 | //SDMA1_IB_OFFSET_FETCH |
3062 | #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 |
3063 | #define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL |
3064 | //SDMA1_PROGRAM |
3065 | #define SDMA1_PROGRAM__STREAM__SHIFT 0x0 |
3066 | #define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL |
3067 | //SDMA1_STATUS_REG |
3068 | #define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 |
3069 | #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 |
3070 | #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 |
3071 | #define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 |
3072 | #define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 |
3073 | #define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 |
3074 | #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 |
3075 | #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 |
3076 | #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 |
3077 | #define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 |
3078 | #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa |
3079 | #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb |
3080 | #define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc |
3081 | #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd |
3082 | #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe |
3083 | #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf |
3084 | #define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 |
3085 | #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 |
3086 | #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 |
3087 | #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 |
3088 | #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 |
3089 | #define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 |
3090 | #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 |
3091 | #define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 |
3092 | #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a |
3093 | #define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b |
3094 | #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c |
3095 | #define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e |
3096 | #define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f |
3097 | #define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L |
3098 | #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L |
3099 | #define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L |
3100 | #define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L |
3101 | #define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L |
3102 | #define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L |
3103 | #define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L |
3104 | #define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L |
3105 | #define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L |
3106 | #define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L |
3107 | #define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L |
3108 | #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L |
3109 | #define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L |
3110 | #define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L |
3111 | #define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L |
3112 | #define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L |
3113 | #define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L |
3114 | #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L |
3115 | #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L |
3116 | #define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L |
3117 | #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L |
3118 | #define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L |
3119 | #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L |
3120 | #define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L |
3121 | #define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L |
3122 | #define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L |
3123 | #define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L |
3124 | #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L |
3125 | #define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L |
3126 | //SDMA1_STATUS1_REG |
3127 | #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 |
3128 | #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 |
3129 | #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 |
3130 | #define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 |
3131 | #define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 |
3132 | #define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 |
3133 | #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 |
3134 | #define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 |
3135 | #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa |
3136 | #define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd |
3137 | #define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe |
3138 | #define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf |
3139 | #define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 |
3140 | #define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 |
3141 | #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L |
3142 | #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L |
3143 | #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L |
3144 | #define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L |
3145 | #define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L |
3146 | #define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L |
3147 | #define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L |
3148 | #define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L |
3149 | #define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L |
3150 | #define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L |
3151 | #define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L |
3152 | #define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L |
3153 | #define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L |
3154 | #define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L |
3155 | //SDMA1_RD_BURST_CNTL |
3156 | #define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 |
3157 | #define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L |
3158 | //SDMA1_HBM_PAGE_CONFIG |
3159 | #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 |
3160 | #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L |
3161 | //SDMA1_UCODE_CHECKSUM |
3162 | #define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 |
3163 | #define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL |
3164 | //SDMA1_F32_CNTL |
3165 | #define SDMA1_F32_CNTL__HALT__SHIFT 0x0 |
3166 | #define SDMA1_F32_CNTL__STEP__SHIFT 0x1 |
3167 | #define SDMA1_F32_CNTL__CHECKSUM_CLR__SHIFT 0x8 |
3168 | #define SDMA1_F32_CNTL__RESET__SHIFT 0x9 |
3169 | #define SDMA1_F32_CNTL__HALT_MASK 0x00000001L |
3170 | #define SDMA1_F32_CNTL__STEP_MASK 0x00000002L |
3171 | #define SDMA1_F32_CNTL__CHECKSUM_CLR_MASK 0x00000100L |
3172 | #define SDMA1_F32_CNTL__RESET_MASK 0x00000200L |
3173 | //SDMA1_FREEZE |
3174 | #define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 |
3175 | #define SDMA1_FREEZE__FORCE_PREEMPT__SHIFT 0x1 |
3176 | #define SDMA1_FREEZE__FREEZE__SHIFT 0x4 |
3177 | #define SDMA1_FREEZE__FROZEN__SHIFT 0x5 |
3178 | #define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 |
3179 | #define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L |
3180 | #define SDMA1_FREEZE__FORCE_PREEMPT_MASK 0x00000002L |
3181 | #define SDMA1_FREEZE__FREEZE_MASK 0x00000010L |
3182 | #define SDMA1_FREEZE__FROZEN_MASK 0x00000020L |
3183 | #define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L |
3184 | //SDMA1_PHASE0_QUANTUM |
3185 | #define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 |
3186 | #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 |
3187 | #define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e |
3188 | #define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL |
3189 | #define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L |
3190 | #define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L |
3191 | //SDMA1_PHASE1_QUANTUM |
3192 | #define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 |
3193 | #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 |
3194 | #define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e |
3195 | #define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL |
3196 | #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L |
3197 | #define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L |
3198 | //SDMA1_EDC_CONFIG |
3199 | #define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 |
3200 | #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 |
3201 | #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L |
3202 | #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L |
3203 | //SDMA1_BA_THRESHOLD |
3204 | #define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 |
3205 | #define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 |
3206 | #define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL |
3207 | #define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L |
3208 | //SDMA1_ID |
3209 | #define SDMA1_ID__DEVICE_ID__SHIFT 0x0 |
3210 | #define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL |
3211 | //SDMA1_VERSION |
3212 | #define SDMA1_VERSION__MINVER__SHIFT 0x0 |
3213 | #define SDMA1_VERSION__MAJVER__SHIFT 0x8 |
3214 | #define SDMA1_VERSION__REV__SHIFT 0x10 |
3215 | #define SDMA1_VERSION__MINVER_MASK 0x0000007FL |
3216 | #define SDMA1_VERSION__MAJVER_MASK 0x00007F00L |
3217 | #define SDMA1_VERSION__REV_MASK 0x003F0000L |
3218 | //SDMA1_EDC_COUNTER |
3219 | #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 |
3220 | #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 |
3221 | #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 |
3222 | #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 |
3223 | #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 |
3224 | #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 |
3225 | #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 |
3226 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 |
3227 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 |
3228 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 |
3229 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa |
3230 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb |
3231 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc |
3232 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd |
3233 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe |
3234 | #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf |
3235 | #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 |
3236 | #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L |
3237 | #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L |
3238 | #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L |
3239 | #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L |
3240 | #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L |
3241 | #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L |
3242 | #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L |
3243 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L |
3244 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L |
3245 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L |
3246 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L |
3247 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L |
3248 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L |
3249 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L |
3250 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L |
3251 | #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L |
3252 | #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L |
3253 | //SDMA1_EDC_COUNTER_CLEAR |
3254 | #define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 |
3255 | #define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L |
3256 | //SDMA1_STATUS2_REG |
3257 | #define SDMA1_STATUS2_REG__ID__SHIFT 0x0 |
3258 | #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 |
3259 | #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 |
3260 | #define SDMA1_STATUS2_REG__ID_MASK 0x00000003L |
3261 | #define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFFCL |
3262 | #define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L |
3263 | //SDMA1_ATOMIC_CNTL |
3264 | #define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 |
3265 | #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f |
3266 | #define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL |
3267 | #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L |
3268 | //SDMA1_ATOMIC_PREOP_LO |
3269 | #define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 |
3270 | #define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL |
3271 | //SDMA1_ATOMIC_PREOP_HI |
3272 | #define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 |
3273 | #define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL |
3274 | //SDMA1_UTCL1_CNTL |
3275 | #define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 |
3276 | #define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 |
3277 | #define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0x6 |
3278 | #define SDMA1_UTCL1_CNTL__RESP_MODE__SHIFT 0x9 |
3279 | #define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe |
3280 | #define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xf |
3281 | #define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x10 |
3282 | #define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 |
3283 | #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d |
3284 | #define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L |
3285 | #define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x0000003EL |
3286 | #define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x000001C0L |
3287 | #define SDMA1_UTCL1_CNTL__RESP_MODE_MASK 0x00000E00L |
3288 | #define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00004000L |
3289 | #define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00008000L |
3290 | #define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FF0000L |
3291 | #define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L |
3292 | #define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L |
3293 | //SDMA1_UTCL1_WATERMK |
3294 | #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 |
3295 | #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa |
3296 | #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 |
3297 | #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a |
3298 | #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL |
3299 | #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L |
3300 | #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L |
3301 | #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L |
3302 | //SDMA1_UTCL1_RD_STATUS |
3303 | #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 |
3304 | #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1 |
3305 | #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2 |
3306 | #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3 |
3307 | #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4 |
3308 | #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5 |
3309 | #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6 |
3310 | #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7 |
3311 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8 |
3312 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9 |
3313 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa |
3314 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb |
3315 | #define SDMA1_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT 0xc |
3316 | #define SDMA1_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT 0xd |
3317 | #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0xe |
3318 | #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0xf |
3319 | #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x10 |
3320 | #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x11 |
3321 | #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x15 |
3322 | #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x18 |
3323 | #define SDMA1_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT 0x19 |
3324 | #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT 0x1a |
3325 | #define SDMA1_UTCL1_RD_STATUS__HIT_CACHE__SHIFT 0x1b |
3326 | #define SDMA1_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT 0x1c |
3327 | #define SDMA1_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT 0x1d |
3328 | #define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT 0x1e |
3329 | #define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT 0x1f |
3330 | #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L |
3331 | #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L |
3332 | #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L |
3333 | #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L |
3334 | #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L |
3335 | #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L |
3336 | #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L |
3337 | #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L |
3338 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L |
3339 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L |
3340 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L |
3341 | #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L |
3342 | #define SDMA1_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L |
3343 | #define SDMA1_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK 0x00002000L |
3344 | #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00004000L |
3345 | #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00008000L |
3346 | #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00010000L |
3347 | #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x001E0000L |
3348 | #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x00E00000L |
3349 | #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x01000000L |
3350 | #define SDMA1_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK 0x02000000L |
3351 | #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK 0x04000000L |
3352 | #define SDMA1_UTCL1_RD_STATUS__HIT_CACHE_MASK 0x08000000L |
3353 | #define SDMA1_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK 0x10000000L |
3354 | #define SDMA1_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK 0x20000000L |
3355 | #define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK 0x40000000L |
3356 | #define SDMA1_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK 0x80000000L |
3357 | //SDMA1_UTCL1_WR_STATUS |
3358 | #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 |
3359 | #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1 |
3360 | #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2 |
3361 | #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3 |
3362 | #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4 |
3363 | #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5 |
3364 | #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6 |
3365 | #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7 |
3366 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8 |
3367 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9 |
3368 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa |
3369 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb |
3370 | #define SDMA1_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT 0xc |
3371 | #define SDMA1_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT 0xd |
3372 | #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0xe |
3373 | #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0xf |
3374 | #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x10 |
3375 | #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x11 |
3376 | #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x15 |
3377 | #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x18 |
3378 | #define SDMA1_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT 0x19 |
3379 | #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT 0x1a |
3380 | #define SDMA1_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT 0x1b |
3381 | #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c |
3382 | #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d |
3383 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e |
3384 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f |
3385 | #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L |
3386 | #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L |
3387 | #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L |
3388 | #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L |
3389 | #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L |
3390 | #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L |
3391 | #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L |
3392 | #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L |
3393 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L |
3394 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L |
3395 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L |
3396 | #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L |
3397 | #define SDMA1_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L |
3398 | #define SDMA1_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK 0x00002000L |
3399 | #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00004000L |
3400 | #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00008000L |
3401 | #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00010000L |
3402 | #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x001E0000L |
3403 | #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x00E00000L |
3404 | #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x01000000L |
3405 | #define SDMA1_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK 0x02000000L |
3406 | #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK 0x04000000L |
3407 | #define SDMA1_UTCL1_WR_STATUS__ATOMIC_OP_MASK 0x08000000L |
3408 | #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L |
3409 | #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L |
3410 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L |
3411 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L |
3412 | //SDMA1_UTCL1_INV0 |
3413 | #define SDMA1_UTCL1_INV0__CPF_INVREQ_EN__SHIFT 0x0 |
3414 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT 0x1 |
3415 | #define SDMA1_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT 0x2 |
3416 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT 0x3 |
3417 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT 0x4 |
3418 | #define SDMA1_UTCL1_INV0__INVREQ_SIZE__SHIFT 0x5 |
3419 | #define SDMA1_UTCL1_INV0__INVREQ_IDLE__SHIFT 0xb |
3420 | #define SDMA1_UTCL1_INV0__VMINV_PEND_CNT__SHIFT 0xc |
3421 | #define SDMA1_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT 0x10 |
3422 | #define SDMA1_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT 0x14 |
3423 | #define SDMA1_UTCL1_INV0__GPUVM_INV_MODE__SHIFT 0x18 |
3424 | #define SDMA1_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT 0x1a |
3425 | #define SDMA1_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT 0x1b |
3426 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT 0x1c |
3427 | #define SDMA1_UTCL1_INV0__CPF_INVREQ_EN_MASK 0x00000001L |
3428 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_EN_MASK 0x00000002L |
3429 | #define SDMA1_UTCL1_INV0__CPF_GPA_INVREQ_MASK 0x00000004L |
3430 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK 0x00000008L |
3431 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK 0x00000010L |
3432 | #define SDMA1_UTCL1_INV0__INVREQ_SIZE_MASK 0x000007E0L |
3433 | #define SDMA1_UTCL1_INV0__INVREQ_IDLE_MASK 0x00000800L |
3434 | #define SDMA1_UTCL1_INV0__VMINV_PEND_CNT_MASK 0x0000F000L |
3435 | #define SDMA1_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK 0x000F0000L |
3436 | #define SDMA1_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK 0x00F00000L |
3437 | #define SDMA1_UTCL1_INV0__GPUVM_INV_MODE_MASK 0x03000000L |
3438 | #define SDMA1_UTCL1_INV0__INVREQ_IS_HEAVY_MASK 0x04000000L |
3439 | #define SDMA1_UTCL1_INV0__INVREQ_FROM_CPF_MASK 0x08000000L |
3440 | #define SDMA1_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK 0xF0000000L |
3441 | //SDMA1_UTCL1_INV1 |
3442 | #define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 |
3443 | #define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL |
3444 | //SDMA1_UTCL1_INV2 |
3445 | #define SDMA1_UTCL1_INV2__INV_VMID_VEC__SHIFT 0x0 |
3446 | #define SDMA1_UTCL1_INV2__RESERVED__SHIFT 0x10 |
3447 | #define SDMA1_UTCL1_INV2__INV_VMID_VEC_MASK 0x0000FFFFL |
3448 | #define SDMA1_UTCL1_INV2__RESERVED_MASK 0xFFFF0000L |
3449 | //SDMA1_UTCL1_RD_XNACK0 |
3450 | #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 |
3451 | #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL |
3452 | //SDMA1_UTCL1_RD_XNACK1 |
3453 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 |
3454 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 |
3455 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 |
3456 | #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a |
3457 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL |
3458 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L |
3459 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L |
3460 | #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L |
3461 | //SDMA1_UTCL1_WR_XNACK0 |
3462 | #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 |
3463 | #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL |
3464 | //SDMA1_UTCL1_WR_XNACK1 |
3465 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 |
3466 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 |
3467 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 |
3468 | #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a |
3469 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL |
3470 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L |
3471 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L |
3472 | #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L |
3473 | //SDMA1_UTCL1_TIMEOUT |
3474 | #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 |
3475 | #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 |
3476 | #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL |
3477 | #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L |
3478 | //SDMA1_UTCL1_PAGE |
3479 | #define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 |
3480 | #define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 |
3481 | #define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 |
3482 | #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa |
3483 | #define SDMA1_UTCL1_PAGE__USE_IO__SHIFT 0xb |
3484 | #define SDMA1_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc |
3485 | #define SDMA1_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe |
3486 | #define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT 0x10 |
3487 | #define SDMA1_UTCL1_PAGE__USE_BC__SHIFT 0x16 |
3488 | #define SDMA1_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17 |
3489 | #define SDMA1_UTCL1_PAGE__LLC_NOALLOC__SHIFT 0x18 |
3490 | #define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L |
3491 | #define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL |
3492 | #define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000003C0L |
3493 | #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L |
3494 | #define SDMA1_UTCL1_PAGE__USE_IO_MASK 0x00000800L |
3495 | #define SDMA1_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L |
3496 | #define SDMA1_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L |
3497 | #define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE_MASK 0x003F0000L |
3498 | #define SDMA1_UTCL1_PAGE__USE_BC_MASK 0x00400000L |
3499 | #define SDMA1_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L |
3500 | #define SDMA1_UTCL1_PAGE__LLC_NOALLOC_MASK 0x01000000L |
3501 | //SDMA1_RELAX_ORDERING_LUT |
3502 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 |
3503 | #define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 |
3504 | #define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 |
3505 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 |
3506 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 |
3507 | #define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 |
3508 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 |
3509 | #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 |
3510 | #define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 |
3511 | #define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa |
3512 | #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb |
3513 | #define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc |
3514 | #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd |
3515 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe |
3516 | #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b |
3517 | #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c |
3518 | #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d |
3519 | #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e |
3520 | #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f |
3521 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L |
3522 | #define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L |
3523 | #define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L |
3524 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L |
3525 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L |
3526 | #define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L |
3527 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L |
3528 | #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L |
3529 | #define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L |
3530 | #define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L |
3531 | #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L |
3532 | #define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L |
3533 | #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L |
3534 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L |
3535 | #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L |
3536 | #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L |
3537 | #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L |
3538 | #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L |
3539 | #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L |
3540 | //SDMA1_CHICKEN_BITS_2 |
3541 | #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 |
3542 | #define SDMA1_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT 0x4 |
3543 | #define SDMA1_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE__SHIFT 0x5 |
3544 | #define SDMA1_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT 0x6 |
3545 | #define SDMA1_CHICKEN_BITS_2__RESERVED0__SHIFT 0x7 |
3546 | #define SDMA1_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN__SHIFT 0xb |
3547 | #define SDMA1_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR__SHIFT 0xf |
3548 | #define SDMA1_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT 0x10 |
3549 | #define SDMA1_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT 0x12 |
3550 | #define SDMA1_CHICKEN_BITS_2__REPEATER_FGCG_EN__SHIFT 0x14 |
3551 | #define SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x15 |
3552 | #define SDMA1_CHICKEN_BITS_2__RESERVED__SHIFT 0x16 |
3553 | #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL |
3554 | #define SDMA1_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK 0x00000010L |
3555 | #define SDMA1_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE_MASK 0x00000020L |
3556 | #define SDMA1_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK 0x00000040L |
3557 | #define SDMA1_CHICKEN_BITS_2__RESERVED0_MASK 0x00000780L |
3558 | #define SDMA1_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN_MASK 0x00007800L |
3559 | #define SDMA1_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR_MASK 0x00008000L |
3560 | #define SDMA1_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK 0x00030000L |
3561 | #define SDMA1_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK 0x000C0000L |
3562 | #define SDMA1_CHICKEN_BITS_2__REPEATER_FGCG_EN_MASK 0x00100000L |
3563 | #define SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00200000L |
3564 | #define SDMA1_CHICKEN_BITS_2__RESERVED_MASK 0xFFC00000L |
3565 | //SDMA1_STATUS3_REG |
3566 | #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 |
3567 | #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 |
3568 | #define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 |
3569 | #define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15 |
3570 | #define SDMA1_STATUS3_REG__TLBI_IDLE__SHIFT 0x16 |
3571 | #define SDMA1_STATUS3_REG__GCR_IDLE__SHIFT 0x17 |
3572 | #define SDMA1_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18 |
3573 | #define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19 |
3574 | #define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a |
3575 | #define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL |
3576 | #define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L |
3577 | #define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L |
3578 | #define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L |
3579 | #define SDMA1_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L |
3580 | #define SDMA1_STATUS3_REG__GCR_IDLE_MASK 0x00800000L |
3581 | #define SDMA1_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L |
3582 | #define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L |
3583 | #define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L |
3584 | //SDMA1_PHYSICAL_ADDR_LO |
3585 | #define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 |
3586 | #define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 |
3587 | #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 |
3588 | #define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc |
3589 | #define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L |
3590 | #define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L |
3591 | #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L |
3592 | #define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L |
3593 | //SDMA1_PHYSICAL_ADDR_HI |
3594 | #define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 |
3595 | #define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL |
3596 | //SDMA1_PHASE2_QUANTUM |
3597 | #define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 |
3598 | #define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 |
3599 | #define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e |
3600 | #define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL |
3601 | #define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L |
3602 | #define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L |
3603 | //SDMA1_ERROR_LOG |
3604 | #define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 |
3605 | #define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 |
3606 | #define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL |
3607 | #define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L |
3608 | //SDMA1_PUB_DUMMY_REG0 |
3609 | #define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 |
3610 | #define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL |
3611 | //SDMA1_PUB_DUMMY_REG1 |
3612 | #define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 |
3613 | #define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL |
3614 | //SDMA1_PUB_DUMMY_REG2 |
3615 | #define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 |
3616 | #define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL |
3617 | //SDMA1_PUB_DUMMY_REG3 |
3618 | #define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 |
3619 | #define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL |
3620 | //SDMA1_F32_COUNTER |
3621 | #define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 |
3622 | #define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL |
3623 | //SDMA1_CRD_CNTL |
3624 | #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 |
3625 | #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd |
3626 | #define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13 |
3627 | #define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19 |
3628 | #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L |
3629 | #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L |
3630 | #define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L |
3631 | #define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L |
3632 | //SDMA1_AQL_STATUS |
3633 | #define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0 |
3634 | #define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1 |
3635 | #define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L |
3636 | #define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L |
3637 | //SDMA1_EA_DBIT_ADDR_DATA |
3638 | #define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 |
3639 | #define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL |
3640 | //SDMA1_EA_DBIT_ADDR_INDEX |
3641 | #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 |
3642 | #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L |
3643 | //SDMA1_TLBI_GCR_CNTL |
3644 | #define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0 |
3645 | #define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4 |
3646 | #define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT 0x8 |
3647 | #define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10 |
3648 | #define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18 |
3649 | #define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL |
3650 | #define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L |
3651 | #define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK 0x00000F00L |
3652 | #define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L |
3653 | #define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L |
3654 | //SDMA1_TILING_CONFIG |
3655 | #define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
3656 | #define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L |
3657 | //SDMA1_INT_STATUS |
3658 | #define SDMA1_INT_STATUS__DATA__SHIFT 0x0 |
3659 | #define SDMA1_INT_STATUS__DATA_MASK 0xFFFFFFFFL |
3660 | //SDMA1_HOLE_ADDR_LO |
3661 | #define SDMA1_HOLE_ADDR_LO__VALUE__SHIFT 0x0 |
3662 | #define SDMA1_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL |
3663 | //SDMA1_HOLE_ADDR_HI |
3664 | #define SDMA1_HOLE_ADDR_HI__VALUE__SHIFT 0x0 |
3665 | #define SDMA1_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL |
3666 | //SDMA1_CLOCK_GATING_REG |
3667 | #define SDMA1_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS__SHIFT 0x0 |
3668 | #define SDMA1_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS__SHIFT 0x1 |
3669 | #define SDMA1_CLOCK_GATING_REG__CE_CLK_GATE_STATUS__SHIFT 0x2 |
3670 | #define SDMA1_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS__SHIFT 0x3 |
3671 | #define SDMA1_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS__SHIFT 0x4 |
3672 | #define SDMA1_CLOCK_GATING_REG__REG_CLK_GATE_STATUS__SHIFT 0x5 |
3673 | #define SDMA1_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS_MASK 0x00000001L |
3674 | #define SDMA1_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS_MASK 0x00000002L |
3675 | #define SDMA1_CLOCK_GATING_REG__CE_CLK_GATE_STATUS_MASK 0x00000004L |
3676 | #define SDMA1_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS_MASK 0x00000008L |
3677 | #define SDMA1_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS_MASK 0x00000010L |
3678 | #define SDMA1_CLOCK_GATING_REG__REG_CLK_GATE_STATUS_MASK 0x00000020L |
3679 | //SDMA1_STATUS4_REG |
3680 | #define SDMA1_STATUS4_REG__IDLE__SHIFT 0x0 |
3681 | #define SDMA1_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 |
3682 | #define SDMA1_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 |
3683 | #define SDMA1_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT 0x4 |
3684 | #define SDMA1_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT 0x5 |
3685 | #define SDMA1_STATUS4_REG__GCR_OUTSTANDING__SHIFT 0x6 |
3686 | #define SDMA1_STATUS4_REG__TLBI_OUTSTANDING__SHIFT 0x7 |
3687 | #define SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x8 |
3688 | #define SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x9 |
3689 | #define SDMA1_STATUS4_REG__REG_POLLING__SHIFT 0xa |
3690 | #define SDMA1_STATUS4_REG__MEM_POLLING__SHIFT 0xb |
3691 | #define SDMA1_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xc |
3692 | #define SDMA1_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xe |
3693 | #define SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 |
3694 | #define SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x14 |
3695 | #define SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x15 |
3696 | #define SDMA1_STATUS4_REG__IDLE_MASK 0x00000001L |
3697 | #define SDMA1_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L |
3698 | #define SDMA1_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L |
3699 | #define SDMA1_STATUS4_REG__CH_RD_OUTSTANDING_MASK 0x00000010L |
3700 | #define SDMA1_STATUS4_REG__CH_WR_OUTSTANDING_MASK 0x00000020L |
3701 | #define SDMA1_STATUS4_REG__GCR_OUTSTANDING_MASK 0x00000040L |
3702 | #define SDMA1_STATUS4_REG__TLBI_OUTSTANDING_MASK 0x00000080L |
3703 | #define SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000100L |
3704 | #define SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000200L |
3705 | #define SDMA1_STATUS4_REG__REG_POLLING_MASK 0x00000400L |
3706 | #define SDMA1_STATUS4_REG__MEM_POLLING_MASK 0x00000800L |
3707 | #define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00003000L |
3708 | #define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x0000C000L |
3709 | #define SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L |
3710 | #define SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00100000L |
3711 | #define SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00200000L |
3712 | //SDMA1_SCRATCH_RAM_DATA |
3713 | #define SDMA1_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 |
3714 | #define SDMA1_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL |
3715 | //SDMA1_SCRATCH_RAM_ADDR |
3716 | #define SDMA1_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 |
3717 | #define SDMA1_SCRATCH_RAM_ADDR__ADDR_MASK 0x000003FFL |
3718 | //SDMA1_TIMESTAMP_CNTL |
3719 | #define SDMA1_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 |
3720 | #define SDMA1_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L |
3721 | //SDMA1_STATUS5_REG |
3722 | #define SDMA1_STATUS5_REG__GFX_RB_ENABLE_STATUS__SHIFT 0x0 |
3723 | #define SDMA1_STATUS5_REG__PAGE_RB_ENABLE_STATUS__SHIFT 0x1 |
3724 | #define SDMA1_STATUS5_REG__RLC0_RB_ENABLE_STATUS__SHIFT 0x2 |
3725 | #define SDMA1_STATUS5_REG__RLC1_RB_ENABLE_STATUS__SHIFT 0x3 |
3726 | #define SDMA1_STATUS5_REG__RLC2_RB_ENABLE_STATUS__SHIFT 0x4 |
3727 | #define SDMA1_STATUS5_REG__RLC3_RB_ENABLE_STATUS__SHIFT 0x5 |
3728 | #define SDMA1_STATUS5_REG__RLC4_RB_ENABLE_STATUS__SHIFT 0x6 |
3729 | #define SDMA1_STATUS5_REG__RLC5_RB_ENABLE_STATUS__SHIFT 0x7 |
3730 | #define SDMA1_STATUS5_REG__RLC6_RB_ENABLE_STATUS__SHIFT 0x8 |
3731 | #define SDMA1_STATUS5_REG__RLC7_RB_ENABLE_STATUS__SHIFT 0x9 |
3732 | #define SDMA1_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 |
3733 | #define SDMA1_STATUS5_REG__GFX_RB_ENABLE_STATUS_MASK 0x00000001L |
3734 | #define SDMA1_STATUS5_REG__PAGE_RB_ENABLE_STATUS_MASK 0x00000002L |
3735 | #define SDMA1_STATUS5_REG__RLC0_RB_ENABLE_STATUS_MASK 0x00000004L |
3736 | #define SDMA1_STATUS5_REG__RLC1_RB_ENABLE_STATUS_MASK 0x00000008L |
3737 | #define SDMA1_STATUS5_REG__RLC2_RB_ENABLE_STATUS_MASK 0x00000010L |
3738 | #define SDMA1_STATUS5_REG__RLC3_RB_ENABLE_STATUS_MASK 0x00000020L |
3739 | #define SDMA1_STATUS5_REG__RLC4_RB_ENABLE_STATUS_MASK 0x00000040L |
3740 | #define SDMA1_STATUS5_REG__RLC5_RB_ENABLE_STATUS_MASK 0x00000080L |
3741 | #define SDMA1_STATUS5_REG__RLC6_RB_ENABLE_STATUS_MASK 0x00000100L |
3742 | #define SDMA1_STATUS5_REG__RLC7_RB_ENABLE_STATUS_MASK 0x00000200L |
3743 | #define SDMA1_STATUS5_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L |
3744 | //SDMA1_QUEUE_RESET_REQ |
3745 | #define SDMA1_QUEUE_RESET_REQ__GFX_QUEUE_RESET__SHIFT 0x0 |
3746 | #define SDMA1_QUEUE_RESET_REQ__PAGE_QUEUE_RESET__SHIFT 0x1 |
3747 | #define SDMA1_QUEUE_RESET_REQ__RLC0_QUEUE_RESET__SHIFT 0x2 |
3748 | #define SDMA1_QUEUE_RESET_REQ__RLC1_QUEUE_RESET__SHIFT 0x3 |
3749 | #define SDMA1_QUEUE_RESET_REQ__RLC2_QUEUE_RESET__SHIFT 0x4 |
3750 | #define SDMA1_QUEUE_RESET_REQ__RLC3_QUEUE_RESET__SHIFT 0x5 |
3751 | #define SDMA1_QUEUE_RESET_REQ__RLC4_QUEUE_RESET__SHIFT 0x6 |
3752 | #define SDMA1_QUEUE_RESET_REQ__RLC5_QUEUE_RESET__SHIFT 0x7 |
3753 | #define SDMA1_QUEUE_RESET_REQ__RLC6_QUEUE_RESET__SHIFT 0x8 |
3754 | #define SDMA1_QUEUE_RESET_REQ__RLC7_QUEUE_RESET__SHIFT 0x9 |
3755 | #define SDMA1_QUEUE_RESET_REQ__RESERVED__SHIFT 0xa |
3756 | #define SDMA1_QUEUE_RESET_REQ__GFX_QUEUE_RESET_MASK 0x00000001L |
3757 | #define SDMA1_QUEUE_RESET_REQ__PAGE_QUEUE_RESET_MASK 0x00000002L |
3758 | #define SDMA1_QUEUE_RESET_REQ__RLC0_QUEUE_RESET_MASK 0x00000004L |
3759 | #define SDMA1_QUEUE_RESET_REQ__RLC1_QUEUE_RESET_MASK 0x00000008L |
3760 | #define SDMA1_QUEUE_RESET_REQ__RLC2_QUEUE_RESET_MASK 0x00000010L |
3761 | #define SDMA1_QUEUE_RESET_REQ__RLC3_QUEUE_RESET_MASK 0x00000020L |
3762 | #define SDMA1_QUEUE_RESET_REQ__RLC4_QUEUE_RESET_MASK 0x00000040L |
3763 | #define SDMA1_QUEUE_RESET_REQ__RLC5_QUEUE_RESET_MASK 0x00000080L |
3764 | #define SDMA1_QUEUE_RESET_REQ__RLC6_QUEUE_RESET_MASK 0x00000100L |
3765 | #define SDMA1_QUEUE_RESET_REQ__RLC7_QUEUE_RESET_MASK 0x00000200L |
3766 | #define SDMA1_QUEUE_RESET_REQ__RESERVED_MASK 0xFFFFFC00L |
3767 | //SDMA1_GFX_RB_CNTL |
3768 | #define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
3769 | #define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 |
3770 | #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
3771 | #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
3772 | #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
3773 | #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
3774 | #define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 |
3775 | #define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 |
3776 | #define SDMA1_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
3777 | #define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
3778 | #define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
3779 | #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
3780 | #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
3781 | #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
3782 | #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
3783 | #define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L |
3784 | #define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L |
3785 | #define SDMA1_GFX_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
3786 | //SDMA1_GFX_RB_BASE |
3787 | #define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 |
3788 | #define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
3789 | //SDMA1_GFX_RB_BASE_HI |
3790 | #define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 |
3791 | #define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
3792 | //SDMA1_GFX_RB_RPTR |
3793 | #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 |
3794 | #define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
3795 | //SDMA1_GFX_RB_RPTR_HI |
3796 | #define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
3797 | #define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
3798 | //SDMA1_GFX_RB_WPTR |
3799 | #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 |
3800 | #define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
3801 | //SDMA1_GFX_RB_WPTR_HI |
3802 | #define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
3803 | #define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
3804 | //SDMA1_GFX_RB_WPTR_POLL_CNTL |
3805 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
3806 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
3807 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
3808 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
3809 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
3810 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
3811 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
3812 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
3813 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
3814 | #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
3815 | //SDMA1_GFX_RB_RPTR_ADDR_HI |
3816 | #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
3817 | #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3818 | //SDMA1_GFX_RB_RPTR_ADDR_LO |
3819 | #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
3820 | #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3821 | //SDMA1_GFX_IB_CNTL |
3822 | #define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
3823 | #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
3824 | #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
3825 | #define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 |
3826 | #define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
3827 | #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
3828 | #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
3829 | #define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
3830 | //SDMA1_GFX_IB_RPTR |
3831 | #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 |
3832 | #define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
3833 | //SDMA1_GFX_IB_OFFSET |
3834 | #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 |
3835 | #define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
3836 | //SDMA1_GFX_IB_BASE_LO |
3837 | #define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 |
3838 | #define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
3839 | //SDMA1_GFX_IB_BASE_HI |
3840 | #define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 |
3841 | #define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
3842 | //SDMA1_GFX_IB_SIZE |
3843 | #define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 |
3844 | #define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL |
3845 | //SDMA1_GFX_SKIP_CNTL |
3846 | #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
3847 | #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
3848 | //SDMA1_GFX_CONTEXT_STATUS |
3849 | #define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
3850 | #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
3851 | #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
3852 | #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
3853 | #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
3854 | #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
3855 | #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
3856 | #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
3857 | #define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
3858 | #define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
3859 | #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
3860 | #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
3861 | #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
3862 | #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
3863 | #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
3864 | #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
3865 | //SDMA1_GFX_DOORBELL |
3866 | #define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c |
3867 | #define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e |
3868 | #define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L |
3869 | #define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L |
3870 | //SDMA1_GFX_CONTEXT_CNTL |
3871 | #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 |
3872 | #define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 |
3873 | #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L |
3874 | #define SDMA1_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L |
3875 | //SDMA1_GFX_STATUS |
3876 | #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
3877 | #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
3878 | #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
3879 | #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
3880 | //SDMA1_GFX_DOORBELL_LOG |
3881 | #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
3882 | #define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 |
3883 | #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
3884 | #define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
3885 | //SDMA1_GFX_WATERMARK |
3886 | #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
3887 | #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
3888 | #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
3889 | #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
3890 | //SDMA1_GFX_DOORBELL_OFFSET |
3891 | #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
3892 | #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
3893 | //SDMA1_GFX_CSA_ADDR_LO |
3894 | #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
3895 | #define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3896 | //SDMA1_GFX_CSA_ADDR_HI |
3897 | #define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
3898 | #define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3899 | //SDMA1_GFX_IB_SUB_REMAIN |
3900 | #define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
3901 | #define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
3902 | //SDMA1_GFX_PREEMPT |
3903 | #define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
3904 | #define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
3905 | //SDMA1_GFX_DUMMY_REG |
3906 | #define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 |
3907 | #define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
3908 | //SDMA1_GFX_RB_WPTR_POLL_ADDR_HI |
3909 | #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
3910 | #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3911 | //SDMA1_GFX_RB_WPTR_POLL_ADDR_LO |
3912 | #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
3913 | #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3914 | //SDMA1_GFX_RB_AQL_CNTL |
3915 | #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
3916 | #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
3917 | #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
3918 | #define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
3919 | #define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
3920 | #define SDMA1_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
3921 | #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
3922 | #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
3923 | #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
3924 | #define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
3925 | #define SDMA1_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
3926 | #define SDMA1_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
3927 | //SDMA1_GFX_MINOR_PTR_UPDATE |
3928 | #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
3929 | #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
3930 | //SDMA1_GFX_MIDCMD_DATA0 |
3931 | #define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
3932 | #define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
3933 | //SDMA1_GFX_MIDCMD_DATA1 |
3934 | #define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
3935 | #define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
3936 | //SDMA1_GFX_MIDCMD_DATA2 |
3937 | #define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
3938 | #define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
3939 | //SDMA1_GFX_MIDCMD_DATA3 |
3940 | #define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
3941 | #define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
3942 | //SDMA1_GFX_MIDCMD_DATA4 |
3943 | #define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
3944 | #define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
3945 | //SDMA1_GFX_MIDCMD_DATA5 |
3946 | #define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
3947 | #define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
3948 | //SDMA1_GFX_MIDCMD_DATA6 |
3949 | #define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
3950 | #define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
3951 | //SDMA1_GFX_MIDCMD_DATA7 |
3952 | #define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
3953 | #define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
3954 | //SDMA1_GFX_MIDCMD_DATA8 |
3955 | #define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
3956 | #define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
3957 | //SDMA1_GFX_MIDCMD_DATA9 |
3958 | #define SDMA1_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
3959 | #define SDMA1_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
3960 | //SDMA1_GFX_MIDCMD_DATA10 |
3961 | #define SDMA1_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
3962 | #define SDMA1_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
3963 | //SDMA1_GFX_MIDCMD_CNTL |
3964 | #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
3965 | #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
3966 | #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
3967 | #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
3968 | #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
3969 | #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
3970 | #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
3971 | #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
3972 | //SDMA1_PAGE_RB_CNTL |
3973 | #define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
3974 | #define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 |
3975 | #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
3976 | #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
3977 | #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
3978 | #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
3979 | #define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 |
3980 | #define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 |
3981 | #define SDMA1_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
3982 | #define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
3983 | #define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
3984 | #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
3985 | #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
3986 | #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
3987 | #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
3988 | #define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L |
3989 | #define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L |
3990 | #define SDMA1_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
3991 | //SDMA1_PAGE_RB_BASE |
3992 | #define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 |
3993 | #define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
3994 | //SDMA1_PAGE_RB_BASE_HI |
3995 | #define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 |
3996 | #define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
3997 | //SDMA1_PAGE_RB_RPTR |
3998 | #define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 |
3999 | #define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4000 | //SDMA1_PAGE_RB_RPTR_HI |
4001 | #define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4002 | #define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4003 | //SDMA1_PAGE_RB_WPTR |
4004 | #define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 |
4005 | #define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4006 | //SDMA1_PAGE_RB_WPTR_HI |
4007 | #define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4008 | #define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4009 | //SDMA1_PAGE_RB_WPTR_POLL_CNTL |
4010 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
4011 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
4012 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
4013 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
4014 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
4015 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
4016 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
4017 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
4018 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
4019 | #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
4020 | //SDMA1_PAGE_RB_RPTR_ADDR_HI |
4021 | #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4022 | #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4023 | //SDMA1_PAGE_RB_RPTR_ADDR_LO |
4024 | #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4025 | #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4026 | //SDMA1_PAGE_IB_CNTL |
4027 | #define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4028 | #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4029 | #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4030 | #define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4031 | #define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4032 | #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4033 | #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4034 | #define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4035 | //SDMA1_PAGE_IB_RPTR |
4036 | #define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 |
4037 | #define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4038 | //SDMA1_PAGE_IB_OFFSET |
4039 | #define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 |
4040 | #define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4041 | //SDMA1_PAGE_IB_BASE_LO |
4042 | #define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 |
4043 | #define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4044 | //SDMA1_PAGE_IB_BASE_HI |
4045 | #define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 |
4046 | #define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4047 | //SDMA1_PAGE_IB_SIZE |
4048 | #define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 |
4049 | #define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4050 | //SDMA1_PAGE_SKIP_CNTL |
4051 | #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4052 | #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4053 | //SDMA1_PAGE_CONTEXT_STATUS |
4054 | #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4055 | #define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4056 | #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4057 | #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4058 | #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4059 | #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
4060 | #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
4061 | #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4062 | #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4063 | #define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4064 | #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4065 | #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4066 | #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4067 | #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
4068 | #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
4069 | #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4070 | //SDMA1_PAGE_DOORBELL |
4071 | #define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c |
4072 | #define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e |
4073 | #define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L |
4074 | #define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L |
4075 | //SDMA1_PAGE_STATUS |
4076 | #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
4077 | #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
4078 | #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
4079 | #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
4080 | //SDMA1_PAGE_DOORBELL_LOG |
4081 | #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
4082 | #define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 |
4083 | #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
4084 | #define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
4085 | //SDMA1_PAGE_WATERMARK |
4086 | #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
4087 | #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
4088 | #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
4089 | #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
4090 | //SDMA1_PAGE_DOORBELL_OFFSET |
4091 | #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4092 | #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4093 | //SDMA1_PAGE_CSA_ADDR_LO |
4094 | #define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4095 | #define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4096 | //SDMA1_PAGE_CSA_ADDR_HI |
4097 | #define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4098 | #define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4099 | //SDMA1_PAGE_IB_SUB_REMAIN |
4100 | #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4101 | #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4102 | //SDMA1_PAGE_PREEMPT |
4103 | #define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4104 | #define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4105 | //SDMA1_PAGE_DUMMY_REG |
4106 | #define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 |
4107 | #define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4108 | //SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI |
4109 | #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4110 | #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4111 | //SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO |
4112 | #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4113 | #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4114 | //SDMA1_PAGE_RB_AQL_CNTL |
4115 | #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4116 | #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4117 | #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4118 | #define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4119 | #define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4120 | #define SDMA1_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4121 | #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4122 | #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4123 | #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4124 | #define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4125 | #define SDMA1_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4126 | #define SDMA1_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4127 | //SDMA1_PAGE_MINOR_PTR_UPDATE |
4128 | #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4129 | #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4130 | //SDMA1_PAGE_MIDCMD_DATA0 |
4131 | #define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4132 | #define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4133 | //SDMA1_PAGE_MIDCMD_DATA1 |
4134 | #define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4135 | #define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4136 | //SDMA1_PAGE_MIDCMD_DATA2 |
4137 | #define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4138 | #define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4139 | //SDMA1_PAGE_MIDCMD_DATA3 |
4140 | #define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4141 | #define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4142 | //SDMA1_PAGE_MIDCMD_DATA4 |
4143 | #define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4144 | #define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4145 | //SDMA1_PAGE_MIDCMD_DATA5 |
4146 | #define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4147 | #define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4148 | //SDMA1_PAGE_MIDCMD_DATA6 |
4149 | #define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4150 | #define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4151 | //SDMA1_PAGE_MIDCMD_DATA7 |
4152 | #define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4153 | #define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4154 | //SDMA1_PAGE_MIDCMD_DATA8 |
4155 | #define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4156 | #define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4157 | //SDMA1_PAGE_MIDCMD_DATA9 |
4158 | #define SDMA1_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
4159 | #define SDMA1_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
4160 | //SDMA1_PAGE_MIDCMD_DATA10 |
4161 | #define SDMA1_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
4162 | #define SDMA1_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
4163 | //SDMA1_PAGE_MIDCMD_CNTL |
4164 | #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4165 | #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4166 | #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4167 | #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4168 | #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4169 | #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4170 | #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4171 | #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4172 | //SDMA1_RLC0_RB_CNTL |
4173 | #define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4174 | #define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4175 | #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4176 | #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4177 | #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4178 | #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4179 | #define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4180 | #define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 |
4181 | #define SDMA1_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
4182 | #define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4183 | #define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4184 | #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4185 | #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4186 | #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4187 | #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4188 | #define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4189 | #define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4190 | #define SDMA1_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
4191 | //SDMA1_RLC0_RB_BASE |
4192 | #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 |
4193 | #define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4194 | //SDMA1_RLC0_RB_BASE_HI |
4195 | #define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 |
4196 | #define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4197 | //SDMA1_RLC0_RB_RPTR |
4198 | #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 |
4199 | #define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4200 | //SDMA1_RLC0_RB_RPTR_HI |
4201 | #define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4202 | #define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4203 | //SDMA1_RLC0_RB_WPTR |
4204 | #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 |
4205 | #define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4206 | //SDMA1_RLC0_RB_WPTR_HI |
4207 | #define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4208 | #define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4209 | //SDMA1_RLC0_RB_WPTR_POLL_CNTL |
4210 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
4211 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
4212 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
4213 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
4214 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
4215 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
4216 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
4217 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
4218 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
4219 | #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
4220 | //SDMA1_RLC0_RB_RPTR_ADDR_HI |
4221 | #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4222 | #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4223 | //SDMA1_RLC0_RB_RPTR_ADDR_LO |
4224 | #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4225 | #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4226 | //SDMA1_RLC0_IB_CNTL |
4227 | #define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4228 | #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4229 | #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4230 | #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4231 | #define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4232 | #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4233 | #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4234 | #define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4235 | //SDMA1_RLC0_IB_RPTR |
4236 | #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 |
4237 | #define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4238 | //SDMA1_RLC0_IB_OFFSET |
4239 | #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 |
4240 | #define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4241 | //SDMA1_RLC0_IB_BASE_LO |
4242 | #define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 |
4243 | #define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4244 | //SDMA1_RLC0_IB_BASE_HI |
4245 | #define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 |
4246 | #define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4247 | //SDMA1_RLC0_IB_SIZE |
4248 | #define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 |
4249 | #define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4250 | //SDMA1_RLC0_SKIP_CNTL |
4251 | #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4252 | #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4253 | //SDMA1_RLC0_CONTEXT_STATUS |
4254 | #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4255 | #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4256 | #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4257 | #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4258 | #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4259 | #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
4260 | #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
4261 | #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4262 | #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4263 | #define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4264 | #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4265 | #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4266 | #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4267 | #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
4268 | #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
4269 | #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4270 | //SDMA1_RLC0_DOORBELL |
4271 | #define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c |
4272 | #define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e |
4273 | #define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L |
4274 | #define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L |
4275 | //SDMA1_RLC0_STATUS |
4276 | #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
4277 | #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
4278 | #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
4279 | #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
4280 | //SDMA1_RLC0_DOORBELL_LOG |
4281 | #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
4282 | #define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 |
4283 | #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
4284 | #define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
4285 | //SDMA1_RLC0_WATERMARK |
4286 | #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
4287 | #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
4288 | #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
4289 | #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
4290 | //SDMA1_RLC0_DOORBELL_OFFSET |
4291 | #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4292 | #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4293 | //SDMA1_RLC0_CSA_ADDR_LO |
4294 | #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4295 | #define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4296 | //SDMA1_RLC0_CSA_ADDR_HI |
4297 | #define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4298 | #define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4299 | //SDMA1_RLC0_IB_SUB_REMAIN |
4300 | #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4301 | #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4302 | //SDMA1_RLC0_PREEMPT |
4303 | #define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4304 | #define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4305 | //SDMA1_RLC0_DUMMY_REG |
4306 | #define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 |
4307 | #define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4308 | //SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI |
4309 | #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4310 | #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4311 | //SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO |
4312 | #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4313 | #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4314 | //SDMA1_RLC0_RB_AQL_CNTL |
4315 | #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4316 | #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4317 | #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4318 | #define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4319 | #define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4320 | #define SDMA1_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4321 | #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4322 | #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4323 | #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4324 | #define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4325 | #define SDMA1_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4326 | #define SDMA1_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4327 | //SDMA1_RLC0_MINOR_PTR_UPDATE |
4328 | #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4329 | #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4330 | //SDMA1_RLC0_MIDCMD_DATA0 |
4331 | #define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4332 | #define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4333 | //SDMA1_RLC0_MIDCMD_DATA1 |
4334 | #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4335 | #define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4336 | //SDMA1_RLC0_MIDCMD_DATA2 |
4337 | #define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4338 | #define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4339 | //SDMA1_RLC0_MIDCMD_DATA3 |
4340 | #define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4341 | #define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4342 | //SDMA1_RLC0_MIDCMD_DATA4 |
4343 | #define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4344 | #define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4345 | //SDMA1_RLC0_MIDCMD_DATA5 |
4346 | #define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4347 | #define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4348 | //SDMA1_RLC0_MIDCMD_DATA6 |
4349 | #define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4350 | #define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4351 | //SDMA1_RLC0_MIDCMD_DATA7 |
4352 | #define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4353 | #define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4354 | //SDMA1_RLC0_MIDCMD_DATA8 |
4355 | #define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4356 | #define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4357 | //SDMA1_RLC0_MIDCMD_DATA9 |
4358 | #define SDMA1_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
4359 | #define SDMA1_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
4360 | //SDMA1_RLC0_MIDCMD_DATA10 |
4361 | #define SDMA1_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
4362 | #define SDMA1_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
4363 | //SDMA1_RLC0_MIDCMD_CNTL |
4364 | #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4365 | #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4366 | #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4367 | #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4368 | #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4369 | #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4370 | #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4371 | #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4372 | //SDMA1_RLC1_RB_CNTL |
4373 | #define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4374 | #define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4375 | #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4376 | #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4377 | #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4378 | #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4379 | #define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4380 | #define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 |
4381 | #define SDMA1_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
4382 | #define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4383 | #define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4384 | #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4385 | #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4386 | #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4387 | #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4388 | #define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4389 | #define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4390 | #define SDMA1_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
4391 | //SDMA1_RLC1_RB_BASE |
4392 | #define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 |
4393 | #define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4394 | //SDMA1_RLC1_RB_BASE_HI |
4395 | #define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 |
4396 | #define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4397 | //SDMA1_RLC1_RB_RPTR |
4398 | #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 |
4399 | #define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4400 | //SDMA1_RLC1_RB_RPTR_HI |
4401 | #define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4402 | #define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4403 | //SDMA1_RLC1_RB_WPTR |
4404 | #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 |
4405 | #define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4406 | //SDMA1_RLC1_RB_WPTR_HI |
4407 | #define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4408 | #define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4409 | //SDMA1_RLC1_RB_WPTR_POLL_CNTL |
4410 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
4411 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
4412 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
4413 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
4414 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
4415 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
4416 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
4417 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
4418 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
4419 | #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
4420 | //SDMA1_RLC1_RB_RPTR_ADDR_HI |
4421 | #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4422 | #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4423 | //SDMA1_RLC1_RB_RPTR_ADDR_LO |
4424 | #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4425 | #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4426 | //SDMA1_RLC1_IB_CNTL |
4427 | #define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4428 | #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4429 | #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4430 | #define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4431 | #define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4432 | #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4433 | #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4434 | #define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4435 | //SDMA1_RLC1_IB_RPTR |
4436 | #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 |
4437 | #define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4438 | //SDMA1_RLC1_IB_OFFSET |
4439 | #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 |
4440 | #define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4441 | //SDMA1_RLC1_IB_BASE_LO |
4442 | #define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 |
4443 | #define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4444 | //SDMA1_RLC1_IB_BASE_HI |
4445 | #define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 |
4446 | #define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4447 | //SDMA1_RLC1_IB_SIZE |
4448 | #define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 |
4449 | #define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4450 | //SDMA1_RLC1_SKIP_CNTL |
4451 | #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4452 | #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4453 | //SDMA1_RLC1_CONTEXT_STATUS |
4454 | #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4455 | #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4456 | #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4457 | #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4458 | #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4459 | #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
4460 | #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
4461 | #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4462 | #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4463 | #define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4464 | #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4465 | #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4466 | #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4467 | #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
4468 | #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
4469 | #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4470 | //SDMA1_RLC1_DOORBELL |
4471 | #define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c |
4472 | #define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e |
4473 | #define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L |
4474 | #define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L |
4475 | //SDMA1_RLC1_STATUS |
4476 | #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
4477 | #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
4478 | #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
4479 | #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
4480 | //SDMA1_RLC1_DOORBELL_LOG |
4481 | #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
4482 | #define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 |
4483 | #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
4484 | #define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
4485 | //SDMA1_RLC1_WATERMARK |
4486 | #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
4487 | #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
4488 | #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
4489 | #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
4490 | //SDMA1_RLC1_DOORBELL_OFFSET |
4491 | #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4492 | #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4493 | //SDMA1_RLC1_CSA_ADDR_LO |
4494 | #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4495 | #define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4496 | //SDMA1_RLC1_CSA_ADDR_HI |
4497 | #define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4498 | #define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4499 | //SDMA1_RLC1_IB_SUB_REMAIN |
4500 | #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4501 | #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4502 | //SDMA1_RLC1_PREEMPT |
4503 | #define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4504 | #define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4505 | //SDMA1_RLC1_DUMMY_REG |
4506 | #define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 |
4507 | #define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4508 | //SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI |
4509 | #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4510 | #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4511 | //SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO |
4512 | #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4513 | #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4514 | //SDMA1_RLC1_RB_AQL_CNTL |
4515 | #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4516 | #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4517 | #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4518 | #define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4519 | #define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4520 | #define SDMA1_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4521 | #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4522 | #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4523 | #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4524 | #define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4525 | #define SDMA1_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4526 | #define SDMA1_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4527 | //SDMA1_RLC1_MINOR_PTR_UPDATE |
4528 | #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4529 | #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4530 | //SDMA1_RLC1_MIDCMD_DATA0 |
4531 | #define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4532 | #define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4533 | //SDMA1_RLC1_MIDCMD_DATA1 |
4534 | #define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4535 | #define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4536 | //SDMA1_RLC1_MIDCMD_DATA2 |
4537 | #define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4538 | #define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4539 | //SDMA1_RLC1_MIDCMD_DATA3 |
4540 | #define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4541 | #define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4542 | //SDMA1_RLC1_MIDCMD_DATA4 |
4543 | #define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4544 | #define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4545 | //SDMA1_RLC1_MIDCMD_DATA5 |
4546 | #define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4547 | #define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4548 | //SDMA1_RLC1_MIDCMD_DATA6 |
4549 | #define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4550 | #define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4551 | //SDMA1_RLC1_MIDCMD_DATA7 |
4552 | #define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4553 | #define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4554 | //SDMA1_RLC1_MIDCMD_DATA8 |
4555 | #define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4556 | #define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4557 | //SDMA1_RLC1_MIDCMD_DATA9 |
4558 | #define SDMA1_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
4559 | #define SDMA1_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
4560 | //SDMA1_RLC1_MIDCMD_DATA10 |
4561 | #define SDMA1_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
4562 | #define SDMA1_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
4563 | //SDMA1_RLC1_MIDCMD_CNTL |
4564 | #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4565 | #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4566 | #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4567 | #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4568 | #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4569 | #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4570 | #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4571 | #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4572 | //SDMA1_RLC2_RB_CNTL |
4573 | #define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4574 | #define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4575 | #define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4576 | #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4577 | #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4578 | #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4579 | #define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4580 | #define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 |
4581 | #define SDMA1_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
4582 | #define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4583 | #define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4584 | #define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4585 | #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4586 | #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4587 | #define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4588 | #define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4589 | #define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4590 | #define SDMA1_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
4591 | //SDMA1_RLC2_RB_BASE |
4592 | #define SDMA1_RLC2_RB_BASE__ADDR__SHIFT 0x0 |
4593 | #define SDMA1_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4594 | //SDMA1_RLC2_RB_BASE_HI |
4595 | #define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 |
4596 | #define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4597 | //SDMA1_RLC2_RB_RPTR |
4598 | #define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 |
4599 | #define SDMA1_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4600 | //SDMA1_RLC2_RB_RPTR_HI |
4601 | #define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4602 | #define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4603 | //SDMA1_RLC2_RB_WPTR |
4604 | #define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 |
4605 | #define SDMA1_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4606 | //SDMA1_RLC2_RB_WPTR_HI |
4607 | #define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4608 | #define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4609 | //SDMA1_RLC2_RB_WPTR_POLL_CNTL |
4610 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
4611 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
4612 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
4613 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
4614 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
4615 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
4616 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
4617 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
4618 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
4619 | #define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
4620 | //SDMA1_RLC2_RB_RPTR_ADDR_HI |
4621 | #define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4622 | #define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4623 | //SDMA1_RLC2_RB_RPTR_ADDR_LO |
4624 | #define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4625 | #define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4626 | //SDMA1_RLC2_IB_CNTL |
4627 | #define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4628 | #define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4629 | #define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4630 | #define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4631 | #define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4632 | #define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4633 | #define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4634 | #define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4635 | //SDMA1_RLC2_IB_RPTR |
4636 | #define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 |
4637 | #define SDMA1_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4638 | //SDMA1_RLC2_IB_OFFSET |
4639 | #define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 |
4640 | #define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4641 | //SDMA1_RLC2_IB_BASE_LO |
4642 | #define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 |
4643 | #define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4644 | //SDMA1_RLC2_IB_BASE_HI |
4645 | #define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 |
4646 | #define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4647 | //SDMA1_RLC2_IB_SIZE |
4648 | #define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT 0x0 |
4649 | #define SDMA1_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4650 | //SDMA1_RLC2_SKIP_CNTL |
4651 | #define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4652 | #define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4653 | //SDMA1_RLC2_CONTEXT_STATUS |
4654 | #define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4655 | #define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4656 | #define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4657 | #define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4658 | #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4659 | #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
4660 | #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
4661 | #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4662 | #define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4663 | #define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4664 | #define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4665 | #define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4666 | #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4667 | #define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
4668 | #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
4669 | #define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4670 | //SDMA1_RLC2_DOORBELL |
4671 | #define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT 0x1c |
4672 | #define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e |
4673 | #define SDMA1_RLC2_DOORBELL__ENABLE_MASK 0x10000000L |
4674 | #define SDMA1_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L |
4675 | //SDMA1_RLC2_STATUS |
4676 | #define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
4677 | #define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
4678 | #define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
4679 | #define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
4680 | //SDMA1_RLC2_DOORBELL_LOG |
4681 | #define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
4682 | #define SDMA1_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 |
4683 | #define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
4684 | #define SDMA1_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
4685 | //SDMA1_RLC2_WATERMARK |
4686 | #define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
4687 | #define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
4688 | #define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
4689 | #define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
4690 | //SDMA1_RLC2_DOORBELL_OFFSET |
4691 | #define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4692 | #define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4693 | //SDMA1_RLC2_CSA_ADDR_LO |
4694 | #define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4695 | #define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4696 | //SDMA1_RLC2_CSA_ADDR_HI |
4697 | #define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4698 | #define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4699 | //SDMA1_RLC2_IB_SUB_REMAIN |
4700 | #define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4701 | #define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4702 | //SDMA1_RLC2_PREEMPT |
4703 | #define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4704 | #define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4705 | //SDMA1_RLC2_DUMMY_REG |
4706 | #define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 |
4707 | #define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4708 | //SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI |
4709 | #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4710 | #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4711 | //SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO |
4712 | #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4713 | #define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4714 | //SDMA1_RLC2_RB_AQL_CNTL |
4715 | #define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4716 | #define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4717 | #define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4718 | #define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4719 | #define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4720 | #define SDMA1_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4721 | #define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4722 | #define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4723 | #define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4724 | #define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4725 | #define SDMA1_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4726 | #define SDMA1_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4727 | //SDMA1_RLC2_MINOR_PTR_UPDATE |
4728 | #define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4729 | #define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4730 | //SDMA1_RLC2_MIDCMD_DATA0 |
4731 | #define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4732 | #define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4733 | //SDMA1_RLC2_MIDCMD_DATA1 |
4734 | #define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4735 | #define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4736 | //SDMA1_RLC2_MIDCMD_DATA2 |
4737 | #define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4738 | #define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4739 | //SDMA1_RLC2_MIDCMD_DATA3 |
4740 | #define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4741 | #define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4742 | //SDMA1_RLC2_MIDCMD_DATA4 |
4743 | #define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4744 | #define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4745 | //SDMA1_RLC2_MIDCMD_DATA5 |
4746 | #define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4747 | #define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4748 | //SDMA1_RLC2_MIDCMD_DATA6 |
4749 | #define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4750 | #define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4751 | //SDMA1_RLC2_MIDCMD_DATA7 |
4752 | #define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4753 | #define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4754 | //SDMA1_RLC2_MIDCMD_DATA8 |
4755 | #define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4756 | #define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4757 | //SDMA1_RLC2_MIDCMD_DATA9 |
4758 | #define SDMA1_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
4759 | #define SDMA1_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
4760 | //SDMA1_RLC2_MIDCMD_DATA10 |
4761 | #define SDMA1_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
4762 | #define SDMA1_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
4763 | //SDMA1_RLC2_MIDCMD_CNTL |
4764 | #define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4765 | #define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4766 | #define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4767 | #define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4768 | #define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4769 | #define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4770 | #define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4771 | #define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4772 | //SDMA1_RLC3_RB_CNTL |
4773 | #define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4774 | #define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4775 | #define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4776 | #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4777 | #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4778 | #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4779 | #define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4780 | #define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 |
4781 | #define SDMA1_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
4782 | #define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4783 | #define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4784 | #define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4785 | #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4786 | #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4787 | #define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4788 | #define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4789 | #define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4790 | #define SDMA1_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
4791 | //SDMA1_RLC3_RB_BASE |
4792 | #define SDMA1_RLC3_RB_BASE__ADDR__SHIFT 0x0 |
4793 | #define SDMA1_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4794 | //SDMA1_RLC3_RB_BASE_HI |
4795 | #define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 |
4796 | #define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4797 | //SDMA1_RLC3_RB_RPTR |
4798 | #define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 |
4799 | #define SDMA1_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4800 | //SDMA1_RLC3_RB_RPTR_HI |
4801 | #define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4802 | #define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4803 | //SDMA1_RLC3_RB_WPTR |
4804 | #define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 |
4805 | #define SDMA1_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4806 | //SDMA1_RLC3_RB_WPTR_HI |
4807 | #define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4808 | #define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4809 | //SDMA1_RLC3_RB_WPTR_POLL_CNTL |
4810 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
4811 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
4812 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
4813 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
4814 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
4815 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
4816 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
4817 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
4818 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
4819 | #define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
4820 | //SDMA1_RLC3_RB_RPTR_ADDR_HI |
4821 | #define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4822 | #define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4823 | //SDMA1_RLC3_RB_RPTR_ADDR_LO |
4824 | #define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4825 | #define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4826 | //SDMA1_RLC3_IB_CNTL |
4827 | #define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4828 | #define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4829 | #define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4830 | #define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4831 | #define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4832 | #define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4833 | #define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4834 | #define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4835 | //SDMA1_RLC3_IB_RPTR |
4836 | #define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 |
4837 | #define SDMA1_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4838 | //SDMA1_RLC3_IB_OFFSET |
4839 | #define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 |
4840 | #define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4841 | //SDMA1_RLC3_IB_BASE_LO |
4842 | #define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 |
4843 | #define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4844 | //SDMA1_RLC3_IB_BASE_HI |
4845 | #define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 |
4846 | #define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4847 | //SDMA1_RLC3_IB_SIZE |
4848 | #define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT 0x0 |
4849 | #define SDMA1_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4850 | //SDMA1_RLC3_SKIP_CNTL |
4851 | #define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4852 | #define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4853 | //SDMA1_RLC3_CONTEXT_STATUS |
4854 | #define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4855 | #define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4856 | #define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4857 | #define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4858 | #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4859 | #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
4860 | #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
4861 | #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4862 | #define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4863 | #define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4864 | #define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4865 | #define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4866 | #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4867 | #define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
4868 | #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
4869 | #define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4870 | //SDMA1_RLC3_DOORBELL |
4871 | #define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT 0x1c |
4872 | #define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e |
4873 | #define SDMA1_RLC3_DOORBELL__ENABLE_MASK 0x10000000L |
4874 | #define SDMA1_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L |
4875 | //SDMA1_RLC3_STATUS |
4876 | #define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
4877 | #define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
4878 | #define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
4879 | #define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
4880 | //SDMA1_RLC3_DOORBELL_LOG |
4881 | #define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
4882 | #define SDMA1_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 |
4883 | #define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
4884 | #define SDMA1_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
4885 | //SDMA1_RLC3_WATERMARK |
4886 | #define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
4887 | #define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
4888 | #define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
4889 | #define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
4890 | //SDMA1_RLC3_DOORBELL_OFFSET |
4891 | #define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4892 | #define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4893 | //SDMA1_RLC3_CSA_ADDR_LO |
4894 | #define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4895 | #define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4896 | //SDMA1_RLC3_CSA_ADDR_HI |
4897 | #define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4898 | #define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4899 | //SDMA1_RLC3_IB_SUB_REMAIN |
4900 | #define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4901 | #define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4902 | //SDMA1_RLC3_PREEMPT |
4903 | #define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4904 | #define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4905 | //SDMA1_RLC3_DUMMY_REG |
4906 | #define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 |
4907 | #define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4908 | //SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI |
4909 | #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4910 | #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4911 | //SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO |
4912 | #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4913 | #define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4914 | //SDMA1_RLC3_RB_AQL_CNTL |
4915 | #define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4916 | #define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4917 | #define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4918 | #define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4919 | #define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4920 | #define SDMA1_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4921 | #define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4922 | #define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4923 | #define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4924 | #define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4925 | #define SDMA1_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4926 | #define SDMA1_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4927 | //SDMA1_RLC3_MINOR_PTR_UPDATE |
4928 | #define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4929 | #define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4930 | //SDMA1_RLC3_MIDCMD_DATA0 |
4931 | #define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4932 | #define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4933 | //SDMA1_RLC3_MIDCMD_DATA1 |
4934 | #define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4935 | #define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4936 | //SDMA1_RLC3_MIDCMD_DATA2 |
4937 | #define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4938 | #define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4939 | //SDMA1_RLC3_MIDCMD_DATA3 |
4940 | #define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4941 | #define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4942 | //SDMA1_RLC3_MIDCMD_DATA4 |
4943 | #define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4944 | #define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4945 | //SDMA1_RLC3_MIDCMD_DATA5 |
4946 | #define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4947 | #define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4948 | //SDMA1_RLC3_MIDCMD_DATA6 |
4949 | #define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4950 | #define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4951 | //SDMA1_RLC3_MIDCMD_DATA7 |
4952 | #define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4953 | #define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4954 | //SDMA1_RLC3_MIDCMD_DATA8 |
4955 | #define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4956 | #define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4957 | //SDMA1_RLC3_MIDCMD_DATA9 |
4958 | #define SDMA1_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
4959 | #define SDMA1_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
4960 | //SDMA1_RLC3_MIDCMD_DATA10 |
4961 | #define SDMA1_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
4962 | #define SDMA1_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
4963 | //SDMA1_RLC3_MIDCMD_CNTL |
4964 | #define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4965 | #define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4966 | #define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4967 | #define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4968 | #define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4969 | #define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4970 | #define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4971 | #define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4972 | //SDMA1_RLC4_RB_CNTL |
4973 | #define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4974 | #define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4975 | #define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4976 | #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4977 | #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4978 | #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4979 | #define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4980 | #define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 |
4981 | #define SDMA1_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
4982 | #define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4983 | #define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4984 | #define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4985 | #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4986 | #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4987 | #define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4988 | #define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4989 | #define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4990 | #define SDMA1_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
4991 | //SDMA1_RLC4_RB_BASE |
4992 | #define SDMA1_RLC4_RB_BASE__ADDR__SHIFT 0x0 |
4993 | #define SDMA1_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4994 | //SDMA1_RLC4_RB_BASE_HI |
4995 | #define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 |
4996 | #define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4997 | //SDMA1_RLC4_RB_RPTR |
4998 | #define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 |
4999 | #define SDMA1_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
5000 | //SDMA1_RLC4_RB_RPTR_HI |
5001 | #define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
5002 | #define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
5003 | //SDMA1_RLC4_RB_WPTR |
5004 | #define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 |
5005 | #define SDMA1_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
5006 | //SDMA1_RLC4_RB_WPTR_HI |
5007 | #define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
5008 | #define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
5009 | //SDMA1_RLC4_RB_WPTR_POLL_CNTL |
5010 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
5011 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
5012 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
5013 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
5014 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
5015 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
5016 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
5017 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
5018 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
5019 | #define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
5020 | //SDMA1_RLC4_RB_RPTR_ADDR_HI |
5021 | #define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
5022 | #define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5023 | //SDMA1_RLC4_RB_RPTR_ADDR_LO |
5024 | #define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
5025 | #define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5026 | //SDMA1_RLC4_IB_CNTL |
5027 | #define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
5028 | #define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
5029 | #define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
5030 | #define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 |
5031 | #define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
5032 | #define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
5033 | #define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
5034 | #define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
5035 | //SDMA1_RLC4_IB_RPTR |
5036 | #define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 |
5037 | #define SDMA1_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
5038 | //SDMA1_RLC4_IB_OFFSET |
5039 | #define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 |
5040 | #define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
5041 | //SDMA1_RLC4_IB_BASE_LO |
5042 | #define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 |
5043 | #define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
5044 | //SDMA1_RLC4_IB_BASE_HI |
5045 | #define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 |
5046 | #define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
5047 | //SDMA1_RLC4_IB_SIZE |
5048 | #define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT 0x0 |
5049 | #define SDMA1_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL |
5050 | //SDMA1_RLC4_SKIP_CNTL |
5051 | #define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
5052 | #define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
5053 | //SDMA1_RLC4_CONTEXT_STATUS |
5054 | #define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
5055 | #define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
5056 | #define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
5057 | #define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
5058 | #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
5059 | #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
5060 | #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
5061 | #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
5062 | #define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
5063 | #define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
5064 | #define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
5065 | #define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
5066 | #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
5067 | #define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
5068 | #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
5069 | #define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
5070 | //SDMA1_RLC4_DOORBELL |
5071 | #define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT 0x1c |
5072 | #define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e |
5073 | #define SDMA1_RLC4_DOORBELL__ENABLE_MASK 0x10000000L |
5074 | #define SDMA1_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L |
5075 | //SDMA1_RLC4_STATUS |
5076 | #define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
5077 | #define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
5078 | #define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
5079 | #define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
5080 | //SDMA1_RLC4_DOORBELL_LOG |
5081 | #define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
5082 | #define SDMA1_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 |
5083 | #define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
5084 | #define SDMA1_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
5085 | //SDMA1_RLC4_WATERMARK |
5086 | #define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
5087 | #define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
5088 | #define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
5089 | #define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
5090 | //SDMA1_RLC4_DOORBELL_OFFSET |
5091 | #define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
5092 | #define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
5093 | //SDMA1_RLC4_CSA_ADDR_LO |
5094 | #define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
5095 | #define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5096 | //SDMA1_RLC4_CSA_ADDR_HI |
5097 | #define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
5098 | #define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5099 | //SDMA1_RLC4_IB_SUB_REMAIN |
5100 | #define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
5101 | #define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
5102 | //SDMA1_RLC4_PREEMPT |
5103 | #define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
5104 | #define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
5105 | //SDMA1_RLC4_DUMMY_REG |
5106 | #define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 |
5107 | #define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
5108 | //SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI |
5109 | #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
5110 | #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5111 | //SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO |
5112 | #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
5113 | #define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5114 | //SDMA1_RLC4_RB_AQL_CNTL |
5115 | #define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
5116 | #define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
5117 | #define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
5118 | #define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
5119 | #define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
5120 | #define SDMA1_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
5121 | #define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
5122 | #define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
5123 | #define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
5124 | #define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
5125 | #define SDMA1_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
5126 | #define SDMA1_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
5127 | //SDMA1_RLC4_MINOR_PTR_UPDATE |
5128 | #define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
5129 | #define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
5130 | //SDMA1_RLC4_MIDCMD_DATA0 |
5131 | #define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
5132 | #define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
5133 | //SDMA1_RLC4_MIDCMD_DATA1 |
5134 | #define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
5135 | #define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
5136 | //SDMA1_RLC4_MIDCMD_DATA2 |
5137 | #define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
5138 | #define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
5139 | //SDMA1_RLC4_MIDCMD_DATA3 |
5140 | #define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
5141 | #define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
5142 | //SDMA1_RLC4_MIDCMD_DATA4 |
5143 | #define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
5144 | #define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
5145 | //SDMA1_RLC4_MIDCMD_DATA5 |
5146 | #define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
5147 | #define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
5148 | //SDMA1_RLC4_MIDCMD_DATA6 |
5149 | #define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
5150 | #define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
5151 | //SDMA1_RLC4_MIDCMD_DATA7 |
5152 | #define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
5153 | #define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
5154 | //SDMA1_RLC4_MIDCMD_DATA8 |
5155 | #define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
5156 | #define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
5157 | //SDMA1_RLC4_MIDCMD_DATA9 |
5158 | #define SDMA1_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
5159 | #define SDMA1_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
5160 | //SDMA1_RLC4_MIDCMD_DATA10 |
5161 | #define SDMA1_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
5162 | #define SDMA1_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
5163 | //SDMA1_RLC4_MIDCMD_CNTL |
5164 | #define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
5165 | #define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
5166 | #define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
5167 | #define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
5168 | #define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
5169 | #define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
5170 | #define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
5171 | #define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
5172 | //SDMA1_RLC5_RB_CNTL |
5173 | #define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
5174 | #define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 |
5175 | #define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
5176 | #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
5177 | #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
5178 | #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
5179 | #define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 |
5180 | #define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 |
5181 | #define SDMA1_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
5182 | #define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
5183 | #define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
5184 | #define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
5185 | #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
5186 | #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
5187 | #define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
5188 | #define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L |
5189 | #define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L |
5190 | #define SDMA1_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
5191 | //SDMA1_RLC5_RB_BASE |
5192 | #define SDMA1_RLC5_RB_BASE__ADDR__SHIFT 0x0 |
5193 | #define SDMA1_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
5194 | //SDMA1_RLC5_RB_BASE_HI |
5195 | #define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 |
5196 | #define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
5197 | //SDMA1_RLC5_RB_RPTR |
5198 | #define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 |
5199 | #define SDMA1_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
5200 | //SDMA1_RLC5_RB_RPTR_HI |
5201 | #define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
5202 | #define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
5203 | //SDMA1_RLC5_RB_WPTR |
5204 | #define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 |
5205 | #define SDMA1_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
5206 | //SDMA1_RLC5_RB_WPTR_HI |
5207 | #define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
5208 | #define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
5209 | //SDMA1_RLC5_RB_WPTR_POLL_CNTL |
5210 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
5211 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
5212 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
5213 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
5214 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
5215 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
5216 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
5217 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
5218 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
5219 | #define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
5220 | //SDMA1_RLC5_RB_RPTR_ADDR_HI |
5221 | #define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
5222 | #define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5223 | //SDMA1_RLC5_RB_RPTR_ADDR_LO |
5224 | #define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
5225 | #define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5226 | //SDMA1_RLC5_IB_CNTL |
5227 | #define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
5228 | #define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
5229 | #define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
5230 | #define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 |
5231 | #define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
5232 | #define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
5233 | #define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
5234 | #define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
5235 | //SDMA1_RLC5_IB_RPTR |
5236 | #define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 |
5237 | #define SDMA1_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
5238 | //SDMA1_RLC5_IB_OFFSET |
5239 | #define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 |
5240 | #define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
5241 | //SDMA1_RLC5_IB_BASE_LO |
5242 | #define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 |
5243 | #define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
5244 | //SDMA1_RLC5_IB_BASE_HI |
5245 | #define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 |
5246 | #define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
5247 | //SDMA1_RLC5_IB_SIZE |
5248 | #define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT 0x0 |
5249 | #define SDMA1_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL |
5250 | //SDMA1_RLC5_SKIP_CNTL |
5251 | #define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
5252 | #define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
5253 | //SDMA1_RLC5_CONTEXT_STATUS |
5254 | #define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
5255 | #define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
5256 | #define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
5257 | #define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
5258 | #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
5259 | #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
5260 | #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
5261 | #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
5262 | #define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
5263 | #define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
5264 | #define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
5265 | #define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
5266 | #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
5267 | #define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
5268 | #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
5269 | #define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
5270 | //SDMA1_RLC5_DOORBELL |
5271 | #define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT 0x1c |
5272 | #define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e |
5273 | #define SDMA1_RLC5_DOORBELL__ENABLE_MASK 0x10000000L |
5274 | #define SDMA1_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L |
5275 | //SDMA1_RLC5_STATUS |
5276 | #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
5277 | #define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
5278 | #define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
5279 | #define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
5280 | //SDMA1_RLC5_DOORBELL_LOG |
5281 | #define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
5282 | #define SDMA1_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 |
5283 | #define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
5284 | #define SDMA1_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
5285 | //SDMA1_RLC5_WATERMARK |
5286 | #define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
5287 | #define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
5288 | #define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
5289 | #define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
5290 | //SDMA1_RLC5_DOORBELL_OFFSET |
5291 | #define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
5292 | #define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
5293 | //SDMA1_RLC5_CSA_ADDR_LO |
5294 | #define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
5295 | #define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5296 | //SDMA1_RLC5_CSA_ADDR_HI |
5297 | #define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
5298 | #define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5299 | //SDMA1_RLC5_IB_SUB_REMAIN |
5300 | #define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
5301 | #define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
5302 | //SDMA1_RLC5_PREEMPT |
5303 | #define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
5304 | #define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
5305 | //SDMA1_RLC5_DUMMY_REG |
5306 | #define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 |
5307 | #define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
5308 | //SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI |
5309 | #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
5310 | #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5311 | //SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO |
5312 | #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
5313 | #define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5314 | //SDMA1_RLC5_RB_AQL_CNTL |
5315 | #define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
5316 | #define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
5317 | #define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
5318 | #define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
5319 | #define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
5320 | #define SDMA1_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
5321 | #define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
5322 | #define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
5323 | #define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
5324 | #define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
5325 | #define SDMA1_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
5326 | #define SDMA1_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
5327 | //SDMA1_RLC5_MINOR_PTR_UPDATE |
5328 | #define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
5329 | #define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
5330 | //SDMA1_RLC5_MIDCMD_DATA0 |
5331 | #define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
5332 | #define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
5333 | //SDMA1_RLC5_MIDCMD_DATA1 |
5334 | #define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
5335 | #define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
5336 | //SDMA1_RLC5_MIDCMD_DATA2 |
5337 | #define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
5338 | #define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
5339 | //SDMA1_RLC5_MIDCMD_DATA3 |
5340 | #define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
5341 | #define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
5342 | //SDMA1_RLC5_MIDCMD_DATA4 |
5343 | #define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
5344 | #define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
5345 | //SDMA1_RLC5_MIDCMD_DATA5 |
5346 | #define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
5347 | #define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
5348 | //SDMA1_RLC5_MIDCMD_DATA6 |
5349 | #define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
5350 | #define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
5351 | //SDMA1_RLC5_MIDCMD_DATA7 |
5352 | #define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
5353 | #define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
5354 | //SDMA1_RLC5_MIDCMD_DATA8 |
5355 | #define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
5356 | #define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
5357 | //SDMA1_RLC5_MIDCMD_DATA9 |
5358 | #define SDMA1_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
5359 | #define SDMA1_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
5360 | //SDMA1_RLC5_MIDCMD_DATA10 |
5361 | #define SDMA1_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
5362 | #define SDMA1_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
5363 | //SDMA1_RLC5_MIDCMD_CNTL |
5364 | #define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
5365 | #define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
5366 | #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
5367 | #define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
5368 | #define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
5369 | #define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
5370 | #define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
5371 | #define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
5372 | //SDMA1_RLC6_RB_CNTL |
5373 | #define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
5374 | #define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 |
5375 | #define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
5376 | #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
5377 | #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
5378 | #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
5379 | #define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 |
5380 | #define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 |
5381 | #define SDMA1_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
5382 | #define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
5383 | #define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
5384 | #define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
5385 | #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
5386 | #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
5387 | #define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
5388 | #define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L |
5389 | #define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L |
5390 | #define SDMA1_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
5391 | //SDMA1_RLC6_RB_BASE |
5392 | #define SDMA1_RLC6_RB_BASE__ADDR__SHIFT 0x0 |
5393 | #define SDMA1_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
5394 | //SDMA1_RLC6_RB_BASE_HI |
5395 | #define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 |
5396 | #define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
5397 | //SDMA1_RLC6_RB_RPTR |
5398 | #define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 |
5399 | #define SDMA1_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
5400 | //SDMA1_RLC6_RB_RPTR_HI |
5401 | #define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
5402 | #define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
5403 | //SDMA1_RLC6_RB_WPTR |
5404 | #define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 |
5405 | #define SDMA1_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
5406 | //SDMA1_RLC6_RB_WPTR_HI |
5407 | #define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
5408 | #define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
5409 | //SDMA1_RLC6_RB_WPTR_POLL_CNTL |
5410 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
5411 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
5412 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
5413 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
5414 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
5415 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
5416 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
5417 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
5418 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
5419 | #define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
5420 | //SDMA1_RLC6_RB_RPTR_ADDR_HI |
5421 | #define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
5422 | #define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5423 | //SDMA1_RLC6_RB_RPTR_ADDR_LO |
5424 | #define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
5425 | #define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5426 | //SDMA1_RLC6_IB_CNTL |
5427 | #define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
5428 | #define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
5429 | #define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
5430 | #define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 |
5431 | #define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
5432 | #define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
5433 | #define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
5434 | #define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
5435 | //SDMA1_RLC6_IB_RPTR |
5436 | #define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 |
5437 | #define SDMA1_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
5438 | //SDMA1_RLC6_IB_OFFSET |
5439 | #define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 |
5440 | #define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
5441 | //SDMA1_RLC6_IB_BASE_LO |
5442 | #define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 |
5443 | #define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
5444 | //SDMA1_RLC6_IB_BASE_HI |
5445 | #define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 |
5446 | #define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
5447 | //SDMA1_RLC6_IB_SIZE |
5448 | #define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT 0x0 |
5449 | #define SDMA1_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL |
5450 | //SDMA1_RLC6_SKIP_CNTL |
5451 | #define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
5452 | #define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
5453 | //SDMA1_RLC6_CONTEXT_STATUS |
5454 | #define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
5455 | #define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
5456 | #define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
5457 | #define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
5458 | #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
5459 | #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
5460 | #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
5461 | #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
5462 | #define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
5463 | #define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
5464 | #define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
5465 | #define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
5466 | #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
5467 | #define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
5468 | #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
5469 | #define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
5470 | //SDMA1_RLC6_DOORBELL |
5471 | #define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT 0x1c |
5472 | #define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e |
5473 | #define SDMA1_RLC6_DOORBELL__ENABLE_MASK 0x10000000L |
5474 | #define SDMA1_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L |
5475 | //SDMA1_RLC6_STATUS |
5476 | #define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
5477 | #define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
5478 | #define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
5479 | #define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
5480 | //SDMA1_RLC6_DOORBELL_LOG |
5481 | #define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
5482 | #define SDMA1_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 |
5483 | #define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
5484 | #define SDMA1_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
5485 | //SDMA1_RLC6_WATERMARK |
5486 | #define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
5487 | #define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
5488 | #define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
5489 | #define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
5490 | //SDMA1_RLC6_DOORBELL_OFFSET |
5491 | #define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
5492 | #define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
5493 | //SDMA1_RLC6_CSA_ADDR_LO |
5494 | #define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
5495 | #define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5496 | //SDMA1_RLC6_CSA_ADDR_HI |
5497 | #define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
5498 | #define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5499 | //SDMA1_RLC6_IB_SUB_REMAIN |
5500 | #define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
5501 | #define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
5502 | //SDMA1_RLC6_PREEMPT |
5503 | #define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
5504 | #define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
5505 | //SDMA1_RLC6_DUMMY_REG |
5506 | #define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 |
5507 | #define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
5508 | //SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI |
5509 | #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
5510 | #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5511 | //SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO |
5512 | #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
5513 | #define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5514 | //SDMA1_RLC6_RB_AQL_CNTL |
5515 | #define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
5516 | #define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
5517 | #define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
5518 | #define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
5519 | #define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
5520 | #define SDMA1_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
5521 | #define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
5522 | #define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
5523 | #define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
5524 | #define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
5525 | #define SDMA1_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
5526 | #define SDMA1_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
5527 | //SDMA1_RLC6_MINOR_PTR_UPDATE |
5528 | #define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
5529 | #define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
5530 | //SDMA1_RLC6_MIDCMD_DATA0 |
5531 | #define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
5532 | #define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
5533 | //SDMA1_RLC6_MIDCMD_DATA1 |
5534 | #define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
5535 | #define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
5536 | //SDMA1_RLC6_MIDCMD_DATA2 |
5537 | #define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
5538 | #define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
5539 | //SDMA1_RLC6_MIDCMD_DATA3 |
5540 | #define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
5541 | #define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
5542 | //SDMA1_RLC6_MIDCMD_DATA4 |
5543 | #define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
5544 | #define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
5545 | //SDMA1_RLC6_MIDCMD_DATA5 |
5546 | #define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
5547 | #define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
5548 | //SDMA1_RLC6_MIDCMD_DATA6 |
5549 | #define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
5550 | #define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
5551 | //SDMA1_RLC6_MIDCMD_DATA7 |
5552 | #define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
5553 | #define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
5554 | //SDMA1_RLC6_MIDCMD_DATA8 |
5555 | #define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
5556 | #define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
5557 | //SDMA1_RLC6_MIDCMD_DATA9 |
5558 | #define SDMA1_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
5559 | #define SDMA1_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
5560 | //SDMA1_RLC6_MIDCMD_DATA10 |
5561 | #define SDMA1_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
5562 | #define SDMA1_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
5563 | //SDMA1_RLC6_MIDCMD_CNTL |
5564 | #define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
5565 | #define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
5566 | #define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
5567 | #define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
5568 | #define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
5569 | #define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
5570 | #define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
5571 | #define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
5572 | //SDMA1_RLC7_RB_CNTL |
5573 | #define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
5574 | #define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 |
5575 | #define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
5576 | #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
5577 | #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
5578 | #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
5579 | #define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 |
5580 | #define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 |
5581 | #define SDMA1_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
5582 | #define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
5583 | #define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
5584 | #define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
5585 | #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
5586 | #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
5587 | #define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
5588 | #define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L |
5589 | #define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L |
5590 | #define SDMA1_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
5591 | //SDMA1_RLC7_RB_BASE |
5592 | #define SDMA1_RLC7_RB_BASE__ADDR__SHIFT 0x0 |
5593 | #define SDMA1_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
5594 | //SDMA1_RLC7_RB_BASE_HI |
5595 | #define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 |
5596 | #define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
5597 | //SDMA1_RLC7_RB_RPTR |
5598 | #define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 |
5599 | #define SDMA1_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
5600 | //SDMA1_RLC7_RB_RPTR_HI |
5601 | #define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
5602 | #define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
5603 | //SDMA1_RLC7_RB_WPTR |
5604 | #define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 |
5605 | #define SDMA1_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
5606 | //SDMA1_RLC7_RB_WPTR_HI |
5607 | #define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
5608 | #define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
5609 | //SDMA1_RLC7_RB_WPTR_POLL_CNTL |
5610 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
5611 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
5612 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
5613 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
5614 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
5615 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
5616 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
5617 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
5618 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
5619 | #define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
5620 | //SDMA1_RLC7_RB_RPTR_ADDR_HI |
5621 | #define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
5622 | #define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5623 | //SDMA1_RLC7_RB_RPTR_ADDR_LO |
5624 | #define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
5625 | #define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5626 | //SDMA1_RLC7_IB_CNTL |
5627 | #define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
5628 | #define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
5629 | #define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
5630 | #define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 |
5631 | #define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
5632 | #define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
5633 | #define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
5634 | #define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
5635 | //SDMA1_RLC7_IB_RPTR |
5636 | #define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 |
5637 | #define SDMA1_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
5638 | //SDMA1_RLC7_IB_OFFSET |
5639 | #define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 |
5640 | #define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
5641 | //SDMA1_RLC7_IB_BASE_LO |
5642 | #define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 |
5643 | #define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
5644 | //SDMA1_RLC7_IB_BASE_HI |
5645 | #define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 |
5646 | #define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
5647 | //SDMA1_RLC7_IB_SIZE |
5648 | #define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT 0x0 |
5649 | #define SDMA1_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL |
5650 | //SDMA1_RLC7_SKIP_CNTL |
5651 | #define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
5652 | #define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
5653 | //SDMA1_RLC7_CONTEXT_STATUS |
5654 | #define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
5655 | #define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
5656 | #define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
5657 | #define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
5658 | #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
5659 | #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
5660 | #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
5661 | #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
5662 | #define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
5663 | #define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
5664 | #define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
5665 | #define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
5666 | #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
5667 | #define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
5668 | #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
5669 | #define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
5670 | //SDMA1_RLC7_DOORBELL |
5671 | #define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT 0x1c |
5672 | #define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e |
5673 | #define SDMA1_RLC7_DOORBELL__ENABLE_MASK 0x10000000L |
5674 | #define SDMA1_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L |
5675 | //SDMA1_RLC7_STATUS |
5676 | #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
5677 | #define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
5678 | #define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
5679 | #define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
5680 | //SDMA1_RLC7_DOORBELL_LOG |
5681 | #define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
5682 | #define SDMA1_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 |
5683 | #define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
5684 | #define SDMA1_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
5685 | //SDMA1_RLC7_WATERMARK |
5686 | #define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
5687 | #define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
5688 | #define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
5689 | #define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
5690 | //SDMA1_RLC7_DOORBELL_OFFSET |
5691 | #define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
5692 | #define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
5693 | //SDMA1_RLC7_CSA_ADDR_LO |
5694 | #define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
5695 | #define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5696 | //SDMA1_RLC7_CSA_ADDR_HI |
5697 | #define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
5698 | #define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5699 | //SDMA1_RLC7_IB_SUB_REMAIN |
5700 | #define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
5701 | #define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
5702 | //SDMA1_RLC7_PREEMPT |
5703 | #define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
5704 | #define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
5705 | //SDMA1_RLC7_DUMMY_REG |
5706 | #define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 |
5707 | #define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
5708 | //SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI |
5709 | #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
5710 | #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5711 | //SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO |
5712 | #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
5713 | #define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5714 | //SDMA1_RLC7_RB_AQL_CNTL |
5715 | #define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
5716 | #define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
5717 | #define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
5718 | #define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
5719 | #define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
5720 | #define SDMA1_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
5721 | #define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
5722 | #define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
5723 | #define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
5724 | #define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
5725 | #define SDMA1_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
5726 | #define SDMA1_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
5727 | //SDMA1_RLC7_MINOR_PTR_UPDATE |
5728 | #define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
5729 | #define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
5730 | //SDMA1_RLC7_MIDCMD_DATA0 |
5731 | #define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
5732 | #define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
5733 | //SDMA1_RLC7_MIDCMD_DATA1 |
5734 | #define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
5735 | #define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
5736 | //SDMA1_RLC7_MIDCMD_DATA2 |
5737 | #define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
5738 | #define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
5739 | //SDMA1_RLC7_MIDCMD_DATA3 |
5740 | #define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
5741 | #define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
5742 | //SDMA1_RLC7_MIDCMD_DATA4 |
5743 | #define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
5744 | #define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
5745 | //SDMA1_RLC7_MIDCMD_DATA5 |
5746 | #define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
5747 | #define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
5748 | //SDMA1_RLC7_MIDCMD_DATA6 |
5749 | #define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
5750 | #define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
5751 | //SDMA1_RLC7_MIDCMD_DATA7 |
5752 | #define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
5753 | #define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
5754 | //SDMA1_RLC7_MIDCMD_DATA8 |
5755 | #define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
5756 | #define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
5757 | //SDMA1_RLC7_MIDCMD_DATA9 |
5758 | #define SDMA1_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
5759 | #define SDMA1_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
5760 | //SDMA1_RLC7_MIDCMD_DATA10 |
5761 | #define SDMA1_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
5762 | #define SDMA1_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
5763 | //SDMA1_RLC7_MIDCMD_CNTL |
5764 | #define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
5765 | #define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
5766 | #define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
5767 | #define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
5768 | #define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
5769 | #define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
5770 | #define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
5771 | #define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
5772 | |
5773 | |
5774 | // addressBlock: gc_grbmdec |
5775 | //GRBM_CNTL |
5776 | #define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 |
5777 | #define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f |
5778 | #define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL |
5779 | #define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L |
5780 | //GRBM_SKEW_CNTL |
5781 | #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 |
5782 | #define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 |
5783 | #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL |
5784 | #define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L |
5785 | //GRBM_STATUS2 |
5786 | #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 |
5787 | #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 |
5788 | #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 |
5789 | #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 |
5790 | #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 |
5791 | #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 |
5792 | #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 |
5793 | #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa |
5794 | #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb |
5795 | #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc |
5796 | #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd |
5797 | #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe |
5798 | #define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf |
5799 | #define GRBM_STATUS2__EA_BUSY__SHIFT 0x10 |
5800 | #define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11 |
5801 | #define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 |
5802 | #define GRBM_STATUS2__SDMA_SCH_RQ_PENDING__SHIFT 0x13 |
5803 | #define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14 |
5804 | #define GRBM_STATUS2__SDMA_BUSY__SHIFT 0x15 |
5805 | #define GRBM_STATUS2__SDMA0_RQ_PENDING__SHIFT 0x16 |
5806 | #define GRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x17 |
5807 | #define GRBM_STATUS2__SDMA2_RQ_PENDING__SHIFT 0x18 |
5808 | #define GRBM_STATUS2__SDMA3_RQ_PENDING__SHIFT 0x19 |
5809 | #define GRBM_STATUS2__RLC_BUSY__SHIFT 0x1a |
5810 | #define GRBM_STATUS2__TCP_BUSY__SHIFT 0x1b |
5811 | #define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c |
5812 | #define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d |
5813 | #define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e |
5814 | #define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f |
5815 | #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL |
5816 | #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L |
5817 | #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L |
5818 | #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L |
5819 | #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L |
5820 | #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L |
5821 | #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L |
5822 | #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L |
5823 | #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L |
5824 | #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L |
5825 | #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L |
5826 | #define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L |
5827 | #define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L |
5828 | #define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L |
5829 | #define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L |
5830 | #define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L |
5831 | #define GRBM_STATUS2__SDMA_SCH_RQ_PENDING_MASK 0x00080000L |
5832 | #define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L |
5833 | #define GRBM_STATUS2__SDMA_BUSY_MASK 0x00200000L |
5834 | #define GRBM_STATUS2__SDMA0_RQ_PENDING_MASK 0x00400000L |
5835 | #define GRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x00800000L |
5836 | #define GRBM_STATUS2__SDMA2_RQ_PENDING_MASK 0x01000000L |
5837 | #define GRBM_STATUS2__SDMA3_RQ_PENDING_MASK 0x02000000L |
5838 | #define GRBM_STATUS2__RLC_BUSY_MASK 0x04000000L |
5839 | #define GRBM_STATUS2__TCP_BUSY_MASK 0x08000000L |
5840 | #define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L |
5841 | #define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L |
5842 | #define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L |
5843 | #define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L |
5844 | //GRBM_PWR_CNTL |
5845 | #define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 |
5846 | #define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 |
5847 | #define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 |
5848 | #define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 |
5849 | #define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe |
5850 | #define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf |
5851 | #define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L |
5852 | #define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL |
5853 | #define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L |
5854 | #define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L |
5855 | #define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L |
5856 | #define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L |
5857 | //GRBM_STATUS |
5858 | #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 |
5859 | #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 |
5860 | #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 |
5861 | #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 |
5862 | #define GRBM_STATUS__DB_CLEAN__SHIFT 0xc |
5863 | #define GRBM_STATUS__CB_CLEAN__SHIFT 0xd |
5864 | #define GRBM_STATUS__TA_BUSY__SHIFT 0xe |
5865 | #define GRBM_STATUS__GDS_BUSY__SHIFT 0xf |
5866 | #define GRBM_STATUS__GE_BUSY_NO_DMA__SHIFT 0x10 |
5867 | #define GRBM_STATUS__SX_BUSY__SHIFT 0x14 |
5868 | #define GRBM_STATUS__GE_BUSY__SHIFT 0x15 |
5869 | #define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 |
5870 | #define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 |
5871 | #define GRBM_STATUS__SC_BUSY__SHIFT 0x18 |
5872 | #define GRBM_STATUS__PA_BUSY__SHIFT 0x19 |
5873 | #define GRBM_STATUS__DB_BUSY__SHIFT 0x1a |
5874 | #define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c |
5875 | #define GRBM_STATUS__CP_BUSY__SHIFT 0x1d |
5876 | #define GRBM_STATUS__CB_BUSY__SHIFT 0x1e |
5877 | #define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f |
5878 | #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL |
5879 | #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L |
5880 | #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L |
5881 | #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L |
5882 | #define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L |
5883 | #define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L |
5884 | #define GRBM_STATUS__TA_BUSY_MASK 0x00004000L |
5885 | #define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L |
5886 | #define GRBM_STATUS__GE_BUSY_NO_DMA_MASK 0x00010000L |
5887 | #define GRBM_STATUS__SX_BUSY_MASK 0x00100000L |
5888 | #define GRBM_STATUS__GE_BUSY_MASK 0x00200000L |
5889 | #define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L |
5890 | #define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L |
5891 | #define GRBM_STATUS__SC_BUSY_MASK 0x01000000L |
5892 | #define GRBM_STATUS__PA_BUSY_MASK 0x02000000L |
5893 | #define GRBM_STATUS__DB_BUSY_MASK 0x04000000L |
5894 | #define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L |
5895 | #define GRBM_STATUS__CP_BUSY_MASK 0x20000000L |
5896 | #define GRBM_STATUS__CB_BUSY_MASK 0x40000000L |
5897 | #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L |
5898 | //GRBM_STATUS_SE0 |
5899 | #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 |
5900 | #define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 |
5901 | #define GRBM_STATUS_SE0__UTCL1_BUSY__SHIFT 0x3 |
5902 | #define GRBM_STATUS_SE0__TCP_BUSY__SHIFT 0x4 |
5903 | #define GRBM_STATUS_SE0__GL1CC_BUSY__SHIFT 0x5 |
5904 | #define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15 |
5905 | #define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 |
5906 | #define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 |
5907 | #define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 |
5908 | #define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a |
5909 | #define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b |
5910 | #define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d |
5911 | #define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e |
5912 | #define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f |
5913 | #define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L |
5914 | #define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L |
5915 | #define GRBM_STATUS_SE0__UTCL1_BUSY_MASK 0x00000008L |
5916 | #define GRBM_STATUS_SE0__TCP_BUSY_MASK 0x00000010L |
5917 | #define GRBM_STATUS_SE0__GL1CC_BUSY_MASK 0x00000020L |
5918 | #define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L |
5919 | #define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L |
5920 | #define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L |
5921 | #define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L |
5922 | #define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L |
5923 | #define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L |
5924 | #define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L |
5925 | #define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L |
5926 | #define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L |
5927 | //GRBM_STATUS_SE1 |
5928 | #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 |
5929 | #define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 |
5930 | #define GRBM_STATUS_SE1__UTCL1_BUSY__SHIFT 0x3 |
5931 | #define GRBM_STATUS_SE1__TCP_BUSY__SHIFT 0x4 |
5932 | #define GRBM_STATUS_SE1__GL1CC_BUSY__SHIFT 0x5 |
5933 | #define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15 |
5934 | #define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 |
5935 | #define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 |
5936 | #define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 |
5937 | #define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a |
5938 | #define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b |
5939 | #define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d |
5940 | #define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e |
5941 | #define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f |
5942 | #define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L |
5943 | #define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L |
5944 | #define GRBM_STATUS_SE1__UTCL1_BUSY_MASK 0x00000008L |
5945 | #define GRBM_STATUS_SE1__TCP_BUSY_MASK 0x00000010L |
5946 | #define GRBM_STATUS_SE1__GL1CC_BUSY_MASK 0x00000020L |
5947 | #define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L |
5948 | #define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L |
5949 | #define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L |
5950 | #define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L |
5951 | #define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L |
5952 | #define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L |
5953 | #define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L |
5954 | #define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L |
5955 | #define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L |
5956 | //GRBM_STATUS3 |
5957 | #define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING__SHIFT 0x5 |
5958 | #define GRBM_STATUS3__GRBM_UTCL2_INTR_CREDIT_PENDING__SHIFT 0x6 |
5959 | #define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING__SHIFT 0x7 |
5960 | #define GRBM_STATUS3__MESPIPE0_RQ_PENDING__SHIFT 0x8 |
5961 | #define GRBM_STATUS3__MESPIPE1_RQ_PENDING__SHIFT 0x9 |
5962 | #define GRBM_STATUS3__MESPIPE2_RQ_PENDING__SHIFT 0xa |
5963 | #define GRBM_STATUS3__MESPIPE3_RQ_PENDING__SHIFT 0xb |
5964 | #define GRBM_STATUS3__PH_BUSY__SHIFT 0xd |
5965 | #define GRBM_STATUS3__CH_BUSY__SHIFT 0xe |
5966 | #define GRBM_STATUS3__GL2CC_BUSY__SHIFT 0xf |
5967 | #define GRBM_STATUS3__GL1CC_BUSY__SHIFT 0x10 |
5968 | #define GRBM_STATUS3__GUS_LINK_BUSY__SHIFT 0x1c |
5969 | #define GRBM_STATUS3__GUS_BUSY__SHIFT 0x1d |
5970 | #define GRBM_STATUS3__UTCL1_BUSY__SHIFT 0x1e |
5971 | #define GRBM_STATUS3__PMM_BUSY__SHIFT 0x1f |
5972 | #define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING_MASK 0x00000020L |
5973 | #define GRBM_STATUS3__GRBM_UTCL2_INTR_CREDIT_PENDING_MASK 0x00000040L |
5974 | #define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING_MASK 0x00000080L |
5975 | #define GRBM_STATUS3__MESPIPE0_RQ_PENDING_MASK 0x00000100L |
5976 | #define GRBM_STATUS3__MESPIPE1_RQ_PENDING_MASK 0x00000200L |
5977 | #define GRBM_STATUS3__MESPIPE2_RQ_PENDING_MASK 0x00000400L |
5978 | #define GRBM_STATUS3__MESPIPE3_RQ_PENDING_MASK 0x00000800L |
5979 | #define GRBM_STATUS3__PH_BUSY_MASK 0x00002000L |
5980 | #define GRBM_STATUS3__CH_BUSY_MASK 0x00004000L |
5981 | #define GRBM_STATUS3__GL2CC_BUSY_MASK 0x00008000L |
5982 | #define GRBM_STATUS3__GL1CC_BUSY_MASK 0x00010000L |
5983 | #define GRBM_STATUS3__GUS_LINK_BUSY_MASK 0x10000000L |
5984 | #define GRBM_STATUS3__GUS_BUSY_MASK 0x20000000L |
5985 | #define GRBM_STATUS3__UTCL1_BUSY_MASK 0x40000000L |
5986 | #define GRBM_STATUS3__PMM_BUSY_MASK 0x80000000L |
5987 | //GRBM_SOFT_RESET |
5988 | #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 |
5989 | #define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 |
5990 | #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 |
5991 | #define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 |
5992 | #define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 |
5993 | #define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 |
5994 | #define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 |
5995 | #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15 |
5996 | #define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 |
5997 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT 0x17 |
5998 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x18 |
5999 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA2__SHIFT 0x19 |
6000 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA3__SHIFT 0x1a |
6001 | #define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L |
6002 | #define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L |
6003 | #define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L |
6004 | #define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L |
6005 | #define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L |
6006 | #define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L |
6007 | #define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L |
6008 | #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L |
6009 | #define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L |
6010 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK 0x00800000L |
6011 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x01000000L |
6012 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA2_MASK 0x02000000L |
6013 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA3_MASK 0x04000000L |
6014 | //GRBM_GFX_CLKEN_CNTL |
6015 | #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 |
6016 | #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 |
6017 | #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL |
6018 | #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L |
6019 | //GRBM_WAIT_IDLE_CLOCKS |
6020 | #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 |
6021 | #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL |
6022 | //GRBM_STATUS_SE2 |
6023 | #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 |
6024 | #define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 |
6025 | #define GRBM_STATUS_SE2__UTCL1_BUSY__SHIFT 0x3 |
6026 | #define GRBM_STATUS_SE2__TCP_BUSY__SHIFT 0x4 |
6027 | #define GRBM_STATUS_SE2__GL1CC_BUSY__SHIFT 0x5 |
6028 | #define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15 |
6029 | #define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 |
6030 | #define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 |
6031 | #define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 |
6032 | #define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a |
6033 | #define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b |
6034 | #define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d |
6035 | #define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e |
6036 | #define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f |
6037 | #define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L |
6038 | #define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L |
6039 | #define GRBM_STATUS_SE2__UTCL1_BUSY_MASK 0x00000008L |
6040 | #define GRBM_STATUS_SE2__TCP_BUSY_MASK 0x00000010L |
6041 | #define GRBM_STATUS_SE2__GL1CC_BUSY_MASK 0x00000020L |
6042 | #define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L |
6043 | #define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L |
6044 | #define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L |
6045 | #define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L |
6046 | #define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L |
6047 | #define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L |
6048 | #define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L |
6049 | #define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L |
6050 | #define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L |
6051 | //GRBM_STATUS_SE3 |
6052 | #define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 |
6053 | #define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 |
6054 | #define GRBM_STATUS_SE3__UTCL1_BUSY__SHIFT 0x3 |
6055 | #define GRBM_STATUS_SE3__TCP_BUSY__SHIFT 0x4 |
6056 | #define GRBM_STATUS_SE3__GL1CC_BUSY__SHIFT 0x5 |
6057 | #define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15 |
6058 | #define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 |
6059 | #define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 |
6060 | #define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 |
6061 | #define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a |
6062 | #define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b |
6063 | #define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d |
6064 | #define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e |
6065 | #define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f |
6066 | #define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L |
6067 | #define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L |
6068 | #define GRBM_STATUS_SE3__UTCL1_BUSY_MASK 0x00000008L |
6069 | #define GRBM_STATUS_SE3__TCP_BUSY_MASK 0x00000010L |
6070 | #define GRBM_STATUS_SE3__GL1CC_BUSY_MASK 0x00000020L |
6071 | #define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L |
6072 | #define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L |
6073 | #define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L |
6074 | #define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L |
6075 | #define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L |
6076 | #define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L |
6077 | #define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L |
6078 | #define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L |
6079 | #define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L |
6080 | //GRBM_READ_ERROR |
6081 | #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 |
6082 | #define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 |
6083 | #define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 |
6084 | #define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f |
6085 | #define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL |
6086 | #define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L |
6087 | #define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L |
6088 | #define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L |
6089 | //GRBM_READ_ERROR2 |
6090 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0__SHIFT 0x9 |
6091 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1__SHIFT 0xa |
6092 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2__SHIFT 0xb |
6093 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3__SHIFT 0xc |
6094 | #define GRBM_READ_ERROR2__READ_REQUESTER_SDMA0__SHIFT 0xd |
6095 | #define GRBM_READ_ERROR2__READ_REQUESTER_SDMA1__SHIFT 0xe |
6096 | #define GRBM_READ_ERROR2__READ_REQUESTER_SDMA2__SHIFT 0xf |
6097 | #define GRBM_READ_ERROR2__READ_REQUESTER_SDMA3__SHIFT 0x10 |
6098 | #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 |
6099 | #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 |
6100 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 |
6101 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 |
6102 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 |
6103 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 |
6104 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 |
6105 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 |
6106 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a |
6107 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b |
6108 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c |
6109 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d |
6110 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e |
6111 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f |
6112 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0_MASK 0x00000200L |
6113 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1_MASK 0x00000400L |
6114 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2_MASK 0x00000800L |
6115 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3_MASK 0x00001000L |
6116 | #define GRBM_READ_ERROR2__READ_REQUESTER_SDMA0_MASK 0x00002000L |
6117 | #define GRBM_READ_ERROR2__READ_REQUESTER_SDMA1_MASK 0x00004000L |
6118 | #define GRBM_READ_ERROR2__READ_REQUESTER_SDMA2_MASK 0x00008000L |
6119 | #define GRBM_READ_ERROR2__READ_REQUESTER_SDMA3_MASK 0x00010000L |
6120 | #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L |
6121 | #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L |
6122 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L |
6123 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L |
6124 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L |
6125 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L |
6126 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L |
6127 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L |
6128 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L |
6129 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L |
6130 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L |
6131 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L |
6132 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L |
6133 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L |
6134 | //GRBM_INT_CNTL |
6135 | #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 |
6136 | #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 |
6137 | #define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L |
6138 | #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L |
6139 | //GRBM_TRAP_OP |
6140 | #define GRBM_TRAP_OP__RW__SHIFT 0x0 |
6141 | #define GRBM_TRAP_OP__RW_MASK 0x00000001L |
6142 | //GRBM_TRAP_ADDR |
6143 | #define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 |
6144 | #define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL |
6145 | //GRBM_TRAP_ADDR_MSK |
6146 | #define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 |
6147 | #define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL |
6148 | //GRBM_TRAP_WD |
6149 | #define GRBM_TRAP_WD__DATA__SHIFT 0x0 |
6150 | #define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL |
6151 | //GRBM_TRAP_WD_MSK |
6152 | #define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 |
6153 | #define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL |
6154 | //GRBM_DSM_BYPASS |
6155 | #define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 |
6156 | #define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 |
6157 | #define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L |
6158 | #define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L |
6159 | //GRBM_WRITE_ERROR |
6160 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 |
6161 | #define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 |
6162 | #define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 |
6163 | #define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc |
6164 | #define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd |
6165 | #define GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL__SHIFT 0x12 |
6166 | #define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 |
6167 | #define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 |
6168 | #define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f |
6169 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L |
6170 | #define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL |
6171 | #define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000007E0L |
6172 | #define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L |
6173 | #define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L |
6174 | #define GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL_MASK 0x00040000L |
6175 | #define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L |
6176 | #define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L |
6177 | #define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L |
6178 | //GRBM_CHIP_REVISION |
6179 | #define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 |
6180 | #define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL |
6181 | //GRBM_GFX_CNTL |
6182 | #define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 |
6183 | #define GRBM_GFX_CNTL__MEID__SHIFT 0x2 |
6184 | #define GRBM_GFX_CNTL__VMID__SHIFT 0x4 |
6185 | #define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 |
6186 | #define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L |
6187 | #define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL |
6188 | #define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L |
6189 | #define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L |
6190 | //GRBM_IH_CREDIT |
6191 | #define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 |
6192 | #define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 |
6193 | #define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L |
6194 | #define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L |
6195 | //GRBM_PWR_CNTL2 |
6196 | #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 |
6197 | #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 |
6198 | #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L |
6199 | #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L |
6200 | //GRBM_UTCL2_INVAL_RANGE_START |
6201 | #define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 |
6202 | #define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL |
6203 | //GRBM_UTCL2_INVAL_RANGE_END |
6204 | #define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 |
6205 | #define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL |
6206 | //GRBM_FENCE_RANGE0 |
6207 | #define GRBM_FENCE_RANGE0__START__SHIFT 0x0 |
6208 | #define GRBM_FENCE_RANGE0__END__SHIFT 0x10 |
6209 | #define GRBM_FENCE_RANGE0__START_MASK 0x0000FFFFL |
6210 | #define GRBM_FENCE_RANGE0__END_MASK 0xFFFF0000L |
6211 | //GRBM_FENCE_RANGE1 |
6212 | #define GRBM_FENCE_RANGE1__START__SHIFT 0x0 |
6213 | #define GRBM_FENCE_RANGE1__END__SHIFT 0x10 |
6214 | #define GRBM_FENCE_RANGE1__START_MASK 0x0000FFFFL |
6215 | #define GRBM_FENCE_RANGE1__END_MASK 0xFFFF0000L |
6216 | //GRBM_NOWHERE |
6217 | #define GRBM_NOWHERE__DATA__SHIFT 0x0 |
6218 | #define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL |
6219 | //GRBM_SCRATCH_REG0 |
6220 | #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 |
6221 | #define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL |
6222 | //GRBM_SCRATCH_REG1 |
6223 | #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 |
6224 | #define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL |
6225 | //GRBM_SCRATCH_REG2 |
6226 | #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 |
6227 | #define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL |
6228 | //GRBM_SCRATCH_REG3 |
6229 | #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 |
6230 | #define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL |
6231 | //GRBM_SCRATCH_REG4 |
6232 | #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 |
6233 | #define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL |
6234 | //GRBM_SCRATCH_REG5 |
6235 | #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 |
6236 | #define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL |
6237 | //GRBM_SCRATCH_REG6 |
6238 | #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 |
6239 | #define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL |
6240 | //GRBM_SCRATCH_REG7 |
6241 | #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 |
6242 | #define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL |
6243 | //VIOLATION_DATA_ASYNC_VF_PROG |
6244 | #define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT 0x0 |
6245 | #define VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT 0x4 |
6246 | #define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT 0x1f |
6247 | #define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK 0x0000000FL |
6248 | #define VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK 0x000003F0L |
6249 | #define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK 0x80000000L |
6250 | |
6251 | |
6252 | // addressBlock: gc_cpdec |
6253 | //CP_CPC_STATUS |
6254 | #define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 |
6255 | #define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 |
6256 | #define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 |
6257 | #define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 |
6258 | #define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 |
6259 | #define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 |
6260 | #define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 |
6261 | #define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 |
6262 | #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa |
6263 | #define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb |
6264 | #define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc |
6265 | #define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd |
6266 | #define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe |
6267 | #define CP_CPC_STATUS__GCRIU_BUSY__SHIFT 0xf |
6268 | #define CP_CPC_STATUS__MES_BUSY__SHIFT 0x10 |
6269 | #define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY__SHIFT 0x11 |
6270 | #define CP_CPC_STATUS__RCIU3_BUSY__SHIFT 0x12 |
6271 | #define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY__SHIFT 0x13 |
6272 | #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d |
6273 | #define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e |
6274 | #define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f |
6275 | #define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L |
6276 | #define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L |
6277 | #define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L |
6278 | #define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L |
6279 | #define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L |
6280 | #define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L |
6281 | #define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L |
6282 | #define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L |
6283 | #define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L |
6284 | #define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L |
6285 | #define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L |
6286 | #define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L |
6287 | #define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L |
6288 | #define CP_CPC_STATUS__GCRIU_BUSY_MASK 0x00008000L |
6289 | #define CP_CPC_STATUS__MES_BUSY_MASK 0x00010000L |
6290 | #define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY_MASK 0x00020000L |
6291 | #define CP_CPC_STATUS__RCIU3_BUSY_MASK 0x00040000L |
6292 | #define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY_MASK 0x00080000L |
6293 | #define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L |
6294 | #define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L |
6295 | #define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L |
6296 | //CP_CPC_BUSY_STAT |
6297 | #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 |
6298 | #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 |
6299 | #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 |
6300 | #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 |
6301 | #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 |
6302 | #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 |
6303 | #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 |
6304 | #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 |
6305 | #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 |
6306 | #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 |
6307 | #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa |
6308 | #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb |
6309 | #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc |
6310 | #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd |
6311 | #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 |
6312 | #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 |
6313 | #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 |
6314 | #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 |
6315 | #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 |
6316 | #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 |
6317 | #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 |
6318 | #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 |
6319 | #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 |
6320 | #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 |
6321 | #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a |
6322 | #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b |
6323 | #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c |
6324 | #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d |
6325 | #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L |
6326 | #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L |
6327 | #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L |
6328 | #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L |
6329 | #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L |
6330 | #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L |
6331 | #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L |
6332 | #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L |
6333 | #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L |
6334 | #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L |
6335 | #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L |
6336 | #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L |
6337 | #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L |
6338 | #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L |
6339 | #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L |
6340 | #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L |
6341 | #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L |
6342 | #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L |
6343 | #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L |
6344 | #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L |
6345 | #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L |
6346 | #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L |
6347 | #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L |
6348 | #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L |
6349 | #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L |
6350 | #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L |
6351 | #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L |
6352 | #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L |
6353 | //CP_CPC_STALLED_STAT1 |
6354 | #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 |
6355 | #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 |
6356 | #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 |
6357 | #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 |
6358 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 |
6359 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa |
6360 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd |
6361 | #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 |
6362 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 |
6363 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 |
6364 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 |
6365 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 |
6366 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 |
6367 | #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 |
6368 | #define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE__SHIFT 0x19 |
6369 | #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L |
6370 | #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L |
6371 | #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L |
6372 | #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L |
6373 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L |
6374 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L |
6375 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L |
6376 | #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L |
6377 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L |
6378 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L |
6379 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L |
6380 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L |
6381 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L |
6382 | #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L |
6383 | #define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE_MASK 0x02000000L |
6384 | //CP_CPF_STATUS |
6385 | #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 |
6386 | #define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 |
6387 | #define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 |
6388 | #define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 |
6389 | #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 |
6390 | #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 |
6391 | #define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 |
6392 | #define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 |
6393 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa |
6394 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb |
6395 | #define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc |
6396 | #define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd |
6397 | #define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe |
6398 | #define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf |
6399 | #define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 |
6400 | #define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 |
6401 | #define CP_CPF_STATUS__RCIU_BUSY__SHIFT 0x12 |
6402 | #define CP_CPF_STATUS__RCIU_GFX_BUSY__SHIFT 0x13 |
6403 | #define CP_CPF_STATUS__RCIU_CMP_BUSY__SHIFT 0x14 |
6404 | #define CP_CPF_STATUS__ROQ_DATA_BUSY__SHIFT 0x15 |
6405 | #define CP_CPF_STATUS__ROQ_CE_DATA_BUSY__SHIFT 0x16 |
6406 | #define CP_CPF_STATUS__GCRIU_BUSY__SHIFT 0x17 |
6407 | #define CP_CPF_STATUS__MES_HQD_BUSY__SHIFT 0x18 |
6408 | #define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a |
6409 | #define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b |
6410 | #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c |
6411 | #define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e |
6412 | #define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f |
6413 | #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L |
6414 | #define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L |
6415 | #define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L |
6416 | #define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L |
6417 | #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L |
6418 | #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L |
6419 | #define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L |
6420 | #define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L |
6421 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L |
6422 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L |
6423 | #define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L |
6424 | #define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L |
6425 | #define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L |
6426 | #define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L |
6427 | #define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L |
6428 | #define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L |
6429 | #define CP_CPF_STATUS__RCIU_BUSY_MASK 0x00040000L |
6430 | #define CP_CPF_STATUS__RCIU_GFX_BUSY_MASK 0x00080000L |
6431 | #define CP_CPF_STATUS__RCIU_CMP_BUSY_MASK 0x00100000L |
6432 | #define CP_CPF_STATUS__ROQ_DATA_BUSY_MASK 0x00200000L |
6433 | #define CP_CPF_STATUS__ROQ_CE_DATA_BUSY_MASK 0x00400000L |
6434 | #define CP_CPF_STATUS__GCRIU_BUSY_MASK 0x00800000L |
6435 | #define CP_CPF_STATUS__MES_HQD_BUSY_MASK 0x01000000L |
6436 | #define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L |
6437 | #define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L |
6438 | #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L |
6439 | #define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L |
6440 | #define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L |
6441 | //CP_CPF_BUSY_STAT |
6442 | #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 |
6443 | #define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 |
6444 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 |
6445 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 |
6446 | #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 |
6447 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 |
6448 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 |
6449 | #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 |
6450 | #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 |
6451 | #define CP_CPF_BUSY_STAT__CSF_DATA_BUSY__SHIFT 0x9 |
6452 | #define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY__SHIFT 0xa |
6453 | #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb |
6454 | #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc |
6455 | #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd |
6456 | #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe |
6457 | #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf |
6458 | #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 |
6459 | #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 |
6460 | #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 |
6461 | #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 |
6462 | #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 |
6463 | #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 |
6464 | #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 |
6465 | #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 |
6466 | #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 |
6467 | #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 |
6468 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a |
6469 | #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b |
6470 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c |
6471 | #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d |
6472 | #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e |
6473 | #define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f |
6474 | #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L |
6475 | #define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L |
6476 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L |
6477 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L |
6478 | #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L |
6479 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L |
6480 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L |
6481 | #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L |
6482 | #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L |
6483 | #define CP_CPF_BUSY_STAT__CSF_DATA_BUSY_MASK 0x00000200L |
6484 | #define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY_MASK 0x00000400L |
6485 | #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L |
6486 | #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L |
6487 | #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L |
6488 | #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L |
6489 | #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L |
6490 | #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L |
6491 | #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L |
6492 | #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L |
6493 | #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L |
6494 | #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L |
6495 | #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L |
6496 | #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L |
6497 | #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L |
6498 | #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L |
6499 | #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L |
6500 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L |
6501 | #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L |
6502 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L |
6503 | #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L |
6504 | #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L |
6505 | #define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L |
6506 | //CP_CPF_STALLED_STAT1 |
6507 | #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 |
6508 | #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 |
6509 | #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 |
6510 | #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 |
6511 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 |
6512 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 |
6513 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 |
6514 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 |
6515 | #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 |
6516 | #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa |
6517 | #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb |
6518 | #define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA__SHIFT 0xc |
6519 | #define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE__SHIFT 0xd |
6520 | #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L |
6521 | #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L |
6522 | #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L |
6523 | #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L |
6524 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L |
6525 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L |
6526 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L |
6527 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L |
6528 | #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L |
6529 | #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L |
6530 | #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L |
6531 | #define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA_MASK 0x00001000L |
6532 | #define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE_MASK 0x00002000L |
6533 | //CP_CPC_BUSY_STAT2 |
6534 | #define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY__SHIFT 0x0 |
6535 | #define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY__SHIFT 0x2 |
6536 | #define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY__SHIFT 0x3 |
6537 | #define CP_CPC_BUSY_STAT2__MES_TC_BUSY__SHIFT 0x7 |
6538 | #define CP_CPC_BUSY_STAT2__MES_DMA_BUSY__SHIFT 0x8 |
6539 | #define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT 0xa |
6540 | #define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY__SHIFT 0xb |
6541 | #define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY__SHIFT 0xc |
6542 | #define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY__SHIFT 0xd |
6543 | #define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY_MASK 0x00000001L |
6544 | #define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY_MASK 0x00000004L |
6545 | #define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY_MASK 0x00000008L |
6546 | #define CP_CPC_BUSY_STAT2__MES_TC_BUSY_MASK 0x00000080L |
6547 | #define CP_CPC_BUSY_STAT2__MES_DMA_BUSY_MASK 0x00000100L |
6548 | #define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY_MASK 0x00000400L |
6549 | #define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY_MASK 0x00000800L |
6550 | #define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY_MASK 0x00001000L |
6551 | #define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY_MASK 0x00002000L |
6552 | //CP_CPC_GRBM_FREE_COUNT |
6553 | #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
6554 | #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL |
6555 | //CP_CPC_PRIV_VIOLATION_ADDR |
6556 | #define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x0 |
6557 | #define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0000FFFFL |
6558 | //CP_MEC_ME1_HEADER_DUMP |
6559 | #define 0x0 |
6560 | #define 0xFFFFFFFFL |
6561 | //CP_MEC_ME2_HEADER_DUMP |
6562 | #define 0x0 |
6563 | #define 0xFFFFFFFFL |
6564 | //CP_CPC_SCRATCH_INDEX |
6565 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 |
6566 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f |
6567 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL |
6568 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L |
6569 | //CP_CPC_SCRATCH_DATA |
6570 | #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 |
6571 | #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL |
6572 | //CP_CPF_GRBM_FREE_COUNT |
6573 | #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
6574 | #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L |
6575 | //CP_CPF_BUSY_STAT2 |
6576 | #define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY__SHIFT 0xc |
6577 | #define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe |
6578 | #define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY__SHIFT 0x11 |
6579 | #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY__SHIFT 0x12 |
6580 | #define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 |
6581 | #define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY__SHIFT 0x17 |
6582 | #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 |
6583 | #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY__SHIFT 0x1b |
6584 | #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY__SHIFT 0x1e |
6585 | #define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY_MASK 0x00001000L |
6586 | #define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L |
6587 | #define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY_MASK 0x00020000L |
6588 | #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY_MASK 0x00040000L |
6589 | #define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L |
6590 | #define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY_MASK 0x00800000L |
6591 | #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L |
6592 | #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY_MASK 0x08000000L |
6593 | #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY_MASK 0x40000000L |
6594 | //CONFIG_RESERVED_REG0 |
6595 | #define CONFIG_RESERVED_REG0__DATA__SHIFT 0x0 |
6596 | #define CONFIG_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL |
6597 | //CONFIG_RESERVED_REG1 |
6598 | #define CONFIG_RESERVED_REG1__DATA__SHIFT 0x0 |
6599 | #define CONFIG_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL |
6600 | //CP_CPC_HALT_HYST_COUNT |
6601 | #define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 |
6602 | #define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL |
6603 | //CP_CE_COMPARE_COUNT |
6604 | #define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 |
6605 | #define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL |
6606 | //CP_CE_DE_COUNT |
6607 | #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 |
6608 | #define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL |
6609 | //CP_DE_CE_COUNT |
6610 | #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 |
6611 | #define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL |
6612 | //CP_DE_LAST_INVAL_COUNT |
6613 | #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 |
6614 | #define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL |
6615 | //CP_DE_DE_COUNT |
6616 | #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 |
6617 | #define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL |
6618 | //CP_STALLED_STAT3 |
6619 | #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 |
6620 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 |
6621 | #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 |
6622 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 |
6623 | #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 |
6624 | #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 |
6625 | #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 |
6626 | #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 |
6627 | #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa |
6628 | #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb |
6629 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc |
6630 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd |
6631 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe |
6632 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf |
6633 | #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 |
6634 | #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 |
6635 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 |
6636 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 |
6637 | #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 |
6638 | #define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE__SHIFT 0x15 |
6639 | #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L |
6640 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L |
6641 | #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L |
6642 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L |
6643 | #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L |
6644 | #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L |
6645 | #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L |
6646 | #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L |
6647 | #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L |
6648 | #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L |
6649 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L |
6650 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L |
6651 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L |
6652 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L |
6653 | #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L |
6654 | #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L |
6655 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L |
6656 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L |
6657 | #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L |
6658 | #define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE_MASK 0x00200000L |
6659 | //CP_STALLED_STAT1 |
6660 | #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 |
6661 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R0__SHIFT 0x2 |
6662 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R1__SHIFT 0x3 |
6663 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0__SHIFT 0x4 |
6664 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1__SHIFT 0x5 |
6665 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa |
6666 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb |
6667 | #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc |
6668 | #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd |
6669 | #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe |
6670 | #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf |
6671 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 |
6672 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 |
6673 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 |
6674 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a |
6675 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b |
6676 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c |
6677 | #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d |
6678 | #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L |
6679 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R0_MASK 0x00000004L |
6680 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R1_MASK 0x00000008L |
6681 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0_MASK 0x00000010L |
6682 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1_MASK 0x00000020L |
6683 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L |
6684 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L |
6685 | #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L |
6686 | #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L |
6687 | #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L |
6688 | #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L |
6689 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L |
6690 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L |
6691 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L |
6692 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L |
6693 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L |
6694 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L |
6695 | #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L |
6696 | //CP_STALLED_STAT2 |
6697 | #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 |
6698 | #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 |
6699 | #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 |
6700 | #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 |
6701 | #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 |
6702 | #define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV__SHIFT 0x6 |
6703 | #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 |
6704 | #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 |
6705 | #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa |
6706 | #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb |
6707 | #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc |
6708 | #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd |
6709 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe |
6710 | #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf |
6711 | #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 |
6712 | #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 |
6713 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 |
6714 | #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 |
6715 | #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 |
6716 | #define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE__SHIFT 0x15 |
6717 | #define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM__SHIFT 0x16 |
6718 | #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 |
6719 | #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 |
6720 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 |
6721 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a |
6722 | #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b |
6723 | #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c |
6724 | #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d |
6725 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e |
6726 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f |
6727 | #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L |
6728 | #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L |
6729 | #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L |
6730 | #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L |
6731 | #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L |
6732 | #define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV_MASK 0x00000040L |
6733 | #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L |
6734 | #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L |
6735 | #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L |
6736 | #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L |
6737 | #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L |
6738 | #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L |
6739 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L |
6740 | #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L |
6741 | #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L |
6742 | #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L |
6743 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L |
6744 | #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L |
6745 | #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L |
6746 | #define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE_MASK 0x00200000L |
6747 | #define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM_MASK 0x00400000L |
6748 | #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L |
6749 | #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L |
6750 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L |
6751 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L |
6752 | #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L |
6753 | #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L |
6754 | #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L |
6755 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L |
6756 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L |
6757 | //CP_BUSY_STAT |
6758 | #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 |
6759 | #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 |
6760 | #define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 |
6761 | #define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 |
6762 | #define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 |
6763 | #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa |
6764 | #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc |
6765 | #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd |
6766 | #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe |
6767 | #define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf |
6768 | #define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 |
6769 | #define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 |
6770 | #define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 |
6771 | #define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 |
6772 | #define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 |
6773 | #define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 |
6774 | #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L |
6775 | #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L |
6776 | #define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L |
6777 | #define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L |
6778 | #define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L |
6779 | #define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L |
6780 | #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L |
6781 | #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L |
6782 | #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L |
6783 | #define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L |
6784 | #define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L |
6785 | #define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L |
6786 | #define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L |
6787 | #define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L |
6788 | #define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L |
6789 | #define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L |
6790 | //CP_STAT |
6791 | #define CP_STAT__ROQ_DB_BUSY__SHIFT 0x5 |
6792 | #define CP_STAT__ROQ_CE_DB_BUSY__SHIFT 0x6 |
6793 | #define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 |
6794 | #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa |
6795 | #define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb |
6796 | #define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc |
6797 | #define CP_STAT__DC_BUSY__SHIFT 0xd |
6798 | #define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe |
6799 | #define CP_STAT__PFP_BUSY__SHIFT 0xf |
6800 | #define CP_STAT__MEQ_BUSY__SHIFT 0x10 |
6801 | #define CP_STAT__ME_BUSY__SHIFT 0x11 |
6802 | #define CP_STAT__QUERY_BUSY__SHIFT 0x12 |
6803 | #define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 |
6804 | #define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 |
6805 | #define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 |
6806 | #define CP_STAT__DMA_BUSY__SHIFT 0x16 |
6807 | #define CP_STAT__RCIU_BUSY__SHIFT 0x17 |
6808 | #define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 |
6809 | #define CP_STAT__GCRIU_BUSY__SHIFT 0x19 |
6810 | #define CP_STAT__CE_BUSY__SHIFT 0x1a |
6811 | #define CP_STAT__TCIU_BUSY__SHIFT 0x1b |
6812 | #define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c |
6813 | #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d |
6814 | #define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e |
6815 | #define CP_STAT__CP_BUSY__SHIFT 0x1f |
6816 | #define CP_STAT__ROQ_DB_BUSY_MASK 0x00000020L |
6817 | #define CP_STAT__ROQ_CE_DB_BUSY_MASK 0x00000040L |
6818 | #define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L |
6819 | #define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L |
6820 | #define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L |
6821 | #define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L |
6822 | #define CP_STAT__DC_BUSY_MASK 0x00002000L |
6823 | #define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L |
6824 | #define CP_STAT__PFP_BUSY_MASK 0x00008000L |
6825 | #define CP_STAT__MEQ_BUSY_MASK 0x00010000L |
6826 | #define CP_STAT__ME_BUSY_MASK 0x00020000L |
6827 | #define CP_STAT__QUERY_BUSY_MASK 0x00040000L |
6828 | #define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L |
6829 | #define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L |
6830 | #define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L |
6831 | #define CP_STAT__DMA_BUSY_MASK 0x00400000L |
6832 | #define CP_STAT__RCIU_BUSY_MASK 0x00800000L |
6833 | #define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L |
6834 | #define CP_STAT__GCRIU_BUSY_MASK 0x02000000L |
6835 | #define CP_STAT__CE_BUSY_MASK 0x04000000L |
6836 | #define CP_STAT__TCIU_BUSY_MASK 0x08000000L |
6837 | #define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L |
6838 | #define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L |
6839 | #define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L |
6840 | #define CP_STAT__CP_BUSY_MASK 0x80000000L |
6841 | //CP_ME_HEADER_DUMP |
6842 | #define 0x0 |
6843 | #define 0xFFFFFFFFL |
6844 | //CP_PFP_HEADER_DUMP |
6845 | #define 0x0 |
6846 | #define 0xFFFFFFFFL |
6847 | //CP_GRBM_FREE_COUNT |
6848 | #define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
6849 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 |
6850 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 |
6851 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL |
6852 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L |
6853 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L |
6854 | //CP_CE_HEADER_DUMP |
6855 | #define 0x0 |
6856 | #define 0xFFFFFFFFL |
6857 | //CP_PFP_INSTR_PNTR |
6858 | #define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
6859 | #define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
6860 | //CP_ME_INSTR_PNTR |
6861 | #define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
6862 | #define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
6863 | //CP_CE_INSTR_PNTR |
6864 | #define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
6865 | #define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
6866 | //CP_MEC1_INSTR_PNTR |
6867 | #define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
6868 | #define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
6869 | //CP_MEC2_INSTR_PNTR |
6870 | #define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
6871 | #define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
6872 | //CP_CSF_STAT |
6873 | #define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 |
6874 | #define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L |
6875 | //CP_MEC_CNTL |
6876 | #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 |
6877 | #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 |
6878 | #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 |
6879 | #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 |
6880 | #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 |
6881 | #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 |
6882 | #define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET__SHIFT 0x16 |
6883 | #define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET__SHIFT 0x17 |
6884 | #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x1b |
6885 | #define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c |
6886 | #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d |
6887 | #define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e |
6888 | #define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f |
6889 | #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L |
6890 | #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L |
6891 | #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L |
6892 | #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L |
6893 | #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L |
6894 | #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L |
6895 | #define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET_MASK 0x00400000L |
6896 | #define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET_MASK 0x00800000L |
6897 | #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x08000000L |
6898 | #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L |
6899 | #define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L |
6900 | #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L |
6901 | #define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L |
6902 | //CP_ME_CNTL |
6903 | #define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 |
6904 | #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 |
6905 | #define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 |
6906 | #define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 |
6907 | #define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 |
6908 | #define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 |
6909 | #define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 |
6910 | #define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 |
6911 | #define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 |
6912 | #define CP_ME_CNTL__CE_HALT__SHIFT 0x18 |
6913 | #define CP_ME_CNTL__CE_STEP__SHIFT 0x19 |
6914 | #define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a |
6915 | #define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b |
6916 | #define CP_ME_CNTL__ME_HALT__SHIFT 0x1c |
6917 | #define CP_ME_CNTL__ME_STEP__SHIFT 0x1d |
6918 | #define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L |
6919 | #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L |
6920 | #define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L |
6921 | #define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L |
6922 | #define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L |
6923 | #define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L |
6924 | #define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L |
6925 | #define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L |
6926 | #define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L |
6927 | #define CP_ME_CNTL__CE_HALT_MASK 0x01000000L |
6928 | #define CP_ME_CNTL__CE_STEP_MASK 0x02000000L |
6929 | #define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L |
6930 | #define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L |
6931 | #define CP_ME_CNTL__ME_HALT_MASK 0x10000000L |
6932 | #define CP_ME_CNTL__ME_STEP_MASK 0x20000000L |
6933 | //CP_CNTX_STAT |
6934 | #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 |
6935 | #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 |
6936 | #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 |
6937 | #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c |
6938 | #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL |
6939 | #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L |
6940 | #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L |
6941 | #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L |
6942 | //CP_ME_PREEMPTION |
6943 | #define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 |
6944 | #define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L |
6945 | //CP_ROQ_THRESHOLDS |
6946 | #define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 |
6947 | #define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 |
6948 | #define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL |
6949 | #define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L |
6950 | //CP_MEQ_STQ_THRESHOLD |
6951 | #define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 |
6952 | #define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL |
6953 | //CP_RB2_RPTR |
6954 | #define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 |
6955 | #define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL |
6956 | //CP_RB1_RPTR |
6957 | #define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 |
6958 | #define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL |
6959 | //CP_RB0_RPTR |
6960 | #define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 |
6961 | #define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL |
6962 | //CP_RB_RPTR |
6963 | #define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 |
6964 | #define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL |
6965 | //CP_RB_WPTR_DELAY |
6966 | #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 |
6967 | #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c |
6968 | #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL |
6969 | #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L |
6970 | //CP_RB_WPTR_POLL_CNTL |
6971 | #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 |
6972 | #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
6973 | #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL |
6974 | #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
6975 | //CP_ROQ1_THRESHOLDS |
6976 | #define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 |
6977 | #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0xa |
6978 | #define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x14 |
6979 | #define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000003FFL |
6980 | #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x000FFC00L |
6981 | #define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0x3FF00000L |
6982 | //CP_ROQ2_THRESHOLDS |
6983 | #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x0 |
6984 | #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0xa |
6985 | #define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x000003FFL |
6986 | #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x000FFC00L |
6987 | //CP_STQ_THRESHOLDS |
6988 | #define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 |
6989 | #define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 |
6990 | #define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 |
6991 | #define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL |
6992 | #define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L |
6993 | #define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L |
6994 | //CP_QUEUE_THRESHOLDS |
6995 | #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 |
6996 | #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 |
6997 | #define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL |
6998 | #define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L |
6999 | //CP_MEQ_THRESHOLDS |
7000 | #define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 |
7001 | #define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 |
7002 | #define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL |
7003 | #define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L |
7004 | //CP_ROQ_AVAIL |
7005 | #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 |
7006 | #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 |
7007 | #define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x00000FFFL |
7008 | #define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x0FFF0000L |
7009 | //CP_STQ_AVAIL |
7010 | #define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 |
7011 | #define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL |
7012 | //CP_ROQ2_AVAIL |
7013 | #define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 |
7014 | #define CP_ROQ2_AVAIL__ROQ_CNT_DB__SHIFT 0x10 |
7015 | #define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x00000FFFL |
7016 | #define CP_ROQ2_AVAIL__ROQ_CNT_DB_MASK 0x0FFF0000L |
7017 | //CP_MEQ_AVAIL |
7018 | #define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 |
7019 | #define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL |
7020 | //CP_CMD_INDEX |
7021 | #define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 |
7022 | #define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc |
7023 | #define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 |
7024 | #define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL |
7025 | #define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L |
7026 | #define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L |
7027 | //CP_CMD_DATA |
7028 | #define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 |
7029 | #define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL |
7030 | //CP_ROQ_RB_STAT |
7031 | #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 |
7032 | #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 |
7033 | #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x00000FFFL |
7034 | #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x0FFF0000L |
7035 | //CP_ROQ_IB1_STAT |
7036 | #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 |
7037 | #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 |
7038 | #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x00000FFFL |
7039 | #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x0FFF0000L |
7040 | //CP_ROQ_IB2_STAT |
7041 | #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 |
7042 | #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 |
7043 | #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x00000FFFL |
7044 | #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x0FFF0000L |
7045 | //CP_STQ_STAT |
7046 | #define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 |
7047 | #define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL |
7048 | //CP_STQ_WR_STAT |
7049 | #define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 |
7050 | #define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL |
7051 | //CP_MEQ_STAT |
7052 | #define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 |
7053 | #define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 |
7054 | #define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL |
7055 | #define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L |
7056 | //CP_CEQ1_AVAIL |
7057 | #define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 |
7058 | #define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 |
7059 | #define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x00000FFFL |
7060 | #define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x0FFF0000L |
7061 | //CP_CEQ2_AVAIL |
7062 | #define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 |
7063 | #define CP_CEQ2_AVAIL__CEQ_CNT_DB__SHIFT 0x10 |
7064 | #define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x00000FFFL |
7065 | #define CP_CEQ2_AVAIL__CEQ_CNT_DB_MASK 0x0FFF0000L |
7066 | //CP_CE_ROQ_RB_STAT |
7067 | #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 |
7068 | #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 |
7069 | #define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x00000FFFL |
7070 | #define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x0FFF0000L |
7071 | //CP_CE_ROQ_IB1_STAT |
7072 | #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 |
7073 | #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 |
7074 | #define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x00000FFFL |
7075 | #define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x0FFF0000L |
7076 | //CP_CE_ROQ_IB2_STAT |
7077 | #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 |
7078 | #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 |
7079 | #define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x00000FFFL |
7080 | #define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x0FFF0000L |
7081 | //CP_CE_ROQ_DB_STAT |
7082 | #define CP_CE_ROQ_DB_STAT__CEQ_RPTR_DB__SHIFT 0x0 |
7083 | #define CP_CE_ROQ_DB_STAT__CEQ_WPTR_DB__SHIFT 0x10 |
7084 | #define CP_CE_ROQ_DB_STAT__CEQ_RPTR_DB_MASK 0x00000FFFL |
7085 | #define CP_CE_ROQ_DB_STAT__CEQ_WPTR_DB_MASK 0x0FFF0000L |
7086 | //CP_ROQ3_THRESHOLDS |
7087 | #define CP_ROQ3_THRESHOLDS__R0_DB_START__SHIFT 0x0 |
7088 | #define CP_ROQ3_THRESHOLDS__R1_DB_START__SHIFT 0xa |
7089 | #define CP_ROQ3_THRESHOLDS__R0_DB_START_MASK 0x000003FFL |
7090 | #define CP_ROQ3_THRESHOLDS__R1_DB_START_MASK 0x000FFC00L |
7091 | //CP_ROQ_DB_STAT |
7092 | #define CP_ROQ_DB_STAT__ROQ_RPTR_DB__SHIFT 0x0 |
7093 | #define CP_ROQ_DB_STAT__ROQ_WPTR_DB__SHIFT 0x10 |
7094 | #define CP_ROQ_DB_STAT__ROQ_RPTR_DB_MASK 0x00000FFFL |
7095 | #define CP_ROQ_DB_STAT__ROQ_WPTR_DB_MASK 0x0FFF0000L |
7096 | #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 |
7097 | #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
7098 | #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L |
7099 | #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
7100 | //CP_PRIV_VIOLATION_ADDR |
7101 | #define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x0 |
7102 | #define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0000FFFFL |
7103 | |
7104 | |
7105 | // addressBlock: gc_padec |
7106 | //VGT_CACHE_INVALIDATION |
7107 | #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 |
7108 | #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 |
7109 | #define 0x5 |
7110 | #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 |
7111 | #define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 |
7112 | #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb |
7113 | #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc |
7114 | #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd |
7115 | #define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 |
7116 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15 |
7117 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16 |
7118 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19 |
7119 | #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c |
7120 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d |
7121 | #define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L |
7122 | #define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L |
7123 | #define 0x00000020L |
7124 | #define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L |
7125 | #define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L |
7126 | #define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L |
7127 | #define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L |
7128 | #define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L |
7129 | #define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L |
7130 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L |
7131 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L |
7132 | #define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L |
7133 | #define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L |
7134 | #define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L |
7135 | //VGT_ESGS_RING_SIZE |
7136 | #define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0 |
7137 | #define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL |
7138 | //VGT_GSVS_RING_SIZE |
7139 | #define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 |
7140 | #define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL |
7141 | //VGT_TF_RING_SIZE |
7142 | #define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 |
7143 | #define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL |
7144 | //VGT_HS_OFFCHIP_PARAM |
7145 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 |
7146 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0xa |
7147 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000003FFL |
7148 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000C00L |
7149 | //VGT_TF_MEMORY_BASE |
7150 | #define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 |
7151 | #define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL |
7152 | //VGT_TF_MEMORY_BASE_HI |
7153 | #define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0 |
7154 | #define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL |
7155 | //VGT_VTX_VECT_EJECT_REG |
7156 | #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 |
7157 | #define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x000003FFL |
7158 | //VGT_DMA_DATA_FIFO_DEPTH |
7159 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 |
7160 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000003FFL |
7161 | //VGT_DMA_REQ_FIFO_DEPTH |
7162 | #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 |
7163 | #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL |
7164 | //VGT_DRAW_INIT_FIFO_DEPTH |
7165 | #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 |
7166 | #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL |
7167 | //VGT_LAST_COPY_STATE |
7168 | #define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 |
7169 | #define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 |
7170 | #define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L |
7171 | #define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L |
7172 | //VGT_FIFO_DEPTHS |
7173 | #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 |
7174 | #define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 |
7175 | #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 |
7176 | #define VGT_FIFO_DEPTHS__RESERVED_1__SHIFT 0x16 |
7177 | #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x17 |
7178 | #define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL |
7179 | #define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L |
7180 | #define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L |
7181 | #define VGT_FIFO_DEPTHS__RESERVED_1_MASK 0x00400000L |
7182 | #define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x1F800000L |
7183 | //VGT_GS_VERTEX_REUSE |
7184 | #define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 |
7185 | #define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL |
7186 | //VGT_MC_LAT_CNTL |
7187 | #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 |
7188 | #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL |
7189 | //IA_UTCL1_STATUS_2 |
7190 | #define IA_UTCL1_STATUS_2__IA_BUSY__SHIFT 0x0 |
7191 | #define IA_UTCL1_STATUS_2__IA_DMA_BUSY__SHIFT 0x1 |
7192 | #define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY__SHIFT 0x2 |
7193 | #define IA_UTCL1_STATUS_2__IA_GRP_BUSY__SHIFT 0x3 |
7194 | #define IA_UTCL1_STATUS_2__IA_ADC_BUSY__SHIFT 0x4 |
7195 | #define IA_UTCL1_STATUS_2__FAULT_DETECTED__SHIFT 0x5 |
7196 | #define IA_UTCL1_STATUS_2__RETRY_DETECTED__SHIFT 0x6 |
7197 | #define IA_UTCL1_STATUS_2__PRT_DETECTED__SHIFT 0x7 |
7198 | #define IA_UTCL1_STATUS_2__FAULT_UTCL1ID__SHIFT 0x8 |
7199 | #define IA_UTCL1_STATUS_2__RETRY_UTCL1ID__SHIFT 0x10 |
7200 | #define IA_UTCL1_STATUS_2__PRT_UTCL1ID__SHIFT 0x18 |
7201 | #define IA_UTCL1_STATUS_2__IA_BUSY_MASK 0x00000001L |
7202 | #define IA_UTCL1_STATUS_2__IA_DMA_BUSY_MASK 0x00000002L |
7203 | #define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY_MASK 0x00000004L |
7204 | #define IA_UTCL1_STATUS_2__IA_GRP_BUSY_MASK 0x00000008L |
7205 | #define IA_UTCL1_STATUS_2__IA_ADC_BUSY_MASK 0x00000010L |
7206 | #define IA_UTCL1_STATUS_2__FAULT_DETECTED_MASK 0x00000020L |
7207 | #define IA_UTCL1_STATUS_2__RETRY_DETECTED_MASK 0x00000040L |
7208 | #define IA_UTCL1_STATUS_2__PRT_DETECTED_MASK 0x00000080L |
7209 | #define IA_UTCL1_STATUS_2__FAULT_UTCL1ID_MASK 0x00003F00L |
7210 | #define IA_UTCL1_STATUS_2__RETRY_UTCL1ID_MASK 0x003F0000L |
7211 | #define IA_UTCL1_STATUS_2__PRT_UTCL1ID_MASK 0x3F000000L |
7212 | //WD_CNTL_STATUS |
7213 | #define WD_CNTL_STATUS__VR3_BUSY__SHIFT 0x0 |
7214 | #define WD_CNTL_STATUS__VR2_BUSY__SHIFT 0x1 |
7215 | #define WD_CNTL_STATUS__VR1_BUSY__SHIFT 0x2 |
7216 | #define WD_CNTL_STATUS__VR0_BUSY__SHIFT 0x3 |
7217 | #define WD_CNTL_STATUS__HS3_BUSY__SHIFT 0x4 |
7218 | #define WD_CNTL_STATUS__HS2_BUSY__SHIFT 0x5 |
7219 | #define WD_CNTL_STATUS__HS1_BUSY__SHIFT 0x6 |
7220 | #define WD_CNTL_STATUS__HS0_BUSY__SHIFT 0x7 |
7221 | #define WD_CNTL_STATUS__GS3_BUSY__SHIFT 0x8 |
7222 | #define WD_CNTL_STATUS__GS2_BUSY__SHIFT 0x9 |
7223 | #define WD_CNTL_STATUS__GS1_BUSY__SHIFT 0xa |
7224 | #define WD_CNTL_STATUS__GS0_BUSY__SHIFT 0xb |
7225 | #define WD_CNTL_STATUS__NGG3_BUSY__SHIFT 0xc |
7226 | #define WD_CNTL_STATUS__NGG2_BUSY__SHIFT 0xd |
7227 | #define WD_CNTL_STATUS__NGG1_BUSY__SHIFT 0xe |
7228 | #define WD_CNTL_STATUS__NGG0_BUSY__SHIFT 0xf |
7229 | #define WD_CNTL_STATUS__DIST_BUSY__SHIFT 0x10 |
7230 | #define WD_CNTL_STATUS__DIST_BE_BUSY__SHIFT 0x11 |
7231 | #define WD_CNTL_STATUS__WD_TE11_BUSY__SHIFT 0x12 |
7232 | #define WD_CNTL_STATUS__SA3_OUTPUT_BLOCK_BUSY__SHIFT 0x13 |
7233 | #define WD_CNTL_STATUS__SA2_OUTPUT_BLOCK_BUSY__SHIFT 0x14 |
7234 | #define WD_CNTL_STATUS__SA1_OUTPUT_BLOCK_BUSY__SHIFT 0x15 |
7235 | #define WD_CNTL_STATUS__SA0_OUTPUT_BLOCK_BUSY__SHIFT 0x16 |
7236 | #define WD_CNTL_STATUS__GE_UTCL1_BUSY__SHIFT 0x17 |
7237 | #define WD_CNTL_STATUS__TE3_BUSY__SHIFT 0x18 |
7238 | #define WD_CNTL_STATUS__TE2_BUSY__SHIFT 0x19 |
7239 | #define WD_CNTL_STATUS__TE1_BUSY__SHIFT 0x1a |
7240 | #define WD_CNTL_STATUS__TE0_BUSY__SHIFT 0x1b |
7241 | #define WD_CNTL_STATUS__WLC_BUSY__SHIFT 0x1c |
7242 | #define WD_CNTL_STATUS__PC_MANAGER_BUSY__SHIFT 0x1d |
7243 | #define WD_CNTL_STATUS__VR3_BUSY_MASK 0x00000001L |
7244 | #define WD_CNTL_STATUS__VR2_BUSY_MASK 0x00000002L |
7245 | #define WD_CNTL_STATUS__VR1_BUSY_MASK 0x00000004L |
7246 | #define WD_CNTL_STATUS__VR0_BUSY_MASK 0x00000008L |
7247 | #define WD_CNTL_STATUS__HS3_BUSY_MASK 0x00000010L |
7248 | #define WD_CNTL_STATUS__HS2_BUSY_MASK 0x00000020L |
7249 | #define WD_CNTL_STATUS__HS1_BUSY_MASK 0x00000040L |
7250 | #define WD_CNTL_STATUS__HS0_BUSY_MASK 0x00000080L |
7251 | #define WD_CNTL_STATUS__GS3_BUSY_MASK 0x00000100L |
7252 | #define WD_CNTL_STATUS__GS2_BUSY_MASK 0x00000200L |
7253 | #define WD_CNTL_STATUS__GS1_BUSY_MASK 0x00000400L |
7254 | #define WD_CNTL_STATUS__GS0_BUSY_MASK 0x00000800L |
7255 | #define WD_CNTL_STATUS__NGG3_BUSY_MASK 0x00001000L |
7256 | #define WD_CNTL_STATUS__NGG2_BUSY_MASK 0x00002000L |
7257 | #define WD_CNTL_STATUS__NGG1_BUSY_MASK 0x00004000L |
7258 | #define WD_CNTL_STATUS__NGG0_BUSY_MASK 0x00008000L |
7259 | #define WD_CNTL_STATUS__DIST_BUSY_MASK 0x00010000L |
7260 | #define WD_CNTL_STATUS__DIST_BE_BUSY_MASK 0x00020000L |
7261 | #define WD_CNTL_STATUS__WD_TE11_BUSY_MASK 0x00040000L |
7262 | #define WD_CNTL_STATUS__SA3_OUTPUT_BLOCK_BUSY_MASK 0x00080000L |
7263 | #define WD_CNTL_STATUS__SA2_OUTPUT_BLOCK_BUSY_MASK 0x00100000L |
7264 | #define WD_CNTL_STATUS__SA1_OUTPUT_BLOCK_BUSY_MASK 0x00200000L |
7265 | #define WD_CNTL_STATUS__SA0_OUTPUT_BLOCK_BUSY_MASK 0x00400000L |
7266 | #define WD_CNTL_STATUS__GE_UTCL1_BUSY_MASK 0x00800000L |
7267 | #define WD_CNTL_STATUS__TE3_BUSY_MASK 0x01000000L |
7268 | #define WD_CNTL_STATUS__TE2_BUSY_MASK 0x02000000L |
7269 | #define WD_CNTL_STATUS__TE1_BUSY_MASK 0x04000000L |
7270 | #define WD_CNTL_STATUS__TE0_BUSY_MASK 0x08000000L |
7271 | #define WD_CNTL_STATUS__WLC_BUSY_MASK 0x10000000L |
7272 | #define WD_CNTL_STATUS__PC_MANAGER_BUSY_MASK 0x20000000L |
7273 | //CC_GC_PRIM_CONFIG |
7274 | #define CC_GC_PRIM_CONFIG__INACTIVE_PA__SHIFT 0x4 |
7275 | #define CC_GC_PRIM_CONFIG__INACTIVE_PA_MASK 0x000FFFF0L |
7276 | //GC_USER_PRIM_CONFIG |
7277 | #define GC_USER_PRIM_CONFIG__INACTIVE_PA__SHIFT 0x4 |
7278 | #define GC_USER_PRIM_CONFIG__INACTIVE_PA_MASK 0x000FFFF0L |
7279 | //WD_QOS |
7280 | #define WD_QOS__DRAW_STALL__SHIFT 0x0 |
7281 | #define WD_QOS__DRAW_STALL_MASK 0x00000001L |
7282 | //WD_UTCL1_CNTL |
7283 | #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
7284 | #define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
7285 | #define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
7286 | #define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
7287 | #define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
7288 | #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
7289 | #define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
7290 | #define WD_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d |
7291 | #define WD_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE__SHIFT 0x1e |
7292 | #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
7293 | #define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
7294 | #define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
7295 | #define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
7296 | #define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
7297 | #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
7298 | #define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
7299 | #define WD_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L |
7300 | #define WD_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE_MASK 0x40000000L |
7301 | //WD_UTCL1_STATUS |
7302 | #define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
7303 | #define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
7304 | #define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
7305 | #define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
7306 | #define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
7307 | #define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
7308 | #define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
7309 | #define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
7310 | #define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
7311 | #define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
7312 | #define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
7313 | #define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
7314 | //GE_PC_CNTL |
7315 | #define GE_PC_CNTL__PC_SIZE__SHIFT 0x0 |
7316 | #define GE_PC_CNTL__NO_RESERVATION_EN__SHIFT 0x11 |
7317 | #define GE_PC_CNTL__WAVES_WITH_NO_GRANT__SHIFT 0x12 |
7318 | #define GE_PC_CNTL__PC_SIZE_MASK 0x0000FFFFL |
7319 | #define GE_PC_CNTL__NO_RESERVATION_EN_MASK 0x00020000L |
7320 | #define GE_PC_CNTL__WAVES_WITH_NO_GRANT_MASK 0x003C0000L |
7321 | //IA_UTCL1_CNTL |
7322 | #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
7323 | #define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
7324 | #define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
7325 | #define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
7326 | #define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
7327 | #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
7328 | #define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
7329 | #define IA_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d |
7330 | #define IA_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE__SHIFT 0x1e |
7331 | #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
7332 | #define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
7333 | #define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
7334 | #define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
7335 | #define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
7336 | #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
7337 | #define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
7338 | #define IA_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L |
7339 | #define IA_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE_MASK 0x40000000L |
7340 | //IA_UTCL1_STATUS |
7341 | #define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
7342 | #define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
7343 | #define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
7344 | #define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
7345 | #define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
7346 | #define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
7347 | #define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
7348 | #define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
7349 | #define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
7350 | #define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
7351 | #define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
7352 | #define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
7353 | //CC_GC_SA_UNIT_DISABLE |
7354 | #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 |
7355 | #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L |
7356 | //GC_USER_SA_UNIT_DISABLE |
7357 | #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 |
7358 | #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L |
7359 | //VGT_SYS_CONFIG |
7360 | #define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 |
7361 | #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 |
7362 | #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 |
7363 | #define VGT_SYS_CONFIG__NUM_SUBGROUPS_IN_FLIGHT__SHIFT 0x8 |
7364 | #define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L |
7365 | #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL |
7366 | #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L |
7367 | #define VGT_SYS_CONFIG__NUM_SUBGROUPS_IN_FLIGHT_MASK 0x0007FF00L |
7368 | //GE_PRIV_CONTROL |
7369 | #define GE_PRIV_CONTROL__DISCARD_LEGACY__SHIFT 0x0 |
7370 | #define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE__SHIFT 0x1 |
7371 | #define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE__SHIFT 0xa |
7372 | #define GE_PRIV_CONTROL__FGCG_OVERRIDE__SHIFT 0xf |
7373 | #define GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE__SHIFT 0x10 |
7374 | #define GE_PRIV_CONTROL__DISCARD_LEGACY_MASK 0x00000001L |
7375 | #define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE_MASK 0x000003FEL |
7376 | #define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE_MASK 0x00000400L |
7377 | #define GE_PRIV_CONTROL__FGCG_OVERRIDE_MASK 0x00008000L |
7378 | #define GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE_MASK 0x00010000L |
7379 | //GE_STATUS |
7380 | #define GE_STATUS__PERFCOUNTER_STATUS__SHIFT 0x0 |
7381 | #define GE_STATUS__THREAD_TRACE_STATUS__SHIFT 0x1 |
7382 | #define GE_STATUS__PERFCOUNTER_STATUS_MASK 0x00000001L |
7383 | #define GE_STATUS__THREAD_TRACE_STATUS_MASK 0x00000002L |
7384 | //VGT_VS_MAX_WAVE_ID |
7385 | #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
7386 | #define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
7387 | //VGT_GS_MAX_WAVE_ID |
7388 | #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
7389 | #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
7390 | //CC_GC_SHADER_ARRAY_CONFIG_GEN1 |
7391 | #define CC_GC_SHADER_ARRAY_CONFIG_GEN1__GEN1_INACTIVE_CU__SHIFT 0x0 |
7392 | #define CC_GC_SHADER_ARRAY_CONFIG_GEN1__GEN1_INACTIVE_CU_MASK 0x00003FFFL |
7393 | //CC_GC_SHADER_ARRAY_CONFIG_GEN0 |
7394 | #define CC_GC_SHADER_ARRAY_CONFIG_GEN0__GEN0_INACTIVE_CU__SHIFT 0x0 |
7395 | #define CC_GC_SHADER_ARRAY_CONFIG_GEN0__GEN0_INACTIVE_CU_MASK 0x00003FFFL |
7396 | //GFX_PIPE_CONTROL |
7397 | #define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 |
7398 | #define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd |
7399 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 |
7400 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN__SHIFT 0x11 |
7401 | #define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL |
7402 | #define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L |
7403 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L |
7404 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN_MASK 0x00020000L |
7405 | //CC_GC_SHADER_ARRAY_CONFIG |
7406 | #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10 |
7407 | #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L |
7408 | //GC_USER_SHADER_ARRAY_CONFIG |
7409 | #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10 |
7410 | #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L |
7411 | //VGT_DMA_PRIMITIVE_TYPE |
7412 | #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 |
7413 | #define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL |
7414 | //VGT_DMA_CONTROL |
7415 | #define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 |
7416 | #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 |
7417 | #define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13 |
7418 | #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 |
7419 | #define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL |
7420 | #define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L |
7421 | #define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L |
7422 | #define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L |
7423 | //VGT_DMA_LS_HS_CONFIG |
7424 | #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 |
7425 | #define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L |
7426 | //VGT_STRMOUT_DELAY |
7427 | #define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 |
7428 | #define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 |
7429 | #define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb |
7430 | #define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe |
7431 | #define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 |
7432 | #define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL |
7433 | #define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L |
7434 | #define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L |
7435 | #define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L |
7436 | #define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L |
7437 | //WD_BUF_RESOURCE_1 |
7438 | #define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0 |
7439 | #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10 |
7440 | #define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL |
7441 | #define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L |
7442 | //WD_BUF_RESOURCE_2 |
7443 | #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0 |
7444 | #define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf |
7445 | #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10 |
7446 | #define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL |
7447 | #define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L |
7448 | #define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L |
7449 | //PA_CL_CNTL_STATUS |
7450 | #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0 |
7451 | #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1 |
7452 | #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2 |
7453 | #define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f |
7454 | #define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L |
7455 | #define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L |
7456 | #define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L |
7457 | #define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L |
7458 | //PA_CL_ENHANCE |
7459 | #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 |
7460 | #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 |
7461 | #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 |
7462 | #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 |
7463 | #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 |
7464 | #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 |
7465 | #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 |
7466 | #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 |
7467 | #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb |
7468 | #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc |
7469 | #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe |
7470 | #define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT 0x11 |
7471 | #define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT__SHIFT 0x12 |
7472 | #define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET__SHIFT 0x13 |
7473 | #define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT 0x14 |
7474 | #define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT 0x15 |
7475 | #define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE__SHIFT 0x16 |
7476 | #define PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO__SHIFT 0x18 |
7477 | #define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c |
7478 | #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d |
7479 | #define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e |
7480 | #define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f |
7481 | #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L |
7482 | #define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L |
7483 | #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L |
7484 | #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L |
7485 | #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L |
7486 | #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L |
7487 | #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L |
7488 | #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L |
7489 | #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L |
7490 | #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L |
7491 | #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L |
7492 | #define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK 0x00020000L |
7493 | #define PA_CL_ENHANCE__OUTPUT_SWITCH_TO_LEGACY_EVENT_MASK 0x00040000L |
7494 | #define PA_CL_ENHANCE__NO_SWITCH_TO_LEGACY_AFTER_VMID_RESET_MASK 0x00080000L |
7495 | #define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK 0x00100000L |
7496 | #define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK 0x00200000L |
7497 | #define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE_MASK 0x00400000L |
7498 | #define PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO_MASK 0x01000000L |
7499 | #define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L |
7500 | #define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L |
7501 | #define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L |
7502 | #define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L |
7503 | //PA_SU_CNTL_STATUS |
7504 | #define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f |
7505 | #define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L |
7506 | //PA_SC_FIFO_DEPTH_CNTL |
7507 | #define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 |
7508 | #define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL |
7509 | //PA_SC_P3D_TRAP_SCREEN_HV_LOCK |
7510 | #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
7511 | #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
7512 | //PA_SC_HP3D_TRAP_SCREEN_HV_LOCK |
7513 | #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
7514 | #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
7515 | //PA_SC_TRAP_SCREEN_HV_LOCK |
7516 | #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
7517 | #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
7518 | //PA_SC_FORCE_EOV_MAX_CNTS |
7519 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 |
7520 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 |
7521 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL |
7522 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L |
7523 | //PA_SC_BINNER_EVENT_CNTL_0 |
7524 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 |
7525 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 |
7526 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 |
7527 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 |
7528 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 |
7529 | #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa |
7530 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc |
7531 | #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe |
7532 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 |
7533 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12 |
7534 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 |
7535 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 |
7536 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 |
7537 | #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a |
7538 | #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c |
7539 | #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e |
7540 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L |
7541 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL |
7542 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L |
7543 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L |
7544 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L |
7545 | #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L |
7546 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L |
7547 | #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L |
7548 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L |
7549 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L |
7550 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L |
7551 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L |
7552 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L |
7553 | #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L |
7554 | #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L |
7555 | #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L |
7556 | //PA_SC_BINNER_EVENT_CNTL_1 |
7557 | #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 |
7558 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 |
7559 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 |
7560 | #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 |
7561 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 |
7562 | #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa |
7563 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc |
7564 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe |
7565 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 |
7566 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 |
7567 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 |
7568 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 |
7569 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 |
7570 | #define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK__SHIFT 0x1a |
7571 | #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c |
7572 | #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e |
7573 | #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L |
7574 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL |
7575 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L |
7576 | #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L |
7577 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L |
7578 | #define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L |
7579 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L |
7580 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L |
7581 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L |
7582 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L |
7583 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L |
7584 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L |
7585 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L |
7586 | #define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK_MASK 0x0C000000L |
7587 | #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L |
7588 | #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L |
7589 | //PA_SC_BINNER_EVENT_CNTL_2 |
7590 | #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 |
7591 | #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 |
7592 | #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 |
7593 | #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35__SHIFT 0x6 |
7594 | #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 |
7595 | #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa |
7596 | #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc |
7597 | #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe |
7598 | #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 |
7599 | #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41__SHIFT 0x12 |
7600 | #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 |
7601 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 |
7602 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 |
7603 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a |
7604 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c |
7605 | #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e |
7606 | #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L |
7607 | #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL |
7608 | #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L |
7609 | #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35_MASK 0x000000C0L |
7610 | #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L |
7611 | #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L |
7612 | #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L |
7613 | #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L |
7614 | #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L |
7615 | #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41_MASK 0x000C0000L |
7616 | #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L |
7617 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L |
7618 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L |
7619 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L |
7620 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L |
7621 | #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L |
7622 | //PA_SC_BINNER_EVENT_CNTL_3 |
7623 | #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 |
7624 | #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 |
7625 | #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50__SHIFT 0x4 |
7626 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 |
7627 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 |
7628 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa |
7629 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW__SHIFT 0xc |
7630 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe |
7631 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 |
7632 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 |
7633 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 |
7634 | #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 |
7635 | #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 |
7636 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a |
7637 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c |
7638 | #define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE__SHIFT 0x1e |
7639 | #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L |
7640 | #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL |
7641 | #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50_MASK 0x00000030L |
7642 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L |
7643 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L |
7644 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L |
7645 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW_MASK 0x00003000L |
7646 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L |
7647 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L |
7648 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L |
7649 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L |
7650 | #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L |
7651 | #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L |
7652 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L |
7653 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L |
7654 | #define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE_MASK 0xC0000000L |
7655 | //PA_SC_BINNER_TIMEOUT_COUNTER |
7656 | #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 |
7657 | #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL |
7658 | //PA_SC_BINNER_PERF_CNTL_0 |
7659 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 |
7660 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa |
7661 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 |
7662 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 |
7663 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL |
7664 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L |
7665 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L |
7666 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L |
7667 | //PA_SC_BINNER_PERF_CNTL_1 |
7668 | #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 |
7669 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 |
7670 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa |
7671 | #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL |
7672 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L |
7673 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L |
7674 | //PA_SC_BINNER_PERF_CNTL_2 |
7675 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 |
7676 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb |
7677 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL |
7678 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L |
7679 | //PA_SC_BINNER_PERF_CNTL_3 |
7680 | #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 |
7681 | #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL |
7682 | //PA_SC_ENHANCE_2 |
7683 | #define PA_SC_ENHANCE_2__DISABLE_SC_MEM_MACRO_FINE_CLOCK_GATE__SHIFT 0x0 |
7684 | #define PA_SC_ENHANCE_2__DISABLE_SC_DB_QUAD_INTF_FINE_CLOCK_GATE__SHIFT 0x1 |
7685 | #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE__SHIFT 0x2 |
7686 | #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE__SHIFT 0x3 |
7687 | #define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK__SHIFT 0x4 |
7688 | #define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK__SHIFT 0x5 |
7689 | #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD__SHIFT 0x7 |
7690 | #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH__SHIFT 0x8 |
7691 | #define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT 0x9 |
7692 | #define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT 0xa |
7693 | #define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE__SHIFT 0xb |
7694 | #define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xc |
7695 | #define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP__SHIFT 0xd |
7696 | #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP__SHIFT 0xe |
7697 | #define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ__SHIFT 0xf |
7698 | #define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP__SHIFT 0x10 |
7699 | #define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP__SHIFT 0x11 |
7700 | #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET__SHIFT 0x12 |
7701 | #define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN1_REG__SHIFT 0x13 |
7702 | #define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN2_REG__SHIFT 0x14 |
7703 | #define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG__SHIFT 0x15 |
7704 | #define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO__SHIFT 0x17 |
7705 | #define PA_SC_ENHANCE_2__DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE__SHIFT 0x18 |
7706 | #define PA_SC_ENHANCE_2__DISABLE_DFSM_FLUSH__SHIFT 0x19 |
7707 | #define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH__SHIFT 0x1a |
7708 | #define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT__SHIFT 0x1b |
7709 | #define PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT__SHIFT 0x1e |
7710 | #define PA_SC_ENHANCE_2__RSVD__SHIFT 0x1f |
7711 | #define PA_SC_ENHANCE_2__DISABLE_SC_MEM_MACRO_FINE_CLOCK_GATE_MASK 0x00000001L |
7712 | #define PA_SC_ENHANCE_2__DISABLE_SC_DB_QUAD_INTF_FINE_CLOCK_GATE_MASK 0x00000002L |
7713 | #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE_MASK 0x00000004L |
7714 | #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE_MASK 0x00000008L |
7715 | #define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK_MASK 0x00000010L |
7716 | #define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK_MASK 0x00000020L |
7717 | #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD_MASK 0x00000080L |
7718 | #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH_MASK 0x00000100L |
7719 | #define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK_MASK 0x00000200L |
7720 | #define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS_MASK 0x00000400L |
7721 | #define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE_MASK 0x00000800L |
7722 | #define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00001000L |
7723 | #define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP_MASK 0x00002000L |
7724 | #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP_MASK 0x00004000L |
7725 | #define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ_MASK 0x00008000L |
7726 | #define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP_MASK 0x00010000L |
7727 | #define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP_MASK 0x00020000L |
7728 | #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET_MASK 0x00040000L |
7729 | #define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN1_REG_MASK 0x00080000L |
7730 | #define PA_SC_ENHANCE_2__ENABLE_BLOCKING_WRITES_OF_GEN2_REG_MASK 0x00100000L |
7731 | #define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG_MASK 0x00200000L |
7732 | #define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO_MASK 0x00800000L |
7733 | #define PA_SC_ENHANCE_2__DISABLE_PBB_EOP_INSERTION_FOR_MIXED_BINNING_AND_IMMEDIATE_MASK 0x01000000L |
7734 | #define PA_SC_ENHANCE_2__DISABLE_DFSM_FLUSH_MASK 0x02000000L |
7735 | #define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH_MASK 0x04000000L |
7736 | #define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT_MASK 0x38000000L |
7737 | #define PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT_MASK 0x40000000L |
7738 | #define PA_SC_ENHANCE_2__RSVD_MASK 0x80000000L |
7739 | //PA_SC_ENHANCE_INTERNAL |
7740 | //PA_SC_BINNER_CNTL_OVERRIDE |
7741 | #define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE__SHIFT 0x0 |
7742 | #define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT 0xa |
7743 | #define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN__SHIFT 0xd |
7744 | #define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH__SHIFT 0x13 |
7745 | #define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE__SHIFT 0x1b |
7746 | #define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE__SHIFT 0x1c |
7747 | #define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE_MASK 0x00000003L |
7748 | #define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L |
7749 | #define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L |
7750 | #define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH_MASK 0x07F80000L |
7751 | #define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE_MASK 0x08000000L |
7752 | #define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE_MASK 0xF0000000L |
7753 | //PA_SC_PBB_OVERRIDE_FLAG |
7754 | #define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE__SHIFT 0x0 |
7755 | #define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID__SHIFT 0x1 |
7756 | #define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE_MASK 0x00000001L |
7757 | #define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID_MASK 0x00000002L |
7758 | //PA_PH_INTERFACE_FIFO_SIZE |
7759 | #define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE__SHIFT 0x0 |
7760 | #define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE__SHIFT 0x10 |
7761 | #define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE_MASK 0x000003FFL |
7762 | #define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE_MASK 0x003F0000L |
7763 | //PA_PH_ENHANCE |
7764 | #define PA_PH_ENHANCE__ECO_SPARE0__SHIFT 0x0 |
7765 | #define PA_PH_ENHANCE__ECO_SPARE1__SHIFT 0x1 |
7766 | #define PA_PH_ENHANCE__ECO_SPARE2__SHIFT 0x2 |
7767 | #define PA_PH_ENHANCE__ECO_SPARE3__SHIFT 0x3 |
7768 | #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE__SHIFT 0x4 |
7769 | #define PA_PH_ENHANCE__DISABLE_FOPKT__SHIFT 0x5 |
7770 | #define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET__SHIFT 0x6 |
7771 | #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE__SHIFT 0x7 |
7772 | #define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG__SHIFT 0x9 |
7773 | #define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT 0xa |
7774 | #define PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT__SHIFT 0xd |
7775 | #define PA_PH_ENHANCE__ECO_SPARE0_MASK 0x00000001L |
7776 | #define PA_PH_ENHANCE__ECO_SPARE1_MASK 0x00000002L |
7777 | #define PA_PH_ENHANCE__ECO_SPARE2_MASK 0x00000004L |
7778 | #define PA_PH_ENHANCE__ECO_SPARE3_MASK 0x00000008L |
7779 | #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE_MASK 0x00000010L |
7780 | #define PA_PH_ENHANCE__DISABLE_FOPKT_MASK 0x00000020L |
7781 | #define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET_MASK 0x00000040L |
7782 | #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE_MASK 0x00000080L |
7783 | #define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG_MASK 0x00000200L |
7784 | #define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH_MASK 0x00001C00L |
7785 | #define PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT_MASK 0x00002000L |
7786 | //PA_SC_BC_WAVE_BREAK |
7787 | #define PA_SC_BC_WAVE_BREAK__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 |
7788 | #define PA_SC_BC_WAVE_BREAK__MAX_FPOVS_IN_WAVE__SHIFT 0x10 |
7789 | #define PA_SC_BC_WAVE_BREAK__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL |
7790 | #define PA_SC_BC_WAVE_BREAK__MAX_FPOVS_IN_WAVE_MASK 0x00FF0000L |
7791 | //PA_SC_ENHANCE_3 |
7792 | #define PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA__SHIFT 0x0 |
7793 | #define PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_HARVEST__SHIFT 0x2 |
7794 | #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 |
7795 | #define PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION__SHIFT 0x4 |
7796 | #define PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN__SHIFT 0x5 |
7797 | #define PA_SC_ENHANCE_3__RSVD__SHIFT 0x6 |
7798 | #define PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA_MASK 0x00000001L |
7799 | #define PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_HARVEST_MASK 0x00000004L |
7800 | #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L |
7801 | #define PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION_MASK 0x00000010L |
7802 | #define PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN_MASK 0x00000020L |
7803 | #define PA_SC_ENHANCE_3__RSVD_MASK 0xFFFFFFC0L |
7804 | //PA_SC_FIFO_SIZE |
7805 | #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 |
7806 | #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 |
7807 | #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf |
7808 | #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 |
7809 | #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL |
7810 | #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L |
7811 | #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L |
7812 | #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L |
7813 | //PA_SC_IF_FIFO_SIZE |
7814 | #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 |
7815 | #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 |
7816 | #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc |
7817 | #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 |
7818 | #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL |
7819 | #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L |
7820 | #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L |
7821 | #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L |
7822 | //PA_SC_PKR_WAVE_TABLE_CNTL |
7823 | #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 |
7824 | #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL |
7825 | //PA_SIDEBAND_REQUEST_DELAYS |
7826 | #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0 |
7827 | #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10 |
7828 | #define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL |
7829 | #define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L |
7830 | //PA_SC_ENHANCE |
7831 | #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 |
7832 | #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 |
7833 | #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 |
7834 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 |
7835 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 |
7836 | #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 |
7837 | #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 |
7838 | #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 |
7839 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 |
7840 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 |
7841 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa |
7842 | #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb |
7843 | #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc |
7844 | #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd |
7845 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe |
7846 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf |
7847 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 |
7848 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 |
7849 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 |
7850 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 |
7851 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 |
7852 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 |
7853 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 |
7854 | #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 |
7855 | #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 |
7856 | #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 |
7857 | #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a |
7858 | #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b |
7859 | #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c |
7860 | #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d |
7861 | #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L |
7862 | #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L |
7863 | #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L |
7864 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L |
7865 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L |
7866 | #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L |
7867 | #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L |
7868 | #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L |
7869 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L |
7870 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L |
7871 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L |
7872 | #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L |
7873 | #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L |
7874 | #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L |
7875 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L |
7876 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L |
7877 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L |
7878 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L |
7879 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L |
7880 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L |
7881 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L |
7882 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L |
7883 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L |
7884 | #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L |
7885 | #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L |
7886 | #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L |
7887 | #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L |
7888 | #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L |
7889 | #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L |
7890 | #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L |
7891 | //PA_SC_ENHANCE_1 |
7892 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 |
7893 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 |
7894 | #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 |
7895 | #define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 |
7896 | #define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5 |
7897 | #define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 |
7898 | #define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 |
7899 | #define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 |
7900 | #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 |
7901 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa |
7902 | #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb |
7903 | #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe |
7904 | #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf |
7905 | #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 |
7906 | #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 |
7907 | #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 |
7908 | #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 |
7909 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 |
7910 | #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 |
7911 | #define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT 0x17 |
7912 | #define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 |
7913 | #define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT 0x19 |
7914 | #define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1a |
7915 | #define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT 0x1b |
7916 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT 0x1c |
7917 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT 0x1d |
7918 | #define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT 0x1e |
7919 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L |
7920 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L |
7921 | #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L |
7922 | #define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L |
7923 | #define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L |
7924 | #define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L |
7925 | #define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L |
7926 | #define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L |
7927 | #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L |
7928 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L |
7929 | #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L |
7930 | #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L |
7931 | #define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L |
7932 | #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L |
7933 | #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L |
7934 | #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L |
7935 | #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L |
7936 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L |
7937 | #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L |
7938 | #define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK 0x00800000L |
7939 | #define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L |
7940 | #define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK 0x02000000L |
7941 | #define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK 0x04000000L |
7942 | #define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK 0x08000000L |
7943 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK 0x10000000L |
7944 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK 0x20000000L |
7945 | #define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK 0x40000000L |
7946 | //PA_SC_DSM_CNTL |
7947 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 |
7948 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 |
7949 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L |
7950 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L |
7951 | //PA_SC_TILE_STEERING_CREST_OVERRIDE |
7952 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 |
7953 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 |
7954 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 |
7955 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT__SHIFT 0x8 |
7956 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE__SHIFT 0x1f |
7957 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L |
7958 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L |
7959 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L |
7960 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT_MASK 0x00000700L |
7961 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE_MASK 0x80000000L |
7962 | |
7963 | |
7964 | // addressBlock: gc_sqdec |
7965 | //SQ_CONFIG |
7966 | #define SQ_CONFIG__UNUSED__SHIFT 0x0 |
7967 | #define SQ_CONFIG__CHICKEN_BIT_DEGGIGXX0_8637__SHIFT 0x5 |
7968 | #define SQ_CONFIG__UNUSED_6__SHIFT 0x6 |
7969 | #define SQ_CONFIG__DISABLE_SGPR_RD_KILL__SHIFT 0xa |
7970 | #define SQ_CONFIG__VGPR_SWIZZLE_EN__SHIFT 0xc |
7971 | #define SQ_CONFIG__LDS_BUSY_HYSTERESIS_CNT__SHIFT 0xd |
7972 | #define SQ_CONFIG__SP_BUSY_HYSTERESIS_CNT__SHIFT 0xf |
7973 | #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 |
7974 | #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 |
7975 | #define SQ_CONFIG__WCLK_HYSTERESIS_CNT__SHIFT 0x15 |
7976 | #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d |
7977 | #define SQ_CONFIG__TA_BUSY_HYSTERESIS_CNT__SHIFT 0x1e |
7978 | #define SQ_CONFIG__UNUSED_MASK 0x0000001FL |
7979 | #define SQ_CONFIG__VGPR_SWIZZLE_EN_MASK 0x00001000L |
7980 | #define SQ_CONFIG__LDS_BUSY_HYSTERESIS_CNT_MASK 0x00006000L |
7981 | #define SQ_CONFIG__SP_BUSY_HYSTERESIS_CNT_MASK 0x00018000L |
7982 | #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L |
7983 | #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L |
7984 | #define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L |
7985 | #define SQ_CONFIG__TA_BUSY_HYSTERESIS_CNT_MASK 0xC0000000L |
7986 | //SQC_CONFIG |
7987 | #define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 |
7988 | #define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 |
7989 | #define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 |
7990 | #define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 |
7991 | #define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 |
7992 | #define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 |
7993 | #define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb |
7994 | #define SQC_CONFIG__EVICT_LRU__SHIFT 0xc |
7995 | #define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe |
7996 | #define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf |
7997 | #define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 |
7998 | #define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L |
7999 | #define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL |
8000 | #define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L |
8001 | #define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L |
8002 | #define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L |
8003 | #define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L |
8004 | #define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L |
8005 | #define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L |
8006 | #define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L |
8007 | #define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L |
8008 | #define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L |
8009 | //LDS_CONFIG |
8010 | #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0 |
8011 | #define LDS_CONFIG__VGPR_SWIZZLE_EN__SHIFT 0x1 |
8012 | #define LDS_CONFIG__WAVE32_INTERP_DUAL_ISSUE_DISABLE__SHIFT 0x2 |
8013 | #define LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE__SHIFT 0x3 |
8014 | #define LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE__SHIFT 0x4 |
8015 | #define LDS_CONFIG__CONF_BIT_5__SHIFT 0x5 |
8016 | #define LDS_CONFIG__CONF_BIT_6__SHIFT 0x6 |
8017 | #define LDS_CONFIG__CONF_BIT_7__SHIFT 0x7 |
8018 | #define LDS_CONFIG__CONF_BIT_8__SHIFT 0x8 |
8019 | #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L |
8020 | #define LDS_CONFIG__VGPR_SWIZZLE_EN_MASK 0x00000002L |
8021 | #define LDS_CONFIG__WAVE32_INTERP_DUAL_ISSUE_DISABLE_MASK 0x00000004L |
8022 | #define LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE_MASK 0x00000008L |
8023 | #define LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE_MASK 0x00000010L |
8024 | #define LDS_CONFIG__CONF_BIT_5_MASK 0x00000020L |
8025 | #define LDS_CONFIG__CONF_BIT_6_MASK 0x00000040L |
8026 | #define LDS_CONFIG__CONF_BIT_7_MASK 0x00000080L |
8027 | #define LDS_CONFIG__CONF_BIT_8_MASK 0x00000100L |
8028 | //SQ_RANDOM_WAVE_PRI |
8029 | #define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 |
8030 | #define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 |
8031 | #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa |
8032 | #define SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID__SHIFT 0x1f |
8033 | #define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL |
8034 | #define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L |
8035 | #define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x00FFFC00L |
8036 | #define SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID_MASK 0x80000000L |
8037 | //SQG_STATUS |
8038 | #define SQG_STATUS__REG_BUSY__SHIFT 0x0 |
8039 | #define SQG_STATUS__REG_BUSY_MASK 0x00000001L |
8040 | //SQ_FIFO_SIZES |
8041 | #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 |
8042 | #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 |
8043 | #define SQ_FIFO_SIZES__EXPORT_BUF_VS_RESERVED__SHIFT 0xc |
8044 | #define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED__SHIFT 0xe |
8045 | #define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE__SHIFT 0x10 |
8046 | #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 |
8047 | #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL |
8048 | #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000300L |
8049 | #define SQ_FIFO_SIZES__EXPORT_BUF_VS_RESERVED_MASK 0x00003000L |
8050 | #define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED_MASK 0x0000C000L |
8051 | #define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE_MASK 0x00030000L |
8052 | #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L |
8053 | //SQ_DSM_CNTL |
8054 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 |
8055 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 |
8056 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 |
8057 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 |
8058 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 |
8059 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 |
8060 | #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa |
8061 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 |
8062 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 |
8063 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 |
8064 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 |
8065 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 |
8066 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 |
8067 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 |
8068 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 |
8069 | #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a |
8070 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L |
8071 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L |
8072 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L |
8073 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L |
8074 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L |
8075 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L |
8076 | #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L |
8077 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L |
8078 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L |
8079 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L |
8080 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L |
8081 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L |
8082 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L |
8083 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L |
8084 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L |
8085 | #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L |
8086 | //SQ_DSM_CNTL2 |
8087 | #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 |
8088 | #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 |
8089 | #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 |
8090 | #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 |
8091 | #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 |
8092 | #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 |
8093 | #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 |
8094 | #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb |
8095 | #define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe |
8096 | #define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 |
8097 | #define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a |
8098 | #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L |
8099 | #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L |
8100 | #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L |
8101 | #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L |
8102 | #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
8103 | #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L |
8104 | #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L |
8105 | #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L |
8106 | #define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L |
8107 | #define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L |
8108 | #define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L |
8109 | //SQ_RUNTIME_CONFIG |
8110 | #define SQ_RUNTIME_CONFIG__UNUSED_REGISTER__SHIFT 0x0 |
8111 | #define SQ_RUNTIME_CONFIG__UNUSED_REGISTER_MASK 0x00000001L |
8112 | //SH_MEM_BASES |
8113 | #define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 |
8114 | #define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 |
8115 | #define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL |
8116 | #define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L |
8117 | //SP_CONFIG |
8118 | #define SP_CONFIG__DEST_CACHE_EVICT_COUNTER__SHIFT 0x0 |
8119 | #define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE__SHIFT 0x2 |
8120 | #define SP_CONFIG__DISABLE_TRANS_COEXEC__SHIFT 0x3 |
8121 | #define SP_CONFIG__CAC_COUNTER_OVERRIDE__SHIFT 0x4 |
8122 | #define SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE__SHIFT 0x5 |
8123 | #define SP_CONFIG__DEST_CACHE_EVICT_COUNTER_MASK 0x00000003L |
8124 | #define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE_MASK 0x00000004L |
8125 | #define SP_CONFIG__DISABLE_TRANS_COEXEC_MASK 0x00000008L |
8126 | #define SP_CONFIG__CAC_COUNTER_OVERRIDE_MASK 0x00000010L |
8127 | #define SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE_MASK 0x00000020L |
8128 | //SQ_ARB_CONFIG |
8129 | #define SQ_ARB_CONFIG__WG_RR_INTERVAL__SHIFT 0x0 |
8130 | #define SQ_ARB_CONFIG__FWD_PROG_INTERVAL__SHIFT 0x4 |
8131 | #define SQ_ARB_CONFIG__WG_RR_INTERVAL_MASK 0x00000003L |
8132 | #define SQ_ARB_CONFIG__FWD_PROG_INTERVAL_MASK 0x00000030L |
8133 | //SH_MEM_CONFIG |
8134 | #define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 |
8135 | #define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x2 |
8136 | #define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x4 |
8137 | #define SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT 0xe |
8138 | #define SH_MEM_CONFIG__ICACHE_USE_GL1__SHIFT 0x12 |
8139 | #define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L |
8140 | #define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x0000000CL |
8141 | #define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0x00000070L |
8142 | #define SH_MEM_CONFIG__INITIAL_INST_PREFETCH_MASK 0x0000C000L |
8143 | #define SH_MEM_CONFIG__ICACHE_USE_GL1_MASK 0x00040000L |
8144 | //SQ_SHADER_TBA_LO |
8145 | #define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 |
8146 | #define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL |
8147 | //SQ_SHADER_TBA_HI |
8148 | #define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 |
8149 | #define SQ_SHADER_TBA_HI__TRAP_EN__SHIFT 0x1f |
8150 | #define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL |
8151 | #define SQ_SHADER_TBA_HI__TRAP_EN_MASK 0x80000000L |
8152 | //SQ_SHADER_TMA_LO |
8153 | #define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 |
8154 | #define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL |
8155 | //SQ_SHADER_TMA_HI |
8156 | #define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 |
8157 | #define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL |
8158 | //SQG_UTCL0_CNTL1 |
8159 | #define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
8160 | #define SQG_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
8161 | #define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
8162 | #define SQG_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 |
8163 | #define SQG_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
8164 | #define SQG_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 |
8165 | #define SQG_UTCL0_CNTL1__RESERVED__SHIFT 0x10 |
8166 | #define SQG_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
8167 | #define SQG_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
8168 | #define SQG_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13 |
8169 | #define SQG_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 |
8170 | #define SQG_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 |
8171 | #define SQG_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
8172 | #define SQG_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a |
8173 | #define SQG_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
8174 | #define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
8175 | #define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
8176 | #define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
8177 | #define SQG_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
8178 | #define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
8179 | #define SQG_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L |
8180 | #define SQG_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
8181 | #define SQG_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L |
8182 | #define SQG_UTCL0_CNTL1__RESERVED_MASK 0x00010000L |
8183 | #define SQG_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
8184 | #define SQG_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
8185 | #define SQG_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L |
8186 | #define SQG_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L |
8187 | #define SQG_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L |
8188 | #define SQG_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
8189 | #define SQG_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L |
8190 | #define SQG_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
8191 | #define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
8192 | #define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
8193 | //SQG_UTCL0_CNTL2 |
8194 | #define SQG_UTCL0_CNTL2__SPARE__SHIFT 0x0 |
8195 | #define SQG_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 |
8196 | #define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
8197 | #define SQG_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa |
8198 | #define SQG_UTCL0_CNTL2__DIS_EDC__SHIFT 0xb |
8199 | #define SQG_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
8200 | #define SQG_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
8201 | #define SQG_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe |
8202 | #define SQG_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
8203 | #define SQG_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT 0x10 |
8204 | #define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
8205 | #define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 |
8206 | #define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
8207 | #define SQG_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 |
8208 | #define SQG_UTCL0_CNTL2__DIS_DUAL_L2_REQ__SHIFT 0x19 |
8209 | #define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
8210 | #define SQG_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b |
8211 | #define SQG_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c |
8212 | #define SQG_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT 0x1d |
8213 | #define SQG_UTCL0_CNTL2__RESERVED__SHIFT 0x1e |
8214 | #define SQG_UTCL0_CNTL2__SPARE_MASK 0x000000FFL |
8215 | #define SQG_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L |
8216 | #define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
8217 | #define SQG_UTCL0_CNTL2__LINE_VALID_MASK 0x00000400L |
8218 | #define SQG_UTCL0_CNTL2__DIS_EDC_MASK 0x00000800L |
8219 | #define SQG_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
8220 | #define SQG_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
8221 | #define SQG_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
8222 | #define SQG_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
8223 | #define SQG_UTCL0_CNTL2__ARB_BURST_MODE_MASK 0x00030000L |
8224 | #define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
8225 | #define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L |
8226 | #define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
8227 | #define SQG_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L |
8228 | #define SQG_UTCL0_CNTL2__DIS_DUAL_L2_REQ_MASK 0x02000000L |
8229 | #define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
8230 | #define SQG_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L |
8231 | #define SQG_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L |
8232 | #define SQG_UTCL0_CNTL2__GPUVM_16K_DEF_MASK 0x20000000L |
8233 | #define SQG_UTCL0_CNTL2__RESERVED_MASK 0xC0000000L |
8234 | //SQG_UTCL0_STATUS |
8235 | #define SQG_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 |
8236 | #define SQG_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 |
8237 | #define SQG_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 |
8238 | #define SQG_UTCL0_STATUS__RESERVED__SHIFT 0x3 |
8239 | #define SQG_UTCL0_STATUS__UNUSED__SHIFT 0x8 |
8240 | #define SQG_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L |
8241 | #define SQG_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L |
8242 | #define SQG_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L |
8243 | #define SQG_UTCL0_STATUS__RESERVED_MASK 0x000000F8L |
8244 | #define SQG_UTCL0_STATUS__UNUSED_MASK 0xFFFFFF00L |
8245 | //SQG_CONFIG |
8246 | #define SQG_CONFIG__UTCL0_PREFETCH_PAGE__SHIFT 0x0 |
8247 | #define SQG_CONFIG__UTCL0_RETRY_TIMER__SHIFT 0x4 |
8248 | #define SQG_CONFIG__UTCL0_PREFETCH_PAGE_MASK 0x0000000FL |
8249 | #define SQG_CONFIG__UTCL0_RETRY_TIMER_MASK 0x000007F0L |
8250 | //CC_GC_SHADER_RATE_CONFIG |
8251 | #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 |
8252 | #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 |
8253 | #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L |
8254 | #define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L |
8255 | //GC_USER_SHADER_RATE_CONFIG |
8256 | #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 |
8257 | #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 |
8258 | #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L |
8259 | #define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L |
8260 | //SQ_INTERRUPT_AUTO_MASK |
8261 | #define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 |
8262 | #define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL |
8263 | //SQ_INTERRUPT_MSG_CTRL |
8264 | #define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 |
8265 | #define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L |
8266 | //SQ_WATCH0_ADDR_H |
8267 | #define SQ_WATCH0_ADDR_H__ADDR__SHIFT 0x0 |
8268 | #define SQ_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL |
8269 | //SQ_WATCH0_ADDR_L |
8270 | #define SQ_WATCH0_ADDR_L__ADDR__SHIFT 0x6 |
8271 | #define SQ_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
8272 | //SQ_WATCH0_CNTL |
8273 | #define SQ_WATCH0_CNTL__MASK__SHIFT 0x0 |
8274 | #define SQ_WATCH0_CNTL__VMID__SHIFT 0x18 |
8275 | #define SQ_WATCH0_CNTL__VALID__SHIFT 0x1f |
8276 | #define SQ_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL |
8277 | #define SQ_WATCH0_CNTL__VMID_MASK 0x0F000000L |
8278 | #define SQ_WATCH0_CNTL__VALID_MASK 0x80000000L |
8279 | //SQ_WATCH1_ADDR_H |
8280 | #define SQ_WATCH1_ADDR_H__ADDR__SHIFT 0x0 |
8281 | #define SQ_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL |
8282 | //SQ_WATCH1_ADDR_L |
8283 | #define SQ_WATCH1_ADDR_L__ADDR__SHIFT 0x6 |
8284 | #define SQ_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
8285 | //SQ_WATCH1_CNTL |
8286 | #define SQ_WATCH1_CNTL__MASK__SHIFT 0x0 |
8287 | #define SQ_WATCH1_CNTL__VMID__SHIFT 0x18 |
8288 | #define SQ_WATCH1_CNTL__VALID__SHIFT 0x1f |
8289 | #define SQ_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL |
8290 | #define SQ_WATCH1_CNTL__VMID_MASK 0x0F000000L |
8291 | #define SQ_WATCH1_CNTL__VALID_MASK 0x80000000L |
8292 | //SQ_WATCH2_ADDR_H |
8293 | #define SQ_WATCH2_ADDR_H__ADDR__SHIFT 0x0 |
8294 | #define SQ_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL |
8295 | //SQ_WATCH2_ADDR_L |
8296 | #define SQ_WATCH2_ADDR_L__ADDR__SHIFT 0x6 |
8297 | #define SQ_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
8298 | //SQ_WATCH2_CNTL |
8299 | #define SQ_WATCH2_CNTL__MASK__SHIFT 0x0 |
8300 | #define SQ_WATCH2_CNTL__VMID__SHIFT 0x18 |
8301 | #define SQ_WATCH2_CNTL__VALID__SHIFT 0x1f |
8302 | #define SQ_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL |
8303 | #define SQ_WATCH2_CNTL__VMID_MASK 0x0F000000L |
8304 | #define SQ_WATCH2_CNTL__VALID_MASK 0x80000000L |
8305 | //SQ_WATCH3_ADDR_H |
8306 | #define SQ_WATCH3_ADDR_H__ADDR__SHIFT 0x0 |
8307 | #define SQ_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL |
8308 | //SQ_WATCH3_ADDR_L |
8309 | #define SQ_WATCH3_ADDR_L__ADDR__SHIFT 0x6 |
8310 | #define SQ_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
8311 | //SQ_WATCH3_CNTL |
8312 | #define SQ_WATCH3_CNTL__MASK__SHIFT 0x0 |
8313 | #define SQ_WATCH3_CNTL__VMID__SHIFT 0x18 |
8314 | #define SQ_WATCH3_CNTL__VALID__SHIFT 0x1f |
8315 | #define SQ_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL |
8316 | #define SQ_WATCH3_CNTL__VMID_MASK 0x0F000000L |
8317 | #define SQ_WATCH3_CNTL__VALID_MASK 0x80000000L |
8318 | //SQ_THREAD_TRACE_BUF0_BASE |
8319 | #define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO__SHIFT 0x0 |
8320 | #define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO_MASK 0xFFFFFFFFL |
8321 | //SQ_THREAD_TRACE_BUF0_SIZE |
8322 | #define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI__SHIFT 0x0 |
8323 | #define SQ_THREAD_TRACE_BUF0_SIZE__SIZE__SHIFT 0x8 |
8324 | #define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI_MASK 0x0000000FL |
8325 | #define SQ_THREAD_TRACE_BUF0_SIZE__SIZE_MASK 0x3FFFFF00L |
8326 | //SQ_THREAD_TRACE_BUF1_BASE |
8327 | #define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO__SHIFT 0x0 |
8328 | #define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO_MASK 0xFFFFFFFFL |
8329 | //SQ_THREAD_TRACE_BUF1_SIZE |
8330 | #define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI__SHIFT 0x0 |
8331 | #define SQ_THREAD_TRACE_BUF1_SIZE__SIZE__SHIFT 0x8 |
8332 | #define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI_MASK 0x0000000FL |
8333 | #define SQ_THREAD_TRACE_BUF1_SIZE__SIZE_MASK 0x3FFFFF00L |
8334 | //SQ_THREAD_TRACE_WPTR |
8335 | #define SQ_THREAD_TRACE_WPTR__OFFSET__SHIFT 0x0 |
8336 | #define SQ_THREAD_TRACE_WPTR__BUFFER_ID__SHIFT 0x1f |
8337 | #define SQ_THREAD_TRACE_WPTR__OFFSET_MASK 0x1FFFFFFFL |
8338 | #define SQ_THREAD_TRACE_WPTR__BUFFER_ID_MASK 0x80000000L |
8339 | //SQ_THREAD_TRACE_MASK |
8340 | #define SQ_THREAD_TRACE_MASK__SIMD_SEL__SHIFT 0x0 |
8341 | #define SQ_THREAD_TRACE_MASK__WGP_SEL__SHIFT 0x4 |
8342 | #define SQ_THREAD_TRACE_MASK__SA_SEL__SHIFT 0x9 |
8343 | #define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE__SHIFT 0xa |
8344 | #define SQ_THREAD_TRACE_MASK__SIMD_SEL_MASK 0x00000003L |
8345 | #define SQ_THREAD_TRACE_MASK__WGP_SEL_MASK 0x000000F0L |
8346 | #define SQ_THREAD_TRACE_MASK__SA_SEL_MASK 0x00000200L |
8347 | #define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE_MASK 0x0001FC00L |
8348 | //SQ_THREAD_TRACE_TOKEN_MASK |
8349 | #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE__SHIFT 0x0 |
8350 | #define SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE__SHIFT 0xc |
8351 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE__SHIFT 0x10 |
8352 | #define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE__SHIFT 0x18 |
8353 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE__SHIFT 0x1a |
8354 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL__SHIFT 0x1f |
8355 | #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE_MASK 0x000007FFL |
8356 | #define SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE_MASK 0x00001000L |
8357 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE_MASK 0x00FF0000L |
8358 | #define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE_MASK 0x03000000L |
8359 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE_MASK 0x1C000000L |
8360 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL_MASK 0x80000000L |
8361 | //SQ_THREAD_TRACE_CTRL |
8362 | #define SQ_THREAD_TRACE_CTRL__MODE__SHIFT 0x0 |
8363 | #define SQ_THREAD_TRACE_CTRL__ALL_VMID__SHIFT 0x2 |
8364 | #define SQ_THREAD_TRACE_CTRL__CH_PERF_EN__SHIFT 0x3 |
8365 | #define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN__SHIFT 0x4 |
8366 | #define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER__SHIFT 0x5 |
8367 | #define SQ_THREAD_TRACE_CTRL__HIWATER__SHIFT 0x6 |
8368 | #define SQ_THREAD_TRACE_CTRL__REG_STALL_EN__SHIFT 0x9 |
8369 | #define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN__SHIFT 0xa |
8370 | #define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN__SHIFT 0xb |
8371 | #define SQ_THREAD_TRACE_CTRL__REG_DROP_ON_STALL__SHIFT 0xc |
8372 | #define SQ_THREAD_TRACE_CTRL__UTIL_TIMER__SHIFT 0xd |
8373 | #define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE__SHIFT 0xe |
8374 | #define SQ_THREAD_TRACE_CTRL__RT_FREQ__SHIFT 0x10 |
8375 | #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS__SHIFT 0x12 |
8376 | #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS__SHIFT 0x13 |
8377 | #define SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET__SHIFT 0x14 |
8378 | #define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS__SHIFT 0x1c |
8379 | #define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE__SHIFT 0x1d |
8380 | #define SQ_THREAD_TRACE_CTRL__CAPTURE_ALL__SHIFT 0x1e |
8381 | #define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN__SHIFT 0x1f |
8382 | #define SQ_THREAD_TRACE_CTRL__MODE_MASK 0x00000003L |
8383 | #define SQ_THREAD_TRACE_CTRL__ALL_VMID_MASK 0x00000004L |
8384 | #define SQ_THREAD_TRACE_CTRL__CH_PERF_EN_MASK 0x00000008L |
8385 | #define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN_MASK 0x00000010L |
8386 | #define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER_MASK 0x00000020L |
8387 | #define SQ_THREAD_TRACE_CTRL__HIWATER_MASK 0x000001C0L |
8388 | #define SQ_THREAD_TRACE_CTRL__REG_STALL_EN_MASK 0x00000200L |
8389 | #define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN_MASK 0x00000400L |
8390 | #define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN_MASK 0x00000800L |
8391 | #define SQ_THREAD_TRACE_CTRL__REG_DROP_ON_STALL_MASK 0x00001000L |
8392 | #define SQ_THREAD_TRACE_CTRL__UTIL_TIMER_MASK 0x00002000L |
8393 | #define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE_MASK 0x0000C000L |
8394 | #define SQ_THREAD_TRACE_CTRL__RT_FREQ_MASK 0x00030000L |
8395 | #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS_MASK 0x00040000L |
8396 | #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS_MASK 0x00080000L |
8397 | #define SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET_MASK 0x00700000L |
8398 | #define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS_MASK 0x10000000L |
8399 | #define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE_MASK 0x20000000L |
8400 | #define SQ_THREAD_TRACE_CTRL__CAPTURE_ALL_MASK 0x40000000L |
8401 | #define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN_MASK 0x80000000L |
8402 | //SQ_THREAD_TRACE_STATUS |
8403 | #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 |
8404 | #define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0xc |
8405 | #define SQ_THREAD_TRACE_STATUS__UTC_ERR__SHIFT 0x18 |
8406 | #define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x19 |
8407 | #define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_OVERFLOW__SHIFT 0x1a |
8408 | #define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_STALL__SHIFT 0x1b |
8409 | #define SQ_THREAD_TRACE_STATUS__OWNER_VMID__SHIFT 0x1c |
8410 | #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x00000FFFL |
8411 | #define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x00FFF000L |
8412 | #define SQ_THREAD_TRACE_STATUS__UTC_ERR_MASK 0x01000000L |
8413 | #define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x02000000L |
8414 | #define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_OVERFLOW_MASK 0x04000000L |
8415 | #define SQ_THREAD_TRACE_STATUS__EVENT_CNTR_STALL_MASK 0x08000000L |
8416 | #define SQ_THREAD_TRACE_STATUS__OWNER_VMID_MASK 0xF0000000L |
8417 | //SQ_THREAD_TRACE_DROPPED_CNTR |
8418 | #define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR__SHIFT 0x0 |
8419 | #define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR_MASK 0xFFFFFFFFL |
8420 | //SQ_THREAD_TRACE_GFX_DRAW_CNTR |
8421 | #define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR__SHIFT 0x0 |
8422 | #define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL |
8423 | //SQ_THREAD_TRACE_GFX_MARKER_CNTR |
8424 | #define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR__SHIFT 0x0 |
8425 | #define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL |
8426 | //SQ_THREAD_TRACE_HP3D_DRAW_CNTR |
8427 | #define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR__SHIFT 0x0 |
8428 | #define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL |
8429 | //SQ_THREAD_TRACE_HP3D_MARKER_CNTR |
8430 | #define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR__SHIFT 0x0 |
8431 | #define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL |
8432 | //SQ_THREAD_TRACE_STATUS2 |
8433 | #define SQ_THREAD_TRACE_STATUS2__BUF0_FULL__SHIFT 0x0 |
8434 | #define SQ_THREAD_TRACE_STATUS2__BUF1_FULL__SHIFT 0x1 |
8435 | #define SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN__SHIFT 0x4 |
8436 | #define SQ_THREAD_TRACE_STATUS2__BUF0_FULL_MASK 0x00000001L |
8437 | #define SQ_THREAD_TRACE_STATUS2__BUF1_FULL_MASK 0x00000002L |
8438 | #define SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN_MASK 0x00000010L |
8439 | //SQ_IND_INDEX |
8440 | #define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 |
8441 | #define SQ_IND_INDEX__WORKITEM_ID__SHIFT 0x5 |
8442 | #define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xb |
8443 | #define SQ_IND_INDEX__INDEX__SHIFT 0x10 |
8444 | #define SQ_IND_INDEX__WAVE_ID_MASK 0x0000001FL |
8445 | #define SQ_IND_INDEX__WORKITEM_ID_MASK 0x000007E0L |
8446 | #define SQ_IND_INDEX__AUTO_INCR_MASK 0x00000800L |
8447 | #define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L |
8448 | //SQ_IND_DATA |
8449 | #define SQ_IND_DATA__DATA__SHIFT 0x0 |
8450 | #define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL |
8451 | //SQ_CMD |
8452 | #define SQ_CMD__CMD__SHIFT 0x0 |
8453 | #define SQ_CMD__MODE__SHIFT 0x4 |
8454 | #define SQ_CMD__CHECK_VMID__SHIFT 0x7 |
8455 | #define SQ_CMD__DATA__SHIFT 0x8 |
8456 | #define SQ_CMD__WAVE_ID__SHIFT 0x10 |
8457 | #define SQ_CMD__QUEUE_ID__SHIFT 0x18 |
8458 | #define SQ_CMD__VM_ID__SHIFT 0x1c |
8459 | #define SQ_CMD__CMD_MASK 0x0000000FL |
8460 | #define SQ_CMD__MODE_MASK 0x00000070L |
8461 | #define SQ_CMD__CHECK_VMID_MASK 0x00000080L |
8462 | #define SQ_CMD__DATA_MASK 0x00000F00L |
8463 | #define SQ_CMD__WAVE_ID_MASK 0x001F0000L |
8464 | #define SQ_CMD__QUEUE_ID_MASK 0x07000000L |
8465 | #define SQ_CMD__VM_ID_MASK 0xF0000000L |
8466 | //SQ_TIME_HI |
8467 | #define SQ_TIME_HI__TIME__SHIFT 0x0 |
8468 | #define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL |
8469 | //SQ_TIME_LO |
8470 | #define SQ_TIME_LO__TIME__SHIFT 0x0 |
8471 | #define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL |
8472 | //SQ_LB_CTR_CTRL |
8473 | #define SQ_LB_CTR_CTRL__START__SHIFT 0x0 |
8474 | #define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 |
8475 | #define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 |
8476 | #define SQ_LB_CTR_CTRL__START_MASK 0x00000001L |
8477 | #define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L |
8478 | #define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L |
8479 | //SQ_LB_DATA0 |
8480 | #define SQ_LB_DATA0__DATA__SHIFT 0x0 |
8481 | #define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL |
8482 | //SQ_LB_DATA1 |
8483 | #define SQ_LB_DATA1__DATA__SHIFT 0x0 |
8484 | #define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL |
8485 | //SQ_LB_DATA2 |
8486 | #define SQ_LB_DATA2__DATA__SHIFT 0x0 |
8487 | #define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL |
8488 | //SQ_LB_DATA3 |
8489 | #define SQ_LB_DATA3__DATA__SHIFT 0x0 |
8490 | #define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL |
8491 | //SQ_LB_CTR_SEL0 |
8492 | #define SQ_LB_CTR_SEL0__SEL0__SHIFT 0x0 |
8493 | #define SQ_LB_CTR_SEL0__DIV0__SHIFT 0xf |
8494 | #define SQ_LB_CTR_SEL0__SEL1__SHIFT 0x10 |
8495 | #define SQ_LB_CTR_SEL0__DIV1__SHIFT 0x1f |
8496 | #define SQ_LB_CTR_SEL0__SEL0_MASK 0x000000FFL |
8497 | #define SQ_LB_CTR_SEL0__DIV0_MASK 0x00008000L |
8498 | #define SQ_LB_CTR_SEL0__SEL1_MASK 0x00FF0000L |
8499 | #define SQ_LB_CTR_SEL0__DIV1_MASK 0x80000000L |
8500 | //SQ_LB_CTR_SEL1 |
8501 | #define SQ_LB_CTR_SEL1__SEL2__SHIFT 0x0 |
8502 | #define SQ_LB_CTR_SEL1__DIV2__SHIFT 0xf |
8503 | #define SQ_LB_CTR_SEL1__SEL3__SHIFT 0x10 |
8504 | #define SQ_LB_CTR_SEL1__DIV3__SHIFT 0x1f |
8505 | #define SQ_LB_CTR_SEL1__SEL2_MASK 0x000000FFL |
8506 | #define SQ_LB_CTR_SEL1__DIV2_MASK 0x00008000L |
8507 | #define SQ_LB_CTR_SEL1__SEL3_MASK 0x00FF0000L |
8508 | #define SQ_LB_CTR_SEL1__DIV3_MASK 0x80000000L |
8509 | //SQ_EDC_CNT |
8510 | #define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0 |
8511 | #define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2 |
8512 | #define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4 |
8513 | #define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6 |
8514 | #define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8 |
8515 | #define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa |
8516 | #define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc |
8517 | #define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe |
8518 | #define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10 |
8519 | #define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12 |
8520 | #define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14 |
8521 | #define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16 |
8522 | #define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18 |
8523 | #define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a |
8524 | #define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L |
8525 | #define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL |
8526 | #define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L |
8527 | #define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L |
8528 | #define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L |
8529 | #define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L |
8530 | #define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L |
8531 | #define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L |
8532 | #define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L |
8533 | #define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L |
8534 | #define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L |
8535 | #define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L |
8536 | #define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L |
8537 | #define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L |
8538 | //SQ_EDC_FUE_CNTL |
8539 | #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 |
8540 | #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 |
8541 | #define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL |
8542 | #define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L |
8543 | //SQ_WREXEC_EXEC_HI |
8544 | #define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 |
8545 | #define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a |
8546 | #define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c |
8547 | #define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f |
8548 | #define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL |
8549 | #define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L |
8550 | #define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L |
8551 | #define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L |
8552 | //SQ_WREXEC_EXEC_LO |
8553 | #define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 |
8554 | #define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL |
8555 | //SQC_ICACHE_UTCL0_CNTL1 |
8556 | #define SQC_ICACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
8557 | #define SQC_ICACHE_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
8558 | #define SQC_ICACHE_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
8559 | #define SQC_ICACHE_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 |
8560 | #define SQC_ICACHE_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
8561 | #define SQC_ICACHE_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 |
8562 | #define SQC_ICACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
8563 | #define SQC_ICACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
8564 | #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13 |
8565 | #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 |
8566 | #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 |
8567 | #define SQC_ICACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
8568 | #define SQC_ICACHE_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a |
8569 | #define SQC_ICACHE_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
8570 | #define SQC_ICACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
8571 | #define SQC_ICACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
8572 | #define SQC_ICACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
8573 | #define SQC_ICACHE_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
8574 | #define SQC_ICACHE_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
8575 | #define SQC_ICACHE_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L |
8576 | #define SQC_ICACHE_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
8577 | #define SQC_ICACHE_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L |
8578 | #define SQC_ICACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
8579 | #define SQC_ICACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
8580 | #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L |
8581 | #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L |
8582 | #define SQC_ICACHE_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L |
8583 | #define SQC_ICACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
8584 | #define SQC_ICACHE_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L |
8585 | #define SQC_ICACHE_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
8586 | #define SQC_ICACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
8587 | #define SQC_ICACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
8588 | //SQC_ICACHE_UTCL0_CNTL2 |
8589 | #define SQC_ICACHE_UTCL0_CNTL2__SPARE__SHIFT 0x0 |
8590 | #define SQC_ICACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 |
8591 | #define SQC_ICACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
8592 | #define SQC_ICACHE_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa |
8593 | #define SQC_ICACHE_UTCL0_CNTL2__DIS_EDC__SHIFT 0xb |
8594 | #define SQC_ICACHE_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
8595 | #define SQC_ICACHE_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
8596 | #define SQC_ICACHE_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe |
8597 | #define SQC_ICACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
8598 | #define SQC_ICACHE_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT 0x10 |
8599 | #define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
8600 | #define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 |
8601 | #define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
8602 | #define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 |
8603 | #define SQC_ICACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
8604 | #define SQC_ICACHE_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b |
8605 | #define SQC_ICACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c |
8606 | #define SQC_ICACHE_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT 0x1d |
8607 | #define SQC_ICACHE_UTCL0_CNTL2__FGCG_DISABLE__SHIFT 0x1e |
8608 | #define SQC_ICACHE_UTCL0_CNTL2__SPARE_MASK 0x000000FFL |
8609 | #define SQC_ICACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L |
8610 | #define SQC_ICACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
8611 | #define SQC_ICACHE_UTCL0_CNTL2__LINE_VALID_MASK 0x00000400L |
8612 | #define SQC_ICACHE_UTCL0_CNTL2__DIS_EDC_MASK 0x00000800L |
8613 | #define SQC_ICACHE_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
8614 | #define SQC_ICACHE_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
8615 | #define SQC_ICACHE_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
8616 | #define SQC_ICACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
8617 | #define SQC_ICACHE_UTCL0_CNTL2__ARB_BURST_MODE_MASK 0x00030000L |
8618 | #define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
8619 | #define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L |
8620 | #define SQC_ICACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
8621 | #define SQC_ICACHE_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L |
8622 | #define SQC_ICACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
8623 | #define SQC_ICACHE_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L |
8624 | #define SQC_ICACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L |
8625 | #define SQC_ICACHE_UTCL0_CNTL2__GPUVM_16K_DEF_MASK 0x20000000L |
8626 | #define SQC_ICACHE_UTCL0_CNTL2__FGCG_DISABLE_MASK 0x40000000L |
8627 | //SQC_DCACHE_UTCL0_CNTL1 |
8628 | #define SQC_DCACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
8629 | #define SQC_DCACHE_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
8630 | #define SQC_DCACHE_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
8631 | #define SQC_DCACHE_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 |
8632 | #define SQC_DCACHE_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
8633 | #define SQC_DCACHE_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 |
8634 | #define SQC_DCACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
8635 | #define SQC_DCACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
8636 | #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13 |
8637 | #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 |
8638 | #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 |
8639 | #define SQC_DCACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
8640 | #define SQC_DCACHE_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a |
8641 | #define SQC_DCACHE_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
8642 | #define SQC_DCACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
8643 | #define SQC_DCACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
8644 | #define SQC_DCACHE_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
8645 | #define SQC_DCACHE_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
8646 | #define SQC_DCACHE_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
8647 | #define SQC_DCACHE_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L |
8648 | #define SQC_DCACHE_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
8649 | #define SQC_DCACHE_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L |
8650 | #define SQC_DCACHE_UTCL0_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
8651 | #define SQC_DCACHE_UTCL0_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
8652 | #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L |
8653 | #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L |
8654 | #define SQC_DCACHE_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L |
8655 | #define SQC_DCACHE_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
8656 | #define SQC_DCACHE_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L |
8657 | #define SQC_DCACHE_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
8658 | #define SQC_DCACHE_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
8659 | #define SQC_DCACHE_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
8660 | //SQC_DCACHE_UTCL0_CNTL2 |
8661 | #define SQC_DCACHE_UTCL0_CNTL2__SPARE__SHIFT 0x0 |
8662 | #define SQC_DCACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 |
8663 | #define SQC_DCACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
8664 | #define SQC_DCACHE_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa |
8665 | #define SQC_DCACHE_UTCL0_CNTL2__DIS_EDC__SHIFT 0xb |
8666 | #define SQC_DCACHE_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
8667 | #define SQC_DCACHE_UTCL0_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
8668 | #define SQC_DCACHE_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe |
8669 | #define SQC_DCACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
8670 | #define SQC_DCACHE_UTCL0_CNTL2__ARB_BURST_MODE__SHIFT 0x10 |
8671 | #define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
8672 | #define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 |
8673 | #define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
8674 | #define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 |
8675 | #define SQC_DCACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
8676 | #define SQC_DCACHE_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b |
8677 | #define SQC_DCACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c |
8678 | #define SQC_DCACHE_UTCL0_CNTL2__GPUVM_16K_DEF__SHIFT 0x1d |
8679 | #define SQC_DCACHE_UTCL0_CNTL2__FGCG_DISABLE__SHIFT 0x1e |
8680 | #define SQC_DCACHE_UTCL0_CNTL2__SPARE_MASK 0x000000FFL |
8681 | #define SQC_DCACHE_UTCL0_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L |
8682 | #define SQC_DCACHE_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
8683 | #define SQC_DCACHE_UTCL0_CNTL2__LINE_VALID_MASK 0x00000400L |
8684 | #define SQC_DCACHE_UTCL0_CNTL2__DIS_EDC_MASK 0x00000800L |
8685 | #define SQC_DCACHE_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
8686 | #define SQC_DCACHE_UTCL0_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
8687 | #define SQC_DCACHE_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
8688 | #define SQC_DCACHE_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
8689 | #define SQC_DCACHE_UTCL0_CNTL2__ARB_BURST_MODE_MASK 0x00030000L |
8690 | #define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
8691 | #define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L |
8692 | #define SQC_DCACHE_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
8693 | #define SQC_DCACHE_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L |
8694 | #define SQC_DCACHE_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
8695 | #define SQC_DCACHE_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L |
8696 | #define SQC_DCACHE_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L |
8697 | #define SQC_DCACHE_UTCL0_CNTL2__GPUVM_16K_DEF_MASK 0x20000000L |
8698 | #define SQC_DCACHE_UTCL0_CNTL2__FGCG_DISABLE_MASK 0x40000000L |
8699 | //SQC_ICACHE_UTCL0_STATUS |
8700 | #define SQC_ICACHE_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 |
8701 | #define SQC_ICACHE_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 |
8702 | #define SQC_ICACHE_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 |
8703 | #define SQC_ICACHE_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L |
8704 | #define SQC_ICACHE_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L |
8705 | #define SQC_ICACHE_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L |
8706 | //SQC_DCACHE_UTCL0_STATUS |
8707 | #define SQC_DCACHE_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 |
8708 | #define SQC_DCACHE_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 |
8709 | #define SQC_DCACHE_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 |
8710 | #define SQC_DCACHE_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L |
8711 | #define SQC_DCACHE_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L |
8712 | #define SQC_DCACHE_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L |
8713 | |
8714 | |
8715 | // addressBlock: gc_shsdec |
8716 | //SX_DEBUG_1 |
8717 | #define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 |
8718 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 |
8719 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 |
8720 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa |
8721 | #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb |
8722 | #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc |
8723 | #define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT 0xd |
8724 | #define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS__SHIFT 0xe |
8725 | #define SX_DEBUG_1__DISABLE_RAM_FGCG__SHIFT 0xf |
8726 | #define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT__SHIFT 0x10 |
8727 | #define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT__SHIFT 0x11 |
8728 | #define SX_DEBUG_1__DISABLE_BC_RB_PLUS__SHIFT 0x12 |
8729 | #define SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING__SHIFT 0x13 |
8730 | #define SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT__SHIFT 0x14 |
8731 | #define SX_DEBUG_1__DISABLE_GDS_CGTS_OPT__SHIFT 0x15 |
8732 | #define SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT__SHIFT 0x16 |
8733 | #define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x17 |
8734 | #define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL |
8735 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L |
8736 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L |
8737 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L |
8738 | #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L |
8739 | #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L |
8740 | #define SX_DEBUG_1__DISABLE_REP_FGCG_MASK 0x00002000L |
8741 | #define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS_MASK 0x00004000L |
8742 | #define SX_DEBUG_1__DISABLE_RAM_FGCG_MASK 0x00008000L |
8743 | #define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT_MASK 0x00010000L |
8744 | #define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT_MASK 0x00020000L |
8745 | #define SX_DEBUG_1__DISABLE_BC_RB_PLUS_MASK 0x00040000L |
8746 | #define SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING_MASK 0x00080000L |
8747 | #define SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT_MASK 0x00100000L |
8748 | #define SX_DEBUG_1__DISABLE_GDS_CGTS_OPT_MASK 0x00200000L |
8749 | #define SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT_MASK 0x00400000L |
8750 | #define SX_DEBUG_1__DEBUG_DATA_MASK 0xFF800000L |
8751 | //SPI_PS_MAX_WAVE_ID |
8752 | #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
8753 | #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10 |
8754 | #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
8755 | #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L |
8756 | //SPI_START_PHASE |
8757 | #define SPI_START_PHASE__PC_X_PHASE_SE0__SHIFT 0x0 |
8758 | #define SPI_START_PHASE__PC_X_PHASE_SE1__SHIFT 0x2 |
8759 | #define SPI_START_PHASE__PC_X_PHASE_SE2__SHIFT 0x4 |
8760 | #define SPI_START_PHASE__PC_X_PHASE_SE3__SHIFT 0x6 |
8761 | #define SPI_START_PHASE__PC_X_PHASE_SE0_MASK 0x00000003L |
8762 | #define SPI_START_PHASE__PC_X_PHASE_SE1_MASK 0x0000000CL |
8763 | #define SPI_START_PHASE__PC_X_PHASE_SE2_MASK 0x00000030L |
8764 | #define SPI_START_PHASE__PC_X_PHASE_SE3_MASK 0x000000C0L |
8765 | //SPI_GFX_CNTL |
8766 | #define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 |
8767 | #define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L |
8768 | //SPI_DSM_CNTL |
8769 | #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
8770 | #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
8771 | #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
8772 | #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
8773 | //SPI_DSM_CNTL2 |
8774 | #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
8775 | #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
8776 | #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x3 |
8777 | #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
8778 | #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
8779 | #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000001F8L |
8780 | //SPI_EDC_CNT |
8781 | #define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0 |
8782 | #define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L |
8783 | //SPI_USER_ACCUM_VMID_CNTL |
8784 | #define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM__SHIFT 0x0 |
8785 | #define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM_MASK 0x0000000FL |
8786 | //SPI_CONFIG_CNTL |
8787 | #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 |
8788 | #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 |
8789 | #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 |
8790 | #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 |
8791 | #define SPI_CONFIG_CNTL__FORCE_HALF_RATE_PC_EXP__SHIFT 0x1a |
8792 | #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b |
8793 | #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c |
8794 | #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d |
8795 | #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e |
8796 | #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL |
8797 | #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L |
8798 | #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L |
8799 | #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L |
8800 | #define SPI_CONFIG_CNTL__FORCE_HALF_RATE_PC_EXP_MASK 0x04000000L |
8801 | #define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L |
8802 | #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L |
8803 | #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L |
8804 | #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L |
8805 | //SPI_WAVE_LIMIT_CNTL |
8806 | #define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT 0x0 |
8807 | #define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN__SHIFT 0x2 |
8808 | #define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT 0x4 |
8809 | #define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT 0x6 |
8810 | #define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK 0x00000003L |
8811 | #define SPI_WAVE_LIMIT_CNTL__VS_WAVE_GRAN_MASK 0x0000000CL |
8812 | #define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK 0x00000030L |
8813 | #define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK 0x000000C0L |
8814 | //SPI_CONFIG_CNTL_2 |
8815 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 |
8816 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 |
8817 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL |
8818 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L |
8819 | //SPI_CONFIG_CNTL_1 |
8820 | #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 |
8821 | #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 |
8822 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x5 |
8823 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 |
8824 | #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 |
8825 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 |
8826 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa |
8827 | #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe |
8828 | #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf |
8829 | #define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT__SHIFT 0x10 |
8830 | #define SPI_CONFIG_CNTL_1__EN_USER_ACCUM__SHIFT 0x15 |
8831 | #define SPI_CONFIG_CNTL_1__SA_SCREEN_MAP__SHIFT 0x16 |
8832 | #define SPI_CONFIG_CNTL_1__RESERVED__SHIFT 0x17 |
8833 | #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL |
8834 | #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L |
8835 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000060L |
8836 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L |
8837 | #define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L |
8838 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L |
8839 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L |
8840 | #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L |
8841 | #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L |
8842 | #define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT_MASK 0x001F0000L |
8843 | #define SPI_CONFIG_CNTL_1__EN_USER_ACCUM_MASK 0x00200000L |
8844 | #define SPI_CONFIG_CNTL_1__SA_SCREEN_MAP_MASK 0x00400000L |
8845 | #define SPI_CONFIG_CNTL_1__RESERVED_MASK 0xFF800000L |
8846 | //SPI_CONFIG_PS_CU_EN |
8847 | #define SPI_CONFIG_PS_CU_EN__PKR_OFFSET__SHIFT 0x0 |
8848 | #define SPI_CONFIG_PS_CU_EN__PKR_OFFSET_MASK 0x0000000FL |
8849 | //SPI_WF_LIFETIME_CNTL |
8850 | #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 |
8851 | #define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 |
8852 | #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL |
8853 | #define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L |
8854 | //SPI_WF_LIFETIME_LIMIT_0 |
8855 | #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 |
8856 | #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f |
8857 | #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL |
8858 | #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L |
8859 | //SPI_WF_LIFETIME_LIMIT_1 |
8860 | #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 |
8861 | #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f |
8862 | #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL |
8863 | #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L |
8864 | //SPI_WF_LIFETIME_LIMIT_2 |
8865 | #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 |
8866 | #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f |
8867 | #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL |
8868 | #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L |
8869 | //SPI_WF_LIFETIME_LIMIT_3 |
8870 | #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 |
8871 | #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f |
8872 | #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL |
8873 | #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L |
8874 | //SPI_WF_LIFETIME_LIMIT_4 |
8875 | #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 |
8876 | #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f |
8877 | #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL |
8878 | #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L |
8879 | //SPI_WF_LIFETIME_LIMIT_5 |
8880 | #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 |
8881 | #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f |
8882 | #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL |
8883 | #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L |
8884 | //SPI_WF_LIFETIME_STATUS_0 |
8885 | #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 |
8886 | #define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f |
8887 | #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL |
8888 | #define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L |
8889 | //SPI_WF_LIFETIME_STATUS_1 |
8890 | #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 |
8891 | #define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f |
8892 | #define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL |
8893 | #define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L |
8894 | //SPI_WF_LIFETIME_STATUS_2 |
8895 | #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 |
8896 | #define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f |
8897 | #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL |
8898 | #define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L |
8899 | //SPI_WF_LIFETIME_STATUS_4 |
8900 | #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 |
8901 | #define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f |
8902 | #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL |
8903 | #define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L |
8904 | //SPI_WF_LIFETIME_STATUS_6 |
8905 | #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 |
8906 | #define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f |
8907 | #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL |
8908 | #define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L |
8909 | //SPI_WF_LIFETIME_STATUS_7 |
8910 | #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 |
8911 | #define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f |
8912 | #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL |
8913 | #define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L |
8914 | //SPI_WF_LIFETIME_STATUS_8 |
8915 | #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 |
8916 | #define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f |
8917 | #define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL |
8918 | #define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L |
8919 | //SPI_WF_LIFETIME_STATUS_9 |
8920 | #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 |
8921 | #define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f |
8922 | #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL |
8923 | #define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L |
8924 | //SPI_WF_LIFETIME_STATUS_11 |
8925 | #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 |
8926 | #define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f |
8927 | #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL |
8928 | #define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L |
8929 | //SPI_WF_LIFETIME_STATUS_13 |
8930 | #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 |
8931 | #define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f |
8932 | #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL |
8933 | #define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L |
8934 | //SPI_WF_LIFETIME_STATUS_14 |
8935 | #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 |
8936 | #define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f |
8937 | #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL |
8938 | #define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L |
8939 | //SPI_WF_LIFETIME_STATUS_15 |
8940 | #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 |
8941 | #define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f |
8942 | #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL |
8943 | #define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L |
8944 | //SPI_WF_LIFETIME_STATUS_16 |
8945 | #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 |
8946 | #define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f |
8947 | #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL |
8948 | #define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L |
8949 | //SPI_WF_LIFETIME_STATUS_17 |
8950 | #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 |
8951 | #define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f |
8952 | #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL |
8953 | #define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L |
8954 | //SPI_WF_LIFETIME_STATUS_18 |
8955 | #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 |
8956 | #define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f |
8957 | #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL |
8958 | #define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L |
8959 | //SPI_WF_LIFETIME_STATUS_19 |
8960 | #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 |
8961 | #define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f |
8962 | #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL |
8963 | #define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L |
8964 | //SPI_WF_LIFETIME_STATUS_20 |
8965 | #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 |
8966 | #define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f |
8967 | #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL |
8968 | #define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L |
8969 | //SPI_WF_LIFETIME_STATUS_21 |
8970 | #define SPI_WF_LIFETIME_STATUS_21__MAX_CNT__SHIFT 0x0 |
8971 | #define SPI_WF_LIFETIME_STATUS_21__INT_SENT__SHIFT 0x1f |
8972 | #define SPI_WF_LIFETIME_STATUS_21__MAX_CNT_MASK 0x7FFFFFFFL |
8973 | #define SPI_WF_LIFETIME_STATUS_21__INT_SENT_MASK 0x80000000L |
8974 | //SPI_LB_CTR_CTRL |
8975 | #define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 |
8976 | #define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1 |
8977 | #define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3 |
8978 | #define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4 |
8979 | #define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L |
8980 | #define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L |
8981 | #define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L |
8982 | #define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L |
8983 | //SPI_LB_WGP_MASK |
8984 | #define SPI_LB_WGP_MASK__WGP_MASK__SHIFT 0x0 |
8985 | #define SPI_LB_WGP_MASK__WGP_MASK_MASK 0xFFFFL |
8986 | //SPI_LB_DATA_REG |
8987 | #define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 |
8988 | #define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL |
8989 | //SPI_PG_ENABLE_STATIC_WGP_MASK |
8990 | #define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK__SHIFT 0x0 |
8991 | #define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK_MASK 0xFFFFL |
8992 | //SPI_GDS_CREDITS |
8993 | #define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 |
8994 | #define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 |
8995 | #define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL |
8996 | #define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L |
8997 | //SPI_SX_EXPORT_BUFFER_SIZES |
8998 | #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 |
8999 | #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 |
9000 | #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL |
9001 | #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L |
9002 | //SPI_SX_SCOREBOARD_BUFFER_SIZES |
9003 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 |
9004 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 |
9005 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL |
9006 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L |
9007 | //SPI_CSQ_WF_ACTIVE_STATUS |
9008 | #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 |
9009 | #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL |
9010 | //SPI_CSQ_WF_ACTIVE_COUNT_0 |
9011 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 |
9012 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10 |
9013 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL |
9014 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L |
9015 | //SPI_CSQ_WF_ACTIVE_COUNT_1 |
9016 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 |
9017 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10 |
9018 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL |
9019 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L |
9020 | //SPI_CSQ_WF_ACTIVE_COUNT_2 |
9021 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 |
9022 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10 |
9023 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL |
9024 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L |
9025 | //SPI_CSQ_WF_ACTIVE_COUNT_3 |
9026 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 |
9027 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10 |
9028 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL |
9029 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L |
9030 | //SPI_LB_DATA_WAVES |
9031 | #define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0 |
9032 | #define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10 |
9033 | #define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL |
9034 | #define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L |
9035 | //SPI_LB_DATA_PERWGP_WAVE_HSGS |
9036 | #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS__SHIFT 0x0 |
9037 | #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS__SHIFT 0x10 |
9038 | #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS_MASK 0x0000FFFFL |
9039 | #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS_MASK 0xFFFF0000L |
9040 | //SPI_LB_DATA_PERWGP_WAVE_VSPS |
9041 | #define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_VS__SHIFT 0x0 |
9042 | #define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_PS__SHIFT 0x10 |
9043 | #define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_VS_MASK 0x0000FFFFL |
9044 | #define SPI_LB_DATA_PERWGP_WAVE_VSPS__WGP_USED_PS_MASK 0xFFFF0000L |
9045 | //SPI_LB_DATA_PERWGP_WAVE_CS |
9046 | #define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE__SHIFT 0x0 |
9047 | #define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE_MASK 0xFFFFL |
9048 | //SPI_P0_TRAP_SCREEN_PSBA_LO |
9049 | #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 |
9050 | #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
9051 | //SPI_P0_TRAP_SCREEN_PSBA_HI |
9052 | #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 |
9053 | #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL |
9054 | //SPI_P0_TRAP_SCREEN_PSMA_LO |
9055 | #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 |
9056 | #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
9057 | //SPI_P0_TRAP_SCREEN_PSMA_HI |
9058 | #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 |
9059 | #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL |
9060 | //SPI_P0_TRAP_SCREEN_GPR_MIN |
9061 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 |
9062 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 |
9063 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL |
9064 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L |
9065 | //SPI_P1_TRAP_SCREEN_PSBA_LO |
9066 | #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 |
9067 | #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
9068 | //SPI_P1_TRAP_SCREEN_PSBA_HI |
9069 | #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 |
9070 | #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL |
9071 | //SPI_P1_TRAP_SCREEN_PSMA_LO |
9072 | #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 |
9073 | #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
9074 | //SPI_P1_TRAP_SCREEN_PSMA_HI |
9075 | #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 |
9076 | #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL |
9077 | //SPI_P1_TRAP_SCREEN_GPR_MIN |
9078 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 |
9079 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 |
9080 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL |
9081 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L |
9082 | |
9083 | |
9084 | // addressBlock: gc_tpdec |
9085 | //TD_STATUS |
9086 | #define TD_STATUS__BUSY__SHIFT 0x1f |
9087 | #define TD_STATUS__BUSY_MASK 0x80000000L |
9088 | //TD_DSM_CNTL |
9089 | #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0 |
9090 | #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
9091 | #define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3 |
9092 | #define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
9093 | #define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 |
9094 | #define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
9095 | #define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L |
9096 | #define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
9097 | #define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L |
9098 | #define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
9099 | #define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
9100 | #define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
9101 | //TD_DSM_CNTL2 |
9102 | #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0 |
9103 | #define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2 |
9104 | #define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3 |
9105 | #define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5 |
9106 | #define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 |
9107 | #define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 |
9108 | #define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a |
9109 | #define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L |
9110 | #define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L |
9111 | #define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L |
9112 | #define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L |
9113 | #define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
9114 | #define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L |
9115 | #define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L |
9116 | //TD_SCRATCH |
9117 | #define TD_SCRATCH__SCRATCH__SHIFT 0x0 |
9118 | #define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL |
9119 | //TA_CNTL |
9120 | #define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 |
9121 | #define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 |
9122 | #define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L |
9123 | #define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L |
9124 | //TA_RESERVED_010C |
9125 | #define TA_RESERVED_010C__Unused__SHIFT 0x0 |
9126 | #define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL |
9127 | //TA_STATUS |
9128 | #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc |
9129 | #define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd |
9130 | #define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe |
9131 | #define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 |
9132 | #define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 |
9133 | #define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 |
9134 | #define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 |
9135 | #define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 |
9136 | #define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 |
9137 | #define TA_STATUS__IN_BUSY__SHIFT 0x18 |
9138 | #define TA_STATUS__FG_BUSY__SHIFT 0x19 |
9139 | #define TA_STATUS__LA_BUSY__SHIFT 0x1a |
9140 | #define TA_STATUS__FL_BUSY__SHIFT 0x1b |
9141 | #define TA_STATUS__TA_BUSY__SHIFT 0x1c |
9142 | #define TA_STATUS__FA_BUSY__SHIFT 0x1d |
9143 | #define TA_STATUS__AL_BUSY__SHIFT 0x1e |
9144 | #define TA_STATUS__BUSY__SHIFT 0x1f |
9145 | #define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L |
9146 | #define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L |
9147 | #define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L |
9148 | #define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L |
9149 | #define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L |
9150 | #define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L |
9151 | #define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L |
9152 | #define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L |
9153 | #define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L |
9154 | #define TA_STATUS__IN_BUSY_MASK 0x01000000L |
9155 | #define TA_STATUS__FG_BUSY_MASK 0x02000000L |
9156 | #define TA_STATUS__LA_BUSY_MASK 0x04000000L |
9157 | #define TA_STATUS__FL_BUSY_MASK 0x08000000L |
9158 | #define TA_STATUS__TA_BUSY_MASK 0x10000000L |
9159 | #define TA_STATUS__FA_BUSY_MASK 0x20000000L |
9160 | #define TA_STATUS__AL_BUSY_MASK 0x40000000L |
9161 | #define TA_STATUS__BUSY_MASK 0x80000000L |
9162 | //TA_SCRATCH |
9163 | #define TA_SCRATCH__SCRATCH__SHIFT 0x0 |
9164 | #define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL |
9165 | |
9166 | |
9167 | // addressBlock: gc_gdsdec |
9168 | //GDS_CONFIG |
9169 | #define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 |
9170 | #define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 |
9171 | #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 |
9172 | #define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 |
9173 | #define GDS_CONFIG__UNUSED__SHIFT 0x9 |
9174 | #define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L |
9175 | #define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L |
9176 | #define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L |
9177 | #define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L |
9178 | #define GDS_CONFIG__UNUSED_MASK 0xFFFFFE00L |
9179 | //GDS_CNTL_STATUS |
9180 | #define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 |
9181 | #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 |
9182 | #define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 |
9183 | #define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 |
9184 | #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 |
9185 | #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 |
9186 | #define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 |
9187 | #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7 |
9188 | #define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8 |
9189 | #define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9 |
9190 | #define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa |
9191 | #define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb |
9192 | #define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc |
9193 | #define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd |
9194 | #define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe |
9195 | #define GDS_CNTL_STATUS__UNUSED__SHIFT 0xf |
9196 | #define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L |
9197 | #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L |
9198 | #define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L |
9199 | #define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L |
9200 | #define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L |
9201 | #define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L |
9202 | #define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L |
9203 | #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L |
9204 | #define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L |
9205 | #define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L |
9206 | #define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L |
9207 | #define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L |
9208 | #define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L |
9209 | #define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L |
9210 | #define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L |
9211 | #define GDS_CNTL_STATUS__UNUSED_MASK 0xFFFF8000L |
9212 | //GDS_ENHANCE |
9213 | #define GDS_ENHANCE__MISC__SHIFT 0x0 |
9214 | #define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 |
9215 | #define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 |
9216 | #define GDS_ENHANCE__UNUSED__SHIFT 0x12 |
9217 | #define GDS_ENHANCE__MISC_MASK 0x0000FFFFL |
9218 | #define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L |
9219 | #define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L |
9220 | #define GDS_ENHANCE__UNUSED_MASK 0xFFFC0000L |
9221 | //GDS_PROTECTION_FAULT |
9222 | #define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 |
9223 | #define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 |
9224 | #define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 |
9225 | #define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 |
9226 | #define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 |
9227 | #define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa |
9228 | #define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc |
9229 | #define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 |
9230 | #define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L |
9231 | #define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L |
9232 | #define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L |
9233 | #define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L |
9234 | #define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L |
9235 | #define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L |
9236 | #define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L |
9237 | #define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L |
9238 | //GDS_VM_PROTECTION_FAULT |
9239 | #define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 |
9240 | #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 |
9241 | #define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 |
9242 | #define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 |
9243 | #define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 |
9244 | #define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5 |
9245 | #define GDS_VM_PROTECTION_FAULT__UNUSED1__SHIFT 0x6 |
9246 | #define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 |
9247 | #define GDS_VM_PROTECTION_FAULT__UNUSED2__SHIFT 0xc |
9248 | #define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 |
9249 | #define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L |
9250 | #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L |
9251 | #define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L |
9252 | #define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L |
9253 | #define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L |
9254 | #define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L |
9255 | #define GDS_VM_PROTECTION_FAULT__UNUSED1_MASK 0x000000C0L |
9256 | #define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L |
9257 | #define GDS_VM_PROTECTION_FAULT__UNUSED2_MASK 0x0000F000L |
9258 | #define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L |
9259 | //GDS_EDC_CNT |
9260 | #define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0 |
9261 | #define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2 |
9262 | #define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4 |
9263 | #define GDS_EDC_CNT__UNUSED__SHIFT 0x6 |
9264 | #define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L |
9265 | #define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL |
9266 | #define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L |
9267 | #define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L |
9268 | //GDS_EDC_GRBM_CNT |
9269 | #define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 |
9270 | #define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2 |
9271 | #define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4 |
9272 | #define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L |
9273 | #define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL |
9274 | #define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L |
9275 | //GDS_EDC_OA_DED |
9276 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 |
9277 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 |
9278 | #define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 |
9279 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3 |
9280 | #define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 |
9281 | #define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 |
9282 | #define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 |
9283 | #define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 |
9284 | #define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 |
9285 | #define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 |
9286 | #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa |
9287 | #define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb |
9288 | #define GDS_EDC_OA_DED__ME0_PIPE1_CS_DED__SHIFT 0xc |
9289 | #define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xd |
9290 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L |
9291 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L |
9292 | #define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L |
9293 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L |
9294 | #define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L |
9295 | #define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L |
9296 | #define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L |
9297 | #define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L |
9298 | #define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L |
9299 | #define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L |
9300 | #define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L |
9301 | #define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L |
9302 | #define GDS_EDC_OA_DED__ME0_PIPE1_CS_DED_MASK 0x00001000L |
9303 | #define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFE000L |
9304 | //GDS_DSM_CNTL |
9305 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0 |
9306 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1 |
9307 | #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
9308 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3 |
9309 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4 |
9310 | #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
9311 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6 |
9312 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7 |
9313 | #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
9314 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9 |
9315 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa |
9316 | #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
9317 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc |
9318 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd |
9319 | #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
9320 | #define GDS_DSM_CNTL__UNUSED__SHIFT 0xf |
9321 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L |
9322 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L |
9323 | #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
9324 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L |
9325 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L |
9326 | #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
9327 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L |
9328 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L |
9329 | #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
9330 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L |
9331 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L |
9332 | #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
9333 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L |
9334 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L |
9335 | #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
9336 | #define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L |
9337 | //GDS_EDC_OA_PHY_CNT |
9338 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0 |
9339 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2 |
9340 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4 |
9341 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6 |
9342 | #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8 |
9343 | #define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa |
9344 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L |
9345 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL |
9346 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L |
9347 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L |
9348 | #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L |
9349 | #define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L |
9350 | //GDS_EDC_OA_PIPE_CNT |
9351 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0 |
9352 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2 |
9353 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4 |
9354 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6 |
9355 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8 |
9356 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa |
9357 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc |
9358 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe |
9359 | #define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10 |
9360 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L |
9361 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL |
9362 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L |
9363 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L |
9364 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L |
9365 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L |
9366 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L |
9367 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L |
9368 | #define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L |
9369 | //GDS_DSM_CNTL2 |
9370 | #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
9371 | #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
9372 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3 |
9373 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5 |
9374 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
9375 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 |
9376 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
9377 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb |
9378 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
9379 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe |
9380 | #define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf |
9381 | #define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a |
9382 | #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
9383 | #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
9384 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L |
9385 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L |
9386 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
9387 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L |
9388 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
9389 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L |
9390 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
9391 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
9392 | #define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L |
9393 | #define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L |
9394 | //GDS_WD_GDS_CSB |
9395 | #define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0 |
9396 | #define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd |
9397 | #define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL |
9398 | #define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L |
9399 | |
9400 | |
9401 | // addressBlock: gc_rbdec |
9402 | //DB_DEBUG |
9403 | #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 |
9404 | #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 |
9405 | #define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 |
9406 | #define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 |
9407 | #define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 |
9408 | #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 |
9409 | #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 |
9410 | #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 |
9411 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa |
9412 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc |
9413 | #define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe |
9414 | #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf |
9415 | #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 |
9416 | #define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 |
9417 | #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 |
9418 | #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 |
9419 | #define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 |
9420 | #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 |
9421 | #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 |
9422 | #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 |
9423 | #define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c |
9424 | #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d |
9425 | #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e |
9426 | #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f |
9427 | #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L |
9428 | #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L |
9429 | #define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L |
9430 | #define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L |
9431 | #define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L |
9432 | #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L |
9433 | #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L |
9434 | #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L |
9435 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L |
9436 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L |
9437 | #define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L |
9438 | #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L |
9439 | #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L |
9440 | #define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L |
9441 | #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L |
9442 | #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L |
9443 | #define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L |
9444 | #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L |
9445 | #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L |
9446 | #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L |
9447 | #define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L |
9448 | #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L |
9449 | #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L |
9450 | #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L |
9451 | //DB_DEBUG2 |
9452 | #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 |
9453 | #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 |
9454 | #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 |
9455 | #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 |
9456 | #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 |
9457 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5 |
9458 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6 |
9459 | #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7 |
9460 | #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8 |
9461 | #define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 |
9462 | #define DB_DEBUG2__FORCE_PERF_COUNTERS_ON__SHIFT 0xe |
9463 | #define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT 0xf |
9464 | #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10 |
9465 | #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 |
9466 | #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 |
9467 | #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 |
9468 | #define DB_DEBUG2__FULL_TILE_WAVE_BREAK_MODE__SHIFT 0x14 |
9469 | #define DB_DEBUG2__DUAL_PIPE_REZ_STALL_MANUAL_CONTROL__SHIFT 0x16 |
9470 | #define DB_DEBUG2__DUAL_PIPE_REZ_STALL_SELECT_NEW__SHIFT 0x17 |
9471 | #define DB_DEBUG2__FORCE_ITERATE_256__SHIFT 0x18 |
9472 | #define DB_DEBUG2__RESERVED1__SHIFT 0x1a |
9473 | #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c |
9474 | #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d |
9475 | #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e |
9476 | #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f |
9477 | #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L |
9478 | #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L |
9479 | #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L |
9480 | #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L |
9481 | #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L |
9482 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L |
9483 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L |
9484 | #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L |
9485 | #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L |
9486 | #define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L |
9487 | #define DB_DEBUG2__FORCE_PERF_COUNTERS_ON_MASK 0x00004000L |
9488 | #define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK 0x00008000L |
9489 | #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x00010000L |
9490 | #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L |
9491 | #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L |
9492 | #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L |
9493 | #define DB_DEBUG2__FULL_TILE_WAVE_BREAK_MODE_MASK 0x00300000L |
9494 | #define DB_DEBUG2__DUAL_PIPE_REZ_STALL_MANUAL_CONTROL_MASK 0x00400000L |
9495 | #define DB_DEBUG2__DUAL_PIPE_REZ_STALL_SELECT_NEW_MASK 0x00800000L |
9496 | #define DB_DEBUG2__FORCE_ITERATE_256_MASK 0x03000000L |
9497 | #define DB_DEBUG2__RESERVED1_MASK 0x04000000L |
9498 | #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L |
9499 | #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L |
9500 | #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L |
9501 | #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L |
9502 | //DB_DEBUG3 |
9503 | #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0 |
9504 | #define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA__SHIFT 0x1 |
9505 | #define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 |
9506 | #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 |
9507 | #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 |
9508 | #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 |
9509 | #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 |
9510 | #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 |
9511 | #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 |
9512 | #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 |
9513 | #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa |
9514 | #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb |
9515 | #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc |
9516 | #define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd |
9517 | #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe |
9518 | #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf |
9519 | #define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH__SHIFT 0x10 |
9520 | #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 |
9521 | #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 |
9522 | #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 |
9523 | #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 |
9524 | #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 |
9525 | #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 |
9526 | #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 |
9527 | #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 |
9528 | #define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 |
9529 | #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a |
9530 | #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b |
9531 | #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c |
9532 | #define DB_DEBUG3__DELETE_CONTEXT_SUSPEND__SHIFT 0x1d |
9533 | #define DB_DEBUG3__DISABLE_TS_WRITE_L0__SHIFT 0x1e |
9534 | #define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT__SHIFT 0x1f |
9535 | #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L |
9536 | #define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA_MASK 0x00000002L |
9537 | #define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L |
9538 | #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L |
9539 | #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L |
9540 | #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L |
9541 | #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L |
9542 | #define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L |
9543 | #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L |
9544 | #define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L |
9545 | #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L |
9546 | #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L |
9547 | #define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L |
9548 | #define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L |
9549 | #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L |
9550 | #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L |
9551 | #define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH_MASK 0x00010000L |
9552 | #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L |
9553 | #define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L |
9554 | #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L |
9555 | #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L |
9556 | #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L |
9557 | #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L |
9558 | #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L |
9559 | #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L |
9560 | #define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L |
9561 | #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L |
9562 | #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L |
9563 | #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L |
9564 | #define DB_DEBUG3__DELETE_CONTEXT_SUSPEND_MASK 0x20000000L |
9565 | #define DB_DEBUG3__DISABLE_TS_WRITE_L0_MASK 0x40000000L |
9566 | #define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT_MASK 0x80000000L |
9567 | //DB_DEBUG4 |
9568 | #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 |
9569 | #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 |
9570 | #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 |
9571 | #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 |
9572 | #define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK__SHIFT 0x4 |
9573 | #define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0x5 |
9574 | #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x6 |
9575 | #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x7 |
9576 | #define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8 |
9577 | #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9 |
9578 | #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa |
9579 | #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb |
9580 | #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0xc |
9581 | #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd |
9582 | #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe |
9583 | #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0xf |
9584 | #define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT__SHIFT 0x10 |
9585 | #define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT__SHIFT 0x11 |
9586 | #define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE__SHIFT 0x12 |
9587 | #define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE__SHIFT 0x13 |
9588 | #define DB_DEBUG4__DISABLE_LATEZ_NO_EXPORT_POWER_SAVING__SHIFT 0x14 |
9589 | #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO__SHIFT 0x15 |
9590 | #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT__SHIFT 0x16 |
9591 | #define DB_DEBUG4__DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK__SHIFT 0x17 |
9592 | #define DB_DEBUG4__WR_MEM_BURST_CTL__SHIFT 0x18 |
9593 | #define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING__SHIFT 0x1b |
9594 | #define DB_DEBUG4__DISABLE_RD_MEM_BURST__SHIFT 0x1c |
9595 | #define DB_DEBUG4__LATE_ACK_SCOREBOARD_NEW__SHIFT 0x1d |
9596 | #define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT__SHIFT 0x1e |
9597 | #define DB_DEBUG4__LATE_ACK_PSD_EOP_GFX9_METHOD__SHIFT 0x1f |
9598 | #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L |
9599 | #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L |
9600 | #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L |
9601 | #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L |
9602 | #define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK_MASK 0x00000010L |
9603 | #define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00000020L |
9604 | #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000040L |
9605 | #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000080L |
9606 | #define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L |
9607 | #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L |
9608 | #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L |
9609 | #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L |
9610 | #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00001000L |
9611 | #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L |
9612 | #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L |
9613 | #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00008000L |
9614 | #define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT_MASK 0x00010000L |
9615 | #define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_ACCUM_ALL_EOT_MASK 0x00020000L |
9616 | #define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE_MASK 0x00040000L |
9617 | #define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE_MASK 0x00080000L |
9618 | #define DB_DEBUG4__DISABLE_LATEZ_NO_EXPORT_POWER_SAVING_MASK 0x00100000L |
9619 | #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_MASK 0x00200000L |
9620 | #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT_MASK 0x00400000L |
9621 | #define DB_DEBUG4__DISABLE_WR_MEM_BURST_FLF_CONSECUTIVE_CHECK_MASK 0x00800000L |
9622 | #define DB_DEBUG4__WR_MEM_BURST_CTL_MASK 0x07000000L |
9623 | #define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING_MASK 0x08000000L |
9624 | #define DB_DEBUG4__DISABLE_RD_MEM_BURST_MASK 0x10000000L |
9625 | #define DB_DEBUG4__LATE_ACK_SCOREBOARD_NEW_MASK 0x20000000L |
9626 | #define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT_MASK 0x40000000L |
9627 | #define DB_DEBUG4__LATE_ACK_PSD_EOP_GFX9_METHOD_MASK 0x80000000L |
9628 | //DB_ETILE_STUTTER_CONTROL |
9629 | #define DB_ETILE_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 |
9630 | #define DB_ETILE_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 |
9631 | #define DB_ETILE_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL |
9632 | #define DB_ETILE_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L |
9633 | //DB_LTILE_STUTTER_CONTROL |
9634 | #define DB_LTILE_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 |
9635 | #define DB_LTILE_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 |
9636 | #define DB_LTILE_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL |
9637 | #define DB_LTILE_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L |
9638 | //DB_EQUAD_STUTTER_CONTROL |
9639 | #define DB_EQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 |
9640 | #define DB_EQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 |
9641 | #define DB_EQUAD_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL |
9642 | #define DB_EQUAD_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L |
9643 | //DB_LQUAD_STUTTER_CONTROL |
9644 | #define DB_LQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 |
9645 | #define DB_LQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 |
9646 | #define DB_LQUAD_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL |
9647 | #define DB_LQUAD_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L |
9648 | //DB_CREDIT_LIMIT |
9649 | #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 |
9650 | #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 |
9651 | #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa |
9652 | #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 |
9653 | #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL |
9654 | #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L |
9655 | #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L |
9656 | #define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L |
9657 | //DB_WATERMARKS |
9658 | #define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 |
9659 | #define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x8 |
9660 | #define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x10 |
9661 | #define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x18 |
9662 | #define DB_WATERMARKS__DEPTH_FREE_MASK 0x000000FFL |
9663 | #define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x0000FF00L |
9664 | #define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x00FF0000L |
9665 | #define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0xFF000000L |
9666 | //DB_SUBTILE_CONTROL |
9667 | #define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 |
9668 | #define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 |
9669 | #define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 |
9670 | #define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 |
9671 | #define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 |
9672 | #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa |
9673 | #define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc |
9674 | #define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe |
9675 | #define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 |
9676 | #define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 |
9677 | #define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L |
9678 | #define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL |
9679 | #define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L |
9680 | #define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L |
9681 | #define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L |
9682 | #define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L |
9683 | #define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L |
9684 | #define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L |
9685 | #define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L |
9686 | #define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L |
9687 | //DB_FREE_CACHELINES |
9688 | #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 |
9689 | #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x8 |
9690 | #define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x10 |
9691 | #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x18 |
9692 | #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x000000FFL |
9693 | #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x0000FF00L |
9694 | #define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x00FF0000L |
9695 | #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0xFF000000L |
9696 | //DB_FIFO_DEPTH1 |
9697 | #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0 |
9698 | #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x8 |
9699 | #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0x10 |
9700 | #define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x18 |
9701 | #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x000000FFL |
9702 | #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x0000FF00L |
9703 | #define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x00FF0000L |
9704 | #define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0xFF000000L |
9705 | //DB_FIFO_DEPTH2 |
9706 | #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 |
9707 | #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 |
9708 | #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x10 |
9709 | #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 |
9710 | #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL |
9711 | #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x0000FF00L |
9712 | #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF0000L |
9713 | #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L |
9714 | //DB_LAST_OF_BURST_CONFIG |
9715 | #define DB_LAST_OF_BURST_CONFIG__MAXBURST__SHIFT 0x0 |
9716 | #define DB_LAST_OF_BURST_CONFIG__TIMEOUT__SHIFT 0x8 |
9717 | #define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT__SHIFT 0xb |
9718 | #define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_USES_MAXBURST__SHIFT 0x10 |
9719 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT__SHIFT 0x11 |
9720 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB__SHIFT 0x12 |
9721 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B__SHIFT 0x13 |
9722 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB__SHIFT 0x14 |
9723 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO__SHIFT 0x15 |
9724 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST__SHIFT 0x19 |
9725 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR__SHIFT 0x1a |
9726 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_RD_BA_ACCUM__SHIFT 0x1b |
9727 | #define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA__SHIFT 0x1c |
9728 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_256B_COALESCE__SHIFT 0x1d |
9729 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST__SHIFT 0x1e |
9730 | #define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN__SHIFT 0x1f |
9731 | #define DB_LAST_OF_BURST_CONFIG__MAXBURST_MASK 0x000000FFL |
9732 | #define DB_LAST_OF_BURST_CONFIG__TIMEOUT_MASK 0x00000700L |
9733 | #define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT_MASK 0x0000F800L |
9734 | #define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_USES_MAXBURST_MASK 0x00010000L |
9735 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT_MASK 0x00020000L |
9736 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB_MASK 0x00040000L |
9737 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B_MASK 0x00080000L |
9738 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB_MASK 0x00100000L |
9739 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO_MASK 0x00200000L |
9740 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST_MASK 0x02000000L |
9741 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR_MASK 0x04000000L |
9742 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_RD_BA_ACCUM_MASK 0x08000000L |
9743 | #define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA_MASK 0x10000000L |
9744 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_256B_COALESCE_MASK 0x20000000L |
9745 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST_MASK 0x40000000L |
9746 | #define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN_MASK 0x80000000L |
9747 | //DB_RING_CONTROL |
9748 | #define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 |
9749 | #define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L |
9750 | //DB_MEM_ARB_WATERMARKS |
9751 | #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0 |
9752 | #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8 |
9753 | #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10 |
9754 | #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18 |
9755 | #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L |
9756 | #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L |
9757 | #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L |
9758 | #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L |
9759 | //DB_FIFO_DEPTH3 |
9760 | #define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x0 |
9761 | #define DB_FIFO_DEPTH3__QUAD_READ_REQS__SHIFT 0x18 |
9762 | #define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH_MASK 0x000000FFL |
9763 | #define DB_FIFO_DEPTH3__QUAD_READ_REQS_MASK 0xFF000000L |
9764 | //DB_RMI_BC_GL2_CACHE_CONTROL |
9765 | #define DB_RMI_BC_GL2_CACHE_CONTROL__Z_WR_POLICY__SHIFT 0x0 |
9766 | #define DB_RMI_BC_GL2_CACHE_CONTROL__S_WR_POLICY__SHIFT 0x2 |
9767 | #define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT 0x4 |
9768 | #define DB_RMI_BC_GL2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT 0x6 |
9769 | #define DB_RMI_BC_GL2_CACHE_CONTROL__Z_RD_POLICY__SHIFT 0x10 |
9770 | #define DB_RMI_BC_GL2_CACHE_CONTROL__S_RD_POLICY__SHIFT 0x12 |
9771 | #define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT 0x14 |
9772 | #define DB_RMI_BC_GL2_CACHE_CONTROL__VOL__SHIFT 0x1f |
9773 | #define DB_RMI_BC_GL2_CACHE_CONTROL__Z_WR_POLICY_MASK 0x00000003L |
9774 | #define DB_RMI_BC_GL2_CACHE_CONTROL__S_WR_POLICY_MASK 0x0000000CL |
9775 | #define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_WR_POLICY_MASK 0x00000030L |
9776 | #define DB_RMI_BC_GL2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK 0x000000C0L |
9777 | #define DB_RMI_BC_GL2_CACHE_CONTROL__Z_RD_POLICY_MASK 0x00030000L |
9778 | #define DB_RMI_BC_GL2_CACHE_CONTROL__S_RD_POLICY_MASK 0x000C0000L |
9779 | #define DB_RMI_BC_GL2_CACHE_CONTROL__HTILE_RD_POLICY_MASK 0x00300000L |
9780 | #define DB_RMI_BC_GL2_CACHE_CONTROL__VOL_MASK 0x80000000L |
9781 | //DB_EXCEPTION_CONTROL |
9782 | #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0 |
9783 | #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1 |
9784 | #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2 |
9785 | #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE__SHIFT 0x3 |
9786 | #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT 0x4 |
9787 | #define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT 0x8 |
9788 | #define DB_EXCEPTION_CONTROL__FORCE_VRS_RATE_FINE__SHIFT 0x10 |
9789 | #define DB_EXCEPTION_CONTROL__DTAG_WATERMARK__SHIFT 0x18 |
9790 | #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L |
9791 | #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L |
9792 | #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L |
9793 | #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE_MASK 0x00000008L |
9794 | #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD_MASK 0x00000010L |
9795 | #define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE_MASK 0x00000F00L |
9796 | #define DB_EXCEPTION_CONTROL__FORCE_VRS_RATE_FINE_MASK 0x00FF0000L |
9797 | #define DB_EXCEPTION_CONTROL__DTAG_WATERMARK_MASK 0x7F000000L |
9798 | //DB_DFSM_CONFIG |
9799 | #define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0 |
9800 | #define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1 |
9801 | #define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2 |
9802 | #define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3 |
9803 | #define DB_DFSM_CONFIG__SQUAD_WATERMARK__SHIFT 0x4 |
9804 | #define DB_DFSM_CONFIG__POPS_INCREMENT_CONTROL__SHIFT 0xe |
9805 | #define DB_DFSM_CONFIG__CAM_WATERMARK__SHIFT 0x10 |
9806 | #define DB_DFSM_CONFIG__FORCE_PUNCHOUT_5BIT_MODE__SHIFT 0x17 |
9807 | #define DB_DFSM_CONFIG__OUTPUT_WATCHDOG__SHIFT 0x18 |
9808 | #define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L |
9809 | #define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L |
9810 | #define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L |
9811 | #define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L |
9812 | #define DB_DFSM_CONFIG__SQUAD_WATERMARK_MASK 0x00003FF0L |
9813 | #define DB_DFSM_CONFIG__POPS_INCREMENT_CONTROL_MASK 0x0000C000L |
9814 | #define DB_DFSM_CONFIG__CAM_WATERMARK_MASK 0x007F0000L |
9815 | #define DB_DFSM_CONFIG__FORCE_PUNCHOUT_5BIT_MODE_MASK 0x00800000L |
9816 | #define DB_DFSM_CONFIG__OUTPUT_WATCHDOG_MASK 0xFF000000L |
9817 | //DB_DEBUG5 |
9818 | #define DB_DEBUG5__DISABLE_TILE_CACHE_PRELOAD__SHIFT 0x0 |
9819 | #define DB_DEBUG5__ENABLE_SECONDARY_MIPS_TAILS_COMPRESSION__SHIFT 0x1 |
9820 | #define DB_DEBUG5__DISABLE_CLEAR_VALUE_UPDATE_ON_TILE_CACHE_HIT__SHIFT 0x2 |
9821 | #define DB_DEBUG5__DISABLE_DB_CB_TILE_SEND_ON_CB_TILE_ONLY_MODES__SHIFT 0x3 |
9822 | #define DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK__SHIFT 0x4 |
9823 | #define DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS__SHIFT 0x5 |
9824 | #define DB_DEBUG5__ENABLE_DUAL_QUAD_MODE_IN_BC__SHIFT 0x6 |
9825 | #define DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT__SHIFT 0x7 |
9826 | #define DB_DEBUG5__DISABLE_DF_TILE_PANIC__SHIFT 0x8 |
9827 | #define DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE__SHIFT 0x9 |
9828 | #define DB_DEBUG5__DISABLE_RTINDEX_MASKING_IN_BC__SHIFT 0xa |
9829 | #define DB_DEBUG5__DISABLE_ZPASS_ADDR_CLAMP_IN_BC__SHIFT 0xb |
9830 | #define DB_DEBUG5__DISABLE_TILE_CACHE_PREFETCH__SHIFT 0xc |
9831 | #define DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX__SHIFT 0xd |
9832 | #define DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED__SHIFT 0xe |
9833 | #define DB_DEBUG5__SPARE_BIT_15__SHIFT 0xf |
9834 | #define DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ__SHIFT 0x10 |
9835 | #define DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE__SHIFT 0x11 |
9836 | #define DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT__SHIFT 0x12 |
9837 | #define DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT__SHIFT 0x13 |
9838 | #define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z__SHIFT 0x14 |
9839 | #define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL__SHIFT 0x15 |
9840 | #define DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK__SHIFT 0x16 |
9841 | #define DB_DEBUG5__DISABLE_EVENT_INSERTION_AFTER_ZPC_BEFORE_CONTEXT_DONE__SHIFT 0x17 |
9842 | #define DB_DEBUG5__DISABLE_HTILE_HARVESTING__SHIFT 0x18 |
9843 | #define DB_DEBUG5__SPARE_BITS__SHIFT 0x19 |
9844 | #define DB_DEBUG5__DISABLE_TILE_CACHE_PRELOAD_MASK 0x00000001L |
9845 | #define DB_DEBUG5__ENABLE_SECONDARY_MIPS_TAILS_COMPRESSION_MASK 0x00000002L |
9846 | #define DB_DEBUG5__DISABLE_CLEAR_VALUE_UPDATE_ON_TILE_CACHE_HIT_MASK 0x00000004L |
9847 | #define DB_DEBUG5__DISABLE_DB_CB_TILE_SEND_ON_CB_TILE_ONLY_MODES_MASK 0x00000008L |
9848 | #define DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK_MASK 0x00000010L |
9849 | #define DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS_MASK 0x00000020L |
9850 | #define DB_DEBUG5__ENABLE_DUAL_QUAD_MODE_IN_BC_MASK 0x00000040L |
9851 | #define DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT_MASK 0x00000080L |
9852 | #define DB_DEBUG5__DISABLE_DF_TILE_PANIC_MASK 0x00000100L |
9853 | #define DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE_MASK 0x00000200L |
9854 | #define DB_DEBUG5__DISABLE_RTINDEX_MASKING_IN_BC_MASK 0x00000400L |
9855 | #define DB_DEBUG5__DISABLE_ZPASS_ADDR_CLAMP_IN_BC_MASK 0x00000800L |
9856 | #define DB_DEBUG5__DISABLE_TILE_CACHE_PREFETCH_MASK 0x00001000L |
9857 | #define DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX_MASK 0x00002000L |
9858 | #define DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED_MASK 0x00004000L |
9859 | #define DB_DEBUG5__SPARE_BIT_15_MASK 0x00008000L |
9860 | #define DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ_MASK 0x00010000L |
9861 | #define DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE_MASK 0x00020000L |
9862 | #define DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT_MASK 0x00040000L |
9863 | #define DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT_MASK 0x00080000L |
9864 | #define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z_MASK 0x00100000L |
9865 | #define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL_MASK 0x00200000L |
9866 | #define DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK_MASK 0x00400000L |
9867 | #define DB_DEBUG5__DISABLE_EVENT_INSERTION_AFTER_ZPC_BEFORE_CONTEXT_DONE_MASK 0x00800000L |
9868 | #define DB_DEBUG5__DISABLE_HTILE_HARVESTING_MASK 0x01000000L |
9869 | #define DB_DEBUG5__SPARE_BITS_MASK 0xFE000000L |
9870 | //DB_DFSM_TILES_IN_FLIGHT |
9871 | #define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 |
9872 | #define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL |
9873 | //DB_DFSM_PRIMS_IN_FLIGHT |
9874 | #define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 |
9875 | #define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL |
9876 | //DB_DFSM_WATCHDOG |
9877 | #define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0 |
9878 | #define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL |
9879 | //DB_DFSM_FLUSH_ENABLE |
9880 | #define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0 |
9881 | #define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18 |
9882 | #define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c |
9883 | #define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000007FFL |
9884 | #define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L |
9885 | #define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L |
9886 | //DB_DFSM_FLUSH_AUX_EVENT |
9887 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0 |
9888 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8 |
9889 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10 |
9890 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18 |
9891 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL |
9892 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L |
9893 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L |
9894 | #define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L |
9895 | //DB_FGCG_SRAMS_CLK_CTRL |
9896 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0__SHIFT 0x0 |
9897 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1__SHIFT 0x1 |
9898 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2__SHIFT 0x2 |
9899 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3__SHIFT 0x3 |
9900 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4__SHIFT 0x4 |
9901 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5__SHIFT 0x5 |
9902 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6__SHIFT 0x6 |
9903 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7__SHIFT 0x7 |
9904 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8__SHIFT 0x8 |
9905 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9__SHIFT 0x9 |
9906 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT 0xa |
9907 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11__SHIFT 0xb |
9908 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12__SHIFT 0xc |
9909 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13__SHIFT 0xd |
9910 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14__SHIFT 0xe |
9911 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15__SHIFT 0xf |
9912 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16__SHIFT 0x10 |
9913 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17__SHIFT 0x11 |
9914 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18__SHIFT 0x12 |
9915 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19__SHIFT 0x13 |
9916 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20__SHIFT 0x14 |
9917 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21__SHIFT 0x15 |
9918 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22__SHIFT 0x16 |
9919 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23__SHIFT 0x17 |
9920 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24__SHIFT 0x18 |
9921 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25__SHIFT 0x19 |
9922 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26__SHIFT 0x1a |
9923 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0_MASK 0x00000001L |
9924 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1_MASK 0x00000002L |
9925 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2_MASK 0x00000004L |
9926 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3_MASK 0x00000008L |
9927 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4_MASK 0x00000010L |
9928 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5_MASK 0x00000020L |
9929 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6_MASK 0x00000040L |
9930 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7_MASK 0x00000080L |
9931 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8_MASK 0x00000100L |
9932 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9_MASK 0x00000200L |
9933 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10_MASK 0x00000400L |
9934 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11_MASK 0x00000800L |
9935 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12_MASK 0x00001000L |
9936 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13_MASK 0x00002000L |
9937 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14_MASK 0x00004000L |
9938 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15_MASK 0x00008000L |
9939 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16_MASK 0x00010000L |
9940 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17_MASK 0x00020000L |
9941 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18_MASK 0x00040000L |
9942 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19_MASK 0x00080000L |
9943 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20_MASK 0x00100000L |
9944 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21_MASK 0x00200000L |
9945 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22_MASK 0x00400000L |
9946 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23_MASK 0x00800000L |
9947 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24_MASK 0x01000000L |
9948 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25_MASK 0x02000000L |
9949 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26_MASK 0x04000000L |
9950 | //DB_FGCG_INTERFACES_CLK_CTRL |
9951 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE__SHIFT 0x0 |
9952 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_TILE_OVERRIDE__SHIFT 0x1 |
9953 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_LQUAD_OVERRIDE__SHIFT 0x2 |
9954 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE__SHIFT 0x3 |
9955 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE__SHIFT 0x4 |
9956 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE__SHIFT 0x5 |
9957 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE__SHIFT 0x6 |
9958 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE_MASK 0x00000001L |
9959 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_TILE_OVERRIDE_MASK 0x00000002L |
9960 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_LQUAD_OVERRIDE_MASK 0x00000004L |
9961 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE_MASK 0x00000008L |
9962 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE_MASK 0x00000010L |
9963 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE_MASK 0x00000020L |
9964 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE_MASK 0x00000040L |
9965 | //CC_RB_REDUNDANCY |
9966 | #define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 |
9967 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc |
9968 | #define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 |
9969 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 |
9970 | #define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L |
9971 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L |
9972 | #define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L |
9973 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L |
9974 | //CC_RB_BACKEND_DISABLE |
9975 | #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 |
9976 | #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L |
9977 | //GB_ADDR_CONFIG |
9978 | #define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
9979 | #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
9980 | #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
9981 | #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 |
9982 | #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
9983 | #define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a |
9984 | #define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
9985 | #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
9986 | #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
9987 | #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L |
9988 | #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
9989 | #define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L |
9990 | //GB_BACKEND_MAP |
9991 | #define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 |
9992 | #define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL |
9993 | //GB_GPU_ID |
9994 | #define GB_GPU_ID__GPU_ID__SHIFT 0x0 |
9995 | #define GB_GPU_ID__GPU_ID_MASK 0x0000000FL |
9996 | //CC_RB_DAISY_CHAIN |
9997 | #define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 |
9998 | #define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 |
9999 | #define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 |
10000 | #define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc |
10001 | #define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 |
10002 | #define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 |
10003 | #define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 |
10004 | #define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c |
10005 | #define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL |
10006 | #define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L |
10007 | #define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L |
10008 | #define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L |
10009 | #define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L |
10010 | #define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L |
10011 | #define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L |
10012 | #define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L |
10013 | //GB_ADDR_CONFIG_READ |
10014 | #define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 |
10015 | #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
10016 | #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
10017 | #define GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 |
10018 | #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 |
10019 | #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a |
10020 | #define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L |
10021 | #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
10022 | #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
10023 | #define GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L |
10024 | #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L |
10025 | #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L |
10026 | //CB_HW_CONTROL_4 |
10027 | #define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_CLS_LOG2__SHIFT 0x0 |
10028 | #define CB_HW_CONTROL_4__FMASK_CACHE_FETCH_NUM_CLS_LOG2__SHIFT 0x3 |
10029 | #define CB_HW_CONTROL_4__DISABLE_USE_OF_QUAD_SCOREBOARD__SHIFT 0x5 |
10030 | #define CB_HW_CONTROL_4__DISABLE_CMASK_CLOCK_GATING__SHIFT 0x6 |
10031 | #define CB_HW_CONTROL_4__DISABLE_FMASK_CLOCK_GATING__SHIFT 0x7 |
10032 | #define CB_HW_CONTROL_4__DISABLE_COLOR_CLOCK_GATING__SHIFT 0x8 |
10033 | #define CB_HW_CONTROL_4__DISABLE_QSB_AA_MODE__SHIFT 0x9 |
10034 | #define CB_HW_CONTROL_4__DISABLE_QSB_WAIT_FOR_SCORE__SHIFT 0xa |
10035 | #define CB_HW_CONTROL_4__DISABLE_QSB_FRAG_GT0__SHIFT 0xb |
10036 | #define CB_HW_CONTROL_4__REVERSE_KEYXFR_RD_PRIORITY__SHIFT 0xc |
10037 | #define CB_HW_CONTROL_4__DISABLE_KEYXFR_HIT_RETURNS__SHIFT 0xd |
10038 | #define CB_HW_CONTROL_4__DISABLE_BC_COLOR_CACHE_PREFETCH__SHIFT 0xe |
10039 | #define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST__SHIFT 0xf |
10040 | #define CB_HW_CONTROL_4__DISABLE_QSB_SPECULATIVE__SHIFT 0x10 |
10041 | #define CB_HW_CONTROL_4__QSB_WAIT_FOR_SCORE__SHIFT 0x11 |
10042 | #define CB_HW_CONTROL_4__DISABLE_TILE_FGCG__SHIFT 0x16 |
10043 | #define CB_HW_CONTROL_4__DISABLE_LQUAD_FGCG__SHIFT 0x17 |
10044 | #define CB_HW_CONTROL_4__FC_QSB_FIFO_DEPTH__SHIFT 0x18 |
10045 | #define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_CLS_LOG2_MASK 0x00000007L |
10046 | #define CB_HW_CONTROL_4__FMASK_CACHE_FETCH_NUM_CLS_LOG2_MASK 0x00000018L |
10047 | #define CB_HW_CONTROL_4__DISABLE_USE_OF_QUAD_SCOREBOARD_MASK 0x00000020L |
10048 | #define CB_HW_CONTROL_4__DISABLE_CMASK_CLOCK_GATING_MASK 0x00000040L |
10049 | #define CB_HW_CONTROL_4__DISABLE_FMASK_CLOCK_GATING_MASK 0x00000080L |
10050 | #define CB_HW_CONTROL_4__DISABLE_COLOR_CLOCK_GATING_MASK 0x00000100L |
10051 | #define CB_HW_CONTROL_4__DISABLE_QSB_AA_MODE_MASK 0x00000200L |
10052 | #define CB_HW_CONTROL_4__DISABLE_QSB_WAIT_FOR_SCORE_MASK 0x00000400L |
10053 | #define CB_HW_CONTROL_4__DISABLE_QSB_FRAG_GT0_MASK 0x00000800L |
10054 | #define CB_HW_CONTROL_4__REVERSE_KEYXFR_RD_PRIORITY_MASK 0x00001000L |
10055 | #define CB_HW_CONTROL_4__DISABLE_KEYXFR_HIT_RETURNS_MASK 0x00002000L |
10056 | #define CB_HW_CONTROL_4__DISABLE_BC_COLOR_CACHE_PREFETCH_MASK 0x00004000L |
10057 | #define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST_MASK 0x00008000L |
10058 | #define CB_HW_CONTROL_4__DISABLE_QSB_SPECULATIVE_MASK 0x00010000L |
10059 | #define CB_HW_CONTROL_4__QSB_WAIT_FOR_SCORE_MASK 0x003E0000L |
10060 | #define CB_HW_CONTROL_4__DISABLE_TILE_FGCG_MASK 0x00400000L |
10061 | #define CB_HW_CONTROL_4__DISABLE_LQUAD_FGCG_MASK 0x00800000L |
10062 | #define CB_HW_CONTROL_4__FC_QSB_FIFO_DEPTH_MASK 0xFF000000L |
10063 | //CB_HW_CONTROL_3 |
10064 | #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 |
10065 | #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 |
10066 | #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2 |
10067 | #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3 |
10068 | #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4 |
10069 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5 |
10070 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7 |
10071 | #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9 |
10072 | #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa |
10073 | #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb |
10074 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc |
10075 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd |
10076 | #define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe |
10077 | #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf |
10078 | #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10 |
10079 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11 |
10080 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12 |
10081 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13 |
10082 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14 |
10083 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15 |
10084 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16 |
10085 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17 |
10086 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18 |
10087 | #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19 |
10088 | #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a |
10089 | #define CB_HW_CONTROL_3__DISABLE_DCC_VRS_OPT__SHIFT 0x1c |
10090 | #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x1e |
10091 | #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_BC__SHIFT 0x1f |
10092 | #define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L |
10093 | #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L |
10094 | #define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L |
10095 | #define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L |
10096 | #define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L |
10097 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L |
10098 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L |
10099 | #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L |
10100 | #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L |
10101 | #define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L |
10102 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L |
10103 | #define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L |
10104 | #define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L |
10105 | #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L |
10106 | #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L |
10107 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L |
10108 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L |
10109 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L |
10110 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L |
10111 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L |
10112 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L |
10113 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L |
10114 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L |
10115 | #define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L |
10116 | #define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L |
10117 | #define CB_HW_CONTROL_3__DISABLE_DCC_VRS_OPT_MASK 0x10000000L |
10118 | #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_MASK 0x40000000L |
10119 | #define CB_HW_CONTROL_3__DISABLE_FMASK_NOFETCH_OPT_BC_MASK 0x80000000L |
10120 | //CB_HW_CONTROL |
10121 | #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x0 |
10122 | #define CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION__SHIFT 0x1 |
10123 | #define CB_HW_CONTROL__DISABLE_FILLRATE_OPT_FIX_WITH_CFC__SHIFT 0x3 |
10124 | #define CB_HW_CONTROL__DISABLE_POST_DCC_WITH_CFC_FIX__SHIFT 0x4 |
10125 | #define CB_HW_CONTROL__DISABLE_COMPRESS_1FRAG_WHEN_VRS_RATE_HINT_EN__SHIFT 0x5 |
10126 | #define CB_HW_CONTROL__RMI_CREDITS__SHIFT 0x6 |
10127 | #define CB_HW_CONTROL__CHICKEN_BITS__SHIFT 0xc |
10128 | #define CB_HW_CONTROL__DISABLE_FMASK_MULTI_MGCG_DOMAINS__SHIFT 0xf |
10129 | #define CB_HW_CONTROL__DISABLE_CMASK_CACHE_BYTEMASKING__SHIFT 0x10 |
10130 | #define CB_HW_CONTROL__DISABLE_DCC_CACHE_BYTEMASKING__SHIFT 0x11 |
10131 | #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 |
10132 | #define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 |
10133 | #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 |
10134 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 |
10135 | #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 |
10136 | #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 |
10137 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 |
10138 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 |
10139 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a |
10140 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b |
10141 | #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c |
10142 | #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d |
10143 | #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e |
10144 | #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f |
10145 | #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00000001L |
10146 | #define CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION_MASK 0x00000002L |
10147 | #define CB_HW_CONTROL__DISABLE_FILLRATE_OPT_FIX_WITH_CFC_MASK 0x00000008L |
10148 | #define CB_HW_CONTROL__DISABLE_POST_DCC_WITH_CFC_FIX_MASK 0x00000010L |
10149 | #define CB_HW_CONTROL__DISABLE_COMPRESS_1FRAG_WHEN_VRS_RATE_HINT_EN_MASK 0x00000020L |
10150 | #define CB_HW_CONTROL__RMI_CREDITS_MASK 0x00000FC0L |
10151 | #define CB_HW_CONTROL__CHICKEN_BITS_MASK 0x00007000L |
10152 | #define CB_HW_CONTROL__DISABLE_FMASK_MULTI_MGCG_DOMAINS_MASK 0x00008000L |
10153 | #define CB_HW_CONTROL__DISABLE_CMASK_CACHE_BYTEMASKING_MASK 0x00010000L |
10154 | #define CB_HW_CONTROL__DISABLE_DCC_CACHE_BYTEMASKING_MASK 0x00020000L |
10155 | #define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L |
10156 | #define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L |
10157 | #define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L |
10158 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L |
10159 | #define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L |
10160 | #define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L |
10161 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L |
10162 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L |
10163 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L |
10164 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L |
10165 | #define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L |
10166 | #define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L |
10167 | #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L |
10168 | #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L |
10169 | //CB_HW_CONTROL_1 |
10170 | #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 |
10171 | #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 |
10172 | #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xc |
10173 | #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x12 |
10174 | #define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL |
10175 | #define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x00000FE0L |
10176 | #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0003F000L |
10177 | #define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x07FC0000L |
10178 | //CB_HW_CONTROL_2 |
10179 | #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 |
10180 | #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 |
10181 | #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf |
10182 | #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18 |
10183 | #define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1e |
10184 | #define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL |
10185 | #define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L |
10186 | #define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L |
10187 | #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x3F000000L |
10188 | #define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xC0000000L |
10189 | //CB_DCC_CONFIG |
10190 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0 |
10191 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5 |
10192 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6 |
10193 | #define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT 0x7 |
10194 | #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8 |
10195 | #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 |
10196 | #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x19 |
10197 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL |
10198 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L |
10199 | #define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L |
10200 | #define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK 0x00000080L |
10201 | #define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L |
10202 | #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x01FF0000L |
10203 | #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xFE000000L |
10204 | //CB_HW_MEM_ARBITER_RD |
10205 | #define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0 |
10206 | #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2 |
10207 | #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6 |
10208 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa |
10209 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc |
10210 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe |
10211 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10 |
10212 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12 |
10213 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14 |
10214 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16 |
10215 | #define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17 |
10216 | #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a |
10217 | #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d |
10218 | #define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L |
10219 | #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL |
10220 | #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L |
10221 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L |
10222 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L |
10223 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L |
10224 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L |
10225 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L |
10226 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L |
10227 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L |
10228 | #define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L |
10229 | #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L |
10230 | #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L |
10231 | //CB_HW_MEM_ARBITER_WR |
10232 | #define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0 |
10233 | #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2 |
10234 | #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6 |
10235 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa |
10236 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc |
10237 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe |
10238 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10 |
10239 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12 |
10240 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14 |
10241 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16 |
10242 | #define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17 |
10243 | #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a |
10244 | #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d |
10245 | #define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L |
10246 | #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL |
10247 | #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L |
10248 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L |
10249 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L |
10250 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L |
10251 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L |
10252 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L |
10253 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L |
10254 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L |
10255 | #define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L |
10256 | #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L |
10257 | #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L |
10258 | //CB_RMI_BC_GL2_CACHE_CONTROL |
10259 | #define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_WR_POLICY__SHIFT 0x0 |
10260 | #define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_WR_POLICY__SHIFT 0x2 |
10261 | #define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT 0x4 |
10262 | #define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT 0x6 |
10263 | #define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_RD_POLICY__SHIFT 0x10 |
10264 | #define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_RD_POLICY__SHIFT 0x12 |
10265 | #define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT 0x14 |
10266 | #define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT 0x16 |
10267 | #define CB_RMI_BC_GL2_CACHE_CONTROL__VOLAT__SHIFT 0x1f |
10268 | #define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_WR_POLICY_MASK 0x00000003L |
10269 | #define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_WR_POLICY_MASK 0x0000000CL |
10270 | #define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK 0x00000030L |
10271 | #define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK 0x000000C0L |
10272 | #define CB_RMI_BC_GL2_CACHE_CONTROL__CMASK_RD_POLICY_MASK 0x00030000L |
10273 | #define CB_RMI_BC_GL2_CACHE_CONTROL__FMASK_RD_POLICY_MASK 0x000C0000L |
10274 | #define CB_RMI_BC_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK 0x00300000L |
10275 | #define CB_RMI_BC_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK 0x00C00000L |
10276 | #define CB_RMI_BC_GL2_CACHE_CONTROL__VOLAT_MASK 0x80000000L |
10277 | //CB_STUTTER_CONTROL_CMASK_RDLAT |
10278 | #define CB_STUTTER_CONTROL_CMASK_RDLAT__THRESHOLD__SHIFT 0x0 |
10279 | #define CB_STUTTER_CONTROL_CMASK_RDLAT__TIMEOUT__SHIFT 0x8 |
10280 | #define CB_STUTTER_CONTROL_CMASK_RDLAT__THRESHOLD_MASK 0x000000FFL |
10281 | #define CB_STUTTER_CONTROL_CMASK_RDLAT__TIMEOUT_MASK 0x0000FF00L |
10282 | //CB_STUTTER_CONTROL_FMASK_RDLAT |
10283 | #define CB_STUTTER_CONTROL_FMASK_RDLAT__THRESHOLD__SHIFT 0x0 |
10284 | #define CB_STUTTER_CONTROL_FMASK_RDLAT__TIMEOUT__SHIFT 0x8 |
10285 | #define CB_STUTTER_CONTROL_FMASK_RDLAT__THRESHOLD_MASK 0x000000FFL |
10286 | #define CB_STUTTER_CONTROL_FMASK_RDLAT__TIMEOUT_MASK 0x0000FF00L |
10287 | //CB_STUTTER_CONTROL_COLOR_RDLAT |
10288 | #define CB_STUTTER_CONTROL_COLOR_RDLAT__THRESHOLD__SHIFT 0x0 |
10289 | #define CB_STUTTER_CONTROL_COLOR_RDLAT__TIMEOUT__SHIFT 0x8 |
10290 | #define CB_STUTTER_CONTROL_COLOR_RDLAT__THRESHOLD_MASK 0x000000FFL |
10291 | #define CB_STUTTER_CONTROL_COLOR_RDLAT__TIMEOUT_MASK 0x0000FF00L |
10292 | //CB_CACHE_EVICT_POINTS |
10293 | #define CB_CACHE_EVICT_POINTS__CM_CACHE_EVICT_POINT__SHIFT 0x0 |
10294 | #define CB_CACHE_EVICT_POINTS__FC_CACHE_EVICT_POINT__SHIFT 0x8 |
10295 | #define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT__SHIFT 0x10 |
10296 | #define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT__SHIFT 0x18 |
10297 | #define CB_CACHE_EVICT_POINTS__CM_CACHE_EVICT_POINT_MASK 0x000000FFL |
10298 | #define CB_CACHE_EVICT_POINTS__FC_CACHE_EVICT_POINT_MASK 0x0000FF00L |
10299 | #define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT_MASK 0x00FF0000L |
10300 | #define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT_MASK 0xFF000000L |
10301 | //GC_USER_RB_REDUNDANCY |
10302 | #define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 |
10303 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc |
10304 | #define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 |
10305 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 |
10306 | #define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L |
10307 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L |
10308 | #define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L |
10309 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L |
10310 | //GC_USER_RB_BACKEND_DISABLE |
10311 | #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 |
10312 | #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L |
10313 | |
10314 | |
10315 | // addressBlock: gc_gceadec2 |
10316 | //GCEA_MISC |
10317 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 |
10318 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 |
10319 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 |
10320 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 |
10321 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 |
10322 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 |
10323 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 |
10324 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 |
10325 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 |
10326 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 |
10327 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa |
10328 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb |
10329 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc |
10330 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd |
10331 | #define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe |
10332 | #define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf |
10333 | #define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 |
10334 | #define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 |
10335 | #define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 |
10336 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a |
10337 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b |
10338 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c |
10339 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d |
10340 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e |
10341 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f |
10342 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L |
10343 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L |
10344 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L |
10345 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L |
10346 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L |
10347 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L |
10348 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L |
10349 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L |
10350 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L |
10351 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L |
10352 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L |
10353 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L |
10354 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L |
10355 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L |
10356 | #define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L |
10357 | #define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L |
10358 | #define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L |
10359 | #define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L |
10360 | #define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L |
10361 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L |
10362 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L |
10363 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L |
10364 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L |
10365 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L |
10366 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L |
10367 | //GCEA_LATENCY_SAMPLING |
10368 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 |
10369 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 |
10370 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 |
10371 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 |
10372 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 |
10373 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 |
10374 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 |
10375 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 |
10376 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 |
10377 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 |
10378 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa |
10379 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb |
10380 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc |
10381 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd |
10382 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe |
10383 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 |
10384 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L |
10385 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L |
10386 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L |
10387 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L |
10388 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L |
10389 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L |
10390 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L |
10391 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L |
10392 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L |
10393 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L |
10394 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L |
10395 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L |
10396 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L |
10397 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L |
10398 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L |
10399 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L |
10400 | //GCEA_DSM_CNTL |
10401 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
10402 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
10403 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
10404 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
10405 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
10406 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
10407 | #define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
10408 | #define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
10409 | #define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
10410 | #define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
10411 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
10412 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
10413 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
10414 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
10415 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
10416 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
10417 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
10418 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
10419 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
10420 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
10421 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
10422 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
10423 | #define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
10424 | #define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
10425 | #define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
10426 | #define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
10427 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
10428 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
10429 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
10430 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
10431 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
10432 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
10433 | //GCEA_DSM_CNTLA |
10434 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
10435 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
10436 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
10437 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
10438 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
10439 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
10440 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
10441 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
10442 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
10443 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
10444 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
10445 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
10446 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
10447 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
10448 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
10449 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
10450 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
10451 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
10452 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
10453 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
10454 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
10455 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
10456 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
10457 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
10458 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
10459 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
10460 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
10461 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
10462 | //GCEA_DSM_CNTLB |
10463 | //GCEA_DSM_CNTL2 |
10464 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
10465 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
10466 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
10467 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
10468 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
10469 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
10470 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
10471 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
10472 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
10473 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
10474 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
10475 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
10476 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
10477 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
10478 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
10479 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 |
10480 | #define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
10481 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
10482 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
10483 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
10484 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
10485 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
10486 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
10487 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
10488 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
10489 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
10490 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
10491 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
10492 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
10493 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
10494 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
10495 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
10496 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L |
10497 | #define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
10498 | //GCEA_DSM_CNTL2A |
10499 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
10500 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
10501 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
10502 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
10503 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
10504 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
10505 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
10506 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
10507 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
10508 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
10509 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
10510 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
10511 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
10512 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
10513 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
10514 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
10515 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
10516 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
10517 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
10518 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
10519 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
10520 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
10521 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
10522 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
10523 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
10524 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
10525 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
10526 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
10527 | //GCEA_DSM_CNTL2B |
10528 | //GCEA_GL2C_XBR_CREDITS |
10529 | #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0 |
10530 | #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6 |
10531 | #define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8 |
10532 | #define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe |
10533 | #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10 |
10534 | #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16 |
10535 | #define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18 |
10536 | #define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e |
10537 | #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL |
10538 | #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L |
10539 | #define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L |
10540 | #define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L |
10541 | #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L |
10542 | #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L |
10543 | #define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L |
10544 | #define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L |
10545 | //GCEA_GL2C_XBR_MAXBURST |
10546 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD__SHIFT 0x0 |
10547 | #define GCEA_GL2C_XBR_MAXBURST__IO_RD__SHIFT 0x4 |
10548 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR__SHIFT 0x8 |
10549 | #define GCEA_GL2C_XBR_MAXBURST__IO_WR__SHIFT 0xc |
10550 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER__SHIFT 0x10 |
10551 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY__SHIFT 0x13 |
10552 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER__SHIFT 0x14 |
10553 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY__SHIFT 0x17 |
10554 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL |
10555 | #define GCEA_GL2C_XBR_MAXBURST__IO_RD_MASK 0x000000F0L |
10556 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L |
10557 | #define GCEA_GL2C_XBR_MAXBURST__IO_WR_MASK 0x0000F000L |
10558 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER_MASK 0x00070000L |
10559 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY_MASK 0x00080000L |
10560 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER_MASK 0x00700000L |
10561 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY_MASK 0x00800000L |
10562 | //GCEA_PROBE_CNTL |
10563 | #define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0 |
10564 | #define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5 |
10565 | #define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL |
10566 | #define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L |
10567 | //GCEA_PROBE_MAP |
10568 | #define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C__SHIFT 0x0 |
10569 | #define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C__SHIFT 0x1 |
10570 | #define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C__SHIFT 0x2 |
10571 | #define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C__SHIFT 0x3 |
10572 | #define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C__SHIFT 0x4 |
10573 | #define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C__SHIFT 0x5 |
10574 | #define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C__SHIFT 0x6 |
10575 | #define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C__SHIFT 0x7 |
10576 | #define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C__SHIFT 0x8 |
10577 | #define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C__SHIFT 0x9 |
10578 | #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C__SHIFT 0xa |
10579 | #define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C__SHIFT 0xb |
10580 | #define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C__SHIFT 0xc |
10581 | #define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C__SHIFT 0xd |
10582 | #define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C__SHIFT 0xe |
10583 | #define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C__SHIFT 0xf |
10584 | #define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10 |
10585 | #define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C_MASK 0x00000001L |
10586 | #define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C_MASK 0x00000002L |
10587 | #define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C_MASK 0x00000004L |
10588 | #define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C_MASK 0x00000008L |
10589 | #define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C_MASK 0x00000010L |
10590 | #define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C_MASK 0x00000020L |
10591 | #define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C_MASK 0x00000040L |
10592 | #define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C_MASK 0x00000080L |
10593 | #define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C_MASK 0x00000100L |
10594 | #define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C_MASK 0x00000200L |
10595 | #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C_MASK 0x00000400L |
10596 | #define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C_MASK 0x00000800L |
10597 | #define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C_MASK 0x00001000L |
10598 | #define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C_MASK 0x00002000L |
10599 | #define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C_MASK 0x00004000L |
10600 | #define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C_MASK 0x00008000L |
10601 | #define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L |
10602 | //GCEA_ERR_STATUS |
10603 | #define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 |
10604 | #define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 |
10605 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 |
10606 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa |
10607 | #define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb |
10608 | #define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc |
10609 | #define GCEA_ERR_STATUS__FUE_FLAG__SHIFT 0xd |
10610 | #define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL |
10611 | #define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L |
10612 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L |
10613 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L |
10614 | #define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L |
10615 | #define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L |
10616 | #define GCEA_ERR_STATUS__FUE_FLAG_MASK 0x00002000L |
10617 | //GCEA_MISC2 |
10618 | #define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 |
10619 | #define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 |
10620 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 |
10621 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 |
10622 | #define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc |
10623 | #define GCEA_MISC2__BLOCK_REQUESTS__SHIFT 0xd |
10624 | #define GCEA_MISC2__REQUESTS_BLOCKED__SHIFT 0xe |
10625 | #define GCEA_MISC2__FGCLKEN_OVERRIDE__SHIFT 0xf |
10626 | #define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L |
10627 | #define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L |
10628 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL |
10629 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L |
10630 | #define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L |
10631 | #define GCEA_MISC2__BLOCK_REQUESTS_MASK 0x00002000L |
10632 | #define GCEA_MISC2__REQUESTS_BLOCKED_MASK 0x00004000L |
10633 | #define GCEA_MISC2__FGCLKEN_OVERRIDE_MASK 0x00008000L |
10634 | |
10635 | |
10636 | // addressBlock: gc_spipdec2 |
10637 | //SPI_PQEV_CTRL |
10638 | #define SPI_PQEV_CTRL__SCAN_PERIOD__SHIFT 0x0 |
10639 | #define SPI_PQEV_CTRL__QUEUE_DURATION__SHIFT 0xa |
10640 | #define SPI_PQEV_CTRL__COMPUTE_PIPE_EN__SHIFT 0x10 |
10641 | #define SPI_PQEV_CTRL__SCAN_PERIOD_MASK 0x000003FFL |
10642 | #define SPI_PQEV_CTRL__QUEUE_DURATION_MASK 0x0000FC00L |
10643 | #define SPI_PQEV_CTRL__COMPUTE_PIPE_EN_MASK 0x00FF0000L |
10644 | //SPI_EXP_THROTTLE_CTRL |
10645 | #define SPI_EXP_THROTTLE_CTRL__ENABLE__SHIFT 0x0 |
10646 | #define SPI_EXP_THROTTLE_CTRL__PERIOD__SHIFT 0x1 |
10647 | #define SPI_EXP_THROTTLE_CTRL__UPSTEP__SHIFT 0x5 |
10648 | #define SPI_EXP_THROTTLE_CTRL__DOWNSTEP__SHIFT 0x9 |
10649 | #define SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT__SHIFT 0xd |
10650 | #define SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT__SHIFT 0x10 |
10651 | #define SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD__SHIFT 0x13 |
10652 | #define SPI_EXP_THROTTLE_CTRL__SKEW_COUNT__SHIFT 0x1a |
10653 | #define SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET__SHIFT 0x1d |
10654 | #define SPI_EXP_THROTTLE_CTRL__ENABLE_MASK 0x00000001L |
10655 | #define SPI_EXP_THROTTLE_CTRL__PERIOD_MASK 0x0000001EL |
10656 | #define SPI_EXP_THROTTLE_CTRL__UPSTEP_MASK 0x000001E0L |
10657 | #define SPI_EXP_THROTTLE_CTRL__DOWNSTEP_MASK 0x00001E00L |
10658 | #define SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT_MASK 0x0000E000L |
10659 | #define SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT_MASK 0x00070000L |
10660 | #define SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD_MASK 0x03F80000L |
10661 | #define SPI_EXP_THROTTLE_CTRL__SKEW_COUNT_MASK 0x1C000000L |
10662 | #define SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET_MASK 0x20000000L |
10663 | |
10664 | |
10665 | // addressBlock: gc_gceadec3 |
10666 | //GCEA_RRET_MEM_RESERVE |
10667 | #define GCEA_RRET_MEM_RESERVE__VC0__SHIFT 0x0 |
10668 | #define GCEA_RRET_MEM_RESERVE__VC1__SHIFT 0x4 |
10669 | #define GCEA_RRET_MEM_RESERVE__VC2__SHIFT 0x8 |
10670 | #define GCEA_RRET_MEM_RESERVE__VC3__SHIFT 0xc |
10671 | #define GCEA_RRET_MEM_RESERVE__VC4__SHIFT 0x10 |
10672 | #define GCEA_RRET_MEM_RESERVE__VC5__SHIFT 0x14 |
10673 | #define GCEA_RRET_MEM_RESERVE__VC6__SHIFT 0x18 |
10674 | #define GCEA_RRET_MEM_RESERVE__VC7__SHIFT 0x1c |
10675 | #define GCEA_RRET_MEM_RESERVE__VC0_MASK 0x0000000FL |
10676 | #define GCEA_RRET_MEM_RESERVE__VC1_MASK 0x000000F0L |
10677 | #define GCEA_RRET_MEM_RESERVE__VC2_MASK 0x00000F00L |
10678 | #define GCEA_RRET_MEM_RESERVE__VC3_MASK 0x0000F000L |
10679 | #define GCEA_RRET_MEM_RESERVE__VC4_MASK 0x000F0000L |
10680 | #define GCEA_RRET_MEM_RESERVE__VC5_MASK 0x00F00000L |
10681 | #define GCEA_RRET_MEM_RESERVE__VC6_MASK 0x0F000000L |
10682 | #define GCEA_RRET_MEM_RESERVE__VC7_MASK 0xF0000000L |
10683 | |
10684 | |
10685 | // addressBlock: gc_rmi_rmidec |
10686 | //RMI_GENERAL_CNTL |
10687 | #define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0 |
10688 | #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1 |
10689 | #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11 |
10690 | #define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13 |
10691 | #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15 |
10692 | #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19 |
10693 | #define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a |
10694 | #define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b |
10695 | #define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c |
10696 | #define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d |
10697 | #define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e |
10698 | #define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L |
10699 | #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL |
10700 | #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L |
10701 | #define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L |
10702 | #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L |
10703 | #define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L |
10704 | #define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L |
10705 | #define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L |
10706 | #define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L |
10707 | #define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L |
10708 | #define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L |
10709 | //RMI_GENERAL_CNTL1 |
10710 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0 |
10711 | #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4 |
10712 | #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6 |
10713 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8 |
10714 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9 |
10715 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xb |
10716 | #define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xc |
10717 | #define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xd |
10718 | #define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE__SHIFT 0xe |
10719 | #define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE__SHIFT 0xf |
10720 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL |
10721 | #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L |
10722 | #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L |
10723 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L |
10724 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000600L |
10725 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000800L |
10726 | #define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00001000L |
10727 | #define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00002000L |
10728 | #define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE_MASK 0x00004000L |
10729 | #define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE_MASK 0x00008000L |
10730 | //RMI_GENERAL_STATUS |
10731 | #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0 |
10732 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1 |
10733 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2 |
10734 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3 |
10735 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4 |
10736 | #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5 |
10737 | #define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6 |
10738 | #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7 |
10739 | #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8 |
10740 | #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9 |
10741 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa |
10742 | #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb |
10743 | #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc |
10744 | #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd |
10745 | #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe |
10746 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf |
10747 | #define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12 |
10748 | #define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13 |
10749 | #define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14 |
10750 | #define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15 |
10751 | #define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d |
10752 | #define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e |
10753 | #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f |
10754 | #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L |
10755 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L |
10756 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L |
10757 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L |
10758 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L |
10759 | #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L |
10760 | #define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L |
10761 | #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L |
10762 | #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L |
10763 | #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L |
10764 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L |
10765 | #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L |
10766 | #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L |
10767 | #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L |
10768 | #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L |
10769 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L |
10770 | #define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L |
10771 | #define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L |
10772 | #define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L |
10773 | #define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L |
10774 | #define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L |
10775 | #define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L |
10776 | #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L |
10777 | //RMI_SUBBLOCK_STATUS0 |
10778 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0 |
10779 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7 |
10780 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8 |
10781 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9 |
10782 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10 |
10783 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11 |
10784 | #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12 |
10785 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL |
10786 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L |
10787 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L |
10788 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L |
10789 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L |
10790 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L |
10791 | #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L |
10792 | //RMI_SUBBLOCK_STATUS1 |
10793 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0 |
10794 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa |
10795 | #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14 |
10796 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL |
10797 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L |
10798 | #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L |
10799 | //RMI_SUBBLOCK_STATUS2 |
10800 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0 |
10801 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9 |
10802 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL |
10803 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L |
10804 | //RMI_SUBBLOCK_STATUS3 |
10805 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0 |
10806 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa |
10807 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL |
10808 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L |
10809 | //RMI_XBAR_CONFIG |
10810 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0 |
10811 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2 |
10812 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6 |
10813 | #define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7 |
10814 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8 |
10815 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc |
10816 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd |
10817 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L |
10818 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL |
10819 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L |
10820 | #define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L |
10821 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L |
10822 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L |
10823 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L |
10824 | //RMI_PROBE_POP_LOGIC_CNTL |
10825 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0 |
10826 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7 |
10827 | #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8 |
10828 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa |
10829 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11 |
10830 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL |
10831 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L |
10832 | #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L |
10833 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L |
10834 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L |
10835 | //RMI_UTC_XNACK_N_MISC_CNTL |
10836 | #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0 |
10837 | #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8 |
10838 | #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc |
10839 | #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd |
10840 | #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL |
10841 | #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L |
10842 | #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L |
10843 | #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L |
10844 | //RMI_DEMUX_CNTL |
10845 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0 |
10846 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1 |
10847 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN__SHIFT 0x2 |
10848 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4 |
10849 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6 |
10850 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe |
10851 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10 |
10852 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11 |
10853 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN__SHIFT 0x12 |
10854 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14 |
10855 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16 |
10856 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e |
10857 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L |
10858 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L |
10859 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN_MASK 0x00000004L |
10860 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L |
10861 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L |
10862 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L |
10863 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L |
10864 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L |
10865 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN_MASK 0x00040000L |
10866 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L |
10867 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L |
10868 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L |
10869 | //RMI_UTCL1_CNTL1 |
10870 | #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
10871 | #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
10872 | #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
10873 | #define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 |
10874 | #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
10875 | #define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 |
10876 | #define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 |
10877 | #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
10878 | #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
10879 | #define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 |
10880 | #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 |
10881 | #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 |
10882 | #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
10883 | #define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a |
10884 | #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
10885 | #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
10886 | #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
10887 | #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
10888 | #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
10889 | #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
10890 | #define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L |
10891 | #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
10892 | #define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L |
10893 | #define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L |
10894 | #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
10895 | #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
10896 | #define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L |
10897 | #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L |
10898 | #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L |
10899 | #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
10900 | #define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L |
10901 | #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
10902 | #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
10903 | #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
10904 | //RMI_UTCL1_CNTL2 |
10905 | #define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0 |
10906 | #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
10907 | #define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa |
10908 | #define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb |
10909 | #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
10910 | #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
10911 | #define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe |
10912 | #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
10913 | #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10 |
10914 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
10915 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13 |
10916 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
10917 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15 |
10918 | #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19 |
10919 | #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
10920 | #define RMI_UTCL1_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b |
10921 | #define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c |
10922 | #define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT__SHIFT 0x1d |
10923 | #define RMI_UTCL1_CNTL2__FGCG_DISABLE__SHIFT 0x1e |
10924 | #define RMI_UTCL1_CNTL2__RESERVED__SHIFT 0x1f |
10925 | #define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL |
10926 | #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
10927 | #define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L |
10928 | #define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L |
10929 | #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
10930 | #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
10931 | #define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
10932 | #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
10933 | #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L |
10934 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
10935 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L |
10936 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
10937 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L |
10938 | #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L |
10939 | #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
10940 | #define RMI_UTCL1_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L |
10941 | #define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L |
10942 | #define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT_MASK 0x20000000L |
10943 | #define RMI_UTCL1_CNTL2__FGCG_DISABLE_MASK 0x40000000L |
10944 | #define RMI_UTCL1_CNTL2__RESERVED_MASK 0x80000000L |
10945 | //RMI_UTC_UNIT_CONFIG |
10946 | //RMI_TCIW_FORMATTER0_CNTL |
10947 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0 |
10948 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1 |
10949 | #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 |
10950 | #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13 |
10951 | #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b |
10952 | #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c |
10953 | #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d |
10954 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e |
10955 | #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f |
10956 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L |
10957 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL |
10958 | #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L |
10959 | #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L |
10960 | #define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L |
10961 | #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L |
10962 | #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L |
10963 | #define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L |
10964 | #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L |
10965 | //RMI_TCIW_FORMATTER1_CNTL |
10966 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0 |
10967 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1 |
10968 | #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 |
10969 | #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13 |
10970 | #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b |
10971 | #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c |
10972 | #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d |
10973 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e |
10974 | #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f |
10975 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L |
10976 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL |
10977 | #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L |
10978 | #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L |
10979 | #define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L |
10980 | #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L |
10981 | #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L |
10982 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L |
10983 | #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L |
10984 | //RMI_SCOREBOARD_CNTL |
10985 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0 |
10986 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1 |
10987 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2 |
10988 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3 |
10989 | #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4 |
10990 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5 |
10991 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6 |
10992 | #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7 |
10993 | #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8 |
10994 | #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9 |
10995 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L |
10996 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L |
10997 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L |
10998 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L |
10999 | #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L |
11000 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L |
11001 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L |
11002 | #define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L |
11003 | #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L |
11004 | #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L |
11005 | //RMI_SCOREBOARD_STATUS0 |
11006 | #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0 |
11007 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1 |
11008 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2 |
11009 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12 |
11010 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13 |
11011 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14 |
11012 | #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15 |
11013 | #define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT__SHIFT 0x16 |
11014 | #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L |
11015 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L |
11016 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL |
11017 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L |
11018 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L |
11019 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L |
11020 | #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L |
11021 | #define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT_MASK 0x07C00000L |
11022 | //RMI_SCOREBOARD_STATUS1 |
11023 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0 |
11024 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc |
11025 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd |
11026 | #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe |
11027 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf |
11028 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b |
11029 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c |
11030 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d |
11031 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e |
11032 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL |
11033 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L |
11034 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L |
11035 | #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L |
11036 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L |
11037 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L |
11038 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L |
11039 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L |
11040 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L |
11041 | //RMI_SCOREBOARD_STATUS2 |
11042 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0 |
11043 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc |
11044 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd |
11045 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19 |
11046 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a |
11047 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b |
11048 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c |
11049 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d |
11050 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e |
11051 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f |
11052 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL |
11053 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L |
11054 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L |
11055 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L |
11056 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L |
11057 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L |
11058 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L |
11059 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L |
11060 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L |
11061 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L |
11062 | //RMI_XBAR_ARBITER_CONFIG |
11063 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0 |
11064 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2 |
11065 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3 |
11066 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4 |
11067 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN__SHIFT 0x5 |
11068 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6 |
11069 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8 |
11070 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10 |
11071 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12 |
11072 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13 |
11073 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14 |
11074 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN__SHIFT 0x15 |
11075 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16 |
11076 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18 |
11077 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L |
11078 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L |
11079 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L |
11080 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L |
11081 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN_MASK 0x00000020L |
11082 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L |
11083 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L |
11084 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L |
11085 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L |
11086 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L |
11087 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L |
11088 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN_MASK 0x00200000L |
11089 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L |
11090 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L |
11091 | //RMI_XBAR_ARBITER_CONFIG_1 |
11092 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0 |
11093 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8 |
11094 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL |
11095 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L |
11096 | //RMI_CLOCK_CNTRL |
11097 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0 |
11098 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5 |
11099 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa |
11100 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf |
11101 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL |
11102 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L |
11103 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L |
11104 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L |
11105 | //RMI_UTCL1_STATUS |
11106 | #define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
11107 | #define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
11108 | #define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
11109 | #define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
11110 | #define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
11111 | #define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
11112 | //RMI_RB_GLX_CID_MAP |
11113 | #define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP__SHIFT 0x0 |
11114 | #define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP__SHIFT 0x4 |
11115 | #define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP__SHIFT 0x8 |
11116 | #define RMI_RB_GLX_CID_MAP__CB_DCC_MAP__SHIFT 0xc |
11117 | #define RMI_RB_GLX_CID_MAP__DB_Z_MAP__SHIFT 0x10 |
11118 | #define RMI_RB_GLX_CID_MAP__DB_S_MAP__SHIFT 0x14 |
11119 | #define RMI_RB_GLX_CID_MAP__DB_TILE_MAP__SHIFT 0x18 |
11120 | #define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP__SHIFT 0x1c |
11121 | #define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP_MASK 0x0000000FL |
11122 | #define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP_MASK 0x000000F0L |
11123 | #define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP_MASK 0x00000F00L |
11124 | #define RMI_RB_GLX_CID_MAP__CB_DCC_MAP_MASK 0x0000F000L |
11125 | #define RMI_RB_GLX_CID_MAP__DB_Z_MAP_MASK 0x000F0000L |
11126 | #define RMI_RB_GLX_CID_MAP__DB_S_MAP_MASK 0x00F00000L |
11127 | #define RMI_RB_GLX_CID_MAP__DB_TILE_MAP_MASK 0x0F000000L |
11128 | #define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP_MASK 0xF0000000L |
11129 | //RMI_SPARE |
11130 | #define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0 |
11131 | #define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE__SHIFT 0x1 |
11132 | #define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE__SHIFT 0x2 |
11133 | #define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE__SHIFT 0x3 |
11134 | #define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS__SHIFT 0x4 |
11135 | #define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS__SHIFT 0x5 |
11136 | #define RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE__SHIFT 0x6 |
11137 | #define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7 |
11138 | #define RMI_SPARE__NOFILL_RMI_CID_CC__SHIFT 0x8 |
11139 | #define RMI_SPARE__NOFILL_RMI_CID_FC__SHIFT 0x9 |
11140 | #define RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT 0xa |
11141 | #define RMI_SPARE__NOFILL_RMI_CID_DC__SHIFT 0xb |
11142 | #define RMI_SPARE__NOFILL_RMI_CID_Z__SHIFT 0xc |
11143 | #define RMI_SPARE__NOFILL_RMI_CID_S__SHIFT 0xd |
11144 | #define RMI_SPARE__NOFILL_RMI_CID_TILE__SHIFT 0xe |
11145 | #define RMI_SPARE__SPARE_BIT_15_0__SHIFT 0xf |
11146 | #define RMI_SPARE__ARBITER_ADDRESS_MASK__SHIFT 0x10 |
11147 | #define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L |
11148 | #define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE_MASK 0x00000002L |
11149 | #define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE_MASK 0x00000004L |
11150 | #define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE_MASK 0x00000008L |
11151 | #define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS_MASK 0x00000010L |
11152 | #define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS_MASK 0x00000020L |
11153 | #define RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE_MASK 0x00000040L |
11154 | #define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L |
11155 | #define RMI_SPARE__NOFILL_RMI_CID_CC_MASK 0x00000100L |
11156 | #define RMI_SPARE__NOFILL_RMI_CID_FC_MASK 0x00000200L |
11157 | #define RMI_SPARE__NOFILL_RMI_CID_CM_MASK 0x00000400L |
11158 | #define RMI_SPARE__NOFILL_RMI_CID_DC_MASK 0x00000800L |
11159 | #define RMI_SPARE__NOFILL_RMI_CID_Z_MASK 0x00001000L |
11160 | #define RMI_SPARE__NOFILL_RMI_CID_S_MASK 0x00002000L |
11161 | #define RMI_SPARE__NOFILL_RMI_CID_TILE_MASK 0x00004000L |
11162 | #define RMI_SPARE__SPARE_BIT_15_0_MASK 0x00008000L |
11163 | #define RMI_SPARE__ARBITER_ADDRESS_MASK_MASK 0xFFFF0000L |
11164 | //RMI_SPARE_1 |
11165 | #define RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE__SHIFT 0x0 |
11166 | #define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1 |
11167 | #define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2 |
11168 | #define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3 |
11169 | #define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4 |
11170 | #define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5 |
11171 | #define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6 |
11172 | #define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7 |
11173 | #define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID__SHIFT 0x8 |
11174 | #define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10 |
11175 | #define RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE_MASK 0x00000001L |
11176 | #define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L |
11177 | #define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L |
11178 | #define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L |
11179 | #define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L |
11180 | #define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L |
11181 | #define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L |
11182 | #define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L |
11183 | #define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID_MASK 0x0000FF00L |
11184 | #define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L |
11185 | //RMI_SPARE_2 |
11186 | #define RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID__SHIFT 0x0 |
11187 | #define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10 |
11188 | #define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18 |
11189 | #define RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID_MASK 0x0000FFFFL |
11190 | #define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L |
11191 | #define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L |
11192 | //CC_RMI_REDUNDANCY |
11193 | #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1 |
11194 | #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2 |
11195 | #define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3 |
11196 | #define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4 |
11197 | #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L |
11198 | #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L |
11199 | #define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L |
11200 | #define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L |
11201 | //GC_USER_RMI_REDUNDANCY |
11202 | #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1 |
11203 | #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2 |
11204 | #define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3 |
11205 | #define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4 |
11206 | #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L |
11207 | #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L |
11208 | #define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L |
11209 | #define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L |
11210 | |
11211 | |
11212 | // addressBlock: gc_pmmdec |
11213 | //GCR_GENERAL_CNTL |
11214 | #define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP__SHIFT 0x0 |
11215 | #define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ__SHIFT 0x1 |
11216 | #define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ__SHIFT 0x2 |
11217 | #define GCR_GENERAL_CNTL__FORCE_INV_ALL__SHIFT 0x3 |
11218 | #define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL__SHIFT 0x4 |
11219 | #define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE__SHIFT 0x6 |
11220 | #define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE__SHIFT 0x7 |
11221 | #define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE__SHIFT 0x8 |
11222 | #define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ__SHIFT 0x9 |
11223 | #define GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT 0xa |
11224 | #define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS__SHIFT 0xd |
11225 | #define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS__SHIFT 0xe |
11226 | #define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ__SHIFT 0xf |
11227 | #define GCR_GENERAL_CNTL__DISABLE_FGCG__SHIFT 0x10 |
11228 | #define GCR_GENERAL_CNTL__CLIENT_ID__SHIFT 0x14 |
11229 | #define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP_MASK 0x00000001L |
11230 | #define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ_MASK 0x00000002L |
11231 | #define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK 0x00000004L |
11232 | #define GCR_GENERAL_CNTL__FORCE_INV_ALL_MASK 0x00000008L |
11233 | #define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL_MASK 0x00000030L |
11234 | #define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE_MASK 0x00000040L |
11235 | #define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE_MASK 0x00000080L |
11236 | #define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE_MASK 0x00000100L |
11237 | #define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ_MASK 0x00000200L |
11238 | #define GCR_GENERAL_CNTL__UTCL2_REQ_PERM_MASK 0x00001C00L |
11239 | #define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS_MASK 0x00002000L |
11240 | #define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS_MASK 0x00004000L |
11241 | #define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ_MASK 0x00008000L |
11242 | #define GCR_GENERAL_CNTL__DISABLE_FGCG_MASK 0x00010000L |
11243 | #define GCR_GENERAL_CNTL__CLIENT_ID_MASK 0x1FF00000L |
11244 | //GCR_CMD_STATUS |
11245 | #define GCR_CMD_STATUS__GCR_CONTROL__SHIFT 0x0 |
11246 | #define GCR_CMD_STATUS__GCR_SRC__SHIFT 0x14 |
11247 | #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN__SHIFT 0x17 |
11248 | #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID__SHIFT 0x18 |
11249 | #define GCR_CMD_STATUS__UTCL2_NACK_STATUS__SHIFT 0x1c |
11250 | #define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR__SHIFT 0x1e |
11251 | #define GCR_CMD_STATUS__UTCL2_NACK_ERROR__SHIFT 0x1f |
11252 | #define GCR_CMD_STATUS__GCR_CONTROL_MASK 0x0007FFFFL |
11253 | #define GCR_CMD_STATUS__GCR_SRC_MASK 0x00700000L |
11254 | #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_MASK 0x00800000L |
11255 | #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID_MASK 0x0F000000L |
11256 | #define GCR_CMD_STATUS__UTCL2_NACK_STATUS_MASK 0x30000000L |
11257 | #define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR_MASK 0x40000000L |
11258 | #define GCR_CMD_STATUS__UTCL2_NACK_ERROR_MASK 0x80000000L |
11259 | //GCR_SPARE |
11260 | #define GCR_SPARE__SPARE_BIT_1__SHIFT 0x1 |
11261 | #define GCR_SPARE__SPARE_BIT_2__SHIFT 0x2 |
11262 | #define GCR_SPARE__SPARE_BIT_3__SHIFT 0x3 |
11263 | #define GCR_SPARE__SPARE_BIT_4__SHIFT 0x4 |
11264 | #define GCR_SPARE__SPARE_BIT_5__SHIFT 0x5 |
11265 | #define GCR_SPARE__SPARE_BIT_6__SHIFT 0x6 |
11266 | #define GCR_SPARE__SPARE_BIT_7__SHIFT 0x7 |
11267 | #define GCR_SPARE__SPARE_BIT_8_0__SHIFT 0x8 |
11268 | #define GCR_SPARE__SPARE_BIT_31_16__SHIFT 0x10 |
11269 | #define GCR_SPARE__SPARE_BIT_1_MASK 0x00000002L |
11270 | #define GCR_SPARE__SPARE_BIT_2_MASK 0x00000004L |
11271 | #define GCR_SPARE__SPARE_BIT_3_MASK 0x00000008L |
11272 | #define GCR_SPARE__SPARE_BIT_4_MASK 0x00000010L |
11273 | #define GCR_SPARE__SPARE_BIT_5_MASK 0x00000020L |
11274 | #define GCR_SPARE__SPARE_BIT_6_MASK 0x00000040L |
11275 | #define GCR_SPARE__SPARE_BIT_7_MASK 0x00000080L |
11276 | #define GCR_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L |
11277 | #define GCR_SPARE__SPARE_BIT_31_16_MASK 0xFFFF0000L |
11278 | //PMM_GENERAL_CNTL |
11279 | #define PMM_GENERAL_CNTL__PMM_MODE__SHIFT 0x0 |
11280 | #define PMM_GENERAL_CNTL__PMM_DISABLE__SHIFT 0x1 |
11281 | #define PMM_GENERAL_CNTL__PMM_ALOG_IH_IDLE__SHIFT 0x2 |
11282 | #define PMM_GENERAL_CNTL__PMM_MODE_MASK 0x00000001L |
11283 | #define PMM_GENERAL_CNTL__PMM_DISABLE_MASK 0x00000002L |
11284 | #define PMM_GENERAL_CNTL__PMM_ALOG_IH_IDLE_MASK 0x00000004L |
11285 | //GCR_PIO_CNTL |
11286 | #define GCR_PIO_CNTL__GCR_DATA_INDEX__SHIFT 0x0 |
11287 | #define GCR_PIO_CNTL__GCR_REG_DONE__SHIFT 0x2 |
11288 | #define GCR_PIO_CNTL__GCR_REG_RESET__SHIFT 0x3 |
11289 | #define GCR_PIO_CNTL__GCR_PIO_RSP_TAG__SHIFT 0x10 |
11290 | #define GCR_PIO_CNTL__GCR_PIO_RSP_DONE__SHIFT 0x1e |
11291 | #define GCR_PIO_CNTL__GCR_READY__SHIFT 0x1f |
11292 | #define GCR_PIO_CNTL__GCR_DATA_INDEX_MASK 0x00000003L |
11293 | #define GCR_PIO_CNTL__GCR_REG_DONE_MASK 0x00000004L |
11294 | #define GCR_PIO_CNTL__GCR_REG_RESET_MASK 0x00000008L |
11295 | #define GCR_PIO_CNTL__GCR_PIO_RSP_TAG_MASK 0x00FF0000L |
11296 | #define GCR_PIO_CNTL__GCR_PIO_RSP_DONE_MASK 0x40000000L |
11297 | #define GCR_PIO_CNTL__GCR_READY_MASK 0x80000000L |
11298 | //GCR_PIO_DATA |
11299 | #define GCR_PIO_DATA__GCR_DATA__SHIFT 0x0 |
11300 | #define GCR_PIO_DATA__GCR_DATA_MASK 0xFFFFFFFFL |
11301 | |
11302 | |
11303 | // addressBlock: gc_utcl1dec |
11304 | //UTCL1_CTRL |
11305 | #define UTCL1_CTRL__UTCL1_SMALL_PAGE_SIZE__SHIFT 0x0 |
11306 | #define UTCL1_CTRL__UTCL1_LARGE_PAGE_SIZE__SHIFT 0x1 |
11307 | #define UTCL1_CTRL__UTCL1_CACHE_CORE_BYPASS__SHIFT 0x2 |
11308 | #define UTCL1_CTRL__UTCL1_TCP_BYPASS__SHIFT 0x3 |
11309 | #define UTCL1_CTRL__UTCL1_SQCI_BYPASS__SHIFT 0x4 |
11310 | #define UTCL1_CTRL__UTCL1_SQCD_BYPASS__SHIFT 0x5 |
11311 | #define UTCL1_CTRL__UTCL1_RMI_BYPASS__SHIFT 0x6 |
11312 | #define UTCL1_CTRL__UTCL1_SQG_BYPASS__SHIFT 0x7 |
11313 | #define UTCL1_CTRL__UTCL1_RMI_DEDICATED_CACHE_CORE__SHIFT 0x8 |
11314 | #define UTCL1_CTRL__UTCL1_FORCE_RANGE_INV_TO_VMID__SHIFT 0x9 |
11315 | #define UTCL1_CTRL__UTCL1_FORCE_INV_ALL__SHIFT 0xa |
11316 | #define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_DONE__SHIFT 0xb |
11317 | #define UTCL1_CTRL__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE__SHIFT 0xc |
11318 | #define UTCL1_CTRL__UTCL1_INV_FILTER_2M__SHIFT 0xd |
11319 | #define UTCL1_CTRL__UTCL1_RANGE_INV_FORCE_CHK_ALL__SHIFT 0xe |
11320 | #define UTCL1_CTRL__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE__SHIFT 0xf |
11321 | #define UTCL1_CTRL__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE__SHIFT 0x10 |
11322 | #define UTCL1_CTRL__GCRD_FGCG_DISABLE__SHIFT 0x11 |
11323 | #define UTCL1_CTRL__UTCL1_MH_INV_FRAG_SIZE_OVERRIDE__SHIFT 0x12 |
11324 | #define UTCL1_CTRL__UTCL1_CACHE_WRITE_PERM__SHIFT 0x13 |
11325 | #define UTCL1_CTRL__UTCL1_MH_CAM_DUPLICATE_4K_FILTER__SHIFT 0x14 |
11326 | #define UTCL1_CTRL__UTCL1_MH_DISABLE_DUPLICATES__SHIFT 0x15 |
11327 | #define UTCL1_CTRL__UTCL1_MH_DISABLE_RECENT_BUFFER__SHIFT 0x17 |
11328 | #define UTCL1_CTRL__UTCL1_MISS_CC_PRIORITY__SHIFT 0x18 |
11329 | #define UTCL1_CTRL__UTCL1_REDUCE_CC_SIZE__SHIFT 0x1a |
11330 | #define UTCL1_CTRL__RESERVED__SHIFT 0x1c |
11331 | #define UTCL1_CTRL__UTCL1_SMALL_PAGE_SIZE_MASK 0x00000001L |
11332 | #define UTCL1_CTRL__UTCL1_LARGE_PAGE_SIZE_MASK 0x00000002L |
11333 | #define UTCL1_CTRL__UTCL1_CACHE_CORE_BYPASS_MASK 0x00000004L |
11334 | #define UTCL1_CTRL__UTCL1_TCP_BYPASS_MASK 0x00000008L |
11335 | #define UTCL1_CTRL__UTCL1_SQCI_BYPASS_MASK 0x00000010L |
11336 | #define UTCL1_CTRL__UTCL1_SQCD_BYPASS_MASK 0x00000020L |
11337 | #define UTCL1_CTRL__UTCL1_RMI_BYPASS_MASK 0x00000040L |
11338 | #define UTCL1_CTRL__UTCL1_SQG_BYPASS_MASK 0x00000080L |
11339 | #define UTCL1_CTRL__UTCL1_RMI_DEDICATED_CACHE_CORE_MASK 0x00000100L |
11340 | #define UTCL1_CTRL__UTCL1_FORCE_RANGE_INV_TO_VMID_MASK 0x00000200L |
11341 | #define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_MASK 0x00000400L |
11342 | #define UTCL1_CTRL__UTCL1_FORCE_INV_ALL_DONE_MASK 0x00000800L |
11343 | #define UTCL1_CTRL__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE_MASK 0x00001000L |
11344 | #define UTCL1_CTRL__UTCL1_INV_FILTER_2M_MASK 0x00002000L |
11345 | #define UTCL1_CTRL__UTCL1_RANGE_INV_FORCE_CHK_ALL_MASK 0x00004000L |
11346 | #define UTCL1_CTRL__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE_MASK 0x00008000L |
11347 | #define UTCL1_CTRL__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE_MASK 0x00010000L |
11348 | #define UTCL1_CTRL__GCRD_FGCG_DISABLE_MASK 0x00020000L |
11349 | #define UTCL1_CTRL__UTCL1_MH_INV_FRAG_SIZE_OVERRIDE_MASK 0x00040000L |
11350 | #define UTCL1_CTRL__UTCL1_CACHE_WRITE_PERM_MASK 0x00080000L |
11351 | #define UTCL1_CTRL__UTCL1_MH_CAM_DUPLICATE_4K_FILTER_MASK 0x00100000L |
11352 | #define UTCL1_CTRL__UTCL1_MH_DISABLE_DUPLICATES_MASK 0x00200000L |
11353 | #define UTCL1_CTRL__UTCL1_MH_DISABLE_RECENT_BUFFER_MASK 0x00800000L |
11354 | #define UTCL1_CTRL__UTCL1_MISS_CC_PRIORITY_MASK 0x03000000L |
11355 | #define UTCL1_CTRL__UTCL1_REDUCE_CC_SIZE_MASK 0x0C000000L |
11356 | #define UTCL1_CTRL__RESERVED_MASK 0xF0000000L |
11357 | //UTCL1_ALOG |
11358 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD__SHIFT 0x0 |
11359 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS__SHIFT 0x3 |
11360 | #define UTCL1_ALOG__UTCL1_ALOG_ACTIVE__SHIFT 0x4 |
11361 | #define UTCL1_ALOG__UTCL1_ALOG_MODE__SHIFT 0x5 |
11362 | #define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW__SHIFT 0x6 |
11363 | #define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS__SHIFT 0x9 |
11364 | #define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT 0xa |
11365 | #define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN__SHIFT 0xc |
11366 | #define UTCL1_ALOG__UTCL1_ALOG_CLEAN__SHIFT 0xf |
11367 | #define UTCL1_ALOG__UTCL1_ALOG_IDLE__SHIFT 0x10 |
11368 | #define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE__SHIFT 0x11 |
11369 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS__SHIFT 0x17 |
11370 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC__SHIFT 0x18 |
11371 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD_MASK 0x00000007L |
11372 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS_MASK 0x00000008L |
11373 | #define UTCL1_ALOG__UTCL1_ALOG_ACTIVE_MASK 0x00000010L |
11374 | #define UTCL1_ALOG__UTCL1_ALOG_MODE_MASK 0x00000020L |
11375 | #define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW_MASK 0x000001C0L |
11376 | #define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS_MASK 0x00000200L |
11377 | #define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD_MASK 0x00000C00L |
11378 | #define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN_MASK 0x00007000L |
11379 | #define UTCL1_ALOG__UTCL1_ALOG_CLEAN_MASK 0x00008000L |
11380 | #define UTCL1_ALOG__UTCL1_ALOG_IDLE_MASK 0x00010000L |
11381 | #define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE_MASK 0x007E0000L |
11382 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS_MASK 0x00800000L |
11383 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC_MASK 0x01000000L |
11384 | //UTCL1_UTCL0_INVREQ_DISABLE |
11385 | #define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE__SHIFT 0x0 |
11386 | #define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE_MASK 0xFFFFFFFFL |
11387 | //GCRD_SA_TARGETS_DISABLE |
11388 | #define GCRD_SA_TARGETS_DISABLE__GCRD_TARGETS_DISABLE__SHIFT 0x0 |
11389 | #define GCRD_SA_TARGETS_DISABLE__GCRD_TARGETS_DISABLE_MASK 0x0007FFFFL |
11390 | //UTCL1_STATUS |
11391 | #define UTCL1_STATUS__UTCL1_HIT_PATH_BUSY__SHIFT 0x0 |
11392 | #define UTCL1_STATUS__UTCL1_MH_BUSY__SHIFT 0x1 |
11393 | #define UTCL1_STATUS__UTCL1_INV_BUSY__SHIFT 0x2 |
11394 | #define UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ__SHIFT 0x3 |
11395 | #define UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET__SHIFT 0x4 |
11396 | #define UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK__SHIFT 0x5 |
11397 | #define UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS__SHIFT 0x7 |
11398 | #define UTCL1_STATUS__RESERVED__SHIFT 0x8 |
11399 | #define UTCL1_STATUS__UTCL1_HIT_PATH_BUSY_MASK 0x00000001L |
11400 | #define UTCL1_STATUS__UTCL1_MH_BUSY_MASK 0x00000002L |
11401 | #define UTCL1_STATUS__UTCL1_INV_BUSY_MASK 0x00000004L |
11402 | #define UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ_MASK 0x00000008L |
11403 | #define UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET_MASK 0x00000010L |
11404 | #define UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK_MASK 0x00000060L |
11405 | #define UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS_MASK 0x00000080L |
11406 | #define UTCL1_STATUS__RESERVED_MASK 0x00000100L |
11407 | |
11408 | |
11409 | // addressBlock: gc_gcvml2pfdec |
11410 | //GCVM_L2_CNTL |
11411 | #define GCVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 |
11412 | #define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 |
11413 | #define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 |
11414 | #define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 |
11415 | #define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 |
11416 | #define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 |
11417 | #define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa |
11418 | #define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb |
11419 | #define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc |
11420 | #define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf |
11421 | #define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 |
11422 | #define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 |
11423 | #define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 |
11424 | #define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a |
11425 | #define GCVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L |
11426 | #define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L |
11427 | #define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL |
11428 | #define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L |
11429 | #define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L |
11430 | #define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L |
11431 | #define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L |
11432 | #define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L |
11433 | #define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L |
11434 | #define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L |
11435 | #define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L |
11436 | #define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L |
11437 | #define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L |
11438 | #define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L |
11439 | //GCVM_L2_CNTL2 |
11440 | #define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 |
11441 | #define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 |
11442 | #define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 |
11443 | #define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 |
11444 | #define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 |
11445 | #define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a |
11446 | #define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c |
11447 | #define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L |
11448 | #define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L |
11449 | #define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L |
11450 | #define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L |
11451 | #define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L |
11452 | #define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L |
11453 | #define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L |
11454 | //GCVM_L2_CNTL3 |
11455 | #define GCVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 |
11456 | #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 |
11457 | #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 |
11458 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf |
11459 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 |
11460 | #define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 |
11461 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 |
11462 | #define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c |
11463 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d |
11464 | #define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e |
11465 | #define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f |
11466 | #define GCVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL |
11467 | #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L |
11468 | #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L |
11469 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L |
11470 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L |
11471 | #define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L |
11472 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L |
11473 | #define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L |
11474 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L |
11475 | #define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L |
11476 | #define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L |
11477 | //GCVM_L2_STATUS |
11478 | #define GCVM_L2_STATUS__L2_BUSY__SHIFT 0x0 |
11479 | #define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 |
11480 | #define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 |
11481 | #define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 |
11482 | #define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 |
11483 | #define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 |
11484 | #define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 |
11485 | #define GCVM_L2_STATUS__L2_BUSY_MASK 0x00000001L |
11486 | #define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL |
11487 | #define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L |
11488 | #define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L |
11489 | #define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L |
11490 | #define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L |
11491 | #define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L |
11492 | //GCVM_DUMMY_PAGE_FAULT_CNTL |
11493 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 |
11494 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 |
11495 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 |
11496 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L |
11497 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L |
11498 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL |
11499 | //GCVM_DUMMY_PAGE_FAULT_ADDR_LO32 |
11500 | #define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 |
11501 | #define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
11502 | //GCVM_DUMMY_PAGE_FAULT_ADDR_HI32 |
11503 | #define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 |
11504 | #define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL |
11505 | //GCVM_INVALIDATE_CNTL |
11506 | #define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 |
11507 | #define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 |
11508 | #define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL |
11509 | #define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L |
11510 | //GCVM_L2_PROTECTION_FAULT_CNTL |
11511 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 |
11512 | #define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 |
11513 | #define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 |
11514 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 |
11515 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 |
11516 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 |
11517 | #define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 |
11518 | #define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 |
11519 | #define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 |
11520 | #define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 |
11521 | #define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
11522 | #define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb |
11523 | #define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
11524 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd |
11525 | #define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d |
11526 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e |
11527 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f |
11528 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L |
11529 | #define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L |
11530 | #define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L |
11531 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L |
11532 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L |
11533 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L |
11534 | #define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L |
11535 | #define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L |
11536 | #define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L |
11537 | #define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L |
11538 | #define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
11539 | #define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L |
11540 | #define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
11541 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L |
11542 | #define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L |
11543 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L |
11544 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L |
11545 | //GCVM_L2_PROTECTION_FAULT_CNTL2 |
11546 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 |
11547 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 |
11548 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 |
11549 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 |
11550 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 |
11551 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL |
11552 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L |
11553 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L |
11554 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L |
11555 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L |
11556 | //GCVM_L2_PROTECTION_FAULT_MM_CNTL3 |
11557 | #define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 |
11558 | #define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL |
11559 | //GCVM_L2_PROTECTION_FAULT_MM_CNTL4 |
11560 | #define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 |
11561 | #define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL |
11562 | //GCVM_L2_PROTECTION_FAULT_STATUS |
11563 | #define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 |
11564 | #define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 |
11565 | #define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 |
11566 | #define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 |
11567 | #define GCVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 |
11568 | #define GCVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 |
11569 | #define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 |
11570 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 |
11571 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 |
11572 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 |
11573 | #define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L |
11574 | #define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL |
11575 | #define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L |
11576 | #define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L |
11577 | #define GCVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L |
11578 | #define GCVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L |
11579 | #define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L |
11580 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L |
11581 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L |
11582 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x3E000000L |
11583 | //GCVM_L2_PROTECTION_FAULT_ADDR_LO32 |
11584 | #define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 |
11585 | #define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
11586 | //GCVM_L2_PROTECTION_FAULT_ADDR_HI32 |
11587 | #define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 |
11588 | #define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL |
11589 | //GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 |
11590 | #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 |
11591 | #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
11592 | //GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 |
11593 | #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 |
11594 | #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL |
11595 | //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 |
11596 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
11597 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
11598 | //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 |
11599 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
11600 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
11601 | //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 |
11602 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
11603 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
11604 | //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 |
11605 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
11606 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
11607 | //GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 |
11608 | #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 |
11609 | #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL |
11610 | //GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 |
11611 | #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 |
11612 | #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL |
11613 | //GCVM_L2_CNTL4 |
11614 | #define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 |
11615 | #define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 |
11616 | #define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 |
11617 | #define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 |
11618 | #define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 |
11619 | #define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c |
11620 | #define GCVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d |
11621 | #define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL |
11622 | #define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L |
11623 | #define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L |
11624 | #define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L |
11625 | #define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L |
11626 | #define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L |
11627 | #define GCVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L |
11628 | //GCVM_L2_MM_GROUP_RT_CLASSES |
11629 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 |
11630 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 |
11631 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 |
11632 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 |
11633 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 |
11634 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 |
11635 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 |
11636 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 |
11637 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 |
11638 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 |
11639 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa |
11640 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb |
11641 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc |
11642 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd |
11643 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe |
11644 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf |
11645 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 |
11646 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 |
11647 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 |
11648 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 |
11649 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 |
11650 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 |
11651 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 |
11652 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 |
11653 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 |
11654 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 |
11655 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a |
11656 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b |
11657 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c |
11658 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d |
11659 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e |
11660 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f |
11661 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L |
11662 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L |
11663 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L |
11664 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L |
11665 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L |
11666 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L |
11667 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L |
11668 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L |
11669 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L |
11670 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L |
11671 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L |
11672 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L |
11673 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L |
11674 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L |
11675 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L |
11676 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L |
11677 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L |
11678 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L |
11679 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L |
11680 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L |
11681 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L |
11682 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L |
11683 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L |
11684 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L |
11685 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L |
11686 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L |
11687 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L |
11688 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L |
11689 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L |
11690 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L |
11691 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L |
11692 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L |
11693 | //GCVM_L2_BANK_SELECT_RESERVED_CID |
11694 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 |
11695 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa |
11696 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 |
11697 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 |
11698 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 |
11699 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a |
11700 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL |
11701 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L |
11702 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L |
11703 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L |
11704 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L |
11705 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L |
11706 | //GCVM_L2_BANK_SELECT_RESERVED_CID2 |
11707 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 |
11708 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa |
11709 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 |
11710 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 |
11711 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 |
11712 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a |
11713 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL |
11714 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L |
11715 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L |
11716 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L |
11717 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L |
11718 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L |
11719 | //GCVM_L2_CACHE_PARITY_CNTL |
11720 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 |
11721 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 |
11722 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 |
11723 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 |
11724 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 |
11725 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 |
11726 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 |
11727 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 |
11728 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc |
11729 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L |
11730 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L |
11731 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L |
11732 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L |
11733 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L |
11734 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L |
11735 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L |
11736 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L |
11737 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L |
11738 | //GCVM_L2_CNTL5 |
11739 | #define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
11740 | #define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 |
11741 | #define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
11742 | #define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L |
11743 | //GCVM_L2_GCR_CNTL |
11744 | #define GCVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 |
11745 | #define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 |
11746 | #define GCVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L |
11747 | #define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL |
11748 | //GCVML2_WALKER_MACRO_THROTTLE_TIME |
11749 | #define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT 0x0 |
11750 | #define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL |
11751 | //GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT |
11752 | #define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 |
11753 | #define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL |
11754 | //GCVML2_WALKER_MICRO_THROTTLE_TIME |
11755 | #define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT 0x0 |
11756 | #define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL |
11757 | //GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT |
11758 | #define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 |
11759 | #define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL |
11760 | //GCVM_L2_PTE_CACHE_DUMP_CNTL |
11761 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 |
11762 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 |
11763 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 |
11764 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 |
11765 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc |
11766 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 |
11767 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L |
11768 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L |
11769 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L |
11770 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L |
11771 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L |
11772 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L |
11773 | //GCVM_L2_PTE_CACHE_DUMP_READ |
11774 | #define GCVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 |
11775 | #define GCVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL |
11776 | |
11777 | |
11778 | // addressBlock: gc_gcvml2vcdec |
11779 | //GCVM_CONTEXT0_CNTL |
11780 | #define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
11781 | #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
11782 | #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
11783 | #define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
11784 | #define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
11785 | #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
11786 | #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
11787 | #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
11788 | #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
11789 | #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
11790 | #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
11791 | #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
11792 | #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
11793 | #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
11794 | #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
11795 | #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
11796 | #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
11797 | #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
11798 | #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
11799 | #define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
11800 | #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
11801 | #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
11802 | #define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
11803 | #define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
11804 | #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
11805 | #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
11806 | #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
11807 | #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
11808 | #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
11809 | #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
11810 | #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
11811 | #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
11812 | #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
11813 | #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
11814 | #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
11815 | #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
11816 | #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
11817 | #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
11818 | //GCVM_CONTEXT1_CNTL |
11819 | #define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
11820 | #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
11821 | #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
11822 | #define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
11823 | #define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
11824 | #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
11825 | #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
11826 | #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
11827 | #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
11828 | #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
11829 | #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
11830 | #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
11831 | #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
11832 | #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
11833 | #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
11834 | #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
11835 | #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
11836 | #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
11837 | #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
11838 | #define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
11839 | #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
11840 | #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
11841 | #define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
11842 | #define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
11843 | #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
11844 | #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
11845 | #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
11846 | #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
11847 | #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
11848 | #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
11849 | #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
11850 | #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
11851 | #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
11852 | #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
11853 | #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
11854 | #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
11855 | #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
11856 | #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
11857 | //GCVM_CONTEXT2_CNTL |
11858 | #define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
11859 | #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
11860 | #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
11861 | #define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
11862 | #define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
11863 | #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
11864 | #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
11865 | #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
11866 | #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
11867 | #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
11868 | #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
11869 | #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
11870 | #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
11871 | #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
11872 | #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
11873 | #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
11874 | #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
11875 | #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
11876 | #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
11877 | #define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
11878 | #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
11879 | #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
11880 | #define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
11881 | #define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
11882 | #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
11883 | #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
11884 | #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
11885 | #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
11886 | #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
11887 | #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
11888 | #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
11889 | #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
11890 | #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
11891 | #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
11892 | #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
11893 | #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
11894 | #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
11895 | #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
11896 | //GCVM_CONTEXT3_CNTL |
11897 | #define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
11898 | #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
11899 | #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
11900 | #define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
11901 | #define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
11902 | #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
11903 | #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
11904 | #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
11905 | #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
11906 | #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
11907 | #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
11908 | #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
11909 | #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
11910 | #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
11911 | #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
11912 | #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
11913 | #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
11914 | #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
11915 | #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
11916 | #define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
11917 | #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
11918 | #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
11919 | #define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
11920 | #define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
11921 | #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
11922 | #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
11923 | #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
11924 | #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
11925 | #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
11926 | #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
11927 | #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
11928 | #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
11929 | #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
11930 | #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
11931 | #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
11932 | #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
11933 | #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
11934 | #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
11935 | //GCVM_CONTEXT4_CNTL |
11936 | #define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
11937 | #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
11938 | #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
11939 | #define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
11940 | #define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
11941 | #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
11942 | #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
11943 | #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
11944 | #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
11945 | #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
11946 | #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
11947 | #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
11948 | #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
11949 | #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
11950 | #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
11951 | #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
11952 | #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
11953 | #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
11954 | #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
11955 | #define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
11956 | #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
11957 | #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
11958 | #define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
11959 | #define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
11960 | #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
11961 | #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
11962 | #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
11963 | #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
11964 | #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
11965 | #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
11966 | #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
11967 | #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
11968 | #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
11969 | #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
11970 | #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
11971 | #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
11972 | #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
11973 | #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
11974 | //GCVM_CONTEXT5_CNTL |
11975 | #define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
11976 | #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
11977 | #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
11978 | #define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
11979 | #define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
11980 | #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
11981 | #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
11982 | #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
11983 | #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
11984 | #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
11985 | #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
11986 | #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
11987 | #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
11988 | #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
11989 | #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
11990 | #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
11991 | #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
11992 | #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
11993 | #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
11994 | #define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
11995 | #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
11996 | #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
11997 | #define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
11998 | #define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
11999 | #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12000 | #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12001 | #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12002 | #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12003 | #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12004 | #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12005 | #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12006 | #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12007 | #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12008 | #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12009 | #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12010 | #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12011 | #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12012 | #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12013 | //GCVM_CONTEXT6_CNTL |
12014 | #define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12015 | #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12016 | #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12017 | #define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12018 | #define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12019 | #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12020 | #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12021 | #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12022 | #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12023 | #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12024 | #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12025 | #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12026 | #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12027 | #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12028 | #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12029 | #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12030 | #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12031 | #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12032 | #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12033 | #define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12034 | #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12035 | #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12036 | #define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12037 | #define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12038 | #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12039 | #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12040 | #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12041 | #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12042 | #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12043 | #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12044 | #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12045 | #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12046 | #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12047 | #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12048 | #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12049 | #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12050 | #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12051 | #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12052 | //GCVM_CONTEXT7_CNTL |
12053 | #define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12054 | #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12055 | #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12056 | #define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12057 | #define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12058 | #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12059 | #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12060 | #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12061 | #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12062 | #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12063 | #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12064 | #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12065 | #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12066 | #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12067 | #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12068 | #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12069 | #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12070 | #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12071 | #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12072 | #define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12073 | #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12074 | #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12075 | #define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12076 | #define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12077 | #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12078 | #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12079 | #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12080 | #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12081 | #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12082 | #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12083 | #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12084 | #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12085 | #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12086 | #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12087 | #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12088 | #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12089 | #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12090 | #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12091 | //GCVM_CONTEXT8_CNTL |
12092 | #define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12093 | #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12094 | #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12095 | #define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12096 | #define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12097 | #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12098 | #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12099 | #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12100 | #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12101 | #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12102 | #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12103 | #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12104 | #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12105 | #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12106 | #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12107 | #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12108 | #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12109 | #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12110 | #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12111 | #define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12112 | #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12113 | #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12114 | #define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12115 | #define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12116 | #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12117 | #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12118 | #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12119 | #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12120 | #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12121 | #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12122 | #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12123 | #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12124 | #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12125 | #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12126 | #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12127 | #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12128 | #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12129 | #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12130 | //GCVM_CONTEXT9_CNTL |
12131 | #define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12132 | #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12133 | #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12134 | #define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12135 | #define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12136 | #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12137 | #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12138 | #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12139 | #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12140 | #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12141 | #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12142 | #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12143 | #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12144 | #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12145 | #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12146 | #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12147 | #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12148 | #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12149 | #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12150 | #define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12151 | #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12152 | #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12153 | #define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12154 | #define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12155 | #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12156 | #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12157 | #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12158 | #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12159 | #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12160 | #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12161 | #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12162 | #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12163 | #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12164 | #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12165 | #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12166 | #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12167 | #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12168 | #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12169 | //GCVM_CONTEXT10_CNTL |
12170 | #define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12171 | #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12172 | #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12173 | #define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12174 | #define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12175 | #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12176 | #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12177 | #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12178 | #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12179 | #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12180 | #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12181 | #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12182 | #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12183 | #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12184 | #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12185 | #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12186 | #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12187 | #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12188 | #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12189 | #define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12190 | #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12191 | #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12192 | #define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12193 | #define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12194 | #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12195 | #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12196 | #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12197 | #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12198 | #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12199 | #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12200 | #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12201 | #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12202 | #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12203 | #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12204 | #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12205 | #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12206 | #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12207 | #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12208 | //GCVM_CONTEXT11_CNTL |
12209 | #define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12210 | #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12211 | #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12212 | #define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12213 | #define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12214 | #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12215 | #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12216 | #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12217 | #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12218 | #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12219 | #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12220 | #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12221 | #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12222 | #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12223 | #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12224 | #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12225 | #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12226 | #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12227 | #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12228 | #define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12229 | #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12230 | #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12231 | #define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12232 | #define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12233 | #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12234 | #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12235 | #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12236 | #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12237 | #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12238 | #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12239 | #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12240 | #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12241 | #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12242 | #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12243 | #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12244 | #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12245 | #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12246 | #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12247 | //GCVM_CONTEXT12_CNTL |
12248 | #define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12249 | #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12250 | #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12251 | #define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12252 | #define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12253 | #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12254 | #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12255 | #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12256 | #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12257 | #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12258 | #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12259 | #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12260 | #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12261 | #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12262 | #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12263 | #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12264 | #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12265 | #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12266 | #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12267 | #define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12268 | #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12269 | #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12270 | #define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12271 | #define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12272 | #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12273 | #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12274 | #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12275 | #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12276 | #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12277 | #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12278 | #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12279 | #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12280 | #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12281 | #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12282 | #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12283 | #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12284 | #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12285 | #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12286 | //GCVM_CONTEXT13_CNTL |
12287 | #define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12288 | #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12289 | #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12290 | #define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12291 | #define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12292 | #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12293 | #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12294 | #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12295 | #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12296 | #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12297 | #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12298 | #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12299 | #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12300 | #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12301 | #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12302 | #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12303 | #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12304 | #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12305 | #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12306 | #define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12307 | #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12308 | #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12309 | #define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12310 | #define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12311 | #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12312 | #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12313 | #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12314 | #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12315 | #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12316 | #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12317 | #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12318 | #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12319 | #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12320 | #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12321 | #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12322 | #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12323 | #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12324 | #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12325 | //GCVM_CONTEXT14_CNTL |
12326 | #define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12327 | #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12328 | #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12329 | #define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12330 | #define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12331 | #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12332 | #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12333 | #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12334 | #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12335 | #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12336 | #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12337 | #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12338 | #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12339 | #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12340 | #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12341 | #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12342 | #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12343 | #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12344 | #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12345 | #define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12346 | #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12347 | #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12348 | #define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12349 | #define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12350 | #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12351 | #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12352 | #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12353 | #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12354 | #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12355 | #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12356 | #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12357 | #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12358 | #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12359 | #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12360 | #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12361 | #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12362 | #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12363 | #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12364 | //GCVM_CONTEXT15_CNTL |
12365 | #define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
12366 | #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
12367 | #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
12368 | #define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
12369 | #define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
12370 | #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
12371 | #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12372 | #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
12373 | #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12374 | #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
12375 | #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
12376 | #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
12377 | #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
12378 | #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
12379 | #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
12380 | #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
12381 | #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
12382 | #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
12383 | #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
12384 | #define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
12385 | #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
12386 | #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
12387 | #define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
12388 | #define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
12389 | #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
12390 | #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12391 | #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
12392 | #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12393 | #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
12394 | #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
12395 | #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
12396 | #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
12397 | #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
12398 | #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
12399 | #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
12400 | #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
12401 | #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
12402 | #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
12403 | //GCVM_CONTEXTS_DISABLE |
12404 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 |
12405 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 |
12406 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 |
12407 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 |
12408 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 |
12409 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 |
12410 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 |
12411 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 |
12412 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 |
12413 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 |
12414 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa |
12415 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb |
12416 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc |
12417 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd |
12418 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe |
12419 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf |
12420 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L |
12421 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L |
12422 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L |
12423 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L |
12424 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L |
12425 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L |
12426 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L |
12427 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L |
12428 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L |
12429 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L |
12430 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L |
12431 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L |
12432 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L |
12433 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L |
12434 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L |
12435 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L |
12436 | //GCVM_INVALIDATE_ENG0_SEM |
12437 | #define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 |
12438 | #define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L |
12439 | //GCVM_INVALIDATE_ENG1_SEM |
12440 | #define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 |
12441 | #define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L |
12442 | //GCVM_INVALIDATE_ENG2_SEM |
12443 | #define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 |
12444 | #define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L |
12445 | //GCVM_INVALIDATE_ENG3_SEM |
12446 | #define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 |
12447 | #define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L |
12448 | //GCVM_INVALIDATE_ENG4_SEM |
12449 | #define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 |
12450 | #define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L |
12451 | //GCVM_INVALIDATE_ENG5_SEM |
12452 | #define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 |
12453 | #define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L |
12454 | //GCVM_INVALIDATE_ENG6_SEM |
12455 | #define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 |
12456 | #define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L |
12457 | //GCVM_INVALIDATE_ENG7_SEM |
12458 | #define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 |
12459 | #define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L |
12460 | //GCVM_INVALIDATE_ENG8_SEM |
12461 | #define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 |
12462 | #define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L |
12463 | //GCVM_INVALIDATE_ENG9_SEM |
12464 | #define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 |
12465 | #define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L |
12466 | //GCVM_INVALIDATE_ENG10_SEM |
12467 | #define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 |
12468 | #define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L |
12469 | //GCVM_INVALIDATE_ENG11_SEM |
12470 | #define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 |
12471 | #define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L |
12472 | //GCVM_INVALIDATE_ENG12_SEM |
12473 | #define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 |
12474 | #define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L |
12475 | //GCVM_INVALIDATE_ENG13_SEM |
12476 | #define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 |
12477 | #define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L |
12478 | //GCVM_INVALIDATE_ENG14_SEM |
12479 | #define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 |
12480 | #define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L |
12481 | //GCVM_INVALIDATE_ENG15_SEM |
12482 | #define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 |
12483 | #define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L |
12484 | //GCVM_INVALIDATE_ENG16_SEM |
12485 | #define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 |
12486 | #define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L |
12487 | //GCVM_INVALIDATE_ENG17_SEM |
12488 | #define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 |
12489 | #define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L |
12490 | //GCVM_INVALIDATE_ENG0_REQ |
12491 | #define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12492 | #define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 |
12493 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12494 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12495 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12496 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12497 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12498 | #define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12499 | #define GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 |
12500 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12501 | #define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12502 | #define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L |
12503 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12504 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12505 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12506 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12507 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12508 | #define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12509 | #define GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L |
12510 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12511 | //GCVM_INVALIDATE_ENG1_REQ |
12512 | #define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12513 | #define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 |
12514 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12515 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12516 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12517 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12518 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12519 | #define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12520 | #define GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 |
12521 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12522 | #define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12523 | #define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L |
12524 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12525 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12526 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12527 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12528 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12529 | #define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12530 | #define GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L |
12531 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12532 | //GCVM_INVALIDATE_ENG2_REQ |
12533 | #define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12534 | #define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 |
12535 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12536 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12537 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12538 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12539 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12540 | #define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12541 | #define GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 |
12542 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12543 | #define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12544 | #define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L |
12545 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12546 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12547 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12548 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12549 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12550 | #define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12551 | #define GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L |
12552 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12553 | //GCVM_INVALIDATE_ENG3_REQ |
12554 | #define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12555 | #define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 |
12556 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12557 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12558 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12559 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12560 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12561 | #define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12562 | #define GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 |
12563 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12564 | #define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12565 | #define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L |
12566 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12567 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12568 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12569 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12570 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12571 | #define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12572 | #define GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L |
12573 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12574 | //GCVM_INVALIDATE_ENG4_REQ |
12575 | #define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12576 | #define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 |
12577 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12578 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12579 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12580 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12581 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12582 | #define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12583 | #define GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 |
12584 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12585 | #define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12586 | #define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L |
12587 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12588 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12589 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12590 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12591 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12592 | #define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12593 | #define GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L |
12594 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12595 | //GCVM_INVALIDATE_ENG5_REQ |
12596 | #define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12597 | #define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 |
12598 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12599 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12600 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12601 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12602 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12603 | #define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12604 | #define GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 |
12605 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12606 | #define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12607 | #define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L |
12608 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12609 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12610 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12611 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12612 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12613 | #define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12614 | #define GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L |
12615 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12616 | //GCVM_INVALIDATE_ENG6_REQ |
12617 | #define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12618 | #define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 |
12619 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12620 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12621 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12622 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12623 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12624 | #define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12625 | #define GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 |
12626 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12627 | #define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12628 | #define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L |
12629 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12630 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12631 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12632 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12633 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12634 | #define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12635 | #define GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L |
12636 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12637 | //GCVM_INVALIDATE_ENG7_REQ |
12638 | #define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12639 | #define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 |
12640 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12641 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12642 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12643 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12644 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12645 | #define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12646 | #define GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 |
12647 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12648 | #define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12649 | #define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L |
12650 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12651 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12652 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12653 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12654 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12655 | #define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12656 | #define GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L |
12657 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12658 | //GCVM_INVALIDATE_ENG8_REQ |
12659 | #define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12660 | #define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 |
12661 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12662 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12663 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12664 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12665 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12666 | #define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12667 | #define GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 |
12668 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12669 | #define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12670 | #define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L |
12671 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12672 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12673 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12674 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12675 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12676 | #define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12677 | #define GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L |
12678 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12679 | //GCVM_INVALIDATE_ENG9_REQ |
12680 | #define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12681 | #define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 |
12682 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12683 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12684 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12685 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12686 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12687 | #define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12688 | #define GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 |
12689 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12690 | #define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12691 | #define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L |
12692 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12693 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12694 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12695 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12696 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12697 | #define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12698 | #define GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L |
12699 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12700 | //GCVM_INVALIDATE_ENG10_REQ |
12701 | #define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12702 | #define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 |
12703 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12704 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12705 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12706 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12707 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12708 | #define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12709 | #define GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 |
12710 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12711 | #define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12712 | #define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L |
12713 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12714 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12715 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12716 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12717 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12718 | #define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12719 | #define GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L |
12720 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12721 | //GCVM_INVALIDATE_ENG11_REQ |
12722 | #define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12723 | #define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 |
12724 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12725 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12726 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12727 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12728 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12729 | #define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12730 | #define GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 |
12731 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12732 | #define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12733 | #define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L |
12734 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12735 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12736 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12737 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12738 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12739 | #define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12740 | #define GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L |
12741 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12742 | //GCVM_INVALIDATE_ENG12_REQ |
12743 | #define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12744 | #define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 |
12745 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12746 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12747 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12748 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12749 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12750 | #define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12751 | #define GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 |
12752 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12753 | #define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12754 | #define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L |
12755 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12756 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12757 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12758 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12759 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12760 | #define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12761 | #define GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L |
12762 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12763 | //GCVM_INVALIDATE_ENG13_REQ |
12764 | #define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12765 | #define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 |
12766 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12767 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12768 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12769 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12770 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12771 | #define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12772 | #define GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 |
12773 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12774 | #define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12775 | #define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L |
12776 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12777 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12778 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12779 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12780 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12781 | #define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12782 | #define GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L |
12783 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12784 | //GCVM_INVALIDATE_ENG14_REQ |
12785 | #define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12786 | #define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 |
12787 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12788 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12789 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12790 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12791 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12792 | #define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12793 | #define GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 |
12794 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12795 | #define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12796 | #define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L |
12797 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12798 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12799 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12800 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12801 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12802 | #define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12803 | #define GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L |
12804 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12805 | //GCVM_INVALIDATE_ENG15_REQ |
12806 | #define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12807 | #define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 |
12808 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12809 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12810 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12811 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12812 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12813 | #define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12814 | #define GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 |
12815 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12816 | #define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12817 | #define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L |
12818 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12819 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12820 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12821 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12822 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12823 | #define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12824 | #define GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L |
12825 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12826 | //GCVM_INVALIDATE_ENG16_REQ |
12827 | #define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12828 | #define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 |
12829 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12830 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12831 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12832 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12833 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12834 | #define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12835 | #define GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 |
12836 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12837 | #define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12838 | #define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L |
12839 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12840 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12841 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12842 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12843 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12844 | #define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12845 | #define GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L |
12846 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12847 | //GCVM_INVALIDATE_ENG17_REQ |
12848 | #define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
12849 | #define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 |
12850 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
12851 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
12852 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
12853 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
12854 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
12855 | #define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
12856 | #define GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 |
12857 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
12858 | #define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
12859 | #define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L |
12860 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
12861 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
12862 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
12863 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
12864 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
12865 | #define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
12866 | #define GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L |
12867 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
12868 | //GCVM_INVALIDATE_ENG0_ACK |
12869 | #define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12870 | #define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 |
12871 | #define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12872 | #define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L |
12873 | //GCVM_INVALIDATE_ENG1_ACK |
12874 | #define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12875 | #define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 |
12876 | #define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12877 | #define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L |
12878 | //GCVM_INVALIDATE_ENG2_ACK |
12879 | #define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12880 | #define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 |
12881 | #define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12882 | #define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L |
12883 | //GCVM_INVALIDATE_ENG3_ACK |
12884 | #define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12885 | #define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 |
12886 | #define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12887 | #define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L |
12888 | //GCVM_INVALIDATE_ENG4_ACK |
12889 | #define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12890 | #define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 |
12891 | #define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12892 | #define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L |
12893 | //GCVM_INVALIDATE_ENG5_ACK |
12894 | #define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12895 | #define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 |
12896 | #define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12897 | #define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L |
12898 | //GCVM_INVALIDATE_ENG6_ACK |
12899 | #define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12900 | #define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 |
12901 | #define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12902 | #define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L |
12903 | //GCVM_INVALIDATE_ENG7_ACK |
12904 | #define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12905 | #define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 |
12906 | #define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12907 | #define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L |
12908 | //GCVM_INVALIDATE_ENG8_ACK |
12909 | #define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12910 | #define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 |
12911 | #define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12912 | #define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L |
12913 | //GCVM_INVALIDATE_ENG9_ACK |
12914 | #define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12915 | #define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 |
12916 | #define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12917 | #define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L |
12918 | //GCVM_INVALIDATE_ENG10_ACK |
12919 | #define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12920 | #define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 |
12921 | #define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12922 | #define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L |
12923 | //GCVM_INVALIDATE_ENG11_ACK |
12924 | #define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12925 | #define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 |
12926 | #define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12927 | #define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L |
12928 | //GCVM_INVALIDATE_ENG12_ACK |
12929 | #define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12930 | #define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 |
12931 | #define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12932 | #define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L |
12933 | //GCVM_INVALIDATE_ENG13_ACK |
12934 | #define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12935 | #define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 |
12936 | #define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12937 | #define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L |
12938 | //GCVM_INVALIDATE_ENG14_ACK |
12939 | #define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12940 | #define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 |
12941 | #define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12942 | #define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L |
12943 | //GCVM_INVALIDATE_ENG15_ACK |
12944 | #define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12945 | #define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 |
12946 | #define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12947 | #define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L |
12948 | //GCVM_INVALIDATE_ENG16_ACK |
12949 | #define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12950 | #define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 |
12951 | #define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12952 | #define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L |
12953 | //GCVM_INVALIDATE_ENG17_ACK |
12954 | #define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
12955 | #define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 |
12956 | #define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
12957 | #define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L |
12958 | //GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 |
12959 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
12960 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
12961 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
12962 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
12963 | //GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 |
12964 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
12965 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
12966 | //GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 |
12967 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
12968 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
12969 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
12970 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
12971 | //GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 |
12972 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
12973 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
12974 | //GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 |
12975 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
12976 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
12977 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
12978 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
12979 | //GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 |
12980 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
12981 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
12982 | //GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 |
12983 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
12984 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
12985 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
12986 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
12987 | //GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 |
12988 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
12989 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
12990 | //GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 |
12991 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
12992 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
12993 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
12994 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
12995 | //GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 |
12996 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
12997 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
12998 | //GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 |
12999 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13000 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13001 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13002 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13003 | //GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 |
13004 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13005 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13006 | //GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 |
13007 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13008 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13009 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13010 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13011 | //GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 |
13012 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13013 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13014 | //GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 |
13015 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13016 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13017 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13018 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13019 | //GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 |
13020 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13021 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13022 | //GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 |
13023 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13024 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13025 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13026 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13027 | //GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 |
13028 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13029 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13030 | //GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 |
13031 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13032 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13033 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13034 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13035 | //GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 |
13036 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13037 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13038 | //GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 |
13039 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13040 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13041 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13042 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13043 | //GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 |
13044 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13045 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13046 | //GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 |
13047 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13048 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13049 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13050 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13051 | //GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 |
13052 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13053 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13054 | //GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 |
13055 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13056 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13057 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13058 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13059 | //GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 |
13060 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13061 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13062 | //GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 |
13063 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13064 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13065 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13066 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13067 | //GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 |
13068 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13069 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13070 | //GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 |
13071 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13072 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13073 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13074 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13075 | //GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 |
13076 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13077 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13078 | //GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 |
13079 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13080 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13081 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13082 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13083 | //GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 |
13084 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13085 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13086 | //GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 |
13087 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13088 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13089 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13090 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13091 | //GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 |
13092 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13093 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13094 | //GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 |
13095 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
13096 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
13097 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
13098 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
13099 | //GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 |
13100 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
13101 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
13102 | //GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 |
13103 | #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13104 | #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13105 | //GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 |
13106 | #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13107 | #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13108 | //GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 |
13109 | #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13110 | #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13111 | //GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 |
13112 | #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13113 | #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13114 | //GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 |
13115 | #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13116 | #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13117 | //GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 |
13118 | #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13119 | #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13120 | //GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 |
13121 | #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13122 | #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13123 | //GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 |
13124 | #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13125 | #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13126 | //GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 |
13127 | #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13128 | #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13129 | //GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 |
13130 | #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13131 | #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13132 | //GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 |
13133 | #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13134 | #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13135 | //GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 |
13136 | #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13137 | #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13138 | //GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 |
13139 | #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13140 | #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13141 | //GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 |
13142 | #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13143 | #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13144 | //GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 |
13145 | #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13146 | #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13147 | //GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 |
13148 | #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13149 | #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13150 | //GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 |
13151 | #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13152 | #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13153 | //GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 |
13154 | #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13155 | #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13156 | //GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 |
13157 | #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13158 | #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13159 | //GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 |
13160 | #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13161 | #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13162 | //GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 |
13163 | #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13164 | #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13165 | //GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 |
13166 | #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13167 | #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13168 | //GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 |
13169 | #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13170 | #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13171 | //GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 |
13172 | #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13173 | #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13174 | //GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 |
13175 | #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13176 | #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13177 | //GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 |
13178 | #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13179 | #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13180 | //GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 |
13181 | #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13182 | #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13183 | //GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 |
13184 | #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13185 | #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13186 | //GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 |
13187 | #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13188 | #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13189 | //GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 |
13190 | #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13191 | #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13192 | //GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 |
13193 | #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
13194 | #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
13195 | //GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 |
13196 | #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
13197 | #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
13198 | //GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 |
13199 | #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13200 | #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13201 | //GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 |
13202 | #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13203 | #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13204 | //GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 |
13205 | #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13206 | #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13207 | //GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 |
13208 | #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13209 | #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13210 | //GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 |
13211 | #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13212 | #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13213 | //GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 |
13214 | #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13215 | #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13216 | //GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 |
13217 | #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13218 | #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13219 | //GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 |
13220 | #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13221 | #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13222 | //GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 |
13223 | #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13224 | #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13225 | //GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 |
13226 | #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13227 | #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13228 | //GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 |
13229 | #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13230 | #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13231 | //GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 |
13232 | #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13233 | #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13234 | //GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 |
13235 | #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13236 | #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13237 | //GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 |
13238 | #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13239 | #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13240 | //GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 |
13241 | #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13242 | #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13243 | //GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 |
13244 | #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13245 | #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13246 | //GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 |
13247 | #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13248 | #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13249 | //GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 |
13250 | #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13251 | #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13252 | //GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 |
13253 | #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13254 | #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13255 | //GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 |
13256 | #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13257 | #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13258 | //GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 |
13259 | #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13260 | #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13261 | //GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 |
13262 | #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13263 | #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13264 | //GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 |
13265 | #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13266 | #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13267 | //GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 |
13268 | #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13269 | #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13270 | //GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 |
13271 | #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13272 | #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13273 | //GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 |
13274 | #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13275 | #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13276 | //GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 |
13277 | #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13278 | #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13279 | //GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 |
13280 | #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13281 | #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13282 | //GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 |
13283 | #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13284 | #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13285 | //GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 |
13286 | #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13287 | #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13288 | //GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 |
13289 | #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13290 | #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13291 | //GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 |
13292 | #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13293 | #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13294 | //GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 |
13295 | #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13296 | #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13297 | //GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 |
13298 | #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13299 | #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13300 | //GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 |
13301 | #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13302 | #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13303 | //GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 |
13304 | #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13305 | #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13306 | //GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 |
13307 | #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13308 | #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13309 | //GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 |
13310 | #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13311 | #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13312 | //GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 |
13313 | #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13314 | #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13315 | //GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 |
13316 | #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13317 | #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13318 | //GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 |
13319 | #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13320 | #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13321 | //GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 |
13322 | #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13323 | #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13324 | //GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 |
13325 | #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13326 | #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13327 | //GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 |
13328 | #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13329 | #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13330 | //GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 |
13331 | #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13332 | #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13333 | //GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 |
13334 | #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13335 | #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13336 | //GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 |
13337 | #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13338 | #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13339 | //GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 |
13340 | #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13341 | #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13342 | //GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 |
13343 | #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13344 | #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13345 | //GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 |
13346 | #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13347 | #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13348 | //GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 |
13349 | #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13350 | #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13351 | //GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 |
13352 | #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13353 | #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13354 | //GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 |
13355 | #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13356 | #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13357 | //GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 |
13358 | #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13359 | #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13360 | //GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 |
13361 | #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13362 | #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13363 | //GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 |
13364 | #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13365 | #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13366 | //GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 |
13367 | #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13368 | #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13369 | //GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 |
13370 | #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13371 | #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13372 | //GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 |
13373 | #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13374 | #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13375 | //GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 |
13376 | #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13377 | #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13378 | //GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 |
13379 | #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13380 | #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13381 | //GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 |
13382 | #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13383 | #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13384 | //GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 |
13385 | #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
13386 | #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
13387 | //GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 |
13388 | #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
13389 | #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
13390 | //GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13391 | #define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13392 | #define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13393 | #define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13394 | #define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13395 | #define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13396 | #define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13397 | //GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13398 | #define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13399 | #define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13400 | #define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13401 | #define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13402 | #define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13403 | #define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13404 | //GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13405 | #define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13406 | #define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13407 | #define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13408 | #define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13409 | #define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13410 | #define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13411 | //GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13412 | #define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13413 | #define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13414 | #define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13415 | #define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13416 | #define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13417 | #define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13418 | //GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13419 | #define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13420 | #define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13421 | #define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13422 | #define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13423 | #define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13424 | #define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13425 | //GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13426 | #define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13427 | #define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13428 | #define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13429 | #define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13430 | #define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13431 | #define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13432 | //GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13433 | #define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13434 | #define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13435 | #define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13436 | #define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13437 | #define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13438 | #define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13439 | //GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13440 | #define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13441 | #define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13442 | #define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13443 | #define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13444 | #define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13445 | #define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13446 | //GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13447 | #define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13448 | #define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13449 | #define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13450 | #define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13451 | #define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13452 | #define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13453 | //GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13454 | #define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13455 | #define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13456 | #define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13457 | #define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13458 | #define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13459 | #define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13460 | //GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13461 | #define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13462 | #define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13463 | #define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13464 | #define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13465 | #define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13466 | #define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13467 | //GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13468 | #define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13469 | #define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13470 | #define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13471 | #define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13472 | #define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13473 | #define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13474 | //GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13475 | #define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13476 | #define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13477 | #define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13478 | #define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13479 | #define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13480 | #define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13481 | //GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13482 | #define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13483 | #define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13484 | #define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13485 | #define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13486 | #define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13487 | #define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13488 | //GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13489 | #define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13490 | #define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13491 | #define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13492 | #define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13493 | #define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13494 | #define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13495 | //GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13496 | #define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13497 | #define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13498 | #define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13499 | #define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13500 | #define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13501 | #define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13502 | //GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
13503 | #define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13504 | #define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
13505 | #define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
13506 | #define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13507 | #define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
13508 | #define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
13509 | |
13510 | |
13511 | // addressBlock: gc_gcvmsharedpfdec |
13512 | //GCMC_VM_NB_MMIOBASE |
13513 | #define GCMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 |
13514 | #define GCMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL |
13515 | //GCMC_VM_NB_MMIOLIMIT |
13516 | #define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 |
13517 | #define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL |
13518 | //GCMC_VM_NB_PCI_CTRL |
13519 | #define GCMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 |
13520 | #define GCMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L |
13521 | //GCMC_VM_NB_PCI_ARB |
13522 | #define GCMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 |
13523 | #define GCMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L |
13524 | //GCMC_VM_NB_TOP_OF_DRAM_SLOT1 |
13525 | #define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 |
13526 | #define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L |
13527 | //GCMC_VM_NB_LOWER_TOP_OF_DRAM2 |
13528 | #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 |
13529 | #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 |
13530 | #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L |
13531 | #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L |
13532 | //GCMC_VM_NB_UPPER_TOP_OF_DRAM2 |
13533 | #define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 |
13534 | #define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL |
13535 | //GCMC_VM_FB_OFFSET |
13536 | #define GCMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 |
13537 | #define GCMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL |
13538 | //GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB |
13539 | #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 |
13540 | #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL |
13541 | //GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB |
13542 | #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 |
13543 | #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL |
13544 | //GCMC_VM_STEERING |
13545 | #define GCMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 |
13546 | #define GCMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L |
13547 | //GCMC_SHARED_VIRT_RESET_REQ |
13548 | #define GCMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 |
13549 | #define GCMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f |
13550 | #define GCMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL |
13551 | #define GCMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L |
13552 | //GCMC_MEM_POWER_LS |
13553 | #define GCMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 |
13554 | #define GCMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 |
13555 | #define GCMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL |
13556 | #define GCMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L |
13557 | //GCMC_VM_CACHEABLE_DRAM_ADDRESS_START |
13558 | #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 |
13559 | #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL |
13560 | //GCMC_VM_CACHEABLE_DRAM_ADDRESS_END |
13561 | #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 |
13562 | #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL |
13563 | //GCMC_VM_APT_CNTL |
13564 | #define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 |
13565 | #define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 |
13566 | #define GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 |
13567 | #define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L |
13568 | #define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L |
13569 | #define GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL |
13570 | //GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL |
13571 | #define GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 |
13572 | #define GCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L |
13573 | //GCMC_VM_LOCAL_HBM_ADDRESS_START |
13574 | #define GCMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 |
13575 | #define GCMC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL |
13576 | //GCMC_VM_LOCAL_HBM_ADDRESS_END |
13577 | #define GCMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 |
13578 | #define GCMC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL |
13579 | //GCMC_SHARED_ACTIVE_FCN_ID |
13580 | #define GCMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
13581 | #define GCMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f |
13582 | #define GCMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL |
13583 | #define GCMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L |
13584 | //GCMC_SHARED_VIRT_RESET_REQ2 |
13585 | #define GCMC_SHARED_VIRT_RESET_REQ2__VF__SHIFT 0x0 |
13586 | #define GCMC_SHARED_VIRT_RESET_REQ2__VF_MASK 0x00000001L |
13587 | //GCMC_VM_XGMI_LFB_CNTL |
13588 | #define GCMC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 |
13589 | #define GCMC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 |
13590 | #define GCMC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL |
13591 | #define GCMC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L |
13592 | //GCMC_VM_XGMI_LFB_SIZE |
13593 | #define GCMC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 |
13594 | #define GCMC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL |
13595 | //GCMC_VM_FB_NOALLOC_CNTL |
13596 | #define GCMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT 0x0 |
13597 | #define GCMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT 0x1 |
13598 | #define GCMC_VM_FB_NOALLOC_CNTL__FB_NOALLOC_WALKER_FETCH__SHIFT 0x2 |
13599 | #define GCMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK 0x00000001L |
13600 | #define GCMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK 0x00000002L |
13601 | #define GCMC_VM_FB_NOALLOC_CNTL__FB_NOALLOC_WALKER_FETCH_MASK 0x00000004L |
13602 | //GCUTCL2_HARVEST_BYPASS_GROUPS |
13603 | #define GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 |
13604 | #define GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL |
13605 | |
13606 | |
13607 | // addressBlock: gc_gcvmsharedvcdec |
13608 | //GCMC_VM_FB_LOCATION_BASE |
13609 | #define GCMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 |
13610 | #define GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL |
13611 | //GCMC_VM_FB_LOCATION_TOP |
13612 | #define GCMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 |
13613 | #define GCMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL |
13614 | //GCMC_VM_AGP_TOP |
13615 | #define GCMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 |
13616 | #define GCMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL |
13617 | //GCMC_VM_AGP_BOT |
13618 | #define GCMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 |
13619 | #define GCMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL |
13620 | //GCMC_VM_AGP_BASE |
13621 | #define GCMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 |
13622 | #define GCMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL |
13623 | //GCMC_VM_SYSTEM_APERTURE_LOW_ADDR |
13624 | #define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 |
13625 | #define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL |
13626 | //GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR |
13627 | #define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 |
13628 | #define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL |
13629 | //GCMC_VM_MX_L1_TLB_CNTL |
13630 | #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 |
13631 | #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 |
13632 | #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 |
13633 | #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 |
13634 | #define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 |
13635 | #define GCMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb |
13636 | #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L |
13637 | #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L |
13638 | #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L |
13639 | #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L |
13640 | #define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L |
13641 | #define GCMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L |
13642 | |
13643 | |
13644 | // addressBlock: gc_gceadec |
13645 | //GCEA_DRAM_RD_CLI2GRP_MAP0 |
13646 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
13647 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
13648 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
13649 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
13650 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
13651 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
13652 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
13653 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
13654 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
13655 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
13656 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
13657 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
13658 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
13659 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
13660 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
13661 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
13662 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
13663 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
13664 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
13665 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
13666 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
13667 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
13668 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
13669 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
13670 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
13671 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
13672 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
13673 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
13674 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
13675 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
13676 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
13677 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
13678 | //GCEA_DRAM_RD_CLI2GRP_MAP1 |
13679 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
13680 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
13681 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
13682 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
13683 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
13684 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
13685 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
13686 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
13687 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
13688 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
13689 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
13690 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
13691 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
13692 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
13693 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
13694 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
13695 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
13696 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
13697 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
13698 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
13699 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
13700 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
13701 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
13702 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
13703 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
13704 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
13705 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
13706 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
13707 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
13708 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
13709 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
13710 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
13711 | //GCEA_DRAM_WR_CLI2GRP_MAP0 |
13712 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
13713 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
13714 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
13715 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
13716 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
13717 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
13718 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
13719 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
13720 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
13721 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
13722 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
13723 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
13724 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
13725 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
13726 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
13727 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
13728 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
13729 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
13730 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
13731 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
13732 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
13733 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
13734 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
13735 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
13736 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
13737 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
13738 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
13739 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
13740 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
13741 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
13742 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
13743 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
13744 | //GCEA_DRAM_WR_CLI2GRP_MAP1 |
13745 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
13746 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
13747 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
13748 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
13749 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
13750 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
13751 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
13752 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
13753 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
13754 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
13755 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
13756 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
13757 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
13758 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
13759 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
13760 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
13761 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
13762 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
13763 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
13764 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
13765 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
13766 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
13767 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
13768 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
13769 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
13770 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
13771 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
13772 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
13773 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
13774 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
13775 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
13776 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
13777 | //GCEA_DRAM_RD_GRP2VC_MAP |
13778 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
13779 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
13780 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
13781 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
13782 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
13783 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
13784 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
13785 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
13786 | //GCEA_DRAM_WR_GRP2VC_MAP |
13787 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
13788 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
13789 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
13790 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
13791 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
13792 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
13793 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
13794 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
13795 | //GCEA_DRAM_RD_LAZY |
13796 | #define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
13797 | #define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
13798 | #define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
13799 | #define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
13800 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
13801 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
13802 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
13803 | #define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
13804 | #define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
13805 | #define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
13806 | #define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
13807 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
13808 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
13809 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
13810 | //GCEA_DRAM_WR_LAZY |
13811 | #define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
13812 | #define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
13813 | #define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
13814 | #define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
13815 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
13816 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
13817 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
13818 | #define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
13819 | #define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
13820 | #define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
13821 | #define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
13822 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
13823 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
13824 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
13825 | //GCEA_DRAM_RD_CAM_CNTL |
13826 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
13827 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
13828 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
13829 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
13830 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
13831 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
13832 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
13833 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
13834 | #define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
13835 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
13836 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
13837 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
13838 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
13839 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
13840 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
13841 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
13842 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
13843 | #define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
13844 | //GCEA_DRAM_WR_CAM_CNTL |
13845 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
13846 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
13847 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
13848 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
13849 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
13850 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
13851 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
13852 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
13853 | #define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
13854 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
13855 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
13856 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
13857 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
13858 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
13859 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
13860 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
13861 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
13862 | #define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
13863 | //GCEA_DRAM_PAGE_BURST |
13864 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
13865 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
13866 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
13867 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
13868 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
13869 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
13870 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
13871 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
13872 | //GCEA_DRAM_RD_PRI_AGE |
13873 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
13874 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
13875 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
13876 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
13877 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
13878 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
13879 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
13880 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
13881 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
13882 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
13883 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
13884 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
13885 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
13886 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
13887 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
13888 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
13889 | //GCEA_DRAM_WR_PRI_AGE |
13890 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
13891 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
13892 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
13893 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
13894 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
13895 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
13896 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
13897 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
13898 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
13899 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
13900 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
13901 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
13902 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
13903 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
13904 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
13905 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
13906 | //GCEA_DRAM_RD_PRI_QUEUING |
13907 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
13908 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
13909 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
13910 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
13911 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
13912 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
13913 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
13914 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
13915 | //GCEA_DRAM_WR_PRI_QUEUING |
13916 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
13917 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
13918 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
13919 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
13920 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
13921 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
13922 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
13923 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
13924 | //GCEA_DRAM_RD_PRI_FIXED |
13925 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
13926 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
13927 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
13928 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
13929 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
13930 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
13931 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
13932 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
13933 | //GCEA_DRAM_WR_PRI_FIXED |
13934 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
13935 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
13936 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
13937 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
13938 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
13939 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
13940 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
13941 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
13942 | //GCEA_DRAM_RD_PRI_URGENCY |
13943 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
13944 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
13945 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
13946 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
13947 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
13948 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
13949 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
13950 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
13951 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
13952 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
13953 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
13954 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
13955 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
13956 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
13957 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
13958 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
13959 | //GCEA_DRAM_WR_PRI_URGENCY |
13960 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
13961 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
13962 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
13963 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
13964 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
13965 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
13966 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
13967 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
13968 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
13969 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
13970 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
13971 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
13972 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
13973 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
13974 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
13975 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
13976 | //GCEA_DRAM_RD_PRI_QUANT_PRI1 |
13977 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
13978 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
13979 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
13980 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
13981 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
13982 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
13983 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
13984 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
13985 | //GCEA_DRAM_RD_PRI_QUANT_PRI2 |
13986 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
13987 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
13988 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
13989 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
13990 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
13991 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
13992 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
13993 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
13994 | //GCEA_DRAM_RD_PRI_QUANT_PRI3 |
13995 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
13996 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
13997 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
13998 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
13999 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
14000 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14001 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14002 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
14003 | //GCEA_DRAM_WR_PRI_QUANT_PRI1 |
14004 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
14005 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
14006 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
14007 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
14008 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
14009 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14010 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14011 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
14012 | //GCEA_DRAM_WR_PRI_QUANT_PRI2 |
14013 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
14014 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
14015 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
14016 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
14017 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
14018 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14019 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14020 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
14021 | //GCEA_DRAM_WR_PRI_QUANT_PRI3 |
14022 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
14023 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
14024 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
14025 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
14026 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
14027 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14028 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14029 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
14030 | //GCEA_IO_RD_CLI2GRP_MAP0 |
14031 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
14032 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
14033 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
14034 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
14035 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
14036 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
14037 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
14038 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
14039 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
14040 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
14041 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
14042 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
14043 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
14044 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
14045 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
14046 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
14047 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
14048 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
14049 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
14050 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
14051 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
14052 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
14053 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
14054 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
14055 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
14056 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
14057 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
14058 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
14059 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
14060 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
14061 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
14062 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
14063 | //GCEA_IO_RD_CLI2GRP_MAP1 |
14064 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
14065 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
14066 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
14067 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
14068 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
14069 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
14070 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
14071 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
14072 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
14073 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
14074 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
14075 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
14076 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
14077 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
14078 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
14079 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
14080 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
14081 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
14082 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
14083 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
14084 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
14085 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
14086 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
14087 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
14088 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
14089 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
14090 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
14091 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
14092 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
14093 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
14094 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
14095 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
14096 | //GCEA_IO_WR_CLI2GRP_MAP0 |
14097 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
14098 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
14099 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
14100 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
14101 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
14102 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
14103 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
14104 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
14105 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
14106 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
14107 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
14108 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
14109 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
14110 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
14111 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
14112 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
14113 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
14114 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
14115 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
14116 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
14117 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
14118 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
14119 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
14120 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
14121 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
14122 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
14123 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
14124 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
14125 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
14126 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
14127 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
14128 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
14129 | //GCEA_IO_WR_CLI2GRP_MAP1 |
14130 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
14131 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
14132 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
14133 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
14134 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
14135 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
14136 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
14137 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
14138 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
14139 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
14140 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
14141 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
14142 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
14143 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
14144 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
14145 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
14146 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
14147 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
14148 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
14149 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
14150 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
14151 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
14152 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
14153 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
14154 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
14155 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
14156 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
14157 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
14158 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
14159 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
14160 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
14161 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
14162 | //GCEA_IO_RD_COMBINE_FLUSH |
14163 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
14164 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
14165 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
14166 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
14167 | #define GCEA_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 |
14168 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
14169 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
14170 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
14171 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
14172 | #define GCEA_IO_RD_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L |
14173 | //GCEA_IO_WR_COMBINE_FLUSH |
14174 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
14175 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
14176 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
14177 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
14178 | #define GCEA_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY__SHIFT 0x10 |
14179 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
14180 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
14181 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
14182 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
14183 | #define GCEA_IO_WR_COMBINE_FLUSH__FORWARD_COMB_ONLY_MASK 0x00010000L |
14184 | //GCEA_IO_GROUP_BURST |
14185 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 |
14186 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 |
14187 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 |
14188 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 |
14189 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
14190 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
14191 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
14192 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
14193 | //GCEA_IO_RD_PRI_AGE |
14194 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
14195 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
14196 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
14197 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
14198 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
14199 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
14200 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
14201 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
14202 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
14203 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
14204 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
14205 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
14206 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
14207 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
14208 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
14209 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
14210 | //GCEA_IO_WR_PRI_AGE |
14211 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
14212 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
14213 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
14214 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
14215 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
14216 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
14217 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
14218 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
14219 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
14220 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
14221 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
14222 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
14223 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
14224 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
14225 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
14226 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
14227 | //GCEA_IO_RD_PRI_QUEUING |
14228 | #define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
14229 | #define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
14230 | #define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
14231 | #define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
14232 | #define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
14233 | #define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
14234 | #define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
14235 | #define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
14236 | //GCEA_IO_WR_PRI_QUEUING |
14237 | #define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
14238 | #define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
14239 | #define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
14240 | #define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
14241 | #define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
14242 | #define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
14243 | #define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
14244 | #define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
14245 | //GCEA_IO_RD_PRI_FIXED |
14246 | #define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
14247 | #define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
14248 | #define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
14249 | #define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
14250 | #define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
14251 | #define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
14252 | #define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
14253 | #define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
14254 | //GCEA_IO_WR_PRI_FIXED |
14255 | #define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
14256 | #define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
14257 | #define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
14258 | #define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
14259 | #define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
14260 | #define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
14261 | #define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
14262 | #define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
14263 | //GCEA_IO_RD_PRI_URGENCY |
14264 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
14265 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
14266 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
14267 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
14268 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
14269 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
14270 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
14271 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
14272 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
14273 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
14274 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
14275 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
14276 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
14277 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
14278 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
14279 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
14280 | //GCEA_IO_WR_PRI_URGENCY |
14281 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
14282 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
14283 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
14284 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
14285 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
14286 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
14287 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
14288 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
14289 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
14290 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
14291 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
14292 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
14293 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
14294 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
14295 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
14296 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
14297 | //GCEA_IO_RD_PRI_URGENCY_MASKING |
14298 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
14299 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
14300 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
14301 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
14302 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
14303 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
14304 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
14305 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
14306 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
14307 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
14308 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
14309 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
14310 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
14311 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
14312 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
14313 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
14314 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
14315 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
14316 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
14317 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
14318 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
14319 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
14320 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
14321 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
14322 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
14323 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
14324 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
14325 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
14326 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
14327 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
14328 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
14329 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
14330 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
14331 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
14332 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
14333 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
14334 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
14335 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
14336 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
14337 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
14338 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
14339 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
14340 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
14341 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
14342 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
14343 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
14344 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
14345 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
14346 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
14347 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
14348 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
14349 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
14350 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
14351 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
14352 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
14353 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
14354 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
14355 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
14356 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
14357 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
14358 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
14359 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
14360 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
14361 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
14362 | //GCEA_IO_WR_PRI_URGENCY_MASKING |
14363 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
14364 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
14365 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
14366 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
14367 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
14368 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
14369 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
14370 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
14371 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
14372 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
14373 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
14374 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
14375 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
14376 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
14377 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
14378 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
14379 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
14380 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
14381 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
14382 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
14383 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
14384 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
14385 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
14386 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
14387 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
14388 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
14389 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
14390 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
14391 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
14392 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
14393 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
14394 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
14395 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
14396 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
14397 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
14398 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
14399 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
14400 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
14401 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
14402 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
14403 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
14404 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
14405 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
14406 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
14407 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
14408 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
14409 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
14410 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
14411 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
14412 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
14413 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
14414 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
14415 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
14416 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
14417 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
14418 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
14419 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
14420 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
14421 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
14422 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
14423 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
14424 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
14425 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
14426 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
14427 | //GCEA_IO_RD_PRI_QUANT_PRI1 |
14428 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
14429 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
14430 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
14431 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
14432 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
14433 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14434 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14435 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
14436 | //GCEA_IO_RD_PRI_QUANT_PRI2 |
14437 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
14438 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
14439 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
14440 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
14441 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
14442 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14443 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14444 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
14445 | //GCEA_IO_RD_PRI_QUANT_PRI3 |
14446 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
14447 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
14448 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
14449 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
14450 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
14451 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14452 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14453 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
14454 | //GCEA_IO_WR_PRI_QUANT_PRI1 |
14455 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
14456 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
14457 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
14458 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
14459 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
14460 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14461 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14462 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
14463 | //GCEA_IO_WR_PRI_QUANT_PRI2 |
14464 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
14465 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
14466 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
14467 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
14468 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
14469 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14470 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14471 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
14472 | //GCEA_IO_WR_PRI_QUANT_PRI3 |
14473 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
14474 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
14475 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
14476 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
14477 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
14478 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
14479 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
14480 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
14481 | |
14482 | |
14483 | // addressBlock: gc_tcdec |
14484 | //TCP_INVALIDATE |
14485 | #define TCP_INVALIDATE__START__SHIFT 0x0 |
14486 | #define TCP_INVALIDATE__START_MASK 0x00000001L |
14487 | //TCP_STATUS |
14488 | #define TCP_STATUS__TCP_BUSY__SHIFT 0x0 |
14489 | #define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 |
14490 | #define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 |
14491 | #define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 |
14492 | #define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 |
14493 | #define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 |
14494 | #define TCP_STATUS__READ_BUSY__SHIFT 0x6 |
14495 | #define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 |
14496 | #define TCP_STATUS__VM_BUSY__SHIFT 0x8 |
14497 | #define TCP_STATUS__MEMIF_BUSY__SHIFT 0x9 |
14498 | #define TCP_STATUS__GCR_BUSY__SHIFT 0xa |
14499 | #define TCP_STATUS__OFIFO_BUSY__SHIFT 0xb |
14500 | #define TCP_STATUS__OFIFO_QUEUE_BUSY__SHIFT 0xc |
14501 | #define TCP_STATUS__TCP_BUSY_MASK 0x00000001L |
14502 | #define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L |
14503 | #define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L |
14504 | #define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L |
14505 | #define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L |
14506 | #define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L |
14507 | #define TCP_STATUS__READ_BUSY_MASK 0x00000040L |
14508 | #define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L |
14509 | #define TCP_STATUS__VM_BUSY_MASK 0x00000100L |
14510 | #define TCP_STATUS__MEMIF_BUSY_MASK 0x00000200L |
14511 | #define TCP_STATUS__GCR_BUSY_MASK 0x00000400L |
14512 | #define TCP_STATUS__OFIFO_BUSY_MASK 0x00000800L |
14513 | #define TCP_STATUS__OFIFO_QUEUE_BUSY_MASK 0x00003000L |
14514 | //TCP_EDC_CNT |
14515 | #define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0 |
14516 | #define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8 |
14517 | #define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10 |
14518 | #define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL |
14519 | #define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L |
14520 | #define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L |
14521 | //TCI_STATUS |
14522 | #define TCI_STATUS__TCI_BUSY__SHIFT 0x0 |
14523 | #define TCI_STATUS__TCI_BUSY_MASK 0x00000001L |
14524 | //TCI_CNTL_1 |
14525 | #define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 |
14526 | #define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 |
14527 | #define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 |
14528 | #define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL |
14529 | #define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L |
14530 | #define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L |
14531 | //TCI_CNTL_2 |
14532 | #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 |
14533 | #define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 |
14534 | #define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L |
14535 | #define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL |
14536 | |
14537 | |
14538 | // addressBlock: gc_shdec |
14539 | //SPI_SHADER_PGM_RSRC4_PS |
14540 | #define SPI_SHADER_PGM_RSRC4_PS__CU_EN__SHIFT 0x0 |
14541 | #define SPI_SHADER_PGM_RSRC4_PS__CU_EN_MASK 0x0000FFFFL |
14542 | //SPI_SHADER_PGM_CHKSUM_PS |
14543 | #define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM__SHIFT 0x0 |
14544 | #define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM_MASK 0xFFFFFFFFL |
14545 | //SPI_SHADER_PGM_RSRC3_PS |
14546 | #define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 |
14547 | #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 |
14548 | #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 |
14549 | #define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL |
14550 | #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L |
14551 | #define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L |
14552 | //SPI_SHADER_PGM_LO_PS |
14553 | #define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 |
14554 | #define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL |
14555 | //SPI_SHADER_PGM_HI_PS |
14556 | #define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 |
14557 | #define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL |
14558 | //SPI_SHADER_PGM_RSRC1_PS |
14559 | #define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 |
14560 | #define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 |
14561 | #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa |
14562 | #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc |
14563 | #define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 |
14564 | #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 |
14565 | #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 |
14566 | #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 |
14567 | #define SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED__SHIFT 0x19 |
14568 | #define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS__SHIFT 0x1a |
14569 | #define SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX__SHIFT 0x1b |
14570 | #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d |
14571 | #define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL |
14572 | #define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L |
14573 | #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L |
14574 | #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L |
14575 | #define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L |
14576 | #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L |
14577 | #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L |
14578 | #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L |
14579 | #define SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED_MASK 0x02000000L |
14580 | #define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS_MASK 0x04000000L |
14581 | #define SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX_MASK 0x08000000L |
14582 | #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L |
14583 | //SPI_SHADER_PGM_RSRC2_PS |
14584 | #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 |
14585 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 |
14586 | #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 |
14587 | #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 |
14588 | #define 0x8 |
14589 | #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 |
14590 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19 |
14591 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a |
14592 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1b |
14593 | #define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT__SHIFT 0x1c |
14594 | #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L |
14595 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL |
14596 | #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L |
14597 | #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L |
14598 | #define 0x0000FF00L |
14599 | #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L |
14600 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L |
14601 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L |
14602 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x08000000L |
14603 | #define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT_MASK 0xF0000000L |
14604 | //SPI_SHADER_USER_DATA_PS_0 |
14605 | #define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 |
14606 | #define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL |
14607 | //SPI_SHADER_USER_DATA_PS_1 |
14608 | #define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 |
14609 | #define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL |
14610 | //SPI_SHADER_USER_DATA_PS_2 |
14611 | #define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 |
14612 | #define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL |
14613 | //SPI_SHADER_USER_DATA_PS_3 |
14614 | #define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 |
14615 | #define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL |
14616 | //SPI_SHADER_USER_DATA_PS_4 |
14617 | #define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 |
14618 | #define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL |
14619 | //SPI_SHADER_USER_DATA_PS_5 |
14620 | #define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 |
14621 | #define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL |
14622 | //SPI_SHADER_USER_DATA_PS_6 |
14623 | #define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 |
14624 | #define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL |
14625 | //SPI_SHADER_USER_DATA_PS_7 |
14626 | #define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 |
14627 | #define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL |
14628 | //SPI_SHADER_USER_DATA_PS_8 |
14629 | #define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 |
14630 | #define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL |
14631 | //SPI_SHADER_USER_DATA_PS_9 |
14632 | #define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 |
14633 | #define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL |
14634 | //SPI_SHADER_USER_DATA_PS_10 |
14635 | #define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 |
14636 | #define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL |
14637 | //SPI_SHADER_USER_DATA_PS_11 |
14638 | #define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 |
14639 | #define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL |
14640 | //SPI_SHADER_USER_DATA_PS_12 |
14641 | #define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 |
14642 | #define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL |
14643 | //SPI_SHADER_USER_DATA_PS_13 |
14644 | #define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 |
14645 | #define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL |
14646 | //SPI_SHADER_USER_DATA_PS_14 |
14647 | #define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 |
14648 | #define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL |
14649 | //SPI_SHADER_USER_DATA_PS_15 |
14650 | #define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 |
14651 | #define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL |
14652 | //SPI_SHADER_USER_DATA_PS_16 |
14653 | #define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0 |
14654 | #define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL |
14655 | //SPI_SHADER_USER_DATA_PS_17 |
14656 | #define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0 |
14657 | #define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL |
14658 | //SPI_SHADER_USER_DATA_PS_18 |
14659 | #define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0 |
14660 | #define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL |
14661 | //SPI_SHADER_USER_DATA_PS_19 |
14662 | #define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0 |
14663 | #define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL |
14664 | //SPI_SHADER_USER_DATA_PS_20 |
14665 | #define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0 |
14666 | #define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL |
14667 | //SPI_SHADER_USER_DATA_PS_21 |
14668 | #define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0 |
14669 | #define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL |
14670 | //SPI_SHADER_USER_DATA_PS_22 |
14671 | #define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0 |
14672 | #define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL |
14673 | //SPI_SHADER_USER_DATA_PS_23 |
14674 | #define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0 |
14675 | #define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL |
14676 | //SPI_SHADER_USER_DATA_PS_24 |
14677 | #define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0 |
14678 | #define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL |
14679 | //SPI_SHADER_USER_DATA_PS_25 |
14680 | #define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0 |
14681 | #define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL |
14682 | //SPI_SHADER_USER_DATA_PS_26 |
14683 | #define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0 |
14684 | #define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL |
14685 | //SPI_SHADER_USER_DATA_PS_27 |
14686 | #define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0 |
14687 | #define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL |
14688 | //SPI_SHADER_USER_DATA_PS_28 |
14689 | #define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0 |
14690 | #define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL |
14691 | //SPI_SHADER_USER_DATA_PS_29 |
14692 | #define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0 |
14693 | #define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL |
14694 | //SPI_SHADER_USER_DATA_PS_30 |
14695 | #define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0 |
14696 | #define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL |
14697 | //SPI_SHADER_USER_DATA_PS_31 |
14698 | #define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0 |
14699 | #define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL |
14700 | //SPI_SHADER_REQ_CTRL_PS |
14701 | #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN__SHIFT 0x0 |
14702 | #define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 |
14703 | #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 |
14704 | #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 |
14705 | #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa |
14706 | #define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf |
14707 | #define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN__SHIFT 0x10 |
14708 | #define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 |
14709 | #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN_MASK 0x00000001L |
14710 | #define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL |
14711 | #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L |
14712 | #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L |
14713 | #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L |
14714 | #define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L |
14715 | #define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN_MASK 0x00010000L |
14716 | #define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L |
14717 | //SPI_SHADER_USER_ACCUM_PS_0 |
14718 | #define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION__SHIFT 0x0 |
14719 | #define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION_MASK 0x0000007FL |
14720 | //SPI_SHADER_USER_ACCUM_PS_1 |
14721 | #define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION__SHIFT 0x0 |
14722 | #define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION_MASK 0x0000007FL |
14723 | //SPI_SHADER_USER_ACCUM_PS_2 |
14724 | #define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION__SHIFT 0x0 |
14725 | #define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION_MASK 0x0000007FL |
14726 | //SPI_SHADER_USER_ACCUM_PS_3 |
14727 | #define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION__SHIFT 0x0 |
14728 | #define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION_MASK 0x0000007FL |
14729 | //SPI_SHADER_PGM_RSRC4_VS |
14730 | #define SPI_SHADER_PGM_RSRC4_VS__CU_EN__SHIFT 0x0 |
14731 | #define SPI_SHADER_PGM_RSRC4_VS__CU_EN_MASK 0x0000FFFFL |
14732 | //SPI_SHADER_PGM_CHKSUM_VS |
14733 | #define SPI_SHADER_PGM_CHKSUM_VS__CHECKSUM__SHIFT 0x0 |
14734 | #define SPI_SHADER_PGM_CHKSUM_VS__CHECKSUM_MASK 0xFFFFFFFFL |
14735 | //SPI_SHADER_PGM_RSRC3_VS |
14736 | #define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 |
14737 | #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 |
14738 | #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 |
14739 | #define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL |
14740 | #define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L |
14741 | #define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L |
14742 | //SPI_SHADER_LATE_ALLOC_VS |
14743 | #define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 |
14744 | #define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL |
14745 | //SPI_SHADER_PGM_LO_VS |
14746 | #define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 |
14747 | #define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL |
14748 | //SPI_SHADER_PGM_HI_VS |
14749 | #define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 |
14750 | #define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL |
14751 | //SPI_SHADER_PGM_RSRC1_VS |
14752 | #define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 |
14753 | #define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 |
14754 | #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa |
14755 | #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc |
14756 | #define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 |
14757 | #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 |
14758 | #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 |
14759 | #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 |
14760 | #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a |
14761 | #define SPI_SHADER_PGM_RSRC1_VS__MEM_ORDERED__SHIFT 0x1b |
14762 | #define SPI_SHADER_PGM_RSRC1_VS__FWD_PROGRESS__SHIFT 0x1c |
14763 | #define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f |
14764 | #define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL |
14765 | #define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L |
14766 | #define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L |
14767 | #define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L |
14768 | #define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L |
14769 | #define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L |
14770 | #define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L |
14771 | #define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L |
14772 | #define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L |
14773 | #define SPI_SHADER_PGM_RSRC1_VS__MEM_ORDERED_MASK 0x08000000L |
14774 | #define SPI_SHADER_PGM_RSRC1_VS__FWD_PROGRESS_MASK 0x10000000L |
14775 | #define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L |
14776 | //SPI_SHADER_PGM_RSRC2_VS |
14777 | #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 |
14778 | #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 |
14779 | #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 |
14780 | #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 |
14781 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 |
14782 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 |
14783 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa |
14784 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb |
14785 | #define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc |
14786 | #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd |
14787 | #define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16 |
14788 | #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18 |
14789 | #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1b |
14790 | #define SPI_SHADER_PGM_RSRC2_VS__SHARED_VGPR_CNT__SHIFT 0x1c |
14791 | #define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L |
14792 | #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL |
14793 | #define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L |
14794 | #define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L |
14795 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L |
14796 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L |
14797 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L |
14798 | #define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L |
14799 | #define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L |
14800 | #define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L |
14801 | #define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L |
14802 | #define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L |
14803 | #define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x08000000L |
14804 | #define SPI_SHADER_PGM_RSRC2_VS__SHARED_VGPR_CNT_MASK 0xF0000000L |
14805 | //SPI_SHADER_USER_DATA_VS_0 |
14806 | #define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 |
14807 | #define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL |
14808 | //SPI_SHADER_USER_DATA_VS_1 |
14809 | #define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 |
14810 | #define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL |
14811 | //SPI_SHADER_USER_DATA_VS_2 |
14812 | #define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 |
14813 | #define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL |
14814 | //SPI_SHADER_USER_DATA_VS_3 |
14815 | #define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 |
14816 | #define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL |
14817 | //SPI_SHADER_USER_DATA_VS_4 |
14818 | #define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 |
14819 | #define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL |
14820 | //SPI_SHADER_USER_DATA_VS_5 |
14821 | #define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 |
14822 | #define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL |
14823 | //SPI_SHADER_USER_DATA_VS_6 |
14824 | #define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 |
14825 | #define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL |
14826 | //SPI_SHADER_USER_DATA_VS_7 |
14827 | #define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 |
14828 | #define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL |
14829 | //SPI_SHADER_USER_DATA_VS_8 |
14830 | #define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 |
14831 | #define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL |
14832 | //SPI_SHADER_USER_DATA_VS_9 |
14833 | #define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 |
14834 | #define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL |
14835 | //SPI_SHADER_USER_DATA_VS_10 |
14836 | #define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 |
14837 | #define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL |
14838 | //SPI_SHADER_USER_DATA_VS_11 |
14839 | #define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 |
14840 | #define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL |
14841 | //SPI_SHADER_USER_DATA_VS_12 |
14842 | #define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 |
14843 | #define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL |
14844 | //SPI_SHADER_USER_DATA_VS_13 |
14845 | #define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 |
14846 | #define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL |
14847 | //SPI_SHADER_USER_DATA_VS_14 |
14848 | #define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 |
14849 | #define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL |
14850 | //SPI_SHADER_USER_DATA_VS_15 |
14851 | #define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 |
14852 | #define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL |
14853 | //SPI_SHADER_USER_DATA_VS_16 |
14854 | #define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0 |
14855 | #define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL |
14856 | //SPI_SHADER_USER_DATA_VS_17 |
14857 | #define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0 |
14858 | #define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL |
14859 | //SPI_SHADER_USER_DATA_VS_18 |
14860 | #define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0 |
14861 | #define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL |
14862 | //SPI_SHADER_USER_DATA_VS_19 |
14863 | #define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0 |
14864 | #define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL |
14865 | //SPI_SHADER_USER_DATA_VS_20 |
14866 | #define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0 |
14867 | #define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL |
14868 | //SPI_SHADER_USER_DATA_VS_21 |
14869 | #define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0 |
14870 | #define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL |
14871 | //SPI_SHADER_USER_DATA_VS_22 |
14872 | #define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0 |
14873 | #define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL |
14874 | //SPI_SHADER_USER_DATA_VS_23 |
14875 | #define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0 |
14876 | #define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL |
14877 | //SPI_SHADER_USER_DATA_VS_24 |
14878 | #define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0 |
14879 | #define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL |
14880 | //SPI_SHADER_USER_DATA_VS_25 |
14881 | #define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0 |
14882 | #define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL |
14883 | //SPI_SHADER_USER_DATA_VS_26 |
14884 | #define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0 |
14885 | #define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL |
14886 | //SPI_SHADER_USER_DATA_VS_27 |
14887 | #define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0 |
14888 | #define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL |
14889 | //SPI_SHADER_USER_DATA_VS_28 |
14890 | #define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0 |
14891 | #define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL |
14892 | //SPI_SHADER_USER_DATA_VS_29 |
14893 | #define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0 |
14894 | #define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL |
14895 | //SPI_SHADER_USER_DATA_VS_30 |
14896 | #define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0 |
14897 | #define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL |
14898 | //SPI_SHADER_USER_DATA_VS_31 |
14899 | #define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0 |
14900 | #define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL |
14901 | //SPI_SHADER_REQ_CTRL_VS |
14902 | #define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_EN__SHIFT 0x0 |
14903 | #define SPI_SHADER_REQ_CTRL_VS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 |
14904 | #define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 |
14905 | #define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 |
14906 | #define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa |
14907 | #define SPI_SHADER_REQ_CTRL_VS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf |
14908 | #define SPI_SHADER_REQ_CTRL_VS__GLOBAL_SCANNING_EN__SHIFT 0x10 |
14909 | #define SPI_SHADER_REQ_CTRL_VS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 |
14910 | #define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_EN_MASK 0x00000001L |
14911 | #define SPI_SHADER_REQ_CTRL_VS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL |
14912 | #define SPI_SHADER_REQ_CTRL_VS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L |
14913 | #define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L |
14914 | #define SPI_SHADER_REQ_CTRL_VS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L |
14915 | #define SPI_SHADER_REQ_CTRL_VS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L |
14916 | #define SPI_SHADER_REQ_CTRL_VS__GLOBAL_SCANNING_EN_MASK 0x00010000L |
14917 | #define SPI_SHADER_REQ_CTRL_VS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L |
14918 | //SPI_SHADER_USER_ACCUM_VS_0 |
14919 | #define SPI_SHADER_USER_ACCUM_VS_0__CONTRIBUTION__SHIFT 0x0 |
14920 | #define SPI_SHADER_USER_ACCUM_VS_0__CONTRIBUTION_MASK 0x0000007FL |
14921 | //SPI_SHADER_USER_ACCUM_VS_1 |
14922 | #define SPI_SHADER_USER_ACCUM_VS_1__CONTRIBUTION__SHIFT 0x0 |
14923 | #define SPI_SHADER_USER_ACCUM_VS_1__CONTRIBUTION_MASK 0x0000007FL |
14924 | //SPI_SHADER_USER_ACCUM_VS_2 |
14925 | #define SPI_SHADER_USER_ACCUM_VS_2__CONTRIBUTION__SHIFT 0x0 |
14926 | #define SPI_SHADER_USER_ACCUM_VS_2__CONTRIBUTION_MASK 0x0000007FL |
14927 | //SPI_SHADER_USER_ACCUM_VS_3 |
14928 | #define SPI_SHADER_USER_ACCUM_VS_3__CONTRIBUTION__SHIFT 0x0 |
14929 | #define SPI_SHADER_USER_ACCUM_VS_3__CONTRIBUTION_MASK 0x0000007FL |
14930 | //SPI_SHADER_PGM_RSRC2_GS_VS |
14931 | #define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0 |
14932 | #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1 |
14933 | #define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6 |
14934 | #define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7 |
14935 | #define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10 |
14936 | #define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12 |
14937 | #define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13 |
14938 | #define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b |
14939 | #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c |
14940 | #define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L |
14941 | #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL |
14942 | #define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L |
14943 | #define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L |
14944 | #define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L |
14945 | #define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L |
14946 | #define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L |
14947 | #define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L |
14948 | #define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L |
14949 | //SPI_SHADER_PGM_CHKSUM_GS |
14950 | #define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM__SHIFT 0x0 |
14951 | #define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM_MASK 0xFFFFFFFFL |
14952 | //SPI_SHADER_PGM_RSRC4_GS |
14953 | #define SPI_SHADER_PGM_RSRC4_GS__CU_EN__SHIFT 0x0 |
14954 | #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x10 |
14955 | #define SPI_SHADER_PGM_RSRC4_GS__CU_EN_MASK 0x0000FFFFL |
14956 | #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x007F0000L |
14957 | //SPI_SHADER_USER_DATA_ADDR_LO_GS |
14958 | #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0 |
14959 | #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL |
14960 | //SPI_SHADER_USER_DATA_ADDR_HI_GS |
14961 | #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0 |
14962 | #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL |
14963 | //SPI_SHADER_PGM_LO_ES_GS |
14964 | #define SPI_SHADER_PGM_LO_ES_GS__MEM_BASE__SHIFT 0x0 |
14965 | #define SPI_SHADER_PGM_LO_ES_GS__MEM_BASE_MASK 0xFFFFFFFFL |
14966 | //SPI_SHADER_PGM_HI_ES_GS |
14967 | #define SPI_SHADER_PGM_HI_ES_GS__MEM_BASE__SHIFT 0x0 |
14968 | #define SPI_SHADER_PGM_HI_ES_GS__MEM_BASE_MASK 0xFFL |
14969 | //SPI_SHADER_PGM_RSRC3_GS |
14970 | #define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 |
14971 | #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 |
14972 | #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 |
14973 | #define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a |
14974 | #define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL |
14975 | #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L |
14976 | #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L |
14977 | #define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xFC000000L |
14978 | //SPI_SHADER_PGM_LO_GS |
14979 | #define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 |
14980 | #define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL |
14981 | //SPI_SHADER_PGM_HI_GS |
14982 | #define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 |
14983 | #define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL |
14984 | //SPI_SHADER_PGM_RSRC1_GS |
14985 | #define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 |
14986 | #define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 |
14987 | #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa |
14988 | #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc |
14989 | #define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 |
14990 | #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 |
14991 | #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 |
14992 | #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 |
14993 | #define SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED__SHIFT 0x19 |
14994 | #define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS__SHIFT 0x1a |
14995 | #define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE__SHIFT 0x1b |
14996 | #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d |
14997 | #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f |
14998 | #define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL |
14999 | #define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L |
15000 | #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L |
15001 | #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L |
15002 | #define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L |
15003 | #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L |
15004 | #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L |
15005 | #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L |
15006 | #define SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED_MASK 0x02000000L |
15007 | #define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS_MASK 0x04000000L |
15008 | #define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE_MASK 0x08000000L |
15009 | #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L |
15010 | #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L |
15011 | //SPI_SHADER_PGM_RSRC2_GS |
15012 | #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 |
15013 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 |
15014 | #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 |
15015 | #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 |
15016 | #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10 |
15017 | #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12 |
15018 | #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13 |
15019 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1b |
15020 | #define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT__SHIFT 0x1c |
15021 | #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L |
15022 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL |
15023 | #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L |
15024 | #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L |
15025 | #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L |
15026 | #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L |
15027 | #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L |
15028 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x08000000L |
15029 | #define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT_MASK 0xF0000000L |
15030 | //SPI_SHADER_USER_DATA_GS_0 |
15031 | #define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0 |
15032 | #define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xFFFFFFFFL |
15033 | //SPI_SHADER_USER_DATA_GS_1 |
15034 | #define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0 |
15035 | #define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xFFFFFFFFL |
15036 | //SPI_SHADER_USER_DATA_GS_2 |
15037 | #define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0 |
15038 | #define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xFFFFFFFFL |
15039 | //SPI_SHADER_USER_DATA_GS_3 |
15040 | #define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0 |
15041 | #define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xFFFFFFFFL |
15042 | //SPI_SHADER_USER_DATA_GS_4 |
15043 | #define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0 |
15044 | #define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xFFFFFFFFL |
15045 | //SPI_SHADER_USER_DATA_GS_5 |
15046 | #define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0 |
15047 | #define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xFFFFFFFFL |
15048 | //SPI_SHADER_USER_DATA_GS_6 |
15049 | #define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0 |
15050 | #define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xFFFFFFFFL |
15051 | //SPI_SHADER_USER_DATA_GS_7 |
15052 | #define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0 |
15053 | #define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xFFFFFFFFL |
15054 | //SPI_SHADER_USER_DATA_GS_8 |
15055 | #define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0 |
15056 | #define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xFFFFFFFFL |
15057 | //SPI_SHADER_USER_DATA_GS_9 |
15058 | #define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0 |
15059 | #define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xFFFFFFFFL |
15060 | //SPI_SHADER_USER_DATA_GS_10 |
15061 | #define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0 |
15062 | #define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xFFFFFFFFL |
15063 | //SPI_SHADER_USER_DATA_GS_11 |
15064 | #define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0 |
15065 | #define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xFFFFFFFFL |
15066 | //SPI_SHADER_USER_DATA_GS_12 |
15067 | #define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0 |
15068 | #define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xFFFFFFFFL |
15069 | //SPI_SHADER_USER_DATA_GS_13 |
15070 | #define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0 |
15071 | #define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xFFFFFFFFL |
15072 | //SPI_SHADER_USER_DATA_GS_14 |
15073 | #define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0 |
15074 | #define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xFFFFFFFFL |
15075 | //SPI_SHADER_USER_DATA_GS_15 |
15076 | #define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0 |
15077 | #define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xFFFFFFFFL |
15078 | //SPI_SHADER_USER_DATA_GS_16 |
15079 | #define SPI_SHADER_USER_DATA_GS_16__DATA__SHIFT 0x0 |
15080 | #define SPI_SHADER_USER_DATA_GS_16__DATA_MASK 0xFFFFFFFFL |
15081 | //SPI_SHADER_USER_DATA_GS_17 |
15082 | #define SPI_SHADER_USER_DATA_GS_17__DATA__SHIFT 0x0 |
15083 | #define SPI_SHADER_USER_DATA_GS_17__DATA_MASK 0xFFFFFFFFL |
15084 | //SPI_SHADER_USER_DATA_GS_18 |
15085 | #define SPI_SHADER_USER_DATA_GS_18__DATA__SHIFT 0x0 |
15086 | #define SPI_SHADER_USER_DATA_GS_18__DATA_MASK 0xFFFFFFFFL |
15087 | //SPI_SHADER_USER_DATA_GS_19 |
15088 | #define SPI_SHADER_USER_DATA_GS_19__DATA__SHIFT 0x0 |
15089 | #define SPI_SHADER_USER_DATA_GS_19__DATA_MASK 0xFFFFFFFFL |
15090 | //SPI_SHADER_USER_DATA_GS_20 |
15091 | #define SPI_SHADER_USER_DATA_GS_20__DATA__SHIFT 0x0 |
15092 | #define SPI_SHADER_USER_DATA_GS_20__DATA_MASK 0xFFFFFFFFL |
15093 | //SPI_SHADER_USER_DATA_GS_21 |
15094 | #define SPI_SHADER_USER_DATA_GS_21__DATA__SHIFT 0x0 |
15095 | #define SPI_SHADER_USER_DATA_GS_21__DATA_MASK 0xFFFFFFFFL |
15096 | //SPI_SHADER_USER_DATA_GS_22 |
15097 | #define SPI_SHADER_USER_DATA_GS_22__DATA__SHIFT 0x0 |
15098 | #define SPI_SHADER_USER_DATA_GS_22__DATA_MASK 0xFFFFFFFFL |
15099 | //SPI_SHADER_USER_DATA_GS_23 |
15100 | #define SPI_SHADER_USER_DATA_GS_23__DATA__SHIFT 0x0 |
15101 | #define SPI_SHADER_USER_DATA_GS_23__DATA_MASK 0xFFFFFFFFL |
15102 | //SPI_SHADER_USER_DATA_GS_24 |
15103 | #define SPI_SHADER_USER_DATA_GS_24__DATA__SHIFT 0x0 |
15104 | #define SPI_SHADER_USER_DATA_GS_24__DATA_MASK 0xFFFFFFFFL |
15105 | //SPI_SHADER_USER_DATA_GS_25 |
15106 | #define SPI_SHADER_USER_DATA_GS_25__DATA__SHIFT 0x0 |
15107 | #define SPI_SHADER_USER_DATA_GS_25__DATA_MASK 0xFFFFFFFFL |
15108 | //SPI_SHADER_USER_DATA_GS_26 |
15109 | #define SPI_SHADER_USER_DATA_GS_26__DATA__SHIFT 0x0 |
15110 | #define SPI_SHADER_USER_DATA_GS_26__DATA_MASK 0xFFFFFFFFL |
15111 | //SPI_SHADER_USER_DATA_GS_27 |
15112 | #define SPI_SHADER_USER_DATA_GS_27__DATA__SHIFT 0x0 |
15113 | #define SPI_SHADER_USER_DATA_GS_27__DATA_MASK 0xFFFFFFFFL |
15114 | //SPI_SHADER_USER_DATA_GS_28 |
15115 | #define SPI_SHADER_USER_DATA_GS_28__DATA__SHIFT 0x0 |
15116 | #define SPI_SHADER_USER_DATA_GS_28__DATA_MASK 0xFFFFFFFFL |
15117 | //SPI_SHADER_USER_DATA_GS_29 |
15118 | #define SPI_SHADER_USER_DATA_GS_29__DATA__SHIFT 0x0 |
15119 | #define SPI_SHADER_USER_DATA_GS_29__DATA_MASK 0xFFFFFFFFL |
15120 | //SPI_SHADER_USER_DATA_GS_30 |
15121 | #define SPI_SHADER_USER_DATA_GS_30__DATA__SHIFT 0x0 |
15122 | #define SPI_SHADER_USER_DATA_GS_30__DATA_MASK 0xFFFFFFFFL |
15123 | //SPI_SHADER_USER_DATA_GS_31 |
15124 | #define SPI_SHADER_USER_DATA_GS_31__DATA__SHIFT 0x0 |
15125 | #define SPI_SHADER_USER_DATA_GS_31__DATA_MASK 0xFFFFFFFFL |
15126 | //SPI_SHADER_REQ_CTRL_ESGS |
15127 | #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN__SHIFT 0x0 |
15128 | #define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 |
15129 | #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 |
15130 | #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 |
15131 | #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa |
15132 | #define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf |
15133 | #define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN__SHIFT 0x10 |
15134 | #define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 |
15135 | #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN_MASK 0x00000001L |
15136 | #define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL |
15137 | #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L |
15138 | #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L |
15139 | #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L |
15140 | #define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L |
15141 | #define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN_MASK 0x00010000L |
15142 | #define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L |
15143 | //SPI_SHADER_USER_ACCUM_ESGS_0 |
15144 | #define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION__SHIFT 0x0 |
15145 | #define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION_MASK 0x0000007FL |
15146 | //SPI_SHADER_USER_ACCUM_ESGS_1 |
15147 | #define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION__SHIFT 0x0 |
15148 | #define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION_MASK 0x0000007FL |
15149 | //SPI_SHADER_USER_ACCUM_ESGS_2 |
15150 | #define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION__SHIFT 0x0 |
15151 | #define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION_MASK 0x0000007FL |
15152 | //SPI_SHADER_USER_ACCUM_ESGS_3 |
15153 | #define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION__SHIFT 0x0 |
15154 | #define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION_MASK 0x0000007FL |
15155 | //SPI_SHADER_PGM_LO_ES |
15156 | #define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 |
15157 | #define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL |
15158 | //SPI_SHADER_PGM_HI_ES |
15159 | #define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 |
15160 | #define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL |
15161 | //SPI_SHADER_PGM_CHKSUM_HS |
15162 | #define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM__SHIFT 0x0 |
15163 | #define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM_MASK 0xFFFFFFFFL |
15164 | //SPI_SHADER_PGM_RSRC4_HS |
15165 | #define SPI_SHADER_PGM_RSRC4_HS__CU_EN__SHIFT 0x0 |
15166 | #define SPI_SHADER_PGM_RSRC4_HS__CU_EN_MASK 0x0000FFFFL |
15167 | //SPI_SHADER_USER_DATA_ADDR_LO_HS |
15168 | #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0 |
15169 | #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL |
15170 | //SPI_SHADER_USER_DATA_ADDR_HI_HS |
15171 | #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0 |
15172 | #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL |
15173 | //SPI_SHADER_PGM_LO_LS_HS |
15174 | #define SPI_SHADER_PGM_LO_LS_HS__MEM_BASE__SHIFT 0x0 |
15175 | #define SPI_SHADER_PGM_LO_LS_HS__MEM_BASE_MASK 0xFFFFFFFFL |
15176 | //SPI_SHADER_PGM_HI_LS_HS |
15177 | #define SPI_SHADER_PGM_HI_LS_HS__MEM_BASE__SHIFT 0x0 |
15178 | #define SPI_SHADER_PGM_HI_LS_HS__MEM_BASE_MASK 0xFFL |
15179 | //SPI_SHADER_PGM_RSRC3_HS |
15180 | #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 |
15181 | #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 |
15182 | #define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa |
15183 | #define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10 |
15184 | #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL |
15185 | #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L |
15186 | #define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0x0000FC00L |
15187 | #define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L |
15188 | //SPI_SHADER_PGM_LO_HS |
15189 | #define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 |
15190 | #define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL |
15191 | //SPI_SHADER_PGM_HI_HS |
15192 | #define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 |
15193 | #define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL |
15194 | //SPI_SHADER_PGM_RSRC1_HS |
15195 | #define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 |
15196 | #define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 |
15197 | #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa |
15198 | #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc |
15199 | #define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 |
15200 | #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 |
15201 | #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 |
15202 | #define SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED__SHIFT 0x18 |
15203 | #define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS__SHIFT 0x19 |
15204 | #define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE__SHIFT 0x1a |
15205 | #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c |
15206 | #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e |
15207 | #define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL |
15208 | #define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L |
15209 | #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L |
15210 | #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L |
15211 | #define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L |
15212 | #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L |
15213 | #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L |
15214 | #define SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED_MASK 0x01000000L |
15215 | #define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS_MASK 0x02000000L |
15216 | #define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE_MASK 0x04000000L |
15217 | #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L |
15218 | #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L |
15219 | //SPI_SHADER_PGM_RSRC2_HS |
15220 | #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 |
15221 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 |
15222 | #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 |
15223 | #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7 |
15224 | #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8 |
15225 | #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9 |
15226 | #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x12 |
15227 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1b |
15228 | #define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT__SHIFT 0x1c |
15229 | #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L |
15230 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL |
15231 | #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L |
15232 | #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x00000080L |
15233 | #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x00000100L |
15234 | #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0003FE00L |
15235 | #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x07FC0000L |
15236 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x08000000L |
15237 | #define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT_MASK 0xF0000000L |
15238 | //SPI_SHADER_USER_DATA_HS_0 |
15239 | #define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0 |
15240 | #define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xFFFFFFFFL |
15241 | //SPI_SHADER_USER_DATA_HS_1 |
15242 | #define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0 |
15243 | #define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xFFFFFFFFL |
15244 | //SPI_SHADER_USER_DATA_HS_2 |
15245 | #define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0 |
15246 | #define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xFFFFFFFFL |
15247 | //SPI_SHADER_USER_DATA_HS_3 |
15248 | #define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0 |
15249 | #define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xFFFFFFFFL |
15250 | //SPI_SHADER_USER_DATA_HS_4 |
15251 | #define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0 |
15252 | #define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xFFFFFFFFL |
15253 | //SPI_SHADER_USER_DATA_HS_5 |
15254 | #define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0 |
15255 | #define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xFFFFFFFFL |
15256 | //SPI_SHADER_USER_DATA_HS_6 |
15257 | #define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0 |
15258 | #define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xFFFFFFFFL |
15259 | //SPI_SHADER_USER_DATA_HS_7 |
15260 | #define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0 |
15261 | #define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xFFFFFFFFL |
15262 | //SPI_SHADER_USER_DATA_HS_8 |
15263 | #define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0 |
15264 | #define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xFFFFFFFFL |
15265 | //SPI_SHADER_USER_DATA_HS_9 |
15266 | #define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0 |
15267 | #define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xFFFFFFFFL |
15268 | //SPI_SHADER_USER_DATA_HS_10 |
15269 | #define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0 |
15270 | #define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xFFFFFFFFL |
15271 | //SPI_SHADER_USER_DATA_HS_11 |
15272 | #define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0 |
15273 | #define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xFFFFFFFFL |
15274 | //SPI_SHADER_USER_DATA_HS_12 |
15275 | #define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0 |
15276 | #define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xFFFFFFFFL |
15277 | //SPI_SHADER_USER_DATA_HS_13 |
15278 | #define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0 |
15279 | #define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xFFFFFFFFL |
15280 | //SPI_SHADER_USER_DATA_HS_14 |
15281 | #define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0 |
15282 | #define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xFFFFFFFFL |
15283 | //SPI_SHADER_USER_DATA_HS_15 |
15284 | #define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0 |
15285 | #define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xFFFFFFFFL |
15286 | //SPI_SHADER_USER_DATA_HS_16 |
15287 | #define SPI_SHADER_USER_DATA_HS_16__DATA__SHIFT 0x0 |
15288 | #define SPI_SHADER_USER_DATA_HS_16__DATA_MASK 0xFFFFFFFFL |
15289 | //SPI_SHADER_USER_DATA_HS_17 |
15290 | #define SPI_SHADER_USER_DATA_HS_17__DATA__SHIFT 0x0 |
15291 | #define SPI_SHADER_USER_DATA_HS_17__DATA_MASK 0xFFFFFFFFL |
15292 | //SPI_SHADER_USER_DATA_HS_18 |
15293 | #define SPI_SHADER_USER_DATA_HS_18__DATA__SHIFT 0x0 |
15294 | #define SPI_SHADER_USER_DATA_HS_18__DATA_MASK 0xFFFFFFFFL |
15295 | //SPI_SHADER_USER_DATA_HS_19 |
15296 | #define SPI_SHADER_USER_DATA_HS_19__DATA__SHIFT 0x0 |
15297 | #define SPI_SHADER_USER_DATA_HS_19__DATA_MASK 0xFFFFFFFFL |
15298 | //SPI_SHADER_USER_DATA_HS_20 |
15299 | #define SPI_SHADER_USER_DATA_HS_20__DATA__SHIFT 0x0 |
15300 | #define SPI_SHADER_USER_DATA_HS_20__DATA_MASK 0xFFFFFFFFL |
15301 | //SPI_SHADER_USER_DATA_HS_21 |
15302 | #define SPI_SHADER_USER_DATA_HS_21__DATA__SHIFT 0x0 |
15303 | #define SPI_SHADER_USER_DATA_HS_21__DATA_MASK 0xFFFFFFFFL |
15304 | //SPI_SHADER_USER_DATA_HS_22 |
15305 | #define SPI_SHADER_USER_DATA_HS_22__DATA__SHIFT 0x0 |
15306 | #define SPI_SHADER_USER_DATA_HS_22__DATA_MASK 0xFFFFFFFFL |
15307 | //SPI_SHADER_USER_DATA_HS_23 |
15308 | #define SPI_SHADER_USER_DATA_HS_23__DATA__SHIFT 0x0 |
15309 | #define SPI_SHADER_USER_DATA_HS_23__DATA_MASK 0xFFFFFFFFL |
15310 | //SPI_SHADER_USER_DATA_HS_24 |
15311 | #define SPI_SHADER_USER_DATA_HS_24__DATA__SHIFT 0x0 |
15312 | #define SPI_SHADER_USER_DATA_HS_24__DATA_MASK 0xFFFFFFFFL |
15313 | //SPI_SHADER_USER_DATA_HS_25 |
15314 | #define SPI_SHADER_USER_DATA_HS_25__DATA__SHIFT 0x0 |
15315 | #define SPI_SHADER_USER_DATA_HS_25__DATA_MASK 0xFFFFFFFFL |
15316 | //SPI_SHADER_USER_DATA_HS_26 |
15317 | #define SPI_SHADER_USER_DATA_HS_26__DATA__SHIFT 0x0 |
15318 | #define SPI_SHADER_USER_DATA_HS_26__DATA_MASK 0xFFFFFFFFL |
15319 | //SPI_SHADER_USER_DATA_HS_27 |
15320 | #define SPI_SHADER_USER_DATA_HS_27__DATA__SHIFT 0x0 |
15321 | #define SPI_SHADER_USER_DATA_HS_27__DATA_MASK 0xFFFFFFFFL |
15322 | //SPI_SHADER_USER_DATA_HS_28 |
15323 | #define SPI_SHADER_USER_DATA_HS_28__DATA__SHIFT 0x0 |
15324 | #define SPI_SHADER_USER_DATA_HS_28__DATA_MASK 0xFFFFFFFFL |
15325 | //SPI_SHADER_USER_DATA_HS_29 |
15326 | #define SPI_SHADER_USER_DATA_HS_29__DATA__SHIFT 0x0 |
15327 | #define SPI_SHADER_USER_DATA_HS_29__DATA_MASK 0xFFFFFFFFL |
15328 | //SPI_SHADER_USER_DATA_HS_30 |
15329 | #define SPI_SHADER_USER_DATA_HS_30__DATA__SHIFT 0x0 |
15330 | #define SPI_SHADER_USER_DATA_HS_30__DATA_MASK 0xFFFFFFFFL |
15331 | //SPI_SHADER_USER_DATA_HS_31 |
15332 | #define SPI_SHADER_USER_DATA_HS_31__DATA__SHIFT 0x0 |
15333 | #define SPI_SHADER_USER_DATA_HS_31__DATA_MASK 0xFFFFFFFFL |
15334 | //SPI_SHADER_REQ_CTRL_LSHS |
15335 | #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN__SHIFT 0x0 |
15336 | #define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 |
15337 | #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 |
15338 | #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 |
15339 | #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa |
15340 | #define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf |
15341 | #define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN__SHIFT 0x10 |
15342 | #define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 |
15343 | #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN_MASK 0x00000001L |
15344 | #define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL |
15345 | #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L |
15346 | #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L |
15347 | #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L |
15348 | #define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L |
15349 | #define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN_MASK 0x00010000L |
15350 | #define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L |
15351 | //SPI_SHADER_USER_ACCUM_LSHS_0 |
15352 | #define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION__SHIFT 0x0 |
15353 | #define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION_MASK 0x0000007FL |
15354 | //SPI_SHADER_USER_ACCUM_LSHS_1 |
15355 | #define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION__SHIFT 0x0 |
15356 | #define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION_MASK 0x0000007FL |
15357 | //SPI_SHADER_USER_ACCUM_LSHS_2 |
15358 | #define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION__SHIFT 0x0 |
15359 | #define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION_MASK 0x0000007FL |
15360 | //SPI_SHADER_USER_ACCUM_LSHS_3 |
15361 | #define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION__SHIFT 0x0 |
15362 | #define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION_MASK 0x0000007FL |
15363 | //SPI_SHADER_PGM_LO_LS |
15364 | #define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 |
15365 | #define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL |
15366 | //SPI_SHADER_PGM_HI_LS |
15367 | #define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 |
15368 | #define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL |
15369 | //COMPUTE_DISPATCH_INITIATOR |
15370 | #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 |
15371 | #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 |
15372 | #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 |
15373 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 |
15374 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 |
15375 | #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 |
15376 | #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 |
15377 | #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa |
15378 | #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb |
15379 | #define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc |
15380 | #define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE__SHIFT 0xd |
15381 | #define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe |
15382 | #define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN__SHIFT 0xf |
15383 | #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L |
15384 | #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L |
15385 | #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L |
15386 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L |
15387 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L |
15388 | #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L |
15389 | #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L |
15390 | #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L |
15391 | #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L |
15392 | #define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L |
15393 | #define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE_MASK 0x00002000L |
15394 | #define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L |
15395 | #define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN_MASK 0x00008000L |
15396 | //COMPUTE_DIM_X |
15397 | #define COMPUTE_DIM_X__SIZE__SHIFT 0x0 |
15398 | #define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL |
15399 | //COMPUTE_DIM_Y |
15400 | #define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 |
15401 | #define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL |
15402 | //COMPUTE_DIM_Z |
15403 | #define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 |
15404 | #define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL |
15405 | //COMPUTE_START_X |
15406 | #define COMPUTE_START_X__START__SHIFT 0x0 |
15407 | #define COMPUTE_START_X__START_MASK 0xFFFFFFFFL |
15408 | //COMPUTE_START_Y |
15409 | #define COMPUTE_START_Y__START__SHIFT 0x0 |
15410 | #define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL |
15411 | //COMPUTE_START_Z |
15412 | #define COMPUTE_START_Z__START__SHIFT 0x0 |
15413 | #define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL |
15414 | //COMPUTE_NUM_THREAD_X |
15415 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 |
15416 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 |
15417 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL |
15418 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L |
15419 | //COMPUTE_NUM_THREAD_Y |
15420 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 |
15421 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 |
15422 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL |
15423 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L |
15424 | //COMPUTE_NUM_THREAD_Z |
15425 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 |
15426 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 |
15427 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL |
15428 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L |
15429 | //COMPUTE_PIPELINESTAT_ENABLE |
15430 | #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 |
15431 | #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L |
15432 | //COMPUTE_PERFCOUNT_ENABLE |
15433 | #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 |
15434 | #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L |
15435 | //COMPUTE_PGM_LO |
15436 | #define COMPUTE_PGM_LO__DATA__SHIFT 0x0 |
15437 | #define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL |
15438 | //COMPUTE_PGM_HI |
15439 | #define COMPUTE_PGM_HI__DATA__SHIFT 0x0 |
15440 | #define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL |
15441 | //COMPUTE_DISPATCH_PKT_ADDR_LO |
15442 | #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 |
15443 | #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL |
15444 | //COMPUTE_DISPATCH_PKT_ADDR_HI |
15445 | #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 |
15446 | #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL |
15447 | //COMPUTE_DISPATCH_SCRATCH_BASE_LO |
15448 | #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 |
15449 | #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL |
15450 | //COMPUTE_DISPATCH_SCRATCH_BASE_HI |
15451 | #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 |
15452 | #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL |
15453 | //COMPUTE_PGM_RSRC1 |
15454 | #define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 |
15455 | #define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 |
15456 | #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa |
15457 | #define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc |
15458 | #define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 |
15459 | #define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 |
15460 | #define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 |
15461 | #define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 |
15462 | #define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a |
15463 | #define COMPUTE_PGM_RSRC1__WGP_MODE__SHIFT 0x1d |
15464 | #define COMPUTE_PGM_RSRC1__MEM_ORDERED__SHIFT 0x1e |
15465 | #define COMPUTE_PGM_RSRC1__FWD_PROGRESS__SHIFT 0x1f |
15466 | #define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL |
15467 | #define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L |
15468 | #define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L |
15469 | #define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L |
15470 | #define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L |
15471 | #define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L |
15472 | #define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L |
15473 | #define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L |
15474 | #define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L |
15475 | #define COMPUTE_PGM_RSRC1__WGP_MODE_MASK 0x20000000L |
15476 | #define COMPUTE_PGM_RSRC1__MEM_ORDERED_MASK 0x40000000L |
15477 | #define COMPUTE_PGM_RSRC1__FWD_PROGRESS_MASK 0x80000000L |
15478 | //COMPUTE_PGM_RSRC2 |
15479 | #define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 |
15480 | #define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 |
15481 | #define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 |
15482 | #define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 |
15483 | #define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 |
15484 | #define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 |
15485 | #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa |
15486 | #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb |
15487 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd |
15488 | #define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf |
15489 | #define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 |
15490 | #define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L |
15491 | #define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL |
15492 | #define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L |
15493 | #define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L |
15494 | #define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L |
15495 | #define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L |
15496 | #define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L |
15497 | #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L |
15498 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L |
15499 | #define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L |
15500 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L |
15501 | //COMPUTE_VMID |
15502 | #define COMPUTE_VMID__DATA__SHIFT 0x0 |
15503 | #define COMPUTE_VMID__DATA_MASK 0x0000000FL |
15504 | //COMPUTE_RESOURCE_LIMITS |
15505 | #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 |
15506 | #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc |
15507 | #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 |
15508 | #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 |
15509 | #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 |
15510 | #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 |
15511 | #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL |
15512 | #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L |
15513 | #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L |
15514 | #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L |
15515 | #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L |
15516 | #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L |
15517 | //COMPUTE_DESTINATION_EN_SE0 |
15518 | #define COMPUTE_DESTINATION_EN_SE0__CU_EN__SHIFT 0x0 |
15519 | #define COMPUTE_DESTINATION_EN_SE0__CU_EN_MASK 0xFFFFFFFFL |
15520 | //COMPUTE_STATIC_THREAD_MGMT_SE0 |
15521 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN__SHIFT 0x0 |
15522 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN__SHIFT 0x10 |
15523 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN_MASK 0x0000FFFFL |
15524 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN_MASK 0xFFFF0000L |
15525 | //COMPUTE_DESTINATION_EN_SE1 |
15526 | #define COMPUTE_DESTINATION_EN_SE1__CU_EN__SHIFT 0x0 |
15527 | #define COMPUTE_DESTINATION_EN_SE1__CU_EN_MASK 0xFFFFFFFFL |
15528 | //COMPUTE_STATIC_THREAD_MGMT_SE1 |
15529 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN__SHIFT 0x0 |
15530 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN__SHIFT 0x10 |
15531 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN_MASK 0x0000FFFFL |
15532 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN_MASK 0xFFFF0000L |
15533 | //COMPUTE_TMPRING_SIZE |
15534 | #define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 |
15535 | #define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc |
15536 | #define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL |
15537 | #define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L |
15538 | //COMPUTE_DESTINATION_EN_SE2 |
15539 | #define COMPUTE_DESTINATION_EN_SE2__CU_EN__SHIFT 0x0 |
15540 | #define COMPUTE_DESTINATION_EN_SE2__CU_EN_MASK 0xFFFFFFFFL |
15541 | //COMPUTE_STATIC_THREAD_MGMT_SE2 |
15542 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN__SHIFT 0x0 |
15543 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN__SHIFT 0x10 |
15544 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN_MASK 0x0000FFFFL |
15545 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN_MASK 0xFFFF0000L |
15546 | //COMPUTE_DESTINATION_EN_SE3 |
15547 | #define COMPUTE_DESTINATION_EN_SE3__CU_EN__SHIFT 0x0 |
15548 | #define COMPUTE_DESTINATION_EN_SE3__CU_EN_MASK 0xFFFFFFFFL |
15549 | //COMPUTE_STATIC_THREAD_MGMT_SE3 |
15550 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN__SHIFT 0x0 |
15551 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN__SHIFT 0x10 |
15552 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN_MASK 0x0000FFFFL |
15553 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN_MASK 0xFFFF0000L |
15554 | //COMPUTE_RESTART_X |
15555 | #define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 |
15556 | #define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL |
15557 | //COMPUTE_RESTART_Y |
15558 | #define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 |
15559 | #define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL |
15560 | //COMPUTE_RESTART_Z |
15561 | #define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 |
15562 | #define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL |
15563 | //COMPUTE_THREAD_TRACE_ENABLE |
15564 | #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 |
15565 | #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L |
15566 | //COMPUTE_MISC_RESERVED |
15567 | #define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 |
15568 | #define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2 |
15569 | #define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 |
15570 | #define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 |
15571 | #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 |
15572 | #define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L |
15573 | #define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x00000004L |
15574 | #define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L |
15575 | #define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L |
15576 | #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L |
15577 | //COMPUTE_DISPATCH_ID |
15578 | #define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 |
15579 | #define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL |
15580 | //COMPUTE_THREADGROUP_ID |
15581 | #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 |
15582 | #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL |
15583 | //COMPUTE_REQ_CTRL |
15584 | #define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN__SHIFT 0x0 |
15585 | #define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 |
15586 | #define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 |
15587 | #define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS__SHIFT 0x9 |
15588 | #define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa |
15589 | #define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf |
15590 | #define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN__SHIFT 0x10 |
15591 | #define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 |
15592 | #define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT__SHIFT 0x14 |
15593 | #define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN_MASK 0x00000001L |
15594 | #define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL |
15595 | #define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L |
15596 | #define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS_MASK 0x00000200L |
15597 | #define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L |
15598 | #define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L |
15599 | #define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN_MASK 0x00010000L |
15600 | #define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L |
15601 | #define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT_MASK 0x07F00000L |
15602 | //COMPUTE_USER_ACCUM_0 |
15603 | #define COMPUTE_USER_ACCUM_0__CONTRIBUTION__SHIFT 0x0 |
15604 | #define COMPUTE_USER_ACCUM_0__CONTRIBUTION_MASK 0x0000007FL |
15605 | //COMPUTE_USER_ACCUM_1 |
15606 | #define COMPUTE_USER_ACCUM_1__CONTRIBUTION__SHIFT 0x0 |
15607 | #define COMPUTE_USER_ACCUM_1__CONTRIBUTION_MASK 0x0000007FL |
15608 | //COMPUTE_USER_ACCUM_2 |
15609 | #define COMPUTE_USER_ACCUM_2__CONTRIBUTION__SHIFT 0x0 |
15610 | #define COMPUTE_USER_ACCUM_2__CONTRIBUTION_MASK 0x0000007FL |
15611 | //COMPUTE_USER_ACCUM_3 |
15612 | #define COMPUTE_USER_ACCUM_3__CONTRIBUTION__SHIFT 0x0 |
15613 | #define COMPUTE_USER_ACCUM_3__CONTRIBUTION_MASK 0x0000007FL |
15614 | //COMPUTE_PGM_RSRC3 |
15615 | #define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT__SHIFT 0x0 |
15616 | #define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT_MASK 0x0000000FL |
15617 | //COMPUTE_DDID_INDEX |
15618 | #define COMPUTE_DDID_INDEX__INDEX__SHIFT 0x0 |
15619 | #define COMPUTE_DDID_INDEX__INDEX_MASK 0x000007FFL |
15620 | //COMPUTE_SHADER_CHKSUM |
15621 | #define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0 |
15622 | #define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL |
15623 | //COMPUTE_RELAUNCH |
15624 | #define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 |
15625 | #define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e |
15626 | #define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f |
15627 | #define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL |
15628 | #define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L |
15629 | #define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L |
15630 | //COMPUTE_WAVE_RESTORE_ADDR_LO |
15631 | #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 |
15632 | #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL |
15633 | //COMPUTE_WAVE_RESTORE_ADDR_HI |
15634 | #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 |
15635 | #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL |
15636 | //COMPUTE_RELAUNCH2 |
15637 | #define COMPUTE_RELAUNCH2__PAYLOAD__SHIFT 0x0 |
15638 | #define COMPUTE_RELAUNCH2__IS_EVENT__SHIFT 0x1e |
15639 | #define COMPUTE_RELAUNCH2__IS_STATE__SHIFT 0x1f |
15640 | #define COMPUTE_RELAUNCH2__PAYLOAD_MASK 0x3FFFFFFFL |
15641 | #define COMPUTE_RELAUNCH2__IS_EVENT_MASK 0x40000000L |
15642 | #define COMPUTE_RELAUNCH2__IS_STATE_MASK 0x80000000L |
15643 | //COMPUTE_USER_DATA_0 |
15644 | #define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 |
15645 | #define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL |
15646 | //COMPUTE_USER_DATA_1 |
15647 | #define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 |
15648 | #define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL |
15649 | //COMPUTE_USER_DATA_2 |
15650 | #define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 |
15651 | #define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL |
15652 | //COMPUTE_USER_DATA_3 |
15653 | #define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 |
15654 | #define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL |
15655 | //COMPUTE_USER_DATA_4 |
15656 | #define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 |
15657 | #define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL |
15658 | //COMPUTE_USER_DATA_5 |
15659 | #define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 |
15660 | #define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL |
15661 | //COMPUTE_USER_DATA_6 |
15662 | #define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 |
15663 | #define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL |
15664 | //COMPUTE_USER_DATA_7 |
15665 | #define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 |
15666 | #define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL |
15667 | //COMPUTE_USER_DATA_8 |
15668 | #define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 |
15669 | #define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL |
15670 | //COMPUTE_USER_DATA_9 |
15671 | #define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 |
15672 | #define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL |
15673 | //COMPUTE_USER_DATA_10 |
15674 | #define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 |
15675 | #define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL |
15676 | //COMPUTE_USER_DATA_11 |
15677 | #define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 |
15678 | #define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL |
15679 | //COMPUTE_USER_DATA_12 |
15680 | #define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 |
15681 | #define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL |
15682 | //COMPUTE_USER_DATA_13 |
15683 | #define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 |
15684 | #define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL |
15685 | //COMPUTE_USER_DATA_14 |
15686 | #define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 |
15687 | #define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL |
15688 | //COMPUTE_USER_DATA_15 |
15689 | #define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 |
15690 | #define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL |
15691 | //COMPUTE_DISPATCH_TUNNEL |
15692 | #define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY__SHIFT 0x0 |
15693 | #define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE__SHIFT 0xa |
15694 | #define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY_MASK 0x000003FFL |
15695 | #define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE_MASK 0x00000400L |
15696 | //COMPUTE_DISPATCH_END |
15697 | #define COMPUTE_DISPATCH_END__DATA__SHIFT 0x0 |
15698 | #define COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL |
15699 | //COMPUTE_NOWHERE |
15700 | #define COMPUTE_NOWHERE__DATA__SHIFT 0x0 |
15701 | #define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL |
15702 | //SH_RESERVED_REG0 |
15703 | #define SH_RESERVED_REG0__DATA__SHIFT 0x0 |
15704 | #define SH_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL |
15705 | //SH_RESERVED_REG1 |
15706 | #define SH_RESERVED_REG1__DATA__SHIFT 0x0 |
15707 | #define SH_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL |
15708 | |
15709 | |
15710 | // addressBlock: gc_cppdec |
15711 | //CP_EOPQ_WAIT_TIME |
15712 | #define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0 |
15713 | #define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa |
15714 | #define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL |
15715 | #define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L |
15716 | //CP_CPC_MGCG_SYNC_CNTL |
15717 | #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 |
15718 | #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 |
15719 | #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL |
15720 | #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L |
15721 | //CPC_INT_INFO |
15722 | #define CPC_INT_INFO__ADDR_HI__SHIFT 0x0 |
15723 | #define CPC_INT_INFO__TYPE__SHIFT 0x10 |
15724 | #define CPC_INT_INFO__VMID__SHIFT 0x14 |
15725 | #define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c |
15726 | #define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL |
15727 | #define CPC_INT_INFO__TYPE_MASK 0x00010000L |
15728 | #define CPC_INT_INFO__VMID_MASK 0x00F00000L |
15729 | #define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L |
15730 | //CP_VIRT_STATUS |
15731 | #define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0 |
15732 | #define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL |
15733 | //CPC_INT_ADDR |
15734 | #define CPC_INT_ADDR__ADDR__SHIFT 0x0 |
15735 | #define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL |
15736 | //CPC_INT_PASID |
15737 | #define CPC_INT_PASID__PASID__SHIFT 0x0 |
15738 | #define CPC_INT_PASID__BYPASS_PASID__SHIFT 0x10 |
15739 | #define CPC_INT_PASID__PASID_MASK 0x0000FFFFL |
15740 | #define CPC_INT_PASID__BYPASS_PASID_MASK 0x00010000L |
15741 | //CP_GFX_ERROR |
15742 | #define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0 |
15743 | #define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4 |
15744 | #define CP_GFX_ERROR__CE_DATA_FETCHER_UTCL1_ERROR__SHIFT 0x5 |
15745 | #define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR__SHIFT 0x6 |
15746 | #define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7 |
15747 | #define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8 |
15748 | #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9 |
15749 | #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa |
15750 | #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb |
15751 | #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc |
15752 | #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd |
15753 | #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe |
15754 | #define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf |
15755 | #define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10 |
15756 | #define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11 |
15757 | #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12 |
15758 | #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13 |
15759 | #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14 |
15760 | #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15 |
15761 | #define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16 |
15762 | #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17 |
15763 | #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18 |
15764 | #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19 |
15765 | #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a |
15766 | #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b |
15767 | #define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c |
15768 | #define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d |
15769 | #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e |
15770 | #define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f |
15771 | #define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL |
15772 | #define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L |
15773 | #define CP_GFX_ERROR__CE_DATA_FETCHER_UTCL1_ERROR_MASK 0x00000020L |
15774 | #define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR_MASK 0x00000040L |
15775 | #define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L |
15776 | #define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L |
15777 | #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L |
15778 | #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L |
15779 | #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L |
15780 | #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L |
15781 | #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L |
15782 | #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L |
15783 | #define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L |
15784 | #define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L |
15785 | #define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L |
15786 | #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L |
15787 | #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L |
15788 | #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L |
15789 | #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L |
15790 | #define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L |
15791 | #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L |
15792 | #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L |
15793 | #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L |
15794 | #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L |
15795 | #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L |
15796 | #define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L |
15797 | #define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L |
15798 | #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L |
15799 | #define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L |
15800 | //CPG_UTCL1_CNTL |
15801 | #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
15802 | #define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
15803 | #define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
15804 | #define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
15805 | #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
15806 | #define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
15807 | #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e |
15808 | #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
15809 | #define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
15810 | #define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
15811 | #define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
15812 | #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
15813 | #define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
15814 | #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L |
15815 | //CPC_UTCL1_CNTL |
15816 | #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
15817 | #define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
15818 | #define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
15819 | #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
15820 | #define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
15821 | #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e |
15822 | #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
15823 | #define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
15824 | #define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
15825 | #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
15826 | #define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
15827 | #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L |
15828 | //CPF_UTCL1_CNTL |
15829 | #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
15830 | #define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
15831 | #define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
15832 | #define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
15833 | #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
15834 | #define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
15835 | #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e |
15836 | #define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f |
15837 | #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
15838 | #define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
15839 | #define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
15840 | #define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
15841 | #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
15842 | #define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
15843 | #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L |
15844 | #define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L |
15845 | //CP_AQL_SMM_STATUS |
15846 | #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0 |
15847 | #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL |
15848 | //CP_RB0_BASE |
15849 | #define CP_RB0_BASE__RB_BASE__SHIFT 0x0 |
15850 | #define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL |
15851 | //CP_RB_BASE |
15852 | #define CP_RB_BASE__RB_BASE__SHIFT 0x0 |
15853 | #define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL |
15854 | //CP_RB0_CNTL |
15855 | #define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 |
15856 | #define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 |
15857 | #define CP_RB0_CNTL__RB_NON_PRIV__SHIFT 0xf |
15858 | #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
15859 | #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
15860 | #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 |
15861 | #define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x1a |
15862 | #define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
15863 | #define CP_RB0_CNTL__RB_EXE__SHIFT 0x1c |
15864 | #define CP_RB0_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e |
15865 | #define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
15866 | #define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL |
15867 | #define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L |
15868 | #define CP_RB0_CNTL__RB_NON_PRIV_MASK 0x00008000L |
15869 | #define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
15870 | #define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
15871 | #define CP_RB0_CNTL__CACHE_POLICY_MASK 0x03000000L |
15872 | #define CP_RB0_CNTL__RB_VOLATILE_MASK 0x04000000L |
15873 | #define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
15874 | #define CP_RB0_CNTL__RB_EXE_MASK 0x10000000L |
15875 | #define CP_RB0_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L |
15876 | #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
15877 | //CP_RB_CNTL |
15878 | #define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 |
15879 | #define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 |
15880 | #define CP_RB_CNTL__RB_NON_PRIV__SHIFT 0xf |
15881 | #define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
15882 | #define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
15883 | #define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 |
15884 | #define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x1a |
15885 | #define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
15886 | #define CP_RB_CNTL__RB_EXE__SHIFT 0x1c |
15887 | #define CP_RB_CNTL__KMD_QUEUE__SHIFT 0x1d |
15888 | #define CP_RB_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e |
15889 | #define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
15890 | #define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL |
15891 | #define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L |
15892 | #define CP_RB_CNTL__RB_NON_PRIV_MASK 0x00008000L |
15893 | #define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
15894 | #define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
15895 | #define CP_RB_CNTL__CACHE_POLICY_MASK 0x03000000L |
15896 | #define CP_RB_CNTL__RB_VOLATILE_MASK 0x04000000L |
15897 | #define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
15898 | #define CP_RB_CNTL__RB_EXE_MASK 0x10000000L |
15899 | #define CP_RB_CNTL__KMD_QUEUE_MASK 0x20000000L |
15900 | #define CP_RB_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L |
15901 | #define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
15902 | //CP_RB_RPTR_WR |
15903 | #define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 |
15904 | #define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL |
15905 | //CP_RB0_RPTR_ADDR |
15906 | #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
15907 | #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
15908 | //CP_RB_RPTR_ADDR |
15909 | #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
15910 | #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
15911 | //CP_RB0_RPTR_ADDR_HI |
15912 | #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
15913 | #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
15914 | //CP_RB_RPTR_ADDR_HI |
15915 | #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
15916 | #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
15917 | //CP_RB0_BUFSZ_MASK |
15918 | #define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0 |
15919 | #define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL |
15920 | //CP_RB_BUFSZ_MASK |
15921 | #define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0 |
15922 | #define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL |
15923 | //CP_INT_CNTL |
15924 | #define CP_INT_CNTL__RESUME_INT_ENABLE__SHIFT 0x8 |
15925 | #define CP_INT_CNTL__SUSPEND_INT_ENABLE__SHIFT 0x9 |
15926 | #define CP_INT_CNTL__DMA_WATCH_INT_ENABLE__SHIFT 0xa |
15927 | #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb |
15928 | #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
15929 | #define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
15930 | #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
15931 | #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 |
15932 | #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 |
15933 | #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 |
15934 | #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 |
15935 | #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
15936 | #define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
15937 | #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
15938 | #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
15939 | #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
15940 | #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
15941 | #define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
15942 | #define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
15943 | #define CP_INT_CNTL__RESUME_INT_ENABLE_MASK 0x00000100L |
15944 | #define CP_INT_CNTL__SUSPEND_INT_ENABLE_MASK 0x00000200L |
15945 | #define CP_INT_CNTL__DMA_WATCH_INT_ENABLE_MASK 0x00000400L |
15946 | #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L |
15947 | #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
15948 | #define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
15949 | #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
15950 | #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L |
15951 | #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L |
15952 | #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L |
15953 | #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L |
15954 | #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
15955 | #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
15956 | #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
15957 | #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
15958 | #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
15959 | #define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
15960 | #define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
15961 | #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
15962 | //CP_INT_STATUS |
15963 | #define CP_INT_STATUS__RESUME_INT_STAT__SHIFT 0x8 |
15964 | #define CP_INT_STATUS__SUSPEND_INT_STAT__SHIFT 0x9 |
15965 | #define CP_INT_STATUS__DMA_WATCH_INT_STAT__SHIFT 0xa |
15966 | #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb |
15967 | #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
15968 | #define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10 |
15969 | #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
15970 | #define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 |
15971 | #define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 |
15972 | #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 |
15973 | #define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 |
15974 | #define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
15975 | #define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 |
15976 | #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
15977 | #define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a |
15978 | #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
15979 | #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d |
15980 | #define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e |
15981 | #define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f |
15982 | #define CP_INT_STATUS__RESUME_INT_STAT_MASK 0x00000100L |
15983 | #define CP_INT_STATUS__SUSPEND_INT_STAT_MASK 0x00000200L |
15984 | #define CP_INT_STATUS__DMA_WATCH_INT_STAT_MASK 0x00000400L |
15985 | #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L |
15986 | #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
15987 | #define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L |
15988 | #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
15989 | #define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L |
15990 | #define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L |
15991 | #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L |
15992 | #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L |
15993 | #define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
15994 | #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L |
15995 | #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
15996 | #define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L |
15997 | #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
15998 | #define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L |
15999 | #define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L |
16000 | #define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L |
16001 | //CP_DEVICE_ID |
16002 | #define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
16003 | #define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL |
16004 | //CP_ME0_PIPE_PRIORITY_CNTS |
16005 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
16006 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
16007 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
16008 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
16009 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
16010 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
16011 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
16012 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
16013 | //CP_RING_PRIORITY_CNTS |
16014 | #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
16015 | #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
16016 | #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
16017 | #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
16018 | #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
16019 | #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
16020 | #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
16021 | #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
16022 | //CP_ME0_PIPE0_PRIORITY |
16023 | #define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
16024 | #define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
16025 | //CP_RING0_PRIORITY |
16026 | #define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 |
16027 | #define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L |
16028 | //CP_ME0_PIPE1_PRIORITY |
16029 | #define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
16030 | #define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
16031 | //CP_RING1_PRIORITY |
16032 | #define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 |
16033 | #define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L |
16034 | //CP_ME0_PIPE2_PRIORITY |
16035 | #define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
16036 | #define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
16037 | //CP_RING2_PRIORITY |
16038 | #define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 |
16039 | #define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L |
16040 | //CP_FATAL_ERROR |
16041 | #define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0 |
16042 | #define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1 |
16043 | #define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2 |
16044 | #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3 |
16045 | #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4 |
16046 | #define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L |
16047 | #define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L |
16048 | #define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L |
16049 | #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L |
16050 | #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L |
16051 | //CP_RB_VMID |
16052 | #define CP_RB_VMID__RB0_VMID__SHIFT 0x0 |
16053 | #define CP_RB_VMID__RB1_VMID__SHIFT 0x8 |
16054 | #define CP_RB_VMID__RB2_VMID__SHIFT 0x10 |
16055 | #define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL |
16056 | #define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L |
16057 | #define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L |
16058 | //CP_ME0_PIPE0_VMID |
16059 | #define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 |
16060 | #define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL |
16061 | //CP_ME0_PIPE1_VMID |
16062 | #define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 |
16063 | #define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL |
16064 | //CP_RB0_WPTR |
16065 | #define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 |
16066 | #define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
16067 | //CP_RB_WPTR |
16068 | #define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 |
16069 | #define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
16070 | //CP_RB0_WPTR_HI |
16071 | #define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0 |
16072 | #define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
16073 | //CP_RB_WPTR_HI |
16074 | #define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0 |
16075 | #define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
16076 | //CP_RB1_WPTR |
16077 | #define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 |
16078 | #define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
16079 | //CP_RB1_WPTR_HI |
16080 | #define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0 |
16081 | #define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
16082 | //CP_RB2_WPTR |
16083 | #define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 |
16084 | #define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL |
16085 | //CP_PROCESS_QUANTUM |
16086 | #define CP_PROCESS_QUANTUM__QUANTUM_DURATION__SHIFT 0x0 |
16087 | #define CP_PROCESS_QUANTUM__TIMER_EXPIRED__SHIFT 0x1c |
16088 | #define CP_PROCESS_QUANTUM__QUANTUM_SCALE__SHIFT 0x1d |
16089 | #define CP_PROCESS_QUANTUM__QUANTUM_EN__SHIFT 0x1f |
16090 | #define CP_PROCESS_QUANTUM__QUANTUM_DURATION_MASK 0x0FFFFFFFL |
16091 | #define CP_PROCESS_QUANTUM__TIMER_EXPIRED_MASK 0x10000000L |
16092 | #define CP_PROCESS_QUANTUM__QUANTUM_SCALE_MASK 0x60000000L |
16093 | #define CP_PROCESS_QUANTUM__QUANTUM_EN_MASK 0x80000000L |
16094 | //CP_RB_DOORBELL_RANGE_LOWER |
16095 | #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 |
16096 | #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x00000FFCL |
16097 | //CP_RB_DOORBELL_RANGE_UPPER |
16098 | #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 |
16099 | #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL |
16100 | //CP_MEC_DOORBELL_RANGE_LOWER |
16101 | #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 |
16102 | #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x00000FFCL |
16103 | //CP_MEC_DOORBELL_RANGE_UPPER |
16104 | #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 |
16105 | #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL |
16106 | //CPG_UTCL1_ERROR |
16107 | #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 |
16108 | #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L |
16109 | //CPC_UTCL1_ERROR |
16110 | #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 |
16111 | #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L |
16112 | //CP_RB1_BASE |
16113 | #define CP_RB1_BASE__RB_BASE__SHIFT 0x0 |
16114 | #define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL |
16115 | //CP_RB1_CNTL |
16116 | #define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 |
16117 | #define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 |
16118 | #define CP_RB1_CNTL__RB_NON_PRIV__SHIFT 0xf |
16119 | #define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
16120 | #define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
16121 | #define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 |
16122 | #define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x1a |
16123 | #define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
16124 | #define CP_RB1_CNTL__RB_EXE__SHIFT 0x1c |
16125 | #define CP_RB1_CNTL__KMD_QUEUE__SHIFT 0x1d |
16126 | #define CP_RB1_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e |
16127 | #define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
16128 | #define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL |
16129 | #define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L |
16130 | #define CP_RB1_CNTL__RB_NON_PRIV_MASK 0x00008000L |
16131 | #define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
16132 | #define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
16133 | #define CP_RB1_CNTL__CACHE_POLICY_MASK 0x03000000L |
16134 | #define CP_RB1_CNTL__RB_VOLATILE_MASK 0x04000000L |
16135 | #define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
16136 | #define CP_RB1_CNTL__RB_EXE_MASK 0x10000000L |
16137 | #define CP_RB1_CNTL__KMD_QUEUE_MASK 0x20000000L |
16138 | #define CP_RB1_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L |
16139 | #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
16140 | //CP_RB1_RPTR_ADDR |
16141 | #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
16142 | #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
16143 | //CP_RB1_RPTR_ADDR_HI |
16144 | #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
16145 | #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
16146 | //CP_RB1_BUFSZ_MASK |
16147 | #define CP_RB1_BUFSZ_MASK__DATA__SHIFT 0x0 |
16148 | #define CP_RB1_BUFSZ_MASK__DATA_MASK 0x000FFFFFL |
16149 | //CP_RB2_BASE |
16150 | #define CP_RB2_BASE__RB_BASE__SHIFT 0x0 |
16151 | #define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL |
16152 | //CP_RB2_CNTL |
16153 | #define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 |
16154 | #define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 |
16155 | #define CP_RB2_CNTL__RB_NON_PRIV__SHIFT 0xf |
16156 | #define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
16157 | #define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
16158 | #define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 |
16159 | #define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x1a |
16160 | #define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
16161 | #define CP_RB2_CNTL__RB_EXE__SHIFT 0x1c |
16162 | #define CP_RB2_CNTL__KMD_QUEUE__SHIFT 0x1d |
16163 | #define CP_RB2_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e |
16164 | #define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
16165 | #define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL |
16166 | #define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L |
16167 | #define CP_RB2_CNTL__RB_NON_PRIV_MASK 0x00008000L |
16168 | #define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
16169 | #define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
16170 | #define CP_RB2_CNTL__CACHE_POLICY_MASK 0x03000000L |
16171 | #define CP_RB2_CNTL__RB_VOLATILE_MASK 0x04000000L |
16172 | #define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
16173 | #define CP_RB2_CNTL__RB_EXE_MASK 0x10000000L |
16174 | #define CP_RB2_CNTL__KMD_QUEUE_MASK 0x20000000L |
16175 | #define CP_RB2_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L |
16176 | #define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
16177 | //CP_RB2_RPTR_ADDR |
16178 | #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
16179 | #define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
16180 | //CP_RB2_RPTR_ADDR_HI |
16181 | #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
16182 | #define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
16183 | //CP_INT_CNTL_RING0 |
16184 | #define CP_INT_CNTL_RING0__RESUME_INT_ENABLE__SHIFT 0x8 |
16185 | #define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE__SHIFT 0x9 |
16186 | #define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE__SHIFT 0xa |
16187 | #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb |
16188 | #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
16189 | #define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10 |
16190 | #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
16191 | #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 |
16192 | #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 |
16193 | #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 |
16194 | #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 |
16195 | #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
16196 | #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
16197 | #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
16198 | #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
16199 | #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
16200 | #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d |
16201 | #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e |
16202 | #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f |
16203 | #define CP_INT_CNTL_RING0__RESUME_INT_ENABLE_MASK 0x00000100L |
16204 | #define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE_MASK 0x00000200L |
16205 | #define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE_MASK 0x00000400L |
16206 | #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L |
16207 | #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
16208 | #define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L |
16209 | #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
16210 | #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L |
16211 | #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L |
16212 | #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L |
16213 | #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L |
16214 | #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
16215 | #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
16216 | #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
16217 | #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
16218 | #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
16219 | #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L |
16220 | #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L |
16221 | #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L |
16222 | //CP_INT_CNTL_RING1 |
16223 | #define CP_INT_CNTL_RING1__DMA_WATCH_INT_ENABLE__SHIFT 0xa |
16224 | #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb |
16225 | #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
16226 | #define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10 |
16227 | #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
16228 | #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12 |
16229 | #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 |
16230 | #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 |
16231 | #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15 |
16232 | #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
16233 | #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
16234 | #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
16235 | #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
16236 | #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
16237 | #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d |
16238 | #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e |
16239 | #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f |
16240 | #define CP_INT_CNTL_RING1__DMA_WATCH_INT_ENABLE_MASK 0x00000400L |
16241 | #define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L |
16242 | #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
16243 | #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L |
16244 | #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
16245 | #define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L |
16246 | #define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L |
16247 | #define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L |
16248 | #define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L |
16249 | #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
16250 | #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
16251 | #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
16252 | #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
16253 | #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
16254 | #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L |
16255 | #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L |
16256 | #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L |
16257 | //CP_INT_CNTL_RING2 |
16258 | #define CP_INT_CNTL_RING2__DMA_WATCH_INT_ENABLE__SHIFT 0xa |
16259 | #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb |
16260 | #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
16261 | #define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10 |
16262 | #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
16263 | #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12 |
16264 | #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 |
16265 | #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 |
16266 | #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15 |
16267 | #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
16268 | #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
16269 | #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
16270 | #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
16271 | #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
16272 | #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d |
16273 | #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e |
16274 | #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f |
16275 | #define CP_INT_CNTL_RING2__DMA_WATCH_INT_ENABLE_MASK 0x00000400L |
16276 | #define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L |
16277 | #define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
16278 | #define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L |
16279 | #define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
16280 | #define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L |
16281 | #define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L |
16282 | #define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L |
16283 | #define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L |
16284 | #define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
16285 | #define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
16286 | #define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
16287 | #define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
16288 | #define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
16289 | #define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L |
16290 | #define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L |
16291 | #define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L |
16292 | //CP_INT_STATUS_RING0 |
16293 | #define CP_INT_STATUS_RING0__RESUME_INT_STAT__SHIFT 0x8 |
16294 | #define CP_INT_STATUS_RING0__SUSPEND_INT_STAT__SHIFT 0x9 |
16295 | #define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT__SHIFT 0xa |
16296 | #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb |
16297 | #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
16298 | #define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10 |
16299 | #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
16300 | #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 |
16301 | #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 |
16302 | #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 |
16303 | #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 |
16304 | #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
16305 | #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 |
16306 | #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
16307 | #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a |
16308 | #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
16309 | #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d |
16310 | #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e |
16311 | #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f |
16312 | #define CP_INT_STATUS_RING0__RESUME_INT_STAT_MASK 0x00000100L |
16313 | #define CP_INT_STATUS_RING0__SUSPEND_INT_STAT_MASK 0x00000200L |
16314 | #define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT_MASK 0x00000400L |
16315 | #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L |
16316 | #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
16317 | #define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L |
16318 | #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
16319 | #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L |
16320 | #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L |
16321 | #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L |
16322 | #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L |
16323 | #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
16324 | #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L |
16325 | #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
16326 | #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L |
16327 | #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
16328 | #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L |
16329 | #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L |
16330 | #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L |
16331 | //CP_INT_STATUS_RING1 |
16332 | #define CP_INT_STATUS_RING1__DMA_WATCH_INT_STAT__SHIFT 0xa |
16333 | #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb |
16334 | #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
16335 | #define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10 |
16336 | #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
16337 | #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12 |
16338 | #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 |
16339 | #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 |
16340 | #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15 |
16341 | #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
16342 | #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 |
16343 | #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
16344 | #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a |
16345 | #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
16346 | #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d |
16347 | #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e |
16348 | #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f |
16349 | #define CP_INT_STATUS_RING1__DMA_WATCH_INT_STAT_MASK 0x00000400L |
16350 | #define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L |
16351 | #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
16352 | #define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L |
16353 | #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
16354 | #define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L |
16355 | #define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L |
16356 | #define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L |
16357 | #define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L |
16358 | #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
16359 | #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L |
16360 | #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
16361 | #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L |
16362 | #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
16363 | #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L |
16364 | #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L |
16365 | #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L |
16366 | //CP_INT_STATUS_RING2 |
16367 | #define CP_INT_STATUS_RING2__DMA_WATCH_INT_STAT__SHIFT 0xa |
16368 | #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb |
16369 | #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
16370 | #define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10 |
16371 | #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
16372 | #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12 |
16373 | #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 |
16374 | #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 |
16375 | #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15 |
16376 | #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
16377 | #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 |
16378 | #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
16379 | #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a |
16380 | #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
16381 | #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d |
16382 | #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e |
16383 | #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f |
16384 | #define CP_INT_STATUS_RING2__DMA_WATCH_INT_STAT_MASK 0x00000400L |
16385 | #define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L |
16386 | #define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
16387 | #define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L |
16388 | #define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
16389 | #define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L |
16390 | #define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L |
16391 | #define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L |
16392 | #define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L |
16393 | #define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
16394 | #define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L |
16395 | #define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
16396 | #define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L |
16397 | #define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
16398 | #define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L |
16399 | #define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L |
16400 | #define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L |
16401 | //CP_ME_F32_INTERRUPT |
16402 | #define CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 |
16403 | #define CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT 0x1 |
16404 | #define CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT 0x2 |
16405 | #define CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT 0x3 |
16406 | #define CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L |
16407 | #define CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK 0x00000002L |
16408 | #define CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK 0x00000004L |
16409 | #define CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK 0x00000008L |
16410 | //CP_PFP_F32_INTERRUPT |
16411 | #define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 |
16412 | #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 |
16413 | #define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
16414 | #define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT 0x3 |
16415 | #define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L |
16416 | #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L |
16417 | #define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
16418 | #define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK 0x00000008L |
16419 | //CP_CE_F32_INTERRUPT |
16420 | #define CP_CE_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 |
16421 | #define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x1 |
16422 | #define CP_CE_F32_INTERRUPT__CE_F32_INT_2__SHIFT 0x2 |
16423 | #define CP_CE_F32_INTERRUPT__CE_F32_INT_3__SHIFT 0x3 |
16424 | #define CP_CE_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L |
16425 | #define CP_CE_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000002L |
16426 | #define CP_CE_F32_INTERRUPT__CE_F32_INT_2_MASK 0x00000004L |
16427 | #define CP_CE_F32_INTERRUPT__CE_F32_INT_3_MASK 0x00000008L |
16428 | //CP_MEC1_F32_INTERRUPT |
16429 | #define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0 |
16430 | #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 |
16431 | #define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
16432 | #define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3 |
16433 | #define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4 |
16434 | #define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5 |
16435 | #define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6 |
16436 | #define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7 |
16437 | #define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8 |
16438 | #define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9 |
16439 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa |
16440 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb |
16441 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc |
16442 | #define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd |
16443 | #define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe |
16444 | #define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf |
16445 | #define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L |
16446 | #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L |
16447 | #define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
16448 | #define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L |
16449 | #define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L |
16450 | #define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L |
16451 | #define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L |
16452 | #define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L |
16453 | #define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L |
16454 | #define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L |
16455 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L |
16456 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L |
16457 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L |
16458 | #define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L |
16459 | #define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L |
16460 | #define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L |
16461 | //CP_MEC2_F32_INTERRUPT |
16462 | #define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0 |
16463 | #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 |
16464 | #define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
16465 | #define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3 |
16466 | #define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4 |
16467 | #define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5 |
16468 | #define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6 |
16469 | #define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7 |
16470 | #define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8 |
16471 | #define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9 |
16472 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa |
16473 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb |
16474 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc |
16475 | #define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd |
16476 | #define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe |
16477 | #define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf |
16478 | #define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L |
16479 | #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L |
16480 | #define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
16481 | #define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L |
16482 | #define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L |
16483 | #define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L |
16484 | #define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L |
16485 | #define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L |
16486 | #define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L |
16487 | #define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L |
16488 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L |
16489 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L |
16490 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L |
16491 | #define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L |
16492 | #define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L |
16493 | #define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L |
16494 | //CP_PWR_CNTL |
16495 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 |
16496 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 |
16497 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 |
16498 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 |
16499 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa |
16500 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb |
16501 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 |
16502 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 |
16503 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 |
16504 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 |
16505 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0__SHIFT 0x14 |
16506 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1__SHIFT 0x15 |
16507 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2__SHIFT 0x16 |
16508 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3__SHIFT 0x17 |
16509 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L |
16510 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L |
16511 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L |
16512 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L |
16513 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L |
16514 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L |
16515 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L |
16516 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L |
16517 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L |
16518 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L |
16519 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0_MASK 0x00100000L |
16520 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1_MASK 0x00200000L |
16521 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2_MASK 0x00400000L |
16522 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3_MASK 0x00800000L |
16523 | //CP_MEM_SLP_CNTL |
16524 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 |
16525 | #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 |
16526 | #define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 |
16527 | #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 |
16528 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 |
16529 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 |
16530 | #define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 |
16531 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L |
16532 | #define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L |
16533 | #define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL |
16534 | #define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L |
16535 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L |
16536 | #define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L |
16537 | #define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L |
16538 | //CP_ECC_FIRSTOCCURRENCE |
16539 | #define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 |
16540 | #define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 |
16541 | #define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 |
16542 | #define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa |
16543 | #define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc |
16544 | #define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 |
16545 | #define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L |
16546 | #define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L |
16547 | #define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L |
16548 | #define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L |
16549 | #define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L |
16550 | #define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L |
16551 | //CP_ECC_FIRSTOCCURRENCE_RING0 |
16552 | #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 |
16553 | #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL |
16554 | //CP_ECC_FIRSTOCCURRENCE_RING1 |
16555 | #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 |
16556 | #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL |
16557 | //CP_ECC_FIRSTOCCURRENCE_RING2 |
16558 | #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0 |
16559 | #define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL |
16560 | //GB_EDC_MODE |
16561 | #define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf |
16562 | #define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 |
16563 | #define GB_EDC_MODE__GATE_FUE__SHIFT 0x11 |
16564 | #define GB_EDC_MODE__DED_MODE__SHIFT 0x14 |
16565 | #define GB_EDC_MODE__PROP_FED__SHIFT 0x1d |
16566 | #define GB_EDC_MODE__BYPASS__SHIFT 0x1f |
16567 | #define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L |
16568 | #define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L |
16569 | #define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L |
16570 | #define GB_EDC_MODE__DED_MODE_MASK 0x00300000L |
16571 | #define GB_EDC_MODE__PROP_FED_MASK 0x20000000L |
16572 | #define GB_EDC_MODE__BYPASS_MASK 0x80000000L |
16573 | //CP_PQ_WPTR_POLL_CNTL |
16574 | #define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 |
16575 | #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d |
16576 | #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e |
16577 | #define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f |
16578 | #define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL |
16579 | #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L |
16580 | #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L |
16581 | #define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L |
16582 | //CP_PQ_WPTR_POLL_CNTL1 |
16583 | #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 |
16584 | #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL |
16585 | //CP_ME1_PIPE0_INT_CNTL |
16586 | #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
16587 | #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
16588 | #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
16589 | #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
16590 | #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
16591 | #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
16592 | #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
16593 | #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
16594 | #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
16595 | #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
16596 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
16597 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
16598 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
16599 | #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
16600 | #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
16601 | #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
16602 | #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
16603 | #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
16604 | #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
16605 | #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
16606 | #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
16607 | #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
16608 | #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
16609 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
16610 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
16611 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
16612 | //CP_ME1_PIPE1_INT_CNTL |
16613 | #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
16614 | #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
16615 | #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
16616 | #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
16617 | #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
16618 | #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
16619 | #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
16620 | #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
16621 | #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
16622 | #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
16623 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
16624 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
16625 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
16626 | #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
16627 | #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
16628 | #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
16629 | #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
16630 | #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
16631 | #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
16632 | #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
16633 | #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
16634 | #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
16635 | #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
16636 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
16637 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
16638 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
16639 | //CP_ME1_PIPE2_INT_CNTL |
16640 | #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
16641 | #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
16642 | #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
16643 | #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
16644 | #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
16645 | #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
16646 | #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
16647 | #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
16648 | #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
16649 | #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
16650 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
16651 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
16652 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
16653 | #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
16654 | #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
16655 | #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
16656 | #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
16657 | #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
16658 | #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
16659 | #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
16660 | #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
16661 | #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
16662 | #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
16663 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
16664 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
16665 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
16666 | //CP_ME1_PIPE3_INT_CNTL |
16667 | #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
16668 | #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
16669 | #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
16670 | #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
16671 | #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
16672 | #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
16673 | #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
16674 | #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
16675 | #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
16676 | #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
16677 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
16678 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
16679 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
16680 | #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
16681 | #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
16682 | #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
16683 | #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
16684 | #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
16685 | #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
16686 | #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
16687 | #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
16688 | #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
16689 | #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
16690 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
16691 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
16692 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
16693 | //CP_ME2_PIPE0_INT_CNTL |
16694 | #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
16695 | #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
16696 | #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
16697 | #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
16698 | #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
16699 | #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
16700 | #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
16701 | #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
16702 | #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
16703 | #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
16704 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
16705 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
16706 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
16707 | #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
16708 | #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
16709 | #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
16710 | #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
16711 | #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
16712 | #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
16713 | #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
16714 | #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
16715 | #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
16716 | #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
16717 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
16718 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
16719 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
16720 | //CP_ME2_PIPE1_INT_CNTL |
16721 | #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
16722 | #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
16723 | #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
16724 | #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
16725 | #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
16726 | #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
16727 | #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
16728 | #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
16729 | #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
16730 | #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
16731 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
16732 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
16733 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
16734 | #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
16735 | #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
16736 | #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
16737 | #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
16738 | #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
16739 | #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
16740 | #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
16741 | #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
16742 | #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
16743 | #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
16744 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
16745 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
16746 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
16747 | //CP_ME2_PIPE2_INT_CNTL |
16748 | #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
16749 | #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
16750 | #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
16751 | #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
16752 | #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
16753 | #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
16754 | #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
16755 | #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
16756 | #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
16757 | #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
16758 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
16759 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
16760 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
16761 | #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
16762 | #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
16763 | #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
16764 | #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
16765 | #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
16766 | #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
16767 | #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
16768 | #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
16769 | #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
16770 | #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
16771 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
16772 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
16773 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
16774 | //CP_ME2_PIPE3_INT_CNTL |
16775 | #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
16776 | #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
16777 | #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
16778 | #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
16779 | #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
16780 | #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
16781 | #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
16782 | #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
16783 | #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
16784 | #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
16785 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
16786 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
16787 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
16788 | #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
16789 | #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
16790 | #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
16791 | #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
16792 | #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
16793 | #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
16794 | #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
16795 | #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
16796 | #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
16797 | #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
16798 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
16799 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
16800 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
16801 | //CP_ME1_PIPE0_INT_STATUS |
16802 | #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
16803 | #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
16804 | #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
16805 | #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
16806 | #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
16807 | #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
16808 | #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
16809 | #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
16810 | #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
16811 | #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
16812 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
16813 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
16814 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
16815 | #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
16816 | #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
16817 | #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
16818 | #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
16819 | #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
16820 | #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
16821 | #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
16822 | #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
16823 | #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
16824 | #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
16825 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
16826 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
16827 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
16828 | //CP_ME1_PIPE1_INT_STATUS |
16829 | #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
16830 | #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
16831 | #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
16832 | #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
16833 | #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
16834 | #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
16835 | #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
16836 | #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
16837 | #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
16838 | #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
16839 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
16840 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
16841 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
16842 | #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
16843 | #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
16844 | #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
16845 | #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
16846 | #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
16847 | #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
16848 | #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
16849 | #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
16850 | #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
16851 | #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
16852 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
16853 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
16854 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
16855 | //CP_ME1_PIPE2_INT_STATUS |
16856 | #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
16857 | #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
16858 | #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
16859 | #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
16860 | #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
16861 | #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
16862 | #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
16863 | #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
16864 | #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
16865 | #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
16866 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
16867 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
16868 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
16869 | #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
16870 | #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
16871 | #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
16872 | #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
16873 | #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
16874 | #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
16875 | #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
16876 | #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
16877 | #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
16878 | #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
16879 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
16880 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
16881 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
16882 | //CP_ME1_PIPE3_INT_STATUS |
16883 | #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
16884 | #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
16885 | #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
16886 | #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
16887 | #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
16888 | #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
16889 | #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
16890 | #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
16891 | #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
16892 | #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
16893 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
16894 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
16895 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
16896 | #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
16897 | #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
16898 | #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
16899 | #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
16900 | #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
16901 | #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
16902 | #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
16903 | #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
16904 | #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
16905 | #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
16906 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
16907 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
16908 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
16909 | //CP_ME2_PIPE0_INT_STATUS |
16910 | #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
16911 | #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
16912 | #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
16913 | #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
16914 | #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
16915 | #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
16916 | #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
16917 | #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
16918 | #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
16919 | #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
16920 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
16921 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
16922 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
16923 | #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
16924 | #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
16925 | #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
16926 | #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
16927 | #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
16928 | #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
16929 | #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
16930 | #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
16931 | #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
16932 | #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
16933 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
16934 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
16935 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
16936 | //CP_ME2_PIPE1_INT_STATUS |
16937 | #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
16938 | #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
16939 | #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
16940 | #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
16941 | #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
16942 | #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
16943 | #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
16944 | #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
16945 | #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
16946 | #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
16947 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
16948 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
16949 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
16950 | #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
16951 | #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
16952 | #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
16953 | #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
16954 | #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
16955 | #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
16956 | #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
16957 | #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
16958 | #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
16959 | #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
16960 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
16961 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
16962 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
16963 | //CP_ME2_PIPE2_INT_STATUS |
16964 | #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
16965 | #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
16966 | #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
16967 | #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
16968 | #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
16969 | #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
16970 | #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
16971 | #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
16972 | #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
16973 | #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
16974 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
16975 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
16976 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
16977 | #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
16978 | #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
16979 | #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
16980 | #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
16981 | #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
16982 | #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
16983 | #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
16984 | #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
16985 | #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
16986 | #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
16987 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
16988 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
16989 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
16990 | //CP_ME2_PIPE3_INT_STATUS |
16991 | #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
16992 | #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
16993 | #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
16994 | #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
16995 | #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
16996 | #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
16997 | #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
16998 | #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
16999 | #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
17000 | #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
17001 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
17002 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
17003 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
17004 | #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
17005 | #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
17006 | #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
17007 | #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
17008 | #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
17009 | #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
17010 | #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
17011 | #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
17012 | #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
17013 | #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
17014 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
17015 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
17016 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
17017 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
17018 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
17019 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
17020 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
17021 | //CP_GFX_QUEUE_INDEX |
17022 | #define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS__SHIFT 0x0 |
17023 | #define CP_GFX_QUEUE_INDEX__PIPE_ID__SHIFT 0x4 |
17024 | #define CP_GFX_QUEUE_INDEX__QUEUE_ID__SHIFT 0x8 |
17025 | #define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS_MASK 0x00000001L |
17026 | #define CP_GFX_QUEUE_INDEX__PIPE_ID_MASK 0x00000030L |
17027 | #define CP_GFX_QUEUE_INDEX__QUEUE_ID_MASK 0x00000700L |
17028 | //CC_GC_EDC_CONFIG |
17029 | #define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 |
17030 | #define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L |
17031 | //CP_ME1_INT_STAT_DEBUG |
17032 | #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc |
17033 | #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd |
17034 | #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe |
17035 | #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
17036 | #define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 |
17037 | #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 |
17038 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
17039 | #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 |
17040 | #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a |
17041 | #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b |
17042 | #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d |
17043 | #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e |
17044 | #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f |
17045 | #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L |
17046 | #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L |
17047 | #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L |
17048 | #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
17049 | #define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L |
17050 | #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L |
17051 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
17052 | #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L |
17053 | #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L |
17054 | #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L |
17055 | #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L |
17056 | #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L |
17057 | #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L |
17058 | //CP_ME2_INT_STAT_DEBUG |
17059 | #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc |
17060 | #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd |
17061 | #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe |
17062 | #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
17063 | #define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 |
17064 | #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 |
17065 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
17066 | #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 |
17067 | #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a |
17068 | #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b |
17069 | #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d |
17070 | #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e |
17071 | #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f |
17072 | #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L |
17073 | #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L |
17074 | #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L |
17075 | #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
17076 | #define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L |
17077 | #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L |
17078 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
17079 | #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L |
17080 | #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L |
17081 | #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L |
17082 | #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L |
17083 | #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L |
17084 | #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L |
17085 | //CP_ME1_PIPE_PRIORITY_CNTS |
17086 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
17087 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
17088 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
17089 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
17090 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
17091 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
17092 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
17093 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
17094 | //CP_ME1_PIPE0_PRIORITY |
17095 | #define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
17096 | #define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
17097 | //CP_ME1_PIPE1_PRIORITY |
17098 | #define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
17099 | #define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
17100 | //CP_ME1_PIPE2_PRIORITY |
17101 | #define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
17102 | #define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
17103 | //CP_ME1_PIPE3_PRIORITY |
17104 | #define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 |
17105 | #define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L |
17106 | //CP_ME2_PIPE_PRIORITY_CNTS |
17107 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
17108 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
17109 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
17110 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
17111 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
17112 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
17113 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
17114 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
17115 | //CP_ME2_PIPE0_PRIORITY |
17116 | #define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
17117 | #define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
17118 | //CP_ME2_PIPE1_PRIORITY |
17119 | #define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
17120 | #define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
17121 | //CP_ME2_PIPE2_PRIORITY |
17122 | #define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
17123 | #define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
17124 | //CP_ME2_PIPE3_PRIORITY |
17125 | #define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 |
17126 | #define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L |
17127 | //CP_CE_PRGRM_CNTR_START |
17128 | #define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
17129 | #define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL |
17130 | //CP_PFP_PRGRM_CNTR_START |
17131 | #define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
17132 | #define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL |
17133 | //CP_ME_PRGRM_CNTR_START |
17134 | #define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
17135 | #define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL |
17136 | //CP_MEC1_PRGRM_CNTR_START |
17137 | #define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
17138 | #define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL |
17139 | //CP_MEC2_PRGRM_CNTR_START |
17140 | #define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
17141 | #define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL |
17142 | //CP_CE_INTR_ROUTINE_START |
17143 | #define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
17144 | #define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL |
17145 | //CP_PFP_INTR_ROUTINE_START |
17146 | #define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
17147 | #define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL |
17148 | //CP_ME_INTR_ROUTINE_START |
17149 | #define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
17150 | #define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL |
17151 | //CP_MEC1_INTR_ROUTINE_START |
17152 | #define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
17153 | #define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL |
17154 | //CP_MEC2_INTR_ROUTINE_START |
17155 | #define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
17156 | #define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL |
17157 | //CP_CONTEXT_CNTL |
17158 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX__SHIFT 0x0 |
17159 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 |
17160 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX__SHIFT 0x10 |
17161 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 |
17162 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX_MASK 0x00000007L |
17163 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L |
17164 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX_MASK 0x00070000L |
17165 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L |
17166 | //CP_MAX_CONTEXT |
17167 | #define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 |
17168 | #define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L |
17169 | //CP_IQ_WAIT_TIME1 |
17170 | #define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 |
17171 | #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 |
17172 | #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 |
17173 | #define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 |
17174 | #define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL |
17175 | #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L |
17176 | #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L |
17177 | #define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L |
17178 | //CP_IQ_WAIT_TIME2 |
17179 | #define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 |
17180 | #define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 |
17181 | #define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 |
17182 | #define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 |
17183 | #define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL |
17184 | #define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L |
17185 | #define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L |
17186 | #define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L |
17187 | //CP_RB0_BASE_HI |
17188 | #define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
17189 | #define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL |
17190 | //CP_RB1_BASE_HI |
17191 | #define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
17192 | #define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL |
17193 | //CP_VMID_RESET |
17194 | #define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 |
17195 | #define CP_VMID_RESET__PIPE0_QUEUES__SHIFT 0x10 |
17196 | #define CP_VMID_RESET__PIPE1_QUEUES__SHIFT 0x18 |
17197 | #define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL |
17198 | #define CP_VMID_RESET__PIPE0_QUEUES_MASK 0x00FF0000L |
17199 | #define CP_VMID_RESET__PIPE1_QUEUES_MASK 0xFF000000L |
17200 | //CPC_INT_CNTL |
17201 | #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
17202 | #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
17203 | #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
17204 | #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
17205 | #define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
17206 | #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
17207 | #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
17208 | #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
17209 | #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
17210 | #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
17211 | #define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
17212 | #define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
17213 | #define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
17214 | #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
17215 | #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
17216 | #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
17217 | #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
17218 | #define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
17219 | #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
17220 | #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
17221 | #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
17222 | #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
17223 | #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
17224 | #define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
17225 | #define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
17226 | #define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
17227 | //CPC_INT_STATUS |
17228 | #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
17229 | #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
17230 | #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
17231 | #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
17232 | #define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
17233 | #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
17234 | #define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
17235 | #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
17236 | #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
17237 | #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
17238 | #define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
17239 | #define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
17240 | #define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
17241 | #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
17242 | #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
17243 | #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
17244 | #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
17245 | #define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
17246 | #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
17247 | #define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
17248 | #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
17249 | #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
17250 | #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
17251 | #define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
17252 | #define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
17253 | #define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
17254 | //CP_VMID_PREEMPT |
17255 | #define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 |
17256 | #define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 |
17257 | #define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL |
17258 | #define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L |
17259 | //CPC_INT_CNTX_ID |
17260 | #define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 |
17261 | #define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL |
17262 | //CP_PQ_STATUS |
17263 | #define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 |
17264 | #define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 |
17265 | #define CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT 0x2 |
17266 | #define CP_PQ_STATUS__DOORBELL_UPDATED_MODE__SHIFT 0x3 |
17267 | #define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L |
17268 | #define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L |
17269 | #define CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK 0x00000004L |
17270 | #define CP_PQ_STATUS__DOORBELL_UPDATED_MODE_MASK 0x00000008L |
17271 | //CP_MEC1_F32_INT_DIS |
17272 | #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 |
17273 | #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 |
17274 | #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
17275 | #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 |
17276 | #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 |
17277 | #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 |
17278 | #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 |
17279 | #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 |
17280 | #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 |
17281 | #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 |
17282 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa |
17283 | #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb |
17284 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc |
17285 | #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd |
17286 | #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe |
17287 | #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf |
17288 | #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L |
17289 | #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L |
17290 | #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
17291 | #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L |
17292 | #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L |
17293 | #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L |
17294 | #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L |
17295 | #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L |
17296 | #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L |
17297 | #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L |
17298 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L |
17299 | #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L |
17300 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L |
17301 | #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L |
17302 | #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L |
17303 | #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L |
17304 | //CP_MEC2_F32_INT_DIS |
17305 | #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 |
17306 | #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 |
17307 | #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
17308 | #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 |
17309 | #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 |
17310 | #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 |
17311 | #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 |
17312 | #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 |
17313 | #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 |
17314 | #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 |
17315 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa |
17316 | #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb |
17317 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc |
17318 | #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd |
17319 | #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe |
17320 | #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf |
17321 | #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L |
17322 | #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L |
17323 | #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
17324 | #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L |
17325 | #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L |
17326 | #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L |
17327 | #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L |
17328 | #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L |
17329 | #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L |
17330 | #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L |
17331 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L |
17332 | #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L |
17333 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L |
17334 | #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L |
17335 | #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L |
17336 | #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L |
17337 | //CP_VMID_STATUS |
17338 | #define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 |
17339 | #define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 |
17340 | #define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL |
17341 | #define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L |
17342 | //CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO |
17343 | #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc |
17344 | #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L |
17345 | //CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI |
17346 | #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
17347 | #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
17348 | //CPC_SUSPEND_CTX_SAVE_CONTROL |
17349 | #define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 |
17350 | #define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 |
17351 | #define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L |
17352 | #define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L |
17353 | //CPC_SUSPEND_CNTL_STACK_OFFSET |
17354 | #define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 |
17355 | #define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL |
17356 | //CPC_SUSPEND_CNTL_STACK_SIZE |
17357 | #define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE__SHIFT 0xc |
17358 | #define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L |
17359 | //CPC_SUSPEND_WG_STATE_OFFSET |
17360 | #define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 |
17361 | #define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL |
17362 | //CPC_SUSPEND_CTX_SAVE_SIZE |
17363 | #define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE__SHIFT 0xc |
17364 | #define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L |
17365 | //CPC_OS_PIPES |
17366 | #define CPC_OS_PIPES__OS_PIPES__SHIFT 0x0 |
17367 | #define CPC_OS_PIPES__OS_PIPES_MASK 0x000000FFL |
17368 | //CP_SUSPEND_RESUME_REQ |
17369 | #define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ__SHIFT 0x0 |
17370 | #define CP_SUSPEND_RESUME_REQ__RESUME_REQ__SHIFT 0x1 |
17371 | #define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ_MASK 0x00000001L |
17372 | #define CP_SUSPEND_RESUME_REQ__RESUME_REQ_MASK 0x00000002L |
17373 | //CP_SUSPEND_CNTL |
17374 | #define CP_SUSPEND_CNTL__SUSPEND_MODE__SHIFT 0x0 |
17375 | #define CP_SUSPEND_CNTL__SUSPEND_ENABLE__SHIFT 0x1 |
17376 | #define CP_SUSPEND_CNTL__RESUME_LOCK__SHIFT 0x2 |
17377 | #define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE__SHIFT 0x3 |
17378 | #define CP_SUSPEND_CNTL__SUSPEND_MODE_MASK 0x00000001L |
17379 | #define CP_SUSPEND_CNTL__SUSPEND_ENABLE_MASK 0x00000002L |
17380 | #define CP_SUSPEND_CNTL__RESUME_LOCK_MASK 0x00000004L |
17381 | #define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE_MASK 0x00000008L |
17382 | //CP_IQ_WAIT_TIME3 |
17383 | #define CP_IQ_WAIT_TIME3__SUSPEND_QUE__SHIFT 0x0 |
17384 | #define CP_IQ_WAIT_TIME3__SUSPEND_QUE_MASK 0x000000FFL |
17385 | //CPC_DDID_BASE_ADDR_LO |
17386 | #define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6 |
17387 | #define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L |
17388 | //CP_DDID_BASE_ADDR_LO |
17389 | #define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6 |
17390 | #define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L |
17391 | //CPC_DDID_BASE_ADDR_HI |
17392 | #define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
17393 | #define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL |
17394 | //CP_DDID_BASE_ADDR_HI |
17395 | #define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
17396 | #define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL |
17397 | //CPC_DDID_CNTL |
17398 | #define CPC_DDID_CNTL__THRESHOLD__SHIFT 0x0 |
17399 | #define CPC_DDID_CNTL__SIZE__SHIFT 0x10 |
17400 | #define CPC_DDID_CNTL__NO_RING_MEMORY__SHIFT 0x13 |
17401 | #define CPC_DDID_CNTL__POLICY__SHIFT 0x1c |
17402 | #define CPC_DDID_CNTL__MODE__SHIFT 0x1e |
17403 | #define CPC_DDID_CNTL__ENABLE__SHIFT 0x1f |
17404 | #define CPC_DDID_CNTL__THRESHOLD_MASK 0x000000FFL |
17405 | #define CPC_DDID_CNTL__SIZE_MASK 0x00010000L |
17406 | #define CPC_DDID_CNTL__NO_RING_MEMORY_MASK 0x00080000L |
17407 | #define CPC_DDID_CNTL__POLICY_MASK 0x30000000L |
17408 | #define CPC_DDID_CNTL__MODE_MASK 0x40000000L |
17409 | #define CPC_DDID_CNTL__ENABLE_MASK 0x80000000L |
17410 | //CP_DDID_CNTL |
17411 | #define CP_DDID_CNTL__THRESHOLD__SHIFT 0x0 |
17412 | #define CP_DDID_CNTL__SIZE__SHIFT 0x10 |
17413 | #define CP_DDID_CNTL__NO_RING_MEMORY__SHIFT 0x13 |
17414 | #define CP_DDID_CNTL__VMID__SHIFT 0x14 |
17415 | #define CP_DDID_CNTL__VMID_SEL__SHIFT 0x18 |
17416 | #define CP_DDID_CNTL__POLICY__SHIFT 0x1c |
17417 | #define CP_DDID_CNTL__MODE__SHIFT 0x1e |
17418 | #define CP_DDID_CNTL__ENABLE__SHIFT 0x1f |
17419 | #define CP_DDID_CNTL__THRESHOLD_MASK 0x000000FFL |
17420 | #define CP_DDID_CNTL__SIZE_MASK 0x00010000L |
17421 | #define CP_DDID_CNTL__NO_RING_MEMORY_MASK 0x00080000L |
17422 | #define CP_DDID_CNTL__VMID_MASK 0x00F00000L |
17423 | #define CP_DDID_CNTL__VMID_SEL_MASK 0x01000000L |
17424 | #define CP_DDID_CNTL__POLICY_MASK 0x30000000L |
17425 | #define CP_DDID_CNTL__MODE_MASK 0x40000000L |
17426 | #define CP_DDID_CNTL__ENABLE_MASK 0x80000000L |
17427 | //CP_GFX_DDID_INFLIGHT_COUNT |
17428 | #define CP_GFX_DDID_INFLIGHT_COUNT__COUNT__SHIFT 0x0 |
17429 | #define CP_GFX_DDID_INFLIGHT_COUNT__COUNT_MASK 0x0000FFFFL |
17430 | //CP_GFX_DDID_WPTR |
17431 | #define CP_GFX_DDID_WPTR__COUNT__SHIFT 0x0 |
17432 | #define CP_GFX_DDID_WPTR__COUNT_MASK 0x0000FFFFL |
17433 | //CP_GFX_DDID_RPTR |
17434 | #define CP_GFX_DDID_RPTR__COUNT__SHIFT 0x0 |
17435 | #define CP_GFX_DDID_RPTR__COUNT_MASK 0x0000FFFFL |
17436 | //CP_GFX_DDID_DELTA_RPT_COUNT |
17437 | #define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT__SHIFT 0x0 |
17438 | #define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT_MASK 0x000000FFL |
17439 | //CP_GFX_HPD_STATUS0 |
17440 | #define CP_GFX_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 |
17441 | #define CP_GFX_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 |
17442 | #define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 |
17443 | #define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE__SHIFT 0x10 |
17444 | #define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 |
17445 | #define CP_GFX_HPD_STATUS0__SUSPEND_REQ__SHIFT 0x1c |
17446 | #define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID__SHIFT 0x1d |
17447 | #define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID__SHIFT 0x1e |
17448 | #define CP_GFX_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f |
17449 | #define CP_GFX_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL |
17450 | #define CP_GFX_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L |
17451 | #define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L |
17452 | #define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE_MASK 0x00070000L |
17453 | #define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L |
17454 | #define CP_GFX_HPD_STATUS0__SUSPEND_REQ_MASK 0x10000000L |
17455 | #define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID_MASK 0x20000000L |
17456 | #define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID_MASK 0x40000000L |
17457 | #define CP_GFX_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L |
17458 | //CP_GFX_HPD_CONTROL0 |
17459 | #define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE__SHIFT 0x0 |
17460 | #define CP_GFX_HPD_CONTROL0__PIPE_HOLDING__SHIFT 0x4 |
17461 | #define CP_GFX_HPD_CONTROL0__RB_CE_ROQ_CNTL__SHIFT 0x8 |
17462 | #define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE_MASK 0x00000001L |
17463 | #define CP_GFX_HPD_CONTROL0__PIPE_HOLDING_MASK 0x00000010L |
17464 | #define CP_GFX_HPD_CONTROL0__RB_CE_ROQ_CNTL_MASK 0x00000100L |
17465 | //CP_GFX_HPD_OSPRE_FENCE_ADDR_LO |
17466 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO__SHIFT 0x2 |
17467 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
17468 | //CP_GFX_HPD_OSPRE_FENCE_ADDR_HI |
17469 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
17470 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD__SHIFT 0x10 |
17471 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
17472 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD_MASK 0xFFFF0000L |
17473 | //CP_GFX_HPD_OSPRE_FENCE_DATA_LO |
17474 | #define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO__SHIFT 0x0 |
17475 | #define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL |
17476 | //CP_GFX_HPD_OSPRE_FENCE_DATA_HI |
17477 | #define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI__SHIFT 0x0 |
17478 | #define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL |
17479 | //CP_GFX_INDEX_MUTEX |
17480 | #define CP_GFX_INDEX_MUTEX__REQUEST__SHIFT 0x0 |
17481 | #define CP_GFX_INDEX_MUTEX__CLIENTID__SHIFT 0x1 |
17482 | #define CP_GFX_INDEX_MUTEX__REQUEST_MASK 0x00000001L |
17483 | #define CP_GFX_INDEX_MUTEX__CLIENTID_MASK 0x0000000EL |
17484 | //CP_GFX_MQD_BASE_ADDR |
17485 | #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 |
17486 | #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL |
17487 | //CP_GFX_MQD_BASE_ADDR_HI |
17488 | #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
17489 | #define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID__SHIFT 0x1c |
17490 | #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL |
17491 | #define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID_MASK 0xF0000000L |
17492 | //CP_GFX_HQD_ACTIVE |
17493 | #define CP_GFX_HQD_ACTIVE__ACTIVE__SHIFT 0x0 |
17494 | #define CP_GFX_HQD_ACTIVE__ACTIVE_MASK 0x00000001L |
17495 | //CP_GFX_HQD_VMID |
17496 | #define CP_GFX_HQD_VMID__VMID__SHIFT 0x0 |
17497 | #define CP_GFX_HQD_VMID__VMID_MASK 0x0000000FL |
17498 | //CP_GFX_HQD_QUEUE_PRIORITY |
17499 | #define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 |
17500 | #define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL |
17501 | //CP_GFX_HQD_QUANTUM |
17502 | #define CP_GFX_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 |
17503 | #define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x3 |
17504 | #define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 |
17505 | #define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f |
17506 | #define CP_GFX_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L |
17507 | #define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000018L |
17508 | #define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x0000FF00L |
17509 | #define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L |
17510 | //CP_GFX_HQD_BASE |
17511 | #define CP_GFX_HQD_BASE__RB_BASE__SHIFT 0x0 |
17512 | #define CP_GFX_HQD_BASE__RB_BASE_MASK 0xFFFFFFFFL |
17513 | //CP_GFX_HQD_BASE_HI |
17514 | #define CP_GFX_HQD_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
17515 | #define CP_GFX_HQD_BASE_HI__RB_BASE_HI_MASK 0x000000FFL |
17516 | //CP_GFX_HQD_RPTR |
17517 | #define CP_GFX_HQD_RPTR__RB_RPTR__SHIFT 0x0 |
17518 | #define CP_GFX_HQD_RPTR__RB_RPTR_MASK 0x000FFFFFL |
17519 | //CP_GFX_HQD_RPTR_ADDR |
17520 | #define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
17521 | #define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
17522 | //CP_GFX_HQD_RPTR_ADDR_HI |
17523 | #define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
17524 | #define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
17525 | //CP_RB_WPTR_POLL_ADDR_LO |
17526 | #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 |
17527 | #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL |
17528 | //CP_RB_WPTR_POLL_ADDR_HI |
17529 | #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 |
17530 | #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL |
17531 | //CP_RB_DOORBELL_CONTROL |
17532 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 |
17533 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 |
17534 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e |
17535 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f |
17536 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L |
17537 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
17538 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L |
17539 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L |
17540 | //CP_GFX_HQD_OFFSET |
17541 | #define CP_GFX_HQD_OFFSET__RB_OFFSET__SHIFT 0x0 |
17542 | #define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET__SHIFT 0x1f |
17543 | #define CP_GFX_HQD_OFFSET__RB_OFFSET_MASK 0x000FFFFFL |
17544 | #define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET_MASK 0x80000000L |
17545 | //CP_GFX_HQD_CNTL |
17546 | #define CP_GFX_HQD_CNTL__RB_BUFSZ__SHIFT 0x0 |
17547 | #define CP_GFX_HQD_CNTL__RB_BLKSZ__SHIFT 0x8 |
17548 | #define CP_GFX_HQD_CNTL__RB_NON_PRIV__SHIFT 0xf |
17549 | #define CP_GFX_HQD_CNTL__BUF_SWAP__SHIFT 0x10 |
17550 | #define CP_GFX_HQD_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
17551 | #define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
17552 | #define CP_GFX_HQD_CNTL__CACHE_POLICY__SHIFT 0x18 |
17553 | #define CP_GFX_HQD_CNTL__RB_VOLATILE__SHIFT 0x1a |
17554 | #define CP_GFX_HQD_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
17555 | #define CP_GFX_HQD_CNTL__RB_EXE__SHIFT 0x1c |
17556 | #define CP_GFX_HQD_CNTL__KMD_QUEUE__SHIFT 0x1d |
17557 | #define CP_GFX_HQD_CNTL__CE_HQD_NEQ_RB_HQD__SHIFT 0x1e |
17558 | #define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
17559 | #define CP_GFX_HQD_CNTL__RB_BUFSZ_MASK 0x0000003FL |
17560 | #define CP_GFX_HQD_CNTL__RB_BLKSZ_MASK 0x00003F00L |
17561 | #define CP_GFX_HQD_CNTL__RB_NON_PRIV_MASK 0x00008000L |
17562 | #define CP_GFX_HQD_CNTL__BUF_SWAP_MASK 0x00030000L |
17563 | #define CP_GFX_HQD_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
17564 | #define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
17565 | #define CP_GFX_HQD_CNTL__CACHE_POLICY_MASK 0x03000000L |
17566 | #define CP_GFX_HQD_CNTL__RB_VOLATILE_MASK 0x04000000L |
17567 | #define CP_GFX_HQD_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
17568 | #define CP_GFX_HQD_CNTL__RB_EXE_MASK 0x10000000L |
17569 | #define CP_GFX_HQD_CNTL__KMD_QUEUE_MASK 0x20000000L |
17570 | #define CP_GFX_HQD_CNTL__CE_HQD_NEQ_RB_HQD_MASK 0x40000000L |
17571 | #define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
17572 | //CP_GFX_HQD_CSMD_RPTR |
17573 | #define CP_GFX_HQD_CSMD_RPTR__RB_RPTR__SHIFT 0x0 |
17574 | #define CP_GFX_HQD_CSMD_RPTR__RB_RPTR_MASK 0x000FFFFFL |
17575 | //CP_GFX_HQD_WPTR |
17576 | #define CP_GFX_HQD_WPTR__RB_WPTR__SHIFT 0x0 |
17577 | #define CP_GFX_HQD_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
17578 | //CP_GFX_HQD_WPTR_HI |
17579 | #define CP_GFX_HQD_WPTR_HI__RB_WPTR__SHIFT 0x0 |
17580 | #define CP_GFX_HQD_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
17581 | //CP_GFX_HQD_DEQUEUE_REQUEST |
17582 | #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 |
17583 | #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 |
17584 | #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 |
17585 | #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa |
17586 | #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000001L |
17587 | #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L |
17588 | #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L |
17589 | #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L |
17590 | //CP_GFX_HQD_MAPPED |
17591 | #define CP_GFX_HQD_MAPPED__MAPPED__SHIFT 0x0 |
17592 | #define CP_GFX_HQD_MAPPED__MAPPED_MASK 0x00000001L |
17593 | //CP_GFX_HQD_QUE_MGR_CONTROL |
17594 | #define CP_GFX_HQD_QUE_MGR_CONTROL__CONTROL__SHIFT 0x0 |
17595 | #define CP_GFX_HQD_QUE_MGR_CONTROL__CONTROL_MASK 0x00FFFFFFL |
17596 | //CP_GFX_HQD_HQ_STATUS0 |
17597 | #define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 |
17598 | #define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS__SHIFT 0x4 |
17599 | #define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK__SHIFT 0x6 |
17600 | #define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e |
17601 | #define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000001L |
17602 | #define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS_MASK 0x00000030L |
17603 | #define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK_MASK 0x00000040L |
17604 | #define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L |
17605 | //CP_GFX_HQD_HQ_CONTROL0 |
17606 | #define CP_GFX_HQD_HQ_CONTROL0__COMMAND__SHIFT 0x0 |
17607 | #define CP_GFX_HQD_HQ_CONTROL0__COMMAND_MASK 0x0000000FL |
17608 | //CP_GFX_MQD_CONTROL |
17609 | #define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0 |
17610 | #define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 |
17611 | #define CP_GFX_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc |
17612 | #define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd |
17613 | #define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 |
17614 | #define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 |
17615 | #define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL |
17616 | #define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L |
17617 | #define CP_GFX_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L |
17618 | #define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L |
17619 | #define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L |
17620 | #define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x03000000L |
17621 | //CP_HQD_GFX_CONTROL |
17622 | #define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0 |
17623 | #define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4 |
17624 | #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf |
17625 | #define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL |
17626 | #define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L |
17627 | #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L |
17628 | //CP_HQD_GFX_STATUS |
17629 | #define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0 |
17630 | #define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL |
17631 | //CP_GFX_HQD_CE_RPTR_WR |
17632 | #define CP_GFX_HQD_CE_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 |
17633 | #define CP_GFX_HQD_CE_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL |
17634 | //CP_GFX_HQD_CE_BASE |
17635 | #define CP_GFX_HQD_CE_BASE__RB_BASE__SHIFT 0x0 |
17636 | #define CP_GFX_HQD_CE_BASE__RB_BASE_MASK 0xFFFFFFFFL |
17637 | //CP_GFX_HQD_CE_BASE_HI |
17638 | #define CP_GFX_HQD_CE_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
17639 | #define CP_GFX_HQD_CE_BASE_HI__RB_BASE_HI_MASK 0x000000FFL |
17640 | //CP_GFX_HQD_CE_RPTR |
17641 | #define CP_GFX_HQD_CE_RPTR__RB_RPTR__SHIFT 0x0 |
17642 | #define CP_GFX_HQD_CE_RPTR__RB_RPTR_MASK 0x000FFFFFL |
17643 | //CP_GFX_HQD_CE_RPTR_ADDR |
17644 | #define CP_GFX_HQD_CE_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
17645 | #define CP_GFX_HQD_CE_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
17646 | //CP_GFX_HQD_CE_RPTR_ADDR_HI |
17647 | #define CP_GFX_HQD_CE_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
17648 | #define CP_GFX_HQD_CE_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
17649 | //CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO |
17650 | #define CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 |
17651 | #define CP_GFX_HQD_CE_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL |
17652 | //CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI |
17653 | #define CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 |
17654 | #define CP_GFX_HQD_CE_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL |
17655 | //CP_GFX_HQD_CE_OFFSET |
17656 | #define CP_GFX_HQD_CE_OFFSET__RB_OFFSET__SHIFT 0x0 |
17657 | #define CP_GFX_HQD_CE_OFFSET__DISABLE_RB_OFFSET__SHIFT 0x1f |
17658 | #define CP_GFX_HQD_CE_OFFSET__RB_OFFSET_MASK 0x000FFFFFL |
17659 | #define CP_GFX_HQD_CE_OFFSET__DISABLE_RB_OFFSET_MASK 0x80000000L |
17660 | //CP_GFX_HQD_CE_CNTL |
17661 | #define CP_GFX_HQD_CE_CNTL__RB_BUFSZ__SHIFT 0x0 |
17662 | #define CP_GFX_HQD_CE_CNTL__RB_BLKSZ__SHIFT 0x8 |
17663 | #define CP_GFX_HQD_CE_CNTL__RB_NON_PRIV__SHIFT 0xf |
17664 | #define CP_GFX_HQD_CE_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
17665 | #define CP_GFX_HQD_CE_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
17666 | #define CP_GFX_HQD_CE_CNTL__CACHE_POLICY__SHIFT 0x18 |
17667 | #define CP_GFX_HQD_CE_CNTL__RB_VOLATILE__SHIFT 0x1a |
17668 | #define CP_GFX_HQD_CE_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
17669 | #define CP_GFX_HQD_CE_CNTL__RB_EXE__SHIFT 0x1c |
17670 | #define CP_GFX_HQD_CE_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
17671 | #define CP_GFX_HQD_CE_CNTL__RB_BUFSZ_MASK 0x0000003FL |
17672 | #define CP_GFX_HQD_CE_CNTL__RB_BLKSZ_MASK 0x00003F00L |
17673 | #define CP_GFX_HQD_CE_CNTL__RB_NON_PRIV_MASK 0x00008000L |
17674 | #define CP_GFX_HQD_CE_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
17675 | #define CP_GFX_HQD_CE_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
17676 | #define CP_GFX_HQD_CE_CNTL__CACHE_POLICY_MASK 0x03000000L |
17677 | #define CP_GFX_HQD_CE_CNTL__RB_VOLATILE_MASK 0x04000000L |
17678 | #define CP_GFX_HQD_CE_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
17679 | #define CP_GFX_HQD_CE_CNTL__RB_EXE_MASK 0x10000000L |
17680 | #define CP_GFX_HQD_CE_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
17681 | //CP_GFX_HQD_CE_CSMD_RPTR |
17682 | #define CP_GFX_HQD_CE_CSMD_RPTR__RB_RPTR__SHIFT 0x0 |
17683 | #define CP_GFX_HQD_CE_CSMD_RPTR__RB_RPTR_MASK 0x000FFFFFL |
17684 | //CP_GFX_HQD_CE_WPTR |
17685 | #define CP_GFX_HQD_CE_WPTR__RB_WPTR__SHIFT 0x0 |
17686 | #define CP_GFX_HQD_CE_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
17687 | //CP_GFX_HQD_CE_WPTR_HI |
17688 | #define CP_GFX_HQD_CE_WPTR_HI__RB_WPTR__SHIFT 0x0 |
17689 | #define CP_GFX_HQD_CE_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
17690 | //CP_CE_DOORBELL_CONTROL |
17691 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 |
17692 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 |
17693 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e |
17694 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f |
17695 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L |
17696 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
17697 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L |
17698 | #define CP_CE_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L |
17699 | //CP_DMA_WATCH0_ADDR_LO |
17700 | #define CP_DMA_WATCH0_ADDR_LO__RSVD__SHIFT 0x0 |
17701 | #define CP_DMA_WATCH0_ADDR_LO__ADDR_LO__SHIFT 0x7 |
17702 | #define CP_DMA_WATCH0_ADDR_LO__RSVD_MASK 0x0000007FL |
17703 | #define CP_DMA_WATCH0_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L |
17704 | //CP_DMA_WATCH0_ADDR_HI |
17705 | #define CP_DMA_WATCH0_ADDR_HI__ADDR_HI__SHIFT 0x0 |
17706 | #define CP_DMA_WATCH0_ADDR_HI__RSVD__SHIFT 0x10 |
17707 | #define CP_DMA_WATCH0_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
17708 | #define CP_DMA_WATCH0_ADDR_HI__RSVD_MASK 0xFFFF0000L |
17709 | //CP_DMA_WATCH0_MASK |
17710 | #define CP_DMA_WATCH0_MASK__RSVD__SHIFT 0x0 |
17711 | #define CP_DMA_WATCH0_MASK__MASK__SHIFT 0x7 |
17712 | #define CP_DMA_WATCH0_MASK__RSVD_MASK 0x0000007FL |
17713 | #define CP_DMA_WATCH0_MASK__MASK_MASK 0xFFFFFF80L |
17714 | //CP_DMA_WATCH0_CNTL |
17715 | #define CP_DMA_WATCH0_CNTL__VMID__SHIFT 0x0 |
17716 | #define CP_DMA_WATCH0_CNTL__RSVD1__SHIFT 0x4 |
17717 | #define CP_DMA_WATCH0_CNTL__WATCH_READS__SHIFT 0x8 |
17718 | #define CP_DMA_WATCH0_CNTL__WATCH_WRITES__SHIFT 0x9 |
17719 | #define CP_DMA_WATCH0_CNTL__ANY_VMID__SHIFT 0xa |
17720 | #define CP_DMA_WATCH0_CNTL__RSVD2__SHIFT 0xb |
17721 | #define CP_DMA_WATCH0_CNTL__VMID_MASK 0x0000000FL |
17722 | #define CP_DMA_WATCH0_CNTL__RSVD1_MASK 0x000000F0L |
17723 | #define CP_DMA_WATCH0_CNTL__WATCH_READS_MASK 0x00000100L |
17724 | #define CP_DMA_WATCH0_CNTL__WATCH_WRITES_MASK 0x00000200L |
17725 | #define CP_DMA_WATCH0_CNTL__ANY_VMID_MASK 0x00000400L |
17726 | #define CP_DMA_WATCH0_CNTL__RSVD2_MASK 0xFFFFF800L |
17727 | //CP_DMA_WATCH1_ADDR_LO |
17728 | #define CP_DMA_WATCH1_ADDR_LO__RSVD__SHIFT 0x0 |
17729 | #define CP_DMA_WATCH1_ADDR_LO__ADDR_LO__SHIFT 0x7 |
17730 | #define CP_DMA_WATCH1_ADDR_LO__RSVD_MASK 0x0000007FL |
17731 | #define CP_DMA_WATCH1_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L |
17732 | //CP_DMA_WATCH1_ADDR_HI |
17733 | #define CP_DMA_WATCH1_ADDR_HI__ADDR_HI__SHIFT 0x0 |
17734 | #define CP_DMA_WATCH1_ADDR_HI__RSVD__SHIFT 0x10 |
17735 | #define CP_DMA_WATCH1_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
17736 | #define CP_DMA_WATCH1_ADDR_HI__RSVD_MASK 0xFFFF0000L |
17737 | //CP_DMA_WATCH1_MASK |
17738 | #define CP_DMA_WATCH1_MASK__RSVD__SHIFT 0x0 |
17739 | #define CP_DMA_WATCH1_MASK__MASK__SHIFT 0x7 |
17740 | #define CP_DMA_WATCH1_MASK__RSVD_MASK 0x0000007FL |
17741 | #define CP_DMA_WATCH1_MASK__MASK_MASK 0xFFFFFF80L |
17742 | //CP_DMA_WATCH1_CNTL |
17743 | #define CP_DMA_WATCH1_CNTL__VMID__SHIFT 0x0 |
17744 | #define CP_DMA_WATCH1_CNTL__RSVD1__SHIFT 0x4 |
17745 | #define CP_DMA_WATCH1_CNTL__WATCH_READS__SHIFT 0x8 |
17746 | #define CP_DMA_WATCH1_CNTL__WATCH_WRITES__SHIFT 0x9 |
17747 | #define CP_DMA_WATCH1_CNTL__ANY_VMID__SHIFT 0xa |
17748 | #define CP_DMA_WATCH1_CNTL__RSVD2__SHIFT 0xb |
17749 | #define CP_DMA_WATCH1_CNTL__VMID_MASK 0x0000000FL |
17750 | #define CP_DMA_WATCH1_CNTL__RSVD1_MASK 0x000000F0L |
17751 | #define CP_DMA_WATCH1_CNTL__WATCH_READS_MASK 0x00000100L |
17752 | #define CP_DMA_WATCH1_CNTL__WATCH_WRITES_MASK 0x00000200L |
17753 | #define CP_DMA_WATCH1_CNTL__ANY_VMID_MASK 0x00000400L |
17754 | #define CP_DMA_WATCH1_CNTL__RSVD2_MASK 0xFFFFF800L |
17755 | //CP_DMA_WATCH2_ADDR_LO |
17756 | #define CP_DMA_WATCH2_ADDR_LO__RSVD__SHIFT 0x0 |
17757 | #define CP_DMA_WATCH2_ADDR_LO__ADDR_LO__SHIFT 0x7 |
17758 | #define CP_DMA_WATCH2_ADDR_LO__RSVD_MASK 0x0000007FL |
17759 | #define CP_DMA_WATCH2_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L |
17760 | //CP_DMA_WATCH2_ADDR_HI |
17761 | #define CP_DMA_WATCH2_ADDR_HI__ADDR_HI__SHIFT 0x0 |
17762 | #define CP_DMA_WATCH2_ADDR_HI__RSVD__SHIFT 0x10 |
17763 | #define CP_DMA_WATCH2_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
17764 | #define CP_DMA_WATCH2_ADDR_HI__RSVD_MASK 0xFFFF0000L |
17765 | //CP_DMA_WATCH2_MASK |
17766 | #define CP_DMA_WATCH2_MASK__RSVD__SHIFT 0x0 |
17767 | #define CP_DMA_WATCH2_MASK__MASK__SHIFT 0x7 |
17768 | #define CP_DMA_WATCH2_MASK__RSVD_MASK 0x0000007FL |
17769 | #define CP_DMA_WATCH2_MASK__MASK_MASK 0xFFFFFF80L |
17770 | //CP_DMA_WATCH2_CNTL |
17771 | #define CP_DMA_WATCH2_CNTL__VMID__SHIFT 0x0 |
17772 | #define CP_DMA_WATCH2_CNTL__RSVD1__SHIFT 0x4 |
17773 | #define CP_DMA_WATCH2_CNTL__WATCH_READS__SHIFT 0x8 |
17774 | #define CP_DMA_WATCH2_CNTL__WATCH_WRITES__SHIFT 0x9 |
17775 | #define CP_DMA_WATCH2_CNTL__ANY_VMID__SHIFT 0xa |
17776 | #define CP_DMA_WATCH2_CNTL__RSVD2__SHIFT 0xb |
17777 | #define CP_DMA_WATCH2_CNTL__VMID_MASK 0x0000000FL |
17778 | #define CP_DMA_WATCH2_CNTL__RSVD1_MASK 0x000000F0L |
17779 | #define CP_DMA_WATCH2_CNTL__WATCH_READS_MASK 0x00000100L |
17780 | #define CP_DMA_WATCH2_CNTL__WATCH_WRITES_MASK 0x00000200L |
17781 | #define CP_DMA_WATCH2_CNTL__ANY_VMID_MASK 0x00000400L |
17782 | #define CP_DMA_WATCH2_CNTL__RSVD2_MASK 0xFFFFF800L |
17783 | //CP_DMA_WATCH3_ADDR_LO |
17784 | #define CP_DMA_WATCH3_ADDR_LO__RSVD__SHIFT 0x0 |
17785 | #define CP_DMA_WATCH3_ADDR_LO__ADDR_LO__SHIFT 0x7 |
17786 | #define CP_DMA_WATCH3_ADDR_LO__RSVD_MASK 0x0000007FL |
17787 | #define CP_DMA_WATCH3_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L |
17788 | //CP_DMA_WATCH3_ADDR_HI |
17789 | #define CP_DMA_WATCH3_ADDR_HI__ADDR_HI__SHIFT 0x0 |
17790 | #define CP_DMA_WATCH3_ADDR_HI__RSVD__SHIFT 0x10 |
17791 | #define CP_DMA_WATCH3_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
17792 | #define CP_DMA_WATCH3_ADDR_HI__RSVD_MASK 0xFFFF0000L |
17793 | //CP_DMA_WATCH3_MASK |
17794 | #define CP_DMA_WATCH3_MASK__RSVD__SHIFT 0x0 |
17795 | #define CP_DMA_WATCH3_MASK__MASK__SHIFT 0x7 |
17796 | #define CP_DMA_WATCH3_MASK__RSVD_MASK 0x0000007FL |
17797 | #define CP_DMA_WATCH3_MASK__MASK_MASK 0xFFFFFF80L |
17798 | //CP_DMA_WATCH3_CNTL |
17799 | #define CP_DMA_WATCH3_CNTL__VMID__SHIFT 0x0 |
17800 | #define CP_DMA_WATCH3_CNTL__RSVD1__SHIFT 0x4 |
17801 | #define CP_DMA_WATCH3_CNTL__WATCH_READS__SHIFT 0x8 |
17802 | #define CP_DMA_WATCH3_CNTL__WATCH_WRITES__SHIFT 0x9 |
17803 | #define CP_DMA_WATCH3_CNTL__ANY_VMID__SHIFT 0xa |
17804 | #define CP_DMA_WATCH3_CNTL__RSVD2__SHIFT 0xb |
17805 | #define CP_DMA_WATCH3_CNTL__VMID_MASK 0x0000000FL |
17806 | #define CP_DMA_WATCH3_CNTL__RSVD1_MASK 0x000000F0L |
17807 | #define CP_DMA_WATCH3_CNTL__WATCH_READS_MASK 0x00000100L |
17808 | #define CP_DMA_WATCH3_CNTL__WATCH_WRITES_MASK 0x00000200L |
17809 | #define CP_DMA_WATCH3_CNTL__ANY_VMID_MASK 0x00000400L |
17810 | #define CP_DMA_WATCH3_CNTL__RSVD2_MASK 0xFFFFF800L |
17811 | //CP_DMA_WATCH_STAT_ADDR_LO |
17812 | #define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO__SHIFT 0x2 |
17813 | #define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
17814 | //CP_DMA_WATCH_STAT_ADDR_HI |
17815 | #define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI__SHIFT 0x0 |
17816 | #define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
17817 | //CP_DMA_WATCH_STAT |
17818 | #define CP_DMA_WATCH_STAT__VMID__SHIFT 0x0 |
17819 | #define CP_DMA_WATCH_STAT__QUEUE_ID__SHIFT 0x4 |
17820 | #define CP_DMA_WATCH_STAT__CLIENT_ID__SHIFT 0x8 |
17821 | #define CP_DMA_WATCH_STAT__PIPE__SHIFT 0xc |
17822 | #define CP_DMA_WATCH_STAT__WATCH_ID__SHIFT 0x10 |
17823 | #define CP_DMA_WATCH_STAT__RD_WR__SHIFT 0x14 |
17824 | #define CP_DMA_WATCH_STAT__TRAP_FLAG__SHIFT 0x1f |
17825 | #define CP_DMA_WATCH_STAT__VMID_MASK 0x0000000FL |
17826 | #define CP_DMA_WATCH_STAT__QUEUE_ID_MASK 0x00000070L |
17827 | #define CP_DMA_WATCH_STAT__CLIENT_ID_MASK 0x00000700L |
17828 | #define CP_DMA_WATCH_STAT__PIPE_MASK 0x00003000L |
17829 | #define CP_DMA_WATCH_STAT__WATCH_ID_MASK 0x00030000L |
17830 | #define CP_DMA_WATCH_STAT__RD_WR_MASK 0x00100000L |
17831 | #define CP_DMA_WATCH_STAT__TRAP_FLAG_MASK 0x80000000L |
17832 | //CP_PFP_JT_STAT |
17833 | #define CP_PFP_JT_STAT__JT_LOADED__SHIFT 0x0 |
17834 | #define CP_PFP_JT_STAT__WR_MASK__SHIFT 0x10 |
17835 | #define CP_PFP_JT_STAT__JT_LOADED_MASK 0x00000003L |
17836 | #define CP_PFP_JT_STAT__WR_MASK_MASK 0x00030000L |
17837 | //CP_CE_JT_STAT |
17838 | #define CP_CE_JT_STAT__JT_LOADED__SHIFT 0x0 |
17839 | #define CP_CE_JT_STAT__WR_MASK__SHIFT 0x10 |
17840 | #define CP_CE_JT_STAT__JT_LOADED_MASK 0x00000003L |
17841 | #define CP_CE_JT_STAT__WR_MASK_MASK 0x00030000L |
17842 | //CP_MEC_JT_STAT |
17843 | #define CP_MEC_JT_STAT__JT_LOADED__SHIFT 0x0 |
17844 | #define CP_MEC_JT_STAT__WR_MASK__SHIFT 0x10 |
17845 | #define CP_MEC_JT_STAT__JT_LOADED_MASK 0x000000FFL |
17846 | #define CP_MEC_JT_STAT__WR_MASK_MASK 0x00FF0000L |
17847 | //CP_FETCHER_SOURCE |
17848 | #define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0 |
17849 | #define CP_FETCHER_SOURCE__ME_SRC_MASK 0x00000001L |
17850 | //CP_CE_CS_PARTITION_INDEX |
17851 | #define CP_CE_CS_PARTITION_INDEX__CS1_INDEX__SHIFT 0x0 |
17852 | #define CP_CE_CS_PARTITION_INDEX__CS1_INDEX_MASK 0x0001FFFFL |
17853 | //CP_RB_DOORBELL_CLEAR |
17854 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0 |
17855 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8 |
17856 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9 |
17857 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa |
17858 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb |
17859 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc |
17860 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd |
17861 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L |
17862 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L |
17863 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L |
17864 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L |
17865 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L |
17866 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L |
17867 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L |
17868 | //CP_RB0_ACTIVE |
17869 | #define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0 |
17870 | #define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L |
17871 | //CP_RB_ACTIVE |
17872 | #define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0 |
17873 | #define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L |
17874 | //CP_RB1_ACTIVE |
17875 | #define CP_RB1_ACTIVE__ACTIVE__SHIFT 0x0 |
17876 | #define CP_RB1_ACTIVE__ACTIVE_MASK 0x00000001L |
17877 | //CP_RB_STATUS |
17878 | #define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0 |
17879 | #define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1 |
17880 | #define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L |
17881 | #define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L |
17882 | //CPG_RCIU_CAM_INDEX |
17883 | #define CPG_RCIU_CAM_INDEX__INDEX__SHIFT 0x0 |
17884 | #define CPG_RCIU_CAM_INDEX__INDEX_MASK 0x0000001FL |
17885 | //CPG_RCIU_CAM_DATA |
17886 | #define CPG_RCIU_CAM_DATA__DATA__SHIFT 0x0 |
17887 | #define CPG_RCIU_CAM_DATA__DATA_MASK 0xFFFFFFFFL |
17888 | //CPG_RCIU_CAM_DATA_PHASE0 |
17889 | #define CPG_RCIU_CAM_DATA_PHASE0__ADDR__SHIFT 0x0 |
17890 | #define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN__SHIFT 0x18 |
17891 | #define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN__SHIFT 0x19 |
17892 | #define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR__SHIFT 0x1f |
17893 | #define CPG_RCIU_CAM_DATA_PHASE0__ADDR_MASK 0x0003FFFFL |
17894 | #define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN_MASK 0x01000000L |
17895 | #define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN_MASK 0x02000000L |
17896 | #define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR_MASK 0x80000000L |
17897 | //CPG_RCIU_CAM_DATA_PHASE1 |
17898 | #define CPG_RCIU_CAM_DATA_PHASE1__MASK__SHIFT 0x0 |
17899 | #define CPG_RCIU_CAM_DATA_PHASE1__MASK_MASK 0xFFFFFFFFL |
17900 | //CPG_RCIU_CAM_DATA_PHASE2 |
17901 | #define CPG_RCIU_CAM_DATA_PHASE2__VALUE__SHIFT 0x0 |
17902 | #define CPG_RCIU_CAM_DATA_PHASE2__VALUE_MASK 0xFFFFFFFFL |
17903 | //CP_GPU_TIMESTAMP_OFFSET_LO |
17904 | #define CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO__SHIFT 0x0 |
17905 | #define CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO_MASK 0xFFFFFFFFL |
17906 | //CP_GPU_TIMESTAMP_OFFSET_HI |
17907 | #define CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI__SHIFT 0x0 |
17908 | #define CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI_MASK 0xFFFFFFFFL |
17909 | //CPF_GCR_CNTL |
17910 | #define CPF_GCR_CNTL__GCR_GL_CMD__SHIFT 0x0 |
17911 | #define CPF_GCR_CNTL__GCR_GL_CMD_MASK 0x0007FFFFL |
17912 | //CPG_UTCL1_STATUS |
17913 | #define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
17914 | #define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
17915 | #define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
17916 | #define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
17917 | #define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
17918 | #define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
17919 | #define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
17920 | #define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
17921 | #define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
17922 | #define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
17923 | #define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
17924 | #define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
17925 | //CPC_UTCL1_STATUS |
17926 | #define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
17927 | #define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
17928 | #define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
17929 | #define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
17930 | #define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
17931 | #define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
17932 | #define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
17933 | #define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
17934 | #define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
17935 | #define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
17936 | #define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
17937 | #define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
17938 | //CPF_UTCL1_STATUS |
17939 | #define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
17940 | #define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
17941 | #define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
17942 | #define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
17943 | #define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
17944 | #define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
17945 | #define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
17946 | #define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
17947 | #define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
17948 | #define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
17949 | #define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
17950 | #define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
17951 | //CP_SD_CNTL |
17952 | #define CP_SD_CNTL__CPF_EN__SHIFT 0x0 |
17953 | #define CP_SD_CNTL__CPG_EN__SHIFT 0x1 |
17954 | #define CP_SD_CNTL__CPC_EN__SHIFT 0x2 |
17955 | #define CP_SD_CNTL__RLC_EN__SHIFT 0x3 |
17956 | #define CP_SD_CNTL__SPI_EN__SHIFT 0x4 |
17957 | #define CP_SD_CNTL__GE_EN__SHIFT 0x5 |
17958 | #define CP_SD_CNTL__UTCL1_EN__SHIFT 0x6 |
17959 | #define CP_SD_CNTL__EA_EN__SHIFT 0x9 |
17960 | #define CP_SD_CNTL__SDMA_EN__SHIFT 0xa |
17961 | #define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE__SHIFT 0x1f |
17962 | #define CP_SD_CNTL__CPF_EN_MASK 0x00000001L |
17963 | #define CP_SD_CNTL__CPG_EN_MASK 0x00000002L |
17964 | #define CP_SD_CNTL__CPC_EN_MASK 0x00000004L |
17965 | #define CP_SD_CNTL__RLC_EN_MASK 0x00000008L |
17966 | #define CP_SD_CNTL__SPI_EN_MASK 0x00000010L |
17967 | #define CP_SD_CNTL__GE_EN_MASK 0x00000020L |
17968 | #define CP_SD_CNTL__UTCL1_EN_MASK 0x00000040L |
17969 | #define CP_SD_CNTL__EA_EN_MASK 0x00000200L |
17970 | #define CP_SD_CNTL__SDMA_EN_MASK 0x00000400L |
17971 | #define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE_MASK 0x80000000L |
17972 | //CP_SOFT_RESET_CNTL |
17973 | #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0 |
17974 | #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1 |
17975 | #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2 |
17976 | #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3 |
17977 | #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4 |
17978 | #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5 |
17979 | #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6 |
17980 | #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L |
17981 | #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L |
17982 | #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L |
17983 | #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L |
17984 | #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L |
17985 | #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L |
17986 | #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L |
17987 | //CP_CPC_GFX_CNTL |
17988 | #define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0 |
17989 | #define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3 |
17990 | #define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5 |
17991 | #define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7 |
17992 | #define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L |
17993 | #define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L |
17994 | #define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L |
17995 | #define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L |
17996 | |
17997 | |
17998 | // addressBlock: gc_spipdec |
17999 | //SPI_ARB_PRIORITY |
18000 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 |
18001 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 |
18002 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 |
18003 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 |
18004 | #define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc |
18005 | #define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe |
18006 | #define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 |
18007 | #define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 |
18008 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L |
18009 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L |
18010 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L |
18011 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L |
18012 | #define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L |
18013 | #define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L |
18014 | #define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L |
18015 | #define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L |
18016 | //SPI_ARB_CYCLES_0 |
18017 | #define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 |
18018 | #define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 |
18019 | #define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL |
18020 | #define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L |
18021 | //SPI_ARB_CYCLES_1 |
18022 | #define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 |
18023 | #define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 |
18024 | #define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL |
18025 | #define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L |
18026 | //SPI_WCL_PIPE_PERCENT_GFX |
18027 | #define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 |
18028 | #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc |
18029 | #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 |
18030 | #define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL |
18031 | #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L |
18032 | #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L |
18033 | //SPI_WCL_PIPE_PERCENT_HP3D |
18034 | #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 |
18035 | #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc |
18036 | #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 |
18037 | #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL |
18038 | #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L |
18039 | #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L |
18040 | //SPI_WCL_PIPE_PERCENT_CS0 |
18041 | #define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 |
18042 | #define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL |
18043 | //SPI_WCL_PIPE_PERCENT_CS1 |
18044 | #define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 |
18045 | #define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL |
18046 | //SPI_WCL_PIPE_PERCENT_CS2 |
18047 | #define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 |
18048 | #define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL |
18049 | //SPI_WCL_PIPE_PERCENT_CS3 |
18050 | #define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 |
18051 | #define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL |
18052 | //SPI_GDBG_WAVE_CNTL |
18053 | #define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 |
18054 | #define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1 |
18055 | #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L |
18056 | #define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x0001FFFEL |
18057 | //SPI_GDBG_TRAP_MASK |
18058 | #define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0 |
18059 | #define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9 |
18060 | #define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x01FFL |
18061 | #define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x0200L |
18062 | //SPI_GDBG_WAVE_CNTL2 |
18063 | #define SPI_GDBG_WAVE_CNTL2__VMID_MASK__SHIFT 0x0 |
18064 | #define SPI_GDBG_WAVE_CNTL2__MODE__SHIFT 0x10 |
18065 | #define SPI_GDBG_WAVE_CNTL2__VMID_MASK_MASK 0x0000FFFFL |
18066 | #define SPI_GDBG_WAVE_CNTL2__MODE_MASK 0x00030000L |
18067 | //SPI_COMPUTE_QUEUE_RESET |
18068 | #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 |
18069 | #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L |
18070 | //SPI_RESOURCE_RESERVE_CU_0 |
18071 | #define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 |
18072 | #define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 |
18073 | #define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 |
18074 | #define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc |
18075 | #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf |
18076 | #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL |
18077 | #define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L |
18078 | #define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L |
18079 | #define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L |
18080 | #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L |
18081 | //SPI_RESOURCE_RESERVE_CU_1 |
18082 | #define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 |
18083 | #define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 |
18084 | #define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 |
18085 | #define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc |
18086 | #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf |
18087 | #define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL |
18088 | #define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L |
18089 | #define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L |
18090 | #define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L |
18091 | #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L |
18092 | //SPI_RESOURCE_RESERVE_CU_2 |
18093 | #define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 |
18094 | #define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 |
18095 | #define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 |
18096 | #define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc |
18097 | #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf |
18098 | #define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL |
18099 | #define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L |
18100 | #define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L |
18101 | #define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L |
18102 | #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L |
18103 | //SPI_RESOURCE_RESERVE_CU_3 |
18104 | #define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 |
18105 | #define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 |
18106 | #define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 |
18107 | #define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc |
18108 | #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf |
18109 | #define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL |
18110 | #define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L |
18111 | #define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L |
18112 | #define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L |
18113 | #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L |
18114 | //SPI_RESOURCE_RESERVE_CU_4 |
18115 | #define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 |
18116 | #define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 |
18117 | #define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 |
18118 | #define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc |
18119 | #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf |
18120 | #define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL |
18121 | #define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L |
18122 | #define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L |
18123 | #define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L |
18124 | #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L |
18125 | //SPI_RESOURCE_RESERVE_CU_5 |
18126 | #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 |
18127 | #define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 |
18128 | #define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 |
18129 | #define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc |
18130 | #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf |
18131 | #define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL |
18132 | #define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L |
18133 | #define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L |
18134 | #define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L |
18135 | #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L |
18136 | //SPI_RESOURCE_RESERVE_CU_6 |
18137 | #define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 |
18138 | #define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 |
18139 | #define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 |
18140 | #define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc |
18141 | #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf |
18142 | #define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL |
18143 | #define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L |
18144 | #define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L |
18145 | #define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L |
18146 | #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L |
18147 | //SPI_RESOURCE_RESERVE_CU_7 |
18148 | #define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 |
18149 | #define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 |
18150 | #define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 |
18151 | #define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc |
18152 | #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf |
18153 | #define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL |
18154 | #define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L |
18155 | #define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L |
18156 | #define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L |
18157 | #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L |
18158 | //SPI_RESOURCE_RESERVE_CU_8 |
18159 | #define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 |
18160 | #define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 |
18161 | #define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 |
18162 | #define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc |
18163 | #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf |
18164 | #define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL |
18165 | #define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L |
18166 | #define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L |
18167 | #define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L |
18168 | #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L |
18169 | //SPI_RESOURCE_RESERVE_CU_9 |
18170 | #define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 |
18171 | #define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 |
18172 | #define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 |
18173 | #define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc |
18174 | #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf |
18175 | #define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL |
18176 | #define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L |
18177 | #define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L |
18178 | #define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L |
18179 | #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L |
18180 | //SPI_RESOURCE_RESERVE_EN_CU_0 |
18181 | #define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 |
18182 | #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 |
18183 | #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 |
18184 | #define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L |
18185 | #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL |
18186 | #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L |
18187 | //SPI_RESOURCE_RESERVE_EN_CU_1 |
18188 | #define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 |
18189 | #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 |
18190 | #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 |
18191 | #define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L |
18192 | #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL |
18193 | #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L |
18194 | //SPI_RESOURCE_RESERVE_EN_CU_2 |
18195 | #define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 |
18196 | #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 |
18197 | #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 |
18198 | #define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L |
18199 | #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL |
18200 | #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L |
18201 | //SPI_RESOURCE_RESERVE_EN_CU_3 |
18202 | #define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 |
18203 | #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 |
18204 | #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 |
18205 | #define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L |
18206 | #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL |
18207 | #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L |
18208 | //SPI_RESOURCE_RESERVE_EN_CU_4 |
18209 | #define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 |
18210 | #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 |
18211 | #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 |
18212 | #define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L |
18213 | #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL |
18214 | #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L |
18215 | //SPI_RESOURCE_RESERVE_EN_CU_5 |
18216 | #define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 |
18217 | #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 |
18218 | #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 |
18219 | #define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L |
18220 | #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL |
18221 | #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L |
18222 | //SPI_RESOURCE_RESERVE_EN_CU_6 |
18223 | #define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 |
18224 | #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 |
18225 | #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 |
18226 | #define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L |
18227 | #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL |
18228 | #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L |
18229 | //SPI_RESOURCE_RESERVE_EN_CU_7 |
18230 | #define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 |
18231 | #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 |
18232 | #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 |
18233 | #define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L |
18234 | #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL |
18235 | #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L |
18236 | //SPI_RESOURCE_RESERVE_EN_CU_8 |
18237 | #define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 |
18238 | #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 |
18239 | #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 |
18240 | #define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L |
18241 | #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL |
18242 | #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L |
18243 | //SPI_RESOURCE_RESERVE_EN_CU_9 |
18244 | #define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 |
18245 | #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 |
18246 | #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 |
18247 | #define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L |
18248 | #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL |
18249 | #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L |
18250 | //SPI_COMPUTE_WF_CTX_SAVE |
18251 | #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 |
18252 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 |
18253 | #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 |
18254 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e |
18255 | #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f |
18256 | #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L |
18257 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L |
18258 | #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L |
18259 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L |
18260 | #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L |
18261 | //SPI_ARB_CNTL_0 |
18262 | #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0 |
18263 | #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4 |
18264 | #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8 |
18265 | #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL |
18266 | #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L |
18267 | #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L |
18268 | //SPI_FEATURE_CTRL |
18269 | #define SPI_FEATURE_CTRL__CU_LOCKING_FAIRNESS_DISABLE__SHIFT 0x0 |
18270 | #define SPI_FEATURE_CTRL__ALLOCATION_RATE_THROTTLE_THRESHOLD__SHIFT 0x2 |
18271 | #define SPI_FEATURE_CTRL__ACTIVE_HARD_LOCK_LIMIT__SHIFT 0x7 |
18272 | #define SPI_FEATURE_CTRL__LR_IMBALANCE_THRESHOLD__SHIFT 0xc |
18273 | #define SPI_FEATURE_CTRL__RA_PIPE_DEPTH_THRESHOLD_ALLOC_STALL_EN__SHIFT 0x12 |
18274 | #define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_ALLOC_STALL_EN__SHIFT 0x13 |
18275 | #define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD__SHIFT 0x14 |
18276 | #define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT__SHIFT 0x1c |
18277 | #define SPI_FEATURE_CTRL__CU_LOCKING_FAIRNESS_DISABLE_MASK 0x00000001L |
18278 | #define SPI_FEATURE_CTRL__ALLOCATION_RATE_THROTTLE_THRESHOLD_MASK 0x0000007CL |
18279 | #define SPI_FEATURE_CTRL__ACTIVE_HARD_LOCK_LIMIT_MASK 0x00000F80L |
18280 | #define SPI_FEATURE_CTRL__LR_IMBALANCE_THRESHOLD_MASK 0x0003F000L |
18281 | #define SPI_FEATURE_CTRL__RA_PIPE_DEPTH_THRESHOLD_ALLOC_STALL_EN_MASK 0x00040000L |
18282 | #define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_ALLOC_STALL_EN_MASK 0x00080000L |
18283 | #define SPI_FEATURE_CTRL__BUS_ACTIVITY_THRESHOLD_MASK 0x0FF00000L |
18284 | #define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT_MASK 0xF0000000L |
18285 | //SPI_SHADER_RSRC_LIMIT_CTRL |
18286 | #define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32__SHIFT 0x0 |
18287 | #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32__SHIFT 0x5 |
18288 | #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE__SHIFT 0xc |
18289 | #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT__SHIFT 0xd |
18290 | #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL__SHIFT 0x13 |
18291 | #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT__SHIFT 0x14 |
18292 | #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL__SHIFT 0x1c |
18293 | #define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE__SHIFT 0x1f |
18294 | #define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32_MASK 0x0000001FL |
18295 | #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32_MASK 0x00000FE0L |
18296 | #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE_MASK 0x00001000L |
18297 | #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_MASK 0x0007E000L |
18298 | #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL_MASK 0x00080000L |
18299 | #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_MASK 0x0FF00000L |
18300 | #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL_MASK 0x10000000L |
18301 | #define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE_MASK 0x80000000L |
18302 | |
18303 | |
18304 | // addressBlock: gc_cpphqddec |
18305 | //CP_HPD_MES_ROQ_OFFSETS |
18306 | #define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 |
18307 | #define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 |
18308 | #define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 |
18309 | #define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L |
18310 | #define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L |
18311 | #define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET_MASK 0x007F0000L |
18312 | //CP_HPD_ROQ_OFFSETS |
18313 | #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 |
18314 | #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 |
18315 | #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 |
18316 | #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L |
18317 | #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L |
18318 | #define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x007F0000L |
18319 | //CP_HPD_STATUS0 |
18320 | #define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 |
18321 | #define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 |
18322 | #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 |
18323 | #define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10 |
18324 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11 |
18325 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12 |
18326 | #define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 |
18327 | #define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS__SHIFT 0x1b |
18328 | #define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT 0x1c |
18329 | #define CP_HPD_STATUS0__FREEZE_QUEUE_STATE__SHIFT 0x1e |
18330 | #define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f |
18331 | #define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL |
18332 | #define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L |
18333 | #define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L |
18334 | #define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L |
18335 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L |
18336 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L |
18337 | #define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L |
18338 | #define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS_MASK 0x08000000L |
18339 | #define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK 0x30000000L |
18340 | #define CP_HPD_STATUS0__FREEZE_QUEUE_STATE_MASK 0x40000000L |
18341 | #define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L |
18342 | //CP_HPD_UTCL1_CNTL |
18343 | #define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0 |
18344 | #define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL |
18345 | //CP_HPD_UTCL1_ERROR |
18346 | #define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0 |
18347 | #define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10 |
18348 | #define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14 |
18349 | #define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL |
18350 | #define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L |
18351 | #define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L |
18352 | //CP_HPD_UTCL1_ERROR_ADDR |
18353 | #define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc |
18354 | #define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L |
18355 | //CP_MQD_BASE_ADDR |
18356 | #define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 |
18357 | #define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL |
18358 | //CP_MQD_BASE_ADDR_HI |
18359 | #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
18360 | #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL |
18361 | //CP_HQD_ACTIVE |
18362 | #define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 |
18363 | #define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 |
18364 | #define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L |
18365 | #define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L |
18366 | //CP_HQD_VMID |
18367 | #define CP_HQD_VMID__VMID__SHIFT 0x0 |
18368 | #define CP_HQD_VMID__IB_VMID__SHIFT 0x8 |
18369 | #define CP_HQD_VMID__VQID__SHIFT 0x10 |
18370 | #define CP_HQD_VMID__VMID_MASK 0x0000000FL |
18371 | #define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L |
18372 | #define CP_HQD_VMID__VQID_MASK 0x03FF0000L |
18373 | //CP_HQD_PERSISTENT_STATE |
18374 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 |
18375 | #define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS__SHIFT 0x7 |
18376 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 |
18377 | #define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN__SHIFT 0x14 |
18378 | #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15 |
18379 | #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16 |
18380 | #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17 |
18381 | #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18 |
18382 | #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19 |
18383 | #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a |
18384 | #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b |
18385 | #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c |
18386 | #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d |
18387 | #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e |
18388 | #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f |
18389 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L |
18390 | #define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS_MASK 0x00000080L |
18391 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L |
18392 | #define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN_MASK 0x00100000L |
18393 | #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L |
18394 | #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L |
18395 | #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L |
18396 | #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L |
18397 | #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L |
18398 | #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L |
18399 | #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L |
18400 | #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L |
18401 | #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L |
18402 | #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L |
18403 | #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L |
18404 | //CP_HQD_PIPE_PRIORITY |
18405 | #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 |
18406 | #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L |
18407 | //CP_HQD_QUEUE_PRIORITY |
18408 | #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 |
18409 | #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL |
18410 | //CP_HQD_QUANTUM |
18411 | #define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 |
18412 | #define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 |
18413 | #define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 |
18414 | #define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f |
18415 | #define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L |
18416 | #define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L |
18417 | #define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L |
18418 | #define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L |
18419 | //CP_HQD_PQ_BASE |
18420 | #define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 |
18421 | #define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL |
18422 | //CP_HQD_PQ_BASE_HI |
18423 | #define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 |
18424 | #define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL |
18425 | //CP_HQD_PQ_RPTR |
18426 | #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 |
18427 | #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL |
18428 | //CP_HQD_PQ_RPTR_REPORT_ADDR |
18429 | #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 |
18430 | #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL |
18431 | //CP_HQD_PQ_RPTR_REPORT_ADDR_HI |
18432 | #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 |
18433 | #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL |
18434 | //CP_HQD_PQ_WPTR_POLL_ADDR |
18435 | #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3 |
18436 | #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L |
18437 | //CP_HQD_PQ_WPTR_POLL_ADDR_HI |
18438 | #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 |
18439 | #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL |
18440 | //CP_HQD_PQ_DOORBELL_CONTROL |
18441 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 |
18442 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 |
18443 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 |
18444 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c |
18445 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d |
18446 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e |
18447 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f |
18448 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L |
18449 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L |
18450 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
18451 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L |
18452 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L |
18453 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L |
18454 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L |
18455 | //CP_HQD_PQ_CONTROL |
18456 | #define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 |
18457 | #define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6 |
18458 | #define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7 |
18459 | #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 |
18460 | #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe |
18461 | #define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf |
18462 | #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x12 |
18463 | #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 |
18464 | #define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17 |
18465 | #define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 |
18466 | #define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT 0x1a |
18467 | #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b |
18468 | #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c |
18469 | #define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH__SHIFT 0x1d |
18470 | #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e |
18471 | #define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f |
18472 | #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL |
18473 | #define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L |
18474 | #define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L |
18475 | #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L |
18476 | #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L |
18477 | #define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L |
18478 | #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x000C0000L |
18479 | #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L |
18480 | #define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L |
18481 | #define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x03000000L |
18482 | #define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK 0x04000000L |
18483 | #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L |
18484 | #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L |
18485 | #define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH_MASK 0x20000000L |
18486 | #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L |
18487 | #define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L |
18488 | //CP_HQD_IB_BASE_ADDR |
18489 | #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 |
18490 | #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL |
18491 | //CP_HQD_IB_BASE_ADDR_HI |
18492 | #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 |
18493 | #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL |
18494 | //CP_HQD_IB_RPTR |
18495 | #define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 |
18496 | #define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL |
18497 | //CP_HQD_IB_CONTROL |
18498 | #define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 |
18499 | #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 |
18500 | #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17 |
18501 | #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 |
18502 | #define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT 0x1a |
18503 | #define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f |
18504 | #define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL |
18505 | #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L |
18506 | #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L |
18507 | #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x03000000L |
18508 | #define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK 0x04000000L |
18509 | #define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L |
18510 | //CP_HQD_IQ_TIMER |
18511 | #define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 |
18512 | #define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 |
18513 | #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb |
18514 | #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc |
18515 | #define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe |
18516 | #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 |
18517 | #define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 |
18518 | #define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17 |
18519 | #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 |
18520 | #define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT 0x1a |
18521 | #define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x1b |
18522 | #define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c |
18523 | #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d |
18524 | #define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e |
18525 | #define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f |
18526 | #define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL |
18527 | #define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L |
18528 | #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L |
18529 | #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L |
18530 | #define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L |
18531 | #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L |
18532 | #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L |
18533 | #define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L |
18534 | #define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x03000000L |
18535 | #define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK 0x04000000L |
18536 | #define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x08000000L |
18537 | #define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L |
18538 | #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L |
18539 | #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L |
18540 | #define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L |
18541 | //CP_HQD_IQ_RPTR |
18542 | #define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 |
18543 | #define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL |
18544 | //CP_HQD_DEQUEUE_REQUEST |
18545 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 |
18546 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 |
18547 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 |
18548 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 |
18549 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa |
18550 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x0000000FL |
18551 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L |
18552 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L |
18553 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L |
18554 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L |
18555 | //CP_HQD_DMA_OFFLOAD |
18556 | #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 |
18557 | #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L |
18558 | //CP_HQD_OFFLOAD |
18559 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 |
18560 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 |
18561 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 |
18562 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 |
18563 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 |
18564 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 |
18565 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L |
18566 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L |
18567 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L |
18568 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L |
18569 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L |
18570 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L |
18571 | //CP_HQD_SEMA_CMD |
18572 | #define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 |
18573 | #define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 |
18574 | #define CP_HQD_SEMA_CMD__POLLING_DIS__SHIFT 0x8 |
18575 | #define CP_HQD_SEMA_CMD__MESSAGE_EN__SHIFT 0x9 |
18576 | #define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L |
18577 | #define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L |
18578 | #define CP_HQD_SEMA_CMD__POLLING_DIS_MASK 0x00000100L |
18579 | #define CP_HQD_SEMA_CMD__MESSAGE_EN_MASK 0x00000200L |
18580 | //CP_HQD_MSG_TYPE |
18581 | #define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 |
18582 | #define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 |
18583 | #define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L |
18584 | #define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L |
18585 | //CP_HQD_ATOMIC0_PREOP_LO |
18586 | #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 |
18587 | #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
18588 | //CP_HQD_ATOMIC0_PREOP_HI |
18589 | #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 |
18590 | #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
18591 | //CP_HQD_ATOMIC1_PREOP_LO |
18592 | #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 |
18593 | #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
18594 | //CP_HQD_ATOMIC1_PREOP_HI |
18595 | #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 |
18596 | #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
18597 | //CP_HQD_HQ_SCHEDULER0 |
18598 | #define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0 |
18599 | #define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL |
18600 | //CP_HQD_HQ_STATUS0 |
18601 | #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 |
18602 | #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2 |
18603 | #define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4 |
18604 | #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 |
18605 | #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 |
18606 | #define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9 |
18607 | #define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa |
18608 | #define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e |
18609 | #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f |
18610 | #define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L |
18611 | #define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL |
18612 | #define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L |
18613 | #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L |
18614 | #define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L |
18615 | #define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L |
18616 | #define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L |
18617 | #define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L |
18618 | #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L |
18619 | //CP_HQD_HQ_CONTROL0 |
18620 | #define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 |
18621 | #define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL |
18622 | //CP_HQD_HQ_SCHEDULER1 |
18623 | #define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 |
18624 | #define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL |
18625 | //CP_MQD_CONTROL |
18626 | #define CP_MQD_CONTROL__VMID__SHIFT 0x0 |
18627 | #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 |
18628 | #define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc |
18629 | #define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd |
18630 | #define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 |
18631 | #define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 |
18632 | #define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT 0x1a |
18633 | #define CP_MQD_CONTROL__VMID_MASK 0x0000000FL |
18634 | #define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L |
18635 | #define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L |
18636 | #define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L |
18637 | #define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L |
18638 | #define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x03000000L |
18639 | #define CP_MQD_CONTROL__MQD_VOLATILE_MASK 0x04000000L |
18640 | //CP_HQD_HQ_STATUS1 |
18641 | #define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 |
18642 | #define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL |
18643 | //CP_HQD_HQ_CONTROL1 |
18644 | #define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 |
18645 | #define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL |
18646 | //CP_HQD_EOP_BASE_ADDR |
18647 | #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
18648 | #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
18649 | //CP_HQD_EOP_BASE_ADDR_HI |
18650 | #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
18651 | #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL |
18652 | //CP_HQD_EOP_CONTROL |
18653 | #define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 |
18654 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 |
18655 | #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc |
18656 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd |
18657 | #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe |
18658 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15 |
18659 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16 |
18660 | #define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17 |
18661 | #define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 |
18662 | #define CP_HQD_EOP_CONTROL__EOP_VOLATILE__SHIFT 0x1a |
18663 | #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d |
18664 | #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f |
18665 | #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL |
18666 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L |
18667 | #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L |
18668 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L |
18669 | #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L |
18670 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L |
18671 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L |
18672 | #define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L |
18673 | #define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x03000000L |
18674 | #define CP_HQD_EOP_CONTROL__EOP_VOLATILE_MASK 0x04000000L |
18675 | #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L |
18676 | #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L |
18677 | //CP_HQD_EOP_RPTR |
18678 | #define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 |
18679 | #define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c |
18680 | #define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d |
18681 | #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e |
18682 | #define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f |
18683 | #define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL |
18684 | #define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L |
18685 | #define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L |
18686 | #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L |
18687 | #define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L |
18688 | //CP_HQD_EOP_WPTR |
18689 | #define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 |
18690 | #define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf |
18691 | #define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 |
18692 | #define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL |
18693 | #define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L |
18694 | #define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L |
18695 | //CP_HQD_EOP_EVENTS |
18696 | #define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 |
18697 | #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 |
18698 | #define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL |
18699 | #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L |
18700 | //CP_HQD_CTX_SAVE_BASE_ADDR_LO |
18701 | #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc |
18702 | #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L |
18703 | //CP_HQD_CTX_SAVE_BASE_ADDR_HI |
18704 | #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
18705 | #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
18706 | //CP_HQD_CTX_SAVE_CONTROL |
18707 | #define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 |
18708 | #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 |
18709 | #define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L |
18710 | #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L |
18711 | //CP_HQD_CNTL_STACK_OFFSET |
18712 | #define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 |
18713 | #define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL |
18714 | //CP_HQD_CNTL_STACK_SIZE |
18715 | #define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc |
18716 | #define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L |
18717 | //CP_HQD_WG_STATE_OFFSET |
18718 | #define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 |
18719 | #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL |
18720 | //CP_HQD_CTX_SAVE_SIZE |
18721 | #define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc |
18722 | #define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L |
18723 | //CP_HQD_GDS_RESOURCE_STATE |
18724 | #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 |
18725 | #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 |
18726 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 |
18727 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc |
18728 | #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L |
18729 | #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L |
18730 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L |
18731 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L |
18732 | //CP_HQD_ERROR |
18733 | #define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 |
18734 | #define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 |
18735 | #define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5 |
18736 | #define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8 |
18737 | #define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9 |
18738 | #define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa |
18739 | #define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb |
18740 | #define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc |
18741 | #define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd |
18742 | #define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe |
18743 | #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf |
18744 | #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10 |
18745 | #define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11 |
18746 | #define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12 |
18747 | #define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13 |
18748 | #define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL |
18749 | #define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L |
18750 | #define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L |
18751 | #define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L |
18752 | #define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L |
18753 | #define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L |
18754 | #define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L |
18755 | #define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L |
18756 | #define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L |
18757 | #define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L |
18758 | #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L |
18759 | #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L |
18760 | #define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L |
18761 | #define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L |
18762 | #define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L |
18763 | //CP_HQD_EOP_WPTR_MEM |
18764 | #define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 |
18765 | #define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL |
18766 | //CP_HQD_AQL_CONTROL |
18767 | #define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0 |
18768 | #define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf |
18769 | #define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10 |
18770 | #define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f |
18771 | #define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL |
18772 | #define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L |
18773 | #define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L |
18774 | #define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L |
18775 | //CP_HQD_PQ_WPTR_LO |
18776 | #define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0 |
18777 | #define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL |
18778 | //CP_HQD_PQ_WPTR_HI |
18779 | #define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0 |
18780 | #define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL |
18781 | //CP_HQD_SUSPEND_CNTL_STACK_OFFSET |
18782 | #define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 |
18783 | #define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL |
18784 | //CP_HQD_SUSPEND_CNTL_STACK_DW_CNT |
18785 | #define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT__SHIFT 0x0 |
18786 | #define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT_MASK 0x00001FFFL |
18787 | //CP_HQD_SUSPEND_WG_STATE_OFFSET |
18788 | #define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 |
18789 | #define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL |
18790 | //CP_HQD_DDID_RPTR |
18791 | #define CP_HQD_DDID_RPTR__RPTR__SHIFT 0x0 |
18792 | #define CP_HQD_DDID_RPTR__RPTR_MASK 0x000007FFL |
18793 | //CP_HQD_DDID_WPTR |
18794 | #define CP_HQD_DDID_WPTR__WPTR__SHIFT 0x0 |
18795 | #define CP_HQD_DDID_WPTR__WPTR_MASK 0x000007FFL |
18796 | //CP_HQD_DDID_INFLIGHT_COUNT |
18797 | #define CP_HQD_DDID_INFLIGHT_COUNT__COUNT__SHIFT 0x0 |
18798 | #define CP_HQD_DDID_INFLIGHT_COUNT__COUNT_MASK 0x0000FFFFL |
18799 | //CP_HQD_DDID_DELTA_RPT_COUNT |
18800 | #define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT__SHIFT 0x0 |
18801 | #define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT_MASK 0x000000FFL |
18802 | //CP_HQD_DEQUEUE_STATUS |
18803 | #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT__SHIFT 0x0 |
18804 | #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND__SHIFT 0x4 |
18805 | #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN__SHIFT 0x9 |
18806 | #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN__SHIFT 0xa |
18807 | #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_MASK 0x0000000FL |
18808 | #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_MASK 0x00000010L |
18809 | #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN_MASK 0x00000200L |
18810 | #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN_MASK 0x00000400L |
18811 | |
18812 | |
18813 | // addressBlock: gc_didtdec |
18814 | //DIDT_IND_INDEX |
18815 | #define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 |
18816 | #define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL |
18817 | //DIDT_IND_DATA |
18818 | #define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 |
18819 | #define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL |
18820 | //DIDT_INDEX_AUTO_INCR_EN |
18821 | #define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT 0x0 |
18822 | #define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK 0x00000001L |
18823 | |
18824 | |
18825 | // addressBlock: gc_gccacdec |
18826 | //GC_CAC_CTRL_1 |
18827 | #define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 |
18828 | #define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18 |
18829 | #define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL |
18830 | #define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L |
18831 | //GC_CAC_CTRL_2 |
18832 | #define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 |
18833 | #define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1 |
18834 | #define GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT 0x2 |
18835 | #define GC_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT 0x3 |
18836 | #define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x4 |
18837 | #define GC_CAC_CTRL_2__TOGGLE_EN__SHIFT 0x5 |
18838 | #define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L |
18839 | #define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L |
18840 | #define GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK 0x00000004L |
18841 | #define GC_CAC_CTRL_2__SE_LCAC_ENABLE_MASK 0x00000008L |
18842 | #define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000010L |
18843 | #define GC_CAC_CTRL_2__TOGGLE_EN_MASK 0x00000020L |
18844 | //GC_CAC_AGGR_LOWER |
18845 | #define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0 |
18846 | #define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL |
18847 | //GC_CAC_AGGR_UPPER |
18848 | #define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0 |
18849 | #define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL |
18850 | //GC_CAC_SOFT_CTRL |
18851 | #define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0 |
18852 | #define GC_CAC_SOFT_CTRL__UNUSED__SHIFT 0x1 |
18853 | #define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L |
18854 | #define GC_CAC_SOFT_CTRL__UNUSED_MASK 0xFFFFFFFEL |
18855 | //GC_EDC_CTRL |
18856 | #define GC_EDC_CTRL__EDC_EN__SHIFT 0x0 |
18857 | #define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
18858 | #define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
18859 | #define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
18860 | #define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
18861 | #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9 |
18862 | #define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0xa |
18863 | #define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0xe |
18864 | #define GC_EDC_CTRL__EDC_ALGORITHM_MODE__SHIFT 0xf |
18865 | #define GC_EDC_CTRL__EDC_AVGDIV__SHIFT 0x10 |
18866 | #define GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL__SHIFT 0x14 |
18867 | #define GC_EDC_CTRL__THROTTLE_SRC0_MASK__SHIFT 0x17 |
18868 | #define GC_EDC_CTRL__THROTTLE_SRC1_MASK__SHIFT 0x18 |
18869 | #define GC_EDC_CTRL__THROTTLE_SRC2_MASK__SHIFT 0x19 |
18870 | #define GC_EDC_CTRL__THROTTLE_SRC3_MASK__SHIFT 0x1a |
18871 | #define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L |
18872 | #define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
18873 | #define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
18874 | #define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
18875 | #define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
18876 | #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L |
18877 | #define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00003C00L |
18878 | #define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x00004000L |
18879 | #define GC_EDC_CTRL__EDC_ALGORITHM_MODE_MASK 0x00008000L |
18880 | #define GC_EDC_CTRL__EDC_AVGDIV_MASK 0x000F0000L |
18881 | #define GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL_MASK 0x00700000L |
18882 | #define GC_EDC_CTRL__THROTTLE_SRC0_MASK_MASK 0x00800000L |
18883 | #define GC_EDC_CTRL__THROTTLE_SRC1_MASK_MASK 0x01000000L |
18884 | #define GC_EDC_CTRL__THROTTLE_SRC2_MASK_MASK 0x02000000L |
18885 | #define GC_EDC_CTRL__THROTTLE_SRC3_MASK_MASK 0x04000000L |
18886 | //GC_EDC_THRESHOLD |
18887 | #define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
18888 | #define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
18889 | //GC_EDC_STATUS |
18890 | #define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0 |
18891 | #define GC_EDC_STATUS__GPIO_IN_0__SHIFT 0x3 |
18892 | #define GC_EDC_STATUS__GPIO_IN_1__SHIFT 0x4 |
18893 | #define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L |
18894 | #define GC_EDC_STATUS__GPIO_IN_0_MASK 0x00000008L |
18895 | #define GC_EDC_STATUS__GPIO_IN_1_MASK 0x00000010L |
18896 | //GC_EDC_OVERFLOW |
18897 | #define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
18898 | #define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
18899 | #define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
18900 | #define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
18901 | //GC_EDC_ROLLING_POWER_DELTA |
18902 | #define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
18903 | #define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
18904 | //GC_THROTTLE_CTRL |
18905 | #define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT 0x0 |
18906 | #define GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x1 |
18907 | #define GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
18908 | #define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL__SHIFT 0x3 |
18909 | #define GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x4 |
18910 | #define GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT 0x5 |
18911 | #define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x6 |
18912 | #define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT 0x7 |
18913 | #define GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT 0x8 |
18914 | #define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE__SHIFT 0x9 |
18915 | #define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT 0xa |
18916 | #define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT 0xb |
18917 | #define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN__SHIFT 0xc |
18918 | #define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT 0xd |
18919 | #define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT 0x17 |
18920 | #define GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX__SHIFT 0x18 |
18921 | #define GC_THROTTLE_CTRL__LUT_HW_UPDATE__SHIFT 0x1d |
18922 | #define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE__SHIFT 0x1e |
18923 | #define GC_THROTTLE_CTRL__PCC_POLARITY_CNTL__SHIFT 0x1f |
18924 | #define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK 0x00000001L |
18925 | #define GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000002L |
18926 | #define GC_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
18927 | #define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL_MASK 0x00000008L |
18928 | #define GC_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000010L |
18929 | #define GC_THROTTLE_CTRL__PATTERN_MODE_MASK 0x00000020L |
18930 | #define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000040L |
18931 | #define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK 0x00000080L |
18932 | #define GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK 0x00000100L |
18933 | #define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE_MASK 0x00000200L |
18934 | #define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK 0x00000400L |
18935 | #define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK 0x00000800L |
18936 | #define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN_MASK 0x00001000L |
18937 | #define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL_MASK 0x007FE000L |
18938 | #define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK 0x00800000L |
18939 | #define GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX_MASK 0x1F000000L |
18940 | #define GC_THROTTLE_CTRL__LUT_HW_UPDATE_MASK 0x20000000L |
18941 | #define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE_MASK 0x40000000L |
18942 | #define GC_THROTTLE_CTRL__PCC_POLARITY_CNTL_MASK 0x80000000L |
18943 | //GC_THROTTLE_CTRL1 |
18944 | #define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT 0x0 |
18945 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT 0x1 |
18946 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT 0x5 |
18947 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0xa |
18948 | #define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT 0xd |
18949 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP__SHIFT 0xe |
18950 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP__SHIFT 0x12 |
18951 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0x17 |
18952 | #define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT__SHIFT 0x1a |
18953 | #define GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN__SHIFT 0x1e |
18954 | #define GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN__SHIFT 0x1f |
18955 | #define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK 0x00000001L |
18956 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK 0x0000001EL |
18957 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK 0x000003E0L |
18958 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x00001C00L |
18959 | #define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN_MASK 0x00002000L |
18960 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP_MASK 0x0003C000L |
18961 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP_MASK 0x007C0000L |
18962 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x03800000L |
18963 | #define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT_MASK 0x0C000000L |
18964 | #define GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN_MASK 0x40000000L |
18965 | #define GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN_MASK 0x80000000L |
18966 | //GC_THROTTLE_STATUS |
18967 | #define GC_THROTTLE_STATUS__FSM_STATE__SHIFT 0x0 |
18968 | #define GC_THROTTLE_STATUS__PATTERN_INDEX__SHIFT 0x4 |
18969 | #define GC_THROTTLE_STATUS__FSM_STATE_MASK 0x0000000FL |
18970 | #define GC_THROTTLE_STATUS__PATTERN_INDEX_MASK 0x000003F0L |
18971 | //EDC_PERF_COUNTER |
18972 | #define EDC_PERF_COUNTER__EDC_PERF_COUNTER__SHIFT 0x0 |
18973 | #define EDC_PERF_COUNTER__EDC_PERF_COUNTER_MASK 0xFFFFFFFFL |
18974 | //PCC_PERF_COUNTER |
18975 | #define PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT 0x0 |
18976 | #define PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK 0xFFFFFFFFL |
18977 | //PWRBRK_PERF_COUNTER |
18978 | #define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT 0x0 |
18979 | #define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK 0xFFFFFFFFL |
18980 | //GC_EDC_STRETCH_CTRL |
18981 | #define GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN__SHIFT 0x0 |
18982 | #define GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY__SHIFT 0x1 |
18983 | #define GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY__SHIFT 0xa |
18984 | #define GC_EDC_STRETCH_CTRL__EDC_CLK_MONITOR_EN__SHIFT 0x13 |
18985 | #define GC_EDC_STRETCH_CTRL__EDC_CLK_MONITOR_INTERVAL__SHIFT 0x14 |
18986 | #define GC_EDC_STRETCH_CTRL__EDC_CLK_MONITOR_THRESHOLD__SHIFT 0x18 |
18987 | #define GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN_MASK 0x00000001L |
18988 | #define GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY_MASK 0x000003FEL |
18989 | #define GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY_MASK 0x0007FC00L |
18990 | #define GC_EDC_STRETCH_CTRL__EDC_CLK_MONITOR_EN_MASK 0x00080000L |
18991 | #define GC_EDC_STRETCH_CTRL__EDC_CLK_MONITOR_INTERVAL_MASK 0x00F00000L |
18992 | #define GC_EDC_STRETCH_CTRL__EDC_CLK_MONITOR_THRESHOLD_MASK 0xFF000000L |
18993 | //GC_EDC_STRETCH_THRESHOLD |
18994 | #define GC_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD__SHIFT 0x0 |
18995 | #define GC_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD_MASK 0xFFFFFFFFL |
18996 | //EDC_HYSTERESIS_CNTL |
18997 | #define EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT 0x0 |
18998 | #define EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK 0x000000FFL |
18999 | //EDC_HYSTERESIS_STAT |
19000 | #define EDC_HYSTERESIS_STAT__HYSTERESIS_CNT__SHIFT 0x0 |
19001 | #define EDC_HYSTERESIS_STAT__EDC_STATUS__SHIFT 0x8 |
19002 | #define EDC_HYSTERESIS_STAT__HYSTERESIS_CNT_MASK 0x000000FFL |
19003 | #define EDC_HYSTERESIS_STAT__EDC_STATUS_MASK 0x00000100L |
19004 | //GC_CAC_IND_INDEX |
19005 | #define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0 |
19006 | #define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL |
19007 | //GC_CAC_IND_DATA |
19008 | #define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0 |
19009 | #define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL |
19010 | //SE_CAC_IND_INDEX |
19011 | #define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0 |
19012 | #define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL |
19013 | //SE_CAC_IND_DATA |
19014 | #define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0 |
19015 | #define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL |
19016 | |
19017 | |
19018 | // addressBlock: gc_tcpdec |
19019 | //TCP_WATCH0_ADDR_H |
19020 | #define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 |
19021 | #define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL |
19022 | //TCP_WATCH0_ADDR_L |
19023 | #define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x7 |
19024 | #define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFF80L |
19025 | //TCP_WATCH0_CNTL |
19026 | #define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 |
19027 | #define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 |
19028 | #define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d |
19029 | #define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f |
19030 | #define TCP_WATCH0_CNTL__MASK_MASK 0x007FFFFFL |
19031 | #define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L |
19032 | #define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L |
19033 | #define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L |
19034 | //TCP_WATCH1_ADDR_H |
19035 | #define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 |
19036 | #define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL |
19037 | //TCP_WATCH1_ADDR_L |
19038 | #define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x7 |
19039 | #define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFF80L |
19040 | //TCP_WATCH1_CNTL |
19041 | #define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 |
19042 | #define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 |
19043 | #define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d |
19044 | #define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f |
19045 | #define TCP_WATCH1_CNTL__MASK_MASK 0x007FFFFFL |
19046 | #define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L |
19047 | #define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L |
19048 | #define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L |
19049 | //TCP_WATCH2_ADDR_H |
19050 | #define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 |
19051 | #define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL |
19052 | //TCP_WATCH2_ADDR_L |
19053 | #define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x7 |
19054 | #define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFF80L |
19055 | //TCP_WATCH2_CNTL |
19056 | #define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 |
19057 | #define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 |
19058 | #define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d |
19059 | #define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f |
19060 | #define TCP_WATCH2_CNTL__MASK_MASK 0x007FFFFFL |
19061 | #define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L |
19062 | #define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L |
19063 | #define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L |
19064 | //TCP_WATCH3_ADDR_H |
19065 | #define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 |
19066 | #define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL |
19067 | //TCP_WATCH3_ADDR_L |
19068 | #define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x7 |
19069 | #define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFF80L |
19070 | //TCP_WATCH3_CNTL |
19071 | #define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 |
19072 | #define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 |
19073 | #define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d |
19074 | #define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f |
19075 | #define TCP_WATCH3_CNTL__MASK_MASK 0x007FFFFFL |
19076 | #define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L |
19077 | #define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L |
19078 | #define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L |
19079 | //TCP_PERFCOUNTER_FILTER |
19080 | #define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 |
19081 | #define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 |
19082 | #define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2 |
19083 | #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5 |
19084 | #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xd |
19085 | #define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0x11 |
19086 | #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x16 |
19087 | #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x18 |
19088 | #define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1b |
19089 | #define TCP_PERFCOUNTER_FILTER__DLC__SHIFT 0x1c |
19090 | #define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x1d |
19091 | #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1e |
19092 | #define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L |
19093 | #define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L |
19094 | #define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL |
19095 | #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x00000FE0L |
19096 | #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x0001E000L |
19097 | #define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x003E0000L |
19098 | #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00C00000L |
19099 | #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x07000000L |
19100 | #define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x08000000L |
19101 | #define TCP_PERFCOUNTER_FILTER__DLC_MASK 0x10000000L |
19102 | #define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x20000000L |
19103 | #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x40000000L |
19104 | //TCP_PERFCOUNTER_FILTER_EN |
19105 | #define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0 |
19106 | #define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1 |
19107 | #define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2 |
19108 | #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3 |
19109 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4 |
19110 | #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5 |
19111 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6 |
19112 | #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7 |
19113 | #define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x8 |
19114 | #define TCP_PERFCOUNTER_FILTER_EN__DLC__SHIFT 0x9 |
19115 | #define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0xa |
19116 | #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xb |
19117 | #define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE__SHIFT 0xc |
19118 | #define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L |
19119 | #define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L |
19120 | #define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L |
19121 | #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L |
19122 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L |
19123 | #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L |
19124 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L |
19125 | #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L |
19126 | #define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000100L |
19127 | #define TCP_PERFCOUNTER_FILTER_EN__DLC_MASK 0x00000200L |
19128 | #define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000400L |
19129 | #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000800L |
19130 | #define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE_MASK 0x00001000L |
19131 | //TCP_PERFCOUNTER_FILTER2 |
19132 | #define TCP_PERFCOUNTER_FILTER2__REQ_MODE__SHIFT 0x0 |
19133 | #define TCP_PERFCOUNTER_FILTER2__REQ_MODE_MASK 0x00000007L |
19134 | |
19135 | |
19136 | // addressBlock: gc_gdspdec |
19137 | //GDS_VMID0_BASE |
19138 | #define GDS_VMID0_BASE__BASE__SHIFT 0x0 |
19139 | #define GDS_VMID0_BASE__UNUSED__SHIFT 0x10 |
19140 | #define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL |
19141 | #define GDS_VMID0_BASE__UNUSED_MASK 0xFFFF0000L |
19142 | //GDS_VMID0_SIZE |
19143 | #define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 |
19144 | #define GDS_VMID0_SIZE__UNUSED__SHIFT 0x11 |
19145 | #define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL |
19146 | #define GDS_VMID0_SIZE__UNUSED_MASK 0xFFFE0000L |
19147 | //GDS_VMID1_BASE |
19148 | #define GDS_VMID1_BASE__BASE__SHIFT 0x0 |
19149 | #define GDS_VMID1_BASE__UNUSED__SHIFT 0x10 |
19150 | #define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL |
19151 | #define GDS_VMID1_BASE__UNUSED_MASK 0xFFFF0000L |
19152 | //GDS_VMID1_SIZE |
19153 | #define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 |
19154 | #define GDS_VMID1_SIZE__UNUSED__SHIFT 0x11 |
19155 | #define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL |
19156 | #define GDS_VMID1_SIZE__UNUSED_MASK 0xFFFE0000L |
19157 | //GDS_VMID2_BASE |
19158 | #define GDS_VMID2_BASE__BASE__SHIFT 0x0 |
19159 | #define GDS_VMID2_BASE__UNUSED__SHIFT 0x10 |
19160 | #define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL |
19161 | #define GDS_VMID2_BASE__UNUSED_MASK 0xFFFF0000L |
19162 | //GDS_VMID2_SIZE |
19163 | #define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 |
19164 | #define GDS_VMID2_SIZE__UNUSED__SHIFT 0x11 |
19165 | #define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL |
19166 | #define GDS_VMID2_SIZE__UNUSED_MASK 0xFFFE0000L |
19167 | //GDS_VMID3_BASE |
19168 | #define GDS_VMID3_BASE__BASE__SHIFT 0x0 |
19169 | #define GDS_VMID3_BASE__UNUSED__SHIFT 0x10 |
19170 | #define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL |
19171 | #define GDS_VMID3_BASE__UNUSED_MASK 0xFFFF0000L |
19172 | //GDS_VMID3_SIZE |
19173 | #define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 |
19174 | #define GDS_VMID3_SIZE__UNUSED__SHIFT 0x11 |
19175 | #define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL |
19176 | #define GDS_VMID3_SIZE__UNUSED_MASK 0xFFFE0000L |
19177 | //GDS_VMID4_BASE |
19178 | #define GDS_VMID4_BASE__BASE__SHIFT 0x0 |
19179 | #define GDS_VMID4_BASE__UNUSED__SHIFT 0x10 |
19180 | #define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL |
19181 | #define GDS_VMID4_BASE__UNUSED_MASK 0xFFFF0000L |
19182 | //GDS_VMID4_SIZE |
19183 | #define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 |
19184 | #define GDS_VMID4_SIZE__UNUSED__SHIFT 0x11 |
19185 | #define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL |
19186 | #define GDS_VMID4_SIZE__UNUSED_MASK 0xFFFE0000L |
19187 | //GDS_VMID5_BASE |
19188 | #define GDS_VMID5_BASE__BASE__SHIFT 0x0 |
19189 | #define GDS_VMID5_BASE__UNUSED__SHIFT 0x10 |
19190 | #define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL |
19191 | #define GDS_VMID5_BASE__UNUSED_MASK 0xFFFF0000L |
19192 | //GDS_VMID5_SIZE |
19193 | #define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 |
19194 | #define GDS_VMID5_SIZE__UNUSED__SHIFT 0x11 |
19195 | #define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL |
19196 | #define GDS_VMID5_SIZE__UNUSED_MASK 0xFFFE0000L |
19197 | //GDS_VMID6_BASE |
19198 | #define GDS_VMID6_BASE__BASE__SHIFT 0x0 |
19199 | #define GDS_VMID6_BASE__UNUSED__SHIFT 0x10 |
19200 | #define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL |
19201 | #define GDS_VMID6_BASE__UNUSED_MASK 0xFFFF0000L |
19202 | //GDS_VMID6_SIZE |
19203 | #define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 |
19204 | #define GDS_VMID6_SIZE__UNUSED__SHIFT 0x11 |
19205 | #define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL |
19206 | #define GDS_VMID6_SIZE__UNUSED_MASK 0xFFFE0000L |
19207 | //GDS_VMID7_BASE |
19208 | #define GDS_VMID7_BASE__BASE__SHIFT 0x0 |
19209 | #define GDS_VMID7_BASE__UNUSED__SHIFT 0x10 |
19210 | #define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL |
19211 | #define GDS_VMID7_BASE__UNUSED_MASK 0xFFFF0000L |
19212 | //GDS_VMID7_SIZE |
19213 | #define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 |
19214 | #define GDS_VMID7_SIZE__UNUSED__SHIFT 0x11 |
19215 | #define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL |
19216 | #define GDS_VMID7_SIZE__UNUSED_MASK 0xFFFE0000L |
19217 | //GDS_VMID8_BASE |
19218 | #define GDS_VMID8_BASE__BASE__SHIFT 0x0 |
19219 | #define GDS_VMID8_BASE__UNUSED__SHIFT 0x10 |
19220 | #define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL |
19221 | #define GDS_VMID8_BASE__UNUSED_MASK 0xFFFF0000L |
19222 | //GDS_VMID8_SIZE |
19223 | #define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 |
19224 | #define GDS_VMID8_SIZE__UNUSED__SHIFT 0x11 |
19225 | #define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL |
19226 | #define GDS_VMID8_SIZE__UNUSED_MASK 0xFFFE0000L |
19227 | //GDS_VMID9_BASE |
19228 | #define GDS_VMID9_BASE__BASE__SHIFT 0x0 |
19229 | #define GDS_VMID9_BASE__UNUSED__SHIFT 0x10 |
19230 | #define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL |
19231 | #define GDS_VMID9_BASE__UNUSED_MASK 0xFFFF0000L |
19232 | //GDS_VMID9_SIZE |
19233 | #define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 |
19234 | #define GDS_VMID9_SIZE__UNUSED__SHIFT 0x11 |
19235 | #define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL |
19236 | #define GDS_VMID9_SIZE__UNUSED_MASK 0xFFFE0000L |
19237 | //GDS_VMID10_BASE |
19238 | #define GDS_VMID10_BASE__BASE__SHIFT 0x0 |
19239 | #define GDS_VMID10_BASE__UNUSED__SHIFT 0x10 |
19240 | #define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL |
19241 | #define GDS_VMID10_BASE__UNUSED_MASK 0xFFFF0000L |
19242 | //GDS_VMID10_SIZE |
19243 | #define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 |
19244 | #define GDS_VMID10_SIZE__UNUSED__SHIFT 0x11 |
19245 | #define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL |
19246 | #define GDS_VMID10_SIZE__UNUSED_MASK 0xFFFE0000L |
19247 | //GDS_VMID11_BASE |
19248 | #define GDS_VMID11_BASE__BASE__SHIFT 0x0 |
19249 | #define GDS_VMID11_BASE__UNUSED__SHIFT 0x10 |
19250 | #define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL |
19251 | #define GDS_VMID11_BASE__UNUSED_MASK 0xFFFF0000L |
19252 | //GDS_VMID11_SIZE |
19253 | #define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 |
19254 | #define GDS_VMID11_SIZE__UNUSED__SHIFT 0x11 |
19255 | #define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL |
19256 | #define GDS_VMID11_SIZE__UNUSED_MASK 0xFFFE0000L |
19257 | //GDS_VMID12_BASE |
19258 | #define GDS_VMID12_BASE__BASE__SHIFT 0x0 |
19259 | #define GDS_VMID12_BASE__UNUSED__SHIFT 0x10 |
19260 | #define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL |
19261 | #define GDS_VMID12_BASE__UNUSED_MASK 0xFFFF0000L |
19262 | //GDS_VMID12_SIZE |
19263 | #define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 |
19264 | #define GDS_VMID12_SIZE__UNUSED__SHIFT 0x11 |
19265 | #define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL |
19266 | #define GDS_VMID12_SIZE__UNUSED_MASK 0xFFFE0000L |
19267 | //GDS_VMID13_BASE |
19268 | #define GDS_VMID13_BASE__BASE__SHIFT 0x0 |
19269 | #define GDS_VMID13_BASE__UNUSED__SHIFT 0x10 |
19270 | #define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL |
19271 | #define GDS_VMID13_BASE__UNUSED_MASK 0xFFFF0000L |
19272 | //GDS_VMID13_SIZE |
19273 | #define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 |
19274 | #define GDS_VMID13_SIZE__UNUSED__SHIFT 0x11 |
19275 | #define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL |
19276 | #define GDS_VMID13_SIZE__UNUSED_MASK 0xFFFE0000L |
19277 | //GDS_VMID14_BASE |
19278 | #define GDS_VMID14_BASE__BASE__SHIFT 0x0 |
19279 | #define GDS_VMID14_BASE__UNUSED__SHIFT 0x10 |
19280 | #define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL |
19281 | #define GDS_VMID14_BASE__UNUSED_MASK 0xFFFF0000L |
19282 | //GDS_VMID14_SIZE |
19283 | #define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 |
19284 | #define GDS_VMID14_SIZE__UNUSED__SHIFT 0x11 |
19285 | #define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL |
19286 | #define GDS_VMID14_SIZE__UNUSED_MASK 0xFFFE0000L |
19287 | //GDS_VMID15_BASE |
19288 | #define GDS_VMID15_BASE__BASE__SHIFT 0x0 |
19289 | #define GDS_VMID15_BASE__UNUSED__SHIFT 0x10 |
19290 | #define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL |
19291 | #define GDS_VMID15_BASE__UNUSED_MASK 0xFFFF0000L |
19292 | //GDS_VMID15_SIZE |
19293 | #define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 |
19294 | #define GDS_VMID15_SIZE__UNUSED__SHIFT 0x11 |
19295 | #define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL |
19296 | #define GDS_VMID15_SIZE__UNUSED_MASK 0xFFFE0000L |
19297 | //GDS_GWS_VMID0 |
19298 | #define GDS_GWS_VMID0__BASE__SHIFT 0x0 |
19299 | #define GDS_GWS_VMID0__UNUSED1__SHIFT 0x6 |
19300 | #define GDS_GWS_VMID0__SIZE__SHIFT 0x10 |
19301 | #define GDS_GWS_VMID0__UNUSED2__SHIFT 0x17 |
19302 | #define GDS_GWS_VMID0__BASE_MASK 0x0000003FL |
19303 | #define GDS_GWS_VMID0__UNUSED1_MASK 0x0000FFC0L |
19304 | #define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L |
19305 | #define GDS_GWS_VMID0__UNUSED2_MASK 0xFF800000L |
19306 | //GDS_GWS_VMID1 |
19307 | #define GDS_GWS_VMID1__BASE__SHIFT 0x0 |
19308 | #define GDS_GWS_VMID1__UNUSED1__SHIFT 0x6 |
19309 | #define GDS_GWS_VMID1__SIZE__SHIFT 0x10 |
19310 | #define GDS_GWS_VMID1__UNUSED2__SHIFT 0x17 |
19311 | #define GDS_GWS_VMID1__BASE_MASK 0x0000003FL |
19312 | #define GDS_GWS_VMID1__UNUSED1_MASK 0x0000FFC0L |
19313 | #define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L |
19314 | #define GDS_GWS_VMID1__UNUSED2_MASK 0xFF800000L |
19315 | //GDS_GWS_VMID2 |
19316 | #define GDS_GWS_VMID2__BASE__SHIFT 0x0 |
19317 | #define GDS_GWS_VMID2__UNUSED1__SHIFT 0x6 |
19318 | #define GDS_GWS_VMID2__SIZE__SHIFT 0x10 |
19319 | #define GDS_GWS_VMID2__UNUSED2__SHIFT 0x17 |
19320 | #define GDS_GWS_VMID2__BASE_MASK 0x0000003FL |
19321 | #define GDS_GWS_VMID2__UNUSED1_MASK 0x0000FFC0L |
19322 | #define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L |
19323 | #define GDS_GWS_VMID2__UNUSED2_MASK 0xFF800000L |
19324 | //GDS_GWS_VMID3 |
19325 | #define GDS_GWS_VMID3__BASE__SHIFT 0x0 |
19326 | #define GDS_GWS_VMID3__UNUSED1__SHIFT 0x6 |
19327 | #define GDS_GWS_VMID3__SIZE__SHIFT 0x10 |
19328 | #define GDS_GWS_VMID3__UNUSED2__SHIFT 0x17 |
19329 | #define GDS_GWS_VMID3__BASE_MASK 0x0000003FL |
19330 | #define GDS_GWS_VMID3__UNUSED1_MASK 0x0000FFC0L |
19331 | #define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L |
19332 | #define GDS_GWS_VMID3__UNUSED2_MASK 0xFF800000L |
19333 | //GDS_GWS_VMID4 |
19334 | #define GDS_GWS_VMID4__BASE__SHIFT 0x0 |
19335 | #define GDS_GWS_VMID4__UNUSED1__SHIFT 0x6 |
19336 | #define GDS_GWS_VMID4__SIZE__SHIFT 0x10 |
19337 | #define GDS_GWS_VMID4__UNUSED2__SHIFT 0x17 |
19338 | #define GDS_GWS_VMID4__BASE_MASK 0x0000003FL |
19339 | #define GDS_GWS_VMID4__UNUSED1_MASK 0x0000FFC0L |
19340 | #define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L |
19341 | #define GDS_GWS_VMID4__UNUSED2_MASK 0xFF800000L |
19342 | //GDS_GWS_VMID5 |
19343 | #define GDS_GWS_VMID5__BASE__SHIFT 0x0 |
19344 | #define GDS_GWS_VMID5__UNUSED1__SHIFT 0x6 |
19345 | #define GDS_GWS_VMID5__SIZE__SHIFT 0x10 |
19346 | #define GDS_GWS_VMID5__UNUSED2__SHIFT 0x17 |
19347 | #define GDS_GWS_VMID5__BASE_MASK 0x0000003FL |
19348 | #define GDS_GWS_VMID5__UNUSED1_MASK 0x0000FFC0L |
19349 | #define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L |
19350 | #define GDS_GWS_VMID5__UNUSED2_MASK 0xFF800000L |
19351 | //GDS_GWS_VMID6 |
19352 | #define GDS_GWS_VMID6__BASE__SHIFT 0x0 |
19353 | #define GDS_GWS_VMID6__UNUSED1__SHIFT 0x6 |
19354 | #define GDS_GWS_VMID6__SIZE__SHIFT 0x10 |
19355 | #define GDS_GWS_VMID6__UNUSED2__SHIFT 0x17 |
19356 | #define GDS_GWS_VMID6__BASE_MASK 0x0000003FL |
19357 | #define GDS_GWS_VMID6__UNUSED1_MASK 0x0000FFC0L |
19358 | #define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L |
19359 | #define GDS_GWS_VMID6__UNUSED2_MASK 0xFF800000L |
19360 | //GDS_GWS_VMID7 |
19361 | #define GDS_GWS_VMID7__BASE__SHIFT 0x0 |
19362 | #define GDS_GWS_VMID7__UNUSED1__SHIFT 0x6 |
19363 | #define GDS_GWS_VMID7__SIZE__SHIFT 0x10 |
19364 | #define GDS_GWS_VMID7__UNUSED2__SHIFT 0x17 |
19365 | #define GDS_GWS_VMID7__BASE_MASK 0x0000003FL |
19366 | #define GDS_GWS_VMID7__UNUSED1_MASK 0x0000FFC0L |
19367 | #define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L |
19368 | #define GDS_GWS_VMID7__UNUSED2_MASK 0xFF800000L |
19369 | //GDS_GWS_VMID8 |
19370 | #define GDS_GWS_VMID8__BASE__SHIFT 0x0 |
19371 | #define GDS_GWS_VMID8__UNUSED1__SHIFT 0x6 |
19372 | #define GDS_GWS_VMID8__SIZE__SHIFT 0x10 |
19373 | #define GDS_GWS_VMID8__UNUSED2__SHIFT 0x17 |
19374 | #define GDS_GWS_VMID8__BASE_MASK 0x0000003FL |
19375 | #define GDS_GWS_VMID8__UNUSED1_MASK 0x0000FFC0L |
19376 | #define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L |
19377 | #define GDS_GWS_VMID8__UNUSED2_MASK 0xFF800000L |
19378 | //GDS_GWS_VMID9 |
19379 | #define GDS_GWS_VMID9__BASE__SHIFT 0x0 |
19380 | #define GDS_GWS_VMID9__UNUSED1__SHIFT 0x6 |
19381 | #define GDS_GWS_VMID9__SIZE__SHIFT 0x10 |
19382 | #define GDS_GWS_VMID9__UNUSED2__SHIFT 0x17 |
19383 | #define GDS_GWS_VMID9__BASE_MASK 0x0000003FL |
19384 | #define GDS_GWS_VMID9__UNUSED1_MASK 0x0000FFC0L |
19385 | #define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L |
19386 | #define GDS_GWS_VMID9__UNUSED2_MASK 0xFF800000L |
19387 | //GDS_GWS_VMID10 |
19388 | #define GDS_GWS_VMID10__BASE__SHIFT 0x0 |
19389 | #define GDS_GWS_VMID10__UNUSED1__SHIFT 0x6 |
19390 | #define GDS_GWS_VMID10__SIZE__SHIFT 0x10 |
19391 | #define GDS_GWS_VMID10__UNUSED2__SHIFT 0x17 |
19392 | #define GDS_GWS_VMID10__BASE_MASK 0x0000003FL |
19393 | #define GDS_GWS_VMID10__UNUSED1_MASK 0x0000FFC0L |
19394 | #define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L |
19395 | #define GDS_GWS_VMID10__UNUSED2_MASK 0xFF800000L |
19396 | //GDS_GWS_VMID11 |
19397 | #define GDS_GWS_VMID11__BASE__SHIFT 0x0 |
19398 | #define GDS_GWS_VMID11__UNUSED1__SHIFT 0x6 |
19399 | #define GDS_GWS_VMID11__SIZE__SHIFT 0x10 |
19400 | #define GDS_GWS_VMID11__UNUSED2__SHIFT 0x17 |
19401 | #define GDS_GWS_VMID11__BASE_MASK 0x0000003FL |
19402 | #define GDS_GWS_VMID11__UNUSED1_MASK 0x0000FFC0L |
19403 | #define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L |
19404 | #define GDS_GWS_VMID11__UNUSED2_MASK 0xFF800000L |
19405 | //GDS_GWS_VMID12 |
19406 | #define GDS_GWS_VMID12__BASE__SHIFT 0x0 |
19407 | #define GDS_GWS_VMID12__UNUSED1__SHIFT 0x6 |
19408 | #define GDS_GWS_VMID12__SIZE__SHIFT 0x10 |
19409 | #define GDS_GWS_VMID12__UNUSED2__SHIFT 0x17 |
19410 | #define GDS_GWS_VMID12__BASE_MASK 0x0000003FL |
19411 | #define GDS_GWS_VMID12__UNUSED1_MASK 0x0000FFC0L |
19412 | #define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L |
19413 | #define GDS_GWS_VMID12__UNUSED2_MASK 0xFF800000L |
19414 | //GDS_GWS_VMID13 |
19415 | #define GDS_GWS_VMID13__BASE__SHIFT 0x0 |
19416 | #define GDS_GWS_VMID13__UNUSED1__SHIFT 0x6 |
19417 | #define GDS_GWS_VMID13__SIZE__SHIFT 0x10 |
19418 | #define GDS_GWS_VMID13__UNUSED2__SHIFT 0x17 |
19419 | #define GDS_GWS_VMID13__BASE_MASK 0x0000003FL |
19420 | #define GDS_GWS_VMID13__UNUSED1_MASK 0x0000FFC0L |
19421 | #define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L |
19422 | #define GDS_GWS_VMID13__UNUSED2_MASK 0xFF800000L |
19423 | //GDS_GWS_VMID14 |
19424 | #define GDS_GWS_VMID14__BASE__SHIFT 0x0 |
19425 | #define GDS_GWS_VMID14__UNUSED1__SHIFT 0x6 |
19426 | #define GDS_GWS_VMID14__SIZE__SHIFT 0x10 |
19427 | #define GDS_GWS_VMID14__UNUSED2__SHIFT 0x17 |
19428 | #define GDS_GWS_VMID14__BASE_MASK 0x0000003FL |
19429 | #define GDS_GWS_VMID14__UNUSED1_MASK 0x0000FFC0L |
19430 | #define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L |
19431 | #define GDS_GWS_VMID14__UNUSED2_MASK 0xFF800000L |
19432 | //GDS_GWS_VMID15 |
19433 | #define GDS_GWS_VMID15__BASE__SHIFT 0x0 |
19434 | #define GDS_GWS_VMID15__UNUSED1__SHIFT 0x6 |
19435 | #define GDS_GWS_VMID15__SIZE__SHIFT 0x10 |
19436 | #define GDS_GWS_VMID15__UNUSED2__SHIFT 0x17 |
19437 | #define GDS_GWS_VMID15__BASE_MASK 0x0000003FL |
19438 | #define GDS_GWS_VMID15__UNUSED1_MASK 0x0000FFC0L |
19439 | #define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L |
19440 | #define GDS_GWS_VMID15__UNUSED2_MASK 0xFF800000L |
19441 | //GDS_OA_VMID0 |
19442 | #define GDS_OA_VMID0__MASK__SHIFT 0x0 |
19443 | #define GDS_OA_VMID0__UNUSED__SHIFT 0x10 |
19444 | #define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL |
19445 | #define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L |
19446 | //GDS_OA_VMID1 |
19447 | #define GDS_OA_VMID1__MASK__SHIFT 0x0 |
19448 | #define GDS_OA_VMID1__UNUSED__SHIFT 0x10 |
19449 | #define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL |
19450 | #define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L |
19451 | //GDS_OA_VMID2 |
19452 | #define GDS_OA_VMID2__MASK__SHIFT 0x0 |
19453 | #define GDS_OA_VMID2__UNUSED__SHIFT 0x10 |
19454 | #define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL |
19455 | #define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L |
19456 | //GDS_OA_VMID3 |
19457 | #define GDS_OA_VMID3__MASK__SHIFT 0x0 |
19458 | #define GDS_OA_VMID3__UNUSED__SHIFT 0x10 |
19459 | #define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL |
19460 | #define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L |
19461 | //GDS_OA_VMID4 |
19462 | #define GDS_OA_VMID4__MASK__SHIFT 0x0 |
19463 | #define GDS_OA_VMID4__UNUSED__SHIFT 0x10 |
19464 | #define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL |
19465 | #define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L |
19466 | //GDS_OA_VMID5 |
19467 | #define GDS_OA_VMID5__MASK__SHIFT 0x0 |
19468 | #define GDS_OA_VMID5__UNUSED__SHIFT 0x10 |
19469 | #define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL |
19470 | #define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L |
19471 | //GDS_OA_VMID6 |
19472 | #define GDS_OA_VMID6__MASK__SHIFT 0x0 |
19473 | #define GDS_OA_VMID6__UNUSED__SHIFT 0x10 |
19474 | #define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL |
19475 | #define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L |
19476 | //GDS_OA_VMID7 |
19477 | #define GDS_OA_VMID7__MASK__SHIFT 0x0 |
19478 | #define GDS_OA_VMID7__UNUSED__SHIFT 0x10 |
19479 | #define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL |
19480 | #define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L |
19481 | //GDS_OA_VMID8 |
19482 | #define GDS_OA_VMID8__MASK__SHIFT 0x0 |
19483 | #define GDS_OA_VMID8__UNUSED__SHIFT 0x10 |
19484 | #define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL |
19485 | #define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L |
19486 | //GDS_OA_VMID9 |
19487 | #define GDS_OA_VMID9__MASK__SHIFT 0x0 |
19488 | #define GDS_OA_VMID9__UNUSED__SHIFT 0x10 |
19489 | #define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL |
19490 | #define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L |
19491 | //GDS_OA_VMID10 |
19492 | #define GDS_OA_VMID10__MASK__SHIFT 0x0 |
19493 | #define GDS_OA_VMID10__UNUSED__SHIFT 0x10 |
19494 | #define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL |
19495 | #define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L |
19496 | //GDS_OA_VMID11 |
19497 | #define GDS_OA_VMID11__MASK__SHIFT 0x0 |
19498 | #define GDS_OA_VMID11__UNUSED__SHIFT 0x10 |
19499 | #define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL |
19500 | #define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L |
19501 | //GDS_OA_VMID12 |
19502 | #define GDS_OA_VMID12__MASK__SHIFT 0x0 |
19503 | #define GDS_OA_VMID12__UNUSED__SHIFT 0x10 |
19504 | #define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL |
19505 | #define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L |
19506 | //GDS_OA_VMID13 |
19507 | #define GDS_OA_VMID13__MASK__SHIFT 0x0 |
19508 | #define GDS_OA_VMID13__UNUSED__SHIFT 0x10 |
19509 | #define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL |
19510 | #define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L |
19511 | //GDS_OA_VMID14 |
19512 | #define GDS_OA_VMID14__MASK__SHIFT 0x0 |
19513 | #define GDS_OA_VMID14__UNUSED__SHIFT 0x10 |
19514 | #define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL |
19515 | #define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L |
19516 | //GDS_OA_VMID15 |
19517 | #define GDS_OA_VMID15__MASK__SHIFT 0x0 |
19518 | #define GDS_OA_VMID15__UNUSED__SHIFT 0x10 |
19519 | #define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL |
19520 | #define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L |
19521 | //GDS_GWS_RESET0 |
19522 | #define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 |
19523 | #define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 |
19524 | #define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 |
19525 | #define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 |
19526 | #define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 |
19527 | #define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 |
19528 | #define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 |
19529 | #define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 |
19530 | #define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 |
19531 | #define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 |
19532 | #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa |
19533 | #define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb |
19534 | #define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc |
19535 | #define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd |
19536 | #define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe |
19537 | #define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf |
19538 | #define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 |
19539 | #define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 |
19540 | #define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 |
19541 | #define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 |
19542 | #define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 |
19543 | #define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 |
19544 | #define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 |
19545 | #define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 |
19546 | #define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 |
19547 | #define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 |
19548 | #define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a |
19549 | #define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b |
19550 | #define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c |
19551 | #define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d |
19552 | #define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e |
19553 | #define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f |
19554 | #define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L |
19555 | #define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L |
19556 | #define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L |
19557 | #define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L |
19558 | #define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L |
19559 | #define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L |
19560 | #define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L |
19561 | #define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L |
19562 | #define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L |
19563 | #define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L |
19564 | #define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L |
19565 | #define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L |
19566 | #define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L |
19567 | #define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L |
19568 | #define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L |
19569 | #define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L |
19570 | #define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L |
19571 | #define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L |
19572 | #define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L |
19573 | #define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L |
19574 | #define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L |
19575 | #define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L |
19576 | #define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L |
19577 | #define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L |
19578 | #define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L |
19579 | #define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L |
19580 | #define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L |
19581 | #define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L |
19582 | #define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L |
19583 | #define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L |
19584 | #define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L |
19585 | #define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L |
19586 | //GDS_GWS_RESET1 |
19587 | #define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 |
19588 | #define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 |
19589 | #define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 |
19590 | #define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 |
19591 | #define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 |
19592 | #define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 |
19593 | #define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 |
19594 | #define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 |
19595 | #define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 |
19596 | #define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 |
19597 | #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa |
19598 | #define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb |
19599 | #define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc |
19600 | #define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd |
19601 | #define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe |
19602 | #define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf |
19603 | #define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 |
19604 | #define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 |
19605 | #define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 |
19606 | #define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 |
19607 | #define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 |
19608 | #define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 |
19609 | #define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 |
19610 | #define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 |
19611 | #define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 |
19612 | #define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 |
19613 | #define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a |
19614 | #define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b |
19615 | #define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c |
19616 | #define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d |
19617 | #define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e |
19618 | #define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f |
19619 | #define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L |
19620 | #define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L |
19621 | #define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L |
19622 | #define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L |
19623 | #define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L |
19624 | #define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L |
19625 | #define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L |
19626 | #define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L |
19627 | #define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L |
19628 | #define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L |
19629 | #define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L |
19630 | #define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L |
19631 | #define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L |
19632 | #define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L |
19633 | #define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L |
19634 | #define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L |
19635 | #define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L |
19636 | #define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L |
19637 | #define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L |
19638 | #define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L |
19639 | #define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L |
19640 | #define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L |
19641 | #define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L |
19642 | #define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L |
19643 | #define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L |
19644 | #define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L |
19645 | #define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L |
19646 | #define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L |
19647 | #define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L |
19648 | #define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L |
19649 | #define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L |
19650 | #define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L |
19651 | //GDS_GWS_RESOURCE_RESET |
19652 | #define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 |
19653 | #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 |
19654 | #define GDS_GWS_RESOURCE_RESET__UNUSED__SHIFT 0x10 |
19655 | #define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L |
19656 | #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L |
19657 | #define GDS_GWS_RESOURCE_RESET__UNUSED_MASK 0xFFFF0000L |
19658 | //GDS_COMPUTE_MAX_WAVE_ID |
19659 | #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
19660 | #define GDS_COMPUTE_MAX_WAVE_ID__UNUSED__SHIFT 0xc |
19661 | #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
19662 | #define GDS_COMPUTE_MAX_WAVE_ID__UNUSED_MASK 0xFFFFF000L |
19663 | //GDS_OA_RESET_MASK |
19664 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 |
19665 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 |
19666 | #define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 |
19667 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3 |
19668 | #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 |
19669 | #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 |
19670 | #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 |
19671 | #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 |
19672 | #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 |
19673 | #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 |
19674 | #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa |
19675 | #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb |
19676 | #define GDS_OA_RESET_MASK__ME0_PIPE1_CS_RESET__SHIFT 0xc |
19677 | #define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xd |
19678 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L |
19679 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L |
19680 | #define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L |
19681 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L |
19682 | #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L |
19683 | #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L |
19684 | #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L |
19685 | #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L |
19686 | #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L |
19687 | #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L |
19688 | #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L |
19689 | #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L |
19690 | #define GDS_OA_RESET_MASK__ME0_PIPE1_CS_RESET_MASK 0x00001000L |
19691 | #define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFE000L |
19692 | //GDS_OA_RESET |
19693 | #define GDS_OA_RESET__RESET__SHIFT 0x0 |
19694 | #define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 |
19695 | #define GDS_OA_RESET__UNUSED__SHIFT 0x10 |
19696 | #define GDS_OA_RESET__RESET_MASK 0x00000001L |
19697 | #define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L |
19698 | #define GDS_OA_RESET__UNUSED_MASK 0xFFFF0000L |
19699 | //GDS_ENHANCE2 |
19700 | #define GDS_ENHANCE2__MISC__SHIFT 0x0 |
19701 | #define GDS_ENHANCE2__RD_BUF_TAG_MISS__SHIFT 0x12 |
19702 | #define GDS_ENHANCE2__GDS_INTERFACES_FGCG_OVERRIDE__SHIFT 0x15 |
19703 | #define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS__SHIFT 0x16 |
19704 | #define GDS_ENHANCE2__DISABLE_LOGIC_ID_CLAMP__SHIFT 0x17 |
19705 | #define GDS_ENHANCE2__DISABLE_MEMORY_VIOLATION_REPORT__SHIFT 0x18 |
19706 | #define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS_MGCG_DSO__SHIFT 0x19 |
19707 | #define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS_MGCG_DSA__SHIFT 0x1d |
19708 | #define GDS_ENHANCE2__MISC_MASK 0x0003FFFFL |
19709 | #define GDS_ENHANCE2__RD_BUF_TAG_MISS_MASK 0x00040000L |
19710 | #define GDS_ENHANCE2__GDS_INTERFACES_FGCG_OVERRIDE_MASK 0x00200000L |
19711 | #define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS_MASK 0x00400000L |
19712 | #define GDS_ENHANCE2__DISABLE_LOGIC_ID_CLAMP_MASK 0x00800000L |
19713 | #define GDS_ENHANCE2__DISABLE_MEMORY_VIOLATION_REPORT_MASK 0x01000000L |
19714 | #define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS_MGCG_DSO_MASK 0x1E000000L |
19715 | #define GDS_ENHANCE2__GDS_CLK_ENHANCE_DIS_MGCG_DSA_MASK 0xE0000000L |
19716 | //GDS_OA_CGPG_RESTORE |
19717 | #define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 |
19718 | #define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 |
19719 | #define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc |
19720 | #define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 |
19721 | #define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 |
19722 | #define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL |
19723 | #define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L |
19724 | #define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L |
19725 | #define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L |
19726 | #define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L |
19727 | //GDS_CS_CTXSW_STATUS |
19728 | #define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 |
19729 | #define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 |
19730 | #define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 |
19731 | #define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L |
19732 | #define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L |
19733 | #define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL |
19734 | //GDS_CS_CTXSW_CNT0 |
19735 | #define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 |
19736 | #define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 |
19737 | #define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
19738 | #define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
19739 | //GDS_CS_CTXSW_CNT1 |
19740 | #define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 |
19741 | #define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 |
19742 | #define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
19743 | #define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
19744 | //GDS_CS_CTXSW_CNT2 |
19745 | #define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 |
19746 | #define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 |
19747 | #define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
19748 | #define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
19749 | //GDS_CS_CTXSW_CNT3 |
19750 | #define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 |
19751 | #define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 |
19752 | #define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
19753 | #define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
19754 | //GDS_GFX_CTXSW_STATUS |
19755 | #define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 |
19756 | #define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 |
19757 | #define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 |
19758 | #define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L |
19759 | #define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L |
19760 | #define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL |
19761 | //GDS_VS_CTXSW_CNT0 |
19762 | #define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0 |
19763 | #define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10 |
19764 | #define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
19765 | #define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
19766 | //GDS_VS_CTXSW_CNT1 |
19767 | #define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0 |
19768 | #define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10 |
19769 | #define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
19770 | #define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
19771 | //GDS_VS_CTXSW_CNT2 |
19772 | #define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0 |
19773 | #define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10 |
19774 | #define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
19775 | #define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
19776 | //GDS_VS_CTXSW_CNT3 |
19777 | #define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0 |
19778 | #define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10 |
19779 | #define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
19780 | #define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
19781 | //GDS_PS_CTXSW_CNT0 |
19782 | #define GDS_PS_CTXSW_CNT0__UPDN__SHIFT 0x0 |
19783 | #define GDS_PS_CTXSW_CNT0__PTR__SHIFT 0x10 |
19784 | #define GDS_PS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
19785 | #define GDS_PS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
19786 | //GDS_PS_CTXSW_CNT1 |
19787 | #define GDS_PS_CTXSW_CNT1__UPDN__SHIFT 0x0 |
19788 | #define GDS_PS_CTXSW_CNT1__PTR__SHIFT 0x10 |
19789 | #define GDS_PS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
19790 | #define GDS_PS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
19791 | //GDS_PS_CTXSW_CNT2 |
19792 | #define GDS_PS_CTXSW_CNT2__UPDN__SHIFT 0x0 |
19793 | #define GDS_PS_CTXSW_CNT2__PTR__SHIFT 0x10 |
19794 | #define GDS_PS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
19795 | #define GDS_PS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
19796 | //GDS_PS_CTXSW_CNT3 |
19797 | #define GDS_PS_CTXSW_CNT3__UPDN__SHIFT 0x0 |
19798 | #define GDS_PS_CTXSW_CNT3__PTR__SHIFT 0x10 |
19799 | #define GDS_PS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
19800 | #define GDS_PS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
19801 | //GDS_PS_CTXSW_IDX |
19802 | #define GDS_PS_CTXSW_IDX__PACKER_ID__SHIFT 0x0 |
19803 | #define GDS_PS_CTXSW_IDX__UNUSED__SHIFT 0x4 |
19804 | #define GDS_PS_CTXSW_IDX__PACKER_ID_MASK 0x0000000FL |
19805 | #define GDS_PS_CTXSW_IDX__UNUSED_MASK 0xFFFFFFF0L |
19806 | //GDS_GS_CTXSW_CNT0 |
19807 | #define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0 |
19808 | #define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10 |
19809 | #define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
19810 | #define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
19811 | //GDS_GS_CTXSW_CNT1 |
19812 | #define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0 |
19813 | #define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10 |
19814 | #define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
19815 | #define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
19816 | //GDS_GS_CTXSW_CNT2 |
19817 | #define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0 |
19818 | #define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10 |
19819 | #define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
19820 | #define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
19821 | //GDS_GS_CTXSW_CNT3 |
19822 | #define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0 |
19823 | #define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10 |
19824 | #define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
19825 | #define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
19826 | //GDS_MEMORY_CLEAN |
19827 | #define GDS_MEMORY_CLEAN__START__SHIFT 0x0 |
19828 | #define GDS_MEMORY_CLEAN__FINISH__SHIFT 0x1 |
19829 | #define GDS_MEMORY_CLEAN__UNUSED__SHIFT 0x2 |
19830 | #define GDS_MEMORY_CLEAN__START_MASK 0x00000001L |
19831 | #define GDS_MEMORY_CLEAN__FINISH_MASK 0x00000002L |
19832 | #define GDS_MEMORY_CLEAN__UNUSED_MASK 0xFFFFFFFCL |
19833 | |
19834 | |
19835 | // addressBlock: gc_gfxdec0 |
19836 | //DB_RENDER_CONTROL |
19837 | #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 |
19838 | #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 |
19839 | #define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 |
19840 | #define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 |
19841 | #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 |
19842 | #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 |
19843 | #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 |
19844 | #define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 |
19845 | #define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 |
19846 | #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc |
19847 | #define DB_RENDER_CONTROL__PS_INVOKE_DISABLE__SHIFT 0xd |
19848 | #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L |
19849 | #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L |
19850 | #define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L |
19851 | #define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L |
19852 | #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L |
19853 | #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L |
19854 | #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L |
19855 | #define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L |
19856 | #define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L |
19857 | #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L |
19858 | #define DB_RENDER_CONTROL__PS_INVOKE_DISABLE_MASK 0x00002000L |
19859 | //DB_COUNT_CONTROL |
19860 | #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 |
19861 | #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 |
19862 | #define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS__SHIFT 0x2 |
19863 | #define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS__SHIFT 0x3 |
19864 | #define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 |
19865 | #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 |
19866 | #define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc |
19867 | #define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 |
19868 | #define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 |
19869 | #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 |
19870 | #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c |
19871 | #define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L |
19872 | #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L |
19873 | #define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS_MASK 0x00000004L |
19874 | #define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS_MASK 0x00000008L |
19875 | #define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L |
19876 | #define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L |
19877 | #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L |
19878 | #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L |
19879 | #define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L |
19880 | #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L |
19881 | #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L |
19882 | //DB_DEPTH_VIEW |
19883 | #define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 |
19884 | #define DB_DEPTH_VIEW__SLICE_START_HI__SHIFT 0xb |
19885 | #define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd |
19886 | #define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 |
19887 | #define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 |
19888 | #define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a |
19889 | #define DB_DEPTH_VIEW__SLICE_MAX_HI__SHIFT 0x1e |
19890 | #define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL |
19891 | #define DB_DEPTH_VIEW__SLICE_START_HI_MASK 0x00001800L |
19892 | #define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L |
19893 | #define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L |
19894 | #define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L |
19895 | #define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L |
19896 | #define DB_DEPTH_VIEW__SLICE_MAX_HI_MASK 0xC0000000L |
19897 | //DB_RENDER_OVERRIDE |
19898 | #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 |
19899 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 |
19900 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 |
19901 | #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 |
19902 | #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 |
19903 | #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 |
19904 | #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 |
19905 | #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa |
19906 | #define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb |
19907 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc |
19908 | #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd |
19909 | #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf |
19910 | #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 |
19911 | #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 |
19912 | #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 |
19913 | #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 |
19914 | #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 |
19915 | #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a |
19916 | #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b |
19917 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c |
19918 | #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d |
19919 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e |
19920 | #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f |
19921 | #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L |
19922 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL |
19923 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L |
19924 | #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L |
19925 | #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L |
19926 | #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L |
19927 | #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L |
19928 | #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L |
19929 | #define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L |
19930 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L |
19931 | #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L |
19932 | #define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L |
19933 | #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L |
19934 | #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L |
19935 | #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L |
19936 | #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L |
19937 | #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L |
19938 | #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L |
19939 | #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L |
19940 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L |
19941 | #define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L |
19942 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L |
19943 | #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L |
19944 | //DB_RENDER_OVERRIDE2 |
19945 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 |
19946 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 |
19947 | #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 |
19948 | #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 |
19949 | #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 |
19950 | #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 |
19951 | #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 |
19952 | #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa |
19953 | #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb |
19954 | #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc |
19955 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf |
19956 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 |
19957 | #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 |
19958 | #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 |
19959 | #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 |
19960 | #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 |
19961 | #define DB_RENDER_OVERRIDE2__FORCE_VRS_RATE_FINE__SHIFT 0x1a |
19962 | #define DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE__SHIFT 0x1b |
19963 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L |
19964 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL |
19965 | #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L |
19966 | #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L |
19967 | #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L |
19968 | #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L |
19969 | #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L |
19970 | #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L |
19971 | #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L |
19972 | #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L |
19973 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L |
19974 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L |
19975 | #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L |
19976 | #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L |
19977 | #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L |
19978 | #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L |
19979 | #define DB_RENDER_OVERRIDE2__FORCE_VRS_RATE_FINE_MASK 0x04000000L |
19980 | #define DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE_MASK 0x18000000L |
19981 | //DB_HTILE_DATA_BASE |
19982 | #define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 |
19983 | #define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL |
19984 | //DB_DEPTH_SIZE_XY |
19985 | #define DB_DEPTH_SIZE_XY__X_MAX__SHIFT 0x0 |
19986 | #define DB_DEPTH_SIZE_XY__Y_MAX__SHIFT 0x10 |
19987 | #define DB_DEPTH_SIZE_XY__X_MAX_MASK 0x00003FFFL |
19988 | #define DB_DEPTH_SIZE_XY__Y_MAX_MASK 0x3FFF0000L |
19989 | //DB_DEPTH_BOUNDS_MIN |
19990 | #define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 |
19991 | #define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL |
19992 | //DB_DEPTH_BOUNDS_MAX |
19993 | #define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 |
19994 | #define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL |
19995 | //DB_STENCIL_CLEAR |
19996 | #define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 |
19997 | #define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL |
19998 | //DB_DEPTH_CLEAR |
19999 | #define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 |
20000 | #define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL |
20001 | //PA_SC_SCREEN_SCISSOR_TL |
20002 | #define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 |
20003 | #define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 |
20004 | #define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL |
20005 | #define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L |
20006 | //PA_SC_SCREEN_SCISSOR_BR |
20007 | #define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 |
20008 | #define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 |
20009 | #define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL |
20010 | #define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L |
20011 | //DB_DFSM_CONTROL |
20012 | #define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0 |
20013 | #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2 |
20014 | #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3 |
20015 | #define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L |
20016 | #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L |
20017 | #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L |
20018 | //DB_RESERVED_REG_2 |
20019 | #define DB_RESERVED_REG_2__FIELD_1__SHIFT 0x0 |
20020 | #define DB_RESERVED_REG_2__FIELD_2__SHIFT 0x4 |
20021 | #define DB_RESERVED_REG_2__FIELD_3__SHIFT 0x8 |
20022 | #define DB_RESERVED_REG_2__FIELD_4__SHIFT 0xd |
20023 | #define DB_RESERVED_REG_2__FIELD_5__SHIFT 0xf |
20024 | #define DB_RESERVED_REG_2__FIELD_6__SHIFT 0x11 |
20025 | #define DB_RESERVED_REG_2__FIELD_7__SHIFT 0x13 |
20026 | #define DB_RESERVED_REG_2__FIELD_8__SHIFT 0x1c |
20027 | #define DB_RESERVED_REG_2__FIELD_1_MASK 0x0000000FL |
20028 | #define DB_RESERVED_REG_2__FIELD_2_MASK 0x000000F0L |
20029 | #define DB_RESERVED_REG_2__FIELD_3_MASK 0x00001F00L |
20030 | #define DB_RESERVED_REG_2__FIELD_4_MASK 0x00006000L |
20031 | #define DB_RESERVED_REG_2__FIELD_5_MASK 0x00018000L |
20032 | #define DB_RESERVED_REG_2__FIELD_6_MASK 0x00060000L |
20033 | #define DB_RESERVED_REG_2__FIELD_7_MASK 0x00180000L |
20034 | #define DB_RESERVED_REG_2__FIELD_8_MASK 0xF0000000L |
20035 | //DB_Z_INFO |
20036 | #define DB_Z_INFO__FORMAT__SHIFT 0x0 |
20037 | #define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 |
20038 | #define DB_Z_INFO__SW_MODE__SHIFT 0x4 |
20039 | #define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0x9 |
20040 | #define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xb |
20041 | #define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc |
20042 | #define DB_Z_INFO__RESERVED_FIELD_1__SHIFT 0xd |
20043 | #define DB_Z_INFO__MAXMIP__SHIFT 0x10 |
20044 | #define DB_Z_INFO__ITERATE_256__SHIFT 0x14 |
20045 | #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 |
20046 | #define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b |
20047 | #define DB_Z_INFO__READ_SIZE__SHIFT 0x1c |
20048 | #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d |
20049 | #define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f |
20050 | #define DB_Z_INFO__FORMAT_MASK 0x00000003L |
20051 | #define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL |
20052 | #define DB_Z_INFO__SW_MODE_MASK 0x000001F0L |
20053 | #define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00000600L |
20054 | #define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00000800L |
20055 | #define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L |
20056 | #define DB_Z_INFO__RESERVED_FIELD_1_MASK 0x0000E000L |
20057 | #define DB_Z_INFO__MAXMIP_MASK 0x000F0000L |
20058 | #define DB_Z_INFO__ITERATE_256_MASK 0x00100000L |
20059 | #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L |
20060 | #define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L |
20061 | #define DB_Z_INFO__READ_SIZE_MASK 0x10000000L |
20062 | #define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L |
20063 | #define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L |
20064 | //DB_STENCIL_INFO |
20065 | #define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 |
20066 | #define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4 |
20067 | #define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0x9 |
20068 | #define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xb |
20069 | #define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc |
20070 | #define DB_STENCIL_INFO__RESERVED_FIELD_1__SHIFT 0xd |
20071 | #define DB_STENCIL_INFO__ITERATE_256__SHIFT 0x14 |
20072 | #define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b |
20073 | #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d |
20074 | #define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L |
20075 | #define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L |
20076 | #define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00000600L |
20077 | #define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00000800L |
20078 | #define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L |
20079 | #define DB_STENCIL_INFO__RESERVED_FIELD_1_MASK 0x0000E000L |
20080 | #define DB_STENCIL_INFO__ITERATE_256_MASK 0x00100000L |
20081 | #define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L |
20082 | #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L |
20083 | //DB_Z_READ_BASE |
20084 | #define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 |
20085 | #define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL |
20086 | //DB_STENCIL_READ_BASE |
20087 | #define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 |
20088 | #define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL |
20089 | //DB_Z_WRITE_BASE |
20090 | #define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 |
20091 | #define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL |
20092 | //DB_STENCIL_WRITE_BASE |
20093 | #define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 |
20094 | #define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL |
20095 | //DB_RESERVED_REG_1 |
20096 | #define DB_RESERVED_REG_1__FIELD_1__SHIFT 0x0 |
20097 | #define DB_RESERVED_REG_1__FIELD_2__SHIFT 0xb |
20098 | #define DB_RESERVED_REG_1__FIELD_1_MASK 0x000007FFL |
20099 | #define DB_RESERVED_REG_1__FIELD_2_MASK 0x003FF800L |
20100 | //DB_RESERVED_REG_3 |
20101 | #define DB_RESERVED_REG_3__FIELD_1__SHIFT 0x0 |
20102 | #define DB_RESERVED_REG_3__FIELD_1_MASK 0x003FFFFFL |
20103 | //DB_VRS_OVERRIDE_CNTL |
20104 | #define DB_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE__SHIFT 0x0 |
20105 | #define DB_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_X__SHIFT 0x4 |
20106 | #define DB_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_Y__SHIFT 0x6 |
20107 | #define DB_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE_MASK 0x00000007L |
20108 | #define DB_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_X_MASK 0x00000030L |
20109 | #define DB_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_Y_MASK 0x000000C0L |
20110 | //DB_Z_READ_BASE_HI |
20111 | #define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 |
20112 | #define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL |
20113 | //DB_STENCIL_READ_BASE_HI |
20114 | #define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0 |
20115 | #define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL |
20116 | //DB_Z_WRITE_BASE_HI |
20117 | #define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 |
20118 | #define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL |
20119 | //DB_STENCIL_WRITE_BASE_HI |
20120 | #define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 |
20121 | #define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL |
20122 | //DB_HTILE_DATA_BASE_HI |
20123 | #define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0 |
20124 | #define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL |
20125 | //DB_RMI_L2_CACHE_CONTROL |
20126 | #define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY__SHIFT 0x0 |
20127 | #define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY__SHIFT 0x2 |
20128 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT 0x4 |
20129 | #define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT 0x6 |
20130 | #define DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY__SHIFT 0x10 |
20131 | #define DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY__SHIFT 0x12 |
20132 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT 0x14 |
20133 | #define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE__SHIFT 0x18 |
20134 | #define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE__SHIFT 0x19 |
20135 | #define DB_RMI_L2_CACHE_CONTROL__Z_NOALLOC__SHIFT 0x1a |
20136 | #define DB_RMI_L2_CACHE_CONTROL__S_NOALLOC__SHIFT 0x1b |
20137 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_NOALLOC__SHIFT 0x1c |
20138 | #define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_NOALLOC__SHIFT 0x1d |
20139 | #define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY_MASK 0x00000003L |
20140 | #define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY_MASK 0x0000000CL |
20141 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY_MASK 0x00000030L |
20142 | #define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK 0x000000C0L |
20143 | #define DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY_MASK 0x00030000L |
20144 | #define DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY_MASK 0x000C0000L |
20145 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY_MASK 0x00300000L |
20146 | #define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE_MASK 0x01000000L |
20147 | #define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE_MASK 0x02000000L |
20148 | #define DB_RMI_L2_CACHE_CONTROL__Z_NOALLOC_MASK 0x04000000L |
20149 | #define DB_RMI_L2_CACHE_CONTROL__S_NOALLOC_MASK 0x08000000L |
20150 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_NOALLOC_MASK 0x10000000L |
20151 | #define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_NOALLOC_MASK 0x20000000L |
20152 | //TA_BC_BASE_ADDR |
20153 | #define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 |
20154 | #define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL |
20155 | //TA_BC_BASE_ADDR_HI |
20156 | #define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 |
20157 | #define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL |
20158 | //COHER_DEST_BASE_HI_0 |
20159 | #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 |
20160 | #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL |
20161 | //COHER_DEST_BASE_HI_1 |
20162 | #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 |
20163 | #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL |
20164 | //COHER_DEST_BASE_HI_2 |
20165 | #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 |
20166 | #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL |
20167 | //COHER_DEST_BASE_HI_3 |
20168 | #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 |
20169 | #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL |
20170 | //COHER_DEST_BASE_2 |
20171 | #define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 |
20172 | #define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL |
20173 | //COHER_DEST_BASE_3 |
20174 | #define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 |
20175 | #define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL |
20176 | //PA_SC_WINDOW_OFFSET |
20177 | #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 |
20178 | #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 |
20179 | #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL |
20180 | #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L |
20181 | //PA_SC_WINDOW_SCISSOR_TL |
20182 | #define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 |
20183 | #define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 |
20184 | #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20185 | #define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL |
20186 | #define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L |
20187 | #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20188 | //PA_SC_WINDOW_SCISSOR_BR |
20189 | #define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 |
20190 | #define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 |
20191 | #define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL |
20192 | #define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L |
20193 | //PA_SC_CLIPRECT_RULE |
20194 | #define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 |
20195 | #define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL |
20196 | //PA_SC_CLIPRECT_0_TL |
20197 | #define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 |
20198 | #define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 |
20199 | #define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL |
20200 | #define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L |
20201 | //PA_SC_CLIPRECT_0_BR |
20202 | #define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 |
20203 | #define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 |
20204 | #define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL |
20205 | #define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L |
20206 | //PA_SC_CLIPRECT_1_TL |
20207 | #define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 |
20208 | #define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 |
20209 | #define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL |
20210 | #define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L |
20211 | //PA_SC_CLIPRECT_1_BR |
20212 | #define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 |
20213 | #define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 |
20214 | #define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL |
20215 | #define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L |
20216 | //PA_SC_CLIPRECT_2_TL |
20217 | #define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 |
20218 | #define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 |
20219 | #define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL |
20220 | #define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L |
20221 | //PA_SC_CLIPRECT_2_BR |
20222 | #define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 |
20223 | #define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 |
20224 | #define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL |
20225 | #define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L |
20226 | //PA_SC_CLIPRECT_3_TL |
20227 | #define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 |
20228 | #define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 |
20229 | #define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL |
20230 | #define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L |
20231 | //PA_SC_CLIPRECT_3_BR |
20232 | #define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 |
20233 | #define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 |
20234 | #define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL |
20235 | #define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L |
20236 | //PA_SC_EDGERULE |
20237 | #define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 |
20238 | #define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 |
20239 | #define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 |
20240 | #define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc |
20241 | #define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 |
20242 | #define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 |
20243 | #define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c |
20244 | #define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL |
20245 | #define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L |
20246 | #define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L |
20247 | #define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L |
20248 | #define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L |
20249 | #define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L |
20250 | #define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L |
20251 | //PA_SU_HARDWARE_SCREEN_OFFSET |
20252 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 |
20253 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 |
20254 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL |
20255 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L |
20256 | //CB_TARGET_MASK |
20257 | #define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 |
20258 | #define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 |
20259 | #define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 |
20260 | #define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc |
20261 | #define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 |
20262 | #define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 |
20263 | #define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 |
20264 | #define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c |
20265 | #define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL |
20266 | #define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L |
20267 | #define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L |
20268 | #define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L |
20269 | #define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L |
20270 | #define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L |
20271 | #define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L |
20272 | #define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L |
20273 | //CB_SHADER_MASK |
20274 | #define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 |
20275 | #define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 |
20276 | #define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 |
20277 | #define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc |
20278 | #define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 |
20279 | #define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 |
20280 | #define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 |
20281 | #define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c |
20282 | #define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL |
20283 | #define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L |
20284 | #define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L |
20285 | #define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L |
20286 | #define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L |
20287 | #define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L |
20288 | #define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L |
20289 | #define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L |
20290 | //PA_SC_GENERIC_SCISSOR_TL |
20291 | #define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 |
20292 | #define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 |
20293 | #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20294 | #define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL |
20295 | #define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L |
20296 | #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20297 | //PA_SC_GENERIC_SCISSOR_BR |
20298 | #define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 |
20299 | #define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 |
20300 | #define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL |
20301 | #define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L |
20302 | //COHER_DEST_BASE_0 |
20303 | #define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 |
20304 | #define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL |
20305 | //COHER_DEST_BASE_1 |
20306 | #define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 |
20307 | #define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL |
20308 | //PA_SC_VPORT_SCISSOR_0_TL |
20309 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 |
20310 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 |
20311 | #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20312 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL |
20313 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L |
20314 | #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20315 | //PA_SC_VPORT_SCISSOR_0_BR |
20316 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 |
20317 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 |
20318 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL |
20319 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L |
20320 | //PA_SC_VPORT_SCISSOR_1_TL |
20321 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 |
20322 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 |
20323 | #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20324 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL |
20325 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L |
20326 | #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20327 | //PA_SC_VPORT_SCISSOR_1_BR |
20328 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 |
20329 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 |
20330 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL |
20331 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L |
20332 | //PA_SC_VPORT_SCISSOR_2_TL |
20333 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 |
20334 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 |
20335 | #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20336 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL |
20337 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L |
20338 | #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20339 | //PA_SC_VPORT_SCISSOR_2_BR |
20340 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 |
20341 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 |
20342 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL |
20343 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L |
20344 | //PA_SC_VPORT_SCISSOR_3_TL |
20345 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 |
20346 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 |
20347 | #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20348 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL |
20349 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L |
20350 | #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20351 | //PA_SC_VPORT_SCISSOR_3_BR |
20352 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 |
20353 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 |
20354 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL |
20355 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L |
20356 | //PA_SC_VPORT_SCISSOR_4_TL |
20357 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 |
20358 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 |
20359 | #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20360 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL |
20361 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L |
20362 | #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20363 | //PA_SC_VPORT_SCISSOR_4_BR |
20364 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 |
20365 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 |
20366 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL |
20367 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L |
20368 | //PA_SC_VPORT_SCISSOR_5_TL |
20369 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 |
20370 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 |
20371 | #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20372 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL |
20373 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L |
20374 | #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20375 | //PA_SC_VPORT_SCISSOR_5_BR |
20376 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 |
20377 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 |
20378 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL |
20379 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L |
20380 | //PA_SC_VPORT_SCISSOR_6_TL |
20381 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 |
20382 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 |
20383 | #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20384 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL |
20385 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L |
20386 | #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20387 | //PA_SC_VPORT_SCISSOR_6_BR |
20388 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 |
20389 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 |
20390 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL |
20391 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L |
20392 | //PA_SC_VPORT_SCISSOR_7_TL |
20393 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 |
20394 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 |
20395 | #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20396 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL |
20397 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L |
20398 | #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20399 | //PA_SC_VPORT_SCISSOR_7_BR |
20400 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 |
20401 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 |
20402 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL |
20403 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L |
20404 | //PA_SC_VPORT_SCISSOR_8_TL |
20405 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 |
20406 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 |
20407 | #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20408 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL |
20409 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L |
20410 | #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20411 | //PA_SC_VPORT_SCISSOR_8_BR |
20412 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 |
20413 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 |
20414 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL |
20415 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L |
20416 | //PA_SC_VPORT_SCISSOR_9_TL |
20417 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 |
20418 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 |
20419 | #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20420 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL |
20421 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L |
20422 | #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20423 | //PA_SC_VPORT_SCISSOR_9_BR |
20424 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 |
20425 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 |
20426 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL |
20427 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L |
20428 | //PA_SC_VPORT_SCISSOR_10_TL |
20429 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 |
20430 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 |
20431 | #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20432 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL |
20433 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L |
20434 | #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20435 | //PA_SC_VPORT_SCISSOR_10_BR |
20436 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 |
20437 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 |
20438 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL |
20439 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L |
20440 | //PA_SC_VPORT_SCISSOR_11_TL |
20441 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 |
20442 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 |
20443 | #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20444 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL |
20445 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L |
20446 | #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20447 | //PA_SC_VPORT_SCISSOR_11_BR |
20448 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 |
20449 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 |
20450 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL |
20451 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L |
20452 | //PA_SC_VPORT_SCISSOR_12_TL |
20453 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 |
20454 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 |
20455 | #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20456 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL |
20457 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L |
20458 | #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20459 | //PA_SC_VPORT_SCISSOR_12_BR |
20460 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 |
20461 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 |
20462 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL |
20463 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L |
20464 | //PA_SC_VPORT_SCISSOR_13_TL |
20465 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 |
20466 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 |
20467 | #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20468 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL |
20469 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L |
20470 | #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20471 | //PA_SC_VPORT_SCISSOR_13_BR |
20472 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 |
20473 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 |
20474 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL |
20475 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L |
20476 | //PA_SC_VPORT_SCISSOR_14_TL |
20477 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 |
20478 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 |
20479 | #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20480 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL |
20481 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L |
20482 | #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20483 | //PA_SC_VPORT_SCISSOR_14_BR |
20484 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 |
20485 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 |
20486 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL |
20487 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L |
20488 | //PA_SC_VPORT_SCISSOR_15_TL |
20489 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 |
20490 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 |
20491 | #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
20492 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL |
20493 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L |
20494 | #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
20495 | //PA_SC_VPORT_SCISSOR_15_BR |
20496 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 |
20497 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 |
20498 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL |
20499 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L |
20500 | //PA_SC_VPORT_ZMIN_0 |
20501 | #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 |
20502 | #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20503 | //PA_SC_VPORT_ZMAX_0 |
20504 | #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 |
20505 | #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20506 | //PA_SC_VPORT_ZMIN_1 |
20507 | #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 |
20508 | #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20509 | //PA_SC_VPORT_ZMAX_1 |
20510 | #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 |
20511 | #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20512 | //PA_SC_VPORT_ZMIN_2 |
20513 | #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 |
20514 | #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20515 | //PA_SC_VPORT_ZMAX_2 |
20516 | #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 |
20517 | #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20518 | //PA_SC_VPORT_ZMIN_3 |
20519 | #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 |
20520 | #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20521 | //PA_SC_VPORT_ZMAX_3 |
20522 | #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 |
20523 | #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20524 | //PA_SC_VPORT_ZMIN_4 |
20525 | #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 |
20526 | #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20527 | //PA_SC_VPORT_ZMAX_4 |
20528 | #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 |
20529 | #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20530 | //PA_SC_VPORT_ZMIN_5 |
20531 | #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 |
20532 | #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20533 | //PA_SC_VPORT_ZMAX_5 |
20534 | #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 |
20535 | #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20536 | //PA_SC_VPORT_ZMIN_6 |
20537 | #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 |
20538 | #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20539 | //PA_SC_VPORT_ZMAX_6 |
20540 | #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 |
20541 | #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20542 | //PA_SC_VPORT_ZMIN_7 |
20543 | #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 |
20544 | #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20545 | //PA_SC_VPORT_ZMAX_7 |
20546 | #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 |
20547 | #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20548 | //PA_SC_VPORT_ZMIN_8 |
20549 | #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 |
20550 | #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20551 | //PA_SC_VPORT_ZMAX_8 |
20552 | #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 |
20553 | #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20554 | //PA_SC_VPORT_ZMIN_9 |
20555 | #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 |
20556 | #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20557 | //PA_SC_VPORT_ZMAX_9 |
20558 | #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 |
20559 | #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20560 | //PA_SC_VPORT_ZMIN_10 |
20561 | #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 |
20562 | #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20563 | //PA_SC_VPORT_ZMAX_10 |
20564 | #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 |
20565 | #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20566 | //PA_SC_VPORT_ZMIN_11 |
20567 | #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 |
20568 | #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20569 | //PA_SC_VPORT_ZMAX_11 |
20570 | #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 |
20571 | #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20572 | //PA_SC_VPORT_ZMIN_12 |
20573 | #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 |
20574 | #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20575 | //PA_SC_VPORT_ZMAX_12 |
20576 | #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 |
20577 | #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20578 | //PA_SC_VPORT_ZMIN_13 |
20579 | #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 |
20580 | #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20581 | //PA_SC_VPORT_ZMAX_13 |
20582 | #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 |
20583 | #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20584 | //PA_SC_VPORT_ZMIN_14 |
20585 | #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 |
20586 | #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20587 | //PA_SC_VPORT_ZMAX_14 |
20588 | #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 |
20589 | #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20590 | //PA_SC_VPORT_ZMIN_15 |
20591 | #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 |
20592 | #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL |
20593 | //PA_SC_VPORT_ZMAX_15 |
20594 | #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 |
20595 | #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL |
20596 | //PA_SC_RASTER_CONFIG |
20597 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 |
20598 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 |
20599 | #define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 |
20600 | #define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 |
20601 | #define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 |
20602 | #define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 |
20603 | #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa |
20604 | #define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc |
20605 | #define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe |
20606 | #define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 |
20607 | #define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 |
20608 | #define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 |
20609 | #define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 |
20610 | #define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a |
20611 | #define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c |
20612 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L |
20613 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL |
20614 | #define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L |
20615 | #define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L |
20616 | #define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L |
20617 | #define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L |
20618 | #define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L |
20619 | #define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L |
20620 | #define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L |
20621 | #define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L |
20622 | #define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L |
20623 | #define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L |
20624 | #define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L |
20625 | #define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x0C000000L |
20626 | #define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000L |
20627 | //PA_SC_RASTER_CONFIG_1 |
20628 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 |
20629 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 |
20630 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4 |
20631 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L |
20632 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000000CL |
20633 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x00000030L |
20634 | //PA_SC_SCREEN_EXTENT_CONTROL |
20635 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 |
20636 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 |
20637 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L |
20638 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL |
20639 | //PA_SC_TILE_STEERING_OVERRIDE |
20640 | #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 |
20641 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1 |
20642 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5 |
20643 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT 0xc |
20644 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT 0x10 |
20645 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT 0x14 |
20646 | #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L |
20647 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L |
20648 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L |
20649 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK 0x00003000L |
20650 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK 0x00030000L |
20651 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK 0x00300000L |
20652 | //CP_PERFMON_CNTX_CNTL |
20653 | #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f |
20654 | #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L |
20655 | //CP_PIPEID |
20656 | #define CP_PIPEID__PIPE_ID__SHIFT 0x0 |
20657 | #define CP_PIPEID__PIPE_ID_MASK 0x00000003L |
20658 | //CP_RINGID |
20659 | #define CP_RINGID__RINGID__SHIFT 0x0 |
20660 | #define CP_RINGID__RINGID_MASK 0x00000003L |
20661 | //CP_VMID |
20662 | #define CP_VMID__VMID__SHIFT 0x0 |
20663 | #define CP_VMID__VMID_MASK 0x0000000FL |
20664 | //CONTEXT_RESERVED_REG0 |
20665 | #define CONTEXT_RESERVED_REG0__DATA__SHIFT 0x0 |
20666 | #define CONTEXT_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL |
20667 | //CONTEXT_RESERVED_REG1 |
20668 | #define CONTEXT_RESERVED_REG1__DATA__SHIFT 0x0 |
20669 | #define CONTEXT_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL |
20670 | //VGT_MAX_VTX_INDX |
20671 | #define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 |
20672 | #define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL |
20673 | //VGT_MIN_VTX_INDX |
20674 | #define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 |
20675 | #define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL |
20676 | //VGT_INDX_OFFSET |
20677 | #define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 |
20678 | #define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL |
20679 | //VGT_MULTI_PRIM_IB_RESET_INDX |
20680 | #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 |
20681 | #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL |
20682 | //CB_RMI_GL2_CACHE_CONTROL |
20683 | #define CB_RMI_GL2_CACHE_CONTROL__CMASK_WR_POLICY__SHIFT 0x0 |
20684 | #define CB_RMI_GL2_CACHE_CONTROL__FMASK_WR_POLICY__SHIFT 0x2 |
20685 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT 0x4 |
20686 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT 0x6 |
20687 | #define CB_RMI_GL2_CACHE_CONTROL__CMASK_RD_POLICY__SHIFT 0x10 |
20688 | #define CB_RMI_GL2_CACHE_CONTROL__FMASK_RD_POLICY__SHIFT 0x12 |
20689 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT 0x14 |
20690 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT 0x16 |
20691 | #define CB_RMI_GL2_CACHE_CONTROL__CMASK_L3_BYPASS__SHIFT 0x18 |
20692 | #define CB_RMI_GL2_CACHE_CONTROL__FMASK_L3_BYPASS__SHIFT 0x19 |
20693 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_L3_BYPASS__SHIFT 0x1a |
20694 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_L3_BYPASS__SHIFT 0x1b |
20695 | #define CB_RMI_GL2_CACHE_CONTROL__FMASK_BIG_PAGE__SHIFT 0x1e |
20696 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE__SHIFT 0x1f |
20697 | #define CB_RMI_GL2_CACHE_CONTROL__CMASK_WR_POLICY_MASK 0x00000003L |
20698 | #define CB_RMI_GL2_CACHE_CONTROL__FMASK_WR_POLICY_MASK 0x0000000CL |
20699 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK 0x00000030L |
20700 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK 0x000000C0L |
20701 | #define CB_RMI_GL2_CACHE_CONTROL__CMASK_RD_POLICY_MASK 0x00030000L |
20702 | #define CB_RMI_GL2_CACHE_CONTROL__FMASK_RD_POLICY_MASK 0x000C0000L |
20703 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK 0x00300000L |
20704 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK 0x00C00000L |
20705 | #define CB_RMI_GL2_CACHE_CONTROL__CMASK_L3_BYPASS_MASK 0x01000000L |
20706 | #define CB_RMI_GL2_CACHE_CONTROL__FMASK_L3_BYPASS_MASK 0x02000000L |
20707 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_L3_BYPASS_MASK 0x04000000L |
20708 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_L3_BYPASS_MASK 0x08000000L |
20709 | #define CB_RMI_GL2_CACHE_CONTROL__FMASK_BIG_PAGE_MASK 0x40000000L |
20710 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE_MASK 0x80000000L |
20711 | //CB_BLEND_RED |
20712 | #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 |
20713 | #define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL |
20714 | //CB_BLEND_GREEN |
20715 | #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 |
20716 | #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL |
20717 | //CB_BLEND_BLUE |
20718 | #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 |
20719 | #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL |
20720 | //CB_BLEND_ALPHA |
20721 | #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 |
20722 | #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL |
20723 | //CB_DCC_CONTROL |
20724 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
20725 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2 |
20726 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT 0x8 |
20727 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT 0x9 |
20728 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0xa |
20729 | #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT 0xc |
20730 | #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT 0xd |
20731 | #define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT 0xe |
20732 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
20733 | #define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL |
20734 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK 0x00000100L |
20735 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK 0x00000200L |
20736 | #define CB_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00000400L |
20737 | #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK 0x00001000L |
20738 | #define CB_DCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK 0x00002000L |
20739 | #define CB_DCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK 0x00004000L |
20740 | //CB_COVERAGE_OUT_CONTROL |
20741 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE__SHIFT 0x0 |
20742 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT__SHIFT 0x1 |
20743 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL__SHIFT 0x4 |
20744 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES__SHIFT 0x8 |
20745 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE_MASK 0x00000001L |
20746 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT_MASK 0x0000000EL |
20747 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL_MASK 0x00000030L |
20748 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES_MASK 0x00000F00L |
20749 | //DB_STENCIL_CONTROL |
20750 | #define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 |
20751 | #define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 |
20752 | #define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 |
20753 | #define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc |
20754 | #define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 |
20755 | #define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 |
20756 | #define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL |
20757 | #define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L |
20758 | #define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L |
20759 | #define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L |
20760 | #define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L |
20761 | #define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L |
20762 | //DB_STENCILREFMASK |
20763 | #define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 |
20764 | #define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 |
20765 | #define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 |
20766 | #define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 |
20767 | #define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL |
20768 | #define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L |
20769 | #define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L |
20770 | #define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L |
20771 | //DB_STENCILREFMASK_BF |
20772 | #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 |
20773 | #define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 |
20774 | #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 |
20775 | #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 |
20776 | #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL |
20777 | #define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L |
20778 | #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L |
20779 | #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L |
20780 | //PA_CL_VPORT_XSCALE |
20781 | #define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 |
20782 | #define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL |
20783 | //PA_CL_VPORT_XOFFSET |
20784 | #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 |
20785 | #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
20786 | //PA_CL_VPORT_YSCALE |
20787 | #define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 |
20788 | #define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL |
20789 | //PA_CL_VPORT_YOFFSET |
20790 | #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 |
20791 | #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
20792 | //PA_CL_VPORT_ZSCALE |
20793 | #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 |
20794 | #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
20795 | //PA_CL_VPORT_ZOFFSET |
20796 | #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 |
20797 | #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
20798 | //PA_CL_VPORT_XSCALE_1 |
20799 | #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 |
20800 | #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL |
20801 | //PA_CL_VPORT_XOFFSET_1 |
20802 | #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 |
20803 | #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
20804 | //PA_CL_VPORT_YSCALE_1 |
20805 | #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 |
20806 | #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL |
20807 | //PA_CL_VPORT_YOFFSET_1 |
20808 | #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 |
20809 | #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
20810 | //PA_CL_VPORT_ZSCALE_1 |
20811 | #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 |
20812 | #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
20813 | //PA_CL_VPORT_ZOFFSET_1 |
20814 | #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 |
20815 | #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
20816 | //PA_CL_VPORT_XSCALE_2 |
20817 | #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 |
20818 | #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL |
20819 | //PA_CL_VPORT_XOFFSET_2 |
20820 | #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 |
20821 | #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
20822 | //PA_CL_VPORT_YSCALE_2 |
20823 | #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 |
20824 | #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL |
20825 | //PA_CL_VPORT_YOFFSET_2 |
20826 | #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 |
20827 | #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
20828 | //PA_CL_VPORT_ZSCALE_2 |
20829 | #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 |
20830 | #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
20831 | //PA_CL_VPORT_ZOFFSET_2 |
20832 | #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 |
20833 | #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
20834 | //PA_CL_VPORT_XSCALE_3 |
20835 | #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 |
20836 | #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL |
20837 | //PA_CL_VPORT_XOFFSET_3 |
20838 | #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 |
20839 | #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
20840 | //PA_CL_VPORT_YSCALE_3 |
20841 | #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 |
20842 | #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL |
20843 | //PA_CL_VPORT_YOFFSET_3 |
20844 | #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 |
20845 | #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
20846 | //PA_CL_VPORT_ZSCALE_3 |
20847 | #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 |
20848 | #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
20849 | //PA_CL_VPORT_ZOFFSET_3 |
20850 | #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 |
20851 | #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
20852 | //PA_CL_VPORT_XSCALE_4 |
20853 | #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 |
20854 | #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL |
20855 | //PA_CL_VPORT_XOFFSET_4 |
20856 | #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 |
20857 | #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
20858 | //PA_CL_VPORT_YSCALE_4 |
20859 | #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 |
20860 | #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL |
20861 | //PA_CL_VPORT_YOFFSET_4 |
20862 | #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 |
20863 | #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
20864 | //PA_CL_VPORT_ZSCALE_4 |
20865 | #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 |
20866 | #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
20867 | //PA_CL_VPORT_ZOFFSET_4 |
20868 | #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 |
20869 | #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
20870 | //PA_CL_VPORT_XSCALE_5 |
20871 | #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 |
20872 | #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL |
20873 | //PA_CL_VPORT_XOFFSET_5 |
20874 | #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 |
20875 | #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
20876 | //PA_CL_VPORT_YSCALE_5 |
20877 | #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 |
20878 | #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL |
20879 | //PA_CL_VPORT_YOFFSET_5 |
20880 | #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 |
20881 | #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
20882 | //PA_CL_VPORT_ZSCALE_5 |
20883 | #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 |
20884 | #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
20885 | //PA_CL_VPORT_ZOFFSET_5 |
20886 | #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 |
20887 | #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
20888 | //PA_CL_VPORT_XSCALE_6 |
20889 | #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 |
20890 | #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL |
20891 | //PA_CL_VPORT_XOFFSET_6 |
20892 | #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 |
20893 | #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
20894 | //PA_CL_VPORT_YSCALE_6 |
20895 | #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 |
20896 | #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL |
20897 | //PA_CL_VPORT_YOFFSET_6 |
20898 | #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 |
20899 | #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
20900 | //PA_CL_VPORT_ZSCALE_6 |
20901 | #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 |
20902 | #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
20903 | //PA_CL_VPORT_ZOFFSET_6 |
20904 | #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 |
20905 | #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
20906 | //PA_CL_VPORT_XSCALE_7 |
20907 | #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 |
20908 | #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL |
20909 | //PA_CL_VPORT_XOFFSET_7 |
20910 | #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 |
20911 | #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
20912 | //PA_CL_VPORT_YSCALE_7 |
20913 | #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 |
20914 | #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL |
20915 | //PA_CL_VPORT_YOFFSET_7 |
20916 | #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 |
20917 | #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
20918 | //PA_CL_VPORT_ZSCALE_7 |
20919 | #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 |
20920 | #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
20921 | //PA_CL_VPORT_ZOFFSET_7 |
20922 | #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 |
20923 | #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
20924 | //PA_CL_VPORT_XSCALE_8 |
20925 | #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 |
20926 | #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL |
20927 | //PA_CL_VPORT_XOFFSET_8 |
20928 | #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 |
20929 | #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
20930 | //PA_CL_VPORT_YSCALE_8 |
20931 | #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 |
20932 | #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL |
20933 | //PA_CL_VPORT_YOFFSET_8 |
20934 | #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 |
20935 | #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
20936 | //PA_CL_VPORT_ZSCALE_8 |
20937 | #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 |
20938 | #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
20939 | //PA_CL_VPORT_ZOFFSET_8 |
20940 | #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 |
20941 | #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
20942 | //PA_CL_VPORT_XSCALE_9 |
20943 | #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 |
20944 | #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL |
20945 | //PA_CL_VPORT_XOFFSET_9 |
20946 | #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 |
20947 | #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
20948 | //PA_CL_VPORT_YSCALE_9 |
20949 | #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 |
20950 | #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL |
20951 | //PA_CL_VPORT_YOFFSET_9 |
20952 | #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 |
20953 | #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
20954 | //PA_CL_VPORT_ZSCALE_9 |
20955 | #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 |
20956 | #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
20957 | //PA_CL_VPORT_ZOFFSET_9 |
20958 | #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 |
20959 | #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
20960 | //PA_CL_VPORT_XSCALE_10 |
20961 | #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 |
20962 | #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL |
20963 | //PA_CL_VPORT_XOFFSET_10 |
20964 | #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 |
20965 | #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
20966 | //PA_CL_VPORT_YSCALE_10 |
20967 | #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 |
20968 | #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL |
20969 | //PA_CL_VPORT_YOFFSET_10 |
20970 | #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 |
20971 | #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
20972 | //PA_CL_VPORT_ZSCALE_10 |
20973 | #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 |
20974 | #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
20975 | //PA_CL_VPORT_ZOFFSET_10 |
20976 | #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 |
20977 | #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
20978 | //PA_CL_VPORT_XSCALE_11 |
20979 | #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 |
20980 | #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL |
20981 | //PA_CL_VPORT_XOFFSET_11 |
20982 | #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 |
20983 | #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
20984 | //PA_CL_VPORT_YSCALE_11 |
20985 | #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 |
20986 | #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL |
20987 | //PA_CL_VPORT_YOFFSET_11 |
20988 | #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 |
20989 | #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
20990 | //PA_CL_VPORT_ZSCALE_11 |
20991 | #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 |
20992 | #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
20993 | //PA_CL_VPORT_ZOFFSET_11 |
20994 | #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 |
20995 | #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
20996 | //PA_CL_VPORT_XSCALE_12 |
20997 | #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 |
20998 | #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL |
20999 | //PA_CL_VPORT_XOFFSET_12 |
21000 | #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 |
21001 | #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
21002 | //PA_CL_VPORT_YSCALE_12 |
21003 | #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 |
21004 | #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL |
21005 | //PA_CL_VPORT_YOFFSET_12 |
21006 | #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 |
21007 | #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
21008 | //PA_CL_VPORT_ZSCALE_12 |
21009 | #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 |
21010 | #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
21011 | //PA_CL_VPORT_ZOFFSET_12 |
21012 | #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 |
21013 | #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
21014 | //PA_CL_VPORT_XSCALE_13 |
21015 | #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 |
21016 | #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL |
21017 | //PA_CL_VPORT_XOFFSET_13 |
21018 | #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 |
21019 | #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
21020 | //PA_CL_VPORT_YSCALE_13 |
21021 | #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 |
21022 | #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL |
21023 | //PA_CL_VPORT_YOFFSET_13 |
21024 | #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 |
21025 | #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
21026 | //PA_CL_VPORT_ZSCALE_13 |
21027 | #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 |
21028 | #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
21029 | //PA_CL_VPORT_ZOFFSET_13 |
21030 | #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 |
21031 | #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
21032 | //PA_CL_VPORT_XSCALE_14 |
21033 | #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 |
21034 | #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL |
21035 | //PA_CL_VPORT_XOFFSET_14 |
21036 | #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 |
21037 | #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
21038 | //PA_CL_VPORT_YSCALE_14 |
21039 | #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 |
21040 | #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL |
21041 | //PA_CL_VPORT_YOFFSET_14 |
21042 | #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 |
21043 | #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
21044 | //PA_CL_VPORT_ZSCALE_14 |
21045 | #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 |
21046 | #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
21047 | //PA_CL_VPORT_ZOFFSET_14 |
21048 | #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 |
21049 | #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
21050 | //PA_CL_VPORT_XSCALE_15 |
21051 | #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 |
21052 | #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL |
21053 | //PA_CL_VPORT_XOFFSET_15 |
21054 | #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 |
21055 | #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
21056 | //PA_CL_VPORT_YSCALE_15 |
21057 | #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 |
21058 | #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL |
21059 | //PA_CL_VPORT_YOFFSET_15 |
21060 | #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 |
21061 | #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
21062 | //PA_CL_VPORT_ZSCALE_15 |
21063 | #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 |
21064 | #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
21065 | //PA_CL_VPORT_ZOFFSET_15 |
21066 | #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 |
21067 | #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
21068 | //PA_CL_UCP_0_X |
21069 | #define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 |
21070 | #define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
21071 | //PA_CL_UCP_0_Y |
21072 | #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 |
21073 | #define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
21074 | //PA_CL_UCP_0_Z |
21075 | #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 |
21076 | #define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
21077 | //PA_CL_UCP_0_W |
21078 | #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 |
21079 | #define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
21080 | //PA_CL_UCP_1_X |
21081 | #define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 |
21082 | #define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
21083 | //PA_CL_UCP_1_Y |
21084 | #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 |
21085 | #define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
21086 | //PA_CL_UCP_1_Z |
21087 | #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 |
21088 | #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
21089 | //PA_CL_UCP_1_W |
21090 | #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 |
21091 | #define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
21092 | //PA_CL_UCP_2_X |
21093 | #define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 |
21094 | #define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
21095 | //PA_CL_UCP_2_Y |
21096 | #define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 |
21097 | #define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
21098 | //PA_CL_UCP_2_Z |
21099 | #define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 |
21100 | #define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
21101 | //PA_CL_UCP_2_W |
21102 | #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 |
21103 | #define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
21104 | //PA_CL_UCP_3_X |
21105 | #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 |
21106 | #define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
21107 | //PA_CL_UCP_3_Y |
21108 | #define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 |
21109 | #define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
21110 | //PA_CL_UCP_3_Z |
21111 | #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 |
21112 | #define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
21113 | //PA_CL_UCP_3_W |
21114 | #define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 |
21115 | #define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
21116 | //PA_CL_UCP_4_X |
21117 | #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 |
21118 | #define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
21119 | //PA_CL_UCP_4_Y |
21120 | #define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 |
21121 | #define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
21122 | //PA_CL_UCP_4_Z |
21123 | #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 |
21124 | #define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
21125 | //PA_CL_UCP_4_W |
21126 | #define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 |
21127 | #define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
21128 | //PA_CL_UCP_5_X |
21129 | #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 |
21130 | #define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
21131 | //PA_CL_UCP_5_Y |
21132 | #define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 |
21133 | #define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
21134 | //PA_CL_UCP_5_Z |
21135 | #define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 |
21136 | #define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
21137 | //PA_CL_UCP_5_W |
21138 | #define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 |
21139 | #define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
21140 | //PA_CL_PROG_NEAR_CLIP_Z |
21141 | #define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT 0x0 |
21142 | #define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
21143 | //SPI_PS_INPUT_CNTL_0 |
21144 | #define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 |
21145 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 |
21146 | #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa |
21147 | #define SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR__SHIFT 0xb |
21148 | #define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd |
21149 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 |
21150 | #define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 |
21151 | #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 |
21152 | #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21153 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21154 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21155 | #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 |
21156 | #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 |
21157 | #define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL |
21158 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L |
21159 | #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L |
21160 | #define SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR_MASK 0x00000800L |
21161 | #define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L |
21162 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L |
21163 | #define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L |
21164 | #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L |
21165 | #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21166 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21167 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21168 | #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L |
21169 | #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L |
21170 | //SPI_PS_INPUT_CNTL_1 |
21171 | #define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 |
21172 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 |
21173 | #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa |
21174 | #define SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR__SHIFT 0xb |
21175 | #define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd |
21176 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 |
21177 | #define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 |
21178 | #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 |
21179 | #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21180 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21181 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21182 | #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 |
21183 | #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 |
21184 | #define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL |
21185 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L |
21186 | #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L |
21187 | #define SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR_MASK 0x00000800L |
21188 | #define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L |
21189 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L |
21190 | #define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L |
21191 | #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L |
21192 | #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21193 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21194 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21195 | #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L |
21196 | #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L |
21197 | //SPI_PS_INPUT_CNTL_2 |
21198 | #define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 |
21199 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 |
21200 | #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa |
21201 | #define SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR__SHIFT 0xb |
21202 | #define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd |
21203 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 |
21204 | #define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 |
21205 | #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 |
21206 | #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21207 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21208 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21209 | #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 |
21210 | #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 |
21211 | #define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL |
21212 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L |
21213 | #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L |
21214 | #define SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR_MASK 0x00000800L |
21215 | #define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L |
21216 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L |
21217 | #define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L |
21218 | #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L |
21219 | #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21220 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21221 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21222 | #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L |
21223 | #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L |
21224 | //SPI_PS_INPUT_CNTL_3 |
21225 | #define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 |
21226 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 |
21227 | #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa |
21228 | #define SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR__SHIFT 0xb |
21229 | #define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd |
21230 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 |
21231 | #define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 |
21232 | #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 |
21233 | #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21234 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21235 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21236 | #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 |
21237 | #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 |
21238 | #define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL |
21239 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L |
21240 | #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L |
21241 | #define SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR_MASK 0x00000800L |
21242 | #define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L |
21243 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L |
21244 | #define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L |
21245 | #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L |
21246 | #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21247 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21248 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21249 | #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L |
21250 | #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L |
21251 | //SPI_PS_INPUT_CNTL_4 |
21252 | #define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 |
21253 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 |
21254 | #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa |
21255 | #define SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR__SHIFT 0xb |
21256 | #define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd |
21257 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 |
21258 | #define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 |
21259 | #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 |
21260 | #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21261 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21262 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21263 | #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 |
21264 | #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 |
21265 | #define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL |
21266 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L |
21267 | #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L |
21268 | #define SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR_MASK 0x00000800L |
21269 | #define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L |
21270 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L |
21271 | #define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L |
21272 | #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L |
21273 | #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21274 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21275 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21276 | #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L |
21277 | #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L |
21278 | //SPI_PS_INPUT_CNTL_5 |
21279 | #define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 |
21280 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 |
21281 | #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa |
21282 | #define SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR__SHIFT 0xb |
21283 | #define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd |
21284 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 |
21285 | #define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 |
21286 | #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 |
21287 | #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21288 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21289 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21290 | #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 |
21291 | #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 |
21292 | #define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL |
21293 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L |
21294 | #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L |
21295 | #define SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR_MASK 0x00000800L |
21296 | #define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L |
21297 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L |
21298 | #define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L |
21299 | #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L |
21300 | #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21301 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21302 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21303 | #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L |
21304 | #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L |
21305 | //SPI_PS_INPUT_CNTL_6 |
21306 | #define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 |
21307 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 |
21308 | #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa |
21309 | #define SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR__SHIFT 0xb |
21310 | #define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd |
21311 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 |
21312 | #define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 |
21313 | #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 |
21314 | #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21315 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21316 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21317 | #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 |
21318 | #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 |
21319 | #define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL |
21320 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L |
21321 | #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L |
21322 | #define SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR_MASK 0x00000800L |
21323 | #define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L |
21324 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L |
21325 | #define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L |
21326 | #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L |
21327 | #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21328 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21329 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21330 | #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L |
21331 | #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L |
21332 | //SPI_PS_INPUT_CNTL_7 |
21333 | #define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 |
21334 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 |
21335 | #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa |
21336 | #define SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR__SHIFT 0xb |
21337 | #define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd |
21338 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 |
21339 | #define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 |
21340 | #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 |
21341 | #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21342 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21343 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21344 | #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 |
21345 | #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 |
21346 | #define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL |
21347 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L |
21348 | #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L |
21349 | #define SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR_MASK 0x00000800L |
21350 | #define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L |
21351 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L |
21352 | #define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L |
21353 | #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L |
21354 | #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21355 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21356 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21357 | #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L |
21358 | #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L |
21359 | //SPI_PS_INPUT_CNTL_8 |
21360 | #define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 |
21361 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 |
21362 | #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa |
21363 | #define SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR__SHIFT 0xb |
21364 | #define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd |
21365 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 |
21366 | #define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 |
21367 | #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 |
21368 | #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21369 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21370 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21371 | #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 |
21372 | #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 |
21373 | #define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL |
21374 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L |
21375 | #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L |
21376 | #define SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR_MASK 0x00000800L |
21377 | #define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L |
21378 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L |
21379 | #define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L |
21380 | #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L |
21381 | #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21382 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21383 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21384 | #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L |
21385 | #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L |
21386 | //SPI_PS_INPUT_CNTL_9 |
21387 | #define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 |
21388 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 |
21389 | #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa |
21390 | #define SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR__SHIFT 0xb |
21391 | #define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd |
21392 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 |
21393 | #define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 |
21394 | #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 |
21395 | #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21396 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21397 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21398 | #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 |
21399 | #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 |
21400 | #define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL |
21401 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L |
21402 | #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L |
21403 | #define SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR_MASK 0x00000800L |
21404 | #define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L |
21405 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L |
21406 | #define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L |
21407 | #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L |
21408 | #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21409 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21410 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21411 | #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L |
21412 | #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L |
21413 | //SPI_PS_INPUT_CNTL_10 |
21414 | #define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 |
21415 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 |
21416 | #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa |
21417 | #define SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR__SHIFT 0xb |
21418 | #define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd |
21419 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 |
21420 | #define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 |
21421 | #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 |
21422 | #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21423 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21424 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21425 | #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 |
21426 | #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 |
21427 | #define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL |
21428 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L |
21429 | #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L |
21430 | #define SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR_MASK 0x00000800L |
21431 | #define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L |
21432 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L |
21433 | #define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L |
21434 | #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L |
21435 | #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21436 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21437 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21438 | #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L |
21439 | #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L |
21440 | //SPI_PS_INPUT_CNTL_11 |
21441 | #define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 |
21442 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 |
21443 | #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa |
21444 | #define SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR__SHIFT 0xb |
21445 | #define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd |
21446 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 |
21447 | #define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 |
21448 | #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 |
21449 | #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21450 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21451 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21452 | #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 |
21453 | #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 |
21454 | #define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL |
21455 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L |
21456 | #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L |
21457 | #define SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR_MASK 0x00000800L |
21458 | #define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L |
21459 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L |
21460 | #define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L |
21461 | #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L |
21462 | #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21463 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21464 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21465 | #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L |
21466 | #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L |
21467 | //SPI_PS_INPUT_CNTL_12 |
21468 | #define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 |
21469 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 |
21470 | #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa |
21471 | #define SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR__SHIFT 0xb |
21472 | #define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd |
21473 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 |
21474 | #define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 |
21475 | #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 |
21476 | #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21477 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21478 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21479 | #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 |
21480 | #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 |
21481 | #define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL |
21482 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L |
21483 | #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L |
21484 | #define SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR_MASK 0x00000800L |
21485 | #define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L |
21486 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L |
21487 | #define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L |
21488 | #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L |
21489 | #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21490 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21491 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21492 | #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L |
21493 | #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L |
21494 | //SPI_PS_INPUT_CNTL_13 |
21495 | #define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 |
21496 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 |
21497 | #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa |
21498 | #define SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR__SHIFT 0xb |
21499 | #define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd |
21500 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 |
21501 | #define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 |
21502 | #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 |
21503 | #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21504 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21505 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21506 | #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 |
21507 | #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 |
21508 | #define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL |
21509 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L |
21510 | #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L |
21511 | #define SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR_MASK 0x00000800L |
21512 | #define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L |
21513 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L |
21514 | #define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L |
21515 | #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L |
21516 | #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21517 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21518 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21519 | #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L |
21520 | #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L |
21521 | //SPI_PS_INPUT_CNTL_14 |
21522 | #define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 |
21523 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 |
21524 | #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa |
21525 | #define SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR__SHIFT 0xb |
21526 | #define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd |
21527 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 |
21528 | #define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 |
21529 | #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 |
21530 | #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21531 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21532 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21533 | #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 |
21534 | #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 |
21535 | #define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL |
21536 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L |
21537 | #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L |
21538 | #define SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR_MASK 0x00000800L |
21539 | #define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L |
21540 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L |
21541 | #define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L |
21542 | #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L |
21543 | #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21544 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21545 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21546 | #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L |
21547 | #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L |
21548 | //SPI_PS_INPUT_CNTL_15 |
21549 | #define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 |
21550 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 |
21551 | #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa |
21552 | #define SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR__SHIFT 0xb |
21553 | #define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd |
21554 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 |
21555 | #define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 |
21556 | #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 |
21557 | #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21558 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21559 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21560 | #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 |
21561 | #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 |
21562 | #define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL |
21563 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L |
21564 | #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L |
21565 | #define SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR_MASK 0x00000800L |
21566 | #define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L |
21567 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L |
21568 | #define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L |
21569 | #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L |
21570 | #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21571 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21572 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21573 | #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L |
21574 | #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L |
21575 | //SPI_PS_INPUT_CNTL_16 |
21576 | #define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 |
21577 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 |
21578 | #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa |
21579 | #define SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR__SHIFT 0xb |
21580 | #define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd |
21581 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 |
21582 | #define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 |
21583 | #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 |
21584 | #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21585 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21586 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21587 | #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 |
21588 | #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 |
21589 | #define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL |
21590 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L |
21591 | #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L |
21592 | #define SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR_MASK 0x00000800L |
21593 | #define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L |
21594 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L |
21595 | #define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L |
21596 | #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L |
21597 | #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21598 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21599 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21600 | #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L |
21601 | #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L |
21602 | //SPI_PS_INPUT_CNTL_17 |
21603 | #define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 |
21604 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 |
21605 | #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa |
21606 | #define SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR__SHIFT 0xb |
21607 | #define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd |
21608 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 |
21609 | #define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 |
21610 | #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 |
21611 | #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21612 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21613 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21614 | #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 |
21615 | #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 |
21616 | #define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL |
21617 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L |
21618 | #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L |
21619 | #define SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR_MASK 0x00000800L |
21620 | #define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L |
21621 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L |
21622 | #define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L |
21623 | #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L |
21624 | #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21625 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21626 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21627 | #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L |
21628 | #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L |
21629 | //SPI_PS_INPUT_CNTL_18 |
21630 | #define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 |
21631 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 |
21632 | #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa |
21633 | #define SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR__SHIFT 0xb |
21634 | #define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd |
21635 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 |
21636 | #define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 |
21637 | #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 |
21638 | #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21639 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21640 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21641 | #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 |
21642 | #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 |
21643 | #define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL |
21644 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L |
21645 | #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L |
21646 | #define SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR_MASK 0x00000800L |
21647 | #define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L |
21648 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L |
21649 | #define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L |
21650 | #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L |
21651 | #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21652 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21653 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21654 | #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L |
21655 | #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L |
21656 | //SPI_PS_INPUT_CNTL_19 |
21657 | #define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 |
21658 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 |
21659 | #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa |
21660 | #define SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR__SHIFT 0xb |
21661 | #define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd |
21662 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 |
21663 | #define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 |
21664 | #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 |
21665 | #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21666 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21667 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
21668 | #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 |
21669 | #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 |
21670 | #define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL |
21671 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L |
21672 | #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L |
21673 | #define SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR_MASK 0x00000800L |
21674 | #define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L |
21675 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L |
21676 | #define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L |
21677 | #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L |
21678 | #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21679 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21680 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
21681 | #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L |
21682 | #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L |
21683 | //SPI_PS_INPUT_CNTL_20 |
21684 | #define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 |
21685 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 |
21686 | #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa |
21687 | #define SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR__SHIFT 0xb |
21688 | #define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 |
21689 | #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 |
21690 | #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21691 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21692 | #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 |
21693 | #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 |
21694 | #define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL |
21695 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L |
21696 | #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L |
21697 | #define SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR_MASK 0x00000800L |
21698 | #define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L |
21699 | #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L |
21700 | #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21701 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21702 | #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L |
21703 | #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L |
21704 | //SPI_PS_INPUT_CNTL_21 |
21705 | #define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 |
21706 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 |
21707 | #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa |
21708 | #define SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR__SHIFT 0xb |
21709 | #define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 |
21710 | #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 |
21711 | #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21712 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21713 | #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 |
21714 | #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 |
21715 | #define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL |
21716 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L |
21717 | #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L |
21718 | #define SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR_MASK 0x00000800L |
21719 | #define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L |
21720 | #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L |
21721 | #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21722 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21723 | #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L |
21724 | #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L |
21725 | //SPI_PS_INPUT_CNTL_22 |
21726 | #define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 |
21727 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 |
21728 | #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa |
21729 | #define SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR__SHIFT 0xb |
21730 | #define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 |
21731 | #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 |
21732 | #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21733 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21734 | #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 |
21735 | #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 |
21736 | #define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL |
21737 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L |
21738 | #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L |
21739 | #define SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR_MASK 0x00000800L |
21740 | #define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L |
21741 | #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L |
21742 | #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21743 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21744 | #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L |
21745 | #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L |
21746 | //SPI_PS_INPUT_CNTL_23 |
21747 | #define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 |
21748 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 |
21749 | #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa |
21750 | #define SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR__SHIFT 0xb |
21751 | #define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 |
21752 | #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 |
21753 | #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21754 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21755 | #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 |
21756 | #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 |
21757 | #define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL |
21758 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L |
21759 | #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L |
21760 | #define SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR_MASK 0x00000800L |
21761 | #define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L |
21762 | #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L |
21763 | #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21764 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21765 | #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L |
21766 | #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L |
21767 | //SPI_PS_INPUT_CNTL_24 |
21768 | #define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 |
21769 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 |
21770 | #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa |
21771 | #define SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR__SHIFT 0xb |
21772 | #define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 |
21773 | #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 |
21774 | #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21775 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21776 | #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 |
21777 | #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 |
21778 | #define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL |
21779 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L |
21780 | #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L |
21781 | #define SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR_MASK 0x00000800L |
21782 | #define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L |
21783 | #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L |
21784 | #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21785 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21786 | #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L |
21787 | #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L |
21788 | //SPI_PS_INPUT_CNTL_25 |
21789 | #define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 |
21790 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 |
21791 | #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa |
21792 | #define SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR__SHIFT 0xb |
21793 | #define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 |
21794 | #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 |
21795 | #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21796 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21797 | #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 |
21798 | #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 |
21799 | #define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL |
21800 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L |
21801 | #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L |
21802 | #define SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR_MASK 0x00000800L |
21803 | #define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L |
21804 | #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L |
21805 | #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21806 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21807 | #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L |
21808 | #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L |
21809 | //SPI_PS_INPUT_CNTL_26 |
21810 | #define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 |
21811 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 |
21812 | #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa |
21813 | #define SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR__SHIFT 0xb |
21814 | #define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 |
21815 | #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 |
21816 | #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21817 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21818 | #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 |
21819 | #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 |
21820 | #define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL |
21821 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L |
21822 | #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L |
21823 | #define SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR_MASK 0x00000800L |
21824 | #define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L |
21825 | #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L |
21826 | #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21827 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21828 | #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L |
21829 | #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L |
21830 | //SPI_PS_INPUT_CNTL_27 |
21831 | #define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 |
21832 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 |
21833 | #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa |
21834 | #define SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR__SHIFT 0xb |
21835 | #define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 |
21836 | #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 |
21837 | #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21838 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21839 | #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 |
21840 | #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 |
21841 | #define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL |
21842 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L |
21843 | #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L |
21844 | #define SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR_MASK 0x00000800L |
21845 | #define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L |
21846 | #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L |
21847 | #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21848 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21849 | #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L |
21850 | #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L |
21851 | //SPI_PS_INPUT_CNTL_28 |
21852 | #define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 |
21853 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 |
21854 | #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa |
21855 | #define SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR__SHIFT 0xb |
21856 | #define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 |
21857 | #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 |
21858 | #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21859 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21860 | #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 |
21861 | #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 |
21862 | #define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL |
21863 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L |
21864 | #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L |
21865 | #define SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR_MASK 0x00000800L |
21866 | #define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L |
21867 | #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L |
21868 | #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21869 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21870 | #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L |
21871 | #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L |
21872 | //SPI_PS_INPUT_CNTL_29 |
21873 | #define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 |
21874 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 |
21875 | #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa |
21876 | #define SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR__SHIFT 0xb |
21877 | #define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 |
21878 | #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 |
21879 | #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21880 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21881 | #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 |
21882 | #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 |
21883 | #define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL |
21884 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L |
21885 | #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L |
21886 | #define SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR_MASK 0x00000800L |
21887 | #define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L |
21888 | #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L |
21889 | #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21890 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21891 | #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L |
21892 | #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L |
21893 | //SPI_PS_INPUT_CNTL_30 |
21894 | #define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 |
21895 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 |
21896 | #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa |
21897 | #define SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR__SHIFT 0xb |
21898 | #define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 |
21899 | #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 |
21900 | #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21901 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21902 | #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 |
21903 | #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 |
21904 | #define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL |
21905 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L |
21906 | #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L |
21907 | #define SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR_MASK 0x00000800L |
21908 | #define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L |
21909 | #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L |
21910 | #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21911 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21912 | #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L |
21913 | #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L |
21914 | //SPI_PS_INPUT_CNTL_31 |
21915 | #define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 |
21916 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 |
21917 | #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa |
21918 | #define SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR__SHIFT 0xb |
21919 | #define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 |
21920 | #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 |
21921 | #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 |
21922 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
21923 | #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 |
21924 | #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 |
21925 | #define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL |
21926 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L |
21927 | #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L |
21928 | #define SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR_MASK 0x00000800L |
21929 | #define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L |
21930 | #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L |
21931 | #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L |
21932 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
21933 | #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L |
21934 | #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L |
21935 | //SPI_VS_OUT_CONFIG |
21936 | #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 |
21937 | #define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 |
21938 | #define SPI_VS_OUT_CONFIG__NO_PC_EXPORT__SHIFT 0x7 |
21939 | #define SPI_VS_OUT_CONFIG__PRIM_EXPORT_COUNT__SHIFT 0x8 |
21940 | #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL |
21941 | #define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L |
21942 | #define SPI_VS_OUT_CONFIG__NO_PC_EXPORT_MASK 0x00000080L |
21943 | #define SPI_VS_OUT_CONFIG__PRIM_EXPORT_COUNT_MASK 0x00001F00L |
21944 | //SPI_PS_INPUT_ENA |
21945 | #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 |
21946 | #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 |
21947 | #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 |
21948 | #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 |
21949 | #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 |
21950 | #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 |
21951 | #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 |
21952 | #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 |
21953 | #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 |
21954 | #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 |
21955 | #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa |
21956 | #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb |
21957 | #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc |
21958 | #define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd |
21959 | #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe |
21960 | #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf |
21961 | #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L |
21962 | #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L |
21963 | #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L |
21964 | #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L |
21965 | #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L |
21966 | #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L |
21967 | #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L |
21968 | #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L |
21969 | #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L |
21970 | #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L |
21971 | #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L |
21972 | #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L |
21973 | #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L |
21974 | #define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L |
21975 | #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L |
21976 | #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L |
21977 | //SPI_PS_INPUT_ADDR |
21978 | #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 |
21979 | #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 |
21980 | #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 |
21981 | #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 |
21982 | #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 |
21983 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 |
21984 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 |
21985 | #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 |
21986 | #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 |
21987 | #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 |
21988 | #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa |
21989 | #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb |
21990 | #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc |
21991 | #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd |
21992 | #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe |
21993 | #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf |
21994 | #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L |
21995 | #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L |
21996 | #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L |
21997 | #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L |
21998 | #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L |
21999 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L |
22000 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L |
22001 | #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L |
22002 | #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L |
22003 | #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L |
22004 | #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L |
22005 | #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L |
22006 | #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L |
22007 | #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L |
22008 | #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L |
22009 | #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L |
22010 | //SPI_INTERP_CONTROL_0 |
22011 | #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 |
22012 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 |
22013 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 |
22014 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 |
22015 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 |
22016 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb |
22017 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe |
22018 | #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L |
22019 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L |
22020 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL |
22021 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L |
22022 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L |
22023 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L |
22024 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L |
22025 | //SPI_PS_IN_CONTROL |
22026 | #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 |
22027 | #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7 |
22028 | #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8 |
22029 | #define SPI_PS_IN_CONTROL__NUM_PRIM_INTERP__SHIFT 0x9 |
22030 | #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe |
22031 | #define SPI_PS_IN_CONTROL__PS_W32_EN__SHIFT 0xf |
22032 | #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL |
22033 | #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L |
22034 | #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L |
22035 | #define SPI_PS_IN_CONTROL__NUM_PRIM_INTERP_MASK 0x00003E00L |
22036 | #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L |
22037 | #define SPI_PS_IN_CONTROL__PS_W32_EN_MASK 0x00008000L |
22038 | //SPI_BARYC_CNTL |
22039 | #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 |
22040 | #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 |
22041 | #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 |
22042 | #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc |
22043 | #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 |
22044 | #define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 |
22045 | #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 |
22046 | #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L |
22047 | #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L |
22048 | #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L |
22049 | #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L |
22050 | #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L |
22051 | #define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L |
22052 | #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L |
22053 | //SPI_TMPRING_SIZE |
22054 | #define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 |
22055 | #define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc |
22056 | #define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL |
22057 | #define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L |
22058 | //SPI_SHADER_IDX_FORMAT |
22059 | #define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT__SHIFT 0x0 |
22060 | #define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT_MASK 0x0000000FL |
22061 | //SPI_SHADER_POS_FORMAT |
22062 | #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 |
22063 | #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 |
22064 | #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 |
22065 | #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc |
22066 | #define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT__SHIFT 0x10 |
22067 | #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL |
22068 | #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L |
22069 | #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L |
22070 | #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L |
22071 | #define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT_MASK 0x000F0000L |
22072 | //SPI_SHADER_Z_FORMAT |
22073 | #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 |
22074 | #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL |
22075 | //SPI_SHADER_COL_FORMAT |
22076 | #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 |
22077 | #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 |
22078 | #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 |
22079 | #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc |
22080 | #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 |
22081 | #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 |
22082 | #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 |
22083 | #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c |
22084 | #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL |
22085 | #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L |
22086 | #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L |
22087 | #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L |
22088 | #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L |
22089 | #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L |
22090 | #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L |
22091 | #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L |
22092 | //SX_PS_DOWNCONVERT_CONTROL |
22093 | #define SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE__SHIFT 0x0 |
22094 | #define SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE__SHIFT 0x1 |
22095 | #define SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE__SHIFT 0x2 |
22096 | #define SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE__SHIFT 0x3 |
22097 | #define SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE__SHIFT 0x4 |
22098 | #define SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE__SHIFT 0x5 |
22099 | #define SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE__SHIFT 0x6 |
22100 | #define SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE__SHIFT 0x7 |
22101 | #define SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE_MASK 0x00000001L |
22102 | #define SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE_MASK 0x00000002L |
22103 | #define SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE_MASK 0x00000004L |
22104 | #define SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE_MASK 0x00000008L |
22105 | #define SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE_MASK 0x00000010L |
22106 | #define SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE_MASK 0x00000020L |
22107 | #define SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE_MASK 0x00000040L |
22108 | #define SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE_MASK 0x00000080L |
22109 | //SX_PS_DOWNCONVERT |
22110 | #define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 |
22111 | #define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 |
22112 | #define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 |
22113 | #define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc |
22114 | #define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 |
22115 | #define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 |
22116 | #define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 |
22117 | #define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c |
22118 | #define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL |
22119 | #define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L |
22120 | #define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L |
22121 | #define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L |
22122 | #define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L |
22123 | #define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L |
22124 | #define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L |
22125 | #define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L |
22126 | //SX_BLEND_OPT_EPSILON |
22127 | #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 |
22128 | #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 |
22129 | #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 |
22130 | #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc |
22131 | #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 |
22132 | #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 |
22133 | #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 |
22134 | #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c |
22135 | #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL |
22136 | #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L |
22137 | #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L |
22138 | #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L |
22139 | #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L |
22140 | #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L |
22141 | #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L |
22142 | #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L |
22143 | //SX_BLEND_OPT_CONTROL |
22144 | #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 |
22145 | #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 |
22146 | #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 |
22147 | #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 |
22148 | #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 |
22149 | #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 |
22150 | #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc |
22151 | #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd |
22152 | #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 |
22153 | #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 |
22154 | #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 |
22155 | #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 |
22156 | #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 |
22157 | #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 |
22158 | #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c |
22159 | #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d |
22160 | #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f |
22161 | #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L |
22162 | #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L |
22163 | #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L |
22164 | #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L |
22165 | #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L |
22166 | #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L |
22167 | #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L |
22168 | #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L |
22169 | #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L |
22170 | #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L |
22171 | #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L |
22172 | #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L |
22173 | #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L |
22174 | #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L |
22175 | #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L |
22176 | #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L |
22177 | #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L |
22178 | //SX_MRT0_BLEND_OPT |
22179 | #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
22180 | #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
22181 | #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
22182 | #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
22183 | #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
22184 | #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
22185 | #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
22186 | #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
22187 | #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
22188 | #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
22189 | #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
22190 | #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
22191 | //SX_MRT1_BLEND_OPT |
22192 | #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
22193 | #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
22194 | #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
22195 | #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
22196 | #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
22197 | #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
22198 | #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
22199 | #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
22200 | #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
22201 | #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
22202 | #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
22203 | #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
22204 | //SX_MRT2_BLEND_OPT |
22205 | #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
22206 | #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
22207 | #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
22208 | #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
22209 | #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
22210 | #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
22211 | #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
22212 | #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
22213 | #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
22214 | #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
22215 | #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
22216 | #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
22217 | //SX_MRT3_BLEND_OPT |
22218 | #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
22219 | #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
22220 | #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
22221 | #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
22222 | #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
22223 | #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
22224 | #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
22225 | #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
22226 | #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
22227 | #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
22228 | #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
22229 | #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
22230 | //SX_MRT4_BLEND_OPT |
22231 | #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
22232 | #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
22233 | #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
22234 | #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
22235 | #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
22236 | #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
22237 | #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
22238 | #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
22239 | #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
22240 | #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
22241 | #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
22242 | #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
22243 | //SX_MRT5_BLEND_OPT |
22244 | #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
22245 | #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
22246 | #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
22247 | #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
22248 | #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
22249 | #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
22250 | #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
22251 | #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
22252 | #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
22253 | #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
22254 | #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
22255 | #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
22256 | //SX_MRT6_BLEND_OPT |
22257 | #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
22258 | #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
22259 | #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
22260 | #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
22261 | #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
22262 | #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
22263 | #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
22264 | #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
22265 | #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
22266 | #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
22267 | #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
22268 | #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
22269 | //SX_MRT7_BLEND_OPT |
22270 | #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
22271 | #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
22272 | #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
22273 | #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
22274 | #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
22275 | #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
22276 | #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
22277 | #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
22278 | #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
22279 | #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
22280 | #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
22281 | #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
22282 | //CB_BLEND0_CONTROL |
22283 | #define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
22284 | #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
22285 | #define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
22286 | #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
22287 | #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
22288 | #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
22289 | #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
22290 | #define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e |
22291 | #define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
22292 | #define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
22293 | #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
22294 | #define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
22295 | #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
22296 | #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
22297 | #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
22298 | #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
22299 | #define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L |
22300 | #define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
22301 | //CB_BLEND1_CONTROL |
22302 | #define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
22303 | #define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
22304 | #define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
22305 | #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
22306 | #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
22307 | #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
22308 | #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
22309 | #define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e |
22310 | #define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
22311 | #define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
22312 | #define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
22313 | #define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
22314 | #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
22315 | #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
22316 | #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
22317 | #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
22318 | #define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L |
22319 | #define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
22320 | //CB_BLEND2_CONTROL |
22321 | #define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
22322 | #define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
22323 | #define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
22324 | #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
22325 | #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
22326 | #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
22327 | #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
22328 | #define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e |
22329 | #define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
22330 | #define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
22331 | #define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
22332 | #define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
22333 | #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
22334 | #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
22335 | #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
22336 | #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
22337 | #define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L |
22338 | #define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
22339 | //CB_BLEND3_CONTROL |
22340 | #define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
22341 | #define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
22342 | #define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
22343 | #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
22344 | #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
22345 | #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
22346 | #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
22347 | #define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e |
22348 | #define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
22349 | #define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
22350 | #define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
22351 | #define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
22352 | #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
22353 | #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
22354 | #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
22355 | #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
22356 | #define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L |
22357 | #define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
22358 | //CB_BLEND4_CONTROL |
22359 | #define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
22360 | #define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
22361 | #define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
22362 | #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
22363 | #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
22364 | #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
22365 | #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
22366 | #define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e |
22367 | #define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
22368 | #define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
22369 | #define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
22370 | #define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
22371 | #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
22372 | #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
22373 | #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
22374 | #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
22375 | #define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L |
22376 | #define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
22377 | //CB_BLEND5_CONTROL |
22378 | #define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
22379 | #define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
22380 | #define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
22381 | #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
22382 | #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
22383 | #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
22384 | #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
22385 | #define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e |
22386 | #define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
22387 | #define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
22388 | #define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
22389 | #define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
22390 | #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
22391 | #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
22392 | #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
22393 | #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
22394 | #define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L |
22395 | #define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
22396 | //CB_BLEND6_CONTROL |
22397 | #define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
22398 | #define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
22399 | #define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
22400 | #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
22401 | #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
22402 | #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
22403 | #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
22404 | #define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e |
22405 | #define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
22406 | #define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
22407 | #define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
22408 | #define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
22409 | #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
22410 | #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
22411 | #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
22412 | #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
22413 | #define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L |
22414 | #define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
22415 | //CB_BLEND7_CONTROL |
22416 | #define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
22417 | #define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
22418 | #define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
22419 | #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
22420 | #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
22421 | #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
22422 | #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
22423 | #define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e |
22424 | #define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
22425 | #define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
22426 | #define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
22427 | #define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
22428 | #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
22429 | #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
22430 | #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
22431 | #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
22432 | #define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L |
22433 | #define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
22434 | //CS_COPY_STATE |
22435 | #define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 |
22436 | #define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L |
22437 | //GFX_COPY_STATE |
22438 | #define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 |
22439 | #define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L |
22440 | //PA_CL_POINT_X_RAD |
22441 | #define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 |
22442 | #define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL |
22443 | //PA_CL_POINT_Y_RAD |
22444 | #define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 |
22445 | #define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL |
22446 | //PA_CL_POINT_SIZE |
22447 | #define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 |
22448 | #define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL |
22449 | //PA_CL_POINT_CULL_RAD |
22450 | #define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 |
22451 | #define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL |
22452 | //VGT_DMA_BASE_HI |
22453 | #define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 |
22454 | #define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL |
22455 | //VGT_DMA_BASE |
22456 | #define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 |
22457 | #define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL |
22458 | //VGT_DRAW_INITIATOR |
22459 | #define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 |
22460 | #define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 |
22461 | #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 |
22462 | #define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 |
22463 | #define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 |
22464 | #define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d |
22465 | #define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L |
22466 | #define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL |
22467 | #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L |
22468 | #define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L |
22469 | #define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L |
22470 | #define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L |
22471 | //VGT_IMMED_DATA |
22472 | #define VGT_IMMED_DATA__DATA__SHIFT 0x0 |
22473 | #define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL |
22474 | //VGT_EVENT_ADDRESS_REG |
22475 | #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 |
22476 | #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL |
22477 | //GE_MAX_OUTPUT_PER_SUBGROUP |
22478 | #define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP__SHIFT 0x0 |
22479 | #define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP_MASK 0x000003FFL |
22480 | //DB_DEPTH_CONTROL |
22481 | #define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 |
22482 | #define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 |
22483 | #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 |
22484 | #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 |
22485 | #define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 |
22486 | #define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 |
22487 | #define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 |
22488 | #define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 |
22489 | #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e |
22490 | #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f |
22491 | #define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L |
22492 | #define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L |
22493 | #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L |
22494 | #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L |
22495 | #define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L |
22496 | #define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L |
22497 | #define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L |
22498 | #define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L |
22499 | #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L |
22500 | #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L |
22501 | //DB_EQAA |
22502 | #define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 |
22503 | #define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 |
22504 | #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 |
22505 | #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc |
22506 | #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 |
22507 | #define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 |
22508 | #define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 |
22509 | #define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 |
22510 | #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 |
22511 | #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 |
22512 | #define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 |
22513 | #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b |
22514 | #define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L |
22515 | #define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L |
22516 | #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L |
22517 | #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L |
22518 | #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L |
22519 | #define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L |
22520 | #define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L |
22521 | #define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L |
22522 | #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L |
22523 | #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L |
22524 | #define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L |
22525 | #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L |
22526 | //CB_COLOR_CONTROL |
22527 | #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 |
22528 | #define CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE__SHIFT 0x1 |
22529 | #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 |
22530 | #define CB_COLOR_CONTROL__MODE__SHIFT 0x4 |
22531 | #define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 |
22532 | #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L |
22533 | #define CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE_MASK 0x00000002L |
22534 | #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L |
22535 | #define CB_COLOR_CONTROL__MODE_MASK 0x00000070L |
22536 | #define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L |
22537 | //DB_SHADER_CONTROL |
22538 | #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 |
22539 | #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 |
22540 | #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 |
22541 | #define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 |
22542 | #define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 |
22543 | #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 |
22544 | #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 |
22545 | #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 |
22546 | #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa |
22547 | #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb |
22548 | #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc |
22549 | #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd |
22550 | #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf |
22551 | #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10 |
22552 | #define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11 |
22553 | #define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14 |
22554 | #define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE__SHIFT 0x17 |
22555 | #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L |
22556 | #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L |
22557 | #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L |
22558 | #define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L |
22559 | #define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L |
22560 | #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L |
22561 | #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L |
22562 | #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L |
22563 | #define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L |
22564 | #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L |
22565 | #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L |
22566 | #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L |
22567 | #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L |
22568 | #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L |
22569 | #define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L |
22570 | #define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L |
22571 | #define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE_MASK 0x00800000L |
22572 | //PA_CL_CLIP_CNTL |
22573 | #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 |
22574 | #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 |
22575 | #define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 |
22576 | #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 |
22577 | #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 |
22578 | #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 |
22579 | #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd |
22580 | #define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe |
22581 | #define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 |
22582 | #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 |
22583 | #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 |
22584 | #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 |
22585 | #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 |
22586 | #define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 |
22587 | #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 |
22588 | #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 |
22589 | #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 |
22590 | #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a |
22591 | #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b |
22592 | #define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT 0x1c |
22593 | #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L |
22594 | #define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L |
22595 | #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L |
22596 | #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L |
22597 | #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L |
22598 | #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L |
22599 | #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L |
22600 | #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L |
22601 | #define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L |
22602 | #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L |
22603 | #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L |
22604 | #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L |
22605 | #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L |
22606 | #define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L |
22607 | #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L |
22608 | #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L |
22609 | #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L |
22610 | #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L |
22611 | #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L |
22612 | #define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK 0x10000000L |
22613 | //PA_SU_SC_MODE_CNTL |
22614 | #define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 |
22615 | #define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 |
22616 | #define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 |
22617 | #define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 |
22618 | #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 |
22619 | #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 |
22620 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb |
22621 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc |
22622 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd |
22623 | #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 |
22624 | #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 |
22625 | #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 |
22626 | #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 |
22627 | #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16 |
22628 | #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17 |
22629 | #define PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE__SHIFT 0x18 |
22630 | #define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L |
22631 | #define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L |
22632 | #define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L |
22633 | #define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L |
22634 | #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L |
22635 | #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L |
22636 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L |
22637 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L |
22638 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L |
22639 | #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L |
22640 | #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L |
22641 | #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L |
22642 | #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L |
22643 | #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L |
22644 | #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L |
22645 | #define PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE_MASK 0x01000000L |
22646 | //PA_CL_VTE_CNTL |
22647 | #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 |
22648 | #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 |
22649 | #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 |
22650 | #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 |
22651 | #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 |
22652 | #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 |
22653 | #define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 |
22654 | #define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 |
22655 | #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa |
22656 | #define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb |
22657 | #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L |
22658 | #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L |
22659 | #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L |
22660 | #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L |
22661 | #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L |
22662 | #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L |
22663 | #define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L |
22664 | #define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L |
22665 | #define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L |
22666 | #define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L |
22667 | //PA_CL_VS_OUT_CNTL |
22668 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 |
22669 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 |
22670 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 |
22671 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 |
22672 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 |
22673 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 |
22674 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 |
22675 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 |
22676 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 |
22677 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 |
22678 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa |
22679 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb |
22680 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc |
22681 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd |
22682 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe |
22683 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf |
22684 | #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 |
22685 | #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 |
22686 | #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 |
22687 | #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 |
22688 | #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 |
22689 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 |
22690 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 |
22691 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 |
22692 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 |
22693 | #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 |
22694 | #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1b |
22695 | #define PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE__SHIFT 0x1c |
22696 | #define PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER__SHIFT 0x1d |
22697 | #define PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER__SHIFT 0x1e |
22698 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L |
22699 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L |
22700 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L |
22701 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L |
22702 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L |
22703 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L |
22704 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L |
22705 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L |
22706 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L |
22707 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L |
22708 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L |
22709 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L |
22710 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L |
22711 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L |
22712 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L |
22713 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L |
22714 | #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L |
22715 | #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L |
22716 | #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L |
22717 | #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L |
22718 | #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L |
22719 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L |
22720 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L |
22721 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L |
22722 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L |
22723 | #define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L |
22724 | #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x08000000L |
22725 | #define PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE_MASK 0x10000000L |
22726 | #define PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER_MASK 0x20000000L |
22727 | #define PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER_MASK 0x40000000L |
22728 | //PA_CL_NANINF_CNTL |
22729 | #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 |
22730 | #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 |
22731 | #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 |
22732 | #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 |
22733 | #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 |
22734 | #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 |
22735 | #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 |
22736 | #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 |
22737 | #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 |
22738 | #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 |
22739 | #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa |
22740 | #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb |
22741 | #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc |
22742 | #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd |
22743 | #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe |
22744 | #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 |
22745 | #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L |
22746 | #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L |
22747 | #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L |
22748 | #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L |
22749 | #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L |
22750 | #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L |
22751 | #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L |
22752 | #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L |
22753 | #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L |
22754 | #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L |
22755 | #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L |
22756 | #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L |
22757 | #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L |
22758 | #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L |
22759 | #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L |
22760 | #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L |
22761 | //PA_SU_LINE_STIPPLE_CNTL |
22762 | #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 |
22763 | #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 |
22764 | #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 |
22765 | #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 |
22766 | #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L |
22767 | #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L |
22768 | #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L |
22769 | #define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L |
22770 | //PA_SU_LINE_STIPPLE_SCALE |
22771 | #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 |
22772 | #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL |
22773 | //PA_SU_PRIM_FILTER_CNTL |
22774 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 |
22775 | #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 |
22776 | #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 |
22777 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 |
22778 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 |
22779 | #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 |
22780 | #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 |
22781 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 |
22782 | #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 |
22783 | #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e |
22784 | #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f |
22785 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L |
22786 | #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L |
22787 | #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L |
22788 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L |
22789 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L |
22790 | #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L |
22791 | #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L |
22792 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L |
22793 | #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L |
22794 | #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L |
22795 | #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L |
22796 | //PA_SU_SMALL_PRIM_FILTER_CNTL |
22797 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0 |
22798 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1 |
22799 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 |
22800 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 |
22801 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 |
22802 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L |
22803 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L |
22804 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L |
22805 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L |
22806 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L |
22807 | //PA_CL_NGG_CNTL |
22808 | #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0 |
22809 | #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1 |
22810 | #define PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH__SHIFT 0x2 |
22811 | #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L |
22812 | #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L |
22813 | #define PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH_MASK 0x000003FCL |
22814 | //PA_SU_OVER_RASTERIZATION_CNTL |
22815 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0 |
22816 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1 |
22817 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2 |
22818 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3 |
22819 | #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4 |
22820 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L |
22821 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L |
22822 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L |
22823 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L |
22824 | #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L |
22825 | //PA_STEREO_CNTL |
22826 | #define PA_STEREO_CNTL__STEREO_MODE__SHIFT 0x1 |
22827 | #define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT 0x5 |
22828 | #define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT 0x8 |
22829 | #define PA_STEREO_CNTL__VP_ID_MODE__SHIFT 0x10 |
22830 | #define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT 0x13 |
22831 | #define PA_STEREO_CNTL__STEREO_MODE_MASK 0x0000001EL |
22832 | #define PA_STEREO_CNTL__RT_SLICE_MODE_MASK 0x000000E0L |
22833 | #define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK 0x00000F00L |
22834 | #define PA_STEREO_CNTL__VP_ID_MODE_MASK 0x00070000L |
22835 | #define PA_STEREO_CNTL__VP_ID_OFFSET_MASK 0x00780000L |
22836 | //PA_STATE_STEREO_X |
22837 | #define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT 0x0 |
22838 | #define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK 0xFFFFFFFFL |
22839 | //PA_CL_VRS_CNTL |
22840 | #define PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE__SHIFT 0x0 |
22841 | #define PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE__SHIFT 0x3 |
22842 | #define PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE__SHIFT 0x6 |
22843 | #define PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE__SHIFT 0x9 |
22844 | #define PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK__SHIFT 0xd |
22845 | #define PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO__SHIFT 0xe |
22846 | #define PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE_MASK 0x00000007L |
22847 | #define PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE_MASK 0x00000038L |
22848 | #define PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE_MASK 0x000001C0L |
22849 | #define PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE_MASK 0x00000E00L |
22850 | #define PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK_MASK 0x00002000L |
22851 | #define PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO_MASK 0x00004000L |
22852 | //PA_SU_POINT_SIZE |
22853 | #define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 |
22854 | #define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 |
22855 | #define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL |
22856 | #define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L |
22857 | //PA_SU_POINT_MINMAX |
22858 | #define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 |
22859 | #define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 |
22860 | #define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL |
22861 | #define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L |
22862 | //PA_SU_LINE_CNTL |
22863 | #define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 |
22864 | #define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL |
22865 | //PA_SC_LINE_STIPPLE |
22866 | #define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 |
22867 | #define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 |
22868 | #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c |
22869 | #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d |
22870 | #define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL |
22871 | #define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L |
22872 | #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L |
22873 | #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L |
22874 | //VGT_OUTPUT_PATH_CNTL |
22875 | #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 |
22876 | #define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L |
22877 | //VGT_HOS_CNTL |
22878 | #define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 |
22879 | #define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L |
22880 | //VGT_HOS_MAX_TESS_LEVEL |
22881 | #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 |
22882 | #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL |
22883 | //VGT_HOS_MIN_TESS_LEVEL |
22884 | #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 |
22885 | #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL |
22886 | //VGT_HOS_REUSE_DEPTH |
22887 | #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 |
22888 | #define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL |
22889 | //VGT_GROUP_PRIM_TYPE |
22890 | #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 |
22891 | #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe |
22892 | #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf |
22893 | #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 |
22894 | #define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL |
22895 | #define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L |
22896 | #define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L |
22897 | #define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L |
22898 | //VGT_GROUP_FIRST_DECR |
22899 | #define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 |
22900 | #define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL |
22901 | //VGT_GROUP_DECR |
22902 | #define VGT_GROUP_DECR__DECR__SHIFT 0x0 |
22903 | #define VGT_GROUP_DECR__DECR_MASK 0x0000000FL |
22904 | //VGT_GROUP_VECT_0_CNTL |
22905 | #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 |
22906 | #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 |
22907 | #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 |
22908 | #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 |
22909 | #define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 |
22910 | #define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 |
22911 | #define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L |
22912 | #define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L |
22913 | #define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L |
22914 | #define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L |
22915 | #define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L |
22916 | #define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L |
22917 | //VGT_GROUP_VECT_1_CNTL |
22918 | #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 |
22919 | #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 |
22920 | #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 |
22921 | #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 |
22922 | #define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 |
22923 | #define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 |
22924 | #define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L |
22925 | #define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L |
22926 | #define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L |
22927 | #define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L |
22928 | #define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L |
22929 | #define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L |
22930 | //VGT_GROUP_VECT_0_FMT_CNTL |
22931 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 |
22932 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 |
22933 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 |
22934 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc |
22935 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 |
22936 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 |
22937 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 |
22938 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c |
22939 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL |
22940 | #define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L |
22941 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L |
22942 | #define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L |
22943 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L |
22944 | #define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L |
22945 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L |
22946 | #define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L |
22947 | //VGT_GROUP_VECT_1_FMT_CNTL |
22948 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 |
22949 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 |
22950 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 |
22951 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc |
22952 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 |
22953 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 |
22954 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 |
22955 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c |
22956 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL |
22957 | #define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L |
22958 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L |
22959 | #define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L |
22960 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L |
22961 | #define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L |
22962 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L |
22963 | #define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L |
22964 | //VGT_GS_MODE |
22965 | #define VGT_GS_MODE__MODE__SHIFT 0x0 |
22966 | #define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 |
22967 | #define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 |
22968 | #define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 |
22969 | #define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb |
22970 | #define VGT_GS_MODE__RESERVED_2__SHIFT 0xc |
22971 | #define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd |
22972 | #define VGT_GS_MODE__COMPUTE_MODE__SHIFT 0xe |
22973 | #define VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT 0xf |
22974 | #define VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT 0x10 |
22975 | #define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 |
22976 | #define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 |
22977 | #define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 |
22978 | #define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 |
22979 | #define VGT_GS_MODE__ONCHIP__SHIFT 0x15 |
22980 | #define VGT_GS_MODE__MODE_MASK 0x00000007L |
22981 | #define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L |
22982 | #define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L |
22983 | #define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L |
22984 | #define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L |
22985 | #define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L |
22986 | #define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L |
22987 | #define VGT_GS_MODE__COMPUTE_MODE_MASK 0x00004000L |
22988 | #define VGT_GS_MODE__FAST_COMPUTE_MODE_MASK 0x00008000L |
22989 | #define VGT_GS_MODE__ELEMENT_INFO_EN_MASK 0x00010000L |
22990 | #define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L |
22991 | #define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L |
22992 | #define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L |
22993 | #define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L |
22994 | #define VGT_GS_MODE__ONCHIP_MASK 0x00600000L |
22995 | //VGT_GS_ONCHIP_CNTL |
22996 | #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 |
22997 | #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb |
22998 | #define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16 |
22999 | #define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL |
23000 | #define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L |
23001 | #define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L |
23002 | //PA_SC_MODE_CNTL_0 |
23003 | #define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 |
23004 | #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 |
23005 | #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 |
23006 | #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 |
23007 | #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5 |
23008 | #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6 |
23009 | #define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L |
23010 | #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L |
23011 | #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L |
23012 | #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L |
23013 | #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L |
23014 | #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L |
23015 | //PA_SC_MODE_CNTL_1 |
23016 | #define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 |
23017 | #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 |
23018 | #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 |
23019 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 |
23020 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 |
23021 | #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 |
23022 | #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 |
23023 | #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 |
23024 | #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa |
23025 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb |
23026 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc |
23027 | #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd |
23028 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe |
23029 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf |
23030 | #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 |
23031 | #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 |
23032 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 |
23033 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 |
23034 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 |
23035 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 |
23036 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 |
23037 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a |
23038 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b |
23039 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c |
23040 | #define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L |
23041 | #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L |
23042 | #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L |
23043 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L |
23044 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L |
23045 | #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L |
23046 | #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L |
23047 | #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L |
23048 | #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L |
23049 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L |
23050 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L |
23051 | #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L |
23052 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L |
23053 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L |
23054 | #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L |
23055 | #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L |
23056 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L |
23057 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L |
23058 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L |
23059 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L |
23060 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L |
23061 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L |
23062 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L |
23063 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L |
23064 | //VGT_ENHANCE |
23065 | #define VGT_ENHANCE__MISC__SHIFT 0x0 |
23066 | #define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL |
23067 | //VGT_GS_PER_ES |
23068 | #define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 |
23069 | #define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL |
23070 | //VGT_ES_PER_GS |
23071 | #define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 |
23072 | #define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL |
23073 | //VGT_GS_PER_VS |
23074 | #define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 |
23075 | #define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL |
23076 | //VGT_GSVS_RING_OFFSET_1 |
23077 | #define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 |
23078 | #define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL |
23079 | //VGT_GSVS_RING_OFFSET_2 |
23080 | #define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 |
23081 | #define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL |
23082 | //VGT_GSVS_RING_OFFSET_3 |
23083 | #define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 |
23084 | #define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL |
23085 | //VGT_GS_OUT_PRIM_TYPE |
23086 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 |
23087 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 |
23088 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 |
23089 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 |
23090 | #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f |
23091 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL |
23092 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L |
23093 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L |
23094 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L |
23095 | #define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L |
23096 | //IA_ENHANCE |
23097 | #define IA_ENHANCE__MISC__SHIFT 0x0 |
23098 | #define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL |
23099 | //VGT_DMA_SIZE |
23100 | #define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 |
23101 | #define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL |
23102 | //VGT_DMA_MAX_SIZE |
23103 | #define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 |
23104 | #define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL |
23105 | //VGT_DMA_INDEX_TYPE |
23106 | #define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 |
23107 | #define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 |
23108 | #define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 |
23109 | #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 |
23110 | #define VGT_DMA_INDEX_TYPE__ATC__SHIFT 0x8 |
23111 | #define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 |
23112 | #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa |
23113 | #define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb |
23114 | #define VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT 0xe |
23115 | #define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L |
23116 | #define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL |
23117 | #define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L |
23118 | #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x000000C0L |
23119 | #define VGT_DMA_INDEX_TYPE__ATC_MASK 0x00000100L |
23120 | #define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L |
23121 | #define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L |
23122 | #define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x00003800L |
23123 | #define VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK 0x00004000L |
23124 | //WD_ENHANCE |
23125 | #define WD_ENHANCE__MISC__SHIFT 0x0 |
23126 | #define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL |
23127 | //VGT_PRIMITIVEID_EN |
23128 | #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 |
23129 | #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 |
23130 | #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2 |
23131 | #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L |
23132 | #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L |
23133 | #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L |
23134 | //VGT_DMA_NUM_INSTANCES |
23135 | #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 |
23136 | #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL |
23137 | //VGT_PRIMITIVEID_RESET |
23138 | #define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 |
23139 | #define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL |
23140 | //VGT_EVENT_INITIATOR |
23141 | #define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 |
23142 | #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa |
23143 | #define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b |
23144 | #define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL |
23145 | #define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L |
23146 | #define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L |
23147 | //VGT_MULTI_PRIM_IB_RESET_EN |
23148 | #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 |
23149 | #define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 |
23150 | #define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L |
23151 | #define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L |
23152 | //VGT_DRAW_PAYLOAD_CNTL |
23153 | #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1 |
23154 | #define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD__SHIFT 0x3 |
23155 | #define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP__SHIFT 0x4 |
23156 | #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L |
23157 | #define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD_MASK 0x00000008L |
23158 | #define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP_MASK 0x00000010L |
23159 | //VGT_INSTANCE_STEP_RATE_0 |
23160 | #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 |
23161 | #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL |
23162 | //VGT_INSTANCE_STEP_RATE_1 |
23163 | #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 |
23164 | #define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL |
23165 | //IA_MULTI_VGT_PARAM |
23166 | #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 |
23167 | #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 |
23168 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 |
23169 | #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 |
23170 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 |
23171 | #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 |
23172 | #define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL |
23173 | #define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L |
23174 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L |
23175 | #define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L |
23176 | #define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L |
23177 | #define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L |
23178 | //VGT_ESGS_RING_ITEMSIZE |
23179 | #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 |
23180 | #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL |
23181 | //VGT_GSVS_RING_ITEMSIZE |
23182 | #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 |
23183 | #define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL |
23184 | //VGT_REUSE_OFF |
23185 | #define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 |
23186 | #define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L |
23187 | //VGT_VTX_CNT_EN |
23188 | #define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 |
23189 | #define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L |
23190 | //DB_HTILE_SURFACE |
23191 | #define DB_HTILE_SURFACE__RESERVED_FIELD_1__SHIFT 0x0 |
23192 | #define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 |
23193 | #define DB_HTILE_SURFACE__RESERVED_FIELD_2__SHIFT 0x2 |
23194 | #define DB_HTILE_SURFACE__RESERVED_FIELD_3__SHIFT 0x3 |
23195 | #define DB_HTILE_SURFACE__RESERVED_FIELD_4__SHIFT 0x4 |
23196 | #define DB_HTILE_SURFACE__RESERVED_FIELD_5__SHIFT 0xa |
23197 | #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 |
23198 | #define DB_HTILE_SURFACE__RESERVED_FIELD_6__SHIFT 0x11 |
23199 | #define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12 |
23200 | #define DB_HTILE_SURFACE__VRS_HTILE_ENCODING__SHIFT 0x13 |
23201 | #define DB_HTILE_SURFACE__RESERVED_FIELD_1_MASK 0x00000001L |
23202 | #define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L |
23203 | #define DB_HTILE_SURFACE__RESERVED_FIELD_2_MASK 0x00000004L |
23204 | #define DB_HTILE_SURFACE__RESERVED_FIELD_3_MASK 0x00000008L |
23205 | #define DB_HTILE_SURFACE__RESERVED_FIELD_4_MASK 0x000003F0L |
23206 | #define DB_HTILE_SURFACE__RESERVED_FIELD_5_MASK 0x0000FC00L |
23207 | #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L |
23208 | #define DB_HTILE_SURFACE__RESERVED_FIELD_6_MASK 0x00020000L |
23209 | #define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L |
23210 | #define DB_HTILE_SURFACE__VRS_HTILE_ENCODING_MASK 0x00180000L |
23211 | //DB_SRESULTS_COMPARE_STATE0 |
23212 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 |
23213 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 |
23214 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc |
23215 | #define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 |
23216 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L |
23217 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L |
23218 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L |
23219 | #define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L |
23220 | //DB_SRESULTS_COMPARE_STATE1 |
23221 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 |
23222 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 |
23223 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc |
23224 | #define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 |
23225 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L |
23226 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L |
23227 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L |
23228 | #define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L |
23229 | //DB_PRELOAD_CONTROL |
23230 | #define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 |
23231 | #define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 |
23232 | #define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 |
23233 | #define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 |
23234 | #define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL |
23235 | #define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L |
23236 | #define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L |
23237 | #define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L |
23238 | //VGT_STRMOUT_BUFFER_SIZE_0 |
23239 | #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 |
23240 | #define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL |
23241 | //VGT_STRMOUT_VTX_STRIDE_0 |
23242 | #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 |
23243 | #define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL |
23244 | //VGT_STRMOUT_BUFFER_OFFSET_0 |
23245 | #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 |
23246 | #define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL |
23247 | //VGT_STRMOUT_BUFFER_SIZE_1 |
23248 | #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 |
23249 | #define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL |
23250 | //VGT_STRMOUT_VTX_STRIDE_1 |
23251 | #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 |
23252 | #define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL |
23253 | //VGT_STRMOUT_BUFFER_OFFSET_1 |
23254 | #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 |
23255 | #define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL |
23256 | //VGT_STRMOUT_BUFFER_SIZE_2 |
23257 | #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 |
23258 | #define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL |
23259 | //VGT_STRMOUT_VTX_STRIDE_2 |
23260 | #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 |
23261 | #define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL |
23262 | //VGT_STRMOUT_BUFFER_OFFSET_2 |
23263 | #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 |
23264 | #define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL |
23265 | //VGT_STRMOUT_BUFFER_SIZE_3 |
23266 | #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 |
23267 | #define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL |
23268 | //VGT_STRMOUT_VTX_STRIDE_3 |
23269 | #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 |
23270 | #define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL |
23271 | //VGT_STRMOUT_BUFFER_OFFSET_3 |
23272 | #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 |
23273 | #define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL |
23274 | //VGT_STRMOUT_DRAW_OPAQUE_OFFSET |
23275 | #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 |
23276 | #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL |
23277 | //VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE |
23278 | #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 |
23279 | #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL |
23280 | //VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE |
23281 | #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 |
23282 | #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL |
23283 | //VGT_GS_MAX_VERT_OUT |
23284 | #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 |
23285 | #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL |
23286 | //GE_NGG_SUBGRP_CNTL |
23287 | #define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR__SHIFT 0x0 |
23288 | #define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP__SHIFT 0x9 |
23289 | #define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR_MASK 0x000001FFL |
23290 | #define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP_MASK 0x0003FE00L |
23291 | //VGT_TESS_DISTRIBUTION |
23292 | #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 |
23293 | #define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 |
23294 | #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 |
23295 | #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 |
23296 | #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d |
23297 | #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL |
23298 | #define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L |
23299 | #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L |
23300 | #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L |
23301 | #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L |
23302 | //VGT_SHADER_STAGES_EN |
23303 | #define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 |
23304 | #define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 |
23305 | #define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 |
23306 | #define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 |
23307 | #define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 |
23308 | #define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8 |
23309 | #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9 |
23310 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa |
23311 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb |
23312 | #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc |
23313 | #define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd |
23314 | #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe |
23315 | #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf |
23316 | #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13 |
23317 | #define VGT_SHADER_STAGES_EN__HS_W32_EN__SHIFT 0x15 |
23318 | #define VGT_SHADER_STAGES_EN__GS_W32_EN__SHIFT 0x16 |
23319 | #define VGT_SHADER_STAGES_EN__VS_W32_EN__SHIFT 0x17 |
23320 | #define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN__SHIFT 0x18 |
23321 | #define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN__SHIFT 0x19 |
23322 | #define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L |
23323 | #define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L |
23324 | #define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L |
23325 | #define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L |
23326 | #define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L |
23327 | #define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x00000100L |
23328 | #define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L |
23329 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L |
23330 | #define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L |
23331 | #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L |
23332 | #define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L |
23333 | #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L |
23334 | #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L |
23335 | #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00180000L |
23336 | #define VGT_SHADER_STAGES_EN__HS_W32_EN_MASK 0x00200000L |
23337 | #define VGT_SHADER_STAGES_EN__GS_W32_EN_MASK 0x00400000L |
23338 | #define VGT_SHADER_STAGES_EN__VS_W32_EN_MASK 0x00800000L |
23339 | #define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN_MASK 0x01000000L |
23340 | #define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN_MASK 0x02000000L |
23341 | //VGT_LS_HS_CONFIG |
23342 | #define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 |
23343 | #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 |
23344 | #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe |
23345 | #define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL |
23346 | #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L |
23347 | #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L |
23348 | //VGT_GS_VERT_ITEMSIZE |
23349 | #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 |
23350 | #define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL |
23351 | //VGT_GS_VERT_ITEMSIZE_1 |
23352 | #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 |
23353 | #define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL |
23354 | //VGT_GS_VERT_ITEMSIZE_2 |
23355 | #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 |
23356 | #define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL |
23357 | //VGT_GS_VERT_ITEMSIZE_3 |
23358 | #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 |
23359 | #define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL |
23360 | //VGT_TF_PARAM |
23361 | #define VGT_TF_PARAM__TYPE__SHIFT 0x0 |
23362 | #define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 |
23363 | #define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 |
23364 | #define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 |
23365 | #define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 |
23366 | #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa |
23367 | #define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe |
23368 | #define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf |
23369 | #define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 |
23370 | #define VGT_TF_PARAM__DETECT_ONE__SHIFT 0x13 |
23371 | #define VGT_TF_PARAM__DETECT_ZERO__SHIFT 0x14 |
23372 | #define VGT_TF_PARAM__MTYPE__SHIFT 0x17 |
23373 | #define VGT_TF_PARAM__TYPE_MASK 0x00000003L |
23374 | #define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL |
23375 | #define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L |
23376 | #define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L |
23377 | #define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L |
23378 | #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x00003C00L |
23379 | #define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L |
23380 | #define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00018000L |
23381 | #define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L |
23382 | #define VGT_TF_PARAM__DETECT_ONE_MASK 0x00080000L |
23383 | #define VGT_TF_PARAM__DETECT_ZERO_MASK 0x00100000L |
23384 | #define VGT_TF_PARAM__MTYPE_MASK 0x03800000L |
23385 | //DB_ALPHA_TO_MASK |
23386 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 |
23387 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 |
23388 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa |
23389 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc |
23390 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe |
23391 | #define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 |
23392 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L |
23393 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L |
23394 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L |
23395 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L |
23396 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L |
23397 | #define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L |
23398 | //VGT_DISPATCH_DRAW_INDEX |
23399 | #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 |
23400 | #define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL |
23401 | //PA_SU_POLY_OFFSET_DB_FMT_CNTL |
23402 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 |
23403 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 |
23404 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL |
23405 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L |
23406 | //PA_SU_POLY_OFFSET_CLAMP |
23407 | #define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 |
23408 | #define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL |
23409 | //PA_SU_POLY_OFFSET_FRONT_SCALE |
23410 | #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 |
23411 | #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL |
23412 | //PA_SU_POLY_OFFSET_FRONT_OFFSET |
23413 | #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 |
23414 | #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL |
23415 | //PA_SU_POLY_OFFSET_BACK_SCALE |
23416 | #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 |
23417 | #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL |
23418 | //PA_SU_POLY_OFFSET_BACK_OFFSET |
23419 | #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 |
23420 | #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL |
23421 | //VGT_GS_INSTANCE_CNT |
23422 | #define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 |
23423 | #define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 |
23424 | #define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE__SHIFT 0x1f |
23425 | #define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L |
23426 | #define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL |
23427 | #define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE_MASK 0x80000000L |
23428 | //VGT_STRMOUT_CONFIG |
23429 | #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 |
23430 | #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 |
23431 | #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 |
23432 | #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 |
23433 | #define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 |
23434 | #define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7 |
23435 | #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 |
23436 | #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f |
23437 | #define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L |
23438 | #define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L |
23439 | #define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L |
23440 | #define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L |
23441 | #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L |
23442 | #define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L |
23443 | #define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L |
23444 | #define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L |
23445 | //VGT_STRMOUT_BUFFER_CONFIG |
23446 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 |
23447 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 |
23448 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 |
23449 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc |
23450 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL |
23451 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L |
23452 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L |
23453 | #define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L |
23454 | //VGT_DMA_EVENT_INITIATOR |
23455 | #define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 |
23456 | #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa |
23457 | #define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b |
23458 | #define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL |
23459 | #define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L |
23460 | #define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L |
23461 | //PA_SC_CENTROID_PRIORITY_0 |
23462 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 |
23463 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 |
23464 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 |
23465 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc |
23466 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 |
23467 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 |
23468 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 |
23469 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c |
23470 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL |
23471 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L |
23472 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L |
23473 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L |
23474 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L |
23475 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L |
23476 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L |
23477 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L |
23478 | //PA_SC_CENTROID_PRIORITY_1 |
23479 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 |
23480 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 |
23481 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 |
23482 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc |
23483 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 |
23484 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 |
23485 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 |
23486 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c |
23487 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL |
23488 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L |
23489 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L |
23490 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L |
23491 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L |
23492 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L |
23493 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L |
23494 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L |
23495 | //PA_SC_LINE_CNTL |
23496 | #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 |
23497 | #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa |
23498 | #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb |
23499 | #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc |
23500 | #define 0xd |
23501 | #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L |
23502 | #define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L |
23503 | #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L |
23504 | #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L |
23505 | #define 0x00002000L |
23506 | //PA_SC_AA_CONFIG |
23507 | #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 |
23508 | #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 |
23509 | #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd |
23510 | #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 |
23511 | #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 |
23512 | #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a |
23513 | #define PA_SC_AA_CONFIG__SAMPLE_COVERAGE_ENCODING__SHIFT 0x1c |
23514 | #define PA_SC_AA_CONFIG__COVERED_CENTROID_IS_CENTER__SHIFT 0x1d |
23515 | #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L |
23516 | #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L |
23517 | #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L |
23518 | #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L |
23519 | #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L |
23520 | #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L |
23521 | #define PA_SC_AA_CONFIG__SAMPLE_COVERAGE_ENCODING_MASK 0x10000000L |
23522 | #define PA_SC_AA_CONFIG__COVERED_CENTROID_IS_CENTER_MASK 0x20000000L |
23523 | //PA_SU_VTX_CNTL |
23524 | #define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 |
23525 | #define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 |
23526 | #define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 |
23527 | #define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L |
23528 | #define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L |
23529 | #define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L |
23530 | //PA_CL_GB_VERT_CLIP_ADJ |
23531 | #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 |
23532 | #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
23533 | //PA_CL_GB_VERT_DISC_ADJ |
23534 | #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 |
23535 | #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
23536 | //PA_CL_GB_HORZ_CLIP_ADJ |
23537 | #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 |
23538 | #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
23539 | //PA_CL_GB_HORZ_DISC_ADJ |
23540 | #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 |
23541 | #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
23542 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 |
23543 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 |
23544 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 |
23545 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 |
23546 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc |
23547 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 |
23548 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 |
23549 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 |
23550 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c |
23551 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL |
23552 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L |
23553 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L |
23554 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L |
23555 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L |
23556 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L |
23557 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L |
23558 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L |
23559 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 |
23560 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 |
23561 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 |
23562 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 |
23563 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc |
23564 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 |
23565 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 |
23566 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 |
23567 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c |
23568 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL |
23569 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L |
23570 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L |
23571 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L |
23572 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L |
23573 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L |
23574 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L |
23575 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L |
23576 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 |
23577 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 |
23578 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 |
23579 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 |
23580 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc |
23581 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 |
23582 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 |
23583 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 |
23584 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c |
23585 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL |
23586 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L |
23587 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L |
23588 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L |
23589 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L |
23590 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L |
23591 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L |
23592 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L |
23593 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 |
23594 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 |
23595 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 |
23596 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 |
23597 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc |
23598 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 |
23599 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 |
23600 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 |
23601 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c |
23602 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL |
23603 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L |
23604 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L |
23605 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L |
23606 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L |
23607 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L |
23608 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L |
23609 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L |
23610 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 |
23611 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 |
23612 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 |
23613 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 |
23614 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc |
23615 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 |
23616 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 |
23617 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 |
23618 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c |
23619 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL |
23620 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L |
23621 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L |
23622 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L |
23623 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L |
23624 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L |
23625 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L |
23626 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L |
23627 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 |
23628 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 |
23629 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 |
23630 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 |
23631 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc |
23632 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 |
23633 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 |
23634 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 |
23635 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c |
23636 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL |
23637 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L |
23638 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L |
23639 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L |
23640 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L |
23641 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L |
23642 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L |
23643 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L |
23644 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 |
23645 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 |
23646 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 |
23647 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 |
23648 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc |
23649 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 |
23650 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 |
23651 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 |
23652 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c |
23653 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL |
23654 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L |
23655 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L |
23656 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L |
23657 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L |
23658 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L |
23659 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L |
23660 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L |
23661 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 |
23662 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 |
23663 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 |
23664 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 |
23665 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc |
23666 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 |
23667 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 |
23668 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 |
23669 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c |
23670 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL |
23671 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L |
23672 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L |
23673 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L |
23674 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L |
23675 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L |
23676 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L |
23677 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L |
23678 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 |
23679 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 |
23680 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 |
23681 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 |
23682 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc |
23683 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 |
23684 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 |
23685 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 |
23686 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c |
23687 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL |
23688 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L |
23689 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L |
23690 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L |
23691 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L |
23692 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L |
23693 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L |
23694 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L |
23695 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 |
23696 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 |
23697 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 |
23698 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 |
23699 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc |
23700 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 |
23701 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 |
23702 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 |
23703 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c |
23704 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL |
23705 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L |
23706 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L |
23707 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L |
23708 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L |
23709 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L |
23710 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L |
23711 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L |
23712 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 |
23713 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 |
23714 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 |
23715 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 |
23716 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc |
23717 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 |
23718 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 |
23719 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 |
23720 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c |
23721 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL |
23722 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L |
23723 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L |
23724 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L |
23725 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L |
23726 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L |
23727 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L |
23728 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L |
23729 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 |
23730 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 |
23731 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 |
23732 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 |
23733 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc |
23734 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 |
23735 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 |
23736 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 |
23737 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c |
23738 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL |
23739 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L |
23740 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L |
23741 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L |
23742 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L |
23743 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L |
23744 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L |
23745 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L |
23746 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 |
23747 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 |
23748 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 |
23749 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 |
23750 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc |
23751 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 |
23752 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 |
23753 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 |
23754 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c |
23755 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL |
23756 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L |
23757 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L |
23758 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L |
23759 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L |
23760 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L |
23761 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L |
23762 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L |
23763 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 |
23764 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 |
23765 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 |
23766 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 |
23767 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc |
23768 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 |
23769 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 |
23770 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 |
23771 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c |
23772 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL |
23773 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L |
23774 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L |
23775 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L |
23776 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L |
23777 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L |
23778 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L |
23779 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L |
23780 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 |
23781 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 |
23782 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 |
23783 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 |
23784 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc |
23785 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 |
23786 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 |
23787 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 |
23788 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c |
23789 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL |
23790 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L |
23791 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L |
23792 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L |
23793 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L |
23794 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L |
23795 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L |
23796 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L |
23797 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 |
23798 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 |
23799 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 |
23800 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 |
23801 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc |
23802 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 |
23803 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 |
23804 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 |
23805 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c |
23806 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL |
23807 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L |
23808 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L |
23809 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L |
23810 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L |
23811 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L |
23812 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L |
23813 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L |
23814 | //PA_SC_AA_MASK_X0Y0_X1Y0 |
23815 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 |
23816 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 |
23817 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL |
23818 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L |
23819 | //PA_SC_AA_MASK_X0Y1_X1Y1 |
23820 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 |
23821 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 |
23822 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL |
23823 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L |
23824 | //PA_SC_SHADER_CONTROL |
23825 | #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 |
23826 | #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2 |
23827 | #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3 |
23828 | #define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE__SHIFT 0x5 |
23829 | #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L |
23830 | #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L |
23831 | #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L |
23832 | #define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE_MASK 0x00000060L |
23833 | //PA_SC_BINNER_CNTL_0 |
23834 | #define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0 |
23835 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2 |
23836 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3 |
23837 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4 |
23838 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7 |
23839 | #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa |
23840 | #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd |
23841 | #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12 |
23842 | #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13 |
23843 | #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b |
23844 | #define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1c |
23845 | #define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE__SHIFT 0x1d |
23846 | #define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L |
23847 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L |
23848 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L |
23849 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L |
23850 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L |
23851 | #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L |
23852 | #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L |
23853 | #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L |
23854 | #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L |
23855 | #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L |
23856 | #define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK 0x10000000L |
23857 | #define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE_MASK 0x60000000L |
23858 | //PA_SC_BINNER_CNTL_1 |
23859 | #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0 |
23860 | #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10 |
23861 | #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL |
23862 | #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L |
23863 | //PA_SC_CONSERVATIVE_RASTERIZATION_CNTL |
23864 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0 |
23865 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1 |
23866 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5 |
23867 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6 |
23868 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa |
23869 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb |
23870 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc |
23871 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd |
23872 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe |
23873 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf |
23874 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10 |
23875 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12 |
23876 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13 |
23877 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14 |
23878 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15 |
23879 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16 |
23880 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17 |
23881 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18 |
23882 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT__SHIFT 0x19 |
23883 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT__SHIFT 0x1b |
23884 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L |
23885 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL |
23886 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L |
23887 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L |
23888 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L |
23889 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L |
23890 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L |
23891 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L |
23892 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L |
23893 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L |
23894 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L |
23895 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L |
23896 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L |
23897 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L |
23898 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L |
23899 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L |
23900 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L |
23901 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L |
23902 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT_MASK 0x06000000L |
23903 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT_MASK 0x18000000L |
23904 | //PA_SC_NGG_MODE_CNTL |
23905 | #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 |
23906 | #define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE__SHIFT 0x10 |
23907 | #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL |
23908 | #define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE_MASK 0x00FF0000L |
23909 | //VGT_VERTEX_REUSE_BLOCK_CNTL |
23910 | #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 |
23911 | #define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL |
23912 | //VGT_OUT_DEALLOC_CNTL |
23913 | #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 |
23914 | #define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL |
23915 | //CB_COLOR0_BASE |
23916 | #define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 |
23917 | #define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL |
23918 | //CB_COLOR0_PITCH |
23919 | #define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0 |
23920 | #define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
23921 | #define CB_COLOR0_PITCH__TILE_MAX_MASK 0x000007FFL |
23922 | #define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
23923 | //CB_COLOR0_SLICE |
23924 | #define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0 |
23925 | #define CB_COLOR0_SLICE__TILE_MAX_MASK 0x003FFFFFL |
23926 | //CB_COLOR0_VIEW |
23927 | #define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 |
23928 | #define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd |
23929 | #define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x1a |
23930 | #define CB_COLOR0_VIEW__SLICE_START_MASK 0x00001FFFL |
23931 | #define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x03FFE000L |
23932 | #define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x3C000000L |
23933 | //CB_COLOR0_INFO |
23934 | #define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 |
23935 | #define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 |
23936 | #define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7 |
23937 | #define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 |
23938 | #define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb |
23939 | #define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd |
23940 | #define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe |
23941 | #define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf |
23942 | #define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 |
23943 | #define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
23944 | #define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 |
23945 | #define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
23946 | #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
23947 | #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
23948 | #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
23949 | #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
23950 | #define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c |
23951 | #define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
23952 | #define CB_COLOR0_INFO__NBC_TILING__SHIFT 0x1f |
23953 | #define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L |
23954 | #define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL |
23955 | #define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x00000080L |
23956 | #define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L |
23957 | #define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L |
23958 | #define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L |
23959 | #define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L |
23960 | #define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L |
23961 | #define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L |
23962 | #define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
23963 | #define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L |
23964 | #define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
23965 | #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
23966 | #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
23967 | #define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
23968 | #define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
23969 | #define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L |
23970 | #define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
23971 | #define CB_COLOR0_INFO__NBC_TILING_MASK 0x80000000L |
23972 | //CB_COLOR0_ATTRIB |
23973 | #define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
23974 | #define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
23975 | #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
23976 | #define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
23977 | #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
23978 | #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
23979 | #define CB_COLOR0_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
23980 | #define CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
23981 | #define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
23982 | #define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
23983 | #define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
23984 | #define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
23985 | #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
23986 | #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
23987 | #define CB_COLOR0_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
23988 | #define CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
23989 | //CB_COLOR0_DCC_CONTROL |
23990 | #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
23991 | #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
23992 | #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
23993 | #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
23994 | #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
23995 | #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
23996 | #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
23997 | #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
23998 | #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
23999 | #define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
24000 | #define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
24001 | #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
24002 | #define CB_COLOR0_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
24003 | #define CB_COLOR0_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x16 |
24004 | #define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
24005 | #define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
24006 | #define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
24007 | #define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
24008 | #define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
24009 | #define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
24010 | #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
24011 | #define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
24012 | #define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
24013 | #define CB_COLOR0_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
24014 | #define CB_COLOR0_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
24015 | #define CB_COLOR0_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
24016 | #define CB_COLOR0_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
24017 | #define CB_COLOR0_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00400000L |
24018 | //CB_COLOR0_CMASK |
24019 | #define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 |
24020 | #define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
24021 | //CB_COLOR0_CMASK_SLICE |
24022 | #define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24023 | #define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
24024 | //CB_COLOR0_FMASK |
24025 | #define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 |
24026 | #define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
24027 | //CB_COLOR0_FMASK_SLICE |
24028 | #define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24029 | #define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24030 | //CB_COLOR0_CLEAR_WORD0 |
24031 | #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
24032 | #define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
24033 | //CB_COLOR0_CLEAR_WORD1 |
24034 | #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
24035 | #define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
24036 | //CB_COLOR0_DCC_BASE |
24037 | #define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 |
24038 | #define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24039 | //CB_COLOR1_BASE |
24040 | #define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 |
24041 | #define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24042 | //CB_COLOR1_PITCH |
24043 | #define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0 |
24044 | #define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
24045 | #define CB_COLOR1_PITCH__TILE_MAX_MASK 0x000007FFL |
24046 | #define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
24047 | //CB_COLOR1_SLICE |
24048 | #define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0 |
24049 | #define CB_COLOR1_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24050 | //CB_COLOR1_VIEW |
24051 | #define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 |
24052 | #define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd |
24053 | #define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x1a |
24054 | #define CB_COLOR1_VIEW__SLICE_START_MASK 0x00001FFFL |
24055 | #define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x03FFE000L |
24056 | #define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x3C000000L |
24057 | //CB_COLOR1_INFO |
24058 | #define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 |
24059 | #define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 |
24060 | #define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7 |
24061 | #define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 |
24062 | #define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb |
24063 | #define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd |
24064 | #define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe |
24065 | #define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf |
24066 | #define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 |
24067 | #define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
24068 | #define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 |
24069 | #define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
24070 | #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
24071 | #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
24072 | #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
24073 | #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
24074 | #define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c |
24075 | #define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
24076 | #define CB_COLOR1_INFO__NBC_TILING__SHIFT 0x1f |
24077 | #define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L |
24078 | #define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL |
24079 | #define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x00000080L |
24080 | #define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L |
24081 | #define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L |
24082 | #define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L |
24083 | #define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L |
24084 | #define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L |
24085 | #define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L |
24086 | #define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
24087 | #define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L |
24088 | #define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
24089 | #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
24090 | #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
24091 | #define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
24092 | #define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
24093 | #define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L |
24094 | #define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
24095 | #define CB_COLOR1_INFO__NBC_TILING_MASK 0x80000000L |
24096 | //CB_COLOR1_ATTRIB |
24097 | #define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
24098 | #define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
24099 | #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
24100 | #define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
24101 | #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
24102 | #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
24103 | #define CB_COLOR1_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
24104 | #define CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
24105 | #define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
24106 | #define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
24107 | #define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
24108 | #define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
24109 | #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
24110 | #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
24111 | #define CB_COLOR1_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
24112 | #define CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
24113 | //CB_COLOR1_DCC_CONTROL |
24114 | #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
24115 | #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
24116 | #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
24117 | #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
24118 | #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
24119 | #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
24120 | #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
24121 | #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
24122 | #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
24123 | #define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
24124 | #define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
24125 | #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
24126 | #define CB_COLOR1_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
24127 | #define CB_COLOR1_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x16 |
24128 | #define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
24129 | #define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
24130 | #define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
24131 | #define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
24132 | #define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
24133 | #define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
24134 | #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
24135 | #define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
24136 | #define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
24137 | #define CB_COLOR1_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
24138 | #define CB_COLOR1_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
24139 | #define CB_COLOR1_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
24140 | #define CB_COLOR1_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
24141 | #define CB_COLOR1_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00400000L |
24142 | //CB_COLOR1_CMASK |
24143 | #define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 |
24144 | #define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
24145 | //CB_COLOR1_CMASK_SLICE |
24146 | #define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24147 | #define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
24148 | //CB_COLOR1_FMASK |
24149 | #define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 |
24150 | #define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
24151 | //CB_COLOR1_FMASK_SLICE |
24152 | #define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24153 | #define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24154 | //CB_COLOR1_CLEAR_WORD0 |
24155 | #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
24156 | #define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
24157 | //CB_COLOR1_CLEAR_WORD1 |
24158 | #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
24159 | #define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
24160 | //CB_COLOR1_DCC_BASE |
24161 | #define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 |
24162 | #define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24163 | //CB_COLOR2_BASE |
24164 | #define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 |
24165 | #define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24166 | //CB_COLOR2_PITCH |
24167 | #define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0 |
24168 | #define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
24169 | #define CB_COLOR2_PITCH__TILE_MAX_MASK 0x000007FFL |
24170 | #define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
24171 | //CB_COLOR2_SLICE |
24172 | #define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0 |
24173 | #define CB_COLOR2_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24174 | //CB_COLOR2_VIEW |
24175 | #define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 |
24176 | #define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd |
24177 | #define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x1a |
24178 | #define CB_COLOR2_VIEW__SLICE_START_MASK 0x00001FFFL |
24179 | #define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x03FFE000L |
24180 | #define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x3C000000L |
24181 | //CB_COLOR2_INFO |
24182 | #define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 |
24183 | #define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 |
24184 | #define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7 |
24185 | #define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 |
24186 | #define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb |
24187 | #define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd |
24188 | #define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe |
24189 | #define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf |
24190 | #define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 |
24191 | #define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
24192 | #define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 |
24193 | #define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
24194 | #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
24195 | #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
24196 | #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
24197 | #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
24198 | #define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c |
24199 | #define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
24200 | #define CB_COLOR2_INFO__NBC_TILING__SHIFT 0x1f |
24201 | #define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L |
24202 | #define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL |
24203 | #define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x00000080L |
24204 | #define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L |
24205 | #define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L |
24206 | #define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L |
24207 | #define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L |
24208 | #define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L |
24209 | #define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L |
24210 | #define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
24211 | #define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L |
24212 | #define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
24213 | #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
24214 | #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
24215 | #define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
24216 | #define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
24217 | #define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L |
24218 | #define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
24219 | #define CB_COLOR2_INFO__NBC_TILING_MASK 0x80000000L |
24220 | //CB_COLOR2_ATTRIB |
24221 | #define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
24222 | #define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
24223 | #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
24224 | #define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
24225 | #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
24226 | #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
24227 | #define CB_COLOR2_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
24228 | #define CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
24229 | #define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
24230 | #define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
24231 | #define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
24232 | #define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
24233 | #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
24234 | #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
24235 | #define CB_COLOR2_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
24236 | #define CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
24237 | //CB_COLOR2_DCC_CONTROL |
24238 | #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
24239 | #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
24240 | #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
24241 | #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
24242 | #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
24243 | #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
24244 | #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
24245 | #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
24246 | #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
24247 | #define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
24248 | #define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
24249 | #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
24250 | #define CB_COLOR2_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
24251 | #define CB_COLOR2_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x16 |
24252 | #define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
24253 | #define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
24254 | #define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
24255 | #define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
24256 | #define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
24257 | #define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
24258 | #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
24259 | #define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
24260 | #define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
24261 | #define CB_COLOR2_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
24262 | #define CB_COLOR2_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
24263 | #define CB_COLOR2_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
24264 | #define CB_COLOR2_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
24265 | #define CB_COLOR2_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00400000L |
24266 | //CB_COLOR2_CMASK |
24267 | #define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 |
24268 | #define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
24269 | //CB_COLOR2_CMASK_SLICE |
24270 | #define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24271 | #define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
24272 | //CB_COLOR2_FMASK |
24273 | #define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 |
24274 | #define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
24275 | //CB_COLOR2_FMASK_SLICE |
24276 | #define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24277 | #define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24278 | //CB_COLOR2_CLEAR_WORD0 |
24279 | #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
24280 | #define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
24281 | //CB_COLOR2_CLEAR_WORD1 |
24282 | #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
24283 | #define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
24284 | //CB_COLOR2_DCC_BASE |
24285 | #define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 |
24286 | #define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24287 | //CB_COLOR3_BASE |
24288 | #define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 |
24289 | #define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24290 | //CB_COLOR3_PITCH |
24291 | #define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0 |
24292 | #define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
24293 | #define CB_COLOR3_PITCH__TILE_MAX_MASK 0x000007FFL |
24294 | #define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
24295 | //CB_COLOR3_SLICE |
24296 | #define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0 |
24297 | #define CB_COLOR3_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24298 | //CB_COLOR3_VIEW |
24299 | #define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 |
24300 | #define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd |
24301 | #define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x1a |
24302 | #define CB_COLOR3_VIEW__SLICE_START_MASK 0x00001FFFL |
24303 | #define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x03FFE000L |
24304 | #define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x3C000000L |
24305 | //CB_COLOR3_INFO |
24306 | #define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 |
24307 | #define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 |
24308 | #define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7 |
24309 | #define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 |
24310 | #define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb |
24311 | #define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd |
24312 | #define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe |
24313 | #define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf |
24314 | #define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 |
24315 | #define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
24316 | #define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 |
24317 | #define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
24318 | #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
24319 | #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
24320 | #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
24321 | #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
24322 | #define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c |
24323 | #define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
24324 | #define CB_COLOR3_INFO__NBC_TILING__SHIFT 0x1f |
24325 | #define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L |
24326 | #define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL |
24327 | #define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x00000080L |
24328 | #define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L |
24329 | #define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L |
24330 | #define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L |
24331 | #define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L |
24332 | #define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L |
24333 | #define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L |
24334 | #define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
24335 | #define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L |
24336 | #define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
24337 | #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
24338 | #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
24339 | #define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
24340 | #define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
24341 | #define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L |
24342 | #define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
24343 | #define CB_COLOR3_INFO__NBC_TILING_MASK 0x80000000L |
24344 | //CB_COLOR3_ATTRIB |
24345 | #define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
24346 | #define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
24347 | #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
24348 | #define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
24349 | #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
24350 | #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
24351 | #define CB_COLOR3_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
24352 | #define CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
24353 | #define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
24354 | #define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
24355 | #define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
24356 | #define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
24357 | #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
24358 | #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
24359 | #define CB_COLOR3_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
24360 | #define CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
24361 | //CB_COLOR3_DCC_CONTROL |
24362 | #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
24363 | #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
24364 | #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
24365 | #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
24366 | #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
24367 | #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
24368 | #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
24369 | #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
24370 | #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
24371 | #define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
24372 | #define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
24373 | #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
24374 | #define CB_COLOR3_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
24375 | #define CB_COLOR3_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x16 |
24376 | #define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
24377 | #define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
24378 | #define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
24379 | #define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
24380 | #define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
24381 | #define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
24382 | #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
24383 | #define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
24384 | #define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
24385 | #define CB_COLOR3_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
24386 | #define CB_COLOR3_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
24387 | #define CB_COLOR3_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
24388 | #define CB_COLOR3_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
24389 | #define CB_COLOR3_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00400000L |
24390 | //CB_COLOR3_CMASK |
24391 | #define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 |
24392 | #define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
24393 | //CB_COLOR3_CMASK_SLICE |
24394 | #define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24395 | #define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
24396 | //CB_COLOR3_FMASK |
24397 | #define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 |
24398 | #define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
24399 | //CB_COLOR3_FMASK_SLICE |
24400 | #define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24401 | #define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24402 | //CB_COLOR3_CLEAR_WORD0 |
24403 | #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
24404 | #define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
24405 | //CB_COLOR3_CLEAR_WORD1 |
24406 | #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
24407 | #define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
24408 | //CB_COLOR3_DCC_BASE |
24409 | #define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 |
24410 | #define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24411 | //CB_COLOR4_BASE |
24412 | #define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 |
24413 | #define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24414 | //CB_COLOR4_PITCH |
24415 | #define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0 |
24416 | #define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
24417 | #define CB_COLOR4_PITCH__TILE_MAX_MASK 0x000007FFL |
24418 | #define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
24419 | //CB_COLOR4_SLICE |
24420 | #define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0 |
24421 | #define CB_COLOR4_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24422 | //CB_COLOR4_VIEW |
24423 | #define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 |
24424 | #define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd |
24425 | #define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x1a |
24426 | #define CB_COLOR4_VIEW__SLICE_START_MASK 0x00001FFFL |
24427 | #define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x03FFE000L |
24428 | #define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x3C000000L |
24429 | //CB_COLOR4_INFO |
24430 | #define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 |
24431 | #define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 |
24432 | #define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7 |
24433 | #define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 |
24434 | #define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb |
24435 | #define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd |
24436 | #define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe |
24437 | #define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf |
24438 | #define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 |
24439 | #define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
24440 | #define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 |
24441 | #define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
24442 | #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
24443 | #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
24444 | #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
24445 | #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
24446 | #define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c |
24447 | #define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
24448 | #define CB_COLOR4_INFO__NBC_TILING__SHIFT 0x1f |
24449 | #define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L |
24450 | #define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL |
24451 | #define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x00000080L |
24452 | #define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L |
24453 | #define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L |
24454 | #define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L |
24455 | #define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L |
24456 | #define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L |
24457 | #define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L |
24458 | #define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
24459 | #define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L |
24460 | #define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
24461 | #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
24462 | #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
24463 | #define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
24464 | #define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
24465 | #define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L |
24466 | #define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
24467 | #define CB_COLOR4_INFO__NBC_TILING_MASK 0x80000000L |
24468 | //CB_COLOR4_ATTRIB |
24469 | #define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
24470 | #define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
24471 | #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
24472 | #define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
24473 | #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
24474 | #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
24475 | #define CB_COLOR4_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
24476 | #define CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
24477 | #define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
24478 | #define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
24479 | #define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
24480 | #define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
24481 | #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
24482 | #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
24483 | #define CB_COLOR4_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
24484 | #define CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
24485 | //CB_COLOR4_DCC_CONTROL |
24486 | #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
24487 | #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
24488 | #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
24489 | #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
24490 | #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
24491 | #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
24492 | #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
24493 | #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
24494 | #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
24495 | #define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
24496 | #define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
24497 | #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
24498 | #define CB_COLOR4_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
24499 | #define CB_COLOR4_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x16 |
24500 | #define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
24501 | #define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
24502 | #define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
24503 | #define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
24504 | #define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
24505 | #define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
24506 | #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
24507 | #define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
24508 | #define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
24509 | #define CB_COLOR4_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
24510 | #define CB_COLOR4_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
24511 | #define CB_COLOR4_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
24512 | #define CB_COLOR4_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
24513 | #define CB_COLOR4_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00400000L |
24514 | //CB_COLOR4_CMASK |
24515 | #define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 |
24516 | #define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
24517 | //CB_COLOR4_CMASK_SLICE |
24518 | #define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24519 | #define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
24520 | //CB_COLOR4_FMASK |
24521 | #define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 |
24522 | #define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
24523 | //CB_COLOR4_FMASK_SLICE |
24524 | #define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24525 | #define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24526 | //CB_COLOR4_CLEAR_WORD0 |
24527 | #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
24528 | #define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
24529 | //CB_COLOR4_CLEAR_WORD1 |
24530 | #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
24531 | #define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
24532 | //CB_COLOR4_DCC_BASE |
24533 | #define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 |
24534 | #define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24535 | //CB_COLOR5_BASE |
24536 | #define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 |
24537 | #define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24538 | //CB_COLOR5_PITCH |
24539 | #define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0 |
24540 | #define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
24541 | #define CB_COLOR5_PITCH__TILE_MAX_MASK 0x000007FFL |
24542 | #define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
24543 | //CB_COLOR5_SLICE |
24544 | #define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0 |
24545 | #define CB_COLOR5_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24546 | //CB_COLOR5_VIEW |
24547 | #define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 |
24548 | #define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd |
24549 | #define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x1a |
24550 | #define CB_COLOR5_VIEW__SLICE_START_MASK 0x00001FFFL |
24551 | #define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x03FFE000L |
24552 | #define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x3C000000L |
24553 | //CB_COLOR5_INFO |
24554 | #define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 |
24555 | #define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 |
24556 | #define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7 |
24557 | #define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 |
24558 | #define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb |
24559 | #define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd |
24560 | #define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe |
24561 | #define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf |
24562 | #define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 |
24563 | #define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
24564 | #define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 |
24565 | #define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
24566 | #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
24567 | #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
24568 | #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
24569 | #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
24570 | #define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c |
24571 | #define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
24572 | #define CB_COLOR5_INFO__NBC_TILING__SHIFT 0x1f |
24573 | #define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L |
24574 | #define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL |
24575 | #define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x00000080L |
24576 | #define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L |
24577 | #define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L |
24578 | #define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L |
24579 | #define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L |
24580 | #define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L |
24581 | #define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L |
24582 | #define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
24583 | #define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L |
24584 | #define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
24585 | #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
24586 | #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
24587 | #define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
24588 | #define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
24589 | #define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L |
24590 | #define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
24591 | #define CB_COLOR5_INFO__NBC_TILING_MASK 0x80000000L |
24592 | //CB_COLOR5_ATTRIB |
24593 | #define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
24594 | #define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
24595 | #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
24596 | #define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
24597 | #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
24598 | #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
24599 | #define CB_COLOR5_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
24600 | #define CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
24601 | #define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
24602 | #define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
24603 | #define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
24604 | #define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
24605 | #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
24606 | #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
24607 | #define CB_COLOR5_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
24608 | #define CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
24609 | //CB_COLOR5_DCC_CONTROL |
24610 | #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
24611 | #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
24612 | #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
24613 | #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
24614 | #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
24615 | #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
24616 | #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
24617 | #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
24618 | #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
24619 | #define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
24620 | #define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
24621 | #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
24622 | #define CB_COLOR5_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
24623 | #define CB_COLOR5_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x16 |
24624 | #define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
24625 | #define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
24626 | #define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
24627 | #define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
24628 | #define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
24629 | #define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
24630 | #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
24631 | #define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
24632 | #define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
24633 | #define CB_COLOR5_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
24634 | #define CB_COLOR5_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
24635 | #define CB_COLOR5_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
24636 | #define CB_COLOR5_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
24637 | #define CB_COLOR5_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00400000L |
24638 | //CB_COLOR5_CMASK |
24639 | #define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 |
24640 | #define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
24641 | //CB_COLOR5_CMASK_SLICE |
24642 | #define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24643 | #define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
24644 | //CB_COLOR5_FMASK |
24645 | #define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 |
24646 | #define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
24647 | //CB_COLOR5_FMASK_SLICE |
24648 | #define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24649 | #define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24650 | //CB_COLOR5_CLEAR_WORD0 |
24651 | #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
24652 | #define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
24653 | //CB_COLOR5_CLEAR_WORD1 |
24654 | #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
24655 | #define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
24656 | //CB_COLOR5_DCC_BASE |
24657 | #define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 |
24658 | #define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24659 | //CB_COLOR6_BASE |
24660 | #define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 |
24661 | #define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24662 | //CB_COLOR6_PITCH |
24663 | #define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0 |
24664 | #define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
24665 | #define CB_COLOR6_PITCH__TILE_MAX_MASK 0x000007FFL |
24666 | #define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
24667 | //CB_COLOR6_SLICE |
24668 | #define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0 |
24669 | #define CB_COLOR6_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24670 | //CB_COLOR6_VIEW |
24671 | #define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 |
24672 | #define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd |
24673 | #define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x1a |
24674 | #define CB_COLOR6_VIEW__SLICE_START_MASK 0x00001FFFL |
24675 | #define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x03FFE000L |
24676 | #define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x3C000000L |
24677 | //CB_COLOR6_INFO |
24678 | #define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 |
24679 | #define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 |
24680 | #define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7 |
24681 | #define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 |
24682 | #define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb |
24683 | #define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd |
24684 | #define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe |
24685 | #define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf |
24686 | #define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 |
24687 | #define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
24688 | #define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 |
24689 | #define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
24690 | #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
24691 | #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
24692 | #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
24693 | #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
24694 | #define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c |
24695 | #define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
24696 | #define CB_COLOR6_INFO__NBC_TILING__SHIFT 0x1f |
24697 | #define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L |
24698 | #define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL |
24699 | #define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x00000080L |
24700 | #define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L |
24701 | #define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L |
24702 | #define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L |
24703 | #define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L |
24704 | #define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L |
24705 | #define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L |
24706 | #define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
24707 | #define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L |
24708 | #define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
24709 | #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
24710 | #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
24711 | #define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
24712 | #define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
24713 | #define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L |
24714 | #define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
24715 | #define CB_COLOR6_INFO__NBC_TILING_MASK 0x80000000L |
24716 | //CB_COLOR6_ATTRIB |
24717 | #define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
24718 | #define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
24719 | #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
24720 | #define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
24721 | #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
24722 | #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
24723 | #define CB_COLOR6_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
24724 | #define CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
24725 | #define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
24726 | #define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
24727 | #define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
24728 | #define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
24729 | #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
24730 | #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
24731 | #define CB_COLOR6_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
24732 | #define CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
24733 | //CB_COLOR6_DCC_CONTROL |
24734 | #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
24735 | #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
24736 | #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
24737 | #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
24738 | #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
24739 | #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
24740 | #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
24741 | #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
24742 | #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
24743 | #define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
24744 | #define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
24745 | #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
24746 | #define CB_COLOR6_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
24747 | #define CB_COLOR6_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x16 |
24748 | #define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
24749 | #define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
24750 | #define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
24751 | #define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
24752 | #define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
24753 | #define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
24754 | #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
24755 | #define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
24756 | #define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
24757 | #define CB_COLOR6_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
24758 | #define CB_COLOR6_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
24759 | #define CB_COLOR6_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
24760 | #define CB_COLOR6_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
24761 | #define CB_COLOR6_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00400000L |
24762 | //CB_COLOR6_CMASK |
24763 | #define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 |
24764 | #define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
24765 | //CB_COLOR6_CMASK_SLICE |
24766 | #define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24767 | #define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
24768 | //CB_COLOR6_FMASK |
24769 | #define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 |
24770 | #define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
24771 | //CB_COLOR6_FMASK_SLICE |
24772 | #define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24773 | #define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24774 | //CB_COLOR6_CLEAR_WORD0 |
24775 | #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
24776 | #define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
24777 | //CB_COLOR6_CLEAR_WORD1 |
24778 | #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
24779 | #define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
24780 | //CB_COLOR6_DCC_BASE |
24781 | #define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 |
24782 | #define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24783 | //CB_COLOR7_BASE |
24784 | #define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 |
24785 | #define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24786 | //CB_COLOR7_PITCH |
24787 | #define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0 |
24788 | #define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14 |
24789 | #define CB_COLOR7_PITCH__TILE_MAX_MASK 0x000007FFL |
24790 | #define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7FF00000L |
24791 | //CB_COLOR7_SLICE |
24792 | #define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0 |
24793 | #define CB_COLOR7_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24794 | //CB_COLOR7_VIEW |
24795 | #define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 |
24796 | #define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd |
24797 | #define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x1a |
24798 | #define CB_COLOR7_VIEW__SLICE_START_MASK 0x00001FFFL |
24799 | #define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x03FFE000L |
24800 | #define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x3C000000L |
24801 | //CB_COLOR7_INFO |
24802 | #define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 |
24803 | #define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 |
24804 | #define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7 |
24805 | #define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 |
24806 | #define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb |
24807 | #define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd |
24808 | #define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe |
24809 | #define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf |
24810 | #define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 |
24811 | #define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
24812 | #define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 |
24813 | #define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13 |
24814 | #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
24815 | #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
24816 | #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a |
24817 | #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b |
24818 | #define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c |
24819 | #define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d |
24820 | #define CB_COLOR7_INFO__NBC_TILING__SHIFT 0x1f |
24821 | #define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L |
24822 | #define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL |
24823 | #define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x00000080L |
24824 | #define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L |
24825 | #define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L |
24826 | #define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L |
24827 | #define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L |
24828 | #define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L |
24829 | #define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L |
24830 | #define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
24831 | #define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L |
24832 | #define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x00080000L |
24833 | #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
24834 | #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
24835 | #define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L |
24836 | #define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L |
24837 | #define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L |
24838 | #define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L |
24839 | #define CB_COLOR7_INFO__NBC_TILING_MASK 0x80000000L |
24840 | //CB_COLOR7_ATTRIB |
24841 | #define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 |
24842 | #define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 |
24843 | #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa |
24844 | #define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc |
24845 | #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf |
24846 | #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 |
24847 | #define CB_COLOR7_ATTRIB__DISABLE_FMASK_NOFETCH_OPT__SHIFT 0x12 |
24848 | #define CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x13 |
24849 | #define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x0000001FL |
24850 | #define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x000003E0L |
24851 | #define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0x00000C00L |
24852 | #define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L |
24853 | #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L |
24854 | #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L |
24855 | #define CB_COLOR7_ATTRIB__DISABLE_FMASK_NOFETCH_OPT_MASK 0x00040000L |
24856 | #define CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00080000L |
24857 | //CB_COLOR7_DCC_CONTROL |
24858 | #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 |
24859 | #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 |
24860 | #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
24861 | #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
24862 | #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
24863 | #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
24864 | #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
24865 | #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa |
24866 | #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe |
24867 | #define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
24868 | #define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
24869 | #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0x14 |
24870 | #define CB_COLOR7_DCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
24871 | #define CB_COLOR7_DCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x16 |
24872 | #define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L |
24873 | #define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L |
24874 | #define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
24875 | #define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
24876 | #define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
24877 | #define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
24878 | #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
24879 | #define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L |
24880 | #define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L |
24881 | #define CB_COLOR7_DCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
24882 | #define CB_COLOR7_DCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
24883 | #define CB_COLOR7_DCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00100000L |
24884 | #define CB_COLOR7_DCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
24885 | #define CB_COLOR7_DCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00400000L |
24886 | //CB_COLOR7_CMASK |
24887 | #define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 |
24888 | #define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL |
24889 | //CB_COLOR7_CMASK_SLICE |
24890 | #define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24891 | #define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x00003FFFL |
24892 | //CB_COLOR7_FMASK |
24893 | #define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 |
24894 | #define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL |
24895 | //CB_COLOR7_FMASK_SLICE |
24896 | #define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0 |
24897 | #define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x003FFFFFL |
24898 | //CB_COLOR7_CLEAR_WORD0 |
24899 | #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 |
24900 | #define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL |
24901 | //CB_COLOR7_CLEAR_WORD1 |
24902 | #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 |
24903 | #define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL |
24904 | //CB_COLOR7_DCC_BASE |
24905 | #define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 |
24906 | #define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
24907 | //CB_COLOR0_BASE_EXT |
24908 | #define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0 |
24909 | #define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24910 | //CB_COLOR1_BASE_EXT |
24911 | #define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0 |
24912 | #define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24913 | //CB_COLOR2_BASE_EXT |
24914 | #define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0 |
24915 | #define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24916 | //CB_COLOR3_BASE_EXT |
24917 | #define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0 |
24918 | #define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24919 | //CB_COLOR4_BASE_EXT |
24920 | #define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0 |
24921 | #define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24922 | //CB_COLOR5_BASE_EXT |
24923 | #define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0 |
24924 | #define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24925 | //CB_COLOR6_BASE_EXT |
24926 | #define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0 |
24927 | #define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24928 | //CB_COLOR7_BASE_EXT |
24929 | #define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0 |
24930 | #define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24931 | //CB_COLOR0_CMASK_BASE_EXT |
24932 | #define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24933 | #define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24934 | //CB_COLOR1_CMASK_BASE_EXT |
24935 | #define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24936 | #define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24937 | //CB_COLOR2_CMASK_BASE_EXT |
24938 | #define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24939 | #define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24940 | //CB_COLOR3_CMASK_BASE_EXT |
24941 | #define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24942 | #define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24943 | //CB_COLOR4_CMASK_BASE_EXT |
24944 | #define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24945 | #define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24946 | //CB_COLOR5_CMASK_BASE_EXT |
24947 | #define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24948 | #define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24949 | //CB_COLOR6_CMASK_BASE_EXT |
24950 | #define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24951 | #define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24952 | //CB_COLOR7_CMASK_BASE_EXT |
24953 | #define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24954 | #define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24955 | //CB_COLOR0_FMASK_BASE_EXT |
24956 | #define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24957 | #define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24958 | //CB_COLOR1_FMASK_BASE_EXT |
24959 | #define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24960 | #define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24961 | //CB_COLOR2_FMASK_BASE_EXT |
24962 | #define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24963 | #define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24964 | //CB_COLOR3_FMASK_BASE_EXT |
24965 | #define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24966 | #define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24967 | //CB_COLOR4_FMASK_BASE_EXT |
24968 | #define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24969 | #define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24970 | //CB_COLOR5_FMASK_BASE_EXT |
24971 | #define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24972 | #define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24973 | //CB_COLOR6_FMASK_BASE_EXT |
24974 | #define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24975 | #define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24976 | //CB_COLOR7_FMASK_BASE_EXT |
24977 | #define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 |
24978 | #define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24979 | //CB_COLOR0_DCC_BASE_EXT |
24980 | #define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
24981 | #define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24982 | //CB_COLOR1_DCC_BASE_EXT |
24983 | #define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
24984 | #define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24985 | //CB_COLOR2_DCC_BASE_EXT |
24986 | #define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
24987 | #define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24988 | //CB_COLOR3_DCC_BASE_EXT |
24989 | #define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
24990 | #define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24991 | //CB_COLOR4_DCC_BASE_EXT |
24992 | #define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
24993 | #define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24994 | //CB_COLOR5_DCC_BASE_EXT |
24995 | #define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
24996 | #define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
24997 | //CB_COLOR6_DCC_BASE_EXT |
24998 | #define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
24999 | #define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
25000 | //CB_COLOR7_DCC_BASE_EXT |
25001 | #define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
25002 | #define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
25003 | //CB_COLOR0_ATTRIB2 |
25004 | #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
25005 | #define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
25006 | #define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c |
25007 | #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
25008 | #define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
25009 | #define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
25010 | //CB_COLOR1_ATTRIB2 |
25011 | #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
25012 | #define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
25013 | #define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c |
25014 | #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
25015 | #define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
25016 | #define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
25017 | //CB_COLOR2_ATTRIB2 |
25018 | #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
25019 | #define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
25020 | #define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c |
25021 | #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
25022 | #define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
25023 | #define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
25024 | //CB_COLOR3_ATTRIB2 |
25025 | #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
25026 | #define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
25027 | #define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c |
25028 | #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
25029 | #define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
25030 | #define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
25031 | //CB_COLOR4_ATTRIB2 |
25032 | #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
25033 | #define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
25034 | #define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c |
25035 | #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
25036 | #define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
25037 | #define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
25038 | //CB_COLOR5_ATTRIB2 |
25039 | #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
25040 | #define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
25041 | #define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c |
25042 | #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
25043 | #define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
25044 | #define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
25045 | //CB_COLOR6_ATTRIB2 |
25046 | #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
25047 | #define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
25048 | #define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c |
25049 | #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
25050 | #define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
25051 | #define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
25052 | //CB_COLOR7_ATTRIB2 |
25053 | #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
25054 | #define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
25055 | #define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c |
25056 | #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
25057 | #define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
25058 | #define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
25059 | //CB_COLOR0_ATTRIB3 |
25060 | #define CB_COLOR0_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
25061 | #define CB_COLOR0_ATTRIB3__META_LINEAR__SHIFT 0xd |
25062 | #define CB_COLOR0_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
25063 | #define CB_COLOR0_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
25064 | #define CB_COLOR0_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
25065 | #define CB_COLOR0_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
25066 | #define CB_COLOR0_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
25067 | #define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
25068 | #define CB_COLOR0_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f |
25069 | #define CB_COLOR0_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
25070 | #define CB_COLOR0_ATTRIB3__META_LINEAR_MASK 0x00002000L |
25071 | #define CB_COLOR0_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
25072 | #define CB_COLOR0_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
25073 | #define CB_COLOR0_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
25074 | #define CB_COLOR0_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
25075 | #define CB_COLOR0_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
25076 | #define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
25077 | #define CB_COLOR0_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L |
25078 | //CB_COLOR1_ATTRIB3 |
25079 | #define CB_COLOR1_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
25080 | #define CB_COLOR1_ATTRIB3__META_LINEAR__SHIFT 0xd |
25081 | #define CB_COLOR1_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
25082 | #define CB_COLOR1_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
25083 | #define CB_COLOR1_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
25084 | #define CB_COLOR1_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
25085 | #define CB_COLOR1_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
25086 | #define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
25087 | #define CB_COLOR1_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f |
25088 | #define CB_COLOR1_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
25089 | #define CB_COLOR1_ATTRIB3__META_LINEAR_MASK 0x00002000L |
25090 | #define CB_COLOR1_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
25091 | #define CB_COLOR1_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
25092 | #define CB_COLOR1_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
25093 | #define CB_COLOR1_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
25094 | #define CB_COLOR1_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
25095 | #define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
25096 | #define CB_COLOR1_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L |
25097 | //CB_COLOR2_ATTRIB3 |
25098 | #define CB_COLOR2_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
25099 | #define CB_COLOR2_ATTRIB3__META_LINEAR__SHIFT 0xd |
25100 | #define CB_COLOR2_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
25101 | #define CB_COLOR2_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
25102 | #define CB_COLOR2_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
25103 | #define CB_COLOR2_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
25104 | #define CB_COLOR2_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
25105 | #define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
25106 | #define CB_COLOR2_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f |
25107 | #define CB_COLOR2_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
25108 | #define CB_COLOR2_ATTRIB3__META_LINEAR_MASK 0x00002000L |
25109 | #define CB_COLOR2_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
25110 | #define CB_COLOR2_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
25111 | #define CB_COLOR2_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
25112 | #define CB_COLOR2_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
25113 | #define CB_COLOR2_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
25114 | #define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
25115 | #define CB_COLOR2_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L |
25116 | //CB_COLOR3_ATTRIB3 |
25117 | #define CB_COLOR3_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
25118 | #define CB_COLOR3_ATTRIB3__META_LINEAR__SHIFT 0xd |
25119 | #define CB_COLOR3_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
25120 | #define CB_COLOR3_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
25121 | #define CB_COLOR3_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
25122 | #define CB_COLOR3_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
25123 | #define CB_COLOR3_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
25124 | #define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
25125 | #define CB_COLOR3_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f |
25126 | #define CB_COLOR3_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
25127 | #define CB_COLOR3_ATTRIB3__META_LINEAR_MASK 0x00002000L |
25128 | #define CB_COLOR3_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
25129 | #define CB_COLOR3_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
25130 | #define CB_COLOR3_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
25131 | #define CB_COLOR3_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
25132 | #define CB_COLOR3_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
25133 | #define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
25134 | #define CB_COLOR3_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L |
25135 | //CB_COLOR4_ATTRIB3 |
25136 | #define CB_COLOR4_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
25137 | #define CB_COLOR4_ATTRIB3__META_LINEAR__SHIFT 0xd |
25138 | #define CB_COLOR4_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
25139 | #define CB_COLOR4_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
25140 | #define CB_COLOR4_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
25141 | #define CB_COLOR4_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
25142 | #define CB_COLOR4_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
25143 | #define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
25144 | #define CB_COLOR4_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f |
25145 | #define CB_COLOR4_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
25146 | #define CB_COLOR4_ATTRIB3__META_LINEAR_MASK 0x00002000L |
25147 | #define CB_COLOR4_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
25148 | #define CB_COLOR4_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
25149 | #define CB_COLOR4_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
25150 | #define CB_COLOR4_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
25151 | #define CB_COLOR4_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
25152 | #define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
25153 | #define CB_COLOR4_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L |
25154 | //CB_COLOR5_ATTRIB3 |
25155 | #define CB_COLOR5_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
25156 | #define CB_COLOR5_ATTRIB3__META_LINEAR__SHIFT 0xd |
25157 | #define CB_COLOR5_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
25158 | #define CB_COLOR5_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
25159 | #define CB_COLOR5_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
25160 | #define CB_COLOR5_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
25161 | #define CB_COLOR5_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
25162 | #define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
25163 | #define CB_COLOR5_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f |
25164 | #define CB_COLOR5_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
25165 | #define CB_COLOR5_ATTRIB3__META_LINEAR_MASK 0x00002000L |
25166 | #define CB_COLOR5_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
25167 | #define CB_COLOR5_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
25168 | #define CB_COLOR5_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
25169 | #define CB_COLOR5_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
25170 | #define CB_COLOR5_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
25171 | #define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
25172 | #define CB_COLOR5_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L |
25173 | //CB_COLOR6_ATTRIB3 |
25174 | #define CB_COLOR6_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
25175 | #define CB_COLOR6_ATTRIB3__META_LINEAR__SHIFT 0xd |
25176 | #define CB_COLOR6_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
25177 | #define CB_COLOR6_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
25178 | #define CB_COLOR6_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
25179 | #define CB_COLOR6_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
25180 | #define CB_COLOR6_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
25181 | #define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
25182 | #define CB_COLOR6_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f |
25183 | #define CB_COLOR6_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
25184 | #define CB_COLOR6_ATTRIB3__META_LINEAR_MASK 0x00002000L |
25185 | #define CB_COLOR6_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
25186 | #define CB_COLOR6_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
25187 | #define CB_COLOR6_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
25188 | #define CB_COLOR6_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
25189 | #define CB_COLOR6_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
25190 | #define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
25191 | #define CB_COLOR6_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L |
25192 | //CB_COLOR7_ATTRIB3 |
25193 | #define CB_COLOR7_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
25194 | #define CB_COLOR7_ATTRIB3__META_LINEAR__SHIFT 0xd |
25195 | #define CB_COLOR7_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
25196 | #define CB_COLOR7_ATTRIB3__FMASK_SW_MODE__SHIFT 0x13 |
25197 | #define CB_COLOR7_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
25198 | #define CB_COLOR7_ATTRIB3__CMASK_PIPE_ALIGNED__SHIFT 0x1a |
25199 | #define CB_COLOR7_ATTRIB3__RESOURCE_LEVEL__SHIFT 0x1b |
25200 | #define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
25201 | #define CB_COLOR7_ATTRIB3__VRS_RATE_HINT_ENABLE__SHIFT 0x1f |
25202 | #define CB_COLOR7_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
25203 | #define CB_COLOR7_ATTRIB3__META_LINEAR_MASK 0x00002000L |
25204 | #define CB_COLOR7_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
25205 | #define CB_COLOR7_ATTRIB3__FMASK_SW_MODE_MASK 0x00F80000L |
25206 | #define CB_COLOR7_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
25207 | #define CB_COLOR7_ATTRIB3__CMASK_PIPE_ALIGNED_MASK 0x04000000L |
25208 | #define CB_COLOR7_ATTRIB3__RESOURCE_LEVEL_MASK 0x38000000L |
25209 | #define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
25210 | #define CB_COLOR7_ATTRIB3__VRS_RATE_HINT_ENABLE_MASK 0x80000000L |
25211 | |
25212 | |
25213 | // addressBlock: gc_gfxudec |
25214 | //CP_EOP_DONE_ADDR_LO |
25215 | #define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 |
25216 | #define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
25217 | //CP_EOP_DONE_ADDR_HI |
25218 | #define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
25219 | #define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
25220 | //CP_EOP_DONE_DATA_LO |
25221 | #define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 |
25222 | #define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL |
25223 | //CP_EOP_DONE_DATA_HI |
25224 | #define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 |
25225 | #define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL |
25226 | //CP_EOP_LAST_FENCE_LO |
25227 | #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 |
25228 | #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL |
25229 | //CP_EOP_LAST_FENCE_HI |
25230 | #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 |
25231 | #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL |
25232 | //CP_STREAM_OUT_ADDR_LO |
25233 | #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 |
25234 | #define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL |
25235 | //CP_STREAM_OUT_ADDR_HI |
25236 | #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 |
25237 | #define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL |
25238 | //CP_NUM_PRIM_WRITTEN_COUNT0_LO |
25239 | #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 |
25240 | #define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL |
25241 | //CP_NUM_PRIM_WRITTEN_COUNT0_HI |
25242 | #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 |
25243 | #define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL |
25244 | //CP_NUM_PRIM_NEEDED_COUNT0_LO |
25245 | #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 |
25246 | #define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL |
25247 | //CP_NUM_PRIM_NEEDED_COUNT0_HI |
25248 | #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 |
25249 | #define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL |
25250 | //CP_NUM_PRIM_WRITTEN_COUNT1_LO |
25251 | #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 |
25252 | #define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL |
25253 | //CP_NUM_PRIM_WRITTEN_COUNT1_HI |
25254 | #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 |
25255 | #define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL |
25256 | //CP_NUM_PRIM_NEEDED_COUNT1_LO |
25257 | #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 |
25258 | #define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL |
25259 | //CP_NUM_PRIM_NEEDED_COUNT1_HI |
25260 | #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 |
25261 | #define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL |
25262 | //CP_NUM_PRIM_WRITTEN_COUNT2_LO |
25263 | #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 |
25264 | #define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL |
25265 | //CP_NUM_PRIM_WRITTEN_COUNT2_HI |
25266 | #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 |
25267 | #define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL |
25268 | //CP_NUM_PRIM_NEEDED_COUNT2_LO |
25269 | #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 |
25270 | #define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL |
25271 | //CP_NUM_PRIM_NEEDED_COUNT2_HI |
25272 | #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 |
25273 | #define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL |
25274 | //CP_NUM_PRIM_WRITTEN_COUNT3_LO |
25275 | #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 |
25276 | #define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL |
25277 | //CP_NUM_PRIM_WRITTEN_COUNT3_HI |
25278 | #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 |
25279 | #define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL |
25280 | //CP_NUM_PRIM_NEEDED_COUNT3_LO |
25281 | #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 |
25282 | #define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL |
25283 | //CP_NUM_PRIM_NEEDED_COUNT3_HI |
25284 | #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 |
25285 | #define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL |
25286 | //CP_PIPE_STATS_ADDR_LO |
25287 | #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 |
25288 | #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL |
25289 | //CP_PIPE_STATS_ADDR_HI |
25290 | #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 |
25291 | #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL |
25292 | //CP_VGT_IAVERT_COUNT_LO |
25293 | #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 |
25294 | #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL |
25295 | //CP_VGT_IAVERT_COUNT_HI |
25296 | #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 |
25297 | #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL |
25298 | //CP_VGT_IAPRIM_COUNT_LO |
25299 | #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 |
25300 | #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL |
25301 | //CP_VGT_IAPRIM_COUNT_HI |
25302 | #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 |
25303 | #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL |
25304 | //CP_VGT_GSPRIM_COUNT_LO |
25305 | #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 |
25306 | #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL |
25307 | //CP_VGT_GSPRIM_COUNT_HI |
25308 | #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 |
25309 | #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL |
25310 | //CP_VGT_VSINVOC_COUNT_LO |
25311 | #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 |
25312 | #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
25313 | //CP_VGT_VSINVOC_COUNT_HI |
25314 | #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 |
25315 | #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
25316 | //CP_VGT_GSINVOC_COUNT_LO |
25317 | #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 |
25318 | #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
25319 | //CP_VGT_GSINVOC_COUNT_HI |
25320 | #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 |
25321 | #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
25322 | //CP_VGT_HSINVOC_COUNT_LO |
25323 | #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 |
25324 | #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
25325 | //CP_VGT_HSINVOC_COUNT_HI |
25326 | #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 |
25327 | #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
25328 | //CP_VGT_DSINVOC_COUNT_LO |
25329 | #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 |
25330 | #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
25331 | //CP_VGT_DSINVOC_COUNT_HI |
25332 | #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 |
25333 | #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
25334 | //CP_PA_CINVOC_COUNT_LO |
25335 | #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 |
25336 | #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
25337 | //CP_PA_CINVOC_COUNT_HI |
25338 | #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 |
25339 | #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
25340 | //CP_PA_CPRIM_COUNT_LO |
25341 | #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 |
25342 | #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL |
25343 | //CP_PA_CPRIM_COUNT_HI |
25344 | #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 |
25345 | #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL |
25346 | //CP_SC_PSINVOC_COUNT0_LO |
25347 | #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 |
25348 | #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL |
25349 | //CP_SC_PSINVOC_COUNT0_HI |
25350 | #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 |
25351 | #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL |
25352 | //CP_SC_PSINVOC_COUNT1_LO |
25353 | #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 |
25354 | #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL |
25355 | //CP_SC_PSINVOC_COUNT1_HI |
25356 | #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 |
25357 | #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL |
25358 | //CP_VGT_CSINVOC_COUNT_LO |
25359 | #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 |
25360 | #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
25361 | //CP_VGT_CSINVOC_COUNT_HI |
25362 | #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 |
25363 | #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
25364 | //CP_PIPE_STATS_CONTROL |
25365 | #define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19 |
25366 | #define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x06000000L |
25367 | //CP_STREAM_OUT_CONTROL |
25368 | #define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19 |
25369 | #define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x06000000L |
25370 | //CP_STRMOUT_CNTL |
25371 | #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 |
25372 | #define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L |
25373 | //SCRATCH_REG0 |
25374 | #define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 |
25375 | #define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL |
25376 | //SCRATCH_REG1 |
25377 | #define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 |
25378 | #define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL |
25379 | //SCRATCH_REG2 |
25380 | #define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 |
25381 | #define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL |
25382 | //SCRATCH_REG3 |
25383 | #define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 |
25384 | #define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL |
25385 | //SCRATCH_REG4 |
25386 | #define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 |
25387 | #define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL |
25388 | //SCRATCH_REG5 |
25389 | #define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 |
25390 | #define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL |
25391 | //SCRATCH_REG6 |
25392 | #define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 |
25393 | #define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL |
25394 | //SCRATCH_REG7 |
25395 | #define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 |
25396 | #define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL |
25397 | //SCRATCH_REG_ATOMIC |
25398 | #define SCRATCH_REG_ATOMIC__IMMED__SHIFT 0x0 |
25399 | #define SCRATCH_REG_ATOMIC__ID__SHIFT 0x18 |
25400 | #define SCRATCH_REG_ATOMIC__reserved27__SHIFT 0x1b |
25401 | #define SCRATCH_REG_ATOMIC__OP__SHIFT 0x1c |
25402 | #define SCRATCH_REG_ATOMIC__reserved31__SHIFT 0x1f |
25403 | #define SCRATCH_REG_ATOMIC__IMMED_MASK 0x00FFFFFFL |
25404 | #define SCRATCH_REG_ATOMIC__ID_MASK 0x07000000L |
25405 | #define SCRATCH_REG_ATOMIC__reserved27_MASK 0x08000000L |
25406 | #define SCRATCH_REG_ATOMIC__OP_MASK 0x70000000L |
25407 | #define SCRATCH_REG_ATOMIC__reserved31_MASK 0x80000000L |
25408 | //SCRATCH_REG_CMPSWAP_ATOMIC |
25409 | #define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE__SHIFT 0x0 |
25410 | #define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE__SHIFT 0xc |
25411 | #define SCRATCH_REG_CMPSWAP_ATOMIC__ID__SHIFT 0x18 |
25412 | #define SCRATCH_REG_CMPSWAP_ATOMIC__reserved27__SHIFT 0x1b |
25413 | #define SCRATCH_REG_CMPSWAP_ATOMIC__OP__SHIFT 0x1c |
25414 | #define SCRATCH_REG_CMPSWAP_ATOMIC__reserved31__SHIFT 0x1f |
25415 | #define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE_MASK 0x00000FFFL |
25416 | #define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE_MASK 0x00FFF000L |
25417 | #define SCRATCH_REG_CMPSWAP_ATOMIC__ID_MASK 0x07000000L |
25418 | #define SCRATCH_REG_CMPSWAP_ATOMIC__reserved27_MASK 0x08000000L |
25419 | #define SCRATCH_REG_CMPSWAP_ATOMIC__OP_MASK 0x70000000L |
25420 | #define SCRATCH_REG_CMPSWAP_ATOMIC__reserved31_MASK 0x80000000L |
25421 | //CP_APPEND_DDID_CNT |
25422 | #define CP_APPEND_DDID_CNT__DATA__SHIFT 0x0 |
25423 | #define CP_APPEND_DDID_CNT__DATA_MASK 0x000000FFL |
25424 | //CP_APPEND_DATA_HI |
25425 | #define CP_APPEND_DATA_HI__DATA__SHIFT 0x0 |
25426 | #define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL |
25427 | //CP_APPEND_LAST_CS_FENCE_HI |
25428 | #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0 |
25429 | #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL |
25430 | //CP_APPEND_LAST_PS_FENCE_HI |
25431 | #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0 |
25432 | #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL |
25433 | //SCRATCH_UMSK |
25434 | #define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 |
25435 | #define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 |
25436 | #define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL |
25437 | #define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L |
25438 | //SCRATCH_ADDR |
25439 | #define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 |
25440 | #define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL |
25441 | //CP_PFP_ATOMIC_PREOP_LO |
25442 | #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 |
25443 | #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL |
25444 | //CP_PFP_ATOMIC_PREOP_HI |
25445 | #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 |
25446 | #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL |
25447 | //CP_PFP_GDS_ATOMIC0_PREOP_LO |
25448 | #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 |
25449 | #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
25450 | //CP_PFP_GDS_ATOMIC0_PREOP_HI |
25451 | #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 |
25452 | #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
25453 | //CP_PFP_GDS_ATOMIC1_PREOP_LO |
25454 | #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 |
25455 | #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
25456 | //CP_PFP_GDS_ATOMIC1_PREOP_HI |
25457 | #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 |
25458 | #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
25459 | //CP_APPEND_ADDR_LO |
25460 | #define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 |
25461 | #define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL |
25462 | //CP_APPEND_ADDR_HI |
25463 | #define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 |
25464 | #define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 |
25465 | #define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 |
25466 | #define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d |
25467 | #define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL |
25468 | #define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L |
25469 | #define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x06000000L |
25470 | #define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L |
25471 | //CP_APPEND_DATA |
25472 | #define CP_APPEND_DATA__DATA__SHIFT 0x0 |
25473 | #define CP_APPEND_DATA__DATA_MASK 0xFFFFFFFFL |
25474 | //CP_APPEND_DATA_LO |
25475 | #define CP_APPEND_DATA_LO__DATA__SHIFT 0x0 |
25476 | #define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL |
25477 | //CP_APPEND_LAST_CS_FENCE |
25478 | #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0 |
25479 | #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xFFFFFFFFL |
25480 | //CP_APPEND_LAST_CS_FENCE_LO |
25481 | #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0 |
25482 | #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL |
25483 | //CP_APPEND_LAST_PS_FENCE |
25484 | #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0 |
25485 | #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xFFFFFFFFL |
25486 | //CP_APPEND_LAST_PS_FENCE_LO |
25487 | #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0 |
25488 | #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL |
25489 | //CP_ATOMIC_PREOP_LO |
25490 | #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 |
25491 | #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL |
25492 | //CP_ME_ATOMIC_PREOP_LO |
25493 | #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 |
25494 | #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL |
25495 | //CP_ATOMIC_PREOP_HI |
25496 | #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 |
25497 | #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL |
25498 | //CP_ME_ATOMIC_PREOP_HI |
25499 | #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 |
25500 | #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL |
25501 | //CP_GDS_ATOMIC0_PREOP_LO |
25502 | #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 |
25503 | #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
25504 | //CP_ME_GDS_ATOMIC0_PREOP_LO |
25505 | #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 |
25506 | #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
25507 | //CP_GDS_ATOMIC0_PREOP_HI |
25508 | #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 |
25509 | #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
25510 | //CP_ME_GDS_ATOMIC0_PREOP_HI |
25511 | #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 |
25512 | #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
25513 | //CP_GDS_ATOMIC1_PREOP_LO |
25514 | #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 |
25515 | #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
25516 | //CP_ME_GDS_ATOMIC1_PREOP_LO |
25517 | #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 |
25518 | #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
25519 | //CP_GDS_ATOMIC1_PREOP_HI |
25520 | #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 |
25521 | #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
25522 | //CP_ME_GDS_ATOMIC1_PREOP_HI |
25523 | #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 |
25524 | #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
25525 | //CP_ME_MC_WADDR_LO |
25526 | #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 |
25527 | #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL |
25528 | //CP_ME_MC_WADDR_HI |
25529 | #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 |
25530 | #define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 |
25531 | #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL |
25532 | #define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00C00000L |
25533 | //CP_ME_MC_WDATA_LO |
25534 | #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 |
25535 | #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL |
25536 | //CP_ME_MC_WDATA_HI |
25537 | #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 |
25538 | #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL |
25539 | //CP_ME_MC_RADDR_LO |
25540 | #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 |
25541 | #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL |
25542 | //CP_ME_MC_RADDR_HI |
25543 | #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 |
25544 | #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 |
25545 | #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL |
25546 | #define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00C00000L |
25547 | //CP_SEM_WAIT_TIMER |
25548 | #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 |
25549 | #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL |
25550 | //CP_SIG_SEM_ADDR_LO |
25551 | #define CP_SIG_SEM_ADDR_LO__SEM_PRIV__SHIFT 0x0 |
25552 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 |
25553 | #define CP_SIG_SEM_ADDR_LO__SEM_PRIV_MASK 0x00000001L |
25554 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L |
25555 | //CP_SIG_SEM_ADDR_HI |
25556 | #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 |
25557 | #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 |
25558 | #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 |
25559 | #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 |
25560 | #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d |
25561 | #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL |
25562 | #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L |
25563 | #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L |
25564 | #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L |
25565 | #define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L |
25566 | //CP_WAIT_REG_MEM_TIMEOUT |
25567 | #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 |
25568 | #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL |
25569 | //CP_WAIT_SEM_ADDR_LO |
25570 | #define CP_WAIT_SEM_ADDR_LO__SEM_PRIV__SHIFT 0x0 |
25571 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 |
25572 | #define CP_WAIT_SEM_ADDR_LO__SEM_PRIV_MASK 0x00000001L |
25573 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L |
25574 | //CP_WAIT_SEM_ADDR_HI |
25575 | #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 |
25576 | #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 |
25577 | #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 |
25578 | #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 |
25579 | #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d |
25580 | #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL |
25581 | #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L |
25582 | #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L |
25583 | #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L |
25584 | #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L |
25585 | //CP_DMA_PFP_CONTROL |
25586 | #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa |
25587 | #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd |
25588 | #define CP_DMA_PFP_CONTROL__SRC_VOLATLE__SHIFT 0xf |
25589 | #define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 |
25590 | #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 |
25591 | #define CP_DMA_PFP_CONTROL__DST_VOLATLE__SHIFT 0x1b |
25592 | #define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d |
25593 | #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L |
25594 | #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00006000L |
25595 | #define CP_DMA_PFP_CONTROL__SRC_VOLATLE_MASK 0x00008000L |
25596 | #define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L |
25597 | #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x06000000L |
25598 | #define CP_DMA_PFP_CONTROL__DST_VOLATLE_MASK 0x08000000L |
25599 | #define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L |
25600 | //CP_DMA_ME_CONTROL |
25601 | #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa |
25602 | #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd |
25603 | #define CP_DMA_ME_CONTROL__SRC_VOLATLE__SHIFT 0xf |
25604 | #define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 |
25605 | #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 |
25606 | #define CP_DMA_ME_CONTROL__DST_VOLATLE__SHIFT 0x1b |
25607 | #define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d |
25608 | #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L |
25609 | #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00006000L |
25610 | #define CP_DMA_ME_CONTROL__SRC_VOLATLE_MASK 0x00008000L |
25611 | #define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L |
25612 | #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x06000000L |
25613 | #define CP_DMA_ME_CONTROL__DST_VOLATLE_MASK 0x08000000L |
25614 | #define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L |
25615 | //CP_COHER_BASE_HI |
25616 | #define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 |
25617 | #define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL |
25618 | //CP_COHER_START_DELAY |
25619 | #define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 |
25620 | #define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL |
25621 | //CP_COHER_CNTL |
25622 | #define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3 |
25623 | #define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4 |
25624 | #define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5 |
25625 | #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf |
25626 | #define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 |
25627 | #define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 |
25628 | #define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 |
25629 | #define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 |
25630 | #define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a |
25631 | #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b |
25632 | #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c |
25633 | #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d |
25634 | #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e |
25635 | #define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L |
25636 | #define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L |
25637 | #define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L |
25638 | #define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L |
25639 | #define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L |
25640 | #define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L |
25641 | #define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L |
25642 | #define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L |
25643 | #define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L |
25644 | #define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L |
25645 | #define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L |
25646 | #define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L |
25647 | #define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L |
25648 | //CP_COHER_SIZE |
25649 | #define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 |
25650 | #define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL |
25651 | //CP_COHER_BASE |
25652 | #define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 |
25653 | #define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL |
25654 | //CP_COHER_STATUS |
25655 | #define CP_COHER_STATUS__MEID__SHIFT 0x18 |
25656 | #define CP_COHER_STATUS__STATUS__SHIFT 0x1f |
25657 | #define CP_COHER_STATUS__MEID_MASK 0x03000000L |
25658 | #define CP_COHER_STATUS__STATUS_MASK 0x80000000L |
25659 | //CP_DMA_ME_SRC_ADDR |
25660 | #define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 |
25661 | #define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL |
25662 | //CP_DMA_ME_SRC_ADDR_HI |
25663 | #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 |
25664 | #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL |
25665 | //CP_DMA_ME_DST_ADDR |
25666 | #define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 |
25667 | #define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL |
25668 | //CP_DMA_ME_DST_ADDR_HI |
25669 | #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 |
25670 | #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL |
25671 | //CP_DMA_ME_COMMAND |
25672 | #define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 |
25673 | #define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a |
25674 | #define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b |
25675 | #define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c |
25676 | #define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d |
25677 | #define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e |
25678 | #define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f |
25679 | #define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL |
25680 | #define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L |
25681 | #define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L |
25682 | #define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L |
25683 | #define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L |
25684 | #define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L |
25685 | #define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L |
25686 | //CP_DMA_PFP_SRC_ADDR |
25687 | #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 |
25688 | #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL |
25689 | //CP_DMA_PFP_SRC_ADDR_HI |
25690 | #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 |
25691 | #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL |
25692 | //CP_DMA_PFP_DST_ADDR |
25693 | #define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 |
25694 | #define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL |
25695 | //CP_DMA_PFP_DST_ADDR_HI |
25696 | #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 |
25697 | #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL |
25698 | //CP_DMA_PFP_COMMAND |
25699 | #define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 |
25700 | #define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a |
25701 | #define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b |
25702 | #define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c |
25703 | #define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d |
25704 | #define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e |
25705 | #define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f |
25706 | #define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL |
25707 | #define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L |
25708 | #define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L |
25709 | #define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L |
25710 | #define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L |
25711 | #define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L |
25712 | #define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L |
25713 | //CP_DMA_CNTL |
25714 | #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0 |
25715 | #define CP_DMA_CNTL__WATCH_CONTROL__SHIFT 0x1 |
25716 | #define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 |
25717 | #define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 |
25718 | #define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c |
25719 | #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d |
25720 | #define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e |
25721 | #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L |
25722 | #define CP_DMA_CNTL__WATCH_CONTROL_MASK 0x00000002L |
25723 | #define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L |
25724 | #define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x01FF0000L |
25725 | #define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L |
25726 | #define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L |
25727 | #define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L |
25728 | //CP_DMA_READ_TAGS |
25729 | #define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 |
25730 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c |
25731 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL |
25732 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L |
25733 | //CP_COHER_SIZE_HI |
25734 | #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 |
25735 | #define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL |
25736 | //CP_PFP_IB_CONTROL |
25737 | #define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 |
25738 | #define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL |
25739 | //CP_PFP_LOAD_CONTROL |
25740 | #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 |
25741 | #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 |
25742 | #define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0xf |
25743 | #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 |
25744 | #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 |
25745 | #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L |
25746 | #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L |
25747 | #define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x00008000L |
25748 | #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L |
25749 | #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L |
25750 | //CP_SCRATCH_INDEX |
25751 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 |
25752 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f |
25753 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL |
25754 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L |
25755 | //CP_SCRATCH_DATA |
25756 | #define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 |
25757 | #define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL |
25758 | //CP_RB_OFFSET |
25759 | #define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 |
25760 | #define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL |
25761 | //CP_IB2_OFFSET |
25762 | #define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 |
25763 | #define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL |
25764 | //CP_IB2_PREAMBLE_BEGIN |
25765 | #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 |
25766 | #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL |
25767 | //CP_IB2_PREAMBLE_END |
25768 | #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 |
25769 | #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL |
25770 | //CP_CE_IB1_OFFSET |
25771 | #define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 |
25772 | #define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL |
25773 | //CP_CE_IB2_OFFSET |
25774 | #define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 |
25775 | #define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL |
25776 | //CP_CE_COUNTER |
25777 | #define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 |
25778 | #define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL |
25779 | //CP_DMA_ME_CMD_ADDR_LO |
25780 | #define CP_DMA_ME_CMD_ADDR_LO__RSVD__SHIFT 0x0 |
25781 | #define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 |
25782 | #define CP_DMA_ME_CMD_ADDR_LO__RSVD_MASK 0x00000003L |
25783 | #define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
25784 | //CP_DMA_ME_CMD_ADDR_HI |
25785 | #define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 |
25786 | #define CP_DMA_ME_CMD_ADDR_HI__RSVD__SHIFT 0x10 |
25787 | #define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
25788 | #define CP_DMA_ME_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L |
25789 | //CP_DMA_PFP_CMD_ADDR_LO |
25790 | #define CP_DMA_PFP_CMD_ADDR_LO__RSVD__SHIFT 0x0 |
25791 | #define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 |
25792 | #define CP_DMA_PFP_CMD_ADDR_LO__RSVD_MASK 0x00000003L |
25793 | #define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
25794 | //CP_DMA_PFP_CMD_ADDR_HI |
25795 | #define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 |
25796 | #define CP_DMA_PFP_CMD_ADDR_HI__RSVD__SHIFT 0x10 |
25797 | #define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
25798 | #define CP_DMA_PFP_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L |
25799 | //CP_APPEND_CMD_ADDR_LO |
25800 | #define CP_APPEND_CMD_ADDR_LO__RSVD__SHIFT 0x0 |
25801 | #define CP_APPEND_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 |
25802 | #define CP_APPEND_CMD_ADDR_LO__RSVD_MASK 0x00000003L |
25803 | #define CP_APPEND_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
25804 | //CP_APPEND_CMD_ADDR_HI |
25805 | #define CP_APPEND_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 |
25806 | #define CP_APPEND_CMD_ADDR_HI__RSVD__SHIFT 0x10 |
25807 | #define CP_APPEND_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
25808 | #define CP_APPEND_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L |
25809 | //UCONFIG_RESERVED_REG0 |
25810 | #define UCONFIG_RESERVED_REG0__DATA__SHIFT 0x0 |
25811 | #define UCONFIG_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL |
25812 | //UCONFIG_RESERVED_REG1 |
25813 | #define UCONFIG_RESERVED_REG1__DATA__SHIFT 0x0 |
25814 | #define UCONFIG_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL |
25815 | //CP_CE_ATOMIC_PREOP_LO |
25816 | #define CP_CE_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 |
25817 | #define CP_CE_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL |
25818 | //CP_CE_ATOMIC_PREOP_HI |
25819 | #define CP_CE_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 |
25820 | #define CP_CE_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL |
25821 | //CP_CE_GDS_ATOMIC0_PREOP_LO |
25822 | #define CP_CE_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 |
25823 | #define CP_CE_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
25824 | //CP_CE_GDS_ATOMIC0_PREOP_HI |
25825 | #define CP_CE_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 |
25826 | #define CP_CE_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
25827 | //CP_CE_GDS_ATOMIC1_PREOP_LO |
25828 | #define CP_CE_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 |
25829 | #define CP_CE_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
25830 | //CP_CE_GDS_ATOMIC1_PREOP_HI |
25831 | #define CP_CE_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 |
25832 | #define CP_CE_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
25833 | //CP_CE_INIT_CMD_BUFSZ |
25834 | #define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0 |
25835 | #define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL |
25836 | //CP_CE_IB1_CMD_BUFSZ |
25837 | #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 |
25838 | #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL |
25839 | //CP_CE_IB2_CMD_BUFSZ |
25840 | #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 |
25841 | #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL |
25842 | //CP_IB2_CMD_BUFSZ |
25843 | #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 |
25844 | #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL |
25845 | //CP_ST_CMD_BUFSZ |
25846 | #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0 |
25847 | #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL |
25848 | //CP_CE_INIT_BASE_LO |
25849 | #define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 |
25850 | #define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L |
25851 | //CP_CE_INIT_BASE_HI |
25852 | #define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 |
25853 | #define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL |
25854 | //CP_CE_INIT_BUFSZ |
25855 | #define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 |
25856 | #define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL |
25857 | //CP_CE_IB1_BASE_LO |
25858 | #define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 |
25859 | #define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL |
25860 | //CP_CE_IB1_BASE_HI |
25861 | #define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 |
25862 | #define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL |
25863 | //CP_CE_IB1_BUFSZ |
25864 | #define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 |
25865 | #define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL |
25866 | //CP_CE_IB2_BASE_LO |
25867 | #define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 |
25868 | #define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL |
25869 | //CP_CE_IB2_BASE_HI |
25870 | #define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 |
25871 | #define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL |
25872 | //CP_CE_IB2_BUFSZ |
25873 | #define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 |
25874 | #define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL |
25875 | //CP_IB1_BASE_LO |
25876 | #define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 |
25877 | #define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL |
25878 | //CP_IB1_BASE_HI |
25879 | #define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 |
25880 | #define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL |
25881 | //CP_IB1_BUFSZ |
25882 | #define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 |
25883 | #define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL |
25884 | //CP_IB2_BASE_LO |
25885 | #define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 |
25886 | #define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL |
25887 | //CP_IB2_BASE_HI |
25888 | #define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 |
25889 | #define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL |
25890 | //CP_IB2_BUFSZ |
25891 | #define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 |
25892 | #define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL |
25893 | //CP_ST_BASE_LO |
25894 | #define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 |
25895 | #define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL |
25896 | //CP_ST_BASE_HI |
25897 | #define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 |
25898 | #define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL |
25899 | //CP_ST_BUFSZ |
25900 | #define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 |
25901 | #define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL |
25902 | //CP_EOP_DONE_EVENT_CNTL |
25903 | #define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL__SHIFT 0xc |
25904 | #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19 |
25905 | #define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT 0x1b |
25906 | #define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c |
25907 | #define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL_MASK 0x00FFF000L |
25908 | #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x06000000L |
25909 | #define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK 0x08000000L |
25910 | #define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L |
25911 | //CP_EOP_DONE_DATA_CNTL |
25912 | #define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 |
25913 | #define CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID__SHIFT 0x14 |
25914 | #define CP_EOP_DONE_DATA_CNTL__ACTION_ID__SHIFT 0x16 |
25915 | #define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 |
25916 | #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d |
25917 | #define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L |
25918 | #define CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID_MASK 0x00300000L |
25919 | #define CP_EOP_DONE_DATA_CNTL__ACTION_ID_MASK 0x00C00000L |
25920 | #define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L |
25921 | #define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L |
25922 | //CP_EOP_DONE_CNTX_ID |
25923 | #define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 |
25924 | #define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL |
25925 | //CP_DB_BASE_LO |
25926 | #define CP_DB_BASE_LO__DB_BASE_LO__SHIFT 0x2 |
25927 | #define CP_DB_BASE_LO__DB_BASE_LO_MASK 0xFFFFFFFCL |
25928 | //CP_DB_BASE_HI |
25929 | #define CP_DB_BASE_HI__DB_BASE_HI__SHIFT 0x0 |
25930 | #define CP_DB_BASE_HI__DB_BASE_HI_MASK 0x0000FFFFL |
25931 | //CP_DB_BUFSZ |
25932 | #define CP_DB_BUFSZ__DB_BUFSZ__SHIFT 0x0 |
25933 | #define CP_DB_BUFSZ__DB_BUFSZ_MASK 0x000FFFFFL |
25934 | //CP_DB_CMD_BUFSZ |
25935 | #define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT 0x0 |
25936 | #define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK 0x000FFFFFL |
25937 | //CP_CE_DB_BASE_LO |
25938 | #define CP_CE_DB_BASE_LO__DB_BASE_LO__SHIFT 0x2 |
25939 | #define CP_CE_DB_BASE_LO__DB_BASE_LO_MASK 0xFFFFFFFCL |
25940 | //CP_CE_DB_BASE_HI |
25941 | #define CP_CE_DB_BASE_HI__DB_BASE_HI__SHIFT 0x0 |
25942 | #define CP_CE_DB_BASE_HI__DB_BASE_HI_MASK 0x0000FFFFL |
25943 | //CP_CE_DB_BUFSZ |
25944 | #define CP_CE_DB_BUFSZ__DB_BUFSZ__SHIFT 0x0 |
25945 | #define CP_CE_DB_BUFSZ__DB_BUFSZ_MASK 0x000FFFFFL |
25946 | //CP_CE_DB_CMD_BUFSZ |
25947 | #define CP_CE_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT 0x0 |
25948 | #define CP_CE_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK 0x000FFFFFL |
25949 | //CP_PFP_COMPLETION_STATUS |
25950 | #define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 |
25951 | #define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L |
25952 | //CP_CE_COMPLETION_STATUS |
25953 | #define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0 |
25954 | #define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L |
25955 | //CP_PRED_NOT_VISIBLE |
25956 | #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 |
25957 | #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L |
25958 | //CP_PFP_METADATA_BASE_ADDR |
25959 | #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 |
25960 | #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
25961 | //CP_PFP_METADATA_BASE_ADDR_HI |
25962 | #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
25963 | #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
25964 | //CP_CE_METADATA_BASE_ADDR |
25965 | #define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 |
25966 | #define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
25967 | //CP_CE_METADATA_BASE_ADDR_HI |
25968 | #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
25969 | #define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
25970 | //CP_DRAW_INDX_INDR_ADDR |
25971 | #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 |
25972 | #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
25973 | //CP_DRAW_INDX_INDR_ADDR_HI |
25974 | #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 |
25975 | #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
25976 | //CP_DISPATCH_INDR_ADDR |
25977 | #define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 |
25978 | #define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
25979 | //CP_DISPATCH_INDR_ADDR_HI |
25980 | #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 |
25981 | #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
25982 | //CP_INDEX_BASE_ADDR |
25983 | #define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 |
25984 | #define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
25985 | //CP_INDEX_BASE_ADDR_HI |
25986 | #define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
25987 | #define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
25988 | //CP_INDEX_TYPE |
25989 | #define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 |
25990 | #define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L |
25991 | //CP_GDS_BKUP_ADDR |
25992 | #define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 |
25993 | #define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
25994 | //CP_GDS_BKUP_ADDR_HI |
25995 | #define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 |
25996 | #define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
25997 | //CP_SAMPLE_STATUS |
25998 | #define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 |
25999 | #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 |
26000 | #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 |
26001 | #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 |
26002 | #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 |
26003 | #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 |
26004 | #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 |
26005 | #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 |
26006 | #define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L |
26007 | #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L |
26008 | #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L |
26009 | #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L |
26010 | #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L |
26011 | #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L |
26012 | #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L |
26013 | #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L |
26014 | //CP_ME_COHER_CNTL |
26015 | #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 |
26016 | #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 |
26017 | #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 |
26018 | #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 |
26019 | #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 |
26020 | #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 |
26021 | #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa |
26022 | #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb |
26023 | #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc |
26024 | #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd |
26025 | #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe |
26026 | #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 |
26027 | #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 |
26028 | #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L |
26029 | #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L |
26030 | #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L |
26031 | #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L |
26032 | #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L |
26033 | #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L |
26034 | #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L |
26035 | #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L |
26036 | #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L |
26037 | #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L |
26038 | #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L |
26039 | #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L |
26040 | #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L |
26041 | //CP_ME_COHER_SIZE |
26042 | #define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 |
26043 | #define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL |
26044 | //CP_ME_COHER_SIZE_HI |
26045 | #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 |
26046 | #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL |
26047 | //CP_ME_COHER_BASE |
26048 | #define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 |
26049 | #define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL |
26050 | //CP_ME_COHER_BASE_HI |
26051 | #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 |
26052 | #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL |
26053 | //CP_ME_COHER_STATUS |
26054 | #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 |
26055 | #define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f |
26056 | #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL |
26057 | #define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L |
26058 | //RLC_GPM_PERF_COUNT_0 |
26059 | #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 |
26060 | #define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 |
26061 | #define RLC_GPM_PERF_COUNT_0__SA_INDEX__SHIFT 0x8 |
26062 | #define RLC_GPM_PERF_COUNT_0__WGP_INDEX__SHIFT 0xc |
26063 | #define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 |
26064 | #define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 |
26065 | #define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 |
26066 | #define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 |
26067 | #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL |
26068 | #define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L |
26069 | #define RLC_GPM_PERF_COUNT_0__SA_INDEX_MASK 0x00000F00L |
26070 | #define RLC_GPM_PERF_COUNT_0__WGP_INDEX_MASK 0x0000F000L |
26071 | #define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L |
26072 | #define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L |
26073 | #define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L |
26074 | #define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L |
26075 | //RLC_GPM_PERF_COUNT_1 |
26076 | #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 |
26077 | #define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 |
26078 | #define RLC_GPM_PERF_COUNT_1__SA_INDEX__SHIFT 0x8 |
26079 | #define RLC_GPM_PERF_COUNT_1__WGP_INDEX__SHIFT 0xc |
26080 | #define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 |
26081 | #define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 |
26082 | #define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 |
26083 | #define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 |
26084 | #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL |
26085 | #define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L |
26086 | #define RLC_GPM_PERF_COUNT_1__SA_INDEX_MASK 0x00000F00L |
26087 | #define RLC_GPM_PERF_COUNT_1__WGP_INDEX_MASK 0x0000F000L |
26088 | #define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L |
26089 | #define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L |
26090 | #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L |
26091 | #define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L |
26092 | //GRBM_GFX_INDEX |
26093 | #define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 |
26094 | #define GRBM_GFX_INDEX__SA_INDEX__SHIFT 0x8 |
26095 | #define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 |
26096 | #define GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT 0x1d |
26097 | #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e |
26098 | #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f |
26099 | #define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL |
26100 | #define GRBM_GFX_INDEX__SA_INDEX_MASK 0x0000FF00L |
26101 | #define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L |
26102 | #define GRBM_GFX_INDEX__SA_BROADCAST_WRITES_MASK 0x20000000L |
26103 | #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L |
26104 | #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L |
26105 | //VGT_ESGS_RING_SIZE_UMD |
26106 | #define VGT_ESGS_RING_SIZE_UMD__MEM_SIZE__SHIFT 0x0 |
26107 | #define VGT_ESGS_RING_SIZE_UMD__MEM_SIZE_MASK 0xFFFFFFFFL |
26108 | //VGT_GSVS_RING_SIZE_UMD |
26109 | #define VGT_GSVS_RING_SIZE_UMD__MEM_SIZE__SHIFT 0x0 |
26110 | #define VGT_GSVS_RING_SIZE_UMD__MEM_SIZE_MASK 0xFFFFFFFFL |
26111 | //VGT_PRIMITIVE_TYPE |
26112 | #define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 |
26113 | #define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL |
26114 | //VGT_INDEX_TYPE |
26115 | #define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 |
26116 | #define VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT 0xe |
26117 | #define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L |
26118 | #define VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK 0x00004000L |
26119 | //VGT_STRMOUT_BUFFER_FILLED_SIZE_0 |
26120 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 |
26121 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL |
26122 | //VGT_STRMOUT_BUFFER_FILLED_SIZE_1 |
26123 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 |
26124 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL |
26125 | //VGT_STRMOUT_BUFFER_FILLED_SIZE_2 |
26126 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 |
26127 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL |
26128 | //VGT_STRMOUT_BUFFER_FILLED_SIZE_3 |
26129 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 |
26130 | #define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL |
26131 | //GE_MIN_VTX_INDX |
26132 | #define GE_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 |
26133 | #define GE_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL |
26134 | //GE_INDX_OFFSET |
26135 | #define GE_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 |
26136 | #define GE_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL |
26137 | //GE_MULTI_PRIM_IB_RESET_EN |
26138 | #define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 |
26139 | #define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 |
26140 | #define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L |
26141 | #define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L |
26142 | //VGT_NUM_INDICES |
26143 | #define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 |
26144 | #define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL |
26145 | //VGT_NUM_INSTANCES |
26146 | #define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 |
26147 | #define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL |
26148 | //VGT_TF_RING_SIZE_UMD |
26149 | #define VGT_TF_RING_SIZE_UMD__SIZE__SHIFT 0x0 |
26150 | #define VGT_TF_RING_SIZE_UMD__SIZE_MASK 0x0000FFFFL |
26151 | //VGT_HS_OFFCHIP_PARAM_UMD |
26152 | #define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_BUFFERING__SHIFT 0x0 |
26153 | #define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_GRANULARITY__SHIFT 0xa |
26154 | #define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_BUFFERING_MASK 0x000003FFL |
26155 | #define VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_GRANULARITY_MASK 0x00000C00L |
26156 | //VGT_TF_MEMORY_BASE_UMD |
26157 | #define VGT_TF_MEMORY_BASE_UMD__BASE__SHIFT 0x0 |
26158 | #define VGT_TF_MEMORY_BASE_UMD__BASE_MASK 0xFFFFFFFFL |
26159 | //GE_DMA_FIRST_INDEX |
26160 | #define GE_DMA_FIRST_INDEX__FIRST_INDEX__SHIFT 0x0 |
26161 | #define GE_DMA_FIRST_INDEX__FIRST_INDEX_MASK 0xFFFFFFFFL |
26162 | //WD_POS_BUF_BASE |
26163 | #define WD_POS_BUF_BASE__BASE__SHIFT 0x0 |
26164 | #define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL |
26165 | //WD_POS_BUF_BASE_HI |
26166 | #define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0 |
26167 | #define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL |
26168 | //WD_CNTL_SB_BUF_BASE |
26169 | #define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0 |
26170 | #define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL |
26171 | //WD_CNTL_SB_BUF_BASE_HI |
26172 | #define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0 |
26173 | #define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL |
26174 | //WD_INDEX_BUF_BASE |
26175 | #define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0 |
26176 | #define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL |
26177 | //WD_INDEX_BUF_BASE_HI |
26178 | #define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0 |
26179 | #define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL |
26180 | //IA_MULTI_VGT_PARAM_PIPED |
26181 | #define IA_MULTI_VGT_PARAM_PIPED__PRIMGROUP_SIZE__SHIFT 0x0 |
26182 | #define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_VS_WAVE_ON__SHIFT 0x10 |
26183 | #define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOP__SHIFT 0x11 |
26184 | #define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_ES_WAVE_ON__SHIFT 0x12 |
26185 | #define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOI__SHIFT 0x13 |
26186 | #define IA_MULTI_VGT_PARAM_PIPED__WD_SWITCH_ON_EOP__SHIFT 0x14 |
26187 | #define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_BASIC__SHIFT 0x15 |
26188 | #define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_ADV__SHIFT 0x16 |
26189 | #define IA_MULTI_VGT_PARAM_PIPED__HW_USE_ONLY__SHIFT 0x17 |
26190 | #define IA_MULTI_VGT_PARAM_PIPED__PRIMGROUP_SIZE_MASK 0x0000FFFFL |
26191 | #define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_VS_WAVE_ON_MASK 0x00010000L |
26192 | #define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOP_MASK 0x00020000L |
26193 | #define IA_MULTI_VGT_PARAM_PIPED__PARTIAL_ES_WAVE_ON_MASK 0x00040000L |
26194 | #define IA_MULTI_VGT_PARAM_PIPED__SWITCH_ON_EOI_MASK 0x00080000L |
26195 | #define IA_MULTI_VGT_PARAM_PIPED__WD_SWITCH_ON_EOP_MASK 0x00100000L |
26196 | #define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_BASIC_MASK 0x00200000L |
26197 | #define IA_MULTI_VGT_PARAM_PIPED__EN_INST_OPT_ADV_MASK 0x00400000L |
26198 | #define IA_MULTI_VGT_PARAM_PIPED__HW_USE_ONLY_MASK 0x00800000L |
26199 | //GE_MAX_VTX_INDX |
26200 | #define GE_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 |
26201 | #define GE_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL |
26202 | //VGT_INSTANCE_BASE_ID |
26203 | #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 |
26204 | #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL |
26205 | //GE_CNTL |
26206 | #define GE_CNTL__PRIM_GRP_SIZE__SHIFT 0x0 |
26207 | #define GE_CNTL__VERT_GRP_SIZE__SHIFT 0x9 |
26208 | #define GE_CNTL__BREAK_WAVE_AT_EOI__SHIFT 0x12 |
26209 | #define GE_CNTL__PACKET_TO_ONE_PA__SHIFT 0x13 |
26210 | #define GE_CNTL__PRIM_GRP_SIZE_MASK 0x000001FFL |
26211 | #define GE_CNTL__VERT_GRP_SIZE_MASK 0x0003FE00L |
26212 | #define GE_CNTL__BREAK_WAVE_AT_EOI_MASK 0x00040000L |
26213 | #define GE_CNTL__PACKET_TO_ONE_PA_MASK 0x00080000L |
26214 | //GE_USER_VGPR1 |
26215 | #define GE_USER_VGPR1__DATA__SHIFT 0x0 |
26216 | #define GE_USER_VGPR1__DATA_MASK 0xFFFFFFFFL |
26217 | //GE_USER_VGPR2 |
26218 | #define GE_USER_VGPR2__DATA__SHIFT 0x0 |
26219 | #define GE_USER_VGPR2__DATA_MASK 0xFFFFFFFFL |
26220 | //GE_USER_VGPR3 |
26221 | #define GE_USER_VGPR3__DATA__SHIFT 0x0 |
26222 | #define GE_USER_VGPR3__DATA_MASK 0xFFFFFFFFL |
26223 | //GE_STEREO_CNTL |
26224 | #define GE_STEREO_CNTL__RT_SLICE__SHIFT 0x0 |
26225 | #define GE_STEREO_CNTL__VIEWPORT__SHIFT 0x3 |
26226 | #define GE_STEREO_CNTL__EN_STEREO__SHIFT 0x8 |
26227 | #define GE_STEREO_CNTL__RT_SLICE_MASK 0x00000007L |
26228 | #define GE_STEREO_CNTL__VIEWPORT_MASK 0x00000078L |
26229 | #define GE_STEREO_CNTL__EN_STEREO_MASK 0x00000100L |
26230 | //GE_PC_ALLOC |
26231 | #define GE_PC_ALLOC__OVERSUB_EN__SHIFT 0x0 |
26232 | #define GE_PC_ALLOC__NUM_PC_LINES__SHIFT 0x1 |
26233 | #define GE_PC_ALLOC__OVERSUB_EN_MASK 0x00000001L |
26234 | #define GE_PC_ALLOC__NUM_PC_LINES_MASK 0x000007FEL |
26235 | //VGT_TF_MEMORY_BASE_HI_UMD |
26236 | #define VGT_TF_MEMORY_BASE_HI_UMD__BASE_HI__SHIFT 0x0 |
26237 | #define VGT_TF_MEMORY_BASE_HI_UMD__BASE_HI_MASK 0x000000FFL |
26238 | //GE_USER_VGPR_EN |
26239 | #define GE_USER_VGPR_EN__EN_USER_VGPR1__SHIFT 0x0 |
26240 | #define GE_USER_VGPR_EN__EN_USER_VGPR2__SHIFT 0x1 |
26241 | #define GE_USER_VGPR_EN__EN_USER_VGPR3__SHIFT 0x2 |
26242 | #define GE_USER_VGPR_EN__EN_USER_VGPR1_MASK 0x00000001L |
26243 | #define GE_USER_VGPR_EN__EN_USER_VGPR2_MASK 0x00000002L |
26244 | #define GE_USER_VGPR_EN__EN_USER_VGPR3_MASK 0x00000004L |
26245 | //PA_SU_LINE_STIPPLE_VALUE |
26246 | #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 |
26247 | #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL |
26248 | //PA_SC_LINE_STIPPLE_STATE |
26249 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 |
26250 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 |
26251 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL |
26252 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L |
26253 | //PA_SC_SCREEN_EXTENT_MIN_0 |
26254 | #define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 |
26255 | #define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 |
26256 | #define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL |
26257 | #define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L |
26258 | //PA_SC_SCREEN_EXTENT_MAX_0 |
26259 | #define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 |
26260 | #define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 |
26261 | #define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL |
26262 | #define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L |
26263 | //PA_SC_SCREEN_EXTENT_MIN_1 |
26264 | #define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 |
26265 | #define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 |
26266 | #define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL |
26267 | #define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L |
26268 | //PA_SC_SCREEN_EXTENT_MAX_1 |
26269 | #define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 |
26270 | #define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 |
26271 | #define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL |
26272 | #define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L |
26273 | //PA_SC_P3D_TRAP_SCREEN_HV_EN |
26274 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 |
26275 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 |
26276 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L |
26277 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L |
26278 | //PA_SC_P3D_TRAP_SCREEN_H |
26279 | #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 |
26280 | #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL |
26281 | //PA_SC_P3D_TRAP_SCREEN_V |
26282 | #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 |
26283 | #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL |
26284 | //PA_SC_P3D_TRAP_SCREEN_OCCURRENCE |
26285 | #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 |
26286 | #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL |
26287 | //PA_SC_P3D_TRAP_SCREEN_COUNT |
26288 | #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 |
26289 | #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL |
26290 | //PA_SC_HP3D_TRAP_SCREEN_HV_EN |
26291 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 |
26292 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 |
26293 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L |
26294 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L |
26295 | //PA_SC_HP3D_TRAP_SCREEN_H |
26296 | #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 |
26297 | #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL |
26298 | //PA_SC_HP3D_TRAP_SCREEN_V |
26299 | #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 |
26300 | #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL |
26301 | //PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE |
26302 | #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 |
26303 | #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL |
26304 | //PA_SC_HP3D_TRAP_SCREEN_COUNT |
26305 | #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 |
26306 | #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL |
26307 | //PA_SC_TRAP_SCREEN_HV_EN |
26308 | #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 |
26309 | #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 |
26310 | #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L |
26311 | #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L |
26312 | //PA_SC_TRAP_SCREEN_H |
26313 | #define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 |
26314 | #define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL |
26315 | //PA_SC_TRAP_SCREEN_V |
26316 | #define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 |
26317 | #define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL |
26318 | //PA_SC_TRAP_SCREEN_OCCURRENCE |
26319 | #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 |
26320 | #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL |
26321 | //PA_SC_TRAP_SCREEN_COUNT |
26322 | #define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 |
26323 | #define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL |
26324 | //SQ_THREAD_TRACE_USERDATA_0 |
26325 | #define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 |
26326 | #define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL |
26327 | //SQ_THREAD_TRACE_USERDATA_1 |
26328 | #define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 |
26329 | #define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL |
26330 | //SQ_THREAD_TRACE_USERDATA_2 |
26331 | #define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 |
26332 | #define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL |
26333 | //SQ_THREAD_TRACE_USERDATA_3 |
26334 | #define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 |
26335 | #define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL |
26336 | //SQ_THREAD_TRACE_USERDATA_4 |
26337 | #define SQ_THREAD_TRACE_USERDATA_4__DATA__SHIFT 0x0 |
26338 | #define SQ_THREAD_TRACE_USERDATA_4__DATA_MASK 0xFFFFFFFFL |
26339 | //SQ_THREAD_TRACE_USERDATA_5 |
26340 | #define SQ_THREAD_TRACE_USERDATA_5__DATA__SHIFT 0x0 |
26341 | #define SQ_THREAD_TRACE_USERDATA_5__DATA_MASK 0xFFFFFFFFL |
26342 | //SQ_THREAD_TRACE_USERDATA_6 |
26343 | #define SQ_THREAD_TRACE_USERDATA_6__DATA__SHIFT 0x0 |
26344 | #define SQ_THREAD_TRACE_USERDATA_6__DATA_MASK 0xFFFFFFFFL |
26345 | //SQ_THREAD_TRACE_USERDATA_7 |
26346 | #define SQ_THREAD_TRACE_USERDATA_7__DATA__SHIFT 0x0 |
26347 | #define SQ_THREAD_TRACE_USERDATA_7__DATA_MASK 0xFFFFFFFFL |
26348 | //SQC_CACHES |
26349 | #define SQC_CACHES__TARGET_INST__SHIFT 0x0 |
26350 | #define SQC_CACHES__TARGET_DATA__SHIFT 0x1 |
26351 | #define SQC_CACHES__INVALIDATE__SHIFT 0x2 |
26352 | #define SQC_CACHES__COMPLETE__SHIFT 0x10 |
26353 | #define SQC_CACHES__L2_WB_POLICY__SHIFT 0x11 |
26354 | #define SQC_CACHES__TARGET_INST_MASK 0x00000001L |
26355 | #define SQC_CACHES__TARGET_DATA_MASK 0x00000002L |
26356 | #define SQC_CACHES__INVALIDATE_MASK 0x00000004L |
26357 | #define SQC_CACHES__COMPLETE_MASK 0x00010000L |
26358 | #define SQC_CACHES__L2_WB_POLICY_MASK 0x00060000L |
26359 | //TA_CS_BC_BASE_ADDR |
26360 | #define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 |
26361 | #define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL |
26362 | //TA_CS_BC_BASE_ADDR_HI |
26363 | #define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 |
26364 | #define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL |
26365 | //DB_OCCLUSION_COUNT0_LOW |
26366 | #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 |
26367 | #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
26368 | //DB_OCCLUSION_COUNT0_HI |
26369 | #define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 |
26370 | #define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL |
26371 | //DB_OCCLUSION_COUNT1_LOW |
26372 | #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 |
26373 | #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
26374 | //DB_OCCLUSION_COUNT1_HI |
26375 | #define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 |
26376 | #define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL |
26377 | //DB_OCCLUSION_COUNT2_LOW |
26378 | #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 |
26379 | #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
26380 | //DB_OCCLUSION_COUNT2_HI |
26381 | #define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 |
26382 | #define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL |
26383 | //DB_OCCLUSION_COUNT3_LOW |
26384 | #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 |
26385 | #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
26386 | //DB_OCCLUSION_COUNT3_HI |
26387 | #define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 |
26388 | #define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL |
26389 | //DB_ZPASS_COUNT_LOW |
26390 | #define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 |
26391 | #define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
26392 | //DB_ZPASS_COUNT_HI |
26393 | #define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 |
26394 | #define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL |
26395 | //GDS_RD_ADDR |
26396 | #define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 |
26397 | #define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL |
26398 | //GDS_RD_DATA |
26399 | #define GDS_RD_DATA__READ_DATA__SHIFT 0x0 |
26400 | #define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL |
26401 | //GDS_RD_BURST_ADDR |
26402 | #define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 |
26403 | #define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL |
26404 | //GDS_RD_BURST_COUNT |
26405 | #define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 |
26406 | #define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL |
26407 | //GDS_RD_BURST_DATA |
26408 | #define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 |
26409 | #define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL |
26410 | //GDS_WR_ADDR |
26411 | #define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 |
26412 | #define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL |
26413 | //GDS_WR_DATA |
26414 | #define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 |
26415 | #define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL |
26416 | //GDS_WR_BURST_ADDR |
26417 | #define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 |
26418 | #define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL |
26419 | //GDS_WR_BURST_DATA |
26420 | #define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 |
26421 | #define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL |
26422 | //GDS_WRITE_COMPLETE |
26423 | #define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 |
26424 | #define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL |
26425 | //GDS_ATOM_CNTL |
26426 | #define GDS_ATOM_CNTL__AINC__SHIFT 0x0 |
26427 | #define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 |
26428 | #define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 |
26429 | #define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa |
26430 | #define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL |
26431 | #define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L |
26432 | #define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L |
26433 | #define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L |
26434 | //GDS_ATOM_COMPLETE |
26435 | #define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 |
26436 | #define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 |
26437 | #define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L |
26438 | #define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL |
26439 | //GDS_ATOM_BASE |
26440 | #define GDS_ATOM_BASE__BASE__SHIFT 0x0 |
26441 | #define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 |
26442 | #define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL |
26443 | #define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L |
26444 | //GDS_ATOM_SIZE |
26445 | #define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 |
26446 | #define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 |
26447 | #define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL |
26448 | #define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L |
26449 | //GDS_ATOM_OFFSET0 |
26450 | #define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 |
26451 | #define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 |
26452 | #define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL |
26453 | #define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L |
26454 | //GDS_ATOM_OFFSET1 |
26455 | #define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 |
26456 | #define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 |
26457 | #define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL |
26458 | #define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L |
26459 | //GDS_ATOM_DST |
26460 | #define GDS_ATOM_DST__DST__SHIFT 0x0 |
26461 | #define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL |
26462 | //GDS_ATOM_OP |
26463 | #define GDS_ATOM_OP__OP__SHIFT 0x0 |
26464 | #define GDS_ATOM_OP__UNUSED__SHIFT 0x8 |
26465 | #define GDS_ATOM_OP__OP_MASK 0x000000FFL |
26466 | #define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L |
26467 | //GDS_ATOM_SRC0 |
26468 | #define GDS_ATOM_SRC0__DATA__SHIFT 0x0 |
26469 | #define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL |
26470 | //GDS_ATOM_SRC0_U |
26471 | #define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 |
26472 | #define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL |
26473 | //GDS_ATOM_SRC1 |
26474 | #define GDS_ATOM_SRC1__DATA__SHIFT 0x0 |
26475 | #define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL |
26476 | //GDS_ATOM_SRC1_U |
26477 | #define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 |
26478 | #define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL |
26479 | //GDS_ATOM_READ0 |
26480 | #define GDS_ATOM_READ0__DATA__SHIFT 0x0 |
26481 | #define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL |
26482 | //GDS_ATOM_READ0_U |
26483 | #define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 |
26484 | #define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL |
26485 | //GDS_ATOM_READ1 |
26486 | #define GDS_ATOM_READ1__DATA__SHIFT 0x0 |
26487 | #define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL |
26488 | //GDS_ATOM_READ1_U |
26489 | #define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 |
26490 | #define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL |
26491 | //GDS_GWS_RESOURCE_CNTL |
26492 | #define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 |
26493 | #define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 |
26494 | #define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL |
26495 | #define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L |
26496 | //GDS_GWS_RESOURCE |
26497 | #define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 |
26498 | #define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 |
26499 | #define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd |
26500 | #define GDS_GWS_RESOURCE__DED__SHIFT 0xe |
26501 | #define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf |
26502 | #define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 |
26503 | #define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b |
26504 | #define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c |
26505 | #define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1d |
26506 | #define GDS_GWS_RESOURCE__HEAD_QUEUE1__SHIFT 0x1e |
26507 | #define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1f |
26508 | #define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L |
26509 | #define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL |
26510 | #define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L |
26511 | #define GDS_GWS_RESOURCE__DED_MASK 0x00004000L |
26512 | #define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L |
26513 | #define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x07FF0000L |
26514 | #define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x08000000L |
26515 | #define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000L |
26516 | #define GDS_GWS_RESOURCE__HALTED_MASK 0x20000000L |
26517 | #define GDS_GWS_RESOURCE__HEAD_QUEUE1_MASK 0x40000000L |
26518 | #define GDS_GWS_RESOURCE__UNUSED1_MASK 0x80000000L |
26519 | //GDS_GWS_RESOURCE_CNT |
26520 | #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 |
26521 | #define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 |
26522 | #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL |
26523 | #define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L |
26524 | //GDS_OA_CNTL |
26525 | #define GDS_OA_CNTL__INDEX__SHIFT 0x0 |
26526 | #define GDS_OA_CNTL__UNUSED__SHIFT 0x4 |
26527 | #define GDS_OA_CNTL__INDEX_MASK 0x0000000FL |
26528 | #define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L |
26529 | //GDS_OA_COUNTER |
26530 | #define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 |
26531 | #define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL |
26532 | //GDS_OA_ADDRESS |
26533 | #define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 |
26534 | #define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x10 |
26535 | #define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x14 |
26536 | #define GDS_OA_ADDRESS__UNUSED__SHIFT 0x18 |
26537 | #define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e |
26538 | #define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f |
26539 | #define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL |
26540 | #define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x000F0000L |
26541 | #define GDS_OA_ADDRESS__CRAWLER_MASK 0x00F00000L |
26542 | #define GDS_OA_ADDRESS__UNUSED_MASK 0x3F000000L |
26543 | #define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L |
26544 | #define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L |
26545 | //GDS_OA_INCDEC |
26546 | #define GDS_OA_INCDEC__VALUE__SHIFT 0x0 |
26547 | #define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f |
26548 | #define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL |
26549 | #define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L |
26550 | //GDS_OA_RING_SIZE |
26551 | #define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 |
26552 | #define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL |
26553 | //SPI_CONFIG_CNTL_REMAP |
26554 | #define SPI_CONFIG_CNTL_REMAP__RESERVED__SHIFT 0x0 |
26555 | #define SPI_CONFIG_CNTL_REMAP__RESERVED_MASK 0xFFFFFFFFL |
26556 | //SPI_CONFIG_CNTL_1_REMAP |
26557 | #define SPI_CONFIG_CNTL_1_REMAP__RESERVED__SHIFT 0x0 |
26558 | #define SPI_CONFIG_CNTL_1_REMAP__RESERVED_MASK 0xFFFFFFFFL |
26559 | //SPI_CONFIG_CNTL_2_REMAP |
26560 | #define SPI_CONFIG_CNTL_2_REMAP__RESERVED__SHIFT 0x0 |
26561 | #define SPI_CONFIG_CNTL_2_REMAP__RESERVED_MASK 0xFFFFFFFFL |
26562 | //SPI_WAVE_LIMIT_CNTL_REMAP |
26563 | #define SPI_WAVE_LIMIT_CNTL_REMAP__RESERVED__SHIFT 0x0 |
26564 | #define SPI_WAVE_LIMIT_CNTL_REMAP__RESERVED_MASK 0xFFFFFFFFL |
26565 | |
26566 | |
26567 | // addressBlock: gc_cprs64dec |
26568 | //CP_MES_PRGRM_CNTR_START |
26569 | #define CP_MES_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
26570 | #define CP_MES_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL |
26571 | //CP_MES_INTR_ROUTINE_START |
26572 | #define CP_MES_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
26573 | #define CP_MES_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL |
26574 | //CP_MES_MTVEC_LO |
26575 | #define CP_MES_MTVEC_LO__ADDR_LO__SHIFT 0x0 |
26576 | #define CP_MES_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL |
26577 | //CP_MES_MTVEC_HI |
26578 | #define CP_MES_MTVEC_HI__ADDR_LO__SHIFT 0x0 |
26579 | #define CP_MES_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL |
26580 | //CP_MES_CNTL |
26581 | #define CP_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT 0x4 |
26582 | #define CP_MES_CNTL__MES_PIPE0_RESET__SHIFT 0x10 |
26583 | #define CP_MES_CNTL__MES_PIPE1_RESET__SHIFT 0x11 |
26584 | #define CP_MES_CNTL__MES_PIPE2_RESET__SHIFT 0x12 |
26585 | #define CP_MES_CNTL__MES_PIPE3_RESET__SHIFT 0x13 |
26586 | #define CP_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT 0x1a |
26587 | #define CP_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT 0x1b |
26588 | #define CP_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT 0x1c |
26589 | #define CP_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT 0x1d |
26590 | #define CP_MES_CNTL__MES_HALT__SHIFT 0x1e |
26591 | #define CP_MES_CNTL__MES_STEP__SHIFT 0x1f |
26592 | #define CP_MES_CNTL__MES_INVALIDATE_ICACHE_MASK 0x00000010L |
26593 | #define CP_MES_CNTL__MES_PIPE0_RESET_MASK 0x00010000L |
26594 | #define CP_MES_CNTL__MES_PIPE1_RESET_MASK 0x00020000L |
26595 | #define CP_MES_CNTL__MES_PIPE2_RESET_MASK 0x00040000L |
26596 | #define CP_MES_CNTL__MES_PIPE3_RESET_MASK 0x00080000L |
26597 | #define CP_MES_CNTL__MES_PIPE0_ACTIVE_MASK 0x04000000L |
26598 | #define CP_MES_CNTL__MES_PIPE1_ACTIVE_MASK 0x08000000L |
26599 | #define CP_MES_CNTL__MES_PIPE2_ACTIVE_MASK 0x10000000L |
26600 | #define CP_MES_CNTL__MES_PIPE3_ACTIVE_MASK 0x20000000L |
26601 | #define CP_MES_CNTL__MES_HALT_MASK 0x40000000L |
26602 | #define CP_MES_CNTL__MES_STEP_MASK 0x80000000L |
26603 | //CP_MES_PIPE_PRIORITY_CNTS |
26604 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
26605 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
26606 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
26607 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
26608 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
26609 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
26610 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
26611 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
26612 | //CP_MES_PIPE0_PRIORITY |
26613 | #define CP_MES_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
26614 | #define CP_MES_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
26615 | //CP_MES_PIPE1_PRIORITY |
26616 | #define CP_MES_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
26617 | #define CP_MES_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
26618 | //CP_MES_PIPE2_PRIORITY |
26619 | #define CP_MES_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
26620 | #define CP_MES_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
26621 | //CP_MES_PIPE3_PRIORITY |
26622 | #define CP_MES_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 |
26623 | #define CP_MES_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L |
26624 | //CP_MES_HEADER_DUMP |
26625 | #define 0x0 |
26626 | #define 0xFFFFFFFFL |
26627 | //CP_MES_MIE_LO |
26628 | #define CP_MES_MIE_LO__MES_INT__SHIFT 0x0 |
26629 | #define CP_MES_MIE_LO__MES_INT_MASK 0xFFFFFFFFL |
26630 | //CP_MES_MIE_HI |
26631 | #define CP_MES_MIE_HI__MES_INT__SHIFT 0x0 |
26632 | #define CP_MES_MIE_HI__MES_INT_MASK 0xFFFFFFFFL |
26633 | //CP_MES_INTERRUPT |
26634 | #define CP_MES_INTERRUPT__MES_INT__SHIFT 0x0 |
26635 | #define CP_MES_INTERRUPT__MES_INT_MASK 0xFFFFFFFFL |
26636 | //CP_MES_SCRATCH_INDEX |
26637 | #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 |
26638 | #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f |
26639 | #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL |
26640 | #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L |
26641 | //CP_MES_SCRATCH_DATA |
26642 | #define CP_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 |
26643 | #define CP_MES_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL |
26644 | //CP_MES_INSTR_PNTR |
26645 | #define CP_MES_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
26646 | #define CP_MES_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL |
26647 | //CP_MES_MSCRATCH_HI |
26648 | #define CP_MES_MSCRATCH_HI__DATA__SHIFT 0x0 |
26649 | #define CP_MES_MSCRATCH_HI__DATA_MASK 0xFFFFFFFFL |
26650 | //CP_MES_MSCRATCH_LO |
26651 | #define CP_MES_MSCRATCH_LO__DATA__SHIFT 0x0 |
26652 | #define CP_MES_MSCRATCH_LO__DATA_MASK 0xFFFFFFFFL |
26653 | //CP_MES_MSTATUS_LO |
26654 | #define CP_MES_MSTATUS_LO__STATUS_LO__SHIFT 0x0 |
26655 | #define CP_MES_MSTATUS_LO__STATUS_LO_MASK 0xFFFFFFFFL |
26656 | //CP_MES_MSTATUS_HI |
26657 | #define CP_MES_MSTATUS_HI__STATUS_HI__SHIFT 0x0 |
26658 | #define CP_MES_MSTATUS_HI__STATUS_HI_MASK 0xFFFFFFFFL |
26659 | //CP_MES_MEPC_LO |
26660 | #define CP_MES_MEPC_LO__MEPC_LO__SHIFT 0x0 |
26661 | #define CP_MES_MEPC_LO__MEPC_LO_MASK 0xFFFFFFFFL |
26662 | //CP_MES_MEPC_HI |
26663 | #define CP_MES_MEPC_HI__MEPC_HI__SHIFT 0x0 |
26664 | #define CP_MES_MEPC_HI__MEPC_HI_MASK 0xFFFFFFFFL |
26665 | //CP_MES_MCAUSE_LO |
26666 | #define CP_MES_MCAUSE_LO__CAUSE_LO__SHIFT 0x0 |
26667 | #define CP_MES_MCAUSE_LO__CAUSE_LO_MASK 0xFFFFFFFFL |
26668 | //CP_MES_MCAUSE_HI |
26669 | #define CP_MES_MCAUSE_HI__CAUSE_HI__SHIFT 0x0 |
26670 | #define CP_MES_MCAUSE_HI__CAUSE_HI_MASK 0xFFFFFFFFL |
26671 | //CP_MES_MBADADDR_LO |
26672 | #define CP_MES_MBADADDR_LO__ADDR_LO__SHIFT 0x0 |
26673 | #define CP_MES_MBADADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL |
26674 | //CP_MES_MBADADDR_HI |
26675 | #define CP_MES_MBADADDR_HI__ADDR_HI__SHIFT 0x0 |
26676 | #define CP_MES_MBADADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL |
26677 | //CP_MES_MIP_LO |
26678 | #define CP_MES_MIP_LO__MIP_LO__SHIFT 0x0 |
26679 | #define CP_MES_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL |
26680 | //CP_MES_MIP_HI |
26681 | #define CP_MES_MIP_HI__MIP_HI__SHIFT 0x0 |
26682 | #define CP_MES_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL |
26683 | //CP_MES_IC_OP_CNTL |
26684 | #define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
26685 | #define CP_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
26686 | #define CP_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
26687 | #define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
26688 | #define CP_MES_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
26689 | #define CP_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
26690 | //CP_MES_MCYCLE_LO |
26691 | #define CP_MES_MCYCLE_LO__CYCLE_LO__SHIFT 0x0 |
26692 | #define CP_MES_MCYCLE_LO__CYCLE_LO_MASK 0xFFFFFFFFL |
26693 | //CP_MES_MCYCLE_HI |
26694 | #define CP_MES_MCYCLE_HI__CYCLE_HI__SHIFT 0x0 |
26695 | #define CP_MES_MCYCLE_HI__CYCLE_HI_MASK 0xFFFFFFFFL |
26696 | //CP_MES_MTIME_LO |
26697 | #define CP_MES_MTIME_LO__TIME_LO__SHIFT 0x0 |
26698 | #define CP_MES_MTIME_LO__TIME_LO_MASK 0xFFFFFFFFL |
26699 | //CP_MES_MTIME_HI |
26700 | #define CP_MES_MTIME_HI__TIME_HI__SHIFT 0x0 |
26701 | #define CP_MES_MTIME_HI__TIME_HI_MASK 0xFFFFFFFFL |
26702 | //CP_MES_MINSTRET_LO |
26703 | #define CP_MES_MINSTRET_LO__INSTRET_LO__SHIFT 0x0 |
26704 | #define CP_MES_MINSTRET_LO__INSTRET_LO_MASK 0xFFFFFFFFL |
26705 | //CP_MES_MINSTRET_HI |
26706 | #define CP_MES_MINSTRET_HI__INSTRET_HI__SHIFT 0x0 |
26707 | #define CP_MES_MINSTRET_HI__INSTRET_HI_MASK 0xFFFFFFFFL |
26708 | //CP_MES_MISA_LO |
26709 | #define CP_MES_MISA_LO__MISA_LO__SHIFT 0x0 |
26710 | #define CP_MES_MISA_LO__MISA_LO_MASK 0xFFFFFFFFL |
26711 | //CP_MES_MISA_HI |
26712 | #define CP_MES_MISA_HI__MISA_HI__SHIFT 0x0 |
26713 | #define CP_MES_MISA_HI__MISA_HI_MASK 0xFFFFFFFFL |
26714 | //CP_MES_MVENDORID_LO |
26715 | #define CP_MES_MVENDORID_LO__MVENDORID_LO__SHIFT 0x0 |
26716 | #define CP_MES_MVENDORID_LO__MVENDORID_LO_MASK 0xFFFFFFFFL |
26717 | //CP_MES_MVENDORID_HI |
26718 | #define CP_MES_MVENDORID_HI__MVENDORID_HI__SHIFT 0x0 |
26719 | #define CP_MES_MVENDORID_HI__MVENDORID_HI_MASK 0xFFFFFFFFL |
26720 | //CP_MES_MARCHID_LO |
26721 | #define CP_MES_MARCHID_LO__MARCHID_LO__SHIFT 0x0 |
26722 | #define CP_MES_MARCHID_LO__MARCHID_LO_MASK 0xFFFFFFFFL |
26723 | //CP_MES_MARCHID_HI |
26724 | #define CP_MES_MARCHID_HI__MARCHID_HI__SHIFT 0x0 |
26725 | #define CP_MES_MARCHID_HI__MARCHID_HI_MASK 0xFFFFFFFFL |
26726 | //CP_MES_MIMPID_LO |
26727 | #define CP_MES_MIMPID_LO__MIMPID_LO__SHIFT 0x0 |
26728 | #define CP_MES_MIMPID_LO__MIMPID_LO_MASK 0xFFFFFFFFL |
26729 | //CP_MES_MIMPID_HI |
26730 | #define CP_MES_MIMPID_HI__MIMPID_HI__SHIFT 0x0 |
26731 | #define CP_MES_MIMPID_HI__MIMPID_HI_MASK 0xFFFFFFFFL |
26732 | //CP_MES_MHARTID_LO |
26733 | #define CP_MES_MHARTID_LO__MHARTID_LO__SHIFT 0x0 |
26734 | #define CP_MES_MHARTID_LO__MHARTID_LO_MASK 0xFFFFFFFFL |
26735 | //CP_MES_MHARTID_HI |
26736 | #define CP_MES_MHARTID_HI__MHARTID_HI__SHIFT 0x0 |
26737 | #define CP_MES_MHARTID_HI__MHARTID_HI_MASK 0xFFFFFFFFL |
26738 | //CP_MES_DC_BASE_CNTL |
26739 | #define CP_MES_DC_BASE_CNTL__VMID__SHIFT 0x0 |
26740 | #define CP_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
26741 | #define CP_MES_DC_BASE_CNTL__VMID_MASK 0x0000000FL |
26742 | #define CP_MES_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
26743 | //CP_MES_DC_OP_CNTL |
26744 | #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 |
26745 | #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 |
26746 | #define CP_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 |
26747 | #define CP_MES_DC_OP_CNTL__BYPASS_UNCACHED__SHIFT 0x3 |
26748 | #define CP_MES_DC_OP_CNTL__PRIME_DCACHE__SHIFT 0x4 |
26749 | #define CP_MES_DC_OP_CNTL__DCACHE_PRIMED__SHIFT 0x5 |
26750 | #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L |
26751 | #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L |
26752 | #define CP_MES_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L |
26753 | #define CP_MES_DC_OP_CNTL__BYPASS_UNCACHED_MASK 0x00000008L |
26754 | #define CP_MES_DC_OP_CNTL__PRIME_DCACHE_MASK 0x00000010L |
26755 | #define CP_MES_DC_OP_CNTL__DCACHE_PRIMED_MASK 0x00000020L |
26756 | //CP_MES_MTIMECMP_LO |
26757 | #define CP_MES_MTIMECMP_LO__TIME_LO__SHIFT 0x0 |
26758 | #define CP_MES_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL |
26759 | //CP_MES_MTIMECMP_HI |
26760 | #define CP_MES_MTIMECMP_HI__TIME_HI__SHIFT 0x0 |
26761 | #define CP_MES_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL |
26762 | //CP_MES_PROCESS_QUANTUM_PIPE0 |
26763 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION__SHIFT 0x0 |
26764 | #define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED__SHIFT 0x1c |
26765 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE__SHIFT 0x1d |
26766 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN__SHIFT 0x1f |
26767 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION_MASK 0x0FFFFFFFL |
26768 | #define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED_MASK 0x10000000L |
26769 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE_MASK 0x60000000L |
26770 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN_MASK 0x80000000L |
26771 | //CP_MES_PROCESS_QUANTUM_PIPE1 |
26772 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION__SHIFT 0x0 |
26773 | #define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED__SHIFT 0x1c |
26774 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE__SHIFT 0x1d |
26775 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN__SHIFT 0x1f |
26776 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION_MASK 0x0FFFFFFFL |
26777 | #define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED_MASK 0x10000000L |
26778 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE_MASK 0x60000000L |
26779 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN_MASK 0x80000000L |
26780 | //CP_MES_DOORBELL_CONTROL1 |
26781 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT 0x2 |
26782 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT 0x1e |
26783 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT__SHIFT 0x1f |
26784 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
26785 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK 0x40000000L |
26786 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK 0x80000000L |
26787 | //CP_MES_DOORBELL_CONTROL2 |
26788 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT 0x2 |
26789 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT 0x1e |
26790 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT__SHIFT 0x1f |
26791 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
26792 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK 0x40000000L |
26793 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK 0x80000000L |
26794 | //CP_MES_DOORBELL_CONTROL3 |
26795 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT 0x2 |
26796 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT 0x1e |
26797 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT__SHIFT 0x1f |
26798 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
26799 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK 0x40000000L |
26800 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK 0x80000000L |
26801 | //CP_MES_DOORBELL_CONTROL4 |
26802 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT 0x2 |
26803 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT 0x1e |
26804 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT__SHIFT 0x1f |
26805 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
26806 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK 0x40000000L |
26807 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK 0x80000000L |
26808 | //CP_MES_DOORBELL_CONTROL5 |
26809 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT 0x2 |
26810 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT 0x1e |
26811 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT__SHIFT 0x1f |
26812 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
26813 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK 0x40000000L |
26814 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK 0x80000000L |
26815 | //CP_MES_DOORBELL_CONTROL6 |
26816 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET__SHIFT 0x2 |
26817 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN__SHIFT 0x1e |
26818 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT__SHIFT 0x1f |
26819 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
26820 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN_MASK 0x40000000L |
26821 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT_MASK 0x80000000L |
26822 | //CP_MES_GP0_LO |
26823 | #define CP_MES_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 |
26824 | #define CP_MES_GP0_LO__DATA__SHIFT 0x1 |
26825 | #define CP_MES_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L |
26826 | #define CP_MES_GP0_LO__DATA_MASK 0xFFFFFFFEL |
26827 | //CP_MES_GP0_HI |
26828 | #define CP_MES_GP0_HI__M_RET_ADDR__SHIFT 0x0 |
26829 | #define CP_MES_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL |
26830 | //CP_MES_GP1_LO |
26831 | #define CP_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 |
26832 | #define CP_MES_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL |
26833 | //CP_MES_GP1_HI |
26834 | #define CP_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 |
26835 | #define CP_MES_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL |
26836 | //CP_MES_GP2_LO |
26837 | #define CP_MES_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 |
26838 | #define CP_MES_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL |
26839 | //CP_MES_GP2_HI |
26840 | #define CP_MES_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 |
26841 | #define CP_MES_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL |
26842 | //CP_MES_GP3_LO |
26843 | #define CP_MES_GP3_LO__DATA__SHIFT 0x0 |
26844 | #define CP_MES_GP3_LO__DATA_MASK 0xFFFFFFFFL |
26845 | //CP_MES_GP3_HI |
26846 | #define CP_MES_GP3_HI__DATA__SHIFT 0x0 |
26847 | #define CP_MES_GP3_HI__DATA_MASK 0xFFFFFFFFL |
26848 | //CP_MES_GP4_LO |
26849 | #define CP_MES_GP4_LO__DATA__SHIFT 0x0 |
26850 | #define CP_MES_GP4_LO__DATA_MASK 0xFFFFFFFFL |
26851 | //CP_MES_GP4_HI |
26852 | #define CP_MES_GP4_HI__DATA__SHIFT 0x0 |
26853 | #define CP_MES_GP4_HI__DATA_MASK 0xFFFFFFFFL |
26854 | //CP_MES_GP5_LO |
26855 | #define CP_MES_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 |
26856 | #define CP_MES_GP5_LO__DATA__SHIFT 0x1 |
26857 | #define CP_MES_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L |
26858 | #define CP_MES_GP5_LO__DATA_MASK 0xFFFFFFFEL |
26859 | //CP_MES_GP5_HI |
26860 | #define CP_MES_GP5_HI__M_RET_ADDR__SHIFT 0x0 |
26861 | #define CP_MES_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL |
26862 | //CP_MES_GP6_LO |
26863 | #define CP_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 |
26864 | #define CP_MES_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL |
26865 | //CP_MES_GP6_HI |
26866 | #define CP_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 |
26867 | #define CP_MES_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL |
26868 | //CP_MES_GP7_LO |
26869 | #define CP_MES_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 |
26870 | #define CP_MES_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL |
26871 | //CP_MES_GP7_HI |
26872 | #define CP_MES_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 |
26873 | #define CP_MES_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL |
26874 | //CP_MES_GP8_LO |
26875 | #define CP_MES_GP8_LO__DATA__SHIFT 0x0 |
26876 | #define CP_MES_GP8_LO__DATA_MASK 0xFFFFFFFFL |
26877 | //CP_MES_GP8_HI |
26878 | #define CP_MES_GP8_HI__DATA__SHIFT 0x0 |
26879 | #define CP_MES_GP8_HI__DATA_MASK 0xFFFFFFFFL |
26880 | //CP_MES_GP9_LO |
26881 | #define CP_MES_GP9_LO__DATA__SHIFT 0x0 |
26882 | #define CP_MES_GP9_LO__DATA_MASK 0xFFFFFFFFL |
26883 | //CP_MES_GP9_HI |
26884 | #define CP_MES_GP9_HI__DATA__SHIFT 0x0 |
26885 | #define CP_MES_GP9_HI__DATA_MASK 0xFFFFFFFFL |
26886 | //CP_MES_DM_INDEX_ADDR |
26887 | #define CP_MES_DM_INDEX_ADDR__ADDR__SHIFT 0x0 |
26888 | #define CP_MES_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL |
26889 | //CP_MES_DM_INDEX_DATA |
26890 | #define CP_MES_DM_INDEX_DATA__DATA__SHIFT 0x0 |
26891 | #define CP_MES_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL |
26892 | //CP_MES_PERFCOUNT_CNTL |
26893 | #define CP_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 |
26894 | #define CP_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL |
26895 | //CP_MES_PENDING_INTERRUPT |
26896 | #define CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 |
26897 | #define CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL |
26898 | |
26899 | |
26900 | // addressBlock: gc_gusdec |
26901 | //GUS_IO_RD_COMBINE_FLUSH |
26902 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
26903 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
26904 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
26905 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
26906 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10 |
26907 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14 |
26908 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
26909 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
26910 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
26911 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
26912 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L |
26913 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L |
26914 | //GUS_IO_WR_COMBINE_FLUSH |
26915 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
26916 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
26917 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
26918 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
26919 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10 |
26920 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14 |
26921 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
26922 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
26923 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
26924 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
26925 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L |
26926 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L |
26927 | //GUS_IO_RD_PRI_AGE_RATE |
26928 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0 |
26929 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3 |
26930 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6 |
26931 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9 |
26932 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc |
26933 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf |
26934 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L |
26935 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L |
26936 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L |
26937 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L |
26938 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L |
26939 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L |
26940 | //GUS_IO_WR_PRI_AGE_RATE |
26941 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0 |
26942 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3 |
26943 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6 |
26944 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9 |
26945 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc |
26946 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf |
26947 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L |
26948 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L |
26949 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L |
26950 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L |
26951 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L |
26952 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L |
26953 | //GUS_IO_RD_PRI_AGE_COEFF |
26954 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0 |
26955 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3 |
26956 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6 |
26957 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9 |
26958 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc |
26959 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf |
26960 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L |
26961 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L |
26962 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L |
26963 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L |
26964 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L |
26965 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L |
26966 | //GUS_IO_WR_PRI_AGE_COEFF |
26967 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0 |
26968 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3 |
26969 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6 |
26970 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9 |
26971 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc |
26972 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf |
26973 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L |
26974 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L |
26975 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L |
26976 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L |
26977 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L |
26978 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L |
26979 | //GUS_IO_RD_PRI_QUEUING |
26980 | #define GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
26981 | #define GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
26982 | #define GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
26983 | #define GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
26984 | #define GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc |
26985 | #define GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf |
26986 | #define GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
26987 | #define GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
26988 | #define GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
26989 | #define GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
26990 | #define GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L |
26991 | #define GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L |
26992 | //GUS_IO_WR_PRI_QUEUING |
26993 | #define GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
26994 | #define GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
26995 | #define GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
26996 | #define GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
26997 | #define GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc |
26998 | #define GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf |
26999 | #define GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
27000 | #define GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
27001 | #define GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
27002 | #define GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
27003 | #define GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L |
27004 | #define GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L |
27005 | //GUS_IO_RD_PRI_FIXED |
27006 | #define GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
27007 | #define GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
27008 | #define GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
27009 | #define GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
27010 | #define GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc |
27011 | #define GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf |
27012 | #define GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
27013 | #define GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
27014 | #define GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
27015 | #define GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
27016 | #define GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L |
27017 | #define GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L |
27018 | //GUS_IO_WR_PRI_FIXED |
27019 | #define GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
27020 | #define GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
27021 | #define GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
27022 | #define GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
27023 | #define GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc |
27024 | #define GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf |
27025 | #define GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
27026 | #define GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
27027 | #define GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
27028 | #define GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
27029 | #define GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L |
27030 | #define GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L |
27031 | //GUS_IO_RD_PRI_URGENCY_COEFF |
27032 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
27033 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
27034 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
27035 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
27036 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc |
27037 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf |
27038 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
27039 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
27040 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
27041 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
27042 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L |
27043 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L |
27044 | //GUS_IO_WR_PRI_URGENCY_COEFF |
27045 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
27046 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
27047 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
27048 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
27049 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc |
27050 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf |
27051 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
27052 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
27053 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
27054 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
27055 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L |
27056 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L |
27057 | //GUS_IO_RD_PRI_URGENCY_MODE |
27058 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0 |
27059 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1 |
27060 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2 |
27061 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3 |
27062 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4 |
27063 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5 |
27064 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L |
27065 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L |
27066 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L |
27067 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L |
27068 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L |
27069 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L |
27070 | //GUS_IO_WR_PRI_URGENCY_MODE |
27071 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0 |
27072 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1 |
27073 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2 |
27074 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3 |
27075 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4 |
27076 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5 |
27077 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L |
27078 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L |
27079 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L |
27080 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L |
27081 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L |
27082 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L |
27083 | //GUS_IO_RD_PRI_QUANT_PRI1 |
27084 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
27085 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
27086 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
27087 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
27088 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
27089 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
27090 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
27091 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
27092 | //GUS_IO_RD_PRI_QUANT_PRI2 |
27093 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
27094 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
27095 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
27096 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
27097 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
27098 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
27099 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
27100 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
27101 | //GUS_IO_RD_PRI_QUANT_PRI3 |
27102 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
27103 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
27104 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
27105 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
27106 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
27107 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
27108 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
27109 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
27110 | //GUS_IO_RD_PRI_QUANT_PRI4 |
27111 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0 |
27112 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8 |
27113 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10 |
27114 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18 |
27115 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL |
27116 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L |
27117 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L |
27118 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L |
27119 | //GUS_IO_WR_PRI_QUANT_PRI1 |
27120 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
27121 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
27122 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
27123 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
27124 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
27125 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
27126 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
27127 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
27128 | //GUS_IO_WR_PRI_QUANT_PRI2 |
27129 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
27130 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
27131 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
27132 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
27133 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
27134 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
27135 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
27136 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
27137 | //GUS_IO_WR_PRI_QUANT_PRI3 |
27138 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
27139 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
27140 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
27141 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
27142 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
27143 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
27144 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
27145 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
27146 | //GUS_IO_WR_PRI_QUANT_PRI4 |
27147 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0 |
27148 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8 |
27149 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10 |
27150 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18 |
27151 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL |
27152 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L |
27153 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L |
27154 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L |
27155 | //GUS_IO_RD_PRI_QUANT1_PRI1 |
27156 | #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0 |
27157 | #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8 |
27158 | #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL |
27159 | #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L |
27160 | //GUS_IO_RD_PRI_QUANT1_PRI2 |
27161 | #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0 |
27162 | #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8 |
27163 | #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL |
27164 | #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L |
27165 | //GUS_IO_RD_PRI_QUANT1_PRI3 |
27166 | #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0 |
27167 | #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8 |
27168 | #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL |
27169 | #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L |
27170 | //GUS_IO_RD_PRI_QUANT1_PRI4 |
27171 | #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0 |
27172 | #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8 |
27173 | #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL |
27174 | #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L |
27175 | //GUS_IO_WR_PRI_QUANT1_PRI1 |
27176 | #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0 |
27177 | #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8 |
27178 | #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL |
27179 | #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L |
27180 | //GUS_IO_WR_PRI_QUANT1_PRI2 |
27181 | #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0 |
27182 | #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8 |
27183 | #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL |
27184 | #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L |
27185 | //GUS_IO_WR_PRI_QUANT1_PRI3 |
27186 | #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0 |
27187 | #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8 |
27188 | #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL |
27189 | #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L |
27190 | //GUS_IO_WR_PRI_QUANT1_PRI4 |
27191 | #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0 |
27192 | #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8 |
27193 | #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL |
27194 | #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L |
27195 | //GUS_DRAM_COMBINE_FLUSH |
27196 | #define GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
27197 | #define GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
27198 | #define GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
27199 | #define GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
27200 | #define GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10 |
27201 | #define GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14 |
27202 | #define GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
27203 | #define GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
27204 | #define GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
27205 | #define GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
27206 | #define GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L |
27207 | #define GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L |
27208 | //GUS_DRAM_COMBINE_RD_WR_EN |
27209 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER__SHIFT 0x0 |
27210 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER__SHIFT 0x2 |
27211 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER__SHIFT 0x4 |
27212 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER__SHIFT 0x6 |
27213 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER__SHIFT 0x8 |
27214 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER__SHIFT 0xa |
27215 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER_MASK 0x00000003L |
27216 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER_MASK 0x0000000CL |
27217 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER_MASK 0x00000030L |
27218 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER_MASK 0x000000C0L |
27219 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER_MASK 0x00000300L |
27220 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER_MASK 0x00000C00L |
27221 | //GUS_DRAM_PRI_AGE_RATE |
27222 | #define GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0 |
27223 | #define GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3 |
27224 | #define GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6 |
27225 | #define GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9 |
27226 | #define GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc |
27227 | #define GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf |
27228 | #define GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L |
27229 | #define GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L |
27230 | #define GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L |
27231 | #define GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L |
27232 | #define GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L |
27233 | #define GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L |
27234 | //GUS_DRAM_PRI_AGE_COEFF |
27235 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0 |
27236 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3 |
27237 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6 |
27238 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9 |
27239 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc |
27240 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf |
27241 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L |
27242 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L |
27243 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L |
27244 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L |
27245 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L |
27246 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L |
27247 | //GUS_DRAM_PRI_QUEUING |
27248 | #define GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
27249 | #define GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
27250 | #define GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
27251 | #define GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
27252 | #define GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc |
27253 | #define GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf |
27254 | #define GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
27255 | #define GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
27256 | #define GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
27257 | #define GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
27258 | #define GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L |
27259 | #define GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L |
27260 | //GUS_DRAM_PRI_FIXED |
27261 | #define GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
27262 | #define GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
27263 | #define GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
27264 | #define GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
27265 | #define GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc |
27266 | #define GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf |
27267 | #define GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
27268 | #define GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
27269 | #define GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
27270 | #define GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
27271 | #define GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L |
27272 | #define GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L |
27273 | //GUS_DRAM_PRI_URGENCY_COEFF |
27274 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
27275 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
27276 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
27277 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
27278 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc |
27279 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf |
27280 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
27281 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
27282 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
27283 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
27284 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L |
27285 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L |
27286 | //GUS_DRAM_PRI_URGENCY_MODE |
27287 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0 |
27288 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1 |
27289 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2 |
27290 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3 |
27291 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4 |
27292 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5 |
27293 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L |
27294 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L |
27295 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L |
27296 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L |
27297 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L |
27298 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L |
27299 | //GUS_DRAM_PRI_QUANT_PRI1 |
27300 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
27301 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
27302 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
27303 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
27304 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
27305 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
27306 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
27307 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
27308 | //GUS_DRAM_PRI_QUANT_PRI2 |
27309 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
27310 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
27311 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
27312 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
27313 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
27314 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
27315 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
27316 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
27317 | //GUS_DRAM_PRI_QUANT_PRI3 |
27318 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
27319 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
27320 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
27321 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
27322 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
27323 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
27324 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
27325 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
27326 | //GUS_DRAM_PRI_QUANT_PRI4 |
27327 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0 |
27328 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8 |
27329 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10 |
27330 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18 |
27331 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL |
27332 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L |
27333 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L |
27334 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L |
27335 | //GUS_DRAM_PRI_QUANT_PRI5 |
27336 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD__SHIFT 0x0 |
27337 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD__SHIFT 0x8 |
27338 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD__SHIFT 0x10 |
27339 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD__SHIFT 0x18 |
27340 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD_MASK 0x000000FFL |
27341 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD_MASK 0x0000FF00L |
27342 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD_MASK 0x00FF0000L |
27343 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD_MASK 0xFF000000L |
27344 | //GUS_DRAM_PRI_QUANT1_PRI1 |
27345 | #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0 |
27346 | #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8 |
27347 | #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL |
27348 | #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L |
27349 | //GUS_DRAM_PRI_QUANT1_PRI2 |
27350 | #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0 |
27351 | #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8 |
27352 | #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL |
27353 | #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L |
27354 | //GUS_DRAM_PRI_QUANT1_PRI3 |
27355 | #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0 |
27356 | #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8 |
27357 | #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL |
27358 | #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L |
27359 | //GUS_DRAM_PRI_QUANT1_PRI4 |
27360 | #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0 |
27361 | #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8 |
27362 | #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL |
27363 | #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L |
27364 | //GUS_DRAM_PRI_QUANT1_PRI5 |
27365 | #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD__SHIFT 0x0 |
27366 | #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD__SHIFT 0x8 |
27367 | #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD_MASK 0x000000FFL |
27368 | #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD_MASK 0x0000FF00L |
27369 | //GUS_IO_GROUP_BURST |
27370 | #define GUS_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 |
27371 | #define GUS_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 |
27372 | #define GUS_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 |
27373 | #define GUS_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 |
27374 | #define GUS_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
27375 | #define GUS_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
27376 | #define GUS_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
27377 | #define GUS_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
27378 | //GUS_DRAM_GROUP_BURST |
27379 | #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO__SHIFT 0x0 |
27380 | #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI__SHIFT 0x8 |
27381 | #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO_MASK 0x000000FFL |
27382 | #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI_MASK 0x0000FF00L |
27383 | //GUS_SDP_ARB_FINAL |
27384 | #define GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT__SHIFT 0x0 |
27385 | #define GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x5 |
27386 | #define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa |
27387 | #define GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf |
27388 | #define GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x11 |
27389 | #define GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x12 |
27390 | #define GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT_MASK 0x0000001FL |
27391 | #define GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x000003E0L |
27392 | #define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L |
27393 | #define GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L |
27394 | #define GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x00020000L |
27395 | #define GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x00040000L |
27396 | //GUS_SDP_QOS_VC_PRIORITY |
27397 | #define GUS_SDP_QOS_VC_PRIORITY__VC2_IORD__SHIFT 0x0 |
27398 | #define GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR__SHIFT 0x4 |
27399 | #define GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM__SHIFT 0x8 |
27400 | #define GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM__SHIFT 0xc |
27401 | #define GUS_SDP_QOS_VC_PRIORITY__VC2_IORD_MASK 0x0000000FL |
27402 | #define GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR_MASK 0x000000F0L |
27403 | #define GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM_MASK 0x00000F00L |
27404 | #define GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM_MASK 0x0000F000L |
27405 | //GUS_SDP_CREDITS |
27406 | #define GUS_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 |
27407 | #define GUS_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 |
27408 | #define GUS_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 |
27409 | #define GUS_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL |
27410 | #define GUS_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L |
27411 | #define GUS_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L |
27412 | //GUS_SDP_TAG_RESERVE0 |
27413 | #define GUS_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 |
27414 | #define GUS_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 |
27415 | #define GUS_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 |
27416 | #define GUS_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 |
27417 | #define GUS_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL |
27418 | #define GUS_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L |
27419 | #define GUS_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L |
27420 | #define GUS_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L |
27421 | //GUS_SDP_TAG_RESERVE1 |
27422 | #define GUS_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 |
27423 | #define GUS_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 |
27424 | #define GUS_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 |
27425 | #define GUS_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 |
27426 | #define GUS_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL |
27427 | #define GUS_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L |
27428 | #define GUS_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L |
27429 | #define GUS_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L |
27430 | //GUS_SDP_VCC_RESERVE0 |
27431 | #define GUS_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
27432 | #define GUS_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
27433 | #define GUS_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc |
27434 | #define GUS_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
27435 | #define GUS_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
27436 | #define GUS_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
27437 | #define GUS_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
27438 | #define GUS_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
27439 | #define GUS_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
27440 | #define GUS_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
27441 | //GUS_SDP_VCC_RESERVE1 |
27442 | #define GUS_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
27443 | #define GUS_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
27444 | #define GUS_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc |
27445 | #define GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
27446 | #define GUS_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
27447 | #define GUS_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
27448 | #define GUS_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
27449 | #define GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
27450 | //GUS_SDP_VCD_RESERVE0 |
27451 | #define GUS_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
27452 | #define GUS_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
27453 | #define GUS_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc |
27454 | #define GUS_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
27455 | #define GUS_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
27456 | #define GUS_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
27457 | #define GUS_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
27458 | #define GUS_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
27459 | #define GUS_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
27460 | #define GUS_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
27461 | //GUS_SDP_VCD_RESERVE1 |
27462 | #define GUS_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
27463 | #define GUS_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
27464 | #define GUS_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc |
27465 | #define GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
27466 | #define GUS_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
27467 | #define GUS_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
27468 | #define GUS_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
27469 | #define GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
27470 | //GUS_SDP_REQ_CNTL |
27471 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 |
27472 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 |
27473 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 |
27474 | #define GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 |
27475 | #define GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 |
27476 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L |
27477 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L |
27478 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L |
27479 | #define GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L |
27480 | #define GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L |
27481 | //GUS_MISC |
27482 | #define GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB__SHIFT 0x0 |
27483 | #define GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x1 |
27484 | #define GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x2 |
27485 | #define GUS_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x3 |
27486 | #define GUS_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x4 |
27487 | #define GUS_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x6 |
27488 | #define GUS_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x8 |
27489 | #define GUS_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xa |
27490 | #define GUS_MISC__SEND0_IOWR_ONLY__SHIFT 0xf |
27491 | #define GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB_MASK 0x00000001L |
27492 | #define GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000002L |
27493 | #define GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000004L |
27494 | #define GUS_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000008L |
27495 | #define GUS_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000030L |
27496 | #define GUS_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x000000C0L |
27497 | #define GUS_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00000300L |
27498 | #define GUS_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x00007C00L |
27499 | #define GUS_MISC__SEND0_IOWR_ONLY_MASK 0x00008000L |
27500 | //GUS_LATENCY_SAMPLING |
27501 | #define GUS_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 |
27502 | #define GUS_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 |
27503 | #define GUS_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x2 |
27504 | #define GUS_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x3 |
27505 | #define GUS_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x4 |
27506 | #define GUS_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x5 |
27507 | #define GUS_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x6 |
27508 | #define GUS_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x7 |
27509 | #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0x8 |
27510 | #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0x9 |
27511 | #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xa |
27512 | #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xb |
27513 | #define GUS_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xc |
27514 | #define GUS_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x14 |
27515 | #define GUS_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L |
27516 | #define GUS_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L |
27517 | #define GUS_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000004L |
27518 | #define GUS_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000008L |
27519 | #define GUS_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000010L |
27520 | #define GUS_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000020L |
27521 | #define GUS_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000040L |
27522 | #define GUS_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000080L |
27523 | #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000100L |
27524 | #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000200L |
27525 | #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00000400L |
27526 | #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00000800L |
27527 | #define GUS_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x000FF000L |
27528 | #define GUS_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x0FF00000L |
27529 | //GUS_ERR_STATUS |
27530 | #define GUS_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 |
27531 | #define GUS_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 |
27532 | #define GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 |
27533 | #define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa |
27534 | #define GUS_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb |
27535 | #define GUS_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc |
27536 | #define GUS_ERR_STATUS__FUE_FLAG__SHIFT 0xd |
27537 | #define GUS_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL |
27538 | #define GUS_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L |
27539 | #define GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L |
27540 | #define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L |
27541 | #define GUS_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L |
27542 | #define GUS_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L |
27543 | #define GUS_ERR_STATUS__FUE_FLAG_MASK 0x00002000L |
27544 | //GUS_MISC2 |
27545 | #define GUS_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0x0 |
27546 | #define GUS_MISC2__CH_L1_RO_MASK__SHIFT 0x1 |
27547 | #define GUS_MISC2__SA0_L1_RO_MASK__SHIFT 0x2 |
27548 | #define GUS_MISC2__SA1_L1_RO_MASK__SHIFT 0x3 |
27549 | #define GUS_MISC2__SA2_L1_RO_MASK__SHIFT 0x4 |
27550 | #define GUS_MISC2__SA3_L1_RO_MASK__SHIFT 0x5 |
27551 | #define GUS_MISC2__CH_L1_PERF_MASK__SHIFT 0x6 |
27552 | #define GUS_MISC2__SA0_L1_PERF_MASK__SHIFT 0x7 |
27553 | #define GUS_MISC2__SA1_L1_PERF_MASK__SHIFT 0x8 |
27554 | #define GUS_MISC2__SA2_L1_PERF_MASK__SHIFT 0x9 |
27555 | #define GUS_MISC2__SA3_L1_PERF_MASK__SHIFT 0xa |
27556 | #define GUS_MISC2__FP_ATOMICS_ENABLE__SHIFT 0xb |
27557 | #define GUS_MISC2__L1_RET_CLKEN__SHIFT 0xc |
27558 | #define GUS_MISC2__FGCLKEN_HIGH__SHIFT 0xd |
27559 | #define GUS_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00000001L |
27560 | #define GUS_MISC2__CH_L1_RO_MASK_MASK 0x00000002L |
27561 | #define GUS_MISC2__SA0_L1_RO_MASK_MASK 0x00000004L |
27562 | #define GUS_MISC2__SA1_L1_RO_MASK_MASK 0x00000008L |
27563 | #define GUS_MISC2__SA2_L1_RO_MASK_MASK 0x00000010L |
27564 | #define GUS_MISC2__SA3_L1_RO_MASK_MASK 0x00000020L |
27565 | #define GUS_MISC2__CH_L1_PERF_MASK_MASK 0x00000040L |
27566 | #define GUS_MISC2__SA0_L1_PERF_MASK_MASK 0x00000080L |
27567 | #define GUS_MISC2__SA1_L1_PERF_MASK_MASK 0x00000100L |
27568 | #define GUS_MISC2__SA2_L1_PERF_MASK_MASK 0x00000200L |
27569 | #define GUS_MISC2__SA3_L1_PERF_MASK_MASK 0x00000400L |
27570 | #define GUS_MISC2__FP_ATOMICS_ENABLE_MASK 0x00000800L |
27571 | #define GUS_MISC2__L1_RET_CLKEN_MASK 0x00001000L |
27572 | #define GUS_MISC2__FGCLKEN_HIGH_MASK 0x00002000L |
27573 | //GUS_SDP_ENABLE |
27574 | #define GUS_SDP_ENABLE__ENABLE__SHIFT 0x0 |
27575 | #define GUS_SDP_ENABLE__ENABLE_MASK 0x00000001L |
27576 | //GUS_L1_CH0_CMD_IN |
27577 | #define GUS_L1_CH0_CMD_IN__COUNT__SHIFT 0x0 |
27578 | #define GUS_L1_CH0_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
27579 | //GUS_L1_CH0_CMD_OUT |
27580 | #define GUS_L1_CH0_CMD_OUT__COUNT__SHIFT 0x0 |
27581 | #define GUS_L1_CH0_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
27582 | //GUS_L1_CH0_DATA_IN |
27583 | #define GUS_L1_CH0_DATA_IN__COUNT__SHIFT 0x0 |
27584 | #define GUS_L1_CH0_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
27585 | //GUS_L1_CH0_DATA_OUT |
27586 | #define GUS_L1_CH0_DATA_OUT__COUNT__SHIFT 0x0 |
27587 | #define GUS_L1_CH0_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
27588 | //GUS_L1_CH0_DATA_U_IN |
27589 | #define GUS_L1_CH0_DATA_U_IN__COUNT__SHIFT 0x0 |
27590 | #define GUS_L1_CH0_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
27591 | //GUS_L1_CH0_DATA_U_OUT |
27592 | #define GUS_L1_CH0_DATA_U_OUT__COUNT__SHIFT 0x0 |
27593 | #define GUS_L1_CH0_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
27594 | //GUS_L1_CH1_CMD_IN |
27595 | #define GUS_L1_CH1_CMD_IN__COUNT__SHIFT 0x0 |
27596 | #define GUS_L1_CH1_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
27597 | //GUS_L1_CH1_CMD_OUT |
27598 | #define GUS_L1_CH1_CMD_OUT__COUNT__SHIFT 0x0 |
27599 | #define GUS_L1_CH1_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
27600 | //GUS_L1_CH1_DATA_IN |
27601 | #define GUS_L1_CH1_DATA_IN__COUNT__SHIFT 0x0 |
27602 | #define GUS_L1_CH1_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
27603 | //GUS_L1_CH1_DATA_OUT |
27604 | #define GUS_L1_CH1_DATA_OUT__COUNT__SHIFT 0x0 |
27605 | #define GUS_L1_CH1_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
27606 | //GUS_L1_CH1_DATA_U_IN |
27607 | #define GUS_L1_CH1_DATA_U_IN__COUNT__SHIFT 0x0 |
27608 | #define GUS_L1_CH1_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
27609 | //GUS_L1_CH1_DATA_U_OUT |
27610 | #define GUS_L1_CH1_DATA_U_OUT__COUNT__SHIFT 0x0 |
27611 | #define GUS_L1_CH1_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
27612 | //GUS_L1_SA0_CMD_IN |
27613 | #define GUS_L1_SA0_CMD_IN__COUNT__SHIFT 0x0 |
27614 | #define GUS_L1_SA0_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
27615 | //GUS_L1_SA0_CMD_OUT |
27616 | #define GUS_L1_SA0_CMD_OUT__COUNT__SHIFT 0x0 |
27617 | #define GUS_L1_SA0_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
27618 | //GUS_L1_SA0_DATA_IN |
27619 | #define GUS_L1_SA0_DATA_IN__COUNT__SHIFT 0x0 |
27620 | #define GUS_L1_SA0_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
27621 | //GUS_L1_SA0_DATA_OUT |
27622 | #define GUS_L1_SA0_DATA_OUT__COUNT__SHIFT 0x0 |
27623 | #define GUS_L1_SA0_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
27624 | //GUS_L1_SA0_DATA_U_IN |
27625 | #define GUS_L1_SA0_DATA_U_IN__COUNT__SHIFT 0x0 |
27626 | #define GUS_L1_SA0_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
27627 | //GUS_L1_SA0_DATA_U_OUT |
27628 | #define GUS_L1_SA0_DATA_U_OUT__COUNT__SHIFT 0x0 |
27629 | #define GUS_L1_SA0_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
27630 | //GUS_L1_SA1_CMD_IN |
27631 | #define GUS_L1_SA1_CMD_IN__COUNT__SHIFT 0x0 |
27632 | #define GUS_L1_SA1_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
27633 | //GUS_L1_SA1_CMD_OUT |
27634 | #define GUS_L1_SA1_CMD_OUT__COUNT__SHIFT 0x0 |
27635 | #define GUS_L1_SA1_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
27636 | //GUS_L1_SA1_DATA_IN |
27637 | #define GUS_L1_SA1_DATA_IN__COUNT__SHIFT 0x0 |
27638 | #define GUS_L1_SA1_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
27639 | //GUS_L1_SA1_DATA_OUT |
27640 | #define GUS_L1_SA1_DATA_OUT__COUNT__SHIFT 0x0 |
27641 | #define GUS_L1_SA1_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
27642 | //GUS_L1_SA1_DATA_U_IN |
27643 | #define GUS_L1_SA1_DATA_U_IN__COUNT__SHIFT 0x0 |
27644 | #define GUS_L1_SA1_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
27645 | //GUS_L1_SA1_DATA_U_OUT |
27646 | #define GUS_L1_SA1_DATA_U_OUT__COUNT__SHIFT 0x0 |
27647 | #define GUS_L1_SA1_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
27648 | //GUS_L1_SA2_CMD_IN |
27649 | #define GUS_L1_SA2_CMD_IN__COUNT__SHIFT 0x0 |
27650 | #define GUS_L1_SA2_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
27651 | //GUS_L1_SA2_CMD_OUT |
27652 | #define GUS_L1_SA2_CMD_OUT__COUNT__SHIFT 0x0 |
27653 | #define GUS_L1_SA2_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
27654 | //GUS_L1_SA2_DATA_IN |
27655 | #define GUS_L1_SA2_DATA_IN__COUNT__SHIFT 0x0 |
27656 | #define GUS_L1_SA2_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
27657 | //GUS_L1_SA2_DATA_OUT |
27658 | #define GUS_L1_SA2_DATA_OUT__COUNT__SHIFT 0x0 |
27659 | #define GUS_L1_SA2_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
27660 | //GUS_L1_SA2_DATA_U_IN |
27661 | #define GUS_L1_SA2_DATA_U_IN__COUNT__SHIFT 0x0 |
27662 | #define GUS_L1_SA2_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
27663 | //GUS_L1_SA2_DATA_U_OUT |
27664 | #define GUS_L1_SA2_DATA_U_OUT__COUNT__SHIFT 0x0 |
27665 | #define GUS_L1_SA2_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
27666 | //GUS_L1_SA3_CMD_IN |
27667 | #define GUS_L1_SA3_CMD_IN__COUNT__SHIFT 0x0 |
27668 | #define GUS_L1_SA3_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
27669 | //GUS_L1_SA3_CMD_OUT |
27670 | #define GUS_L1_SA3_CMD_OUT__COUNT__SHIFT 0x0 |
27671 | #define GUS_L1_SA3_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
27672 | //GUS_L1_SA3_DATA_IN |
27673 | #define GUS_L1_SA3_DATA_IN__COUNT__SHIFT 0x0 |
27674 | #define GUS_L1_SA3_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
27675 | //GUS_L1_SA3_DATA_OUT |
27676 | #define GUS_L1_SA3_DATA_OUT__COUNT__SHIFT 0x0 |
27677 | #define GUS_L1_SA3_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
27678 | //GUS_L1_SA3_DATA_U_IN |
27679 | #define GUS_L1_SA3_DATA_U_IN__COUNT__SHIFT 0x0 |
27680 | #define GUS_L1_SA3_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
27681 | //GUS_L1_SA3_DATA_U_OUT |
27682 | #define GUS_L1_SA3_DATA_U_OUT__COUNT__SHIFT 0x0 |
27683 | #define GUS_L1_SA3_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
27684 | //GUS_MISC3 |
27685 | #define GUS_MISC3__FP_ATOMICS_LOG__SHIFT 0x0 |
27686 | #define GUS_MISC3__CLEAR_LOG__SHIFT 0x1 |
27687 | #define GUS_MISC3__FP_ATOMICS_LOG_MASK 0x00000001L |
27688 | #define GUS_MISC3__CLEAR_LOG_MASK 0x00000002L |
27689 | //GUS_WRRSP_FIFO_CNTL |
27690 | #define GUS_WRRSP_FIFO_CNTL__THRESHOLD__SHIFT 0x0 |
27691 | #define GUS_WRRSP_FIFO_CNTL__THRESHOLD_MASK 0x0000003FL |
27692 | |
27693 | |
27694 | // addressBlock: gc_gl1dec |
27695 | //GL1_DRAM_BURST_MASK |
27696 | #define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 |
27697 | #define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL |
27698 | //GL1_ARB_STATUS |
27699 | #define GL1_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 |
27700 | #define GL1_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 |
27701 | #define GL1_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L |
27702 | #define GL1_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L |
27703 | //GL1_PIPE_STEER |
27704 | #define GL1_PIPE_STEER__PIPE0__SHIFT 0x0 |
27705 | #define GL1_PIPE_STEER__PIPE1__SHIFT 0x2 |
27706 | #define GL1_PIPE_STEER__PIPE2__SHIFT 0x4 |
27707 | #define GL1_PIPE_STEER__PIPE3__SHIFT 0x6 |
27708 | #define GL1_PIPE_STEER__PIPE0_MASK 0x00000003L |
27709 | #define GL1_PIPE_STEER__PIPE1_MASK 0x0000000CL |
27710 | #define GL1_PIPE_STEER__PIPE2_MASK 0x00000030L |
27711 | #define GL1_PIPE_STEER__PIPE3_MASK 0x000000C0L |
27712 | //GL1C_STATUS |
27713 | #define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 |
27714 | #define GL1C_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 |
27715 | #define GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2 |
27716 | #define GL1C_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 |
27717 | #define GL1C_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 |
27718 | #define GL1C_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 |
27719 | #define GL1C_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 |
27720 | #define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 |
27721 | #define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 |
27722 | #define GL1C_STATUS__GL2_RH_BUSY__SHIFT 0x9 |
27723 | #define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa |
27724 | #define GL1C_STATUS__LATENCY_FIFO_FULL_STALL__SHIFT 0x14 |
27725 | #define GL1C_STATUS__TAG_STALL__SHIFT 0x15 |
27726 | #define GL1C_STATUS__TAG_BUSY__SHIFT 0x16 |
27727 | #define GL1C_STATUS__TAG_ACK_STALL__SHIFT 0x17 |
27728 | #define GL1C_STATUS__TAG_GCR_INV_STALL__SHIFT 0x18 |
27729 | #define GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL__SHIFT 0x19 |
27730 | #define GL1C_STATUS__TAG_EVICT__SHIFT 0x1a |
27731 | #define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION__SHIFT 0x1b |
27732 | #define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET__SHIFT 0x1f |
27733 | #define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L |
27734 | #define GL1C_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L |
27735 | #define GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L |
27736 | #define GL1C_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L |
27737 | #define GL1C_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L |
27738 | #define GL1C_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L |
27739 | #define GL1C_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L |
27740 | #define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L |
27741 | #define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L |
27742 | #define GL1C_STATUS__GL2_RH_BUSY_MASK 0x00000200L |
27743 | #define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L |
27744 | #define GL1C_STATUS__LATENCY_FIFO_FULL_STALL_MASK 0x00100000L |
27745 | #define GL1C_STATUS__TAG_STALL_MASK 0x00200000L |
27746 | #define GL1C_STATUS__TAG_BUSY_MASK 0x00400000L |
27747 | #define GL1C_STATUS__TAG_ACK_STALL_MASK 0x00800000L |
27748 | #define GL1C_STATUS__TAG_GCR_INV_STALL_MASK 0x01000000L |
27749 | #define GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL_MASK 0x02000000L |
27750 | #define GL1C_STATUS__TAG_EVICT_MASK 0x04000000L |
27751 | #define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION_MASK 0x78000000L |
27752 | #define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET_MASK 0x80000000L |
27753 | //GL1C_UTCL0_CNTL2 |
27754 | #define GL1C_UTCL0_CNTL2__SPARE__SHIFT 0x0 |
27755 | #define GL1C_UTCL0_CNTL2__COMP_SYNC_DISABLE__SHIFT 0x8 |
27756 | #define GL1C_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
27757 | #define GL1C_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT 0xa |
27758 | #define GL1C_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
27759 | #define GL1C_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe |
27760 | #define GL1C_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
27761 | #define GL1C_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
27762 | #define GL1C_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b |
27763 | #define GL1C_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c |
27764 | #define GL1C_UTCL0_CNTL2__GPUVM_16K_DEFAULT__SHIFT 0x1d |
27765 | #define GL1C_UTCL0_CNTL2__FGCG_DISABLE__SHIFT 0x1e |
27766 | #define GL1C_UTCL0_CNTL2__BIG_PAGE_DISABLE__SHIFT 0x1f |
27767 | #define GL1C_UTCL0_CNTL2__SPARE_MASK 0x000000FFL |
27768 | #define GL1C_UTCL0_CNTL2__COMP_SYNC_DISABLE_MASK 0x00000100L |
27769 | #define GL1C_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
27770 | #define GL1C_UTCL0_CNTL2__ANY_LINE_VALID_MASK 0x00000400L |
27771 | #define GL1C_UTCL0_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
27772 | #define GL1C_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
27773 | #define GL1C_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
27774 | #define GL1C_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
27775 | #define GL1C_UTCL0_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L |
27776 | #define GL1C_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L |
27777 | #define GL1C_UTCL0_CNTL2__GPUVM_16K_DEFAULT_MASK 0x20000000L |
27778 | #define GL1C_UTCL0_CNTL2__FGCG_DISABLE_MASK 0x40000000L |
27779 | #define GL1C_UTCL0_CNTL2__BIG_PAGE_DISABLE_MASK 0x80000000L |
27780 | //GL1C_UTCL0_STATUS |
27781 | #define GL1C_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 |
27782 | #define GL1C_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 |
27783 | #define GL1C_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 |
27784 | #define GL1C_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L |
27785 | #define GL1C_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L |
27786 | #define GL1C_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L |
27787 | //GL1C_UTCL0_RETRY |
27788 | #define GL1C_UTCL0_RETRY__INCR__SHIFT 0x0 |
27789 | #define GL1C_UTCL0_RETRY__COUNT__SHIFT 0x8 |
27790 | #define GL1C_UTCL0_RETRY__INCR_MASK 0x000000FFL |
27791 | #define GL1C_UTCL0_RETRY__COUNT_MASK 0x00000F00L |
27792 | |
27793 | |
27794 | // addressBlock: gc_chdec |
27795 | //CH_ARB_CTRL |
27796 | #define CH_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0 |
27797 | #define CH_ARB_CTRL__UC_IO_WR_PATH__SHIFT 0x2 |
27798 | #define CH_ARB_CTRL__FGCG_DISABLE__SHIFT 0x3 |
27799 | #define CH_ARB_CTRL__CHICKEN_BITS__SHIFT 0x4 |
27800 | #define CH_ARB_CTRL__NUM_MEM_PIPES_MASK 0x00000003L |
27801 | #define CH_ARB_CTRL__UC_IO_WR_PATH_MASK 0x00000004L |
27802 | #define CH_ARB_CTRL__FGCG_DISABLE_MASK 0x00000008L |
27803 | #define CH_ARB_CTRL__CHICKEN_BITS_MASK 0x00000FF0L |
27804 | //CH_DRAM_BURST_MASK |
27805 | #define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 |
27806 | #define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL |
27807 | //CH_ARB_STATUS |
27808 | #define CH_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 |
27809 | #define CH_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 |
27810 | #define CH_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L |
27811 | #define CH_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L |
27812 | //CH_DRAM_BURST_CTRL |
27813 | #define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0 |
27814 | #define CH_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 |
27815 | #define CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT 0x4 |
27816 | #define CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE__SHIFT 0x5 |
27817 | #define CH_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE__SHIFT 0x6 |
27818 | #define CH_DRAM_BURST_CTRL__GATHER_32B_IO_BURST_DISABLE__SHIFT 0x7 |
27819 | #define CH_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE__SHIFT 0x8 |
27820 | #define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L |
27821 | #define CH_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L |
27822 | #define CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK 0x00000010L |
27823 | #define CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE_MASK 0x00000020L |
27824 | #define CH_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE_MASK 0x00000040L |
27825 | #define CH_DRAM_BURST_CTRL__GATHER_32B_IO_BURST_DISABLE_MASK 0x00000080L |
27826 | #define CH_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE_MASK 0x00000100L |
27827 | //CHA_CHC_CREDITS |
27828 | #define CHA_CHC_CREDITS__CHC_REQ_CREDITS__SHIFT 0x0 |
27829 | #define CHA_CHC_CREDITS__CHCG_REQ_CREDITS__SHIFT 0x8 |
27830 | #define CHA_CHC_CREDITS__CHC_REQ_CREDITS_MASK 0x000000FFL |
27831 | #define CHA_CHC_CREDITS__CHCG_REQ_CREDITS_MASK 0x0000FF00L |
27832 | //CHA_CLIENT_FREE_DELAY |
27833 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY__SHIFT 0x0 |
27834 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY__SHIFT 0x3 |
27835 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY__SHIFT 0x6 |
27836 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY__SHIFT 0x9 |
27837 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY__SHIFT 0xc |
27838 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_5_FREE_DELAY__SHIFT 0xf |
27839 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_6_FREE_DELAY__SHIFT 0x12 |
27840 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_7_FREE_DELAY__SHIFT 0x15 |
27841 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_8_FREE_DELAY__SHIFT 0x18 |
27842 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_9_FREE_DELAY__SHIFT 0x1b |
27843 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY_MASK 0x00000007L |
27844 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY_MASK 0x00000038L |
27845 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY_MASK 0x000001C0L |
27846 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY_MASK 0x00000E00L |
27847 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY_MASK 0x00007000L |
27848 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_5_FREE_DELAY_MASK 0x00038000L |
27849 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_6_FREE_DELAY_MASK 0x001C0000L |
27850 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_7_FREE_DELAY_MASK 0x00E00000L |
27851 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_8_FREE_DELAY_MASK 0x07000000L |
27852 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_9_FREE_DELAY_MASK 0x38000000L |
27853 | //CH_PIPE_STEER |
27854 | #define CH_PIPE_STEER__PIPE0__SHIFT 0x0 |
27855 | #define CH_PIPE_STEER__PIPE1__SHIFT 0x2 |
27856 | #define CH_PIPE_STEER__PIPE2__SHIFT 0x4 |
27857 | #define CH_PIPE_STEER__PIPE3__SHIFT 0x6 |
27858 | #define CH_PIPE_STEER__PIPE0_MASK 0x00000003L |
27859 | #define CH_PIPE_STEER__PIPE1_MASK 0x0000000CL |
27860 | #define CH_PIPE_STEER__PIPE2_MASK 0x00000030L |
27861 | #define CH_PIPE_STEER__PIPE3_MASK 0x000000C0L |
27862 | //CH_VC5_ENABLE |
27863 | #define CH_VC5_ENABLE__UTCL2_VC5_ENABLE__SHIFT 0x1 |
27864 | #define CH_VC5_ENABLE__UTCL2_VC5_ENABLE_MASK 0x00000002L |
27865 | //CHC_CTRL |
27866 | #define CHC_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 |
27867 | #define CHC_CTRL__GL2_REQ_CREDITS__SHIFT 0x4 |
27868 | #define CHC_CTRL__GL2_DATA_CREDITS__SHIFT 0xb |
27869 | #define CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x12 |
27870 | #define CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x13 |
27871 | #define CHC_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL |
27872 | #define CHC_CTRL__GL2_REQ_CREDITS_MASK 0x000007F0L |
27873 | #define CHC_CTRL__GL2_DATA_CREDITS_MASK 0x0003F800L |
27874 | #define CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x00040000L |
27875 | #define CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x00080000L |
27876 | //CHC_STATUS |
27877 | #define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 |
27878 | #define CHC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 |
27879 | #define CHC_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2 |
27880 | #define CHC_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 |
27881 | #define CHC_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 |
27882 | #define CHC_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 |
27883 | #define CHC_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 |
27884 | #define CHC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 |
27885 | #define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 |
27886 | #define CHC_STATUS__GL2_RH_BUSY__SHIFT 0x9 |
27887 | #define CHC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa |
27888 | #define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14 |
27889 | #define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15 |
27890 | #define CHC_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16 |
27891 | #define CHC_STATUS__BUFFER_FULL__SHIFT 0x17 |
27892 | #define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L |
27893 | #define CHC_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L |
27894 | #define CHC_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L |
27895 | #define CHC_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L |
27896 | #define CHC_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L |
27897 | #define CHC_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L |
27898 | #define CHC_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L |
27899 | #define CHC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L |
27900 | #define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L |
27901 | #define CHC_STATUS__GL2_RH_BUSY_MASK 0x00000200L |
27902 | #define CHC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L |
27903 | #define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L |
27904 | #define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L |
27905 | #define CHC_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L |
27906 | #define CHC_STATUS__BUFFER_FULL_MASK 0x00800000L |
27907 | //CHCG_CTRL |
27908 | #define CHCG_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 |
27909 | #define CHCG_CTRL__VC0_BUFFER_DEPTH_MAX__SHIFT 0x4 |
27910 | #define CHCG_CTRL__GL2_REQ_CREDITS__SHIFT 0x8 |
27911 | #define CHCG_CTRL__GL2_DATA_CREDITS__SHIFT 0xf |
27912 | #define CHCG_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x16 |
27913 | #define CHCG_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x17 |
27914 | #define CHCG_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL |
27915 | #define CHCG_CTRL__VC0_BUFFER_DEPTH_MAX_MASK 0x000000F0L |
27916 | #define CHCG_CTRL__GL2_REQ_CREDITS_MASK 0x00007F00L |
27917 | #define CHCG_CTRL__GL2_DATA_CREDITS_MASK 0x003F8000L |
27918 | #define CHCG_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x00400000L |
27919 | #define CHCG_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x00800000L |
27920 | //CHCG_STATUS |
27921 | #define CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 |
27922 | #define CHCG_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 |
27923 | #define CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2 |
27924 | #define CHCG_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 |
27925 | #define CHCG_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 |
27926 | #define CHCG_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 |
27927 | #define CHCG_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 |
27928 | #define CHCG_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 |
27929 | #define CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 |
27930 | #define CHCG_STATUS__GL2_RH_BUSY__SHIFT 0x9 |
27931 | #define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa |
27932 | #define CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14 |
27933 | #define CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15 |
27934 | #define CHCG_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16 |
27935 | #define CHCG_STATUS__BUFFER_FULL__SHIFT 0x17 |
27936 | #define CHCG_STATUS__INPUT_BUFFER_VC1_BUSY__SHIFT 0x18 |
27937 | #define CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY__SHIFT 0x19 |
27938 | #define CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL__SHIFT 0x1a |
27939 | #define CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL__SHIFT 0x1b |
27940 | #define CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L |
27941 | #define CHCG_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L |
27942 | #define CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L |
27943 | #define CHCG_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L |
27944 | #define CHCG_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L |
27945 | #define CHCG_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L |
27946 | #define CHCG_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L |
27947 | #define CHCG_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L |
27948 | #define CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L |
27949 | #define CHCG_STATUS__GL2_RH_BUSY_MASK 0x00000200L |
27950 | #define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L |
27951 | #define CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L |
27952 | #define CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L |
27953 | #define CHCG_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L |
27954 | #define CHCG_STATUS__BUFFER_FULL_MASK 0x00800000L |
27955 | #define CHCG_STATUS__INPUT_BUFFER_VC1_BUSY_MASK 0x01000000L |
27956 | #define CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY_MASK 0x02000000L |
27957 | #define CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL_MASK 0x04000000L |
27958 | #define CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL_MASK 0x08000000L |
27959 | |
27960 | |
27961 | // addressBlock: gc_gl2dec |
27962 | //GL2C_CTRL |
27963 | #define GL2C_CTRL__CACHE_SIZE__SHIFT 0x0 |
27964 | #define GL2C_CTRL__RATE__SHIFT 0x2 |
27965 | #define GL2C_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 |
27966 | #define GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8 |
27967 | #define GL2C_CTRL__SRC_FIFO_SIZE__SHIFT 0xc |
27968 | #define GL2C_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 |
27969 | #define GL2C_CTRL__METADATA_TO_HI_PRIORITY__SHIFT 0x14 |
27970 | #define GL2C_CTRL__FORCE_HIT_QUEUE_POP__SHIFT 0x16 |
27971 | #define GL2C_CTRL__MDC_SIZE__SHIFT 0x18 |
27972 | #define GL2C_CTRL__METADATA_TO_HIT_QUEUE__SHIFT 0x1a |
27973 | #define GL2C_CTRL__IGNORE_FULLY_WRITTEN__SHIFT 0x1b |
27974 | #define GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c |
27975 | #define GL2C_CTRL__CACHE_SIZE_MASK 0x00000003L |
27976 | #define GL2C_CTRL__RATE_MASK 0x0000000CL |
27977 | #define GL2C_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L |
27978 | #define GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L |
27979 | #define GL2C_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L |
27980 | #define GL2C_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L |
27981 | #define GL2C_CTRL__METADATA_TO_HI_PRIORITY_MASK 0x00100000L |
27982 | #define GL2C_CTRL__FORCE_HIT_QUEUE_POP_MASK 0x00C00000L |
27983 | #define GL2C_CTRL__MDC_SIZE_MASK 0x03000000L |
27984 | #define GL2C_CTRL__METADATA_TO_HIT_QUEUE_MASK 0x04000000L |
27985 | #define GL2C_CTRL__IGNORE_FULLY_WRITTEN_MASK 0x08000000L |
27986 | #define GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L |
27987 | //GL2C_CTRL2 |
27988 | #define GL2C_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0 |
27989 | #define GL2C_CTRL2__ADDR_MATCH_DISABLE__SHIFT 0x4 |
27990 | #define GL2C_CTRL2__FILL_SIZE_32__SHIFT 0x5 |
27991 | #define GL2C_CTRL2__RB_TO_HI_PRIORITY__SHIFT 0x6 |
27992 | #define GL2C_CTRL2__HIT_UNDER_MISS_DISABLE__SHIFT 0x7 |
27993 | #define GL2C_CTRL2__RO_DISABLE__SHIFT 0x8 |
27994 | #define GL2C_CTRL2__FORCE_MDC_INV__SHIFT 0x9 |
27995 | #define GL2C_CTRL2__GCR_ARB_CTRL__SHIFT 0xa |
27996 | #define GL2C_CTRL2__GCR_ALL_SET__SHIFT 0xd |
27997 | #define GL2C_CTRL2__MDC_PF_BLOCK__SHIFT 0xe |
27998 | #define GL2C_CTRL2__MDC_PF_MAX_SIZE__SHIFT 0x10 |
27999 | #define GL2C_CTRL2__FILL_SIZE_64__SHIFT 0x11 |
28000 | #define GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT 0x12 |
28001 | #define GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE__SHIFT 0x13 |
28002 | #define GL2C_CTRL2__METADATA_VOLATILE_EN__SHIFT 0x14 |
28003 | #define GL2C_CTRL2__RB_VOLATILE_EN__SHIFT 0x15 |
28004 | #define GL2C_CTRL2__PROBE_UNSHARED_EN__SHIFT 0x16 |
28005 | #define GL2C_CTRL2__MAX_MIN_CTRL__SHIFT 0x17 |
28006 | #define GL2C_CTRL2__MDC_PF_LINEAR_METADATA__SHIFT 0x19 |
28007 | #define GL2C_CTRL2__MDC_UC_TO_C_RO_EN__SHIFT 0x1a |
28008 | #define GL2C_CTRL2__MDC_PF_MIN_PAGE_SIZE__SHIFT 0x1b |
28009 | #define GL2C_CTRL2__MDC_PF_DISABLE__SHIFT 0x1d |
28010 | #define GL2C_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL |
28011 | #define GL2C_CTRL2__ADDR_MATCH_DISABLE_MASK 0x00000010L |
28012 | #define GL2C_CTRL2__FILL_SIZE_32_MASK 0x00000020L |
28013 | #define GL2C_CTRL2__RB_TO_HI_PRIORITY_MASK 0x00000040L |
28014 | #define GL2C_CTRL2__HIT_UNDER_MISS_DISABLE_MASK 0x00000080L |
28015 | #define GL2C_CTRL2__RO_DISABLE_MASK 0x00000100L |
28016 | #define GL2C_CTRL2__FORCE_MDC_INV_MASK 0x00000200L |
28017 | #define GL2C_CTRL2__GCR_ARB_CTRL_MASK 0x00001C00L |
28018 | #define GL2C_CTRL2__GCR_ALL_SET_MASK 0x00002000L |
28019 | #define GL2C_CTRL2__MDC_PF_BLOCK_MASK 0x0000C000L |
28020 | #define GL2C_CTRL2__MDC_PF_MAX_SIZE_MASK 0x00010000L |
28021 | #define GL2C_CTRL2__FILL_SIZE_64_MASK 0x00020000L |
28022 | #define GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK 0x00040000L |
28023 | #define GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE_MASK 0x00080000L |
28024 | #define GL2C_CTRL2__METADATA_VOLATILE_EN_MASK 0x00100000L |
28025 | #define GL2C_CTRL2__RB_VOLATILE_EN_MASK 0x00200000L |
28026 | #define GL2C_CTRL2__PROBE_UNSHARED_EN_MASK 0x00400000L |
28027 | #define GL2C_CTRL2__MAX_MIN_CTRL_MASK 0x01800000L |
28028 | #define GL2C_CTRL2__MDC_PF_LINEAR_METADATA_MASK 0x02000000L |
28029 | #define GL2C_CTRL2__MDC_UC_TO_C_RO_EN_MASK 0x04000000L |
28030 | #define GL2C_CTRL2__MDC_PF_MIN_PAGE_SIZE_MASK 0x18000000L |
28031 | #define GL2C_CTRL2__MDC_PF_DISABLE_MASK 0xE0000000L |
28032 | //GL2C_ADDR_MATCH_MASK |
28033 | #define GL2C_ADDR_MATCH_MASK__ADDR_MASK__SHIFT 0x0 |
28034 | #define GL2C_ADDR_MATCH_MASK__ADDR_MASK_MASK 0xFFFFFFFFL |
28035 | //GL2C_ADDR_MATCH_SIZE |
28036 | #define GL2C_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT 0x0 |
28037 | #define GL2C_ADDR_MATCH_SIZE__MAX_COUNT_MASK 0x00000007L |
28038 | //GL2C_WBINVL2 |
28039 | #define GL2C_WBINVL2__DONE__SHIFT 0x4 |
28040 | #define GL2C_WBINVL2__DONE_MASK 0x00000010L |
28041 | //GL2C_SOFT_RESET |
28042 | #define GL2C_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0 |
28043 | #define GL2C_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L |
28044 | //GL2C_CM_CTRL0 |
28045 | //GL2C_CM_CTRL1 |
28046 | #define GL2C_CM_CTRL1__BURST_TIMER__SHIFT 0x8 |
28047 | #define GL2C_CM_CTRL1__RVF_SIZE__SHIFT 0x10 |
28048 | #define GL2C_CM_CTRL1__WRITE_COH_MODE__SHIFT 0x17 |
28049 | #define GL2C_CM_CTRL1__MDC_ARB_MODE__SHIFT 0x19 |
28050 | #define GL2C_CM_CTRL1__READ_REQ_ONLY__SHIFT 0x1a |
28051 | #define GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN__SHIFT 0x1b |
28052 | #define GL2C_CM_CTRL1__COMP_TO_SINGLE_EN__SHIFT 0x1c |
28053 | #define GL2C_CM_CTRL1__BURST_MODE__SHIFT 0x1d |
28054 | #define GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER__SHIFT 0x1e |
28055 | #define GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE__SHIFT 0x1f |
28056 | #define GL2C_CM_CTRL1__BURST_TIMER_MASK 0x0000FF00L |
28057 | #define GL2C_CM_CTRL1__RVF_SIZE_MASK 0x000F0000L |
28058 | #define GL2C_CM_CTRL1__WRITE_COH_MODE_MASK 0x01800000L |
28059 | #define GL2C_CM_CTRL1__MDC_ARB_MODE_MASK 0x02000000L |
28060 | #define GL2C_CM_CTRL1__READ_REQ_ONLY_MASK 0x04000000L |
28061 | #define GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN_MASK 0x08000000L |
28062 | #define GL2C_CM_CTRL1__COMP_TO_SINGLE_EN_MASK 0x10000000L |
28063 | #define GL2C_CM_CTRL1__BURST_MODE_MASK 0x20000000L |
28064 | #define GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER_MASK 0x40000000L |
28065 | #define GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE_MASK 0x80000000L |
28066 | //GL2C_CM_STALL |
28067 | #define GL2C_CM_STALL__QUEUE__SHIFT 0x0 |
28068 | #define GL2C_CM_STALL__QUEUE_MASK 0xFFFFFFFFL |
28069 | //GL2C_MDC_PF_FLAG_CTRL |
28070 | #define GL2C_MDC_PF_FLAG_CTRL__TIMER__SHIFT 0x0 |
28071 | #define GL2C_MDC_PF_FLAG_CTRL__TIMER_MASK 0xFFFFFFFFL |
28072 | //GL2C_LB_CTR_CTRL |
28073 | #define GL2C_LB_CTR_CTRL__START__SHIFT 0x0 |
28074 | #define GL2C_LB_CTR_CTRL__LOAD__SHIFT 0x1 |
28075 | #define GL2C_LB_CTR_CTRL__CLEAR__SHIFT 0x2 |
28076 | #define GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x1f |
28077 | #define GL2C_LB_CTR_CTRL__START_MASK 0x00000001L |
28078 | #define GL2C_LB_CTR_CTRL__LOAD_MASK 0x00000002L |
28079 | #define GL2C_LB_CTR_CTRL__CLEAR_MASK 0x00000004L |
28080 | #define GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x80000000L |
28081 | //GL2C_LB_DATA0 |
28082 | #define GL2C_LB_DATA0__DATA__SHIFT 0x0 |
28083 | #define GL2C_LB_DATA0__DATA_MASK 0xFFFFFFFFL |
28084 | //GL2C_LB_DATA1 |
28085 | #define GL2C_LB_DATA1__DATA__SHIFT 0x0 |
28086 | #define GL2C_LB_DATA1__DATA_MASK 0xFFFFFFFFL |
28087 | //GL2C_LB_DATA2 |
28088 | #define GL2C_LB_DATA2__DATA__SHIFT 0x0 |
28089 | #define GL2C_LB_DATA2__DATA_MASK 0xFFFFFFFFL |
28090 | //GL2C_LB_DATA3 |
28091 | #define GL2C_LB_DATA3__DATA__SHIFT 0x0 |
28092 | #define GL2C_LB_DATA3__DATA_MASK 0xFFFFFFFFL |
28093 | //GL2C_LB_CTR_SEL0 |
28094 | #define GL2C_LB_CTR_SEL0__SEL0__SHIFT 0x0 |
28095 | #define GL2C_LB_CTR_SEL0__DIV0__SHIFT 0xf |
28096 | #define GL2C_LB_CTR_SEL0__SEL1__SHIFT 0x10 |
28097 | #define GL2C_LB_CTR_SEL0__DIV1__SHIFT 0x1f |
28098 | #define GL2C_LB_CTR_SEL0__SEL0_MASK 0x000000FFL |
28099 | #define GL2C_LB_CTR_SEL0__DIV0_MASK 0x00008000L |
28100 | #define GL2C_LB_CTR_SEL0__SEL1_MASK 0x00FF0000L |
28101 | #define GL2C_LB_CTR_SEL0__DIV1_MASK 0x80000000L |
28102 | //GL2C_LB_CTR_SEL1 |
28103 | #define GL2C_LB_CTR_SEL1__SEL2__SHIFT 0x0 |
28104 | #define GL2C_LB_CTR_SEL1__DIV2__SHIFT 0xf |
28105 | #define GL2C_LB_CTR_SEL1__SEL3__SHIFT 0x10 |
28106 | #define GL2C_LB_CTR_SEL1__DIV3__SHIFT 0x1f |
28107 | #define GL2C_LB_CTR_SEL1__SEL2_MASK 0x000000FFL |
28108 | #define GL2C_LB_CTR_SEL1__DIV2_MASK 0x00008000L |
28109 | #define GL2C_LB_CTR_SEL1__SEL3_MASK 0x00FF0000L |
28110 | #define GL2C_LB_CTR_SEL1__DIV3_MASK 0x80000000L |
28111 | //GL2A_ADDR_MATCH_CTRL |
28112 | #define GL2A_ADDR_MATCH_CTRL__DISABLE__SHIFT 0x0 |
28113 | #define GL2A_ADDR_MATCH_CTRL__DISABLE_MASK 0xFFFFFFFFL |
28114 | //GL2A_ADDR_MATCH_MASK |
28115 | #define GL2A_ADDR_MATCH_MASK__ADDR_MASK__SHIFT 0x0 |
28116 | #define GL2A_ADDR_MATCH_MASK__ADDR_MASK_MASK 0xFFFFFFFFL |
28117 | //GL2A_ADDR_MATCH_SIZE |
28118 | #define GL2A_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT 0x0 |
28119 | #define GL2A_ADDR_MATCH_SIZE__MAX_COUNT_MASK 0x00000007L |
28120 | //GL2A_PRIORITY_CTRL |
28121 | #define GL2A_PRIORITY_CTRL__DISABLE__SHIFT 0x0 |
28122 | #define GL2A_PRIORITY_CTRL__DISABLE_MASK 0xFFFFFFFFL |
28123 | //GL2_PIPE_STEER_0 |
28124 | #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0__SHIFT 0x0 |
28125 | #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0__SHIFT 0x4 |
28126 | #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0__SHIFT 0x8 |
28127 | #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0__SHIFT 0xc |
28128 | #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1__SHIFT 0x10 |
28129 | #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1__SHIFT 0x14 |
28130 | #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1__SHIFT 0x18 |
28131 | #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1__SHIFT 0x1c |
28132 | #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0_MASK 0x00000007L |
28133 | #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0_MASK 0x00000070L |
28134 | #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0_MASK 0x00000700L |
28135 | #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0_MASK 0x00007000L |
28136 | #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1_MASK 0x00070000L |
28137 | #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1_MASK 0x00700000L |
28138 | #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1_MASK 0x07000000L |
28139 | #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1_MASK 0x70000000L |
28140 | //GL2_PIPE_STEER_1 |
28141 | #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2__SHIFT 0x0 |
28142 | #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2__SHIFT 0x4 |
28143 | #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2__SHIFT 0x8 |
28144 | #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2__SHIFT 0xc |
28145 | #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3__SHIFT 0x10 |
28146 | #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3__SHIFT 0x14 |
28147 | #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3__SHIFT 0x18 |
28148 | #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3__SHIFT 0x1c |
28149 | #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2_MASK 0x00000007L |
28150 | #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2_MASK 0x00000070L |
28151 | #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2_MASK 0x00000700L |
28152 | #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2_MASK 0x00007000L |
28153 | #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3_MASK 0x00070000L |
28154 | #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3_MASK 0x00700000L |
28155 | #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3_MASK 0x07000000L |
28156 | #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3_MASK 0x70000000L |
28157 | |
28158 | |
28159 | // addressBlock: gc_perfddec |
28160 | //CPG_PERFCOUNTER1_LO |
28161 | #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28162 | #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28163 | //CPG_PERFCOUNTER1_HI |
28164 | #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28165 | #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28166 | //CPG_PERFCOUNTER0_LO |
28167 | #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28168 | #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28169 | //CPG_PERFCOUNTER0_HI |
28170 | #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28171 | #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28172 | //CPC_PERFCOUNTER1_LO |
28173 | #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28174 | #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28175 | //CPC_PERFCOUNTER1_HI |
28176 | #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28177 | #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28178 | //CPC_PERFCOUNTER0_LO |
28179 | #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28180 | #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28181 | //CPC_PERFCOUNTER0_HI |
28182 | #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28183 | #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28184 | //CPF_PERFCOUNTER1_LO |
28185 | #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28186 | #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28187 | //CPF_PERFCOUNTER1_HI |
28188 | #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28189 | #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28190 | //CPF_PERFCOUNTER0_LO |
28191 | #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28192 | #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28193 | //CPF_PERFCOUNTER0_HI |
28194 | #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28195 | #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28196 | //CPF_LATENCY_STATS_DATA |
28197 | #define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0 |
28198 | #define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL |
28199 | //CPG_LATENCY_STATS_DATA |
28200 | #define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0 |
28201 | #define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL |
28202 | //CPC_LATENCY_STATS_DATA |
28203 | #define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0 |
28204 | #define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL |
28205 | //GRBM_PERFCOUNTER0_LO |
28206 | #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28207 | #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28208 | //GRBM_PERFCOUNTER0_HI |
28209 | #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28210 | #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28211 | //GRBM_PERFCOUNTER1_LO |
28212 | #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28213 | #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28214 | //GRBM_PERFCOUNTER1_HI |
28215 | #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28216 | #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28217 | //GRBM_SE0_PERFCOUNTER_LO |
28218 | #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28219 | #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28220 | //GRBM_SE0_PERFCOUNTER_HI |
28221 | #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28222 | #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28223 | //GRBM_SE1_PERFCOUNTER_LO |
28224 | #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28225 | #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28226 | //GRBM_SE1_PERFCOUNTER_HI |
28227 | #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28228 | #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28229 | //GRBM_SE2_PERFCOUNTER_LO |
28230 | #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28231 | #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28232 | //GRBM_SE2_PERFCOUNTER_HI |
28233 | #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28234 | #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28235 | //GRBM_SE3_PERFCOUNTER_LO |
28236 | #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28237 | #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28238 | //GRBM_SE3_PERFCOUNTER_HI |
28239 | #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28240 | #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28241 | //GE1_PERFCOUNTER0_LO |
28242 | #define GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28243 | #define GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28244 | //GE1_PERFCOUNTER0_HI |
28245 | #define GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28246 | #define GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28247 | //GE1_PERFCOUNTER1_LO |
28248 | #define GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28249 | #define GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28250 | //GE1_PERFCOUNTER1_HI |
28251 | #define GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28252 | #define GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28253 | //GE1_PERFCOUNTER2_LO |
28254 | #define GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28255 | #define GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28256 | //GE1_PERFCOUNTER2_HI |
28257 | #define GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28258 | #define GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28259 | //GE1_PERFCOUNTER3_LO |
28260 | #define GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28261 | #define GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28262 | //GE1_PERFCOUNTER3_HI |
28263 | #define GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28264 | #define GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28265 | //GE2_DIST_PERFCOUNTER0_LO |
28266 | #define GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28267 | #define GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28268 | //GE2_DIST_PERFCOUNTER0_HI |
28269 | #define GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28270 | #define GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28271 | //GE2_DIST_PERFCOUNTER1_LO |
28272 | #define GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28273 | #define GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28274 | //GE2_DIST_PERFCOUNTER1_HI |
28275 | #define GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28276 | #define GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28277 | //GE2_DIST_PERFCOUNTER2_LO |
28278 | #define GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28279 | #define GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28280 | //GE2_DIST_PERFCOUNTER2_HI |
28281 | #define GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28282 | #define GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28283 | //GE2_DIST_PERFCOUNTER3_LO |
28284 | #define GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28285 | #define GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28286 | //GE2_DIST_PERFCOUNTER3_HI |
28287 | #define GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28288 | #define GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28289 | //GE2_SE_PERFCOUNTER0_LO |
28290 | #define GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28291 | #define GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28292 | //GE2_SE_PERFCOUNTER0_HI |
28293 | #define GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28294 | #define GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28295 | //GE2_SE_PERFCOUNTER1_LO |
28296 | #define GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28297 | #define GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28298 | //GE2_SE_PERFCOUNTER1_HI |
28299 | #define GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28300 | #define GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28301 | //GE2_SE_PERFCOUNTER2_LO |
28302 | #define GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28303 | #define GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28304 | //GE2_SE_PERFCOUNTER2_HI |
28305 | #define GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28306 | #define GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28307 | //GE2_SE_PERFCOUNTER3_LO |
28308 | #define GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28309 | #define GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28310 | //GE2_SE_PERFCOUNTER3_HI |
28311 | #define GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28312 | #define GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28313 | //PA_SU_PERFCOUNTER0_LO |
28314 | #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28315 | #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28316 | //PA_SU_PERFCOUNTER0_HI |
28317 | #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28318 | #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28319 | //PA_SU_PERFCOUNTER1_LO |
28320 | #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28321 | #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28322 | //PA_SU_PERFCOUNTER1_HI |
28323 | #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28324 | #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28325 | //PA_SU_PERFCOUNTER2_LO |
28326 | #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28327 | #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28328 | //PA_SU_PERFCOUNTER2_HI |
28329 | #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28330 | #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28331 | //PA_SU_PERFCOUNTER3_LO |
28332 | #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28333 | #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28334 | //PA_SU_PERFCOUNTER3_HI |
28335 | #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28336 | #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28337 | //PA_SC_PERFCOUNTER0_LO |
28338 | #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28339 | #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28340 | //PA_SC_PERFCOUNTER0_HI |
28341 | #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28342 | #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28343 | //PA_SC_PERFCOUNTER1_LO |
28344 | #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28345 | #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28346 | //PA_SC_PERFCOUNTER1_HI |
28347 | #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28348 | #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28349 | //PA_SC_PERFCOUNTER2_LO |
28350 | #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28351 | #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28352 | //PA_SC_PERFCOUNTER2_HI |
28353 | #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28354 | #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28355 | //PA_SC_PERFCOUNTER3_LO |
28356 | #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28357 | #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28358 | //PA_SC_PERFCOUNTER3_HI |
28359 | #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28360 | #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28361 | //PA_SC_PERFCOUNTER4_LO |
28362 | #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28363 | #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28364 | //PA_SC_PERFCOUNTER4_HI |
28365 | #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28366 | #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28367 | //PA_SC_PERFCOUNTER5_LO |
28368 | #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28369 | #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28370 | //PA_SC_PERFCOUNTER5_HI |
28371 | #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28372 | #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28373 | //PA_SC_PERFCOUNTER6_LO |
28374 | #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28375 | #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28376 | //PA_SC_PERFCOUNTER6_HI |
28377 | #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28378 | #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28379 | //PA_SC_PERFCOUNTER7_LO |
28380 | #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28381 | #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28382 | //PA_SC_PERFCOUNTER7_HI |
28383 | #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28384 | #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28385 | //SPI_PERFCOUNTER0_HI |
28386 | #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28387 | #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28388 | //SPI_PERFCOUNTER0_LO |
28389 | #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28390 | #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28391 | //SPI_PERFCOUNTER1_HI |
28392 | #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28393 | #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28394 | //SPI_PERFCOUNTER1_LO |
28395 | #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28396 | #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28397 | //SPI_PERFCOUNTER2_HI |
28398 | #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28399 | #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28400 | //SPI_PERFCOUNTER2_LO |
28401 | #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28402 | #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28403 | //SPI_PERFCOUNTER3_HI |
28404 | #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28405 | #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28406 | //SPI_PERFCOUNTER3_LO |
28407 | #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28408 | #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28409 | //SPI_PERFCOUNTER4_HI |
28410 | #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28411 | #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28412 | //SPI_PERFCOUNTER4_LO |
28413 | #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28414 | #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28415 | //SPI_PERFCOUNTER5_HI |
28416 | #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28417 | #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28418 | //SPI_PERFCOUNTER5_LO |
28419 | #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28420 | #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28421 | //SQ_PERFCOUNTER0_LO |
28422 | #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28423 | #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28424 | //SQ_PERFCOUNTER0_HI |
28425 | #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28426 | #define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28427 | //SQ_PERFCOUNTER1_LO |
28428 | #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28429 | #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28430 | //SQ_PERFCOUNTER1_HI |
28431 | #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28432 | #define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28433 | //SQ_PERFCOUNTER2_LO |
28434 | #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28435 | #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28436 | //SQ_PERFCOUNTER2_HI |
28437 | #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28438 | #define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28439 | //SQ_PERFCOUNTER3_LO |
28440 | #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28441 | #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28442 | //SQ_PERFCOUNTER3_HI |
28443 | #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28444 | #define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28445 | //SQ_PERFCOUNTER4_LO |
28446 | #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28447 | #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28448 | //SQ_PERFCOUNTER4_HI |
28449 | #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28450 | #define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28451 | //SQ_PERFCOUNTER5_LO |
28452 | #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28453 | #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28454 | //SQ_PERFCOUNTER5_HI |
28455 | #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28456 | #define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28457 | //SQ_PERFCOUNTER6_LO |
28458 | #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28459 | #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28460 | //SQ_PERFCOUNTER6_HI |
28461 | #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28462 | #define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28463 | //SQ_PERFCOUNTER7_LO |
28464 | #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28465 | #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28466 | //SQ_PERFCOUNTER7_HI |
28467 | #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28468 | #define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28469 | //SQ_PERFCOUNTER8_LO |
28470 | #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28471 | #define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28472 | //SQ_PERFCOUNTER8_HI |
28473 | #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28474 | #define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28475 | //SQ_PERFCOUNTER9_LO |
28476 | #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28477 | #define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28478 | //SQ_PERFCOUNTER9_HI |
28479 | #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28480 | #define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28481 | //SQ_PERFCOUNTER10_LO |
28482 | #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28483 | #define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28484 | //SQ_PERFCOUNTER10_HI |
28485 | #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28486 | #define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28487 | //SQ_PERFCOUNTER11_LO |
28488 | #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28489 | #define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28490 | //SQ_PERFCOUNTER11_HI |
28491 | #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28492 | #define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28493 | //SQ_PERFCOUNTER12_LO |
28494 | #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28495 | #define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28496 | //SQ_PERFCOUNTER12_HI |
28497 | #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28498 | #define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28499 | //SQ_PERFCOUNTER13_LO |
28500 | #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28501 | #define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28502 | //SQ_PERFCOUNTER13_HI |
28503 | #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28504 | #define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28505 | //SQ_PERFCOUNTER14_LO |
28506 | #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28507 | #define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28508 | //SQ_PERFCOUNTER14_HI |
28509 | #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28510 | #define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28511 | //SQ_PERFCOUNTER15_LO |
28512 | #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28513 | #define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28514 | //SQ_PERFCOUNTER15_HI |
28515 | #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28516 | #define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28517 | //SX_PERFCOUNTER0_LO |
28518 | #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28519 | #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28520 | //SX_PERFCOUNTER0_HI |
28521 | #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28522 | #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28523 | //SX_PERFCOUNTER1_LO |
28524 | #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28525 | #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28526 | //SX_PERFCOUNTER1_HI |
28527 | #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28528 | #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28529 | //SX_PERFCOUNTER2_LO |
28530 | #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28531 | #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28532 | //SX_PERFCOUNTER2_HI |
28533 | #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28534 | #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28535 | //SX_PERFCOUNTER3_LO |
28536 | #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28537 | #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28538 | //SX_PERFCOUNTER3_HI |
28539 | #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28540 | #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28541 | //GCEA_PERFCOUNTER2_LO |
28542 | #define GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28543 | #define GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28544 | //GCEA_PERFCOUNTER2_HI |
28545 | #define GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28546 | #define GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28547 | //GCEA_PERFCOUNTER_LO |
28548 | #define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
28549 | #define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
28550 | //GCEA_PERFCOUNTER_HI |
28551 | #define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
28552 | #define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
28553 | #define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
28554 | #define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
28555 | //GDS_PERFCOUNTER0_LO |
28556 | #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28557 | #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28558 | //GDS_PERFCOUNTER0_HI |
28559 | #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28560 | #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28561 | //GDS_PERFCOUNTER1_LO |
28562 | #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28563 | #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28564 | //GDS_PERFCOUNTER1_HI |
28565 | #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28566 | #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28567 | //GDS_PERFCOUNTER2_LO |
28568 | #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28569 | #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28570 | //GDS_PERFCOUNTER2_HI |
28571 | #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28572 | #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28573 | //GDS_PERFCOUNTER3_LO |
28574 | #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28575 | #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28576 | //GDS_PERFCOUNTER3_HI |
28577 | #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28578 | #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28579 | //TA_PERFCOUNTER0_LO |
28580 | #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28581 | #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28582 | //TA_PERFCOUNTER0_HI |
28583 | #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28584 | #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28585 | //TA_PERFCOUNTER1_LO |
28586 | #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28587 | #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28588 | //TA_PERFCOUNTER1_HI |
28589 | #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28590 | #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28591 | //TD_PERFCOUNTER0_LO |
28592 | #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28593 | #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28594 | //TD_PERFCOUNTER0_HI |
28595 | #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28596 | #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28597 | //TD_PERFCOUNTER1_LO |
28598 | #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28599 | #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28600 | //TD_PERFCOUNTER1_HI |
28601 | #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28602 | #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28603 | //TCP_PERFCOUNTER0_LO |
28604 | #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28605 | #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28606 | //TCP_PERFCOUNTER0_HI |
28607 | #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28608 | #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28609 | //TCP_PERFCOUNTER1_LO |
28610 | #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28611 | #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28612 | //TCP_PERFCOUNTER1_HI |
28613 | #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28614 | #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28615 | //TCP_PERFCOUNTER2_LO |
28616 | #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28617 | #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28618 | //TCP_PERFCOUNTER2_HI |
28619 | #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28620 | #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28621 | //TCP_PERFCOUNTER3_LO |
28622 | #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28623 | #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28624 | //TCP_PERFCOUNTER3_HI |
28625 | #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28626 | #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28627 | //GL2C_PERFCOUNTER0_LO |
28628 | #define GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28629 | #define GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28630 | //GL2C_PERFCOUNTER0_HI |
28631 | #define GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28632 | #define GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28633 | //GL2C_PERFCOUNTER1_LO |
28634 | #define GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28635 | #define GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28636 | //GL2C_PERFCOUNTER1_HI |
28637 | #define GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28638 | #define GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28639 | //GL2C_PERFCOUNTER2_LO |
28640 | #define GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28641 | #define GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28642 | //GL2C_PERFCOUNTER2_HI |
28643 | #define GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28644 | #define GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28645 | //GL2C_PERFCOUNTER3_LO |
28646 | #define GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28647 | #define GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28648 | //GL2C_PERFCOUNTER3_HI |
28649 | #define GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28650 | #define GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28651 | //GL2A_PERFCOUNTER0_LO |
28652 | #define GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28653 | #define GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28654 | //GL2A_PERFCOUNTER0_HI |
28655 | #define GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28656 | #define GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28657 | //GL2A_PERFCOUNTER1_LO |
28658 | #define GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28659 | #define GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28660 | //GL2A_PERFCOUNTER1_HI |
28661 | #define GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28662 | #define GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28663 | //GL2A_PERFCOUNTER2_LO |
28664 | #define GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28665 | #define GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28666 | //GL2A_PERFCOUNTER2_HI |
28667 | #define GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28668 | #define GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28669 | //GL2A_PERFCOUNTER3_LO |
28670 | #define GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28671 | #define GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28672 | //GL2A_PERFCOUNTER3_HI |
28673 | #define GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28674 | #define GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28675 | //GL1C_PERFCOUNTER0_LO |
28676 | #define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28677 | #define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28678 | //GL1C_PERFCOUNTER0_HI |
28679 | #define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28680 | #define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28681 | //GL1C_PERFCOUNTER1_LO |
28682 | #define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28683 | #define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28684 | //GL1C_PERFCOUNTER1_HI |
28685 | #define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28686 | #define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28687 | //GL1C_PERFCOUNTER2_LO |
28688 | #define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28689 | #define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28690 | //GL1C_PERFCOUNTER2_HI |
28691 | #define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28692 | #define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28693 | //GL1C_PERFCOUNTER3_LO |
28694 | #define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28695 | #define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28696 | //GL1C_PERFCOUNTER3_HI |
28697 | #define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28698 | #define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28699 | //CHC_PERFCOUNTER0_LO |
28700 | #define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28701 | #define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28702 | //CHC_PERFCOUNTER0_HI |
28703 | #define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28704 | #define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28705 | //CHC_PERFCOUNTER1_LO |
28706 | #define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28707 | #define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28708 | //CHC_PERFCOUNTER1_HI |
28709 | #define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28710 | #define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28711 | //CHC_PERFCOUNTER2_LO |
28712 | #define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28713 | #define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28714 | //CHC_PERFCOUNTER2_HI |
28715 | #define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28716 | #define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28717 | //CHC_PERFCOUNTER3_LO |
28718 | #define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28719 | #define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28720 | //CHC_PERFCOUNTER3_HI |
28721 | #define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28722 | #define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28723 | //CHCG_PERFCOUNTER0_LO |
28724 | #define CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28725 | #define CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28726 | //CHCG_PERFCOUNTER0_HI |
28727 | #define CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28728 | #define CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28729 | //CHCG_PERFCOUNTER1_LO |
28730 | #define CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28731 | #define CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28732 | //CHCG_PERFCOUNTER1_HI |
28733 | #define CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28734 | #define CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28735 | //CHCG_PERFCOUNTER2_LO |
28736 | #define CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28737 | #define CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28738 | //CHCG_PERFCOUNTER2_HI |
28739 | #define CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28740 | #define CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28741 | //CHCG_PERFCOUNTER3_LO |
28742 | #define CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28743 | #define CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28744 | //CHCG_PERFCOUNTER3_HI |
28745 | #define CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28746 | #define CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28747 | //CB_PERFCOUNTER0_LO |
28748 | #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28749 | #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28750 | //CB_PERFCOUNTER0_HI |
28751 | #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28752 | #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28753 | //CB_PERFCOUNTER1_LO |
28754 | #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28755 | #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28756 | //CB_PERFCOUNTER1_HI |
28757 | #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28758 | #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28759 | //CB_PERFCOUNTER2_LO |
28760 | #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28761 | #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28762 | //CB_PERFCOUNTER2_HI |
28763 | #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28764 | #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28765 | //CB_PERFCOUNTER3_LO |
28766 | #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28767 | #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28768 | //CB_PERFCOUNTER3_HI |
28769 | #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28770 | #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28771 | //DB_PERFCOUNTER0_LO |
28772 | #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28773 | #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28774 | //DB_PERFCOUNTER0_HI |
28775 | #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28776 | #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28777 | //DB_PERFCOUNTER1_LO |
28778 | #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28779 | #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28780 | //DB_PERFCOUNTER1_HI |
28781 | #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28782 | #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28783 | //DB_PERFCOUNTER2_LO |
28784 | #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28785 | #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28786 | //DB_PERFCOUNTER2_HI |
28787 | #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28788 | #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28789 | //DB_PERFCOUNTER3_LO |
28790 | #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28791 | #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28792 | //DB_PERFCOUNTER3_HI |
28793 | #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28794 | #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28795 | //RLC_PERFCOUNTER0_LO |
28796 | #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28797 | #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28798 | //RLC_PERFCOUNTER0_HI |
28799 | #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28800 | #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28801 | //RLC_PERFCOUNTER1_LO |
28802 | #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28803 | #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28804 | //RLC_PERFCOUNTER1_HI |
28805 | #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28806 | #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28807 | //RMI_PERFCOUNTER0_LO |
28808 | #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28809 | #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28810 | //RMI_PERFCOUNTER0_HI |
28811 | #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28812 | #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28813 | //RMI_PERFCOUNTER1_LO |
28814 | #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28815 | #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28816 | //RMI_PERFCOUNTER1_HI |
28817 | #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28818 | #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28819 | //RMI_PERFCOUNTER2_LO |
28820 | #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28821 | #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28822 | //RMI_PERFCOUNTER2_HI |
28823 | #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28824 | #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28825 | //RMI_PERFCOUNTER3_LO |
28826 | #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28827 | #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28828 | //RMI_PERFCOUNTER3_HI |
28829 | #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28830 | #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28831 | //UTCL1_PERFCOUNTER0_LO |
28832 | #define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28833 | #define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28834 | //UTCL1_PERFCOUNTER0_HI |
28835 | #define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28836 | #define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28837 | //UTCL1_PERFCOUNTER1_LO |
28838 | #define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28839 | #define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28840 | //UTCL1_PERFCOUNTER1_HI |
28841 | #define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28842 | #define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28843 | //GCR_PERFCOUNTER0_LO |
28844 | #define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28845 | #define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28846 | //GCR_PERFCOUNTER0_HI |
28847 | #define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28848 | #define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28849 | //GCR_PERFCOUNTER1_LO |
28850 | #define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28851 | #define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28852 | //GCR_PERFCOUNTER1_HI |
28853 | #define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28854 | #define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28855 | //PA_PH_PERFCOUNTER0_LO |
28856 | #define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28857 | #define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28858 | //PA_PH_PERFCOUNTER0_HI |
28859 | #define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28860 | #define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28861 | //PA_PH_PERFCOUNTER1_LO |
28862 | #define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28863 | #define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28864 | //PA_PH_PERFCOUNTER1_HI |
28865 | #define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28866 | #define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28867 | //PA_PH_PERFCOUNTER2_LO |
28868 | #define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28869 | #define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28870 | //PA_PH_PERFCOUNTER2_HI |
28871 | #define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28872 | #define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28873 | //PA_PH_PERFCOUNTER3_LO |
28874 | #define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28875 | #define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28876 | //PA_PH_PERFCOUNTER3_HI |
28877 | #define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28878 | #define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28879 | //PA_PH_PERFCOUNTER4_LO |
28880 | #define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28881 | #define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28882 | //PA_PH_PERFCOUNTER4_HI |
28883 | #define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28884 | #define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28885 | //PA_PH_PERFCOUNTER5_LO |
28886 | #define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28887 | #define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28888 | //PA_PH_PERFCOUNTER5_HI |
28889 | #define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28890 | #define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28891 | //PA_PH_PERFCOUNTER6_LO |
28892 | #define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28893 | #define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28894 | //PA_PH_PERFCOUNTER6_HI |
28895 | #define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28896 | #define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28897 | //PA_PH_PERFCOUNTER7_LO |
28898 | #define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28899 | #define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28900 | //PA_PH_PERFCOUNTER7_HI |
28901 | #define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28902 | #define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28903 | //GL1A_PERFCOUNTER0_LO |
28904 | #define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28905 | #define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28906 | //GL1A_PERFCOUNTER0_HI |
28907 | #define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28908 | #define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28909 | //GL1A_PERFCOUNTER1_LO |
28910 | #define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28911 | #define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28912 | //GL1A_PERFCOUNTER1_HI |
28913 | #define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28914 | #define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28915 | //GL1A_PERFCOUNTER2_LO |
28916 | #define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28917 | #define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28918 | //GL1A_PERFCOUNTER2_HI |
28919 | #define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28920 | #define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28921 | //GL1A_PERFCOUNTER3_LO |
28922 | #define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28923 | #define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28924 | //GL1A_PERFCOUNTER3_HI |
28925 | #define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28926 | #define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28927 | //CHA_PERFCOUNTER0_LO |
28928 | #define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28929 | #define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28930 | //CHA_PERFCOUNTER0_HI |
28931 | #define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28932 | #define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28933 | //CHA_PERFCOUNTER1_LO |
28934 | #define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28935 | #define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28936 | //CHA_PERFCOUNTER1_HI |
28937 | #define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28938 | #define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28939 | //CHA_PERFCOUNTER2_LO |
28940 | #define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28941 | #define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28942 | //CHA_PERFCOUNTER2_HI |
28943 | #define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28944 | #define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28945 | //CHA_PERFCOUNTER3_LO |
28946 | #define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28947 | #define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28948 | //CHA_PERFCOUNTER3_HI |
28949 | #define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28950 | #define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28951 | //GUS_PERFCOUNTER2_LO |
28952 | #define GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28953 | #define GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28954 | //GUS_PERFCOUNTER2_HI |
28955 | #define GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28956 | #define GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28957 | //GUS_PERFCOUNTER_LO |
28958 | #define GUS_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
28959 | #define GUS_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
28960 | //GUS_PERFCOUNTER_HI |
28961 | #define GUS_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
28962 | #define GUS_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
28963 | #define GUS_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
28964 | #define GUS_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
28965 | |
28966 | |
28967 | // addressBlock: gc_gcvml2prdec |
28968 | //GCMC_VM_L2_PERFCOUNTER_LO |
28969 | #define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
28970 | #define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
28971 | //GCMC_VM_L2_PERFCOUNTER_HI |
28972 | #define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
28973 | #define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
28974 | #define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
28975 | #define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
28976 | //GCUTCL2_PERFCOUNTER_LO |
28977 | #define GCUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
28978 | #define GCUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
28979 | //GCUTCL2_PERFCOUNTER_HI |
28980 | #define GCUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
28981 | #define GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
28982 | #define GCUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
28983 | #define GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
28984 | |
28985 | |
28986 | // addressBlock: gc_gcvml2perfddec |
28987 | //GCVML2_PERFCOUNTER2_0_LO |
28988 | #define GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28989 | #define GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28990 | //GCVML2_PERFCOUNTER2_1_LO |
28991 | #define GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
28992 | #define GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
28993 | //GCVML2_PERFCOUNTER2_0_HI |
28994 | #define GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28995 | #define GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28996 | //GCVML2_PERFCOUNTER2_1_HI |
28997 | #define GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
28998 | #define GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
28999 | |
29000 | |
29001 | // addressBlock: gc_sdma0_sdma0perfddec |
29002 | //SDMA0_PERFCNT_PERFCOUNTER_LO |
29003 | #define SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
29004 | #define SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
29005 | //SDMA0_PERFCNT_PERFCOUNTER_HI |
29006 | #define SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
29007 | #define SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
29008 | #define SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
29009 | #define SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
29010 | //SDMA0_PERFCOUNTER0_LO |
29011 | #define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
29012 | #define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
29013 | //SDMA0_PERFCOUNTER0_HI |
29014 | #define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
29015 | #define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
29016 | //SDMA0_PERFCOUNTER1_LO |
29017 | #define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
29018 | #define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
29019 | //SDMA0_PERFCOUNTER1_HI |
29020 | #define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
29021 | #define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
29022 | |
29023 | |
29024 | // addressBlock: gc_sdma1_sdma1perfddec |
29025 | //SDMA1_PERFCNT_PERFCOUNTER_LO |
29026 | #define SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
29027 | #define SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
29028 | //SDMA1_PERFCNT_PERFCOUNTER_HI |
29029 | #define SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
29030 | #define SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
29031 | #define SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
29032 | #define SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
29033 | //SDMA1_PERFCOUNTER0_LO |
29034 | #define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
29035 | #define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
29036 | //SDMA1_PERFCOUNTER0_HI |
29037 | #define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
29038 | #define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
29039 | //SDMA1_PERFCOUNTER1_LO |
29040 | #define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
29041 | #define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
29042 | //SDMA1_PERFCOUNTER1_HI |
29043 | #define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
29044 | #define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
29045 | |
29046 | |
29047 | // addressBlock: gc_sdma2_sdma2perfddec |
29048 | //SDMA2_PERFCNT_PERFCOUNTER_LO |
29049 | #define SDMA2_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
29050 | #define SDMA2_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
29051 | //SDMA2_PERFCNT_PERFCOUNTER_HI |
29052 | #define SDMA2_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
29053 | #define SDMA2_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
29054 | #define SDMA2_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
29055 | #define SDMA2_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
29056 | //SDMA2_PERFCOUNTER0_LO |
29057 | #define SDMA2_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
29058 | #define SDMA2_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
29059 | //SDMA2_PERFCOUNTER0_HI |
29060 | #define SDMA2_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
29061 | #define SDMA2_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
29062 | //SDMA2_PERFCOUNTER1_LO |
29063 | #define SDMA2_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
29064 | #define SDMA2_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
29065 | //SDMA2_PERFCOUNTER1_HI |
29066 | #define SDMA2_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
29067 | #define SDMA2_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
29068 | |
29069 | |
29070 | // addressBlock: gc_sdma3_sdma3perfddec |
29071 | //SDMA3_PERFCNT_PERFCOUNTER_LO |
29072 | #define SDMA3_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
29073 | #define SDMA3_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
29074 | //SDMA3_PERFCNT_PERFCOUNTER_HI |
29075 | #define SDMA3_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
29076 | #define SDMA3_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
29077 | #define SDMA3_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
29078 | #define SDMA3_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
29079 | //SDMA3_PERFCOUNTER0_LO |
29080 | #define SDMA3_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
29081 | #define SDMA3_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
29082 | //SDMA3_PERFCOUNTER0_HI |
29083 | #define SDMA3_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
29084 | #define SDMA3_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
29085 | //SDMA3_PERFCOUNTER1_LO |
29086 | #define SDMA3_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
29087 | #define SDMA3_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
29088 | //SDMA3_PERFCOUNTER1_HI |
29089 | #define SDMA3_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
29090 | #define SDMA3_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
29091 | |
29092 | |
29093 | // addressBlock: gc_perfsdec |
29094 | //CPG_PERFCOUNTER1_SELECT |
29095 | #define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
29096 | #define CPG_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
29097 | #define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
29098 | #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 |
29099 | #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c |
29100 | #define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
29101 | #define CPG_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29102 | #define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
29103 | #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L |
29104 | #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L |
29105 | //CPG_PERFCOUNTER0_SELECT1 |
29106 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
29107 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
29108 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 |
29109 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c |
29110 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29111 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29112 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L |
29113 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L |
29114 | //CPG_PERFCOUNTER0_SELECT |
29115 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
29116 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
29117 | #define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
29118 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 |
29119 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c |
29120 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
29121 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29122 | #define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
29123 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L |
29124 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L |
29125 | //CPC_PERFCOUNTER1_SELECT |
29126 | #define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
29127 | #define CPC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
29128 | #define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
29129 | #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 |
29130 | #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c |
29131 | #define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
29132 | #define CPC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29133 | #define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
29134 | #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L |
29135 | #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L |
29136 | //CPC_PERFCOUNTER0_SELECT1 |
29137 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
29138 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
29139 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 |
29140 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c |
29141 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29142 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29143 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L |
29144 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L |
29145 | //CPF_PERFCOUNTER1_SELECT |
29146 | #define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
29147 | #define CPF_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
29148 | #define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
29149 | #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 |
29150 | #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c |
29151 | #define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
29152 | #define CPF_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29153 | #define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
29154 | #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L |
29155 | #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L |
29156 | //CPF_PERFCOUNTER0_SELECT1 |
29157 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
29158 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
29159 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 |
29160 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c |
29161 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29162 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29163 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L |
29164 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L |
29165 | //CPF_PERFCOUNTER0_SELECT |
29166 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
29167 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
29168 | #define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
29169 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 |
29170 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c |
29171 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
29172 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29173 | #define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
29174 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L |
29175 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L |
29176 | //CP_PERFMON_CNTL |
29177 | #define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
29178 | #define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 |
29179 | #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 |
29180 | #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa |
29181 | #define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL |
29182 | #define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L |
29183 | #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L |
29184 | #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L |
29185 | //CPC_PERFCOUNTER0_SELECT |
29186 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
29187 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
29188 | #define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
29189 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 |
29190 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c |
29191 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
29192 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29193 | #define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
29194 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L |
29195 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L |
29196 | //CPF_TC_PERF_COUNTER_WINDOW_SELECT |
29197 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 |
29198 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e |
29199 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f |
29200 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L |
29201 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L |
29202 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L |
29203 | //CPG_TC_PERF_COUNTER_WINDOW_SELECT |
29204 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 |
29205 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e |
29206 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f |
29207 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL |
29208 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L |
29209 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L |
29210 | //CPF_LATENCY_STATS_SELECT |
29211 | #define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 |
29212 | #define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e |
29213 | #define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f |
29214 | #define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL |
29215 | #define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L |
29216 | #define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L |
29217 | //CPG_LATENCY_STATS_SELECT |
29218 | #define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 |
29219 | #define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e |
29220 | #define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f |
29221 | #define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL |
29222 | #define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L |
29223 | #define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L |
29224 | //CPC_LATENCY_STATS_SELECT |
29225 | #define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 |
29226 | #define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e |
29227 | #define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f |
29228 | #define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL |
29229 | #define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L |
29230 | #define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L |
29231 | //CP_DRAW_OBJECT |
29232 | #define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 |
29233 | #define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL |
29234 | //CP_DRAW_OBJECT_COUNTER |
29235 | #define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 |
29236 | #define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL |
29237 | //CP_DRAW_WINDOW_MASK_HI |
29238 | #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 |
29239 | #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL |
29240 | //CP_DRAW_WINDOW_HI |
29241 | #define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 |
29242 | #define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL |
29243 | //CP_DRAW_WINDOW_LO |
29244 | #define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 |
29245 | #define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 |
29246 | #define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL |
29247 | #define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L |
29248 | //CP_DRAW_WINDOW_CNTL |
29249 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 |
29250 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 |
29251 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 |
29252 | #define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 |
29253 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L |
29254 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L |
29255 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L |
29256 | #define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L |
29257 | //GRBM_PERFCOUNTER0_SELECT |
29258 | #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
29259 | #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
29260 | #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
29261 | #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
29262 | #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe |
29263 | #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
29264 | #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
29265 | #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
29266 | #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 |
29267 | #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
29268 | #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
29269 | #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
29270 | #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
29271 | #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
29272 | #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a |
29273 | #define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b |
29274 | #define GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c |
29275 | #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d |
29276 | #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e |
29277 | #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f |
29278 | #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL |
29279 | #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
29280 | #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
29281 | #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
29282 | #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L |
29283 | #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
29284 | #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
29285 | #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
29286 | #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L |
29287 | #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
29288 | #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
29289 | #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
29290 | #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
29291 | #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
29292 | #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L |
29293 | #define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L |
29294 | #define GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L |
29295 | #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L |
29296 | #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L |
29297 | #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L |
29298 | //GRBM_PERFCOUNTER1_SELECT |
29299 | #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
29300 | #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
29301 | #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
29302 | #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
29303 | #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe |
29304 | #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
29305 | #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
29306 | #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
29307 | #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 |
29308 | #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
29309 | #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
29310 | #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
29311 | #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
29312 | #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
29313 | #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a |
29314 | #define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b |
29315 | #define GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c |
29316 | #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d |
29317 | #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e |
29318 | #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f |
29319 | #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL |
29320 | #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
29321 | #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
29322 | #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
29323 | #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L |
29324 | #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
29325 | #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
29326 | #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
29327 | #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L |
29328 | #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
29329 | #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
29330 | #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
29331 | #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
29332 | #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
29333 | #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L |
29334 | #define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L |
29335 | #define GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L |
29336 | #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L |
29337 | #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L |
29338 | #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L |
29339 | //GRBM_SE0_PERFCOUNTER_SELECT |
29340 | #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
29341 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
29342 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
29343 | #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
29344 | #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
29345 | #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
29346 | #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
29347 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
29348 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
29349 | #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
29350 | #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
29351 | #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
29352 | #define GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 |
29353 | #define GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
29354 | #define GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
29355 | #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
29356 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
29357 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
29358 | #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
29359 | #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
29360 | #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
29361 | #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
29362 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
29363 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
29364 | #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
29365 | #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
29366 | #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
29367 | #define GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L |
29368 | #define GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
29369 | #define GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
29370 | //GRBM_SE1_PERFCOUNTER_SELECT |
29371 | #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
29372 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
29373 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
29374 | #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
29375 | #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
29376 | #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
29377 | #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
29378 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
29379 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
29380 | #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
29381 | #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
29382 | #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
29383 | #define GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 |
29384 | #define GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
29385 | #define GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
29386 | #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
29387 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
29388 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
29389 | #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
29390 | #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
29391 | #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
29392 | #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
29393 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
29394 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
29395 | #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
29396 | #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
29397 | #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
29398 | #define GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L |
29399 | #define GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
29400 | #define GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
29401 | //GRBM_SE2_PERFCOUNTER_SELECT |
29402 | #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
29403 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
29404 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
29405 | #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
29406 | #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
29407 | #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
29408 | #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
29409 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
29410 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
29411 | #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
29412 | #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
29413 | #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
29414 | #define GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 |
29415 | #define GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
29416 | #define GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
29417 | #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
29418 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
29419 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
29420 | #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
29421 | #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
29422 | #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
29423 | #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
29424 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
29425 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
29426 | #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
29427 | #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
29428 | #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
29429 | #define GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L |
29430 | #define GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
29431 | #define GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
29432 | //GRBM_SE3_PERFCOUNTER_SELECT |
29433 | #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
29434 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
29435 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
29436 | #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
29437 | #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
29438 | #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
29439 | #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
29440 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
29441 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
29442 | #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
29443 | #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
29444 | #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
29445 | #define GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 |
29446 | #define GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
29447 | #define GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
29448 | #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
29449 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
29450 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
29451 | #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
29452 | #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
29453 | #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
29454 | #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
29455 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
29456 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
29457 | #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
29458 | #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
29459 | #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
29460 | #define GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L |
29461 | #define GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
29462 | #define GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
29463 | //GRBM_PERFCOUNTER0_SELECT_HI |
29464 | #define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1 |
29465 | #define GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT 0x2 |
29466 | #define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT 0x3 |
29467 | #define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT 0x4 |
29468 | #define GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT 0x5 |
29469 | #define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT 0x6 |
29470 | #define GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT 0x7 |
29471 | #define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x8 |
29472 | #define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00000002L |
29473 | #define GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK 0x00000004L |
29474 | #define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK 0x00000008L |
29475 | #define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK 0x00000010L |
29476 | #define GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK 0x00000020L |
29477 | #define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK 0x00000040L |
29478 | #define GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK 0x00000080L |
29479 | #define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000100L |
29480 | //GRBM_PERFCOUNTER1_SELECT_HI |
29481 | #define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1 |
29482 | #define GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT 0x2 |
29483 | #define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT 0x3 |
29484 | #define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT 0x4 |
29485 | #define GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT 0x5 |
29486 | #define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT 0x6 |
29487 | #define GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT 0x7 |
29488 | #define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x8 |
29489 | #define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00000002L |
29490 | #define GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK 0x00000004L |
29491 | #define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK 0x00000008L |
29492 | #define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK 0x00000010L |
29493 | #define GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK 0x00000020L |
29494 | #define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK 0x00000040L |
29495 | #define GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK 0x00000080L |
29496 | #define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000100L |
29497 | //GE1_PERFCOUNTER0_SELECT |
29498 | #define GE1_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 |
29499 | #define GE1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
29500 | #define GE1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
29501 | #define GE1_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x18 |
29502 | #define GE1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x1c |
29503 | #define GE1_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL |
29504 | #define GE1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29505 | #define GE1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
29506 | #define GE1_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0x0F000000L |
29507 | #define GE1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xF0000000L |
29508 | //GE1_PERFCOUNTER0_SELECT1 |
29509 | #define GE1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
29510 | #define GE1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
29511 | #define GE1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
29512 | #define GE1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
29513 | #define GE1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29514 | #define GE1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29515 | #define GE1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
29516 | #define GE1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
29517 | //GE1_PERFCOUNTER1_SELECT |
29518 | #define GE1_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 |
29519 | #define GE1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
29520 | #define GE1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
29521 | #define GE1_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x18 |
29522 | #define GE1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x1c |
29523 | #define GE1_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL |
29524 | #define GE1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29525 | #define GE1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
29526 | #define GE1_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0x0F000000L |
29527 | #define GE1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xF0000000L |
29528 | //GE1_PERFCOUNTER1_SELECT1 |
29529 | #define GE1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
29530 | #define GE1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
29531 | #define GE1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 |
29532 | #define GE1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c |
29533 | #define GE1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29534 | #define GE1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29535 | #define GE1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L |
29536 | #define GE1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L |
29537 | //GE1_PERFCOUNTER2_SELECT |
29538 | #define GE1_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 |
29539 | #define GE1_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
29540 | #define GE1_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
29541 | #define GE1_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x18 |
29542 | #define GE1_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x1c |
29543 | #define GE1_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL |
29544 | #define GE1_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29545 | #define GE1_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
29546 | #define GE1_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0x0F000000L |
29547 | #define GE1_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xF0000000L |
29548 | //GE1_PERFCOUNTER2_SELECT1 |
29549 | #define GE1_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
29550 | #define GE1_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
29551 | #define GE1_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x18 |
29552 | #define GE1_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x1c |
29553 | #define GE1_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29554 | #define GE1_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29555 | #define GE1_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0x0F000000L |
29556 | #define GE1_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0xF0000000L |
29557 | //GE1_PERFCOUNTER3_SELECT |
29558 | #define GE1_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 |
29559 | #define GE1_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
29560 | #define GE1_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
29561 | #define GE1_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x18 |
29562 | #define GE1_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x1c |
29563 | #define GE1_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL |
29564 | #define GE1_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29565 | #define GE1_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
29566 | #define GE1_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0x0F000000L |
29567 | #define GE1_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xF0000000L |
29568 | //GE1_PERFCOUNTER3_SELECT1 |
29569 | #define GE1_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
29570 | #define GE1_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
29571 | #define GE1_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x18 |
29572 | #define GE1_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x1c |
29573 | #define GE1_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29574 | #define GE1_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29575 | #define GE1_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0x0F000000L |
29576 | #define GE1_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0xF0000000L |
29577 | //GE2_DIST_PERFCOUNTER0_SELECT |
29578 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 |
29579 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
29580 | #define GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
29581 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x18 |
29582 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x1c |
29583 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL |
29584 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29585 | #define GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
29586 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0x0F000000L |
29587 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xF0000000L |
29588 | //GE2_DIST_PERFCOUNTER0_SELECT1 |
29589 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
29590 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
29591 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
29592 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
29593 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29594 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29595 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
29596 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
29597 | //GE2_DIST_PERFCOUNTER1_SELECT |
29598 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 |
29599 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
29600 | #define GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
29601 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x18 |
29602 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x1c |
29603 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL |
29604 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29605 | #define GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
29606 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0x0F000000L |
29607 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xF0000000L |
29608 | //GE2_DIST_PERFCOUNTER1_SELECT1 |
29609 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
29610 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
29611 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 |
29612 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c |
29613 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29614 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29615 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L |
29616 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L |
29617 | //GE2_DIST_PERFCOUNTER2_SELECT |
29618 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 |
29619 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
29620 | #define GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
29621 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x18 |
29622 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x1c |
29623 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL |
29624 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29625 | #define GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
29626 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0x0F000000L |
29627 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xF0000000L |
29628 | //GE2_DIST_PERFCOUNTER2_SELECT1 |
29629 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
29630 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
29631 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x18 |
29632 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x1c |
29633 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29634 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29635 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0x0F000000L |
29636 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0xF0000000L |
29637 | //GE2_DIST_PERFCOUNTER3_SELECT |
29638 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 |
29639 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
29640 | #define GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
29641 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x18 |
29642 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x1c |
29643 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL |
29644 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29645 | #define GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
29646 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0x0F000000L |
29647 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xF0000000L |
29648 | //GE2_DIST_PERFCOUNTER3_SELECT1 |
29649 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
29650 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
29651 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x18 |
29652 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x1c |
29653 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29654 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29655 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0x0F000000L |
29656 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0xF0000000L |
29657 | //GE2_SE_PERFCOUNTER0_SELECT |
29658 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 |
29659 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
29660 | #define GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
29661 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x18 |
29662 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x1c |
29663 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL |
29664 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29665 | #define GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
29666 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0x0F000000L |
29667 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xF0000000L |
29668 | //GE2_SE_PERFCOUNTER0_SELECT1 |
29669 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
29670 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
29671 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
29672 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
29673 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29674 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29675 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
29676 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
29677 | //GE2_SE_PERFCOUNTER1_SELECT |
29678 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 |
29679 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
29680 | #define GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
29681 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x18 |
29682 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x1c |
29683 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL |
29684 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29685 | #define GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
29686 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0x0F000000L |
29687 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xF0000000L |
29688 | //GE2_SE_PERFCOUNTER1_SELECT1 |
29689 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
29690 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
29691 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 |
29692 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c |
29693 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29694 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29695 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L |
29696 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L |
29697 | //GE2_SE_PERFCOUNTER2_SELECT |
29698 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 |
29699 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
29700 | #define GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
29701 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x18 |
29702 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x1c |
29703 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL |
29704 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29705 | #define GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
29706 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0x0F000000L |
29707 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xF0000000L |
29708 | //GE2_SE_PERFCOUNTER2_SELECT1 |
29709 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
29710 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
29711 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x18 |
29712 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x1c |
29713 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29714 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29715 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0x0F000000L |
29716 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0xF0000000L |
29717 | //GE2_SE_PERFCOUNTER3_SELECT |
29718 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 |
29719 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
29720 | #define GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
29721 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x18 |
29722 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x1c |
29723 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL |
29724 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29725 | #define GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
29726 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0x0F000000L |
29727 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xF0000000L |
29728 | //GE2_SE_PERFCOUNTER3_SELECT1 |
29729 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
29730 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
29731 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x18 |
29732 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x1c |
29733 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29734 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29735 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0x0F000000L |
29736 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0xF0000000L |
29737 | //PA_SU_PERFCOUNTER0_SELECT |
29738 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
29739 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
29740 | #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
29741 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
29742 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
29743 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
29744 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29745 | #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
29746 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
29747 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
29748 | //PA_SU_PERFCOUNTER0_SELECT1 |
29749 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
29750 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
29751 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
29752 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
29753 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29754 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29755 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
29756 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
29757 | //PA_SU_PERFCOUNTER1_SELECT |
29758 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
29759 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
29760 | #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
29761 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
29762 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
29763 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
29764 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29765 | #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
29766 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
29767 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
29768 | //PA_SU_PERFCOUNTER1_SELECT1 |
29769 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
29770 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
29771 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
29772 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
29773 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29774 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29775 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
29776 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
29777 | //PA_SU_PERFCOUNTER2_SELECT |
29778 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
29779 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
29780 | #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
29781 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
29782 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
29783 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
29784 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29785 | #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
29786 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
29787 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
29788 | //PA_SU_PERFCOUNTER2_SELECT1 |
29789 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
29790 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
29791 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
29792 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
29793 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29794 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29795 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
29796 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
29797 | //PA_SU_PERFCOUNTER3_SELECT |
29798 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
29799 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
29800 | #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
29801 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
29802 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
29803 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
29804 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29805 | #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
29806 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
29807 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
29808 | //PA_SU_PERFCOUNTER3_SELECT1 |
29809 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
29810 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
29811 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
29812 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
29813 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29814 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29815 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
29816 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
29817 | //PA_SC_PERFCOUNTER0_SELECT |
29818 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
29819 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
29820 | #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
29821 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
29822 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
29823 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
29824 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29825 | #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
29826 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
29827 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
29828 | //PA_SC_PERFCOUNTER0_SELECT1 |
29829 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
29830 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
29831 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
29832 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
29833 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29834 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29835 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
29836 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
29837 | //PA_SC_PERFCOUNTER1_SELECT |
29838 | #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
29839 | #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
29840 | //PA_SC_PERFCOUNTER2_SELECT |
29841 | #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
29842 | #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
29843 | //PA_SC_PERFCOUNTER3_SELECT |
29844 | #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
29845 | #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
29846 | //PA_SC_PERFCOUNTER4_SELECT |
29847 | #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
29848 | #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL |
29849 | //PA_SC_PERFCOUNTER5_SELECT |
29850 | #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
29851 | #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL |
29852 | //PA_SC_PERFCOUNTER6_SELECT |
29853 | #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 |
29854 | #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL |
29855 | //PA_SC_PERFCOUNTER7_SELECT |
29856 | #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 |
29857 | #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL |
29858 | //SPI_PERFCOUNTER0_SELECT |
29859 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
29860 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
29861 | #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
29862 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
29863 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
29864 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
29865 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29866 | #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
29867 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
29868 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
29869 | //SPI_PERFCOUNTER1_SELECT |
29870 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
29871 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
29872 | #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
29873 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
29874 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
29875 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
29876 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29877 | #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
29878 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
29879 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
29880 | //SPI_PERFCOUNTER2_SELECT |
29881 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
29882 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
29883 | #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
29884 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
29885 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
29886 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
29887 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29888 | #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
29889 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
29890 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
29891 | //SPI_PERFCOUNTER3_SELECT |
29892 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
29893 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
29894 | #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
29895 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
29896 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
29897 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
29898 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
29899 | #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
29900 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
29901 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
29902 | //SPI_PERFCOUNTER0_SELECT1 |
29903 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
29904 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
29905 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
29906 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
29907 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29908 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29909 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
29910 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
29911 | //SPI_PERFCOUNTER1_SELECT1 |
29912 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
29913 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
29914 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
29915 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
29916 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29917 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29918 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
29919 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
29920 | //SPI_PERFCOUNTER2_SELECT1 |
29921 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
29922 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
29923 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
29924 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
29925 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29926 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29927 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
29928 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
29929 | //SPI_PERFCOUNTER3_SELECT1 |
29930 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
29931 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
29932 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
29933 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
29934 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
29935 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
29936 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
29937 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
29938 | //SPI_PERFCOUNTER4_SELECT |
29939 | #define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
29940 | #define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL |
29941 | //SPI_PERFCOUNTER5_SELECT |
29942 | #define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
29943 | #define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL |
29944 | //SPI_PERFCOUNTER_BINS |
29945 | #define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 |
29946 | #define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 |
29947 | #define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 |
29948 | #define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc |
29949 | #define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 |
29950 | #define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 |
29951 | #define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 |
29952 | #define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c |
29953 | #define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL |
29954 | #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L |
29955 | #define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L |
29956 | #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L |
29957 | #define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L |
29958 | #define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L |
29959 | #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L |
29960 | #define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L |
29961 | //SQ_PERFCOUNTER0_SELECT |
29962 | #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
29963 | #define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
29964 | #define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
29965 | #define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL |
29966 | #define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
29967 | #define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
29968 | //SQ_PERFCOUNTER1_SELECT |
29969 | #define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
29970 | #define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
29971 | #define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
29972 | #define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL |
29973 | #define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
29974 | #define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
29975 | //SQ_PERFCOUNTER2_SELECT |
29976 | #define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
29977 | #define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 |
29978 | #define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
29979 | #define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL |
29980 | #define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L |
29981 | #define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
29982 | //SQ_PERFCOUNTER3_SELECT |
29983 | #define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
29984 | #define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 |
29985 | #define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
29986 | #define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL |
29987 | #define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L |
29988 | #define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
29989 | //SQ_PERFCOUNTER4_SELECT |
29990 | #define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
29991 | #define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 |
29992 | #define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c |
29993 | #define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL |
29994 | #define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L |
29995 | #define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L |
29996 | //SQ_PERFCOUNTER5_SELECT |
29997 | #define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
29998 | #define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 |
29999 | #define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c |
30000 | #define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL |
30001 | #define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L |
30002 | #define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L |
30003 | //SQ_PERFCOUNTER6_SELECT |
30004 | #define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 |
30005 | #define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 |
30006 | #define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c |
30007 | #define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL |
30008 | #define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L |
30009 | #define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L |
30010 | //SQ_PERFCOUNTER7_SELECT |
30011 | #define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 |
30012 | #define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 |
30013 | #define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c |
30014 | #define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL |
30015 | #define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L |
30016 | #define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L |
30017 | //SQ_PERFCOUNTER8_SELECT |
30018 | #define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 |
30019 | #define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 |
30020 | #define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c |
30021 | #define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL |
30022 | #define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L |
30023 | #define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L |
30024 | //SQ_PERFCOUNTER9_SELECT |
30025 | #define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 |
30026 | #define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 |
30027 | #define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c |
30028 | #define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL |
30029 | #define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L |
30030 | #define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L |
30031 | //SQ_PERFCOUNTER10_SELECT |
30032 | #define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 |
30033 | #define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 |
30034 | #define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c |
30035 | #define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL |
30036 | #define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L |
30037 | #define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L |
30038 | //SQ_PERFCOUNTER11_SELECT |
30039 | #define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 |
30040 | #define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 |
30041 | #define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c |
30042 | #define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL |
30043 | #define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L |
30044 | #define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L |
30045 | //SQ_PERFCOUNTER12_SELECT |
30046 | #define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 |
30047 | #define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 |
30048 | #define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c |
30049 | #define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL |
30050 | #define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L |
30051 | #define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L |
30052 | //SQ_PERFCOUNTER13_SELECT |
30053 | #define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 |
30054 | #define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 |
30055 | #define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c |
30056 | #define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL |
30057 | #define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L |
30058 | #define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L |
30059 | //SQ_PERFCOUNTER14_SELECT |
30060 | #define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 |
30061 | #define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 |
30062 | #define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c |
30063 | #define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL |
30064 | #define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L |
30065 | #define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L |
30066 | //SQ_PERFCOUNTER15_SELECT |
30067 | #define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 |
30068 | #define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 |
30069 | #define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c |
30070 | #define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL |
30071 | #define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L |
30072 | #define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L |
30073 | //SQ_PERFCOUNTER_CTRL |
30074 | #define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 |
30075 | #define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 |
30076 | #define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 |
30077 | #define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 |
30078 | #define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 |
30079 | #define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 |
30080 | #define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 |
30081 | #define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 |
30082 | #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd |
30083 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF__SHIFT 0xe |
30084 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF__SHIFT 0xf |
30085 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF__SHIFT 0x10 |
30086 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF__SHIFT 0x11 |
30087 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF__SHIFT 0x12 |
30088 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF__SHIFT 0x13 |
30089 | #define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L |
30090 | #define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L |
30091 | #define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L |
30092 | #define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L |
30093 | #define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L |
30094 | #define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L |
30095 | #define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L |
30096 | #define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00000300L |
30097 | #define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L |
30098 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF_MASK 0x00004000L |
30099 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF_MASK 0x00008000L |
30100 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF_MASK 0x00010000L |
30101 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF_MASK 0x00020000L |
30102 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF_MASK 0x00040000L |
30103 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF_MASK 0x00080000L |
30104 | //SQ_PERFCOUNTER_CTRL2 |
30105 | #define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 |
30106 | #define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L |
30107 | //GCEA_PERFCOUNTER2_SELECT |
30108 | #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
30109 | #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
30110 | #define GCEA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
30111 | #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
30112 | #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
30113 | #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
30114 | #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30115 | #define GCEA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
30116 | #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
30117 | #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
30118 | //GCEA_PERFCOUNTER2_SELECT1 |
30119 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
30120 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
30121 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
30122 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
30123 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30124 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30125 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
30126 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
30127 | //GCEA_PERFCOUNTER2_MODE |
30128 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT 0x0 |
30129 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT 0x2 |
30130 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT 0x4 |
30131 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT 0x6 |
30132 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT 0x8 |
30133 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT 0xc |
30134 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT 0x10 |
30135 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT 0x14 |
30136 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK 0x00000003L |
30137 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK 0x0000000CL |
30138 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK 0x00000030L |
30139 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK 0x000000C0L |
30140 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK 0x00000F00L |
30141 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK 0x0000F000L |
30142 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK 0x000F0000L |
30143 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK 0x00F00000L |
30144 | //GCEA_PERFCOUNTER0_CFG |
30145 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
30146 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
30147 | #define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
30148 | #define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
30149 | #define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
30150 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
30151 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
30152 | #define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
30153 | #define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
30154 | #define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
30155 | //GCEA_PERFCOUNTER1_CFG |
30156 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
30157 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
30158 | #define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
30159 | #define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
30160 | #define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
30161 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
30162 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
30163 | #define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
30164 | #define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
30165 | #define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
30166 | //GCEA_PERFCOUNTER_RSLT_CNTL |
30167 | #define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
30168 | #define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
30169 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
30170 | #define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
30171 | #define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
30172 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
30173 | #define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
30174 | #define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
30175 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
30176 | #define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
30177 | #define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
30178 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
30179 | //SX_PERFCOUNTER0_SELECT |
30180 | #define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30181 | #define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30182 | #define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
30183 | #define SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
30184 | #define SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
30185 | #define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
30186 | #define SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30187 | #define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
30188 | #define SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
30189 | #define SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
30190 | //SX_PERFCOUNTER1_SELECT |
30191 | #define SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30192 | #define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
30193 | #define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
30194 | #define SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
30195 | #define SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
30196 | #define SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
30197 | #define SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30198 | #define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
30199 | #define SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
30200 | #define SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
30201 | //SX_PERFCOUNTER2_SELECT |
30202 | #define SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
30203 | #define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
30204 | #define SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
30205 | #define SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
30206 | #define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
30207 | #define SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
30208 | //SX_PERFCOUNTER3_SELECT |
30209 | #define SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
30210 | #define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
30211 | #define SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
30212 | #define SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
30213 | #define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
30214 | #define SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
30215 | //SX_PERFCOUNTER0_SELECT1 |
30216 | #define SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30217 | #define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30218 | #define SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
30219 | #define SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
30220 | #define SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30221 | #define SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30222 | #define SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
30223 | #define SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
30224 | //SX_PERFCOUNTER1_SELECT1 |
30225 | #define SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
30226 | #define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
30227 | #define SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
30228 | #define SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
30229 | #define SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30230 | #define SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30231 | #define SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
30232 | #define SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
30233 | //GDS_PERFCOUNTER0_SELECT |
30234 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30235 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30236 | #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
30237 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
30238 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
30239 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
30240 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30241 | #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
30242 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
30243 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
30244 | //GDS_PERFCOUNTER1_SELECT |
30245 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30246 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
30247 | #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
30248 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
30249 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
30250 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
30251 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30252 | #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
30253 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
30254 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
30255 | //GDS_PERFCOUNTER2_SELECT |
30256 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
30257 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
30258 | #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
30259 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
30260 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
30261 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
30262 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30263 | #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
30264 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
30265 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
30266 | //GDS_PERFCOUNTER3_SELECT |
30267 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
30268 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
30269 | #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
30270 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
30271 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
30272 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
30273 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30274 | #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
30275 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
30276 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
30277 | //GDS_PERFCOUNTER0_SELECT1 |
30278 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30279 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30280 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
30281 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
30282 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30283 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30284 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
30285 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
30286 | //GDS_PERFCOUNTER1_SELECT1 |
30287 | #define GDS_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
30288 | #define GDS_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
30289 | #define GDS_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
30290 | #define GDS_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
30291 | #define GDS_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30292 | #define GDS_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30293 | #define GDS_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
30294 | #define GDS_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
30295 | //GDS_PERFCOUNTER2_SELECT1 |
30296 | #define GDS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
30297 | #define GDS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
30298 | #define GDS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
30299 | #define GDS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
30300 | #define GDS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30301 | #define GDS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30302 | #define GDS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
30303 | #define GDS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
30304 | //GDS_PERFCOUNTER3_SELECT1 |
30305 | #define GDS_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
30306 | #define GDS_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
30307 | #define GDS_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
30308 | #define GDS_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
30309 | #define GDS_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30310 | #define GDS_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30311 | #define GDS_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
30312 | #define GDS_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
30313 | //TA_PERFCOUNTER0_SELECT |
30314 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30315 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30316 | #define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
30317 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
30318 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
30319 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
30320 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30321 | #define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
30322 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
30323 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
30324 | //TA_PERFCOUNTER0_SELECT1 |
30325 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30326 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30327 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
30328 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
30329 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30330 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30331 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
30332 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
30333 | //TA_PERFCOUNTER1_SELECT |
30334 | #define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30335 | #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
30336 | #define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
30337 | #define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
30338 | #define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
30339 | #define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
30340 | //TD_PERFCOUNTER0_SELECT |
30341 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30342 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30343 | #define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
30344 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
30345 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
30346 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
30347 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30348 | #define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
30349 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
30350 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
30351 | //TD_PERFCOUNTER0_SELECT1 |
30352 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30353 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30354 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
30355 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
30356 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30357 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30358 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
30359 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
30360 | //TD_PERFCOUNTER1_SELECT |
30361 | #define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30362 | #define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
30363 | #define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
30364 | #define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
30365 | #define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
30366 | #define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
30367 | //TCP_PERFCOUNTER0_SELECT |
30368 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30369 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30370 | #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
30371 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
30372 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
30373 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
30374 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30375 | #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
30376 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
30377 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
30378 | //TCP_PERFCOUNTER0_SELECT1 |
30379 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30380 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30381 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
30382 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
30383 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30384 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30385 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
30386 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
30387 | //TCP_PERFCOUNTER1_SELECT |
30388 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30389 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
30390 | #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
30391 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
30392 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
30393 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
30394 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30395 | #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
30396 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
30397 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
30398 | //TCP_PERFCOUNTER1_SELECT1 |
30399 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
30400 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
30401 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
30402 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
30403 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30404 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30405 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
30406 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
30407 | //TCP_PERFCOUNTER2_SELECT |
30408 | #define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
30409 | #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
30410 | #define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
30411 | #define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
30412 | #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
30413 | #define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
30414 | //TCP_PERFCOUNTER3_SELECT |
30415 | #define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
30416 | #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
30417 | #define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
30418 | #define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
30419 | #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
30420 | #define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
30421 | //GL2C_PERFCOUNTER0_SELECT |
30422 | #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30423 | #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30424 | #define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
30425 | #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
30426 | #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
30427 | #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
30428 | #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30429 | #define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
30430 | #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
30431 | #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
30432 | //GL2C_PERFCOUNTER0_SELECT1 |
30433 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30434 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30435 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
30436 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
30437 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30438 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30439 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
30440 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
30441 | //GL2C_PERFCOUNTER1_SELECT |
30442 | #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30443 | #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
30444 | #define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
30445 | #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
30446 | #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
30447 | #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
30448 | #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30449 | #define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
30450 | #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
30451 | #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
30452 | //GL2C_PERFCOUNTER1_SELECT1 |
30453 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
30454 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
30455 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 |
30456 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c |
30457 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30458 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30459 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L |
30460 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L |
30461 | //GL2C_PERFCOUNTER2_SELECT |
30462 | #define GL2C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
30463 | #define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
30464 | #define GL2C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
30465 | #define GL2C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
30466 | #define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
30467 | #define GL2C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
30468 | //GL2C_PERFCOUNTER3_SELECT |
30469 | #define GL2C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
30470 | #define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
30471 | #define GL2C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
30472 | #define GL2C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
30473 | #define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
30474 | #define GL2C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
30475 | //GL2A_PERFCOUNTER0_SELECT |
30476 | #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30477 | #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30478 | #define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
30479 | #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
30480 | #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
30481 | #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
30482 | #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30483 | #define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
30484 | #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
30485 | #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
30486 | //GL2A_PERFCOUNTER0_SELECT1 |
30487 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30488 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30489 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
30490 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
30491 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30492 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30493 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
30494 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
30495 | //GL2A_PERFCOUNTER1_SELECT |
30496 | #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30497 | #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
30498 | #define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
30499 | #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
30500 | #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
30501 | #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
30502 | #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30503 | #define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
30504 | #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
30505 | #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
30506 | //GL2A_PERFCOUNTER1_SELECT1 |
30507 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
30508 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
30509 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 |
30510 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c |
30511 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30512 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30513 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L |
30514 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L |
30515 | //GL2A_PERFCOUNTER2_SELECT |
30516 | #define GL2A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
30517 | #define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
30518 | #define GL2A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
30519 | #define GL2A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
30520 | #define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
30521 | #define GL2A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
30522 | //GL2A_PERFCOUNTER3_SELECT |
30523 | #define GL2A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
30524 | #define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
30525 | #define GL2A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
30526 | #define GL2A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
30527 | #define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
30528 | #define GL2A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
30529 | //GL1C_PERFCOUNTER0_SELECT |
30530 | #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30531 | #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30532 | #define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
30533 | #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
30534 | #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
30535 | #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
30536 | #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30537 | #define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
30538 | #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
30539 | #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
30540 | //GL1C_PERFCOUNTER0_SELECT1 |
30541 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30542 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30543 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
30544 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
30545 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30546 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30547 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
30548 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
30549 | //GL1C_PERFCOUNTER1_SELECT |
30550 | #define GL1C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30551 | #define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
30552 | #define GL1C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
30553 | #define GL1C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
30554 | #define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
30555 | #define GL1C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
30556 | //GL1C_PERFCOUNTER2_SELECT |
30557 | #define GL1C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
30558 | #define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
30559 | #define GL1C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
30560 | #define GL1C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
30561 | #define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
30562 | #define GL1C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
30563 | //GL1C_PERFCOUNTER3_SELECT |
30564 | #define GL1C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
30565 | #define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
30566 | #define GL1C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
30567 | #define GL1C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
30568 | #define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
30569 | #define GL1C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
30570 | //CHC_PERFCOUNTER0_SELECT |
30571 | #define CHC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30572 | #define CHC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30573 | #define CHC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
30574 | #define CHC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
30575 | #define CHC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
30576 | #define CHC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
30577 | #define CHC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30578 | #define CHC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
30579 | #define CHC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
30580 | #define CHC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
30581 | //CHC_PERFCOUNTER0_SELECT1 |
30582 | #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30583 | #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30584 | #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
30585 | #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
30586 | #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30587 | #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30588 | #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
30589 | #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
30590 | //CHC_PERFCOUNTER1_SELECT |
30591 | #define CHC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30592 | #define CHC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
30593 | #define CHC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
30594 | #define CHC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
30595 | #define CHC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
30596 | #define CHC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
30597 | //CHC_PERFCOUNTER2_SELECT |
30598 | #define CHC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
30599 | #define CHC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
30600 | #define CHC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
30601 | #define CHC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
30602 | #define CHC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
30603 | #define CHC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
30604 | //CHC_PERFCOUNTER3_SELECT |
30605 | #define CHC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
30606 | #define CHC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
30607 | #define CHC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
30608 | #define CHC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
30609 | #define CHC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
30610 | #define CHC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
30611 | //CHCG_PERFCOUNTER0_SELECT |
30612 | #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30613 | #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30614 | #define CHCG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
30615 | #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
30616 | #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
30617 | #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
30618 | #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30619 | #define CHCG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
30620 | #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
30621 | #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
30622 | //CHCG_PERFCOUNTER0_SELECT1 |
30623 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30624 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30625 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
30626 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
30627 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30628 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30629 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
30630 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
30631 | //CHCG_PERFCOUNTER1_SELECT |
30632 | #define CHCG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30633 | #define CHCG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
30634 | #define CHCG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
30635 | #define CHCG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
30636 | #define CHCG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
30637 | #define CHCG_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
30638 | //CHCG_PERFCOUNTER2_SELECT |
30639 | #define CHCG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
30640 | #define CHCG_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
30641 | #define CHCG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
30642 | #define CHCG_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
30643 | #define CHCG_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
30644 | #define CHCG_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
30645 | //CHCG_PERFCOUNTER3_SELECT |
30646 | #define CHCG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
30647 | #define CHCG_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
30648 | #define CHCG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
30649 | #define CHCG_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
30650 | #define CHCG_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
30651 | #define CHCG_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
30652 | //CB_PERFCOUNTER_FILTER |
30653 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 |
30654 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 |
30655 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 |
30656 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 |
30657 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa |
30658 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb |
30659 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc |
30660 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd |
30661 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 |
30662 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 |
30663 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 |
30664 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 |
30665 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L |
30666 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL |
30667 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L |
30668 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L |
30669 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L |
30670 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L |
30671 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L |
30672 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L |
30673 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L |
30674 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L |
30675 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L |
30676 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L |
30677 | //CB_PERFCOUNTER0_SELECT |
30678 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30679 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30680 | #define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
30681 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
30682 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
30683 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL |
30684 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L |
30685 | #define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
30686 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
30687 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
30688 | //CB_PERFCOUNTER0_SELECT1 |
30689 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30690 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30691 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
30692 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
30693 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL |
30694 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L |
30695 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
30696 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
30697 | //CB_PERFCOUNTER1_SELECT |
30698 | #define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30699 | #define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
30700 | #define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL |
30701 | #define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
30702 | //CB_PERFCOUNTER2_SELECT |
30703 | #define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
30704 | #define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
30705 | #define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL |
30706 | #define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
30707 | //CB_PERFCOUNTER3_SELECT |
30708 | #define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
30709 | #define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
30710 | #define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL |
30711 | #define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
30712 | //DB_PERFCOUNTER0_SELECT |
30713 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
30714 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
30715 | #define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
30716 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
30717 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
30718 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
30719 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30720 | #define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
30721 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
30722 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
30723 | //DB_PERFCOUNTER0_SELECT1 |
30724 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
30725 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
30726 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
30727 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
30728 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30729 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30730 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
30731 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
30732 | //DB_PERFCOUNTER1_SELECT |
30733 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
30734 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
30735 | #define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
30736 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
30737 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
30738 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
30739 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30740 | #define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
30741 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
30742 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
30743 | //DB_PERFCOUNTER1_SELECT1 |
30744 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
30745 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
30746 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
30747 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
30748 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
30749 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
30750 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
30751 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
30752 | //DB_PERFCOUNTER2_SELECT |
30753 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
30754 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
30755 | #define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
30756 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
30757 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
30758 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
30759 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30760 | #define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
30761 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
30762 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
30763 | //DB_PERFCOUNTER3_SELECT |
30764 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
30765 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
30766 | #define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
30767 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
30768 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
30769 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
30770 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
30771 | #define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
30772 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
30773 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
30774 | //RLC_SPM_PERFMON_CNTL |
30775 | #define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 |
30776 | #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc |
30777 | #define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe |
30778 | #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 |
30779 | #define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFFL |
30780 | #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L |
30781 | #define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L |
30782 | #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L |
30783 | //RLC_SPM_PERFMON_RING_BASE_LO |
30784 | #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 |
30785 | #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL |
30786 | //RLC_SPM_PERFMON_RING_BASE_HI |
30787 | #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 |
30788 | #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 |
30789 | #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL |
30790 | #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L |
30791 | //RLC_SPM_PERFMON_RING_SIZE |
30792 | #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 |
30793 | #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL |
30794 | //RLC_SPM_PERFMON_SEGMENT_SIZE |
30795 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 |
30796 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 |
30797 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb |
30798 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 |
30799 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 |
30800 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a |
30801 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f |
30802 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL |
30803 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L |
30804 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L |
30805 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L |
30806 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L |
30807 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L |
30808 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L |
30809 | //RLC_SPM_RING_RDPTR |
30810 | #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 |
30811 | #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL |
30812 | //RLC_SPM_SEGMENT_THRESHOLD |
30813 | #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 |
30814 | #define RLC_SPM_SEGMENT_THRESHOLD__RESERVED__SHIFT 0x8 |
30815 | #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0x000000FFL |
30816 | #define RLC_SPM_SEGMENT_THRESHOLD__RESERVED_MASK 0xFFFFFF00L |
30817 | //RLC_SPM_SE_MUXSEL_ADDR |
30818 | #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 |
30819 | #define RLC_SPM_SE_MUXSEL_ADDR__RESERVED__SHIFT 0x9 |
30820 | #define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0x000001FFL |
30821 | #define RLC_SPM_SE_MUXSEL_ADDR__RESERVED_MASK 0xFFFFFE00L |
30822 | //RLC_SPM_SE_MUXSEL_DATA |
30823 | #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 |
30824 | #define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL |
30825 | //RLC_SPM_GLOBAL_MUXSEL_ADDR |
30826 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 |
30827 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED__SHIFT 0x8 |
30828 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0x000000FFL |
30829 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED_MASK 0xFFFFFF00L |
30830 | //RLC_SPM_GLOBAL_MUXSEL_DATA |
30831 | #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 |
30832 | #define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL |
30833 | //RLC_SPM_DESER_START_SKEW |
30834 | #define RLC_SPM_DESER_START_SKEW__DESER_START_SKEW__SHIFT 0x0 |
30835 | #define RLC_SPM_DESER_START_SKEW__RESERVED__SHIFT 0x7 |
30836 | #define RLC_SPM_DESER_START_SKEW__DESER_START_SKEW_MASK 0x0000007FL |
30837 | #define RLC_SPM_DESER_START_SKEW__RESERVED_MASK 0xFFFFFF80L |
30838 | //RLC_SPM_GLOBALS_SAMPLE_SKEW |
30839 | #define RLC_SPM_GLOBALS_SAMPLE_SKEW__GLOBALS_SAMPLE_SKEW__SHIFT 0x0 |
30840 | #define RLC_SPM_GLOBALS_SAMPLE_SKEW__RESERVED__SHIFT 0x7 |
30841 | #define RLC_SPM_GLOBALS_SAMPLE_SKEW__GLOBALS_SAMPLE_SKEW_MASK 0x0000007FL |
30842 | #define RLC_SPM_GLOBALS_SAMPLE_SKEW__RESERVED_MASK 0xFFFFFF80L |
30843 | //RLC_SPM_GLOBALS_MUXSEL_SKEW |
30844 | #define RLC_SPM_GLOBALS_MUXSEL_SKEW__GLOBALS_MUXSEL_SKEW__SHIFT 0x0 |
30845 | #define RLC_SPM_GLOBALS_MUXSEL_SKEW__RESERVED__SHIFT 0x7 |
30846 | #define RLC_SPM_GLOBALS_MUXSEL_SKEW__GLOBALS_MUXSEL_SKEW_MASK 0x0000007FL |
30847 | #define RLC_SPM_GLOBALS_MUXSEL_SKEW__RESERVED_MASK 0xFFFFFF80L |
30848 | //RLC_SPM_SE_SAMPLE_SKEW |
30849 | #define RLC_SPM_SE_SAMPLE_SKEW__SE_SAMPLE_SKEW__SHIFT 0x0 |
30850 | #define RLC_SPM_SE_SAMPLE_SKEW__RESERVED__SHIFT 0x7 |
30851 | #define RLC_SPM_SE_SAMPLE_SKEW__SE_SAMPLE_SKEW_MASK 0x0000007FL |
30852 | #define RLC_SPM_SE_SAMPLE_SKEW__RESERVED_MASK 0xFFFFFF80L |
30853 | //RLC_SPM_SE_MUXSEL_SKEW |
30854 | #define RLC_SPM_SE_MUXSEL_SKEW__SE_MUXSEL_SKEW__SHIFT 0x0 |
30855 | #define RLC_SPM_SE_MUXSEL_SKEW__RESERVED__SHIFT 0x7 |
30856 | #define RLC_SPM_SE_MUXSEL_SKEW__SE_MUXSEL_SKEW_MASK 0x0000007FL |
30857 | #define RLC_SPM_SE_MUXSEL_SKEW__RESERVED_MASK 0xFFFFFF80L |
30858 | //RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR |
30859 | #define RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR__GLB_SAMPLEDELAY_INDEX__SHIFT 0x0 |
30860 | #define RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR__GLB_SAMPLEDELAY_INDEX_MASK 0xFFFFFFFFL |
30861 | //RLC_SPM_GLB_SAMPLEDELAY_IND_DATA |
30862 | #define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__data__SHIFT 0x0 |
30863 | #define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__RESERVED__SHIFT 0x7 |
30864 | #define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__data_MASK 0x0000007FL |
30865 | #define RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__RESERVED_MASK 0xFFFFFF80L |
30866 | //RLC_SPM_SE_SAMPLEDELAY_IND_ADDR |
30867 | #define RLC_SPM_SE_SAMPLEDELAY_IND_ADDR__SE_SAMPLEDELAY_INDEX__SHIFT 0x0 |
30868 | #define RLC_SPM_SE_SAMPLEDELAY_IND_ADDR__SE_SAMPLEDELAY_INDEX_MASK 0xFFFFFFFFL |
30869 | //RLC_SPM_SE_SAMPLEDELAY_IND_DATA |
30870 | #define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__data__SHIFT 0x0 |
30871 | #define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__RESERVED__SHIFT 0x7 |
30872 | #define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__data_MASK 0x0000007FL |
30873 | #define RLC_SPM_SE_SAMPLEDELAY_IND_DATA__RESERVED_MASK 0xFFFFFF80L |
30874 | //RLC_SPM_RING_WRPTR |
30875 | #define RLC_SPM_RING_WRPTR__RESERVED__SHIFT 0x0 |
30876 | #define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR__SHIFT 0x5 |
30877 | #define RLC_SPM_RING_WRPTR__RESERVED_MASK 0x0000001FL |
30878 | #define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR_MASK 0xFFFFFFE0L |
30879 | //RLC_SPM_ACCUM_DATARAM_ADDR |
30880 | #define RLC_SPM_ACCUM_DATARAM_ADDR__addr__SHIFT 0x0 |
30881 | #define RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED__SHIFT 0x7 |
30882 | #define RLC_SPM_ACCUM_DATARAM_ADDR__addr_MASK 0x0000007FL |
30883 | #define RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED_MASK 0xFFFFFF80L |
30884 | //RLC_SPM_ACCUM_DATARAM_DATA |
30885 | #define RLC_SPM_ACCUM_DATARAM_DATA__data__SHIFT 0x0 |
30886 | #define RLC_SPM_ACCUM_DATARAM_DATA__data_MASK 0xFFFFFFFFL |
30887 | //RLC_SPM_ACCUM_CTRLRAM_ADDR |
30888 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR__addr__SHIFT 0x0 |
30889 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED__SHIFT 0xb |
30890 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR__addr_MASK 0x000007FFL |
30891 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED_MASK 0xFFFFF800L |
30892 | //RLC_SPM_ACCUM_CTRLRAM_DATA |
30893 | #define RLC_SPM_ACCUM_CTRLRAM_DATA__data__SHIFT 0x0 |
30894 | #define RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED__SHIFT 0x8 |
30895 | #define RLC_SPM_ACCUM_CTRLRAM_DATA__data_MASK 0x000000FFL |
30896 | #define RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED_MASK 0xFFFFFF00L |
30897 | //RLC_SPM_ACCUM_STATUS |
30898 | #define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted__SHIFT 0x0 |
30899 | #define RLC_SPM_ACCUM_STATUS__AccumDone__SHIFT 0x8 |
30900 | #define RLC_SPM_ACCUM_STATUS__SpmDone__SHIFT 0x9 |
30901 | #define RLC_SPM_ACCUM_STATUS__AccumOverflow__SHIFT 0xa |
30902 | #define RLC_SPM_ACCUM_STATUS__AccumArmed__SHIFT 0xb |
30903 | #define RLC_SPM_ACCUM_STATUS__SequenceInProgress__SHIFT 0xc |
30904 | #define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress__SHIFT 0xd |
30905 | #define RLC_SPM_ACCUM_STATUS__AllFifosEmpty__SHIFT 0xe |
30906 | #define RLC_SPM_ACCUM_STATUS__FSMIsIdle__SHIFT 0xf |
30907 | #define RLC_SPM_ACCUM_STATUS__SwaAccumDone__SHIFT 0x10 |
30908 | #define RLC_SPM_ACCUM_STATUS__SwaSpmDone__SHIFT 0x11 |
30909 | #define RLC_SPM_ACCUM_STATUS__SwaAccumOverflow__SHIFT 0x12 |
30910 | #define RLC_SPM_ACCUM_STATUS__SwaAccumArmed__SHIFT 0x13 |
30911 | #define RLC_SPM_ACCUM_STATUS__AllSegsDone__SHIFT 0x14 |
30912 | #define RLC_SPM_ACCUM_STATUS__RearmSwaPending__SHIFT 0x15 |
30913 | #define RLC_SPM_ACCUM_STATUS__RearmSppPending__SHIFT 0x16 |
30914 | #define RLC_SPM_ACCUM_STATUS__RESERVED__SHIFT 0x17 |
30915 | #define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted_MASK 0x000000FFL |
30916 | #define RLC_SPM_ACCUM_STATUS__AccumDone_MASK 0x00000100L |
30917 | #define RLC_SPM_ACCUM_STATUS__SpmDone_MASK 0x00000200L |
30918 | #define RLC_SPM_ACCUM_STATUS__AccumOverflow_MASK 0x00000400L |
30919 | #define RLC_SPM_ACCUM_STATUS__AccumArmed_MASK 0x00000800L |
30920 | #define RLC_SPM_ACCUM_STATUS__SequenceInProgress_MASK 0x00001000L |
30921 | #define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress_MASK 0x00002000L |
30922 | #define RLC_SPM_ACCUM_STATUS__AllFifosEmpty_MASK 0x00004000L |
30923 | #define RLC_SPM_ACCUM_STATUS__FSMIsIdle_MASK 0x00008000L |
30924 | #define RLC_SPM_ACCUM_STATUS__SwaAccumDone_MASK 0x00010000L |
30925 | #define RLC_SPM_ACCUM_STATUS__SwaSpmDone_MASK 0x00020000L |
30926 | #define RLC_SPM_ACCUM_STATUS__SwaAccumOverflow_MASK 0x00040000L |
30927 | #define RLC_SPM_ACCUM_STATUS__SwaAccumArmed_MASK 0x00080000L |
30928 | #define RLC_SPM_ACCUM_STATUS__AllSegsDone_MASK 0x00100000L |
30929 | #define RLC_SPM_ACCUM_STATUS__RearmSwaPending_MASK 0x00200000L |
30930 | #define RLC_SPM_ACCUM_STATUS__RearmSppPending_MASK 0x00400000L |
30931 | #define RLC_SPM_ACCUM_STATUS__RESERVED_MASK 0xFF800000L |
30932 | //RLC_SPM_ACCUM_CTRL |
30933 | #define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors__SHIFT 0x0 |
30934 | #define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation__SHIFT 0x1 |
30935 | #define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum__SHIFT 0x2 |
30936 | #define RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock__SHIFT 0x3 |
30937 | #define RLC_SPM_ACCUM_CTRL__StrobeStartSpm__SHIFT 0x4 |
30938 | #define RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum__SHIFT 0x8 |
30939 | #define RLC_SPM_ACCUM_CTRL__StrobeStartSwa__SHIFT 0x9 |
30940 | #define RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires__SHIFT 0xa |
30941 | #define RLC_SPM_ACCUM_CTRL__RESERVED__SHIFT 0xb |
30942 | #define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors_MASK 0x00000001L |
30943 | #define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation_MASK 0x00000002L |
30944 | #define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum_MASK 0x00000004L |
30945 | #define RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock_MASK 0x00000008L |
30946 | #define RLC_SPM_ACCUM_CTRL__StrobeStartSpm_MASK 0x000000F0L |
30947 | #define RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum_MASK 0x00000100L |
30948 | #define RLC_SPM_ACCUM_CTRL__StrobeStartSwa_MASK 0x00000200L |
30949 | #define RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires_MASK 0x00000400L |
30950 | #define RLC_SPM_ACCUM_CTRL__RESERVED_MASK 0xFFFFF800L |
30951 | //RLC_SPM_ACCUM_MODE |
30952 | #define RLC_SPM_ACCUM_MODE__EnableAccum__SHIFT 0x0 |
30953 | #define RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode__SHIFT 0x1 |
30954 | #define RLC_SPM_ACCUM_MODE__EnableSPPMode__SHIFT 0x2 |
30955 | #define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable__SHIFT 0x3 |
30956 | #define RLC_SPM_ACCUM_MODE__SwaAutoResetPerfmonDisable__SHIFT 0x4 |
30957 | #define RLC_SPM_ACCUM_MODE__AutoAccumEn__SHIFT 0x5 |
30958 | #define RLC_SPM_ACCUM_MODE__SwaAutoAccumEn__SHIFT 0x6 |
30959 | #define RLC_SPM_ACCUM_MODE__AutoSpmEn__SHIFT 0x7 |
30960 | #define RLC_SPM_ACCUM_MODE__SwaAutoSpmEn__SHIFT 0x8 |
30961 | #define RLC_SPM_ACCUM_MODE__Globals_LoadOverride__SHIFT 0x9 |
30962 | #define RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride__SHIFT 0xa |
30963 | #define RLC_SPM_ACCUM_MODE__SE0_LoadOverride__SHIFT 0xb |
30964 | #define RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride__SHIFT 0xc |
30965 | #define RLC_SPM_ACCUM_MODE__SE1_LoadOverride__SHIFT 0xd |
30966 | #define RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride__SHIFT 0xe |
30967 | #define RLC_SPM_ACCUM_MODE__SE2_LoadOverride__SHIFT 0xf |
30968 | #define RLC_SPM_ACCUM_MODE__SE2_SwaLoadOverride__SHIFT 0x10 |
30969 | #define RLC_SPM_ACCUM_MODE__SE3_LoadOverride__SHIFT 0x11 |
30970 | #define RLC_SPM_ACCUM_MODE__SE3_SwaLoadOverride__SHIFT 0x12 |
30971 | #define RLC_SPM_ACCUM_MODE__EnableAccum_MASK 0x00000001L |
30972 | #define RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode_MASK 0x00000002L |
30973 | #define RLC_SPM_ACCUM_MODE__EnableSPPMode_MASK 0x00000004L |
30974 | #define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable_MASK 0x00000008L |
30975 | #define RLC_SPM_ACCUM_MODE__SwaAutoResetPerfmonDisable_MASK 0x00000010L |
30976 | #define RLC_SPM_ACCUM_MODE__AutoAccumEn_MASK 0x00000020L |
30977 | #define RLC_SPM_ACCUM_MODE__SwaAutoAccumEn_MASK 0x00000040L |
30978 | #define RLC_SPM_ACCUM_MODE__AutoSpmEn_MASK 0x00000080L |
30979 | #define RLC_SPM_ACCUM_MODE__SwaAutoSpmEn_MASK 0x00000100L |
30980 | #define RLC_SPM_ACCUM_MODE__Globals_LoadOverride_MASK 0x00000200L |
30981 | #define RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride_MASK 0x00000400L |
30982 | #define RLC_SPM_ACCUM_MODE__SE0_LoadOverride_MASK 0x00000800L |
30983 | #define RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride_MASK 0x00001000L |
30984 | #define RLC_SPM_ACCUM_MODE__SE1_LoadOverride_MASK 0x00002000L |
30985 | #define RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride_MASK 0x00004000L |
30986 | #define RLC_SPM_ACCUM_MODE__SE2_LoadOverride_MASK 0x00008000L |
30987 | #define RLC_SPM_ACCUM_MODE__SE2_SwaLoadOverride_MASK 0x00010000L |
30988 | #define RLC_SPM_ACCUM_MODE__SE3_LoadOverride_MASK 0x00020000L |
30989 | #define RLC_SPM_ACCUM_MODE__SE3_SwaLoadOverride_MASK 0x00040000L |
30990 | //RLC_SPM_ACCUM_THRESHOLD |
30991 | #define RLC_SPM_ACCUM_THRESHOLD__Threshold__SHIFT 0x0 |
30992 | #define RLC_SPM_ACCUM_THRESHOLD__Threshold_MASK 0x0000FFFFL |
30993 | //RLC_SPM_ACCUM_SAMPLES_REQUESTED |
30994 | #define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested__SHIFT 0x0 |
30995 | #define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested_MASK 0x000000FFL |
30996 | //RLC_SPM_ACCUM_DATARAM_WRCOUNT |
30997 | #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount__SHIFT 0x0 |
30998 | #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED__SHIFT 0x13 |
30999 | #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount_MASK 0x0007FFFFL |
31000 | #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED_MASK 0xFFF80000L |
31001 | //RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE |
31002 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x0 |
31003 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x8 |
31004 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x10 |
31005 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE__SHIFT 0x18 |
31006 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x000000FFL |
31007 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x0000FF00L |
31008 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x00FF0000L |
31009 | #define RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE_MASK 0xFF000000L |
31010 | //RLC_SPM_PERFMON_GLB_SEGMENT_SIZE |
31011 | #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 |
31012 | #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0x8 |
31013 | #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__RESERVED__SHIFT 0x10 |
31014 | #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL |
31015 | #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000FF00L |
31016 | #define RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__RESERVED_MASK 0xFFFF0000L |
31017 | //RLC_SPM_VIRT_CTRL |
31018 | #define RLC_SPM_VIRT_CTRL__PauseSpmSamplingRequest__SHIFT 0x0 |
31019 | #define RLC_SPM_VIRT_CTRL__PauseSpmSamplingRequest_MASK 0x00000001L |
31020 | //RLC_SPM_PERFMON_SWA_SEGMENT_SIZE |
31021 | #define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 |
31022 | #define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 |
31023 | #define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb |
31024 | #define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 |
31025 | #define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 |
31026 | #define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a |
31027 | #define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__RESERVED__SHIFT 0x1f |
31028 | #define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL |
31029 | #define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L |
31030 | #define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L |
31031 | #define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L |
31032 | #define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L |
31033 | #define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L |
31034 | #define RLC_SPM_PERFMON_SWA_SEGMENT_SIZE__RESERVED_MASK 0x80000000L |
31035 | //RLC_SPM_VIRT_STATUS |
31036 | #define RLC_SPM_VIRT_STATUS__SpmSamplingPaused__SHIFT 0x0 |
31037 | #define RLC_SPM_VIRT_STATUS__SpmSamplingPaused_MASK 0x00000001L |
31038 | //RLC_SPM_GFXCLOCK_HIGHCOUNT |
31039 | #define RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT__SHIFT 0x0 |
31040 | #define RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT_MASK 0xFFFFFFFFL |
31041 | //RLC_SPM_GFXCLOCK_LOWCOUNT |
31042 | #define RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT__SHIFT 0x0 |
31043 | #define RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT_MASK 0xFFFFFFFFL |
31044 | //RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE |
31045 | #define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x0 |
31046 | #define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x8 |
31047 | #define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x10 |
31048 | #define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE__SHIFT 0x18 |
31049 | #define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x000000FFL |
31050 | #define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x0000FF00L |
31051 | #define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x00FF0000L |
31052 | #define RLC_SPM_PERFMON_SWA_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE_MASK 0xFF000000L |
31053 | //RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET |
31054 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET__OFFSET__SHIFT 0x0 |
31055 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET__RESERVED__SHIFT 0x10 |
31056 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET__OFFSET_MASK 0x0000FFFFL |
31057 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR_OFFSET__RESERVED_MASK 0xFFFF0000L |
31058 | //RLC_SPM_SE_MUXSEL_ADDR_OFFSET |
31059 | #define RLC_SPM_SE_MUXSEL_ADDR_OFFSET__OFFSET__SHIFT 0x0 |
31060 | #define RLC_SPM_SE_MUXSEL_ADDR_OFFSET__RESERVED__SHIFT 0x10 |
31061 | #define RLC_SPM_SE_MUXSEL_ADDR_OFFSET__OFFSET_MASK 0x0000FFFFL |
31062 | #define RLC_SPM_SE_MUXSEL_ADDR_OFFSET__RESERVED_MASK 0xFFFF0000L |
31063 | //RLC_SPM_ACCUM_SWA_DATARAM_ADDR |
31064 | #define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__addr__SHIFT 0x0 |
31065 | #define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__RESERVED__SHIFT 0x7 |
31066 | #define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__addr_MASK 0x0000007FL |
31067 | #define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__RESERVED_MASK 0xFFFFFF80L |
31068 | //RLC_SPM_ACCUM_SWA_DATARAM_DATA |
31069 | #define RLC_SPM_ACCUM_SWA_DATARAM_DATA__data__SHIFT 0x0 |
31070 | #define RLC_SPM_ACCUM_SWA_DATARAM_DATA__data_MASK 0xFFFFFFFFL |
31071 | //RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET |
31072 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset__SHIFT 0x0 |
31073 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset__SHIFT 0x8 |
31074 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset__SHIFT 0x10 |
31075 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__RESERVED__SHIFT 0x18 |
31076 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset_MASK 0x000000FFL |
31077 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset_MASK 0x0000FF00L |
31078 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset_MASK 0x00FF0000L |
31079 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__RESERVED_MASK 0xFF000000L |
31080 | //RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE |
31081 | #define RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 |
31082 | #define RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0x8 |
31083 | #define RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE__RESERVED__SHIFT 0x10 |
31084 | #define RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL |
31085 | #define RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000FF00L |
31086 | #define RLC_SPM_PERFMON_SWA_GLB_SEGMENT_SIZE__RESERVED_MASK 0xFFFF0000L |
31087 | //RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS |
31088 | #define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region__SHIFT 0x0 |
31089 | #define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region__SHIFT 0x8 |
31090 | #define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__RESERVED__SHIFT 0x10 |
31091 | #define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region_MASK 0x000000FFL |
31092 | #define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region_MASK 0x0000FF00L |
31093 | #define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__RESERVED_MASK 0xFFFF0000L |
31094 | //RLC_PERFMON_CNTL |
31095 | #define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
31096 | #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa |
31097 | #define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L |
31098 | #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L |
31099 | //RLC_PERFCOUNTER0_SELECT |
31100 | #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 |
31101 | #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000FFL |
31102 | //RLC_PERFCOUNTER1_SELECT |
31103 | #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 |
31104 | #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000FFL |
31105 | //RLC_GPU_IOV_PERF_CNT_CNTL |
31106 | #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0 |
31107 | #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1 |
31108 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2 |
31109 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3 |
31110 | #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L |
31111 | #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L |
31112 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L |
31113 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L |
31114 | //RLC_GPU_IOV_PERF_CNT_WR_ADDR |
31115 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0 |
31116 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4 |
31117 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6 |
31118 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL |
31119 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L |
31120 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L |
31121 | //RLC_GPU_IOV_PERF_CNT_WR_DATA |
31122 | #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0 |
31123 | #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0xFFFFFFFFL |
31124 | //RLC_GPU_IOV_PERF_CNT_RD_ADDR |
31125 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0 |
31126 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4 |
31127 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6 |
31128 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL |
31129 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L |
31130 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L |
31131 | //RLC_GPU_IOV_PERF_CNT_RD_DATA |
31132 | #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0 |
31133 | #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0xFFFFFFFFL |
31134 | //RLC_PERFMON_CLK_CNTL |
31135 | #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0 |
31136 | #define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L |
31137 | //RMI_PERFCOUNTER0_SELECT |
31138 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31139 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31140 | #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31141 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31142 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31143 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL |
31144 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L |
31145 | #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31146 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31147 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31148 | //RMI_PERFCOUNTER0_SELECT1 |
31149 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31150 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31151 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
31152 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
31153 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL |
31154 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L |
31155 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31156 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31157 | //RMI_PERFCOUNTER1_SELECT |
31158 | #define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31159 | #define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
31160 | #define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL |
31161 | #define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
31162 | //RMI_PERFCOUNTER2_SELECT |
31163 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
31164 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
31165 | #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
31166 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
31167 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
31168 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL |
31169 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L |
31170 | #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
31171 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
31172 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
31173 | //RMI_PERFCOUNTER2_SELECT1 |
31174 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
31175 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
31176 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
31177 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
31178 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL |
31179 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L |
31180 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31181 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31182 | //RMI_PERFCOUNTER3_SELECT |
31183 | #define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
31184 | #define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
31185 | #define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL |
31186 | #define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
31187 | //RMI_PERF_COUNTER_CNTL |
31188 | #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0 |
31189 | #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2 |
31190 | #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4 |
31191 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6 |
31192 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8 |
31193 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa |
31194 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe |
31195 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13 |
31196 | #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19 |
31197 | #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a |
31198 | #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L |
31199 | #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL |
31200 | #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L |
31201 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L |
31202 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L |
31203 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L |
31204 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L |
31205 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L |
31206 | #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L |
31207 | #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L |
31208 | //GCR_PERFCOUNTER0_SELECT |
31209 | #define GCR_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31210 | #define GCR_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31211 | #define GCR_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31212 | #define GCR_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31213 | #define GCR_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31214 | #define GCR_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL |
31215 | #define GCR_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L |
31216 | #define GCR_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31217 | #define GCR_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31218 | #define GCR_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31219 | //GCR_PERFCOUNTER0_SELECT1 |
31220 | #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31221 | #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31222 | #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
31223 | #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
31224 | #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL |
31225 | #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L |
31226 | #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31227 | #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31228 | //GCR_PERFCOUNTER1_SELECT |
31229 | #define GCR_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31230 | #define GCR_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x18 |
31231 | #define GCR_PERFCOUNTER1_SELECT__CNTL_MODE__SHIFT 0x1c |
31232 | #define GCR_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL |
31233 | #define GCR_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0x0F000000L |
31234 | #define GCR_PERFCOUNTER1_SELECT__CNTL_MODE_MASK 0xF0000000L |
31235 | //UTCL1_PERFCOUNTER0_SELECT |
31236 | #define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31237 | #define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE__SHIFT 0x1c |
31238 | #define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
31239 | #define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE_MASK 0xF0000000L |
31240 | //UTCL1_PERFCOUNTER1_SELECT |
31241 | #define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31242 | #define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT 0x1c |
31243 | #define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
31244 | #define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK 0xF0000000L |
31245 | //PA_PH_PERFCOUNTER0_SELECT |
31246 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31247 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31248 | #define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31249 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31250 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31251 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
31252 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31253 | #define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31254 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31255 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31256 | //PA_PH_PERFCOUNTER0_SELECT1 |
31257 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31258 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31259 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
31260 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
31261 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31262 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31263 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31264 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31265 | //PA_PH_PERFCOUNTER1_SELECT |
31266 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31267 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
31268 | #define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
31269 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
31270 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
31271 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
31272 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31273 | #define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31274 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
31275 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
31276 | //PA_PH_PERFCOUNTER2_SELECT |
31277 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
31278 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
31279 | #define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
31280 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
31281 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
31282 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
31283 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31284 | #define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
31285 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
31286 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
31287 | //PA_PH_PERFCOUNTER3_SELECT |
31288 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
31289 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
31290 | #define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
31291 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
31292 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
31293 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
31294 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31295 | #define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
31296 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
31297 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
31298 | //PA_PH_PERFCOUNTER4_SELECT |
31299 | #define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
31300 | #define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL |
31301 | //PA_PH_PERFCOUNTER5_SELECT |
31302 | #define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
31303 | #define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL |
31304 | //PA_PH_PERFCOUNTER6_SELECT |
31305 | #define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 |
31306 | #define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL |
31307 | //PA_PH_PERFCOUNTER7_SELECT |
31308 | #define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 |
31309 | #define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL |
31310 | //PA_PH_PERFCOUNTER1_SELECT1 |
31311 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
31312 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
31313 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
31314 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
31315 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31316 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31317 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31318 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31319 | //PA_PH_PERFCOUNTER2_SELECT1 |
31320 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
31321 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
31322 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
31323 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
31324 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31325 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31326 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31327 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31328 | //PA_PH_PERFCOUNTER3_SELECT1 |
31329 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
31330 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
31331 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
31332 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
31333 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31334 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31335 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31336 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31337 | //GL1A_PERFCOUNTER0_SELECT |
31338 | #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31339 | #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31340 | #define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31341 | #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31342 | #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31343 | #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
31344 | #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31345 | #define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31346 | #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31347 | #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31348 | //GL1A_PERFCOUNTER0_SELECT1 |
31349 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31350 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31351 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
31352 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
31353 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31354 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31355 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
31356 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
31357 | //GL1A_PERFCOUNTER1_SELECT |
31358 | #define GL1A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31359 | #define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
31360 | #define GL1A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
31361 | #define GL1A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
31362 | #define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31363 | #define GL1A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
31364 | //GL1A_PERFCOUNTER2_SELECT |
31365 | #define GL1A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
31366 | #define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
31367 | #define GL1A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
31368 | #define GL1A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
31369 | #define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
31370 | #define GL1A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
31371 | //GL1A_PERFCOUNTER3_SELECT |
31372 | #define GL1A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
31373 | #define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
31374 | #define GL1A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
31375 | #define GL1A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
31376 | #define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
31377 | #define GL1A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
31378 | //CHA_PERFCOUNTER0_SELECT |
31379 | #define CHA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31380 | #define CHA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31381 | #define CHA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31382 | #define CHA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31383 | #define CHA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31384 | #define CHA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
31385 | #define CHA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31386 | #define CHA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31387 | #define CHA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31388 | #define CHA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31389 | //CHA_PERFCOUNTER0_SELECT1 |
31390 | #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31391 | #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31392 | #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
31393 | #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
31394 | #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31395 | #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31396 | #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
31397 | #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
31398 | //CHA_PERFCOUNTER1_SELECT |
31399 | #define CHA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31400 | #define CHA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
31401 | #define CHA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
31402 | #define CHA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
31403 | #define CHA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31404 | #define CHA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
31405 | //CHA_PERFCOUNTER2_SELECT |
31406 | #define CHA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
31407 | #define CHA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
31408 | #define CHA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
31409 | #define CHA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
31410 | #define CHA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
31411 | #define CHA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
31412 | //CHA_PERFCOUNTER3_SELECT |
31413 | #define CHA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
31414 | #define CHA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
31415 | #define CHA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
31416 | #define CHA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
31417 | #define CHA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
31418 | #define CHA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
31419 | //GUS_PERFCOUNTER2_SELECT |
31420 | #define GUS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
31421 | #define GUS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
31422 | #define GUS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
31423 | #define GUS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
31424 | #define GUS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
31425 | #define GUS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
31426 | #define GUS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31427 | #define GUS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
31428 | #define GUS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
31429 | #define GUS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
31430 | //GUS_PERFCOUNTER2_SELECT1 |
31431 | #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
31432 | #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
31433 | #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
31434 | #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
31435 | #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31436 | #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31437 | #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31438 | #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31439 | //GUS_PERFCOUNTER2_MODE |
31440 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT 0x0 |
31441 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT 0x2 |
31442 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT 0x4 |
31443 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT 0x6 |
31444 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT 0x8 |
31445 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT 0xc |
31446 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT 0x10 |
31447 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT 0x14 |
31448 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK 0x00000003L |
31449 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK 0x0000000CL |
31450 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK 0x00000030L |
31451 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK 0x000000C0L |
31452 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK 0x00000F00L |
31453 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK 0x0000F000L |
31454 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK 0x000F0000L |
31455 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK 0x00F00000L |
31456 | //GUS_PERFCOUNTER0_CFG |
31457 | #define GUS_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
31458 | #define GUS_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
31459 | #define GUS_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
31460 | #define GUS_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
31461 | #define GUS_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
31462 | #define GUS_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
31463 | #define GUS_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31464 | #define GUS_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
31465 | #define GUS_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
31466 | #define GUS_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
31467 | //GUS_PERFCOUNTER1_CFG |
31468 | #define GUS_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
31469 | #define GUS_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
31470 | #define GUS_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
31471 | #define GUS_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
31472 | #define GUS_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
31473 | #define GUS_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
31474 | #define GUS_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31475 | #define GUS_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
31476 | #define GUS_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
31477 | #define GUS_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
31478 | //GUS_PERFCOUNTER_RSLT_CNTL |
31479 | #define GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
31480 | #define GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
31481 | #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
31482 | #define GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
31483 | #define GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
31484 | #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
31485 | #define GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
31486 | #define GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
31487 | #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
31488 | #define GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
31489 | #define GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
31490 | #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
31491 | |
31492 | |
31493 | // addressBlock: gc_gcvml2pldec |
31494 | //GCMC_VM_L2_PERFCOUNTER0_CFG |
31495 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
31496 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
31497 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
31498 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
31499 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
31500 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
31501 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31502 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
31503 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
31504 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
31505 | //GCMC_VM_L2_PERFCOUNTER1_CFG |
31506 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
31507 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
31508 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
31509 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
31510 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
31511 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
31512 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31513 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
31514 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
31515 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
31516 | //GCMC_VM_L2_PERFCOUNTER2_CFG |
31517 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
31518 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
31519 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
31520 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
31521 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
31522 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
31523 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31524 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
31525 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
31526 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
31527 | //GCMC_VM_L2_PERFCOUNTER3_CFG |
31528 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 |
31529 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 |
31530 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 |
31531 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c |
31532 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d |
31533 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL |
31534 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31535 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L |
31536 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L |
31537 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L |
31538 | //GCMC_VM_L2_PERFCOUNTER4_CFG |
31539 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 |
31540 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 |
31541 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 |
31542 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c |
31543 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d |
31544 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL |
31545 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31546 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L |
31547 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L |
31548 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L |
31549 | //GCMC_VM_L2_PERFCOUNTER5_CFG |
31550 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 |
31551 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 |
31552 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 |
31553 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c |
31554 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d |
31555 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL |
31556 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31557 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L |
31558 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L |
31559 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L |
31560 | //GCMC_VM_L2_PERFCOUNTER6_CFG |
31561 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 |
31562 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 |
31563 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 |
31564 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c |
31565 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d |
31566 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL |
31567 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31568 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L |
31569 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L |
31570 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L |
31571 | //GCMC_VM_L2_PERFCOUNTER7_CFG |
31572 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 |
31573 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 |
31574 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 |
31575 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c |
31576 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d |
31577 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL |
31578 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31579 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L |
31580 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L |
31581 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L |
31582 | //GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL |
31583 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
31584 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
31585 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
31586 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
31587 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
31588 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
31589 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
31590 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
31591 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
31592 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
31593 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
31594 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
31595 | //GCUTCL2_PERFCOUNTER0_CFG |
31596 | #define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
31597 | #define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
31598 | #define GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
31599 | #define GCUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
31600 | #define GCUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
31601 | #define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
31602 | #define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31603 | #define GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
31604 | #define GCUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
31605 | #define GCUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
31606 | //GCUTCL2_PERFCOUNTER1_CFG |
31607 | #define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
31608 | #define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
31609 | #define GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
31610 | #define GCUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
31611 | #define GCUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
31612 | #define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
31613 | #define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31614 | #define GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
31615 | #define GCUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
31616 | #define GCUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
31617 | //GCUTCL2_PERFCOUNTER2_CFG |
31618 | #define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
31619 | #define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
31620 | #define GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
31621 | #define GCUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
31622 | #define GCUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
31623 | #define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
31624 | #define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31625 | #define GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
31626 | #define GCUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
31627 | #define GCUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
31628 | //GCUTCL2_PERFCOUNTER3_CFG |
31629 | #define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 |
31630 | #define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 |
31631 | #define GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 |
31632 | #define GCUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c |
31633 | #define GCUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d |
31634 | #define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL |
31635 | #define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31636 | #define GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L |
31637 | #define GCUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L |
31638 | #define GCUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L |
31639 | //GCUTCL2_PERFCOUNTER_RSLT_CNTL |
31640 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
31641 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
31642 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
31643 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
31644 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
31645 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
31646 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
31647 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
31648 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
31649 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
31650 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
31651 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
31652 | |
31653 | |
31654 | // addressBlock: gc_gcvml2perfsdec |
31655 | //GCVML2_PERFCOUNTER2_0_SELECT |
31656 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL__SHIFT 0x0 |
31657 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1__SHIFT 0xa |
31658 | #define GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE__SHIFT 0x14 |
31659 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1__SHIFT 0x18 |
31660 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE__SHIFT 0x1c |
31661 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL_MASK 0x000003FFL |
31662 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31663 | #define GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31664 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31665 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE_MASK 0xF0000000L |
31666 | //GCVML2_PERFCOUNTER2_1_SELECT |
31667 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL__SHIFT 0x0 |
31668 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1__SHIFT 0xa |
31669 | #define GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE__SHIFT 0x14 |
31670 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1__SHIFT 0x18 |
31671 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE__SHIFT 0x1c |
31672 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL_MASK 0x000003FFL |
31673 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31674 | #define GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31675 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1_MASK 0x0F000000L |
31676 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE_MASK 0xF0000000L |
31677 | //GCVML2_PERFCOUNTER2_0_SELECT1 |
31678 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31679 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3__SHIFT 0xa |
31680 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3__SHIFT 0x18 |
31681 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2__SHIFT 0x1c |
31682 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31683 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31684 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31685 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31686 | //GCVML2_PERFCOUNTER2_1_SELECT1 |
31687 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2__SHIFT 0x0 |
31688 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3__SHIFT 0xa |
31689 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3__SHIFT 0x18 |
31690 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2__SHIFT 0x1c |
31691 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31692 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31693 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31694 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31695 | //GCVML2_PERFCOUNTER2_0_MODE |
31696 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0__SHIFT 0x0 |
31697 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1__SHIFT 0x2 |
31698 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2__SHIFT 0x4 |
31699 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3__SHIFT 0x6 |
31700 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0__SHIFT 0x8 |
31701 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1__SHIFT 0xc |
31702 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2__SHIFT 0x10 |
31703 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3__SHIFT 0x14 |
31704 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0_MASK 0x00000003L |
31705 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1_MASK 0x0000000CL |
31706 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2_MASK 0x00000030L |
31707 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3_MASK 0x000000C0L |
31708 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0_MASK 0x00000F00L |
31709 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1_MASK 0x0000F000L |
31710 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2_MASK 0x000F0000L |
31711 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3_MASK 0x00F00000L |
31712 | //GCVML2_PERFCOUNTER2_1_MODE |
31713 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0__SHIFT 0x0 |
31714 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1__SHIFT 0x2 |
31715 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2__SHIFT 0x4 |
31716 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3__SHIFT 0x6 |
31717 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0__SHIFT 0x8 |
31718 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1__SHIFT 0xc |
31719 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2__SHIFT 0x10 |
31720 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3__SHIFT 0x14 |
31721 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0_MASK 0x00000003L |
31722 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1_MASK 0x0000000CL |
31723 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2_MASK 0x00000030L |
31724 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3_MASK 0x000000C0L |
31725 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0_MASK 0x00000F00L |
31726 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1_MASK 0x0000F000L |
31727 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2_MASK 0x000F0000L |
31728 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3_MASK 0x00F00000L |
31729 | |
31730 | |
31731 | // addressBlock: gc_sdma0_sdma0perfsdec |
31732 | //SDMA0_PERFCNT_PERFCOUNTER0_CFG |
31733 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
31734 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
31735 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
31736 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
31737 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
31738 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
31739 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31740 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
31741 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
31742 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
31743 | //SDMA0_PERFCNT_PERFCOUNTER1_CFG |
31744 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
31745 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
31746 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
31747 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
31748 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
31749 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
31750 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31751 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
31752 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
31753 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
31754 | //SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL |
31755 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
31756 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
31757 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
31758 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
31759 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
31760 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
31761 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
31762 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
31763 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
31764 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
31765 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
31766 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
31767 | //SDMA0_PERFCNT_MISC_CNTL |
31768 | #define SDMA0_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 |
31769 | #define SDMA0_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL |
31770 | //SDMA0_PERFCOUNTER0_SELECT |
31771 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31772 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31773 | #define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31774 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31775 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31776 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
31777 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31778 | #define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31779 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31780 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31781 | //SDMA0_PERFCOUNTER0_SELECT1 |
31782 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31783 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31784 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
31785 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
31786 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31787 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31788 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31789 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31790 | //SDMA0_PERFCOUNTER1_SELECT |
31791 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31792 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
31793 | #define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
31794 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
31795 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
31796 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
31797 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31798 | #define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31799 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
31800 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
31801 | //SDMA0_PERFCOUNTER1_SELECT1 |
31802 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
31803 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
31804 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
31805 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
31806 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31807 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31808 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31809 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31810 | |
31811 | |
31812 | // addressBlock: gc_sdma1_sdma1perfsdec |
31813 | //SDMA1_PERFCNT_PERFCOUNTER0_CFG |
31814 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
31815 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
31816 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
31817 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
31818 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
31819 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
31820 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31821 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
31822 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
31823 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
31824 | //SDMA1_PERFCNT_PERFCOUNTER1_CFG |
31825 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
31826 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
31827 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
31828 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
31829 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
31830 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
31831 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31832 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
31833 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
31834 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
31835 | //SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL |
31836 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
31837 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
31838 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
31839 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
31840 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
31841 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
31842 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
31843 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
31844 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
31845 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
31846 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
31847 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
31848 | //SDMA1_PERFCNT_MISC_CNTL |
31849 | #define SDMA1_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 |
31850 | #define SDMA1_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL |
31851 | //SDMA1_PERFCOUNTER0_SELECT |
31852 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31853 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31854 | #define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31855 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31856 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31857 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
31858 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31859 | #define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31860 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31861 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31862 | //SDMA1_PERFCOUNTER0_SELECT1 |
31863 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31864 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31865 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
31866 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
31867 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31868 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31869 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31870 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31871 | //SDMA1_PERFCOUNTER1_SELECT |
31872 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31873 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
31874 | #define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
31875 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
31876 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
31877 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
31878 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31879 | #define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31880 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
31881 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
31882 | //SDMA1_PERFCOUNTER1_SELECT1 |
31883 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
31884 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
31885 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
31886 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
31887 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31888 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31889 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31890 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31891 | |
31892 | |
31893 | // addressBlock: gc_sdma2_sdma2perfsdec |
31894 | //SDMA2_PERFCNT_PERFCOUNTER0_CFG |
31895 | #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
31896 | #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
31897 | #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
31898 | #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
31899 | #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
31900 | #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
31901 | #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31902 | #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
31903 | #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
31904 | #define SDMA2_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
31905 | //SDMA2_PERFCNT_PERFCOUNTER1_CFG |
31906 | #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
31907 | #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
31908 | #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
31909 | #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
31910 | #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
31911 | #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
31912 | #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31913 | #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
31914 | #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
31915 | #define SDMA2_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
31916 | //SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL |
31917 | #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
31918 | #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
31919 | #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
31920 | #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
31921 | #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
31922 | #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
31923 | #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
31924 | #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
31925 | #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
31926 | #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
31927 | #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
31928 | #define SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
31929 | //SDMA2_PERFCNT_MISC_CNTL |
31930 | #define SDMA2_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 |
31931 | #define SDMA2_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL |
31932 | //SDMA2_PERFCOUNTER0_SELECT |
31933 | #define SDMA2_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
31934 | #define SDMA2_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
31935 | #define SDMA2_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
31936 | #define SDMA2_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
31937 | #define SDMA2_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
31938 | #define SDMA2_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
31939 | #define SDMA2_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31940 | #define SDMA2_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
31941 | #define SDMA2_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
31942 | #define SDMA2_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
31943 | //SDMA2_PERFCOUNTER0_SELECT1 |
31944 | #define SDMA2_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
31945 | #define SDMA2_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
31946 | #define SDMA2_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
31947 | #define SDMA2_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
31948 | #define SDMA2_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31949 | #define SDMA2_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31950 | #define SDMA2_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31951 | #define SDMA2_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31952 | //SDMA2_PERFCOUNTER1_SELECT |
31953 | #define SDMA2_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
31954 | #define SDMA2_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
31955 | #define SDMA2_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
31956 | #define SDMA2_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
31957 | #define SDMA2_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
31958 | #define SDMA2_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
31959 | #define SDMA2_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
31960 | #define SDMA2_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
31961 | #define SDMA2_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
31962 | #define SDMA2_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
31963 | //SDMA2_PERFCOUNTER1_SELECT1 |
31964 | #define SDMA2_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
31965 | #define SDMA2_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
31966 | #define SDMA2_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
31967 | #define SDMA2_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
31968 | #define SDMA2_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
31969 | #define SDMA2_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
31970 | #define SDMA2_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
31971 | #define SDMA2_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
31972 | |
31973 | |
31974 | // addressBlock: gc_sdma3_sdma3perfsdec |
31975 | //SDMA3_PERFCNT_PERFCOUNTER0_CFG |
31976 | #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
31977 | #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
31978 | #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
31979 | #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
31980 | #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
31981 | #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
31982 | #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31983 | #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
31984 | #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
31985 | #define SDMA3_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
31986 | //SDMA3_PERFCNT_PERFCOUNTER1_CFG |
31987 | #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
31988 | #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
31989 | #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
31990 | #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
31991 | #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
31992 | #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
31993 | #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
31994 | #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
31995 | #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
31996 | #define SDMA3_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
31997 | //SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL |
31998 | #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
31999 | #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
32000 | #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
32001 | #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
32002 | #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
32003 | #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
32004 | #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
32005 | #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
32006 | #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
32007 | #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
32008 | #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
32009 | #define SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
32010 | //SDMA3_PERFCNT_MISC_CNTL |
32011 | #define SDMA3_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 |
32012 | #define SDMA3_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL |
32013 | //SDMA3_PERFCOUNTER0_SELECT |
32014 | #define SDMA3_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
32015 | #define SDMA3_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
32016 | #define SDMA3_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
32017 | #define SDMA3_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
32018 | #define SDMA3_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
32019 | #define SDMA3_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
32020 | #define SDMA3_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32021 | #define SDMA3_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
32022 | #define SDMA3_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
32023 | #define SDMA3_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
32024 | //SDMA3_PERFCOUNTER0_SELECT1 |
32025 | #define SDMA3_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
32026 | #define SDMA3_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
32027 | #define SDMA3_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
32028 | #define SDMA3_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
32029 | #define SDMA3_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32030 | #define SDMA3_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32031 | #define SDMA3_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
32032 | #define SDMA3_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
32033 | //SDMA3_PERFCOUNTER1_SELECT |
32034 | #define SDMA3_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
32035 | #define SDMA3_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
32036 | #define SDMA3_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
32037 | #define SDMA3_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
32038 | #define SDMA3_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
32039 | #define SDMA3_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
32040 | #define SDMA3_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
32041 | #define SDMA3_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
32042 | #define SDMA3_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
32043 | #define SDMA3_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
32044 | //SDMA3_PERFCOUNTER1_SELECT1 |
32045 | #define SDMA3_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
32046 | #define SDMA3_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
32047 | #define SDMA3_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
32048 | #define SDMA3_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
32049 | #define SDMA3_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
32050 | #define SDMA3_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
32051 | #define SDMA3_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
32052 | #define SDMA3_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
32053 | |
32054 | |
32055 | |
32056 | |
32057 | // addressBlock: gc_grtavfsdec |
32058 | //GRTAVFS_RTAVFS_REG_ADDR |
32059 | #define GRTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT 0x0 |
32060 | #define GRTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR_MASK 0x000003FFL |
32061 | //RTAVFS_RTAVFS_REG_ADDR |
32062 | #define RTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT 0x0 |
32063 | #define RTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR_MASK 0x000003FFL |
32064 | //GRTAVFS_RTAVFS_WR_DATA |
32065 | #define GRTAVFS_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT 0x0 |
32066 | #define GRTAVFS_RTAVFS_WR_DATA__RTAVFSDATA_MASK 0xFFFFFFFFL |
32067 | //RTAVFS_RTAVFS_WR_DATA |
32068 | #define RTAVFS_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT 0x0 |
32069 | #define RTAVFS_RTAVFS_WR_DATA__RTAVFSDATA_MASK 0xFFFFFFFFL |
32070 | //GRTAVFS_GENERAL_0 |
32071 | #define GRTAVFS_GENERAL_0__DATA__SHIFT 0x0 |
32072 | #define GRTAVFS_GENERAL_0__DATA_MASK 0xFFFFFFFFL |
32073 | //GRTAVFS_RTAVFS_RD_DATA |
32074 | #define GRTAVFS_RTAVFS_RD_DATA__RTAVFSDATA__SHIFT 0x0 |
32075 | #define GRTAVFS_RTAVFS_RD_DATA__RTAVFSDATA_MASK 0xFFFFFFFFL |
32076 | //GRTAVFS_RTAVFS_REG_CTRL |
32077 | #define GRTAVFS_RTAVFS_REG_CTRL__SET_WR_EN__SHIFT 0x0 |
32078 | #define GRTAVFS_RTAVFS_REG_CTRL__SET_RD_EN__SHIFT 0x1 |
32079 | #define GRTAVFS_RTAVFS_REG_CTRL__SET_WR_EN_MASK 0x00000001L |
32080 | #define GRTAVFS_RTAVFS_REG_CTRL__SET_RD_EN_MASK 0x00000002L |
32081 | //GRTAVFS_RTAVFS_REG_STATUS |
32082 | #define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_WR_ACK__SHIFT 0x0 |
32083 | #define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID__SHIFT 0x1 |
32084 | #define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_WR_ACK_MASK 0x00000001L |
32085 | #define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID_MASK 0x00000002L |
32086 | //GRTAVFS_TARG_FREQ |
32087 | #define GRTAVFS_TARG_FREQ__TARGET_FREQUENCY__SHIFT 0x0 |
32088 | #define GRTAVFS_TARG_FREQ__REQUEST__SHIFT 0x10 |
32089 | #define GRTAVFS_TARG_FREQ__RESERVED__SHIFT 0x11 |
32090 | #define GRTAVFS_TARG_FREQ__TARGET_FREQUENCY_MASK 0x0000FFFFL |
32091 | #define GRTAVFS_TARG_FREQ__REQUEST_MASK 0x00010000L |
32092 | #define GRTAVFS_TARG_FREQ__RESERVED_MASK 0xFFFE0000L |
32093 | //GRTAVFS_TARG_VOLT |
32094 | #define GRTAVFS_TARG_VOLT__TARGET_VOLTAGE__SHIFT 0x0 |
32095 | #define GRTAVFS_TARG_VOLT__VALID__SHIFT 0xa |
32096 | #define GRTAVFS_TARG_VOLT__RESERVED__SHIFT 0xb |
32097 | #define GRTAVFS_TARG_VOLT__TARGET_VOLTAGE_MASK 0x000003FFL |
32098 | #define GRTAVFS_TARG_VOLT__VALID_MASK 0x00000400L |
32099 | #define GRTAVFS_TARG_VOLT__RESERVED_MASK 0xFFFFF800L |
32100 | //GRTAVFS_SOFT_RESET |
32101 | #define GRTAVFS_SOFT_RESET__RESETN_OVERRIDE__SHIFT 0x0 |
32102 | #define GRTAVFS_SOFT_RESET__RESERVED__SHIFT 0x1 |
32103 | #define GRTAVFS_SOFT_RESET__RESETN_OVERRIDE_MASK 0x00000001L |
32104 | #define GRTAVFS_SOFT_RESET__RESERVED_MASK 0xFFFFFFFEL |
32105 | //GRTAVFS_PSM_CNTL |
32106 | #define GRTAVFS_PSM_CNTL__PSM_COUNT__SHIFT 0x0 |
32107 | #define GRTAVFS_PSM_CNTL__PSM_SAMPLE_EN__SHIFT 0xe |
32108 | #define GRTAVFS_PSM_CNTL__RESERVED__SHIFT 0xf |
32109 | #define GRTAVFS_PSM_CNTL__PSM_COUNT_MASK 0x00003FFFL |
32110 | #define GRTAVFS_PSM_CNTL__PSM_SAMPLE_EN_MASK 0x00004000L |
32111 | #define GRTAVFS_PSM_CNTL__RESERVED_MASK 0xFFFF8000L |
32112 | //GRTAVFS_CLK_CNTL |
32113 | #define GRTAVFS_CLK_CNTL__GRTAVFS_MUX_CLK_SEL__SHIFT 0x0 |
32114 | #define GRTAVFS_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL__SHIFT 0x1 |
32115 | #define GRTAVFS_CLK_CNTL__RESERVED__SHIFT 0x2 |
32116 | #define GRTAVFS_CLK_CNTL__GRTAVFS_MUX_CLK_SEL_MASK 0x00000001L |
32117 | #define GRTAVFS_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL_MASK 0x00000002L |
32118 | #define GRTAVFS_CLK_CNTL__RESERVED_MASK 0xFFFFFFFCL |
32119 | |
32120 | |
32121 | // addressBlock: gc_rlcdec |
32122 | //RLC_CNTL |
32123 | #define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 |
32124 | #define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 |
32125 | #define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 |
32126 | #define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 |
32127 | #define RLC_CNTL__RESERVED__SHIFT 0x4 |
32128 | #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L |
32129 | #define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L |
32130 | #define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L |
32131 | #define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L |
32132 | #define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L |
32133 | //RLC_F32_UCODE_VERSION |
32134 | #define RLC_F32_UCODE_VERSION__THREAD0_VERSION__SHIFT 0x0 |
32135 | #define RLC_F32_UCODE_VERSION__THREAD1_VERSION__SHIFT 0xa |
32136 | #define RLC_F32_UCODE_VERSION__THREAD2_VERSION__SHIFT 0x14 |
32137 | #define RLC_F32_UCODE_VERSION__THREAD0_VERSION_MASK 0x000003FFL |
32138 | #define RLC_F32_UCODE_VERSION__THREAD1_VERSION_MASK 0x000FFC00L |
32139 | #define RLC_F32_UCODE_VERSION__THREAD2_VERSION_MASK 0x3FF00000L |
32140 | //RLC_STAT |
32141 | #define RLC_STAT__RLC_BUSY__SHIFT 0x0 |
32142 | #define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x1 |
32143 | #define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x2 |
32144 | #define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x3 |
32145 | #define RLC_STAT__MC_BUSY__SHIFT 0x4 |
32146 | #define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5 |
32147 | #define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6 |
32148 | #define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7 |
32149 | #define RLC_STAT__RESERVED__SHIFT 0x8 |
32150 | #define RLC_STAT__RLC_BUSY_MASK 0x00000001L |
32151 | #define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000002L |
32152 | #define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000004L |
32153 | #define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000008L |
32154 | #define RLC_STAT__MC_BUSY_MASK 0x00000010L |
32155 | #define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L |
32156 | #define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L |
32157 | #define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L |
32158 | #define RLC_STAT__RESERVED_MASK 0xFFFFFF00L |
32159 | //RLC_MEM_SLP_CNTL |
32160 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 |
32161 | #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 |
32162 | #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 |
32163 | #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 |
32164 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 |
32165 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 |
32166 | #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 |
32167 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L |
32168 | #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L |
32169 | #define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL |
32170 | #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L |
32171 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L |
32172 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L |
32173 | #define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L |
32174 | //SMU_RLC_RESPONSE |
32175 | #define SMU_RLC_RESPONSE__RESP__SHIFT 0x0 |
32176 | #define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL |
32177 | //RLC_RLCV_SAFE_MODE |
32178 | #define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 |
32179 | #define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 |
32180 | #define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 |
32181 | #define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 |
32182 | #define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc |
32183 | #define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L |
32184 | #define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL |
32185 | #define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L |
32186 | #define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L |
32187 | #define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L |
32188 | //RLC_SMU_SAFE_MODE |
32189 | #define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 |
32190 | #define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 |
32191 | #define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 |
32192 | #define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 |
32193 | #define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc |
32194 | #define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L |
32195 | #define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL |
32196 | #define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L |
32197 | #define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L |
32198 | #define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L |
32199 | //RLC_RLCV_COMMAND |
32200 | #define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 |
32201 | #define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 |
32202 | #define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL |
32203 | #define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L |
32204 | //RLC_REFCLOCK_TIMESTAMP_LSB |
32205 | #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0 |
32206 | #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL |
32207 | //RLC_REFCLOCK_TIMESTAMP_MSB |
32208 | #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0 |
32209 | #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL |
32210 | //RLC_GPM_TIMER_INT_0 |
32211 | #define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0 |
32212 | #define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL |
32213 | //RLC_GPM_TIMER_INT_1 |
32214 | #define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0 |
32215 | #define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL |
32216 | //RLC_GPM_TIMER_INT_2 |
32217 | #define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0 |
32218 | #define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL |
32219 | //RLC_GPM_TIMER_CTRL |
32220 | #define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 |
32221 | #define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 |
32222 | #define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2 |
32223 | #define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3 |
32224 | #define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x4 |
32225 | #define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x5 |
32226 | #define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM__SHIFT 0x6 |
32227 | #define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM__SHIFT 0x7 |
32228 | #define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x8 |
32229 | #define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x9 |
32230 | #define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR__SHIFT 0xa |
32231 | #define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR__SHIFT 0xb |
32232 | #define RLC_GPM_TIMER_CTRL__TIMER_4_EN__SHIFT 0xc |
32233 | #define RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM__SHIFT 0xd |
32234 | #define RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR__SHIFT 0xe |
32235 | #define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0xf |
32236 | #define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L |
32237 | #define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L |
32238 | #define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L |
32239 | #define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L |
32240 | #define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000010L |
32241 | #define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000020L |
32242 | #define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM_MASK 0x00000040L |
32243 | #define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM_MASK 0x00000080L |
32244 | #define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00000100L |
32245 | #define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00000200L |
32246 | #define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR_MASK 0x00000400L |
32247 | #define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR_MASK 0x00000800L |
32248 | #define RLC_GPM_TIMER_CTRL__TIMER_4_EN_MASK 0x00001000L |
32249 | #define RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM_MASK 0x00002000L |
32250 | #define RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR_MASK 0x00004000L |
32251 | #define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFF8000L |
32252 | //RLC_LB_CNTR_MAX_1 |
32253 | #define RLC_LB_CNTR_MAX_1__LB_CNTR_MAX__SHIFT 0x0 |
32254 | #define RLC_LB_CNTR_MAX_1__LB_CNTR_MAX_MASK 0xFFFFFFFFL |
32255 | //RLC_GPM_TIMER_STAT |
32256 | #define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 |
32257 | #define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 |
32258 | #define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2 |
32259 | #define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3 |
32260 | #define RLC_GPM_TIMER_STAT__TIMER_4_STAT__SHIFT 0x4 |
32261 | #define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 |
32262 | #define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 |
32263 | #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa |
32264 | #define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT 0xb |
32265 | #define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xc |
32266 | #define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0xd |
32267 | #define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC__SHIFT 0xe |
32268 | #define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC__SHIFT 0xf |
32269 | #define RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC__SHIFT 0x10 |
32270 | #define RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC__SHIFT 0x11 |
32271 | #define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x12 |
32272 | #define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L |
32273 | #define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L |
32274 | #define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L |
32275 | #define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L |
32276 | #define RLC_GPM_TIMER_STAT__TIMER_4_STAT_MASK 0x00000010L |
32277 | #define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L |
32278 | #define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L |
32279 | #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK 0x00000400L |
32280 | #define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK 0x00000800L |
32281 | #define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00001000L |
32282 | #define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00002000L |
32283 | #define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC_MASK 0x00004000L |
32284 | #define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC_MASK 0x00008000L |
32285 | #define RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC_MASK 0x00010000L |
32286 | #define RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC_MASK 0x00020000L |
32287 | #define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFC0000L |
32288 | //RLC_GPM_TIMER_INT_3 |
32289 | #define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0 |
32290 | #define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL |
32291 | //RLC_GPM_LEGACY_INT_STAT |
32292 | #define RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED__SHIFT 0x0 |
32293 | #define RLC_GPM_LEGACY_INT_STAT__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT 0x1 |
32294 | #define RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED__SHIFT 0x2 |
32295 | #define RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED_MASK 0x00000001L |
32296 | #define RLC_GPM_LEGACY_INT_STAT__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK 0x00000002L |
32297 | #define RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED_MASK 0x00000004L |
32298 | //RLC_GPM_LEGACY_INT_CLEAR |
32299 | #define RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED__SHIFT 0x0 |
32300 | #define RLC_GPM_LEGACY_INT_CLEAR__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT 0x1 |
32301 | #define RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED__SHIFT 0x2 |
32302 | #define RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED_MASK 0x00000001L |
32303 | #define RLC_GPM_LEGACY_INT_CLEAR__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK 0x00000002L |
32304 | #define RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED_MASK 0x00000004L |
32305 | //RLC_INT_STAT |
32306 | #define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0 |
32307 | #define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8 |
32308 | #define RLC_INT_STAT__RESERVED__SHIFT 0x9 |
32309 | #define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL |
32310 | #define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L |
32311 | #define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L |
32312 | //RLC_LB_CNTL |
32313 | #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 |
32314 | #define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 |
32315 | #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 |
32316 | #define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 |
32317 | #define RLC_LB_CNTL__RESERVED__SHIFT 0x4 |
32318 | #define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L |
32319 | #define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L |
32320 | #define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L |
32321 | #define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L |
32322 | #define RLC_LB_CNTL__RESERVED_MASK 0xFFFFFFF0L |
32323 | //RLC_MGCG_CTRL |
32324 | #define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 |
32325 | #define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 |
32326 | #define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 |
32327 | #define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 |
32328 | #define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 |
32329 | #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf |
32330 | #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10 |
32331 | #define RLC_MGCG_CTRL__SPARE__SHIFT 0x11 |
32332 | #define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L |
32333 | #define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L |
32334 | #define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L |
32335 | #define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L |
32336 | #define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L |
32337 | #define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L |
32338 | #define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L |
32339 | #define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L |
32340 | //RLC_LB_CNTR_INIT_1 |
32341 | #define RLC_LB_CNTR_INIT_1__LB_CNTR_INIT__SHIFT 0x0 |
32342 | #define RLC_LB_CNTR_INIT_1__LB_CNTR_INIT_MASK 0xFFFFFFFFL |
32343 | //RLC_LB_CNTR_1 |
32344 | #define RLC_LB_CNTR_1__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 |
32345 | #define RLC_LB_CNTR_1__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL |
32346 | //RLC_JUMP_TABLE_RESTORE |
32347 | #define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 |
32348 | #define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL |
32349 | //RLC_PG_DELAY_2 |
32350 | #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 |
32351 | #define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 |
32352 | #define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE__SHIFT 0x10 |
32353 | #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL |
32354 | #define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L |
32355 | #define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE_MASK 0xFFFF0000L |
32356 | //RLC_GPU_CLOCK_COUNT_LSB |
32357 | #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 |
32358 | #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
32359 | //RLC_GPU_CLOCK_COUNT_MSB |
32360 | #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 |
32361 | #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
32362 | //RLC_CAPTURE_GPU_CLOCK_COUNT |
32363 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 |
32364 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 |
32365 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L |
32366 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL |
32367 | //RLC_UCODE_CNTL |
32368 | #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 |
32369 | #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL |
32370 | //RLC_GPM_THREAD_RESET |
32371 | #define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 |
32372 | #define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 |
32373 | #define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 |
32374 | #define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 |
32375 | #define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 |
32376 | #define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L |
32377 | #define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L |
32378 | #define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L |
32379 | #define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L |
32380 | #define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L |
32381 | //RLC_GPM_CP_DMA_COMPLETE_T0 |
32382 | #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0 |
32383 | #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1 |
32384 | #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L |
32385 | #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL |
32386 | //RLC_GPM_CP_DMA_COMPLETE_T1 |
32387 | #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0 |
32388 | #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1 |
32389 | #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L |
32390 | #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL |
32391 | //RLC_LB_CNTR_INIT_2 |
32392 | #define RLC_LB_CNTR_INIT_2__LB_CNTR_INIT__SHIFT 0x0 |
32393 | #define RLC_LB_CNTR_INIT_2__LB_CNTR_INIT_MASK 0xFFFFFFFFL |
32394 | //RLC_LB_CNTR_MAX_2 |
32395 | #define RLC_LB_CNTR_MAX_2__LB_CNTR_MAX__SHIFT 0x0 |
32396 | #define RLC_LB_CNTR_MAX_2__LB_CNTR_MAX_MASK 0xFFFFFFFFL |
32397 | //RLC_LB_CONFIG_5 |
32398 | #define RLC_LB_CONFIG_5__DATA__SHIFT 0x0 |
32399 | #define RLC_LB_CONFIG_5__DATA_MASK 0xFFFFFFFFL |
32400 | //RLC_GPM_TIMER_INT_4 |
32401 | #define RLC_GPM_TIMER_INT_4__TIMER__SHIFT 0x0 |
32402 | #define RLC_GPM_TIMER_INT_4__TIMER_MASK 0xFFFFFFFFL |
32403 | //RLC_CLK_COUNT_GFXCLK_LSB |
32404 | #define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT 0x0 |
32405 | #define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK 0xFFFFFFFFL |
32406 | //RLC_CLK_COUNT_GFXCLK_MSB |
32407 | #define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT 0x0 |
32408 | #define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK 0xFFFFFFFFL |
32409 | //RLC_CLK_COUNT_REFCLK_LSB |
32410 | #define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT 0x0 |
32411 | #define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK 0xFFFFFFFFL |
32412 | //RLC_CLK_COUNT_REFCLK_MSB |
32413 | #define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT 0x0 |
32414 | #define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK 0xFFFFFFFFL |
32415 | //RLC_CLK_COUNT_CTRL |
32416 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT 0x0 |
32417 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT 0x1 |
32418 | #define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT 0x2 |
32419 | #define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT 0x3 |
32420 | #define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT 0x4 |
32421 | #define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT 0x5 |
32422 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK 0x00000001L |
32423 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK 0x00000002L |
32424 | #define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK 0x00000004L |
32425 | #define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK 0x00000008L |
32426 | #define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK 0x00000010L |
32427 | #define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK 0x00000020L |
32428 | //RLC_CLK_COUNT_STAT |
32429 | #define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT 0x0 |
32430 | #define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT 0x1 |
32431 | #define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT 0x2 |
32432 | #define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT 0x3 |
32433 | #define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT 0x4 |
32434 | #define RLC_CLK_COUNT_STAT__RESERVED__SHIFT 0x5 |
32435 | #define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK 0x00000001L |
32436 | #define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK 0x00000002L |
32437 | #define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK 0x00000004L |
32438 | #define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK 0x00000008L |
32439 | #define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK 0x00000010L |
32440 | #define RLC_CLK_COUNT_STAT__RESERVED_MASK 0xFFFFFFE0L |
32441 | //RLC_RLCG_DOORBELL_CNTL |
32442 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 |
32443 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 |
32444 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 |
32445 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 |
32446 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 |
32447 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 |
32448 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L |
32449 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL |
32450 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L |
32451 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L |
32452 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L |
32453 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L |
32454 | //RLC_CGTT_MGCG_OVERRIDE |
32455 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0__SHIFT 0x0 |
32456 | #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1 |
32457 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2 |
32458 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3 |
32459 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4 |
32460 | #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5 |
32461 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6 |
32462 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7 |
32463 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT 0x8 |
32464 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_9__SHIFT 0x9 |
32465 | #define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY__SHIFT 0x10 |
32466 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17__SHIFT 0x11 |
32467 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_0_MASK 0x00000001L |
32468 | #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L |
32469 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L |
32470 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L |
32471 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L |
32472 | #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L |
32473 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L |
32474 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L |
32475 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK 0x00000100L |
32476 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_9_MASK 0x0000FE00L |
32477 | #define RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK 0x00010000L |
32478 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17_MASK 0xFFFE0000L |
32479 | //RLC_RLCG_DOORBELL_STAT |
32480 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 |
32481 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 |
32482 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 |
32483 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 |
32484 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L |
32485 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L |
32486 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L |
32487 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L |
32488 | //RLC_RLCG_DOORBELL_0_DATA_LO |
32489 | #define RLC_RLCG_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 |
32490 | #define RLC_RLCG_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL |
32491 | //RLC_RLCG_DOORBELL_0_DATA_HI |
32492 | #define RLC_RLCG_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 |
32493 | #define RLC_RLCG_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL |
32494 | //RLC_RLCG_DOORBELL_1_DATA_LO |
32495 | #define RLC_RLCG_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 |
32496 | #define RLC_RLCG_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL |
32497 | //RLC_RLCG_DOORBELL_1_DATA_HI |
32498 | #define RLC_RLCG_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 |
32499 | #define RLC_RLCG_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL |
32500 | //RLC_RLCG_DOORBELL_2_DATA_LO |
32501 | #define RLC_RLCG_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 |
32502 | #define RLC_RLCG_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL |
32503 | //RLC_RLCG_DOORBELL_2_DATA_HI |
32504 | #define RLC_RLCG_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 |
32505 | #define RLC_RLCG_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL |
32506 | //RLC_RLCG_DOORBELL_3_DATA_LO |
32507 | #define RLC_RLCG_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 |
32508 | #define RLC_RLCG_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL |
32509 | //RLC_RLCG_DOORBELL_3_DATA_HI |
32510 | #define RLC_RLCG_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 |
32511 | #define RLC_RLCG_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL |
32512 | //RLC_GPU_CLOCK_32_RES_SEL |
32513 | #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 |
32514 | #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 |
32515 | #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL |
32516 | #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L |
32517 | //RLC_GPU_CLOCK_32 |
32518 | #define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 |
32519 | #define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL |
32520 | //RLC_PG_CNTL |
32521 | #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 |
32522 | #define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 |
32523 | #define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE__SHIFT 0x2 |
32524 | #define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE__SHIFT 0x3 |
32525 | #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 |
32526 | #define RLC_PG_CNTL__RESERVED__SHIFT 0x5 |
32527 | #define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe |
32528 | #define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf |
32529 | #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 |
32530 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 |
32531 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 |
32532 | #define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13 |
32533 | #define RLC_PG_CNTL__RESERVED1__SHIFT 0x14 |
32534 | #define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT 0x15 |
32535 | #define RLC_PG_CNTL__RESERVED2__SHIFT 0x16 |
32536 | #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L |
32537 | #define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L |
32538 | #define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE_MASK 0x00000004L |
32539 | #define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE_MASK 0x00000008L |
32540 | #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L |
32541 | #define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L |
32542 | #define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L |
32543 | #define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L |
32544 | #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L |
32545 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L |
32546 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L |
32547 | #define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x00080000L |
32548 | #define RLC_PG_CNTL__RESERVED1_MASK 0x00100000L |
32549 | #define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK 0x00200000L |
32550 | #define RLC_PG_CNTL__RESERVED2_MASK 0x00C00000L |
32551 | //RLC_GPM_THREAD_PRIORITY |
32552 | #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 |
32553 | #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 |
32554 | #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 |
32555 | #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 |
32556 | #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL |
32557 | #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L |
32558 | #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L |
32559 | #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L |
32560 | //RLC_GPM_THREAD_ENABLE |
32561 | #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 |
32562 | #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 |
32563 | #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 |
32564 | #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 |
32565 | #define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 |
32566 | #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L |
32567 | #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L |
32568 | #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L |
32569 | #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L |
32570 | #define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L |
32571 | //RLC_RLCG_DOORBELL_RANGE |
32572 | #define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 |
32573 | #define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 |
32574 | #define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 |
32575 | #define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 |
32576 | #define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L |
32577 | #define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL |
32578 | #define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L |
32579 | #define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L |
32580 | //RLC_CGCG_CGLS_CTRL |
32581 | #define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 |
32582 | #define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 |
32583 | #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 |
32584 | #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 |
32585 | #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b |
32586 | #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c |
32587 | #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d |
32588 | #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f |
32589 | #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L |
32590 | #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L |
32591 | #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL |
32592 | #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L |
32593 | #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L |
32594 | #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L |
32595 | #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L |
32596 | #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L |
32597 | //RLC_CGCG_RAMP_CTRL |
32598 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 |
32599 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 |
32600 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 |
32601 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc |
32602 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 |
32603 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c |
32604 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL |
32605 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L |
32606 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L |
32607 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L |
32608 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L |
32609 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L |
32610 | //RLC_DYN_PG_STATUS |
32611 | #define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT 0x0 |
32612 | #define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK_MASK 0xFFFFFFFFL |
32613 | //RLC_DYN_PG_REQUEST |
32614 | #define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK__SHIFT 0x0 |
32615 | #define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK_MASK 0xFFFFFFFFL |
32616 | //RLC_PG_DELAY |
32617 | #define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 |
32618 | #define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 |
32619 | #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 |
32620 | #define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 |
32621 | #define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL |
32622 | #define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L |
32623 | #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L |
32624 | #define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L |
32625 | //RLC_WGP_STATUS |
32626 | #define RLC_WGP_STATUS__WORK_PENDING__SHIFT 0x0 |
32627 | #define RLC_WGP_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL |
32628 | //RLC_LB_INIT_WGP_MASK |
32629 | #define RLC_LB_INIT_WGP_MASK__INIT_WGP_MASK__SHIFT 0x0 |
32630 | #define RLC_LB_INIT_WGP_MASK__INIT_WGP_MASK_MASK 0xFFFFFFFFL |
32631 | //RLC_LB_ALWAYS_ACTIVE_WGP_MASK |
32632 | #define RLC_LB_ALWAYS_ACTIVE_WGP_MASK__ALWAYS_ACTIVE_WGP_MASK__SHIFT 0x0 |
32633 | #define RLC_LB_ALWAYS_ACTIVE_WGP_MASK__ALWAYS_ACTIVE_WGP_MASK_MASK 0xFFFFFFFFL |
32634 | //RLC_LB_PARAMS |
32635 | #define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 |
32636 | #define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 |
32637 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 |
32638 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 |
32639 | #define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L |
32640 | #define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL |
32641 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L |
32642 | #define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L |
32643 | //RLC_LB_DELAY |
32644 | #define RLC_LB_DELAY__WGP_IDLE_DELAY__SHIFT 0x0 |
32645 | #define RLC_LB_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 |
32646 | #define RLC_LB_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 |
32647 | #define RLC_LB_DELAY__SPARE__SHIFT 0x18 |
32648 | #define RLC_LB_DELAY__WGP_IDLE_DELAY_MASK 0x000000FFL |
32649 | #define RLC_LB_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L |
32650 | #define RLC_LB_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L |
32651 | #define RLC_LB_DELAY__SPARE_MASK 0xFF000000L |
32652 | //RLC_PG_ALWAYS_ON_WGP_MASK |
32653 | #define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK__SHIFT 0x0 |
32654 | #define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK 0xFFFFFFFFL |
32655 | //RLC_MAX_PG_WGP |
32656 | #define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP__SHIFT 0x0 |
32657 | #define RLC_MAX_PG_WGP__SPARE__SHIFT 0x8 |
32658 | #define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP_MASK 0x000000FFL |
32659 | #define RLC_MAX_PG_WGP__SPARE_MASK 0xFFFFFF00L |
32660 | //RLC_AUTO_PG_CTRL |
32661 | #define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 |
32662 | #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 |
32663 | #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 |
32664 | #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 |
32665 | #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 |
32666 | #define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L |
32667 | #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L |
32668 | #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L |
32669 | #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L |
32670 | #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L |
32671 | //RLC_SMU_GRBM_REG_SAVE_CTRL |
32672 | #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 |
32673 | #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 |
32674 | #define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L |
32675 | #define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xFFFFFFFEL |
32676 | //RLC_SERDES_RD_INDEX |
32677 | #define RLC_SERDES_RD_INDEX__DATA_REG_ID__SHIFT 0x0 |
32678 | #define RLC_SERDES_RD_INDEX__SPARE__SHIFT 0x2 |
32679 | #define RLC_SERDES_RD_INDEX__DATA_REG_ID_MASK 0x00000003L |
32680 | #define RLC_SERDES_RD_INDEX__SPARE_MASK 0xFFFFFFFCL |
32681 | //RLC_SERDES_RD_DATA_0 |
32682 | #define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 |
32683 | #define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL |
32684 | //RLC_SERDES_RD_DATA_1 |
32685 | #define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 |
32686 | #define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL |
32687 | //RLC_SERDES_RD_DATA_2 |
32688 | #define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 |
32689 | #define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL |
32690 | //RLC_SERDES_RD_DATA_3 |
32691 | #define RLC_SERDES_RD_DATA_3__DATA__SHIFT 0x0 |
32692 | #define RLC_SERDES_RD_DATA_3__DATA_MASK 0xFFFFFFFFL |
32693 | //RLC_SERDES_MASK |
32694 | #define RLC_SERDES_MASK__GC_CENTER_HUB_0__SHIFT 0x0 |
32695 | #define RLC_SERDES_MASK__GC_CENTER_HUB_1__SHIFT 0x1 |
32696 | #define RLC_SERDES_MASK__RESERVED__SHIFT 0x2 |
32697 | #define RLC_SERDES_MASK__GC_SE_0__SHIFT 0x10 |
32698 | #define RLC_SERDES_MASK__GC_SE_1__SHIFT 0x11 |
32699 | #define RLC_SERDES_MASK__GC_SE_2__SHIFT 0x12 |
32700 | #define RLC_SERDES_MASK__GC_SE_3__SHIFT 0x13 |
32701 | #define RLC_SERDES_MASK__RESERVED_1__SHIFT 0x14 |
32702 | #define RLC_SERDES_MASK__GC_CENTER_HUB_0_MASK 0x00000001L |
32703 | #define RLC_SERDES_MASK__GC_CENTER_HUB_1_MASK 0x00000002L |
32704 | #define RLC_SERDES_MASK__RESERVED_MASK 0x0000FFFCL |
32705 | #define RLC_SERDES_MASK__GC_SE_0_MASK 0x00010000L |
32706 | #define RLC_SERDES_MASK__GC_SE_1_MASK 0x00020000L |
32707 | #define RLC_SERDES_MASK__GC_SE_2_MASK 0x00040000L |
32708 | #define RLC_SERDES_MASK__GC_SE_3_MASK 0x00080000L |
32709 | #define RLC_SERDES_MASK__RESERVED_1_MASK 0xFFF00000L |
32710 | //RLC_SERDES_CTRL |
32711 | #define RLC_SERDES_CTRL__BPM_BROADCAST__SHIFT 0x0 |
32712 | #define RLC_SERDES_CTRL__BPM_REG_WRITE__SHIFT 0x1 |
32713 | #define RLC_SERDES_CTRL__BPM_LONG_CMD__SHIFT 0x2 |
32714 | #define RLC_SERDES_CTRL__BPM_ADDR__SHIFT 0x3 |
32715 | #define RLC_SERDES_CTRL__REG_ADDR__SHIFT 0x10 |
32716 | #define RLC_SERDES_CTRL__BPM_BROADCAST_MASK 0x000001L |
32717 | #define RLC_SERDES_CTRL__BPM_REG_WRITE_MASK 0x000002L |
32718 | #define RLC_SERDES_CTRL__BPM_LONG_CMD_MASK 0x000004L |
32719 | #define RLC_SERDES_CTRL__BPM_ADDR_MASK 0x00FFF8L |
32720 | #define RLC_SERDES_CTRL__REG_ADDR_MASK 0xFF0000L |
32721 | //RLC_SERDES_DATA |
32722 | #define RLC_SERDES_DATA__DATA__SHIFT 0x0 |
32723 | #define RLC_SERDES_DATA__DATA_MASK 0xFFFFFFFFL |
32724 | //RLC_SERDES_BUSY |
32725 | #define RLC_SERDES_BUSY__GC_CENTER_HUB_0__SHIFT 0x0 |
32726 | #define RLC_SERDES_BUSY__GC_CENTER_HUB_1__SHIFT 0x1 |
32727 | #define RLC_SERDES_BUSY__RESERVED__SHIFT 0x2 |
32728 | #define RLC_SERDES_BUSY__GC_SE_0__SHIFT 0x10 |
32729 | #define RLC_SERDES_BUSY__GC_SE_1__SHIFT 0x11 |
32730 | #define RLC_SERDES_BUSY__GC_SE_2__SHIFT 0x12 |
32731 | #define RLC_SERDES_BUSY__GC_SE_3__SHIFT 0x13 |
32732 | #define RLC_SERDES_BUSY__RESERVED_29_20__SHIFT 0x14 |
32733 | #define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY__SHIFT 0x1e |
32734 | #define RLC_SERDES_BUSY__RD_PENDING__SHIFT 0x1f |
32735 | #define RLC_SERDES_BUSY__GC_CENTER_HUB_0_MASK 0x00000001L |
32736 | #define RLC_SERDES_BUSY__GC_CENTER_HUB_1_MASK 0x00000002L |
32737 | #define RLC_SERDES_BUSY__RESERVED_MASK 0x0000FFFCL |
32738 | #define RLC_SERDES_BUSY__GC_SE_0_MASK 0x00010000L |
32739 | #define RLC_SERDES_BUSY__GC_SE_1_MASK 0x00020000L |
32740 | #define RLC_SERDES_BUSY__GC_SE_2_MASK 0x00040000L |
32741 | #define RLC_SERDES_BUSY__GC_SE_3_MASK 0x00080000L |
32742 | #define RLC_SERDES_BUSY__RESERVED_29_20_MASK 0x3FF00000L |
32743 | #define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY_MASK 0x40000000L |
32744 | #define RLC_SERDES_BUSY__RD_PENDING_MASK 0x80000000L |
32745 | //RLC_GPM_GENERAL_0 |
32746 | #define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 |
32747 | #define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL |
32748 | //RLC_GPM_GENERAL_1 |
32749 | #define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 |
32750 | #define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL |
32751 | //RLC_GPM_GENERAL_2 |
32752 | #define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 |
32753 | #define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL |
32754 | //RLC_GPM_GENERAL_3 |
32755 | #define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 |
32756 | #define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL |
32757 | //RLC_GPM_GENERAL_4 |
32758 | #define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 |
32759 | #define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL |
32760 | //RLC_GPM_GENERAL_5 |
32761 | #define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 |
32762 | #define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL |
32763 | //RLC_GPM_GENERAL_6 |
32764 | #define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 |
32765 | #define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL |
32766 | //RLC_GPM_GENERAL_7 |
32767 | #define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 |
32768 | #define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL |
32769 | //RLC_STATIC_PG_STATUS |
32770 | #define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT 0x0 |
32771 | #define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK_MASK 0xFFFFFFFFL |
32772 | //RLC_SPM_INT_INFO_1 |
32773 | #define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 |
32774 | #define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL |
32775 | //RLC_SPM_INT_INFO_2 |
32776 | #define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 |
32777 | #define RLC_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 |
32778 | #define RLC_SPM_INT_INFO_2__RESERVED__SHIFT 0x18 |
32779 | #define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL |
32780 | #define RLC_SPM_INT_INFO_2__INTERRUPT_ID_MASK 0x00FF0000L |
32781 | #define RLC_SPM_INT_INFO_2__RESERVED_MASK 0xFF000000L |
32782 | //RLC_SPM_MC_CNTL |
32783 | #define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0 |
32784 | #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4 |
32785 | #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x6 |
32786 | #define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x7 |
32787 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x8 |
32788 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x9 |
32789 | #define RLC_SPM_MC_CNTL__RLC_SPM_BC__SHIFT 0xc |
32790 | #define RLC_SPM_MC_CNTL__RLC_SPM_RO__SHIFT 0xd |
32791 | #define RLC_SPM_MC_CNTL__RLC_SPM_VOL__SHIFT 0xe |
32792 | #define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL__SHIFT 0xf |
32793 | #define RLC_SPM_MC_CNTL__RESERVED_3__SHIFT 0x10 |
32794 | #define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC__SHIFT 0x12 |
32795 | #define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_OVER__SHIFT 0x13 |
32796 | #define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0x14 |
32797 | #define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL |
32798 | #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000030L |
32799 | #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000040L |
32800 | #define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000080L |
32801 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000100L |
32802 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000E00L |
32803 | #define RLC_SPM_MC_CNTL__RLC_SPM_BC_MASK 0x00001000L |
32804 | #define RLC_SPM_MC_CNTL__RLC_SPM_RO_MASK 0x00002000L |
32805 | #define RLC_SPM_MC_CNTL__RLC_SPM_VOL_MASK 0x00004000L |
32806 | #define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL_MASK 0x00008000L |
32807 | #define RLC_SPM_MC_CNTL__RESERVED_3_MASK 0x00030000L |
32808 | #define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_MASK 0x00040000L |
32809 | #define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_OVER_MASK 0x00080000L |
32810 | #define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFF00000L |
32811 | //RLC_SPM_INT_CNTL |
32812 | #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 |
32813 | #define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 |
32814 | #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L |
32815 | #define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL |
32816 | //RLC_SPM_INT_STATUS |
32817 | #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 |
32818 | #define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 |
32819 | #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L |
32820 | #define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL |
32821 | //RLC_SMU_MESSAGE |
32822 | #define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 |
32823 | #define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL |
32824 | //RLC_GPM_LOG_SIZE |
32825 | #define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 |
32826 | #define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL |
32827 | //RLC_PG_DELAY_3 |
32828 | #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 |
32829 | #define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 |
32830 | #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL |
32831 | #define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L |
32832 | //RLC_GPR_REG1 |
32833 | #define RLC_GPR_REG1__DATA__SHIFT 0x0 |
32834 | #define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL |
32835 | //RLC_GPR_REG2 |
32836 | #define RLC_GPR_REG2__DATA__SHIFT 0x0 |
32837 | #define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL |
32838 | //RLC_GPM_LOG_CONT |
32839 | #define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 |
32840 | #define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL |
32841 | //RLC_GPM_INT_DISABLE_TH0 |
32842 | #define RLC_GPM_INT_DISABLE_TH0__DISABLE_INT__SHIFT 0x0 |
32843 | #define RLC_GPM_INT_DISABLE_TH0__DISABLE_INT_MASK 0xFFFFFFFFL |
32844 | //RLC_GPM_LEGACY_INT_DISABLE |
32845 | #define RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED__SHIFT 0x0 |
32846 | #define RLC_GPM_LEGACY_INT_DISABLE__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT 0x1 |
32847 | #define RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED__SHIFT 0x2 |
32848 | #define RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED_MASK 0x00000001L |
32849 | #define RLC_GPM_LEGACY_INT_DISABLE__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK 0x00000002L |
32850 | #define RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED_MASK 0x00000004L |
32851 | //RLC_GPM_INT_FORCE_TH0 |
32852 | #define RLC_GPM_INT_FORCE_TH0__FORCE_INT__SHIFT 0x0 |
32853 | #define RLC_GPM_INT_FORCE_TH0__FORCE_INT_MASK 0xFFFFFFFFL |
32854 | //RLC_SRM_CNTL |
32855 | #define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 |
32856 | #define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 |
32857 | #define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 |
32858 | #define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L |
32859 | #define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L |
32860 | #define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL |
32861 | //RLC_SRM_GPM_COMMAND |
32862 | #define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 |
32863 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 |
32864 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 |
32865 | #define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 |
32866 | #define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11 |
32867 | #define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d |
32868 | #define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f |
32869 | #define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L |
32870 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L |
32871 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL |
32872 | #define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0001FFE0L |
32873 | #define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L |
32874 | #define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000L |
32875 | #define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L |
32876 | //RLC_SRM_GPM_COMMAND_STATUS |
32877 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 |
32878 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 |
32879 | #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 |
32880 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L |
32881 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L |
32882 | #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL |
32883 | //RLC_SRM_RLCV_COMMAND |
32884 | #define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0 |
32885 | #define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1 |
32886 | #define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4 |
32887 | #define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10 |
32888 | #define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c |
32889 | #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f |
32890 | #define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L |
32891 | #define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL |
32892 | #define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L |
32893 | #define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L |
32894 | #define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L |
32895 | #define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L |
32896 | //RLC_SRM_RLCV_COMMAND_STATUS |
32897 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 |
32898 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 |
32899 | #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2 |
32900 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L |
32901 | #define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L |
32902 | #define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL |
32903 | //RLC_SRM_INDEX_CNTL_ADDR_0 |
32904 | #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 |
32905 | #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10 |
32906 | #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL |
32907 | #define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L |
32908 | //RLC_SRM_INDEX_CNTL_ADDR_1 |
32909 | #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 |
32910 | #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10 |
32911 | #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL |
32912 | #define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L |
32913 | //RLC_SRM_INDEX_CNTL_ADDR_2 |
32914 | #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 |
32915 | #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10 |
32916 | #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL |
32917 | #define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L |
32918 | //RLC_SRM_INDEX_CNTL_ADDR_3 |
32919 | #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 |
32920 | #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10 |
32921 | #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL |
32922 | #define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L |
32923 | //RLC_SRM_INDEX_CNTL_ADDR_4 |
32924 | #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 |
32925 | #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10 |
32926 | #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL |
32927 | #define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L |
32928 | //RLC_SRM_INDEX_CNTL_ADDR_5 |
32929 | #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 |
32930 | #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10 |
32931 | #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL |
32932 | #define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L |
32933 | //RLC_SRM_INDEX_CNTL_ADDR_6 |
32934 | #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 |
32935 | #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10 |
32936 | #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL |
32937 | #define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L |
32938 | //RLC_SRM_INDEX_CNTL_ADDR_7 |
32939 | #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 |
32940 | #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10 |
32941 | #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL |
32942 | #define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L |
32943 | //RLC_SRM_INDEX_CNTL_DATA_0 |
32944 | #define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 |
32945 | #define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL |
32946 | //RLC_SRM_INDEX_CNTL_DATA_1 |
32947 | #define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 |
32948 | #define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL |
32949 | //RLC_SRM_INDEX_CNTL_DATA_2 |
32950 | #define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 |
32951 | #define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL |
32952 | //RLC_SRM_INDEX_CNTL_DATA_3 |
32953 | #define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 |
32954 | #define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL |
32955 | //RLC_SRM_INDEX_CNTL_DATA_4 |
32956 | #define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 |
32957 | #define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL |
32958 | //RLC_SRM_INDEX_CNTL_DATA_5 |
32959 | #define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 |
32960 | #define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL |
32961 | //RLC_SRM_INDEX_CNTL_DATA_6 |
32962 | #define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 |
32963 | #define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL |
32964 | //RLC_SRM_INDEX_CNTL_DATA_7 |
32965 | #define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 |
32966 | #define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL |
32967 | //RLC_SRM_STAT |
32968 | #define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0 |
32969 | #define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1 |
32970 | #define RLC_SRM_STAT__RESERVED__SHIFT 0x2 |
32971 | #define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L |
32972 | #define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L |
32973 | #define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL |
32974 | //RLC_SRM_GPM_ABORT |
32975 | #define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 |
32976 | #define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 |
32977 | #define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L |
32978 | #define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL |
32979 | //RLC_SPARE_INT_2 |
32980 | #define RLC_SPARE_INT_2__DATA__SHIFT 0x0 |
32981 | #define RLC_SPARE_INT_2__PROCESSING__SHIFT 0x1e |
32982 | #define RLC_SPARE_INT_2__COMPLETE__SHIFT 0x1f |
32983 | #define RLC_SPARE_INT_2__DATA_MASK 0x3FFFFFFFL |
32984 | #define RLC_SPARE_INT_2__PROCESSING_MASK 0x40000000L |
32985 | #define RLC_SPARE_INT_2__COMPLETE_MASK 0x80000000L |
32986 | //RLC_RLCV_SPARE_INT_1 |
32987 | #define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT 0x0 |
32988 | #define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT 0x1 |
32989 | #define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK 0x00000001L |
32990 | #define RLC_RLCV_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL |
32991 | //RLC_PACE_SPARE_INT_1 |
32992 | #define RLC_PACE_SPARE_INT_1__INTERRUPT__SHIFT 0x0 |
32993 | #define RLC_PACE_SPARE_INT_1__RESERVED__SHIFT 0x1 |
32994 | #define RLC_PACE_SPARE_INT_1__INTERRUPT_MASK 0x00000001L |
32995 | #define RLC_PACE_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL |
32996 | //RLC_SAFE_MODE |
32997 | #define RLC_SAFE_MODE__CMD__SHIFT 0x0 |
32998 | #define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 |
32999 | #define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 |
33000 | #define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 |
33001 | #define RLC_SAFE_MODE__RESERVED__SHIFT 0xc |
33002 | #define RLC_SAFE_MODE__CMD_MASK 0x00000001L |
33003 | #define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL |
33004 | #define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L |
33005 | #define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L |
33006 | #define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L |
33007 | //RLC_CP_SCHEDULERS |
33008 | #define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 |
33009 | #define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 |
33010 | #define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10 |
33011 | #define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18 |
33012 | #define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL |
33013 | #define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L |
33014 | #define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L |
33015 | #define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L |
33016 | //RLC_CSIB_ADDR_LO |
33017 | #define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 |
33018 | #define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL |
33019 | //RLC_CSIB_ADDR_HI |
33020 | #define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 |
33021 | #define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL |
33022 | //RLC_CSIB_LENGTH |
33023 | #define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 |
33024 | #define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL |
33025 | //RLC_SPARE_INT_0 |
33026 | #define RLC_SPARE_INT_0__DATA__SHIFT 0x0 |
33027 | #define RLC_SPARE_INT_0__PROCESSING__SHIFT 0x1e |
33028 | #define RLC_SPARE_INT_0__COMPLETE__SHIFT 0x1f |
33029 | #define RLC_SPARE_INT_0__DATA_MASK 0x3FFFFFFFL |
33030 | #define RLC_SPARE_INT_0__PROCESSING_MASK 0x40000000L |
33031 | #define RLC_SPARE_INT_0__COMPLETE_MASK 0x80000000L |
33032 | //RLC_CP_EOF_INT_CNT |
33033 | #define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0 |
33034 | #define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL |
33035 | //RLC_CP_EOF_INT |
33036 | #define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0 |
33037 | #define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1 |
33038 | #define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L |
33039 | #define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL |
33040 | //RLC_SMU_COMMAND |
33041 | #define RLC_SMU_COMMAND__CMD__SHIFT 0x0 |
33042 | #define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL |
33043 | //RLC_SMU_ARGUMENT_1 |
33044 | #define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0 |
33045 | #define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL |
33046 | //RLC_SMU_ARGUMENT_2 |
33047 | #define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0 |
33048 | #define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL |
33049 | //RLC_GPM_GENERAL_8 |
33050 | #define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 |
33051 | #define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL |
33052 | //RLC_GPM_GENERAL_9 |
33053 | #define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 |
33054 | #define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL |
33055 | //RLC_GPM_GENERAL_10 |
33056 | #define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 |
33057 | #define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL |
33058 | //RLC_GPM_GENERAL_11 |
33059 | #define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 |
33060 | #define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL |
33061 | //RLC_GPM_GENERAL_12 |
33062 | #define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 |
33063 | #define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL |
33064 | //RLC_GPM_UTCL1_CNTL_0 |
33065 | #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
33066 | #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18 |
33067 | #define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19 |
33068 | #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a |
33069 | #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b |
33070 | #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c |
33071 | #define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e |
33072 | #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
33073 | #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L |
33074 | #define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L |
33075 | #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L |
33076 | #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L |
33077 | #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L |
33078 | #define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L |
33079 | //RLC_GPM_UTCL1_CNTL_1 |
33080 | #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
33081 | #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18 |
33082 | #define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19 |
33083 | #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a |
33084 | #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b |
33085 | #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c |
33086 | #define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e |
33087 | #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
33088 | #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L |
33089 | #define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L |
33090 | #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L |
33091 | #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L |
33092 | #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L |
33093 | #define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L |
33094 | //RLC_GPM_UTCL1_CNTL_2 |
33095 | #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
33096 | #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18 |
33097 | #define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19 |
33098 | #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a |
33099 | #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b |
33100 | #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c |
33101 | #define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e |
33102 | #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
33103 | #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L |
33104 | #define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L |
33105 | #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L |
33106 | #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L |
33107 | #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L |
33108 | #define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L |
33109 | //RLC_SPM_UTCL1_CNTL |
33110 | #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
33111 | #define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
33112 | #define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
33113 | #define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
33114 | #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
33115 | #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
33116 | #define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e |
33117 | #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
33118 | #define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
33119 | #define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
33120 | #define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
33121 | #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
33122 | #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
33123 | #define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L |
33124 | //RLC_UTCL1_STATUS_2 |
33125 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0 |
33126 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1 |
33127 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2 |
33128 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3 |
33129 | #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4 |
33130 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5 |
33131 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6 |
33132 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7 |
33133 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8 |
33134 | #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9 |
33135 | #define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa |
33136 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L |
33137 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L |
33138 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L |
33139 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L |
33140 | #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L |
33141 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L |
33142 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L |
33143 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L |
33144 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L |
33145 | #define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L |
33146 | #define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L |
33147 | //RLC_LB_CONFIG_2 |
33148 | #define RLC_LB_CONFIG_2__DATA__SHIFT 0x0 |
33149 | #define RLC_LB_CONFIG_2__DATA_MASK 0xFFFFFFFFL |
33150 | //RLC_LB_CONFIG_3 |
33151 | #define RLC_LB_CONFIG_3__DATA__SHIFT 0x0 |
33152 | #define RLC_LB_CONFIG_3__DATA_MASK 0xFFFFFFFFL |
33153 | //RLC_LB_CONFIG_4 |
33154 | #define RLC_LB_CONFIG_4__DATA__SHIFT 0x0 |
33155 | #define RLC_LB_CONFIG_4__DATA_MASK 0xFFFFFFFFL |
33156 | //RLC_SPM_UTCL1_ERROR_1 |
33157 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 |
33158 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
33159 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
33160 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L |
33161 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
33162 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
33163 | //RLC_SPM_UTCL1_ERROR_2 |
33164 | #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
33165 | #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
33166 | //RLC_GPM_UTCL1_TH0_ERROR_1 |
33167 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0 |
33168 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
33169 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
33170 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L |
33171 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
33172 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
33173 | //RLC_LB_CONFIG_1 |
33174 | #define RLC_LB_CONFIG_1__DATA__SHIFT 0x0 |
33175 | #define RLC_LB_CONFIG_1__DATA_MASK 0xFFFFFFFFL |
33176 | //RLC_GPM_UTCL1_TH0_ERROR_2 |
33177 | #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
33178 | #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
33179 | //RLC_GPM_UTCL1_TH1_ERROR_1 |
33180 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0 |
33181 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
33182 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
33183 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L |
33184 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
33185 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
33186 | //RLC_GPM_UTCL1_TH1_ERROR_2 |
33187 | #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
33188 | #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
33189 | //RLC_GPM_UTCL1_TH2_ERROR_1 |
33190 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0 |
33191 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
33192 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
33193 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L |
33194 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
33195 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
33196 | //RLC_GPM_UTCL1_TH2_ERROR_2 |
33197 | #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
33198 | #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
33199 | //RLC_CGCG_CGLS_CTRL_3D |
33200 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0 |
33201 | #define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1 |
33202 | #define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 |
33203 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 |
33204 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b |
33205 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c |
33206 | #define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d |
33207 | #define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f |
33208 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L |
33209 | #define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L |
33210 | #define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL |
33211 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L |
33212 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L |
33213 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L |
33214 | #define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L |
33215 | #define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L |
33216 | //RLC_CGCG_RAMP_CTRL_3D |
33217 | #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0 |
33218 | #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4 |
33219 | #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8 |
33220 | #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc |
33221 | #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10 |
33222 | #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c |
33223 | #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL |
33224 | #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L |
33225 | #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L |
33226 | #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L |
33227 | #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L |
33228 | #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L |
33229 | //RLC_SEMAPHORE_0 |
33230 | #define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 |
33231 | #define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5 |
33232 | #define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL |
33233 | #define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L |
33234 | //RLC_SEMAPHORE_1 |
33235 | #define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 |
33236 | #define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5 |
33237 | #define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL |
33238 | #define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L |
33239 | //RLC_PACE_INT_STAT |
33240 | #define RLC_PACE_INT_STAT__STATUS__SHIFT 0x0 |
33241 | #define RLC_PACE_INT_STAT__STATUS_MASK 0xFFFFFFFFL |
33242 | //RLC_PREWALKER_UTCL1_CNTL |
33243 | #define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
33244 | #define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
33245 | #define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
33246 | #define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
33247 | #define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
33248 | #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
33249 | #define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e |
33250 | #define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
33251 | #define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
33252 | #define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
33253 | #define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
33254 | #define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
33255 | #define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
33256 | #define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L |
33257 | //RLC_PREWALKER_UTCL1_TRIG |
33258 | #define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0 |
33259 | #define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1 |
33260 | #define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5 |
33261 | #define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6 |
33262 | #define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7 |
33263 | #define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8 |
33264 | #define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9 |
33265 | #define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f |
33266 | #define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L |
33267 | #define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL |
33268 | #define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L |
33269 | #define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L |
33270 | #define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L |
33271 | #define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L |
33272 | #define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L |
33273 | #define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L |
33274 | //RLC_PREWALKER_UTCL1_ADDR_LSB |
33275 | #define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0 |
33276 | #define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL |
33277 | //RLC_PREWALKER_UTCL1_ADDR_MSB |
33278 | #define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0 |
33279 | #define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL |
33280 | //RLC_PREWALKER_UTCL1_SIZE_LSB |
33281 | #define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0 |
33282 | #define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL |
33283 | //RLC_PREWALKER_UTCL1_SIZE_MSB |
33284 | #define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0 |
33285 | #define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L |
33286 | //RLC_UTCL1_STATUS |
33287 | #define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
33288 | #define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
33289 | #define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
33290 | #define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3 |
33291 | #define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
33292 | #define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe |
33293 | #define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
33294 | #define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16 |
33295 | #define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
33296 | #define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e |
33297 | #define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
33298 | #define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
33299 | #define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
33300 | #define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L |
33301 | #define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
33302 | #define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L |
33303 | #define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
33304 | #define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L |
33305 | #define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
33306 | #define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L |
33307 | //RLC_R2I_CNTL_0 |
33308 | #define RLC_R2I_CNTL_0__Data__SHIFT 0x0 |
33309 | #define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL |
33310 | //RLC_R2I_CNTL_1 |
33311 | #define RLC_R2I_CNTL_1__Data__SHIFT 0x0 |
33312 | #define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL |
33313 | //RLC_R2I_CNTL_2 |
33314 | #define RLC_R2I_CNTL_2__Data__SHIFT 0x0 |
33315 | #define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL |
33316 | //RLC_R2I_CNTL_3 |
33317 | #define RLC_R2I_CNTL_3__Data__SHIFT 0x0 |
33318 | #define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL |
33319 | //RLC_LB_WGP_STAT |
33320 | #define RLC_LB_WGP_STAT__MAX_WGP__SHIFT 0x0 |
33321 | #define RLC_LB_WGP_STAT__ON_WGP__SHIFT 0x10 |
33322 | #define RLC_LB_WGP_STAT__MAX_WGP_MASK 0x0000FFFFL |
33323 | #define RLC_LB_WGP_STAT__ON_WGP_MASK 0xFFFF0000L |
33324 | //RLC_GPM_INT_STAT_TH0 |
33325 | #define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT 0x0 |
33326 | #define RLC_GPM_INT_STAT_TH0__STATUS_MASK 0xFFFFFFFFL |
33327 | //RLC_GPM_GENERAL_13 |
33328 | #define RLC_GPM_GENERAL_13__DATA__SHIFT 0x0 |
33329 | #define RLC_GPM_GENERAL_13__DATA_MASK 0xFFFFFFFFL |
33330 | //RLC_GPM_GENERAL_14 |
33331 | #define RLC_GPM_GENERAL_14__DATA__SHIFT 0x0 |
33332 | #define RLC_GPM_GENERAL_14__DATA_MASK 0xFFFFFFFFL |
33333 | //RLC_GPM_GENERAL_15 |
33334 | #define RLC_GPM_GENERAL_15__DATA__SHIFT 0x0 |
33335 | #define RLC_GPM_GENERAL_15__DATA_MASK 0xFFFFFFFFL |
33336 | //RLC_SPARE_INT_1 |
33337 | #define RLC_SPARE_INT_1__DATA__SHIFT 0x0 |
33338 | #define RLC_SPARE_INT_1__PROCESSING__SHIFT 0x1e |
33339 | #define RLC_SPARE_INT_1__COMPLETE__SHIFT 0x1f |
33340 | #define RLC_SPARE_INT_1__DATA_MASK 0x3FFFFFFFL |
33341 | #define RLC_SPARE_INT_1__PROCESSING_MASK 0x40000000L |
33342 | #define RLC_SPARE_INT_1__COMPLETE_MASK 0x80000000L |
33343 | //RLC_SEMAPHORE_2 |
33344 | #define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 |
33345 | #define RLC_SEMAPHORE_2__RESERVED__SHIFT 0x5 |
33346 | #define RLC_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL |
33347 | #define RLC_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L |
33348 | //RLC_SEMAPHORE_3 |
33349 | #define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 |
33350 | #define RLC_SEMAPHORE_3__RESERVED__SHIFT 0x5 |
33351 | #define RLC_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL |
33352 | #define RLC_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L |
33353 | //RLC_SMU_ARGUMENT_3 |
33354 | #define RLC_SMU_ARGUMENT_3__ARG__SHIFT 0x0 |
33355 | #define RLC_SMU_ARGUMENT_3__ARG_MASK 0xFFFFFFFFL |
33356 | //RLC_SMU_ARGUMENT_4 |
33357 | #define RLC_SMU_ARGUMENT_4__ARG__SHIFT 0x0 |
33358 | #define RLC_SMU_ARGUMENT_4__ARG_MASK 0xFFFFFFFFL |
33359 | //RLC_GPU_CLOCK_COUNT_LSB_1 |
33360 | #define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT 0x0 |
33361 | #define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
33362 | //RLC_GPU_CLOCK_COUNT_MSB_1 |
33363 | #define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT 0x0 |
33364 | #define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
33365 | //RLC_CAPTURE_GPU_CLOCK_COUNT_1 |
33366 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT 0x0 |
33367 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT 0x1 |
33368 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK 0x00000001L |
33369 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK 0xFFFFFFFEL |
33370 | //RLC_GPU_CLOCK_COUNT_LSB_2 |
33371 | #define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT 0x0 |
33372 | #define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
33373 | //RLC_GPU_CLOCK_COUNT_MSB_2 |
33374 | #define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT 0x0 |
33375 | #define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
33376 | //RLC_PACE_INT_DISABLE |
33377 | #define RLC_PACE_INT_DISABLE__DISABLE_INT__SHIFT 0x0 |
33378 | #define RLC_PACE_INT_DISABLE__DISABLE_INT_MASK 0xFFFFFFFFL |
33379 | //RLC_CAPTURE_GPU_CLOCK_COUNT_2 |
33380 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT 0x0 |
33381 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT 0x1 |
33382 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK 0x00000001L |
33383 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK 0xFFFFFFFEL |
33384 | //RLC_RLCV_DOORBELL_RANGE |
33385 | #define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 |
33386 | #define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 |
33387 | #define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 |
33388 | #define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 |
33389 | #define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L |
33390 | #define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL |
33391 | #define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L |
33392 | #define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L |
33393 | //RLC_RLCV_DOORBELL_CNTL |
33394 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 |
33395 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 |
33396 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 |
33397 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 |
33398 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 |
33399 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 |
33400 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L |
33401 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL |
33402 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L |
33403 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L |
33404 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L |
33405 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L |
33406 | //RLC_RLCV_DOORBELL_STAT |
33407 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 |
33408 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 |
33409 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 |
33410 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 |
33411 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L |
33412 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L |
33413 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L |
33414 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L |
33415 | //RLC_RLCV_DOORBELL_0_DATA_LO |
33416 | #define RLC_RLCV_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 |
33417 | #define RLC_RLCV_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL |
33418 | //RLC_RLCV_DOORBELL_0_DATA_HI |
33419 | #define RLC_RLCV_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 |
33420 | #define RLC_RLCV_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL |
33421 | //RLC_RLCV_DOORBELL_1_DATA_LO |
33422 | #define RLC_RLCV_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 |
33423 | #define RLC_RLCV_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL |
33424 | //RLC_RLCV_DOORBELL_1_DATA_HI |
33425 | #define RLC_RLCV_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 |
33426 | #define RLC_RLCV_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL |
33427 | //RLC_RLCV_DOORBELL_2_DATA_LO |
33428 | #define RLC_RLCV_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 |
33429 | #define RLC_RLCV_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL |
33430 | //RLC_RLCV_DOORBELL_2_DATA_HI |
33431 | #define RLC_RLCV_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 |
33432 | #define RLC_RLCV_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL |
33433 | //RLC_RLCV_DOORBELL_3_DATA_LO |
33434 | #define RLC_RLCV_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 |
33435 | #define RLC_RLCV_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL |
33436 | //RLC_RLCV_DOORBELL_3_DATA_HI |
33437 | #define RLC_RLCV_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 |
33438 | #define RLC_RLCV_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL |
33439 | //RLC_RLCV_SPARE_INT |
33440 | #define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 |
33441 | #define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 |
33442 | #define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L |
33443 | #define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL |
33444 | //RLC_PACE_TIMER_INT_0 |
33445 | #define RLC_PACE_TIMER_INT_0__TIMER__SHIFT 0x0 |
33446 | #define RLC_PACE_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL |
33447 | //RLC_PACE_TIMER_CTRL |
33448 | #define RLC_PACE_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 |
33449 | #define RLC_PACE_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 |
33450 | #define RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x2 |
33451 | #define RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x3 |
33452 | #define RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x4 |
33453 | #define RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x5 |
33454 | #define RLC_PACE_TIMER_CTRL__RESERVED__SHIFT 0x6 |
33455 | #define RLC_PACE_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L |
33456 | #define RLC_PACE_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L |
33457 | #define RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000004L |
33458 | #define RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000008L |
33459 | #define RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00000010L |
33460 | #define RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00000020L |
33461 | #define RLC_PACE_TIMER_CTRL__RESERVED_MASK 0xFFFFFFC0L |
33462 | //RLC_PACE_TIMER_INT_1 |
33463 | #define RLC_PACE_TIMER_INT_1__TIMER__SHIFT 0x0 |
33464 | #define RLC_PACE_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL |
33465 | //RLC_PACE_SPARE_INT |
33466 | #define RLC_PACE_SPARE_INT__INTERRUPT__SHIFT 0x0 |
33467 | #define RLC_PACE_SPARE_INT__RESERVED__SHIFT 0x1 |
33468 | #define RLC_PACE_SPARE_INT__INTERRUPT_MASK 0x00000001L |
33469 | #define RLC_PACE_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL |
33470 | //RLC_SMU_CLK_REQ |
33471 | #define RLC_SMU_CLK_REQ__VALID__SHIFT 0x0 |
33472 | #define RLC_SMU_CLK_REQ__VALID_MASK 0x00000001L |
33473 | //RLC_CP_STAT_INVAL_STAT |
33474 | #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND__SHIFT 0x0 |
33475 | #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND__SHIFT 0x1 |
33476 | #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND__SHIFT 0x2 |
33477 | #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED__SHIFT 0x3 |
33478 | #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED__SHIFT 0x4 |
33479 | #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED__SHIFT 0x5 |
33480 | #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_MASK 0x00000001L |
33481 | #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_MASK 0x00000002L |
33482 | #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_MASK 0x00000004L |
33483 | #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED_MASK 0x00000008L |
33484 | #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED_MASK 0x00000010L |
33485 | #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED_MASK 0x00000020L |
33486 | //RLC_CP_STAT_INVAL_CTRL |
33487 | #define RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN__SHIFT 0x0 |
33488 | #define RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN__SHIFT 0x1 |
33489 | #define RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN__SHIFT 0x2 |
33490 | #define RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN_MASK 0x00000001L |
33491 | #define RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN_MASK 0x00000002L |
33492 | #define RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN_MASK 0x00000004L |
33493 | //RLC_CLK_STATUS |
33494 | #define RLC_CLK_STATUS__RLC_ALL_CLK_VALID__SHIFT 0x0 |
33495 | #define RLC_CLK_STATUS__RLC_CMN_GPM_SCLK_DYN_VLD__SHIFT 0x1 |
33496 | #define RLC_CLK_STATUS__RLC_CMN_TC_SCLK_DYN_VLD__SHIFT 0x2 |
33497 | #define RLC_CLK_STATUS__RLC_CMN_SPP_SCLK_DYN_VLD__SHIFT 0x3 |
33498 | #define RLC_CLK_STATUS__RLC_CMN_SRM_SCLK_DYN_VLD__SHIFT 0x5 |
33499 | #define RLC_CLK_STATUS__RLC_SRM_CLK_BUSY__SHIFT 0x6 |
33500 | #define RLC_CLK_STATUS__RLC_CMN_SPM_SCLK_DYN_VLD__SHIFT 0x7 |
33501 | #define RLC_CLK_STATUS__RLC_SPM_CLK_BUSY__SHIFT 0x8 |
33502 | #define RLC_CLK_STATUS__RESERVED__SHIFT 0x9 |
33503 | #define RLC_CLK_STATUS__RLC_ALL_CLK_VALID_MASK 0x00000001L |
33504 | #define RLC_CLK_STATUS__RLC_CMN_GPM_SCLK_DYN_VLD_MASK 0x00000002L |
33505 | #define RLC_CLK_STATUS__RLC_CMN_TC_SCLK_DYN_VLD_MASK 0x00000004L |
33506 | #define RLC_CLK_STATUS__RLC_CMN_SPP_SCLK_DYN_VLD_MASK 0x00000008L |
33507 | #define RLC_CLK_STATUS__RLC_CMN_SRM_SCLK_DYN_VLD_MASK 0x00000020L |
33508 | #define RLC_CLK_STATUS__RLC_SRM_CLK_BUSY_MASK 0x00000040L |
33509 | #define RLC_CLK_STATUS__RLC_CMN_SPM_SCLK_DYN_VLD_MASK 0x00000080L |
33510 | #define RLC_CLK_STATUS__RLC_SPM_CLK_BUSY_MASK 0x00000100L |
33511 | #define RLC_CLK_STATUS__RESERVED_MASK 0xFFFFFE00L |
33512 | //RLC_SPP_CTRL |
33513 | #define RLC_SPP_CTRL__ENABLE__SHIFT 0x0 |
33514 | #define RLC_SPP_CTRL__ENABLE_PPROF__SHIFT 0x1 |
33515 | #define RLC_SPP_CTRL__ENABLE_PWR_OPT__SHIFT 0x2 |
33516 | #define RLC_SPP_CTRL__PAUSE__SHIFT 0x3 |
33517 | #define RLC_SPP_CTRL__ENABLE_MASK 0x00000001L |
33518 | #define RLC_SPP_CTRL__ENABLE_PPROF_MASK 0x00000002L |
33519 | #define RLC_SPP_CTRL__ENABLE_PWR_OPT_MASK 0x00000004L |
33520 | #define RLC_SPP_CTRL__PAUSE_MASK 0x00000008L |
33521 | //RLC_SPP_SHADER_PROFILE_EN |
33522 | #define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE__SHIFT 0x0 |
33523 | #define RLC_SPP_SHADER_PROFILE_EN__VS_ENABLE__SHIFT 0x1 |
33524 | #define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE__SHIFT 0x2 |
33525 | #define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE__SHIFT 0x3 |
33526 | #define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE__SHIFT 0x4 |
33527 | #define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE__SHIFT 0x5 |
33528 | #define RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION__SHIFT 0x6 |
33529 | #define RLC_SPP_SHADER_PROFILE_EN__VS_STOP_CONDITION__SHIFT 0x7 |
33530 | #define RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION__SHIFT 0x8 |
33531 | #define RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION__SHIFT 0x9 |
33532 | #define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION__SHIFT 0xa |
33533 | #define RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION__SHIFT 0xb |
33534 | #define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION__SHIFT 0xc |
33535 | #define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION__SHIFT 0xd |
33536 | #define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS__SHIFT 0xe |
33537 | #define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED__SHIFT 0xf |
33538 | #define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK__SHIFT 0x10 |
33539 | #define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE_MASK 0x00000001L |
33540 | #define RLC_SPP_SHADER_PROFILE_EN__VS_ENABLE_MASK 0x00000002L |
33541 | #define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE_MASK 0x00000004L |
33542 | #define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE_MASK 0x00000008L |
33543 | #define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE_MASK 0x00000010L |
33544 | #define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE_MASK 0x00000020L |
33545 | #define RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION_MASK 0x00000040L |
33546 | #define RLC_SPP_SHADER_PROFILE_EN__VS_STOP_CONDITION_MASK 0x00000080L |
33547 | #define RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION_MASK 0x00000100L |
33548 | #define RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION_MASK 0x00000200L |
33549 | #define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION_MASK 0x00000400L |
33550 | #define RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION_MASK 0x00000800L |
33551 | #define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION_MASK 0x00001000L |
33552 | #define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION_MASK 0x00002000L |
33553 | #define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS_MASK 0x00004000L |
33554 | #define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED_MASK 0x00008000L |
33555 | #define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK_MASK 0x00010000L |
33556 | //RLC_SPP_SSF_CAPTURE_EN |
33557 | #define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE__SHIFT 0x0 |
33558 | #define RLC_SPP_SSF_CAPTURE_EN__VS_ENABLE__SHIFT 0x1 |
33559 | #define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE__SHIFT 0x2 |
33560 | #define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE__SHIFT 0x3 |
33561 | #define RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE__SHIFT 0x4 |
33562 | #define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE__SHIFT 0x5 |
33563 | #define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE_MASK 0x00000001L |
33564 | #define RLC_SPP_SSF_CAPTURE_EN__VS_ENABLE_MASK 0x00000002L |
33565 | #define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE_MASK 0x00000004L |
33566 | #define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE_MASK 0x00000008L |
33567 | #define RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE_MASK 0x00000010L |
33568 | #define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE_MASK 0x00000020L |
33569 | //RLC_SPP_SSF_THRESHOLD_0 |
33570 | #define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD__SHIFT 0x0 |
33571 | #define RLC_SPP_SSF_THRESHOLD_0__VS_THRESHOLD__SHIFT 0x10 |
33572 | #define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD_MASK 0x0000FFFFL |
33573 | #define RLC_SPP_SSF_THRESHOLD_0__VS_THRESHOLD_MASK 0xFFFF0000L |
33574 | //RLC_SPP_SSF_THRESHOLD_1 |
33575 | #define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD__SHIFT 0x0 |
33576 | #define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD__SHIFT 0x10 |
33577 | #define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD_MASK 0x0000FFFFL |
33578 | #define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD_MASK 0xFFFF0000L |
33579 | //RLC_SPP_SSF_THRESHOLD_2 |
33580 | #define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD__SHIFT 0x0 |
33581 | #define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD__SHIFT 0x10 |
33582 | #define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD_MASK 0x0000FFFFL |
33583 | #define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD_MASK 0xFFFF0000L |
33584 | //RLC_SPP_INFLIGHT_RD_ADDR |
33585 | #define RLC_SPP_INFLIGHT_RD_ADDR__ADDR__SHIFT 0x0 |
33586 | #define RLC_SPP_INFLIGHT_RD_ADDR__ADDR_MASK 0x0000001FL |
33587 | //RLC_SPP_INFLIGHT_RD_DATA |
33588 | #define RLC_SPP_INFLIGHT_RD_DATA__DATA__SHIFT 0x0 |
33589 | #define RLC_SPP_INFLIGHT_RD_DATA__DATA_MASK 0xFFFFFFFFL |
33590 | //RLC_GPM_GENERAL_16 |
33591 | #define RLC_GPM_GENERAL_16__DATA__SHIFT 0x0 |
33592 | #define RLC_GPM_GENERAL_16__DATA_MASK 0xFFFFFFFFL |
33593 | //RLC_SPP_PROF_INFO_1 |
33594 | #define RLC_SPP_PROF_INFO_1__SH_ID__SHIFT 0x0 |
33595 | #define RLC_SPP_PROF_INFO_1__SH_ID_MASK 0xFFFFFFFFL |
33596 | //RLC_SPP_PROF_INFO_2 |
33597 | #define RLC_SPP_PROF_INFO_2__SH_TYPE__SHIFT 0x0 |
33598 | #define RLC_SPP_PROF_INFO_2__CAM_HIT__SHIFT 0x4 |
33599 | #define RLC_SPP_PROF_INFO_2__CAM_LOCK__SHIFT 0x5 |
33600 | #define RLC_SPP_PROF_INFO_2__CAM_CONFLICT__SHIFT 0x6 |
33601 | #define RLC_SPP_PROF_INFO_2__SH_TYPE_MASK 0x0000000FL |
33602 | #define RLC_SPP_PROF_INFO_2__CAM_HIT_MASK 0x00000010L |
33603 | #define RLC_SPP_PROF_INFO_2__CAM_LOCK_MASK 0x00000020L |
33604 | #define RLC_SPP_PROF_INFO_2__CAM_CONFLICT_MASK 0x00000040L |
33605 | //RLC_SPP_GLOBAL_SH_ID |
33606 | #define RLC_SPP_GLOBAL_SH_ID__SH_ID__SHIFT 0x0 |
33607 | #define RLC_SPP_GLOBAL_SH_ID__SH_ID_MASK 0xFFFFFFFFL |
33608 | //RLC_SPP_GLOBAL_SH_ID_VALID |
33609 | #define RLC_SPP_GLOBAL_SH_ID_VALID__VALID__SHIFT 0x0 |
33610 | #define RLC_SPP_GLOBAL_SH_ID_VALID__VALID_MASK 0x00000001L |
33611 | //RLC_SPP_STATUS |
33612 | #define RLC_SPP_STATUS__RESERVED_0__SHIFT 0x0 |
33613 | #define RLC_SPP_STATUS__SSF_BUSY__SHIFT 0x1 |
33614 | #define RLC_SPP_STATUS__EVENT_ARB_BUSY__SHIFT 0x2 |
33615 | #define RLC_SPP_STATUS__SPP_BUSY__SHIFT 0x1f |
33616 | #define RLC_SPP_STATUS__RESERVED_0_MASK 0x00000001L |
33617 | #define RLC_SPP_STATUS__SSF_BUSY_MASK 0x00000002L |
33618 | #define RLC_SPP_STATUS__EVENT_ARB_BUSY_MASK 0x00000004L |
33619 | #define RLC_SPP_STATUS__SPP_BUSY_MASK 0x80000000L |
33620 | //RLC_SPP_PVT_STAT_0 |
33621 | #define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER__SHIFT 0x0 |
33622 | #define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER__SHIFT 0x6 |
33623 | #define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER__SHIFT 0xc |
33624 | #define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER__SHIFT 0x12 |
33625 | #define RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER__SHIFT 0x18 |
33626 | #define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER_MASK 0x0000003FL |
33627 | #define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER_MASK 0x00000FC0L |
33628 | #define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER_MASK 0x0003F000L |
33629 | #define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER_MASK 0x00FC0000L |
33630 | #define RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER_MASK 0x7F000000L |
33631 | //RLC_SPP_PVT_STAT_1 |
33632 | #define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER__SHIFT 0x0 |
33633 | #define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER__SHIFT 0x6 |
33634 | #define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER__SHIFT 0xc |
33635 | #define RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER__SHIFT 0x12 |
33636 | #define RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER__SHIFT 0x18 |
33637 | #define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER_MASK 0x0000003FL |
33638 | #define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER_MASK 0x00000FC0L |
33639 | #define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER_MASK 0x0003F000L |
33640 | #define RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER_MASK 0x00FC0000L |
33641 | #define RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER_MASK 0x7F000000L |
33642 | //RLC_SPP_PVT_STAT_2 |
33643 | #define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER__SHIFT 0x0 |
33644 | #define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER__SHIFT 0x6 |
33645 | #define RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER__SHIFT 0xc |
33646 | #define RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER__SHIFT 0x12 |
33647 | #define RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER__SHIFT 0x18 |
33648 | #define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER_MASK 0x0000003FL |
33649 | #define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER_MASK 0x00000FC0L |
33650 | #define RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER_MASK 0x0003F000L |
33651 | #define RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER_MASK 0x00FC0000L |
33652 | #define RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER_MASK 0x7F000000L |
33653 | //RLC_SPP_PVT_STAT_3 |
33654 | #define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER__SHIFT 0x0 |
33655 | #define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER_MASK 0x0000003FL |
33656 | //RLC_SPP_PVT_LEVEL_MAX |
33657 | #define RLC_SPP_PVT_LEVEL_MAX__LEVEL__SHIFT 0x0 |
33658 | #define RLC_SPP_PVT_LEVEL_MAX__LEVEL_MASK 0x0000000FL |
33659 | //RLC_SPP_STALL_STATE_UPDATE |
33660 | #define RLC_SPP_STALL_STATE_UPDATE__STALL__SHIFT 0x0 |
33661 | #define RLC_SPP_STALL_STATE_UPDATE__ENABLE__SHIFT 0x1 |
33662 | #define RLC_SPP_STALL_STATE_UPDATE__STALL_MASK 0x00000001L |
33663 | #define RLC_SPP_STALL_STATE_UPDATE__ENABLE_MASK 0x00000002L |
33664 | //RLC_SPP_PBB_INFO |
33665 | #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE__SHIFT 0x0 |
33666 | #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID__SHIFT 0x1 |
33667 | #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE__SHIFT 0x2 |
33668 | #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID__SHIFT 0x3 |
33669 | #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_MASK 0x00000001L |
33670 | #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID_MASK 0x00000002L |
33671 | #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_MASK 0x00000004L |
33672 | #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID_MASK 0x00000008L |
33673 | //RLC_SPP_RESET |
33674 | #define RLC_SPP_RESET__SSF_RESET__SHIFT 0x0 |
33675 | #define RLC_SPP_RESET__EVENT_ARB_RESET__SHIFT 0x1 |
33676 | #define RLC_SPP_RESET__CAM_RESET__SHIFT 0x2 |
33677 | #define RLC_SPP_RESET__PVT_RESET__SHIFT 0x3 |
33678 | #define RLC_SPP_RESET__SSF_RESET_MASK 0x00000001L |
33679 | #define RLC_SPP_RESET__EVENT_ARB_RESET_MASK 0x00000002L |
33680 | #define RLC_SPP_RESET__CAM_RESET_MASK 0x00000004L |
33681 | #define RLC_SPP_RESET__PVT_RESET_MASK 0x00000008L |
33682 | //RLC_SPM_SAMPLE_CNT |
33683 | #define RLC_SPM_SAMPLE_CNT__COUNT__SHIFT 0x0 |
33684 | #define RLC_SPM_SAMPLE_CNT__COUNT_MASK 0xFFFFFFFFL |
33685 | //RLC_RLCP_DOORBELL_RANGE |
33686 | #define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 |
33687 | #define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 |
33688 | #define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 |
33689 | #define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 |
33690 | #define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L |
33691 | #define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL |
33692 | #define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L |
33693 | #define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L |
33694 | //RLC_RLCP_DOORBELL_CNTL |
33695 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 |
33696 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 |
33697 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 |
33698 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 |
33699 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 |
33700 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 |
33701 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L |
33702 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL |
33703 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L |
33704 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L |
33705 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L |
33706 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L |
33707 | //RLC_RLCP_DOORBELL_STAT |
33708 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 |
33709 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 |
33710 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 |
33711 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 |
33712 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L |
33713 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L |
33714 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L |
33715 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L |
33716 | //RLC_RLCP_DOORBELL_0_DATA_LO |
33717 | #define RLC_RLCP_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 |
33718 | #define RLC_RLCP_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL |
33719 | //RLC_RLCP_DOORBELL_0_DATA_HI |
33720 | #define RLC_RLCP_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 |
33721 | #define RLC_RLCP_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL |
33722 | //RLC_RLCP_DOORBELL_1_DATA_LO |
33723 | #define RLC_RLCP_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 |
33724 | #define RLC_RLCP_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL |
33725 | //RLC_RLCP_DOORBELL_1_DATA_HI |
33726 | #define RLC_RLCP_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 |
33727 | #define RLC_RLCP_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL |
33728 | //RLC_RLCP_DOORBELL_2_DATA_LO |
33729 | #define RLC_RLCP_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 |
33730 | #define RLC_RLCP_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL |
33731 | //RLC_RLCP_DOORBELL_2_DATA_HI |
33732 | #define RLC_RLCP_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 |
33733 | #define RLC_RLCP_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL |
33734 | //RLC_RLCP_DOORBELL_3_DATA_LO |
33735 | #define RLC_RLCP_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 |
33736 | #define RLC_RLCP_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL |
33737 | //RLC_RLCP_DOORBELL_3_DATA_HI |
33738 | #define RLC_RLCP_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 |
33739 | #define RLC_RLCP_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL |
33740 | //RLC_PCC_STRETCH_HYSTERESIS_CNTL |
33741 | #define RLC_PCC_STRETCH_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT 0x0 |
33742 | #define RLC_PCC_STRETCH_HYSTERESIS_CNTL__HYSTERESIS_CNT__SHIFT 0x8 |
33743 | #define RLC_PCC_STRETCH_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK 0x000000FFL |
33744 | #define RLC_PCC_STRETCH_HYSTERESIS_CNTL__HYSTERESIS_CNT_MASK 0x0000FF00L |
33745 | //RLC_CAC_MASK_CNTL |
33746 | #define RLC_CAC_MASK_CNTL__RLC_CAC_MASK__SHIFT 0x0 |
33747 | #define RLC_CAC_MASK_CNTL__RLC_CAC_MASK_MASK 0xFFFFFFFFL |
33748 | //RLC_GPU_CLOCK_COUNT_SPM_LSB |
33749 | #define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 |
33750 | #define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
33751 | //RLC_GPU_CLOCK_COUNT_SPM_MSB |
33752 | #define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 |
33753 | #define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
33754 | //RLC_SPM_THREAD_TRACE_CTRL |
33755 | #define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN__SHIFT 0x0 |
33756 | #define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN_MASK 0x00000001L |
33757 | //RLC_LB_CNTR_2 |
33758 | #define RLC_LB_CNTR_2__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 |
33759 | #define RLC_LB_CNTR_2__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL |
33760 | //RLC_CPAXI_DOORBELL_MON_CTRL |
33761 | #define RLC_CPAXI_DOORBELL_MON_CTRL__EN__SHIFT 0x0 |
33762 | #define RLC_CPAXI_DOORBELL_MON_CTRL__ID__SHIFT 0x1 |
33763 | #define RLC_CPAXI_DOORBELL_MON_CTRL__EN_MASK 0x00000001L |
33764 | #define RLC_CPAXI_DOORBELL_MON_CTRL__ID_MASK 0x0000003EL |
33765 | //RLC_CPAXI_DOORBELL_MON_STAT |
33766 | #define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH__SHIFT 0x0 |
33767 | #define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR__SHIFT 0x1 |
33768 | #define RLC_CPAXI_DOORBELL_MON_STAT__ADDR__SHIFT 0x2 |
33769 | #define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH_MASK 0x00000001L |
33770 | #define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR_MASK 0x00000002L |
33771 | #define RLC_CPAXI_DOORBELL_MON_STAT__ADDR_MASK 0x0FFFFFFCL |
33772 | //RLC_CPAXI_DOORBELL_MON_DATA_LSB |
33773 | #define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA__SHIFT 0x0 |
33774 | #define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA_MASK 0xFFFFFFFFL |
33775 | //RLC_CPAXI_DOORBELL_MON_DATA_MSB |
33776 | #define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA__SHIFT 0x0 |
33777 | #define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA_MASK 0xFFFFFFFFL |
33778 | //RLC_XT_DOORBELL_RANGE |
33779 | #define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 |
33780 | #define RLC_XT_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 |
33781 | #define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 |
33782 | #define RLC_XT_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 |
33783 | #define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L |
33784 | #define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL |
33785 | #define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L |
33786 | #define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L |
33787 | //RLC_XT_DOORBELL_CNTL |
33788 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 |
33789 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 |
33790 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 |
33791 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 |
33792 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 |
33793 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 |
33794 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L |
33795 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL |
33796 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L |
33797 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L |
33798 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L |
33799 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L |
33800 | //RLC_XT_DOORBELL_STAT |
33801 | #define RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 |
33802 | #define RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 |
33803 | #define RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 |
33804 | #define RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 |
33805 | #define RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L |
33806 | #define RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L |
33807 | #define RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L |
33808 | #define RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L |
33809 | //RLC_XT_DOORBELL_0_DATA_LO |
33810 | #define RLC_XT_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 |
33811 | #define RLC_XT_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL |
33812 | //RLC_XT_DOORBELL_0_DATA_HI |
33813 | #define RLC_XT_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 |
33814 | #define RLC_XT_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL |
33815 | //RLC_XT_DOORBELL_1_DATA_LO |
33816 | #define RLC_XT_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 |
33817 | #define RLC_XT_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL |
33818 | //RLC_XT_DOORBELL_1_DATA_HI |
33819 | #define RLC_XT_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 |
33820 | #define RLC_XT_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL |
33821 | //RLC_XT_DOORBELL_2_DATA_LO |
33822 | #define RLC_XT_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 |
33823 | #define RLC_XT_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL |
33824 | //RLC_XT_DOORBELL_2_DATA_HI |
33825 | #define RLC_XT_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 |
33826 | #define RLC_XT_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL |
33827 | //RLC_XT_DOORBELL_3_DATA_LO |
33828 | #define RLC_XT_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 |
33829 | #define RLC_XT_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL |
33830 | //RLC_XT_DOORBELL_3_DATA_HI |
33831 | #define RLC_XT_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 |
33832 | #define RLC_XT_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL |
33833 | |
33834 | |
33835 | // addressBlock: gc_rlcrdec |
33836 | //RLC_SPP_CAM_ADDR |
33837 | #define RLC_SPP_CAM_ADDR__ADDR__SHIFT 0x0 |
33838 | #define RLC_SPP_CAM_ADDR__ADDR_MASK 0x000000FFL |
33839 | //RLC_SPP_CAM_DATA |
33840 | #define RLC_SPP_CAM_DATA__DATA__SHIFT 0x0 |
33841 | #define RLC_SPP_CAM_DATA__TAG__SHIFT 0x8 |
33842 | #define RLC_SPP_CAM_DATA__DATA_MASK 0x000000FFL |
33843 | #define RLC_SPP_CAM_DATA__TAG_MASK 0xFFFFFF00L |
33844 | //RLC_SPP_CAM_EXT_ADDR |
33845 | #define RLC_SPP_CAM_EXT_ADDR__ADDR__SHIFT 0x0 |
33846 | #define RLC_SPP_CAM_EXT_ADDR__ADDR_MASK 0x000000FFL |
33847 | //RLC_SPP_CAM_EXT_DATA |
33848 | #define RLC_SPP_CAM_EXT_DATA__VALID__SHIFT 0x0 |
33849 | #define RLC_SPP_CAM_EXT_DATA__LOCK__SHIFT 0x1 |
33850 | #define RLC_SPP_CAM_EXT_DATA__VALID_MASK 0x00000001L |
33851 | #define RLC_SPP_CAM_EXT_DATA__LOCK_MASK 0x00000002L |
33852 | //RLC_PACE_SCRATCH_ADDR |
33853 | #define RLC_PACE_SCRATCH_ADDR__ADDR__SHIFT 0x0 |
33854 | #define RLC_PACE_SCRATCH_ADDR__ADDR_MASK 0x0000FFFFL |
33855 | //RLC_PACE_SCRATCH_DATA |
33856 | #define RLC_PACE_SCRATCH_DATA__DATA__SHIFT 0x0 |
33857 | #define RLC_PACE_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL |
33858 | |
33859 | |
33860 | // addressBlock: gc_rlcsdec |
33861 | //RLC_RLCS_DEC_START |
33862 | //RLC_RLCS_DEC_DUMP_ADDR |
33863 | //RLC_RLCS_EXCEPTION_REG_1 |
33864 | #define RLC_RLCS_EXCEPTION_REG_1__ADDR__SHIFT 0x0 |
33865 | #define RLC_RLCS_EXCEPTION_REG_1__RESERVED__SHIFT 0x12 |
33866 | #define RLC_RLCS_EXCEPTION_REG_1__ADDR_MASK 0x0003FFFFL |
33867 | #define RLC_RLCS_EXCEPTION_REG_1__RESERVED_MASK 0xFFFC0000L |
33868 | //RLC_RLCS_EXCEPTION_REG_2 |
33869 | #define RLC_RLCS_EXCEPTION_REG_2__ADDR__SHIFT 0x0 |
33870 | #define RLC_RLCS_EXCEPTION_REG_2__RESERVED__SHIFT 0x12 |
33871 | #define RLC_RLCS_EXCEPTION_REG_2__ADDR_MASK 0x0003FFFFL |
33872 | #define RLC_RLCS_EXCEPTION_REG_2__RESERVED_MASK 0xFFFC0000L |
33873 | //RLC_RLCS_EXCEPTION_REG_3 |
33874 | #define RLC_RLCS_EXCEPTION_REG_3__ADDR__SHIFT 0x0 |
33875 | #define RLC_RLCS_EXCEPTION_REG_3__RESERVED__SHIFT 0x12 |
33876 | #define RLC_RLCS_EXCEPTION_REG_3__ADDR_MASK 0x0003FFFFL |
33877 | #define RLC_RLCS_EXCEPTION_REG_3__RESERVED_MASK 0xFFFC0000L |
33878 | //RLC_RLCS_EXCEPTION_REG_4 |
33879 | #define RLC_RLCS_EXCEPTION_REG_4__ADDR__SHIFT 0x0 |
33880 | #define RLC_RLCS_EXCEPTION_REG_4__RESERVED__SHIFT 0x12 |
33881 | #define RLC_RLCS_EXCEPTION_REG_4__ADDR_MASK 0x0003FFFFL |
33882 | #define RLC_RLCS_EXCEPTION_REG_4__RESERVED_MASK 0xFFFC0000L |
33883 | //RLC_RLCS_GENERAL_6 |
33884 | #define RLC_RLCS_GENERAL_6__DATA__SHIFT 0x0 |
33885 | #define RLC_RLCS_GENERAL_6__DATA_MASK 0xFFFFFFFFL |
33886 | //RLC_RLCS_GENERAL_7 |
33887 | #define RLC_RLCS_GENERAL_7__DATA__SHIFT 0x0 |
33888 | #define RLC_RLCS_GENERAL_7__DATA_MASK 0xFFFFFFFFL |
33889 | //RLC_RLCS_CGCG_REQUEST |
33890 | #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST__SHIFT 0x0 |
33891 | #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D__SHIFT 0x1 |
33892 | #define RLC_RLCS_CGCG_REQUEST__RESERVED__SHIFT 0x2 |
33893 | #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_MASK 0x00000001L |
33894 | #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D_MASK 0x00000002L |
33895 | #define RLC_RLCS_CGCG_REQUEST__RESERVED_MASK 0xFFFFFFFCL |
33896 | //RLC_RLCS_CGCG_STATUS |
33897 | #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS__SHIFT 0x0 |
33898 | #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS__SHIFT 0x2 |
33899 | #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D__SHIFT 0x3 |
33900 | #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D__SHIFT 0x5 |
33901 | #define RLC_RLCS_CGCG_STATUS__RESERVED__SHIFT 0x6 |
33902 | #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_MASK 0x00000003L |
33903 | #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_MASK 0x00000004L |
33904 | #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D_MASK 0x00000018L |
33905 | #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D_MASK 0x00000020L |
33906 | #define RLC_RLCS_CGCG_STATUS__RESERVED_MASK 0xFFFFFFC0L |
33907 | //RLC_RLCS_SMU_GFXCLK_STATUS |
33908 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_DONETOG__SHIFT 0x0 |
33909 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXMUX_CUR_VALUE__SHIFT 0x1 |
33910 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_STRETCH_PCC__SHIFT 0x2 |
33911 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_PCC_CTRL__SHIFT 0x3 |
33912 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_DONETOG_MASK 0x00000001L |
33913 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXMUX_CUR_VALUE_MASK 0x00000002L |
33914 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_STRETCH_PCC_MASK 0x00000004L |
33915 | #define RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_PCC_CTRL_MASK 0x00000008L |
33916 | //RLC_RLCS_SMU_GFXCLK_CONTROL |
33917 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_CHGTOG__SHIFT 0x0 |
33918 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_DIVIDER__SHIFT 0x1 |
33919 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXMUX_SEL__SHIFT 0x8 |
33920 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__RESERVED__SHIFT 0x9 |
33921 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_CHGTOG_MASK 0x00000001L |
33922 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_DIVIDER_MASK 0x000000FEL |
33923 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXMUX_SEL_MASK 0x00000100L |
33924 | #define RLC_RLCS_SMU_GFXCLK_CONTROL__RESERVED_MASK 0xFFFFFE00L |
33925 | //RLC_RLCS_SOC_DS_CNTL |
33926 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW__SHIFT 0x0 |
33927 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x1 |
33928 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x2 |
33929 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT 0x6 |
33930 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT 0x7 |
33931 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK__SHIFT 0x10 |
33932 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK__SHIFT 0x11 |
33933 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK__SHIFT 0x12 |
33934 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK__SHIFT 0x13 |
33935 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK__SHIFT 0x14 |
33936 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK__SHIFT 0x15 |
33937 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK__SHIFT 0x16 |
33938 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK__SHIFT 0x17 |
33939 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW_MASK 0x00000001L |
33940 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00000002L |
33941 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00000004L |
33942 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK_MASK 0x00000040L |
33943 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK_MASK 0x00000080L |
33944 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK_MASK 0x00010000L |
33945 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK_MASK 0x00020000L |
33946 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK_MASK 0x00040000L |
33947 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK_MASK 0x00080000L |
33948 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK_MASK 0x00100000L |
33949 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK_MASK 0x00200000L |
33950 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK_MASK 0x00400000L |
33951 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK_MASK 0x00800000L |
33952 | //RLC_RLCS_GFX_DS_CNTL |
33953 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW__SHIFT 0x0 |
33954 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x1 |
33955 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x2 |
33956 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT 0x6 |
33957 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT 0x7 |
33958 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK__SHIFT 0x10 |
33959 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK__SHIFT 0x11 |
33960 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK__SHIFT 0x12 |
33961 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK__SHIFT 0x13 |
33962 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK__SHIFT 0x14 |
33963 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK__SHIFT 0x15 |
33964 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK__SHIFT 0x16 |
33965 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK__SHIFT 0x17 |
33966 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW_MASK 0x00000001L |
33967 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000002L |
33968 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000004L |
33969 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK_MASK 0x00000040L |
33970 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK_MASK 0x00000080L |
33971 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK_MASK 0x00010000L |
33972 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK_MASK 0x00020000L |
33973 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK_MASK 0x00040000L |
33974 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK_MASK 0x00080000L |
33975 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK_MASK 0x00100000L |
33976 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK_MASK 0x00200000L |
33977 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK_MASK 0x00400000L |
33978 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK_MASK 0x00800000L |
33979 | //RLC_GPM_STAT |
33980 | #define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 |
33981 | #define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 |
33982 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 |
33983 | #define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 |
33984 | #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 |
33985 | #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 |
33986 | #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 |
33987 | #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 |
33988 | #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 |
33989 | #define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 |
33990 | #define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa |
33991 | #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb |
33992 | #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc |
33993 | #define RLC_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT 0xd |
33994 | #define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT 0xe |
33995 | #define RLC_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT 0xf |
33996 | #define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT 0x10 |
33997 | #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 |
33998 | #define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12 |
33999 | #define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13 |
34000 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14 |
34001 | #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 |
34002 | #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 |
34003 | #define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 |
34004 | #define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 |
34005 | #define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L |
34006 | #define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L |
34007 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L |
34008 | #define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L |
34009 | #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L |
34010 | #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L |
34011 | #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L |
34012 | #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L |
34013 | #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L |
34014 | #define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L |
34015 | #define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L |
34016 | #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L |
34017 | #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L |
34018 | #define RLC_GPM_STAT__STATIC_WGP_POWERING_UP_MASK 0x00002000L |
34019 | #define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK 0x00004000L |
34020 | #define RLC_GPM_STAT__DYN_WGP_POWERING_UP_MASK 0x00008000L |
34021 | #define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK 0x00010000L |
34022 | #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L |
34023 | #define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L |
34024 | #define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L |
34025 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L |
34026 | #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L |
34027 | #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L |
34028 | #define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L |
34029 | #define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L |
34030 | //RLC_RLCS_GPM_STAT |
34031 | #define RLC_RLCS_GPM_STAT__RLC_BUSY__SHIFT 0x0 |
34032 | #define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 |
34033 | #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 |
34034 | #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 |
34035 | #define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 |
34036 | #define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 |
34037 | #define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 |
34038 | #define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 |
34039 | #define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 |
34040 | #define RLC_RLCS_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 |
34041 | #define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa |
34042 | #define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb |
34043 | #define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc |
34044 | #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT 0xd |
34045 | #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT 0xe |
34046 | #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT 0xf |
34047 | #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT 0x10 |
34048 | #define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 |
34049 | #define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS__SHIFT 0x12 |
34050 | #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13 |
34051 | #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14 |
34052 | #define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 |
34053 | #define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 |
34054 | #define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 |
34055 | #define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 |
34056 | #define RLC_RLCS_GPM_STAT__RLC_BUSY_MASK 0x00000001L |
34057 | #define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L |
34058 | #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L |
34059 | #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L |
34060 | #define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L |
34061 | #define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L |
34062 | #define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L |
34063 | #define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L |
34064 | #define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L |
34065 | #define RLC_RLCS_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L |
34066 | #define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L |
34067 | #define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L |
34068 | #define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L |
34069 | #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP_MASK 0x00002000L |
34070 | #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK 0x00004000L |
34071 | #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP_MASK 0x00008000L |
34072 | #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK 0x00010000L |
34073 | #define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L |
34074 | #define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS_MASK 0x00040000L |
34075 | #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L |
34076 | #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L |
34077 | #define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L |
34078 | #define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L |
34079 | #define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L |
34080 | #define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L |
34081 | //RLC_RLCS_ABORTED_PD_SEQUENCE |
34082 | #define RLC_RLCS_ABORTED_PD_SEQUENCE__APS__SHIFT 0x0 |
34083 | #define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED__SHIFT 0x10 |
34084 | #define RLC_RLCS_ABORTED_PD_SEQUENCE__APS_MASK 0x0000FFFFL |
34085 | #define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED_MASK 0xFFFF0000L |
34086 | //RLC_RLCS_DIDT_FORCE_STALL |
34087 | #define RLC_RLCS_DIDT_FORCE_STALL__DFS__SHIFT 0x0 |
34088 | #define RLC_RLCS_DIDT_FORCE_STALL__RESERVED__SHIFT 0x3 |
34089 | #define RLC_RLCS_DIDT_FORCE_STALL__DFS_MASK 0x00000007L |
34090 | #define RLC_RLCS_DIDT_FORCE_STALL__RESERVED_MASK 0xFFFFFFF8L |
34091 | //RLC_RLCS_IOV_CMD_STATUS |
34092 | #define RLC_RLCS_IOV_CMD_STATUS__DATA__SHIFT 0x0 |
34093 | #define RLC_RLCS_IOV_CMD_STATUS__DATA_MASK 0xFFFFFFFFL |
34094 | //RLC_RLCS_IOV_CNTX_LOC_SIZE |
34095 | #define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA__SHIFT 0x0 |
34096 | #define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED__SHIFT 0x8 |
34097 | #define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA_MASK 0x000000FFL |
34098 | #define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED_MASK 0xFFFFFF00L |
34099 | //RLC_RLCS_IOV_SCH_BLOCK |
34100 | #define RLC_RLCS_IOV_SCH_BLOCK__DATA__SHIFT 0x0 |
34101 | #define RLC_RLCS_IOV_SCH_BLOCK__DATA_MASK 0xFFFFFFFFL |
34102 | //RLC_RLCS_IOV_VM_BUSY_STATUS |
34103 | #define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA__SHIFT 0x0 |
34104 | #define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA_MASK 0xFFFFFFFFL |
34105 | //RLC_RLCS_GPM_STAT_2 |
34106 | #define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR__SHIFT 0x0 |
34107 | #define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED__SHIFT 0x1 |
34108 | #define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS__SHIFT 0x2 |
34109 | #define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS__SHIFT 0x3 |
34110 | #define RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS__SHIFT 0x4 |
34111 | #define RLC_RLCS_GPM_STAT_2__RESERVED__SHIFT 0x5 |
34112 | #define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR_MASK 0x00000001L |
34113 | #define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED_MASK 0x00000002L |
34114 | #define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS_MASK 0x00000004L |
34115 | #define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS_MASK 0x00000008L |
34116 | #define RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS_MASK 0x00000010L |
34117 | #define RLC_RLCS_GPM_STAT_2__RESERVED_MASK 0xFFFFFFE0L |
34118 | //RLC_RLCS_GRBM_SOFT_RESET |
34119 | #define RLC_RLCS_GRBM_SOFT_RESET__RESET__SHIFT 0x0 |
34120 | #define RLC_RLCS_GRBM_SOFT_RESET__RESERVED__SHIFT 0x1 |
34121 | #define RLC_RLCS_GRBM_SOFT_RESET__RESET_MASK 0x00000001L |
34122 | #define RLC_RLCS_GRBM_SOFT_RESET__RESERVED_MASK 0xFFFFFFFEL |
34123 | //RLC_RLCS_PG_CHANGE_STATUS |
34124 | #define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED__SHIFT 0x0 |
34125 | #define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED__SHIFT 0x1 |
34126 | #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED__SHIFT 0x2 |
34127 | #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED__SHIFT 0x3 |
34128 | #define RLC_RLCS_PG_CHANGE_STATUS__RESERVED__SHIFT 0x4 |
34129 | #define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED_MASK 0x00000001L |
34130 | #define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED_MASK 0x00000002L |
34131 | #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED_MASK 0x00000004L |
34132 | #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED_MASK 0x00000008L |
34133 | #define RLC_RLCS_PG_CHANGE_STATUS__RESERVED_MASK 0xFFFFFFF0L |
34134 | //RLC_RLCS_PG_CHANGE_READ |
34135 | #define RLC_RLCS_PG_CHANGE_READ__PG_CNTL_CHANGED__SHIFT 0x0 |
34136 | #define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED__SHIFT 0x1 |
34137 | #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED__SHIFT 0x2 |
34138 | #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED__SHIFT 0x3 |
34139 | #define RLC_RLCS_PG_CHANGE_READ__RESERVED__SHIFT 0x4 |
34140 | #define RLC_RLCS_PG_CHANGE_READ__PG_CNTL_CHANGED_MASK 0x00000001L |
34141 | #define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED_MASK 0x00000002L |
34142 | #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED_MASK 0x00000004L |
34143 | #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED_MASK 0x00000008L |
34144 | #define RLC_RLCS_PG_CHANGE_READ__RESERVED_MASK 0xFFFFFFF0L |
34145 | //RLC_RLCS_LB_STATUS |
34146 | #define RLC_RLCS_LB_STATUS__LB_CNTR_START__SHIFT 0x0 |
34147 | #define RLC_RLCS_LB_STATUS__LB_CNTR_STOP__SHIFT 0x1 |
34148 | #define RLC_RLCS_LB_STATUS__LB_CNTR_1_MAX_FLAG__SHIFT 0x2 |
34149 | #define RLC_RLCS_LB_STATUS__LB_CNTR_2_MAX_FLAG__SHIFT 0x3 |
34150 | #define RLC_RLCS_LB_STATUS__LBPW_DISABLE_FLAG__SHIFT 0x4 |
34151 | #define RLC_RLCS_LB_STATUS__RESERVED__SHIFT 0x5 |
34152 | #define RLC_RLCS_LB_STATUS__LB_CNTR_START_MASK 0x00000001L |
34153 | #define RLC_RLCS_LB_STATUS__LB_CNTR_STOP_MASK 0x00000002L |
34154 | #define RLC_RLCS_LB_STATUS__LB_CNTR_1_MAX_FLAG_MASK 0x00000004L |
34155 | #define RLC_RLCS_LB_STATUS__LB_CNTR_2_MAX_FLAG_MASK 0x00000008L |
34156 | #define RLC_RLCS_LB_STATUS__LBPW_DISABLE_FLAG_MASK 0x00000010L |
34157 | #define RLC_RLCS_LB_STATUS__RESERVED_MASK 0xFFFFFFE0L |
34158 | //RLC_RLCS_LB_READ |
34159 | #define RLC_RLCS_LB_READ__LB_CNTR_START__SHIFT 0x0 |
34160 | #define RLC_RLCS_LB_READ__LB_CNTR_STOP__SHIFT 0x1 |
34161 | #define RLC_RLCS_LB_READ__LB_CNTR_1_MAX_FLAG__SHIFT 0x2 |
34162 | #define RLC_RLCS_LB_READ__LB_CNTR_2_MAX_FLAG__SHIFT 0x3 |
34163 | #define RLC_RLCS_LB_READ__LBPW_DISABLE_FLAG__SHIFT 0x4 |
34164 | #define RLC_RLCS_LB_READ__RESERVED__SHIFT 0x5 |
34165 | #define RLC_RLCS_LB_READ__LB_CNTR_START_MASK 0x00000001L |
34166 | #define RLC_RLCS_LB_READ__LB_CNTR_STOP_MASK 0x00000002L |
34167 | #define RLC_RLCS_LB_READ__LB_CNTR_1_MAX_FLAG_MASK 0x00000004L |
34168 | #define RLC_RLCS_LB_READ__LB_CNTR_2_MAX_FLAG_MASK 0x00000008L |
34169 | #define RLC_RLCS_LB_READ__LBPW_DISABLE_FLAG_MASK 0x00000010L |
34170 | #define RLC_RLCS_LB_READ__RESERVED_MASK 0xFFFFFFE0L |
34171 | //RLC_RLCS_LB_CONTROL |
34172 | #define RLC_RLCS_LB_CONTROL__NEW_LBPW_REQ__SHIFT 0x0 |
34173 | #define RLC_RLCS_LB_CONTROL__LB_CNTR_INC_CP_BUSY__SHIFT 0x1 |
34174 | #define RLC_RLCS_LB_CONTROL__RESERVED__SHIFT 0x2 |
34175 | #define RLC_RLCS_LB_CONTROL__NEW_LBPW_REQ_MASK 0x00000001L |
34176 | #define RLC_RLCS_LB_CONTROL__LB_CNTR_INC_CP_BUSY_MASK 0x00000002L |
34177 | #define RLC_RLCS_LB_CONTROL__RESERVED_MASK 0xFFFFFFFCL |
34178 | //RLC_RLCS_IH_SEMAPHORE |
34179 | #define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID__SHIFT 0x0 |
34180 | #define RLC_RLCS_IH_SEMAPHORE__RESERVED__SHIFT 0x5 |
34181 | #define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID_MASK 0x0000001FL |
34182 | #define RLC_RLCS_IH_SEMAPHORE__RESERVED_MASK 0xFFFFFFE0L |
34183 | //RLC_RLCS_IH_COOKIE_SEMAPHORE |
34184 | #define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID__SHIFT 0x0 |
34185 | #define RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED__SHIFT 0x5 |
34186 | #define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID_MASK 0x0000001FL |
34187 | #define RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED_MASK 0xFFFFFFE0L |
34188 | //RLC_RLCS_IH_CTRL_1 |
34189 | #define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1__SHIFT 0x0 |
34190 | #define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1_MASK 0xFFFFFFFFL |
34191 | //RLC_RLCS_IH_CTRL_2 |
34192 | #define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2__SHIFT 0x0 |
34193 | #define RLC_RLCS_IH_CTRL_2__IH_RING_ID__SHIFT 0x8 |
34194 | #define RLC_RLCS_IH_CTRL_2__IH_VM_ID__SHIFT 0x10 |
34195 | #define RLC_RLCS_IH_CTRL_2__RESERVED__SHIFT 0x14 |
34196 | #define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2_MASK 0x000000FFL |
34197 | #define RLC_RLCS_IH_CTRL_2__IH_RING_ID_MASK 0x0000FF00L |
34198 | #define RLC_RLCS_IH_CTRL_2__IH_VM_ID_MASK 0x000F0000L |
34199 | #define RLC_RLCS_IH_CTRL_2__RESERVED_MASK 0xFFF00000L |
34200 | //RLC_RLCS_IH_CTRL_3 |
34201 | #define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID__SHIFT 0x0 |
34202 | #define RLC_RLCS_IH_CTRL_3__IH_VF_ID__SHIFT 0x8 |
34203 | #define RLC_RLCS_IH_CTRL_3__IH_VF__SHIFT 0xd |
34204 | #define RLC_RLCS_IH_CTRL_3__RESERVED__SHIFT 0xe |
34205 | #define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID_MASK 0x000000FFL |
34206 | #define RLC_RLCS_IH_CTRL_3__IH_VF_ID_MASK 0x00001F00L |
34207 | #define RLC_RLCS_IH_CTRL_3__IH_VF_MASK 0x00002000L |
34208 | #define RLC_RLCS_IH_CTRL_3__RESERVED_MASK 0xFFFFC000L |
34209 | //RLC_RLCS_IH_STATUS |
34210 | #define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT__SHIFT 0x0 |
34211 | #define RLC_RLCS_IH_STATUS__IH_BUSY__SHIFT 0x6 |
34212 | #define RLC_RLCS_IH_STATUS__RESERVED__SHIFT 0x7 |
34213 | #define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT_MASK 0x0000003FL |
34214 | #define RLC_RLCS_IH_STATUS__IH_BUSY_MASK 0x00000040L |
34215 | #define RLC_RLCS_IH_STATUS__RESERVED_MASK 0xFFFFFF80L |
34216 | //RLC_RLCS_WGP_STATUS |
34217 | #define RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE__SHIFT 0x0 |
34218 | #define RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED__SHIFT 0x1 |
34219 | #define RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED__SHIFT 0x2 |
34220 | #define RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE__SHIFT 0x3 |
34221 | #define RLC_RLCS_WGP_STATUS__RESERVED__SHIFT 0x4 |
34222 | #define RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE_MASK 0x00000001L |
34223 | #define RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED_MASK 0x00000002L |
34224 | #define RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED_MASK 0x00000004L |
34225 | #define RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE_MASK 0x00000008L |
34226 | #define RLC_RLCS_WGP_STATUS__RESERVED_MASK 0xFFFFFFF0L |
34227 | //RLC_RLCS_WGP_READ |
34228 | #define RLC_RLCS_WGP_READ__CS_WORK_ACTIVE__SHIFT 0x0 |
34229 | #define RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED__SHIFT 0x1 |
34230 | #define RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED__SHIFT 0x2 |
34231 | #define RLC_RLCS_WGP_READ__RESERVED__SHIFT 0x3 |
34232 | #define RLC_RLCS_WGP_READ__CS_WORK_ACTIVE_MASK 0x00000001L |
34233 | #define RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED_MASK 0x00000002L |
34234 | #define RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED_MASK 0x00000004L |
34235 | #define RLC_RLCS_WGP_READ__RESERVED_MASK 0xFFFFFFF8L |
34236 | //RLC_RLCS_CP_INT_CTRL_1 |
34237 | #define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK__SHIFT 0x0 |
34238 | #define RLC_RLCS_CP_INT_CTRL_1__RESERVED__SHIFT 0x1 |
34239 | #define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK_MASK 0x00000001L |
34240 | #define RLC_RLCS_CP_INT_CTRL_1__RESERVED_MASK 0xFFFFFFFEL |
34241 | //RLC_RLCS_CP_INT_CTRL_2 |
34242 | #define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN__SHIFT 0x0 |
34243 | #define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN__SHIFT 0x1 |
34244 | #define RLC_RLCS_CP_INT_CTRL_2__RESERVED__SHIFT 0x2 |
34245 | #define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN_MASK 0x00000001L |
34246 | #define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN_MASK 0x00000002L |
34247 | #define RLC_RLCS_CP_INT_CTRL_2__RESERVED_MASK 0xFFFFFFFCL |
34248 | //RLC_RLCS_CP_INT_INFO_1 |
34249 | #define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 |
34250 | #define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL |
34251 | //RLC_RLCS_CP_INT_INFO_2 |
34252 | #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 |
34253 | #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 |
34254 | #define RLC_RLCS_CP_INT_INFO_2__RESERVED__SHIFT 0x19 |
34255 | #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL |
34256 | #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID_MASK 0x01FF0000L |
34257 | #define RLC_RLCS_CP_INT_INFO_2__RESERVED_MASK 0xFE000000L |
34258 | //RLC_RLCS_SPM_INT_CTRL |
34259 | #define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK__SHIFT 0x0 |
34260 | #define RLC_RLCS_SPM_INT_CTRL__RESERVED__SHIFT 0x1 |
34261 | #define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK_MASK 0x00000001L |
34262 | #define RLC_RLCS_SPM_INT_CTRL__RESERVED_MASK 0xFFFFFFFEL |
34263 | //RLC_RLCS_SPM_INT_INFO_1 |
34264 | #define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 |
34265 | #define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL |
34266 | //RLC_RLCS_SPM_INT_INFO_2 |
34267 | #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 |
34268 | #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 |
34269 | #define RLC_RLCS_SPM_INT_INFO_2__RESERVED__SHIFT 0x19 |
34270 | #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL |
34271 | #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID_MASK 0x01FF0000L |
34272 | #define RLC_RLCS_SPM_INT_INFO_2__RESERVED_MASK 0xFE000000L |
34273 | //RLC_RLCS_DSM_TRIG |
34274 | #define RLC_RLCS_DSM_TRIG__START__SHIFT 0x0 |
34275 | #define RLC_RLCS_DSM_TRIG__RESERVED__SHIFT 0x1 |
34276 | #define RLC_RLCS_DSM_TRIG__START_MASK 0x00000001L |
34277 | #define RLC_RLCS_DSM_TRIG__RESERVED_MASK 0xFFFFFFFEL |
34278 | //RLC_RLCS_BOOTLOAD_STATUS |
34279 | #define RLC_RLCS_BOOTLOAD_STATUS__RLC_RLCG_IRAM_LOADED__SHIFT 0x0 |
34280 | #define RLC_RLCS_BOOTLOAD_STATUS__RESERVED__SHIFT 0x1 |
34281 | #define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE__SHIFT 0x1f |
34282 | #define RLC_RLCS_BOOTLOAD_STATUS__RLC_RLCG_IRAM_LOADED_MASK 0x00000001L |
34283 | #define RLC_RLCS_BOOTLOAD_STATUS__RESERVED_MASK 0x7FFFFFFEL |
34284 | #define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE_MASK 0x80000000L |
34285 | //RLC_RLCS_POWER_BRAKE_CNTL |
34286 | #define RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE__SHIFT 0x0 |
34287 | #define RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR__SHIFT 0x1 |
34288 | #define RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS__SHIFT 0x2 |
34289 | #define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT__SHIFT 0xa |
34290 | #define RLC_RLCS_POWER_BRAKE_CNTL__RESERVED__SHIFT 0x12 |
34291 | #define RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE_MASK 0x00000001L |
34292 | #define RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR_MASK 0x00000002L |
34293 | #define RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS_MASK 0x000003FCL |
34294 | #define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT_MASK 0x0003FC00L |
34295 | #define RLC_RLCS_POWER_BRAKE_CNTL__RESERVED_MASK 0xFFFC0000L |
34296 | //RLC_RLCS_GENERAL_0 |
34297 | #define RLC_RLCS_GENERAL_0__DATA__SHIFT 0x0 |
34298 | #define RLC_RLCS_GENERAL_0__DATA_MASK 0xFFFFFFFFL |
34299 | //RLC_RLCS_GENERAL_1 |
34300 | #define RLC_RLCS_GENERAL_1__DATA__SHIFT 0x0 |
34301 | #define RLC_RLCS_GENERAL_1__DATA_MASK 0xFFFFFFFFL |
34302 | //RLC_RLCS_GENERAL_2 |
34303 | #define RLC_RLCS_GENERAL_2__DATA__SHIFT 0x0 |
34304 | #define RLC_RLCS_GENERAL_2__DATA_MASK 0xFFFFFFFFL |
34305 | //RLC_RLCS_GENERAL_3 |
34306 | #define RLC_RLCS_GENERAL_3__DATA__SHIFT 0x0 |
34307 | #define RLC_RLCS_GENERAL_3__DATA_MASK 0xFFFFFFFFL |
34308 | //RLC_RLCS_GENERAL_4 |
34309 | #define RLC_RLCS_GENERAL_4__DATA__SHIFT 0x0 |
34310 | #define RLC_RLCS_GENERAL_4__DATA_MASK 0xFFFFFFFFL |
34311 | //RLC_RLCS_GENERAL_5 |
34312 | #define RLC_RLCS_GENERAL_5__DATA__SHIFT 0x0 |
34313 | #define RLC_RLCS_GENERAL_5__DATA_MASK 0xFFFFFFFFL |
34314 | //RLC_RLCS_GRBM_IDLE_BUSY_STAT |
34315 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE__SHIFT 0x0 |
34316 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY__SHIFT 0x10 |
34317 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY__SHIFT 0x11 |
34318 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY__SHIFT 0x12 |
34319 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY__SHIFT 0x13 |
34320 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY__SHIFT 0x14 |
34321 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY__SHIFT 0x15 |
34322 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY__SHIFT 0x16 |
34323 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY__SHIFT 0x17 |
34324 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED__SHIFT 0x18 |
34325 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED__SHIFT 0x19 |
34326 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED__SHIFT 0x1a |
34327 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED__SHIFT 0x1b |
34328 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED__SHIFT 0x1c |
34329 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED__SHIFT 0x1d |
34330 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED__SHIFT 0x1e |
34331 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED__SHIFT 0x1f |
34332 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE_MASK 0x00000003L |
34333 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_MASK 0x00010000L |
34334 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_MASK 0x00020000L |
34335 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_MASK 0x00040000L |
34336 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_MASK 0x00080000L |
34337 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_MASK 0x00100000L |
34338 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_MASK 0x00200000L |
34339 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_MASK 0x00400000L |
34340 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_MASK 0x00800000L |
34341 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED_MASK 0x01000000L |
34342 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED_MASK 0x02000000L |
34343 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED_MASK 0x04000000L |
34344 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED_MASK 0x08000000L |
34345 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED_MASK 0x10000000L |
34346 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED_MASK 0x20000000L |
34347 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED_MASK 0x40000000L |
34348 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED_MASK 0x80000000L |
34349 | //RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL |
34350 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR__SHIFT 0x0 |
34351 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR__SHIFT 0x1 |
34352 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR__SHIFT 0x2 |
34353 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR__SHIFT 0x3 |
34354 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR__SHIFT 0x4 |
34355 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR__SHIFT 0x5 |
34356 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR__SHIFT 0x6 |
34357 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR__SHIFT 0x7 |
34358 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR_MASK 0x00000001L |
34359 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR_MASK 0x00000002L |
34360 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR_MASK 0x00000004L |
34361 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR_MASK 0x00000008L |
34362 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR_MASK 0x00000010L |
34363 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR_MASK 0x00000020L |
34364 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR_MASK 0x00000040L |
34365 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR_MASK 0x00000080L |
34366 | //RLC_RLCS_CMP_IDLE_CNTL |
34367 | #define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR__SHIFT 0x0 |
34368 | #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST__SHIFT 0x1 |
34369 | #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE__SHIFT 0x2 |
34370 | #define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS__SHIFT 0x3 |
34371 | #define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT__SHIFT 0xb |
34372 | #define RLC_RLCS_CMP_IDLE_CNTL__RESERVED__SHIFT 0x13 |
34373 | #define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR_MASK 0x00000001L |
34374 | #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST_MASK 0x00000002L |
34375 | #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_MASK 0x00000004L |
34376 | #define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS_MASK 0x000007F8L |
34377 | #define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT_MASK 0x0007F800L |
34378 | #define RLC_RLCS_CMP_IDLE_CNTL__RESERVED_MASK 0xFFF80000L |
34379 | //RLC_RLCS_POWER_BRAKE_CNTL_TH1 |
34380 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE__SHIFT 0x0 |
34381 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR__SHIFT 0x1 |
34382 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS__SHIFT 0x2 |
34383 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT__SHIFT 0xa |
34384 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED__SHIFT 0x12 |
34385 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE_MASK 0x00000001L |
34386 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR_MASK 0x00000002L |
34387 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS_MASK 0x000003FCL |
34388 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT_MASK 0x0003FC00L |
34389 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED_MASK 0xFFFC0000L |
34390 | //RLC_RLCS_AUXILIARY_REG_1 |
34391 | #define RLC_RLCS_AUXILIARY_REG_1__ADDR__SHIFT 0x0 |
34392 | #define RLC_RLCS_AUXILIARY_REG_1__RESERVED__SHIFT 0x12 |
34393 | #define RLC_RLCS_AUXILIARY_REG_1__ADDR_MASK 0x0003FFFFL |
34394 | #define RLC_RLCS_AUXILIARY_REG_1__RESERVED_MASK 0xFFFC0000L |
34395 | //RLC_RLCS_AUXILIARY_REG_2 |
34396 | #define RLC_RLCS_AUXILIARY_REG_2__ADDR__SHIFT 0x0 |
34397 | #define RLC_RLCS_AUXILIARY_REG_2__RESERVED__SHIFT 0x12 |
34398 | #define RLC_RLCS_AUXILIARY_REG_2__ADDR_MASK 0x0003FFFFL |
34399 | #define RLC_RLCS_AUXILIARY_REG_2__RESERVED_MASK 0xFFFC0000L |
34400 | //RLC_RLCS_AUXILIARY_REG_3 |
34401 | #define RLC_RLCS_AUXILIARY_REG_3__ADDR__SHIFT 0x0 |
34402 | #define RLC_RLCS_AUXILIARY_REG_3__RESERVED__SHIFT 0x12 |
34403 | #define RLC_RLCS_AUXILIARY_REG_3__ADDR_MASK 0x0003FFFFL |
34404 | #define RLC_RLCS_AUXILIARY_REG_3__RESERVED_MASK 0xFFFC0000L |
34405 | //RLC_RLCS_AUXILIARY_REG_4 |
34406 | #define RLC_RLCS_AUXILIARY_REG_4__ADDR__SHIFT 0x0 |
34407 | #define RLC_RLCS_AUXILIARY_REG_4__RESERVED__SHIFT 0x12 |
34408 | #define RLC_RLCS_AUXILIARY_REG_4__ADDR_MASK 0x0003FFFFL |
34409 | #define RLC_RLCS_AUXILIARY_REG_4__RESERVED_MASK 0xFFFC0000L |
34410 | //RLC_RLCS_SPM_SQTT_MODE |
34411 | #define RLC_RLCS_SPM_SQTT_MODE__MODE__SHIFT 0x0 |
34412 | #define RLC_RLCS_SPM_SQTT_MODE__MODE_MASK 0x00000001L |
34413 | //RLC_RLCS_CP_DMA_SRCID_OVER |
34414 | #define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE__SHIFT 0x0 |
34415 | #define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE_MASK 0x00000001L |
34416 | //RLC_RLCS_UTCL2_CNTL |
34417 | #define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0 |
34418 | #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE__SHIFT 0x1 |
34419 | #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE__SHIFT 0x2 |
34420 | #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE__SHIFT 0x3 |
34421 | #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE__SHIFT 0x5 |
34422 | #define RLC_RLCS_UTCL2_CNTL__RESERVED__SHIFT 0x6 |
34423 | #define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L |
34424 | #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_MASK 0x00000002L |
34425 | #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_MASK 0x00000004L |
34426 | #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE_MASK 0x00000018L |
34427 | #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE_MASK 0x00000020L |
34428 | #define RLC_RLCS_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFC0L |
34429 | //RLC_RLCS_MP1_RLC_DOORBELL_CTRL |
34430 | #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__INT_CLEAR__SHIFT 0x0 |
34431 | #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__DOORBELL__SHIFT 0x1 |
34432 | #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__RESERVED__SHIFT 0x2 |
34433 | #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__INT_CLEAR_MASK 0x00000001L |
34434 | #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__DOORBELL_MASK 0x00000002L |
34435 | #define RLC_RLCS_MP1_RLC_DOORBELL_CTRL__RESERVED_MASK 0xFFFFFFFCL |
34436 | //RLC_RLCS_BOOTLOAD_ID_STATUS1 |
34437 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED__SHIFT 0x0 |
34438 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED__SHIFT 0x1 |
34439 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED__SHIFT 0x2 |
34440 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED__SHIFT 0x3 |
34441 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED__SHIFT 0x4 |
34442 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED__SHIFT 0x5 |
34443 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED__SHIFT 0x6 |
34444 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED__SHIFT 0x7 |
34445 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED__SHIFT 0x8 |
34446 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED__SHIFT 0x9 |
34447 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED__SHIFT 0xa |
34448 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED__SHIFT 0xb |
34449 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED__SHIFT 0xc |
34450 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED__SHIFT 0xd |
34451 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED__SHIFT 0xe |
34452 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED__SHIFT 0xf |
34453 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED__SHIFT 0x10 |
34454 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED__SHIFT 0x11 |
34455 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED__SHIFT 0x12 |
34456 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED__SHIFT 0x13 |
34457 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED__SHIFT 0x14 |
34458 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED__SHIFT 0x15 |
34459 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED__SHIFT 0x16 |
34460 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED__SHIFT 0x17 |
34461 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED__SHIFT 0x18 |
34462 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED__SHIFT 0x19 |
34463 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED__SHIFT 0x1a |
34464 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED__SHIFT 0x1b |
34465 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED__SHIFT 0x1c |
34466 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED__SHIFT 0x1d |
34467 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED__SHIFT 0x1e |
34468 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED__SHIFT 0x1f |
34469 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED_MASK 0x00000001L |
34470 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED_MASK 0x00000002L |
34471 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED_MASK 0x00000004L |
34472 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED_MASK 0x00000008L |
34473 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED_MASK 0x00000010L |
34474 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED_MASK 0x00000020L |
34475 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED_MASK 0x00000040L |
34476 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED_MASK 0x00000080L |
34477 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED_MASK 0x00000100L |
34478 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED_MASK 0x00000200L |
34479 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED_MASK 0x00000400L |
34480 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED_MASK 0x00000800L |
34481 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED_MASK 0x00001000L |
34482 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED_MASK 0x00002000L |
34483 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED_MASK 0x00004000L |
34484 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED_MASK 0x00008000L |
34485 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED_MASK 0x00010000L |
34486 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED_MASK 0x00020000L |
34487 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED_MASK 0x00040000L |
34488 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED_MASK 0x00080000L |
34489 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED_MASK 0x00100000L |
34490 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED_MASK 0x00200000L |
34491 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED_MASK 0x00400000L |
34492 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED_MASK 0x00800000L |
34493 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED_MASK 0x01000000L |
34494 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED_MASK 0x02000000L |
34495 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED_MASK 0x04000000L |
34496 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED_MASK 0x08000000L |
34497 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED_MASK 0x10000000L |
34498 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED_MASK 0x20000000L |
34499 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED_MASK 0x40000000L |
34500 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED_MASK 0x80000000L |
34501 | //RLC_RLCS_BOOTLOAD_ID_STATUS2 |
34502 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED__SHIFT 0x0 |
34503 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED__SHIFT 0x1 |
34504 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED__SHIFT 0x2 |
34505 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED__SHIFT 0x3 |
34506 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED__SHIFT 0x4 |
34507 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED__SHIFT 0x5 |
34508 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED__SHIFT 0x6 |
34509 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED__SHIFT 0x7 |
34510 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED__SHIFT 0x8 |
34511 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED__SHIFT 0x9 |
34512 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED__SHIFT 0xa |
34513 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED__SHIFT 0xb |
34514 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED__SHIFT 0xc |
34515 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED__SHIFT 0xd |
34516 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED__SHIFT 0xe |
34517 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED__SHIFT 0xf |
34518 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED__SHIFT 0x10 |
34519 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED__SHIFT 0x11 |
34520 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED__SHIFT 0x12 |
34521 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED__SHIFT 0x13 |
34522 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED__SHIFT 0x14 |
34523 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED__SHIFT 0x15 |
34524 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED__SHIFT 0x16 |
34525 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED__SHIFT 0x17 |
34526 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED__SHIFT 0x18 |
34527 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED__SHIFT 0x19 |
34528 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED__SHIFT 0x1a |
34529 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED__SHIFT 0x1b |
34530 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED__SHIFT 0x1c |
34531 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED__SHIFT 0x1d |
34532 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED__SHIFT 0x1e |
34533 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED__SHIFT 0x1f |
34534 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED_MASK 0x00000001L |
34535 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED_MASK 0x00000002L |
34536 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED_MASK 0x00000004L |
34537 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED_MASK 0x00000008L |
34538 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED_MASK 0x00000010L |
34539 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED_MASK 0x00000020L |
34540 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED_MASK 0x00000040L |
34541 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED_MASK 0x00000080L |
34542 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED_MASK 0x00000100L |
34543 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED_MASK 0x00000200L |
34544 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED_MASK 0x00000400L |
34545 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED_MASK 0x00000800L |
34546 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED_MASK 0x00001000L |
34547 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED_MASK 0x00002000L |
34548 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED_MASK 0x00004000L |
34549 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED_MASK 0x00008000L |
34550 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED_MASK 0x00010000L |
34551 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED_MASK 0x00020000L |
34552 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED_MASK 0x00040000L |
34553 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED_MASK 0x00080000L |
34554 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED_MASK 0x00100000L |
34555 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED_MASK 0x00200000L |
34556 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED_MASK 0x00400000L |
34557 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED_MASK 0x00800000L |
34558 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED_MASK 0x01000000L |
34559 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED_MASK 0x02000000L |
34560 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED_MASK 0x04000000L |
34561 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED_MASK 0x08000000L |
34562 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED_MASK 0x10000000L |
34563 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED_MASK 0x20000000L |
34564 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED_MASK 0x40000000L |
34565 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED_MASK 0x80000000L |
34566 | //RLC_RLCS_SMUIO_VIDCHG_CTRL |
34567 | #define RLC_RLCS_SMUIO_VIDCHG_CTRL__REQ__SHIFT 0x0 |
34568 | #define RLC_RLCS_SMUIO_VIDCHG_CTRL__DATA__SHIFT 0x1 |
34569 | #define RLC_RLCS_SMUIO_VIDCHG_CTRL__PSIEN__SHIFT 0xa |
34570 | #define RLC_RLCS_SMUIO_VIDCHG_CTRL__ACK__SHIFT 0xb |
34571 | #define RLC_RLCS_SMUIO_VIDCHG_CTRL__REQ_MASK 0x00000001L |
34572 | #define RLC_RLCS_SMUIO_VIDCHG_CTRL__DATA_MASK 0x000003FEL |
34573 | #define RLC_RLCS_SMUIO_VIDCHG_CTRL__PSIEN_MASK 0x00000400L |
34574 | #define RLC_RLCS_SMUIO_VIDCHG_CTRL__ACK_MASK 0x00000800L |
34575 | //RLC_RLCS_EDC_INT_CNTL |
34576 | #define RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR__SHIFT 0x0 |
34577 | #define RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR_MASK 0x00000001L |
34578 | //RLC_RLCS_KMD_LOG_CNTL1 |
34579 | #define RLC_RLCS_KMD_LOG_CNTL1__DATA__SHIFT 0x0 |
34580 | #define RLC_RLCS_KMD_LOG_CNTL1__DATA_MASK 0xFFFFFFFFL |
34581 | //RLC_RLCS_KMD_LOG_CNTL2 |
34582 | #define RLC_RLCS_KMD_LOG_CNTL2__DATA__SHIFT 0x0 |
34583 | #define RLC_RLCS_KMD_LOG_CNTL2__DATA_MASK 0xFFFFFFFFL |
34584 | //RLC_RLCS_GPM_LEGACY_INT_STAT |
34585 | #define RLC_RLCS_GPM_LEGACY_INT_STAT__GC_CAC_EDC_EVENT_CHANGED__SHIFT 0x0 |
34586 | #define RLC_RLCS_GPM_LEGACY_INT_STAT__GFX_POWER_BRAKE_CHANGED__SHIFT 0x1 |
34587 | #define RLC_RLCS_GPM_LEGACY_INT_STAT__GC_CAC_EDC_EVENT_CHANGED_MASK 0x00000001L |
34588 | #define RLC_RLCS_GPM_LEGACY_INT_STAT__GFX_POWER_BRAKE_CHANGED_MASK 0x00000002L |
34589 | //RLC_RLCS_GPM_LEGACY_INT_DISABLE |
34590 | #define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GC_CAC_EDC_EVENT_CHANGED__SHIFT 0x0 |
34591 | #define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GFX_POWER_BRAKE_CHANGED__SHIFT 0x1 |
34592 | #define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GC_CAC_EDC_EVENT_CHANGED_MASK 0x00000001L |
34593 | #define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GFX_POWER_BRAKE_CHANGED_MASK 0x00000002L |
34594 | //RLC_RLCS_SRM_SRCID_CNTL |
34595 | #define RLC_RLCS_SRM_SRCID_CNTL__SRCID__SHIFT 0x0 |
34596 | #define RLC_RLCS_SRM_SRCID_CNTL__SRCID_MASK 0x00000007L |
34597 | //RLC_RLCS_PERFMON_CLK_CNTL_UCODE |
34598 | #define RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT 0x0 |
34599 | #define RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK 0x00000001L |
34600 | //RLC_RLCS_DEC_END |
34601 | |
34602 | |
34603 | // addressBlock: gc_pwrdec |
34604 | //CGTS_RD_CTRL_REG |
34605 | #define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 |
34606 | #define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x4 |
34607 | #define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000000FL |
34608 | #define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x000000F0L |
34609 | //CGTS_RD_REG |
34610 | #define CGTS_RD_REG__READ_DATA__SHIFT 0x0 |
34611 | #define CGTS_RD_REG__READ_DATA_MASK 0xFFFFFFFFL |
34612 | //CGTS_TCC_DISABLE |
34613 | #define CGTS_TCC_DISABLE__HI_TCC_DISABLE__SHIFT 0x8 |
34614 | #define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 |
34615 | #define CGTS_TCC_DISABLE__HI_TCC_DISABLE_MASK 0x0000FF00L |
34616 | #define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L |
34617 | //CGTS_USER_TCC_DISABLE |
34618 | #define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE__SHIFT 0x8 |
34619 | #define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 |
34620 | #define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE_MASK 0x0000FF00L |
34621 | #define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L |
34622 | //CGTS_STATUS_REG |
34623 | #define CGTS_STATUS_REG__SA0_QUAD0_MGCG_ENABLED__SHIFT 0x0 |
34624 | #define CGTS_STATUS_REG__SA0_QUAD0_CG_STATUS__SHIFT 0x1 |
34625 | #define CGTS_STATUS_REG__SA1_QUAD0_MGCG_ENABLED__SHIFT 0x8 |
34626 | #define CGTS_STATUS_REG__SA1_QUAD0_CG_STATUS__SHIFT 0x9 |
34627 | #define CGTS_STATUS_REG__SA0_QUAD0_MGCG_ENABLED_MASK 0x00000001L |
34628 | #define CGTS_STATUS_REG__SA0_QUAD0_CG_STATUS_MASK 0x00000006L |
34629 | #define CGTS_STATUS_REG__SA1_QUAD0_MGCG_ENABLED_MASK 0x00000100L |
34630 | #define CGTS_STATUS_REG__SA1_QUAD0_CG_STATUS_MASK 0x00000600L |
34631 | //CGTT_SPI_CGTSSM_CLK_CTRL |
34632 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b |
34633 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c |
34634 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d |
34635 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e |
34636 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L |
34637 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L |
34638 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L |
34639 | #define CGTT_SPI_CGTSSM_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L |
34640 | //CGTT_SPI_PS_CLK_CTRL |
34641 | #define CGTT_SPI_PS_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
34642 | #define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
34643 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 |
34644 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 |
34645 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 |
34646 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 |
34647 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
34648 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
34649 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
34650 | #define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 |
34651 | #define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 |
34652 | #define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a |
34653 | #define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b |
34654 | #define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c |
34655 | #define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d |
34656 | #define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e |
34657 | #define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
34658 | #define CGTT_SPI_PS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
34659 | #define CGTT_SPI_PS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
34660 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L |
34661 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L |
34662 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L |
34663 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L |
34664 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
34665 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
34666 | #define CGTT_SPI_PS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
34667 | #define CGTT_SPI_PS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L |
34668 | #define CGTT_SPI_PS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L |
34669 | #define CGTT_SPI_PS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L |
34670 | #define CGTT_SPI_PS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L |
34671 | #define CGTT_SPI_PS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L |
34672 | #define CGTT_SPI_PS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L |
34673 | #define CGTT_SPI_PS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L |
34674 | #define CGTT_SPI_PS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
34675 | //CGTT_SPIS_CLK_CTRL |
34676 | #define CGTT_SPIS_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
34677 | #define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
34678 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 |
34679 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 |
34680 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 |
34681 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 |
34682 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
34683 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
34684 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
34685 | #define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 |
34686 | #define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 |
34687 | #define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a |
34688 | #define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b |
34689 | #define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c |
34690 | #define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d |
34691 | #define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e |
34692 | #define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
34693 | #define CGTT_SPIS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
34694 | #define CGTT_SPIS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
34695 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L |
34696 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L |
34697 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L |
34698 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L |
34699 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
34700 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
34701 | #define CGTT_SPIS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
34702 | #define CGTT_SPIS_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L |
34703 | #define CGTT_SPIS_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L |
34704 | #define CGTT_SPIS_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L |
34705 | #define CGTT_SPIS_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L |
34706 | #define CGTT_SPIS_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L |
34707 | #define CGTT_SPIS_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L |
34708 | #define CGTT_SPIS_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L |
34709 | #define CGTT_SPIS_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
34710 | //CGTT_SPI_CLK_CTRL |
34711 | #define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
34712 | #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
34713 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 |
34714 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 |
34715 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 |
34716 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 |
34717 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
34718 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
34719 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
34720 | #define CGTT_SPI_CLK_CTRL__GRP6_OVERRIDE__SHIFT 0x18 |
34721 | #define CGTT_SPI_CLK_CTRL__GRP5_OVERRIDE__SHIFT 0x19 |
34722 | #define CGTT_SPI_CLK_CTRL__GRP4_OVERRIDE__SHIFT 0x1a |
34723 | #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b |
34724 | #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c |
34725 | #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d |
34726 | #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e |
34727 | #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
34728 | #define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
34729 | #define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
34730 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L |
34731 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L |
34732 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L |
34733 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L |
34734 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
34735 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
34736 | #define CGTT_SPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
34737 | #define CGTT_SPI_CLK_CTRL__GRP6_OVERRIDE_MASK 0x01000000L |
34738 | #define CGTT_SPI_CLK_CTRL__GRP5_OVERRIDE_MASK 0x02000000L |
34739 | #define CGTT_SPI_CLK_CTRL__GRP4_OVERRIDE_MASK 0x04000000L |
34740 | #define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L |
34741 | #define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L |
34742 | #define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L |
34743 | #define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L |
34744 | #define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
34745 | //CGTT_PC_CLK_CTRL |
34746 | #define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
34747 | #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
34748 | #define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE__SHIFT 0x11 |
34749 | #define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0xd |
34750 | #define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0xe |
34751 | #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b |
34752 | #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c |
34753 | #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d |
34754 | #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e |
34755 | #define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
34756 | #define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
34757 | #define CGTT_PC_CLK_CTRL__PC_RAM_FGCG_OVERRIDE_MASK 0x00020000L |
34758 | #define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x00002000L |
34759 | #define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x00004000L |
34760 | #define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L |
34761 | #define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L |
34762 | #define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L |
34763 | #define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L |
34764 | //CGTT_BCI_CLK_CTRL |
34765 | #define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
34766 | #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
34767 | #define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc |
34768 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
34769 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
34770 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
34771 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
34772 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
34773 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
34774 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
34775 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
34776 | #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 |
34777 | #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 |
34778 | #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a |
34779 | #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b |
34780 | #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c |
34781 | #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d |
34782 | #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e |
34783 | #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
34784 | #define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
34785 | #define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
34786 | #define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L |
34787 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
34788 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
34789 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
34790 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
34791 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
34792 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
34793 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
34794 | #define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
34795 | #define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L |
34796 | #define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L |
34797 | #define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L |
34798 | #define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L |
34799 | #define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L |
34800 | #define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L |
34801 | #define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L |
34802 | #define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
34803 | //CGTT_VGT_CLK_CTRL |
34804 | #define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
34805 | #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
34806 | #define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf |
34807 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
34808 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
34809 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
34810 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
34811 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
34812 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
34813 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
34814 | #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c |
34815 | #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d |
34816 | #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
34817 | #define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
34818 | #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
34819 | #define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L |
34820 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
34821 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
34822 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
34823 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
34824 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
34825 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
34826 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
34827 | #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L |
34828 | #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L |
34829 | #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
34830 | //CGTT_IA_CLK_CTRL |
34831 | #define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
34832 | #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
34833 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
34834 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
34835 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
34836 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
34837 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
34838 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
34839 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
34840 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
34841 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
34842 | #define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 |
34843 | #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e |
34844 | #define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
34845 | #define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
34846 | #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
34847 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
34848 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
34849 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
34850 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
34851 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
34852 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
34853 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
34854 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
34855 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
34856 | #define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L |
34857 | #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L |
34858 | #define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
34859 | //CGTT_WD_CLK_CTRL |
34860 | #define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
34861 | #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
34862 | #define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf |
34863 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
34864 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
34865 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
34866 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
34867 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
34868 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
34869 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
34870 | #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
34871 | #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d |
34872 | #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e |
34873 | #define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
34874 | #define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
34875 | #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
34876 | #define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L |
34877 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
34878 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
34879 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
34880 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
34881 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
34882 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
34883 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
34884 | #define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
34885 | #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L |
34886 | #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L |
34887 | #define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
34888 | //CGTT_GS_NGG_CLK_CTRL |
34889 | #define CGTT_GS_NGG_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
34890 | #define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
34891 | #define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE__SHIFT 0xf |
34892 | #define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 |
34893 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
34894 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
34895 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
34896 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
34897 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
34898 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
34899 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
34900 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
34901 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
34902 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
34903 | #define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1c |
34904 | #define CGTT_GS_NGG_CLK_CTRL__GS1_OVERRIDE__SHIFT 0x1d |
34905 | #define CGTT_GS_NGG_CLK_CTRL__GS0_OVERRIDE__SHIFT 0x1e |
34906 | #define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
34907 | #define CGTT_GS_NGG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
34908 | #define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
34909 | #define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L |
34910 | #define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L |
34911 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
34912 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
34913 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
34914 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
34915 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
34916 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
34917 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
34918 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
34919 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
34920 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
34921 | #define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x10000000L |
34922 | #define CGTT_GS_NGG_CLK_CTRL__GS1_OVERRIDE_MASK 0x20000000L |
34923 | #define CGTT_GS_NGG_CLK_CTRL__GS0_OVERRIDE_MASK 0x40000000L |
34924 | #define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
34925 | //CGTT_PA_CLK_CTRL |
34926 | #define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
34927 | #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
34928 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
34929 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
34930 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
34931 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
34932 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
34933 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
34934 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
34935 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
34936 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
34937 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
34938 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
34939 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
34940 | #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d |
34941 | #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e |
34942 | #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f |
34943 | #define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
34944 | #define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
34945 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
34946 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
34947 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
34948 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
34949 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
34950 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
34951 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
34952 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
34953 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
34954 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
34955 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
34956 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
34957 | #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L |
34958 | #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L |
34959 | #define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L |
34960 | //CGTT_SC_CLK_CTRL0 |
34961 | #define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0 |
34962 | #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 |
34963 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10 |
34964 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11 |
34965 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12 |
34966 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13 |
34967 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
34968 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
34969 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
34970 | #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17 |
34971 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18 |
34972 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19 |
34973 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a |
34974 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b |
34975 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c |
34976 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d |
34977 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e |
34978 | #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f |
34979 | #define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL |
34980 | #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L |
34981 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L |
34982 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L |
34983 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L |
34984 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L |
34985 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
34986 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
34987 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
34988 | #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L |
34989 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L |
34990 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L |
34991 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L |
34992 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L |
34993 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L |
34994 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L |
34995 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L |
34996 | #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L |
34997 | //CGTT_SC_CLK_CTRL1 |
34998 | #define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0 |
34999 | #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 |
35000 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0__SHIFT 0x10 |
35001 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11 |
35002 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12 |
35003 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13 |
35004 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14 |
35005 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15 |
35006 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16 |
35007 | #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE__SHIFT 0x17 |
35008 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0__SHIFT 0x18 |
35009 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19 |
35010 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a |
35011 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b |
35012 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c |
35013 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d |
35014 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e |
35015 | #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE__SHIFT 0x1f |
35016 | #define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL |
35017 | #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L |
35018 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0_MASK 0x00010000L |
35019 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L |
35020 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L |
35021 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L |
35022 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L |
35023 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L |
35024 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L |
35025 | #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE_MASK 0x00800000L |
35026 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0_MASK 0x01000000L |
35027 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L |
35028 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L |
35029 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L |
35030 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L |
35031 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L |
35032 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L |
35033 | #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE_MASK 0x80000000L |
35034 | //CGTT_SC_CLK_CTRL2 |
35035 | #define CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT 0x0 |
35036 | #define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 |
35037 | #define CGTT_SC_CLK_CTRL2__DBR_CLK_OVERRIDE__SHIFT 0x1a |
35038 | #define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT 0x1b |
35039 | #define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT 0x1c |
35040 | #define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT 0x1d |
35041 | #define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT 0x1e |
35042 | #define CGTT_SC_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL |
35043 | #define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L |
35044 | #define CGTT_SC_CLK_CTRL2__DBR_CLK_OVERRIDE_MASK 0x04000000L |
35045 | #define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK 0x08000000L |
35046 | #define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK 0x10000000L |
35047 | #define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK 0x20000000L |
35048 | #define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK 0x40000000L |
35049 | //CGTT_SQ_CLK_CTRL |
35050 | #define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
35051 | #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35052 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35053 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35054 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35055 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35056 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35057 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35058 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35059 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35060 | #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e |
35061 | #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
35062 | #define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35063 | #define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35064 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35065 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35066 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35067 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35068 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35069 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35070 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35071 | #define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35072 | #define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L |
35073 | #define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
35074 | //CGTT_SQG_CLK_CTRL |
35075 | #define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
35076 | #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35077 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35078 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35079 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35080 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35081 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35082 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35083 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35084 | #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c |
35085 | #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d |
35086 | #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e |
35087 | #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
35088 | #define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35089 | #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35090 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35091 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35092 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35093 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35094 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35095 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35096 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35097 | #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L |
35098 | #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L |
35099 | #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L |
35100 | #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
35101 | //SQ_ALU_CLK_CTRL |
35102 | #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 |
35103 | #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 |
35104 | #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL |
35105 | #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L |
35106 | //SQ_TEX_CLK_CTRL |
35107 | #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 |
35108 | #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 |
35109 | #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL |
35110 | #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L |
35111 | //SQ_LDS_CLK_CTRL |
35112 | #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 |
35113 | #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 |
35114 | #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL |
35115 | #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L |
35116 | //CGTT_SX_CLK_CTRL0 |
35117 | #define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 |
35118 | #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 |
35119 | #define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc |
35120 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35121 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35122 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35123 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35124 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35125 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35126 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35127 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35128 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 |
35129 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 |
35130 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a |
35131 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b |
35132 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c |
35133 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d |
35134 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e |
35135 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f |
35136 | #define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL |
35137 | #define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L |
35138 | #define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L |
35139 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35140 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35141 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35142 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35143 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35144 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35145 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35146 | #define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35147 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L |
35148 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L |
35149 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L |
35150 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L |
35151 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L |
35152 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L |
35153 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L |
35154 | #define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L |
35155 | //CGTT_SX_CLK_CTRL1 |
35156 | #define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 |
35157 | #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 |
35158 | #define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc |
35159 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35160 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35161 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35162 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35163 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35164 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35165 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35166 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35167 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 |
35168 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a |
35169 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b |
35170 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c |
35171 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d |
35172 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e |
35173 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f |
35174 | #define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL |
35175 | #define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L |
35176 | #define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L |
35177 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35178 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35179 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35180 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35181 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35182 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35183 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35184 | #define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35185 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L |
35186 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L |
35187 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L |
35188 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L |
35189 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L |
35190 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L |
35191 | #define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L |
35192 | //CGTT_SX_CLK_CTRL2 |
35193 | #define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 |
35194 | #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 |
35195 | #define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd |
35196 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35197 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35198 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35199 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35200 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35201 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35202 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35203 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35204 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 |
35205 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a |
35206 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b |
35207 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c |
35208 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d |
35209 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e |
35210 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f |
35211 | #define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL |
35212 | #define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L |
35213 | #define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L |
35214 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35215 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35216 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35217 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35218 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35219 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35220 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35221 | #define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35222 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L |
35223 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L |
35224 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L |
35225 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L |
35226 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L |
35227 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L |
35228 | #define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L |
35229 | //CGTT_SX_CLK_CTRL3 |
35230 | #define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 |
35231 | #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 |
35232 | #define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd |
35233 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35234 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35235 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35236 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35237 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35238 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35239 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35240 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35241 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 |
35242 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a |
35243 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b |
35244 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c |
35245 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d |
35246 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e |
35247 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f |
35248 | #define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL |
35249 | #define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L |
35250 | #define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L |
35251 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35252 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35253 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35254 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35255 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35256 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35257 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35258 | #define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35259 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L |
35260 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L |
35261 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L |
35262 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L |
35263 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L |
35264 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L |
35265 | #define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L |
35266 | //CGTT_SX_CLK_CTRL4 |
35267 | #define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 |
35268 | #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 |
35269 | #define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc |
35270 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35271 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35272 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35273 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35274 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35275 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35276 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35277 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35278 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 |
35279 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a |
35280 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b |
35281 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c |
35282 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d |
35283 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e |
35284 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f |
35285 | #define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL |
35286 | #define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L |
35287 | #define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L |
35288 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35289 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35290 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35291 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35292 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35293 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35294 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35295 | #define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35296 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L |
35297 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L |
35298 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L |
35299 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L |
35300 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L |
35301 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L |
35302 | #define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L |
35303 | //TD_CGTT_CTRL |
35304 | #define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 |
35305 | #define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35306 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35307 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35308 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35309 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35310 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35311 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35312 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35313 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35314 | #define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
35315 | #define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
35316 | #define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
35317 | #define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
35318 | #define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
35319 | #define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
35320 | #define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
35321 | #define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
35322 | #define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL |
35323 | #define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35324 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35325 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35326 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35327 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35328 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35329 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35330 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35331 | #define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35332 | #define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
35333 | #define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
35334 | #define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
35335 | #define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
35336 | #define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
35337 | #define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
35338 | #define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
35339 | #define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
35340 | //TA_CGTT_CTRL |
35341 | #define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 |
35342 | #define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35343 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35344 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35345 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35346 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35347 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35348 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35349 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35350 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35351 | #define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
35352 | #define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
35353 | #define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
35354 | #define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
35355 | #define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
35356 | #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
35357 | #define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
35358 | #define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
35359 | #define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL |
35360 | #define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35361 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35362 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35363 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35364 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35365 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35366 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35367 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35368 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35369 | #define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
35370 | #define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
35371 | #define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
35372 | #define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
35373 | #define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
35374 | #define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
35375 | #define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
35376 | #define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
35377 | //CGTT_TCPI_CLK_CTRL |
35378 | #define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
35379 | #define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35380 | #define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0xc |
35381 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0xf |
35382 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 |
35383 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 |
35384 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 |
35385 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 |
35386 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
35387 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
35388 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
35389 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x17 |
35390 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x18 |
35391 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x19 |
35392 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1a |
35393 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1b |
35394 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1c |
35395 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1d |
35396 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1e |
35397 | #define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35398 | #define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35399 | #define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x00007000L |
35400 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00008000L |
35401 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L |
35402 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L |
35403 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L |
35404 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L |
35405 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
35406 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
35407 | #define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
35408 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x00800000L |
35409 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x01000000L |
35410 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x02000000L |
35411 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x04000000L |
35412 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x08000000L |
35413 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x10000000L |
35414 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x20000000L |
35415 | #define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x40000000L |
35416 | //CGTT_GDS_CLK_CTRL |
35417 | #define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
35418 | #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35419 | #define CGTT_GDS_CLK_CTRL__UNUSED__SHIFT 0xc |
35420 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35421 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35422 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35423 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35424 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35425 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35426 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35427 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35428 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
35429 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
35430 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
35431 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
35432 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
35433 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
35434 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
35435 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
35436 | #define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35437 | #define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35438 | #define CGTT_GDS_CLK_CTRL__UNUSED_MASK 0x0000F000L |
35439 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35440 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35441 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35442 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35443 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35444 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35445 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35446 | #define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35447 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
35448 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
35449 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
35450 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
35451 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
35452 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
35453 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
35454 | #define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
35455 | //DB_CGTT_CLK_CTRL_0 |
35456 | #define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 |
35457 | #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 |
35458 | #define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc |
35459 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35460 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35461 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35462 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35463 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35464 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35465 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35466 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35467 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 |
35468 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 |
35469 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a |
35470 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b |
35471 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c |
35472 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d |
35473 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e |
35474 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f |
35475 | #define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL |
35476 | #define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L |
35477 | #define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L |
35478 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35479 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35480 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35481 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35482 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35483 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35484 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35485 | #define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35486 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L |
35487 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L |
35488 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L |
35489 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L |
35490 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L |
35491 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L |
35492 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L |
35493 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L |
35494 | //CB_CGTT_SCLK_CTRL |
35495 | #define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 |
35496 | #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35497 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35498 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35499 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35500 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35501 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35502 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35503 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35504 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35505 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
35506 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
35507 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
35508 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
35509 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
35510 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
35511 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
35512 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
35513 | #define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35514 | #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35515 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35516 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35517 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35518 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35519 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35520 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35521 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35522 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35523 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
35524 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
35525 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
35526 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
35527 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
35528 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
35529 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
35530 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
35531 | //GL2C_CGTT_SCLK_CTRL |
35532 | #define GL2C_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 |
35533 | #define GL2C_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35534 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35535 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35536 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35537 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35538 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35539 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35540 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35541 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35542 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
35543 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
35544 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
35545 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
35546 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
35547 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
35548 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
35549 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
35550 | #define GL2C_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35551 | #define GL2C_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35552 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35553 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35554 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35555 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35556 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35557 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35558 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35559 | #define GL2C_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35560 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
35561 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
35562 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
35563 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
35564 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
35565 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
35566 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
35567 | #define GL2C_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
35568 | //GL2A_CGTT_SCLK_CTRL |
35569 | #define GL2A_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 |
35570 | #define GL2A_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35571 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35572 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35573 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35574 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35575 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35576 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35577 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35578 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35579 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
35580 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
35581 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
35582 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
35583 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
35584 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
35585 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
35586 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
35587 | #define GL2A_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35588 | #define GL2A_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35589 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35590 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35591 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35592 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35593 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35594 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35595 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35596 | #define GL2A_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35597 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
35598 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
35599 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
35600 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
35601 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
35602 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
35603 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
35604 | #define GL2A_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
35605 | //GL2A_CGTT_SCLK_CTRL_1 |
35606 | #define GL2A_CGTT_SCLK_CTRL_1__ON_DELAY__SHIFT 0x0 |
35607 | #define GL2A_CGTT_SCLK_CTRL_1__OFF_HYSTERESIS__SHIFT 0x4 |
35608 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35609 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35610 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35611 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35612 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35613 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35614 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35615 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35616 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE7__SHIFT 0x18 |
35617 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE6__SHIFT 0x19 |
35618 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE5__SHIFT 0x1a |
35619 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE4__SHIFT 0x1b |
35620 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE3__SHIFT 0x1c |
35621 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE2__SHIFT 0x1d |
35622 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE1__SHIFT 0x1e |
35623 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE0__SHIFT 0x1f |
35624 | #define GL2A_CGTT_SCLK_CTRL_1__ON_DELAY_MASK 0x0000000FL |
35625 | #define GL2A_CGTT_SCLK_CTRL_1__OFF_HYSTERESIS_MASK 0x00000FF0L |
35626 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35627 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35628 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35629 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35630 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35631 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35632 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35633 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35634 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE7_MASK 0x01000000L |
35635 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE6_MASK 0x02000000L |
35636 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE5_MASK 0x04000000L |
35637 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE4_MASK 0x08000000L |
35638 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE3_MASK 0x10000000L |
35639 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE2_MASK 0x20000000L |
35640 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE1_MASK 0x40000000L |
35641 | #define GL2A_CGTT_SCLK_CTRL_1__SOFT_OVERRIDE0_MASK 0x80000000L |
35642 | //CGTT_CP_CLK_CTRL |
35643 | #define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
35644 | #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35645 | #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
35646 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35647 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35648 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35649 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35650 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35651 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35652 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35653 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35654 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d |
35655 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
35656 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
35657 | #define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35658 | #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35659 | #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
35660 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35661 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35662 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35663 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35664 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35665 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35666 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35667 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35668 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L |
35669 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
35670 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
35671 | //CGTT_CPF_CLK_CTRL |
35672 | #define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
35673 | #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35674 | #define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
35675 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35676 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35677 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35678 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35679 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35680 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35681 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35682 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35683 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1a |
35684 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT__SHIFT 0x1b |
35685 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP__SHIFT 0x1c |
35686 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX__SHIFT 0x1d |
35687 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
35688 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
35689 | #define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35690 | #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35691 | #define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
35692 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35693 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35694 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35695 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35696 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35697 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35698 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35699 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35700 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x04000000L |
35701 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT_MASK 0x08000000L |
35702 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP_MASK 0x10000000L |
35703 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX_MASK 0x20000000L |
35704 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
35705 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
35706 | //CGTT_CPC_CLK_CTRL |
35707 | #define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
35708 | #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35709 | #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
35710 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35711 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35712 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35713 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35714 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35715 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35716 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35717 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35718 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d |
35719 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
35720 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
35721 | #define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35722 | #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35723 | #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
35724 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35725 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35726 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35727 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35728 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35729 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35730 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35731 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35732 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L |
35733 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
35734 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
35735 | //CGTT_RLC_CLK_CTRL |
35736 | #define CGTT_RLC_CLK_CTRL__RESERVED__SHIFT 0x0 |
35737 | #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35738 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35739 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35740 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35741 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35742 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35743 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35744 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35745 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35746 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
35747 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
35748 | #define CGTT_RLC_CLK_CTRL__RESERVED_MASK 0x0000000FL |
35749 | #define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35750 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35751 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35752 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35753 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35754 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35755 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35756 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35757 | #define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35758 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
35759 | #define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
35760 | //RLC_GFX_RM_CNTL |
35761 | #define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0 |
35762 | #define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1 |
35763 | #define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L |
35764 | #define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL |
35765 | //RMI_CGTT_SCLK_CTRL |
35766 | #define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 |
35767 | #define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35768 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35769 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35770 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35771 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35772 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35773 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35774 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35775 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35776 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
35777 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
35778 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
35779 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
35780 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
35781 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
35782 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
35783 | #define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35784 | #define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35785 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35786 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35787 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35788 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35789 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35790 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35791 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35792 | #define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35793 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
35794 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
35795 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
35796 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
35797 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
35798 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
35799 | #define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
35800 | //CGTT_TCPF_CLK_CTRL |
35801 | #define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
35802 | #define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35803 | #define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0xc |
35804 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0xf |
35805 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x10 |
35806 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x11 |
35807 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x12 |
35808 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x13 |
35809 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
35810 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
35811 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
35812 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x17 |
35813 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x18 |
35814 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x19 |
35815 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1a |
35816 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1b |
35817 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1c |
35818 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1d |
35819 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1e |
35820 | #define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35821 | #define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35822 | #define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x00007000L |
35823 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00008000L |
35824 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00010000L |
35825 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00020000L |
35826 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00040000L |
35827 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00080000L |
35828 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
35829 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
35830 | #define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
35831 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x00800000L |
35832 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x01000000L |
35833 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x02000000L |
35834 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x04000000L |
35835 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x08000000L |
35836 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x10000000L |
35837 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x20000000L |
35838 | #define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x40000000L |
35839 | //GCR_CGTT_SCLK_CTRL |
35840 | #define GCR_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 |
35841 | #define GCR_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35842 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35843 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35844 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35845 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35846 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35847 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35848 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35849 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35850 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
35851 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
35852 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
35853 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
35854 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
35855 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
35856 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
35857 | #define GCR_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35858 | #define GCR_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35859 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35860 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35861 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35862 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35863 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35864 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35865 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35866 | #define GCR_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35867 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
35868 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
35869 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
35870 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
35871 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
35872 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
35873 | #define GCR_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
35874 | //UTCL1_CGTT_CLK_CTRL |
35875 | #define UTCL1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
35876 | #define UTCL1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35877 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35878 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35879 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35880 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35881 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35882 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35883 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35884 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35885 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
35886 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
35887 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
35888 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
35889 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
35890 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
35891 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
35892 | #define UTCL1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35893 | #define UTCL1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35894 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35895 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35896 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35897 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35898 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35899 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35900 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35901 | #define UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35902 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
35903 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
35904 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
35905 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
35906 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
35907 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
35908 | #define UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
35909 | //GCEA_CGTT_CLK_CTRL |
35910 | #define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
35911 | #define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35912 | #define GCEA_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc |
35913 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 |
35914 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 |
35915 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 |
35916 | #define GCEA_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 |
35917 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c |
35918 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d |
35919 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e |
35920 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f |
35921 | #define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35922 | #define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35923 | #define GCEA_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L |
35924 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L |
35925 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L |
35926 | #define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L |
35927 | #define GCEA_CGTT_CLK_CTRL__SPARE1_MASK 0x0F800000L |
35928 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L |
35929 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L |
35930 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L |
35931 | #define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L |
35932 | //SE_CAC_CGTT_CLK_CTRL |
35933 | #define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
35934 | #define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35935 | #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
35936 | #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
35937 | #define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35938 | #define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35939 | #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
35940 | #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
35941 | //GC_CAC_CGTT_CLK_CTRL |
35942 | #define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
35943 | #define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35944 | #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
35945 | #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
35946 | #define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35947 | #define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35948 | #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
35949 | #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
35950 | //GRBM_CGTT_CLK_CNTL |
35951 | #define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0 |
35952 | #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4 |
35953 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
35954 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
35955 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
35956 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
35957 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
35958 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
35959 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
35960 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
35961 | #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
35962 | #define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL |
35963 | #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35964 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
35965 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
35966 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
35967 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
35968 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
35969 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
35970 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
35971 | #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
35972 | #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
35973 | //GUS_CGTT_CLK_CTRL |
35974 | #define GUS_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
35975 | #define GUS_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
35976 | #define GUS_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc |
35977 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_DRAM__SHIFT 0x13 |
35978 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 |
35979 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 |
35980 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 |
35981 | #define GUS_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 |
35982 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_DRAM__SHIFT 0x1b |
35983 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c |
35984 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d |
35985 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e |
35986 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f |
35987 | #define GUS_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
35988 | #define GUS_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
35989 | #define GUS_CGTT_CLK_CTRL__SPARE0_MASK 0x0007F000L |
35990 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_DRAM_MASK 0x00080000L |
35991 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L |
35992 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L |
35993 | #define GUS_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L |
35994 | #define GUS_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L |
35995 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_DRAM_MASK 0x08000000L |
35996 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L |
35997 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L |
35998 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L |
35999 | #define GUS_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L |
36000 | //CGTT_PH_CLK_CTRL0 |
36001 | #define CGTT_PH_CLK_CTRL0__ON_DELAY__SHIFT 0x0 |
36002 | #define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 |
36003 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
36004 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
36005 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
36006 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
36007 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
36008 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
36009 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
36010 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 |
36011 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 |
36012 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a |
36013 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b |
36014 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c |
36015 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d |
36016 | #define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE__SHIFT 0x1e |
36017 | #define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f |
36018 | #define CGTT_PH_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL |
36019 | #define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L |
36020 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
36021 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
36022 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
36023 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
36024 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
36025 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
36026 | #define CGTT_PH_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
36027 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L |
36028 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L |
36029 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L |
36030 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L |
36031 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L |
36032 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L |
36033 | #define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE_MASK 0x40000000L |
36034 | #define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L |
36035 | //CGTT_PH_CLK_CTRL1 |
36036 | #define CGTT_PH_CLK_CTRL1__ON_DELAY__SHIFT 0x0 |
36037 | #define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 |
36038 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18 |
36039 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 |
36040 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a |
36041 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b |
36042 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c |
36043 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d |
36044 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e |
36045 | #define CGTT_PH_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL |
36046 | #define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L |
36047 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x01000000L |
36048 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L |
36049 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L |
36050 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L |
36051 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L |
36052 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L |
36053 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L |
36054 | //CGTT_PH_CLK_CTRL2 |
36055 | #define CGTT_PH_CLK_CTRL2__ON_DELAY__SHIFT 0x0 |
36056 | #define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 |
36057 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18 |
36058 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 |
36059 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a |
36060 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b |
36061 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c |
36062 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d |
36063 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e |
36064 | #define CGTT_PH_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL |
36065 | #define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L |
36066 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x01000000L |
36067 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L |
36068 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L |
36069 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L |
36070 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L |
36071 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L |
36072 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L |
36073 | //CGTT_PH_CLK_CTRL3 |
36074 | #define CGTT_PH_CLK_CTRL3__ON_DELAY__SHIFT 0x0 |
36075 | #define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 |
36076 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18 |
36077 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 |
36078 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a |
36079 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b |
36080 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c |
36081 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d |
36082 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e |
36083 | #define CGTT_PH_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL |
36084 | #define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L |
36085 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L |
36086 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L |
36087 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L |
36088 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L |
36089 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L |
36090 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L |
36091 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L |
36092 | |
36093 | // addressBlock: gc_hypdec |
36094 | //CP_HYP_PFP_UCODE_ADDR |
36095 | #define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36096 | #define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36097 | //CP_PFP_UCODE_ADDR |
36098 | #define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36099 | #define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36100 | //CP_HYP_PFP_UCODE_DATA |
36101 | #define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36102 | #define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36103 | //CP_PFP_UCODE_DATA |
36104 | #define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36105 | #define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36106 | //CP_HYP_ME_UCODE_ADDR |
36107 | #define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36108 | #define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36109 | //CP_ME_RAM_RADDR |
36110 | #define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 |
36111 | #define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000FFFFFL |
36112 | //CP_ME_RAM_WADDR |
36113 | #define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 |
36114 | #define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x001FFFFFL |
36115 | //CP_HYP_ME_UCODE_DATA |
36116 | #define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36117 | #define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36118 | //CP_ME_RAM_DATA |
36119 | #define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 |
36120 | #define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL |
36121 | //CP_CE_UCODE_ADDR |
36122 | #define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36123 | #define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36124 | //CP_HYP_CE_UCODE_ADDR |
36125 | #define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36126 | #define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36127 | //CP_CE_UCODE_DATA |
36128 | #define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36129 | #define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36130 | //CP_HYP_CE_UCODE_DATA |
36131 | #define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36132 | #define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36133 | //CP_HYP_MEC1_UCODE_ADDR |
36134 | #define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36135 | #define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36136 | //CP_MEC_ME1_UCODE_ADDR |
36137 | #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36138 | #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36139 | //CP_HYP_MEC1_UCODE_DATA |
36140 | #define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36141 | #define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36142 | //CP_MEC_ME1_UCODE_DATA |
36143 | #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36144 | #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36145 | //CP_HYP_MEC2_UCODE_ADDR |
36146 | #define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36147 | #define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36148 | //CP_MEC_ME2_UCODE_ADDR |
36149 | #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36150 | #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36151 | //CP_HYP_MEC2_UCODE_DATA |
36152 | #define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36153 | #define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36154 | //CP_MEC_ME2_UCODE_DATA |
36155 | #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36156 | #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36157 | //CP_PFP_IC_BASE_LO |
36158 | #define CP_PFP_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
36159 | #define CP_PFP_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
36160 | //CP_PFP_IC_BASE_HI |
36161 | #define CP_PFP_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
36162 | #define CP_PFP_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
36163 | //CP_PFP_IC_BASE_CNTL |
36164 | #define CP_PFP_IC_BASE_CNTL__VMID__SHIFT 0x0 |
36165 | #define CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4 |
36166 | #define CP_PFP_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
36167 | #define CP_PFP_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
36168 | #define CP_PFP_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
36169 | #define CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L |
36170 | #define CP_PFP_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
36171 | #define CP_PFP_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
36172 | //CP_PFP_IC_OP_CNTL |
36173 | #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
36174 | #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 |
36175 | #define CP_PFP_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
36176 | #define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
36177 | #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
36178 | #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L |
36179 | #define CP_PFP_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
36180 | #define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
36181 | //CP_ME_IC_BASE_LO |
36182 | #define CP_ME_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
36183 | #define CP_ME_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
36184 | //CP_ME_IC_BASE_HI |
36185 | #define CP_ME_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
36186 | #define CP_ME_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
36187 | //CP_ME_IC_BASE_CNTL |
36188 | #define CP_ME_IC_BASE_CNTL__VMID__SHIFT 0x0 |
36189 | #define CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4 |
36190 | #define CP_ME_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
36191 | #define CP_ME_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
36192 | #define CP_ME_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
36193 | #define CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L |
36194 | #define CP_ME_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
36195 | #define CP_ME_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
36196 | //CP_ME_IC_OP_CNTL |
36197 | #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
36198 | #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 |
36199 | #define CP_ME_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
36200 | #define CP_ME_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
36201 | #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
36202 | #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L |
36203 | #define CP_ME_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
36204 | #define CP_ME_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
36205 | //CP_CE_IC_BASE_LO |
36206 | #define CP_CE_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
36207 | #define CP_CE_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
36208 | //CP_CE_IC_BASE_HI |
36209 | #define CP_CE_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
36210 | #define CP_CE_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
36211 | //CP_CE_IC_BASE_CNTL |
36212 | #define CP_CE_IC_BASE_CNTL__VMID__SHIFT 0x0 |
36213 | #define CP_CE_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4 |
36214 | #define CP_CE_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
36215 | #define CP_CE_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
36216 | #define CP_CE_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
36217 | #define CP_CE_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L |
36218 | #define CP_CE_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
36219 | #define CP_CE_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
36220 | //CP_CE_IC_OP_CNTL |
36221 | #define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
36222 | #define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 |
36223 | #define CP_CE_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
36224 | #define CP_CE_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
36225 | #define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
36226 | #define CP_CE_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L |
36227 | #define CP_CE_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
36228 | #define CP_CE_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
36229 | //CP_CPC_IC_BASE_LO |
36230 | #define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
36231 | #define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
36232 | //CP_CPC_IC_BASE_HI |
36233 | #define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
36234 | #define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
36235 | //CP_CPC_IC_BASE_CNTL |
36236 | #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 |
36237 | #define CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4 |
36238 | #define CP_CPC_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
36239 | #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
36240 | #define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
36241 | #define CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L |
36242 | #define CP_CPC_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
36243 | #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
36244 | //CP_CPC_IC_OP_CNTL |
36245 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
36246 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 |
36247 | #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
36248 | #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
36249 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
36250 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L |
36251 | #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
36252 | #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
36253 | //CP_MES_IC_BASE_LO |
36254 | #define CP_MES_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
36255 | #define CP_MES_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
36256 | //CP_MES_MIBASE_LO |
36257 | #define CP_MES_MIBASE_LO__IC_BASE_LO__SHIFT 0xc |
36258 | #define CP_MES_MIBASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
36259 | //CP_MES_IC_BASE_HI |
36260 | #define CP_MES_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
36261 | #define CP_MES_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
36262 | //CP_MES_MIBASE_HI |
36263 | #define CP_MES_MIBASE_HI__IC_BASE_HI__SHIFT 0x0 |
36264 | #define CP_MES_MIBASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
36265 | //CP_MES_IC_BASE_CNTL |
36266 | #define CP_MES_IC_BASE_CNTL__VMID__SHIFT 0x0 |
36267 | #define CP_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
36268 | #define CP_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
36269 | #define CP_MES_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
36270 | #define CP_MES_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
36271 | #define CP_MES_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
36272 | //CP_MES_DC_BASE_LO |
36273 | #define CP_MES_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 |
36274 | #define CP_MES_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L |
36275 | //CP_MES_MDBASE_LO |
36276 | #define CP_MES_MDBASE_LO__BASE_LO__SHIFT 0x10 |
36277 | #define CP_MES_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L |
36278 | //CP_MES_DC_BASE_HI |
36279 | #define CP_MES_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 |
36280 | #define CP_MES_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL |
36281 | //CP_MES_MDBASE_HI |
36282 | #define CP_MES_MDBASE_HI__BASE_HI__SHIFT 0x0 |
36283 | #define CP_MES_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL |
36284 | //CP_MES_LOCAL_BASE0_LO |
36285 | #define CP_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 |
36286 | #define CP_MES_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L |
36287 | //CP_MES_LOCAL_BASE0_HI |
36288 | #define CP_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 |
36289 | #define CP_MES_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL |
36290 | //CP_MES_LOCAL_MASK0_LO |
36291 | #define CP_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 |
36292 | #define CP_MES_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L |
36293 | //CP_MES_LOCAL_MASK0_HI |
36294 | #define CP_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 |
36295 | #define CP_MES_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL |
36296 | //CP_MES_LOCAL_APERTURE |
36297 | #define CP_MES_LOCAL_APERTURE__APERTURE__SHIFT 0x0 |
36298 | #define CP_MES_LOCAL_APERTURE__APERTURE_MASK 0x00000003L |
36299 | //CP_MES_MIBOUND_LO |
36300 | #define CP_MES_MIBOUND_LO__BOUND_LO__SHIFT 0x0 |
36301 | #define CP_MES_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL |
36302 | //CP_MES_MIBOUND_HI |
36303 | #define CP_MES_MIBOUND_HI__BOUND_HI__SHIFT 0x0 |
36304 | #define CP_MES_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL |
36305 | //CP_MES_MDBOUND_LO |
36306 | #define CP_MES_MDBOUND_LO__BOUND_LO__SHIFT 0x0 |
36307 | #define CP_MES_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL |
36308 | //CP_MES_MDBOUND_HI |
36309 | #define CP_MES_MDBOUND_HI__BOUND_HI__SHIFT 0x0 |
36310 | #define CP_MES_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL |
36311 | //GFX_PIPE_PRIORITY |
36312 | #define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0 |
36313 | #define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x00000001L |
36314 | //GRBM_GFX_INDEX_SR_SELECT |
36315 | #define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0 |
36316 | #define GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT 0x1f |
36317 | #define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L |
36318 | #define GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK 0x80000000L |
36319 | //GRBM_GFX_INDEX_SR_DATA |
36320 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0 |
36321 | #define GRBM_GFX_INDEX_SR_DATA__SA_INDEX__SHIFT 0x8 |
36322 | #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10 |
36323 | #define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES__SHIFT 0x1d |
36324 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e |
36325 | #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f |
36326 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL |
36327 | #define GRBM_GFX_INDEX_SR_DATA__SA_INDEX_MASK 0x0000FF00L |
36328 | #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L |
36329 | #define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES_MASK 0x20000000L |
36330 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L |
36331 | #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L |
36332 | //GRBM_GFX_CNTL_SR_SELECT |
36333 | #define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0 |
36334 | #define GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT 0x1f |
36335 | #define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L |
36336 | #define GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK 0x80000000L |
36337 | //GRBM_GFX_CNTL_SR_DATA |
36338 | #define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0 |
36339 | #define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2 |
36340 | #define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4 |
36341 | #define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8 |
36342 | #define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L |
36343 | #define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL |
36344 | #define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L |
36345 | #define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L |
36346 | //GRBM_CAM_INDEX |
36347 | #define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 |
36348 | #define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x0000000FL |
36349 | //GRBM_HYP_CAM_INDEX |
36350 | #define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 |
36351 | #define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x0000000FL |
36352 | //GRBM_CAM_DATA |
36353 | #define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 |
36354 | #define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 |
36355 | #define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL |
36356 | #define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L |
36357 | //GRBM_HYP_CAM_DATA |
36358 | #define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 |
36359 | #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 |
36360 | #define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL |
36361 | #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L |
36362 | //GRBM_CAM_DATA_UPPER |
36363 | #define GRBM_CAM_DATA_UPPER__CAM_ADDR__SHIFT 0x0 |
36364 | #define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT 0x10 |
36365 | #define GRBM_CAM_DATA_UPPER__CAM_ADDR_MASK 0x00000003L |
36366 | #define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR_MASK 0x00030000L |
36367 | //GRBM_HYP_CAM_DATA_UPPER |
36368 | #define GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR__SHIFT 0x0 |
36369 | #define GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT 0x10 |
36370 | #define GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR_MASK 0x00000003L |
36371 | #define GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR_MASK 0x00030000L |
36372 | //GC_IH_COOKIE_0_PTR |
36373 | #define GC_IH_COOKIE_0_PTR__ADDR__SHIFT 0x0 |
36374 | #define GC_IH_COOKIE_0_PTR__ADDR_MASK 0x000FFFFFL |
36375 | //GRBM_SE_REMAP_CNTL |
36376 | #define GRBM_SE_REMAP_CNTL__SE0_REMAP_EN__SHIFT 0x0 |
36377 | #define GRBM_SE_REMAP_CNTL__SE0_REMAP__SHIFT 0x1 |
36378 | #define GRBM_SE_REMAP_CNTL__SE1_REMAP_EN__SHIFT 0x4 |
36379 | #define GRBM_SE_REMAP_CNTL__SE1_REMAP__SHIFT 0x5 |
36380 | #define GRBM_SE_REMAP_CNTL__SE2_REMAP_EN__SHIFT 0x8 |
36381 | #define GRBM_SE_REMAP_CNTL__SE2_REMAP__SHIFT 0x9 |
36382 | #define GRBM_SE_REMAP_CNTL__SE3_REMAP_EN__SHIFT 0xc |
36383 | #define GRBM_SE_REMAP_CNTL__SE3_REMAP__SHIFT 0xd |
36384 | #define GRBM_SE_REMAP_CNTL__SE4_REMAP_EN__SHIFT 0x10 |
36385 | #define GRBM_SE_REMAP_CNTL__SE4_REMAP__SHIFT 0x11 |
36386 | #define GRBM_SE_REMAP_CNTL__SE5_REMAP_EN__SHIFT 0x14 |
36387 | #define GRBM_SE_REMAP_CNTL__SE5_REMAP__SHIFT 0x15 |
36388 | #define GRBM_SE_REMAP_CNTL__SE6_REMAP_EN__SHIFT 0x18 |
36389 | #define GRBM_SE_REMAP_CNTL__SE6_REMAP__SHIFT 0x19 |
36390 | #define GRBM_SE_REMAP_CNTL__SE7_REMAP_EN__SHIFT 0x1c |
36391 | #define GRBM_SE_REMAP_CNTL__SE7_REMAP__SHIFT 0x1d |
36392 | #define GRBM_SE_REMAP_CNTL__SE0_REMAP_EN_MASK 0x00000001L |
36393 | #define GRBM_SE_REMAP_CNTL__SE0_REMAP_MASK 0x0000000EL |
36394 | #define GRBM_SE_REMAP_CNTL__SE1_REMAP_EN_MASK 0x00000010L |
36395 | #define GRBM_SE_REMAP_CNTL__SE1_REMAP_MASK 0x000000E0L |
36396 | #define GRBM_SE_REMAP_CNTL__SE2_REMAP_EN_MASK 0x00000100L |
36397 | #define GRBM_SE_REMAP_CNTL__SE2_REMAP_MASK 0x00000E00L |
36398 | #define GRBM_SE_REMAP_CNTL__SE3_REMAP_EN_MASK 0x00001000L |
36399 | #define GRBM_SE_REMAP_CNTL__SE3_REMAP_MASK 0x0000E000L |
36400 | #define GRBM_SE_REMAP_CNTL__SE4_REMAP_EN_MASK 0x00010000L |
36401 | #define GRBM_SE_REMAP_CNTL__SE4_REMAP_MASK 0x000E0000L |
36402 | #define GRBM_SE_REMAP_CNTL__SE5_REMAP_EN_MASK 0x00100000L |
36403 | #define GRBM_SE_REMAP_CNTL__SE5_REMAP_MASK 0x00E00000L |
36404 | #define GRBM_SE_REMAP_CNTL__SE6_REMAP_EN_MASK 0x01000000L |
36405 | #define GRBM_SE_REMAP_CNTL__SE6_REMAP_MASK 0x0E000000L |
36406 | #define GRBM_SE_REMAP_CNTL__SE7_REMAP_EN_MASK 0x10000000L |
36407 | #define GRBM_SE_REMAP_CNTL__SE7_REMAP_MASK 0xE0000000L |
36408 | //RLC_GPU_IOV_VF_ENABLE |
36409 | #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 |
36410 | #define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 |
36411 | #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 |
36412 | #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L |
36413 | #define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL |
36414 | #define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L |
36415 | //RLC_GPU_IOV_CFG_REG6 |
36416 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 |
36417 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 |
36418 | #define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 |
36419 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa |
36420 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL |
36421 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L |
36422 | #define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L |
36423 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L |
36424 | //RLC_SDMA0_STATUS |
36425 | #define RLC_SDMA0_STATUS__STATUS__SHIFT 0x0 |
36426 | #define RLC_SDMA0_STATUS__STATUS_MASK 0xFFFFFFFFL |
36427 | //RLC_SDMA1_STATUS |
36428 | #define RLC_SDMA1_STATUS__STATUS__SHIFT 0x0 |
36429 | #define RLC_SDMA1_STATUS__STATUS_MASK 0xFFFFFFFFL |
36430 | //RLC_SDMA2_STATUS |
36431 | #define RLC_SDMA2_STATUS__STATUS__SHIFT 0x0 |
36432 | #define RLC_SDMA2_STATUS__STATUS_MASK 0xFFFFFFFFL |
36433 | //RLC_SDMA3_STATUS |
36434 | #define RLC_SDMA3_STATUS__STATUS__SHIFT 0x0 |
36435 | #define RLC_SDMA3_STATUS__STATUS_MASK 0xFFFFFFFFL |
36436 | //RLC_SDMA0_BUSY_STATUS |
36437 | #define RLC_SDMA0_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 |
36438 | #define RLC_SDMA0_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL |
36439 | //RLC_SDMA1_BUSY_STATUS |
36440 | #define RLC_SDMA1_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 |
36441 | #define RLC_SDMA1_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL |
36442 | //RLC_SDMA2_BUSY_STATUS |
36443 | #define RLC_SDMA2_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 |
36444 | #define RLC_SDMA2_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL |
36445 | //RLC_SDMA3_BUSY_STATUS |
36446 | #define RLC_SDMA3_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 |
36447 | #define RLC_SDMA3_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL |
36448 | //RLC_GPU_IOV_CFG_REG8 |
36449 | #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 |
36450 | #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36451 | //RLC_RLCV_TIMER_INT_0 |
36452 | #define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0 |
36453 | #define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL |
36454 | //RLC_RLCV_TIMER_CTRL |
36455 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 |
36456 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 |
36457 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x2 |
36458 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x3 |
36459 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x4 |
36460 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x5 |
36461 | #define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x6 |
36462 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L |
36463 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L |
36464 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000004L |
36465 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000008L |
36466 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00000010L |
36467 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00000020L |
36468 | #define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFC0L |
36469 | //RLC_RLCV_TIMER_STAT |
36470 | #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 |
36471 | #define RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 |
36472 | #define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x2 |
36473 | #define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 |
36474 | #define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 |
36475 | #define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xa |
36476 | #define RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0xb |
36477 | #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L |
36478 | #define RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L |
36479 | #define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0x000000FCL |
36480 | #define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L |
36481 | #define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L |
36482 | #define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00000400L |
36483 | #define RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00000800L |
36484 | //RLC_GPU_IOV_VF_DOORBELL_STATUS |
36485 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0 |
36486 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f |
36487 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x7FFFFFFFL |
36488 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L |
36489 | //RLC_GPU_IOV_VF_DOORBELL_STATUS_SET |
36490 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0 |
36491 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f |
36492 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x7FFFFFFFL |
36493 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L |
36494 | //RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR |
36495 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0 |
36496 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f |
36497 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x7FFFFFFFL |
36498 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L |
36499 | //RLC_GPU_IOV_VF_MASK |
36500 | #define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0 |
36501 | #define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x7FFFFFFFL |
36502 | //RLC_HYP_SEMAPHORE_0 |
36503 | #define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 |
36504 | #define RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT 0x5 |
36505 | #define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL |
36506 | #define RLC_HYP_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L |
36507 | //RLC_HYP_SEMAPHORE_1 |
36508 | #define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 |
36509 | #define RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT 0x5 |
36510 | #define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL |
36511 | #define RLC_HYP_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L |
36512 | //RLC_BUSY_CLK_CNTL |
36513 | #define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY__SHIFT 0x0 |
36514 | #define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY_MASK 0x0000003FL |
36515 | //RLC_CLK_CNTL |
36516 | #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0 |
36517 | #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x2 |
36518 | #define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT 0x4 |
36519 | #define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT 0x5 |
36520 | #define RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT 0x6 |
36521 | #define RLC_CLK_CNTL__RESERVED_7__SHIFT 0x7 |
36522 | #define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT 0x8 |
36523 | #define RLC_CLK_CNTL__RESERVED_9__SHIFT 0x9 |
36524 | #define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT 0xa |
36525 | #define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT 0xc |
36526 | #define RLC_CLK_CNTL__RESERVED_15__SHIFT 0xf |
36527 | #define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT 0x12 |
36528 | #define RLC_CLK_CNTL__RESERVED__SHIFT 0x13 |
36529 | #define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000003L |
36530 | #define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x0000000CL |
36531 | #define RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK 0x00000010L |
36532 | #define RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK 0x00000020L |
36533 | #define RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK 0x00000040L |
36534 | #define RLC_CLK_CNTL__RESERVED_7_MASK 0x00000080L |
36535 | #define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK 0x00000100L |
36536 | #define RLC_CLK_CNTL__RESERVED_9_MASK 0x00000200L |
36537 | #define RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK 0x00000C00L |
36538 | #define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK 0x00001000L |
36539 | #define RLC_CLK_CNTL__RESERVED_15_MASK 0x00008000L |
36540 | #define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK 0x00040000L |
36541 | #define RLC_CLK_CNTL__RESERVED_MASK 0xFFF80000L |
36542 | //RLC_PACE_TIMER_STAT |
36543 | #define RLC_PACE_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 |
36544 | #define RLC_PACE_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 |
36545 | #define RLC_PACE_TIMER_STAT__RESERVED__SHIFT 0x2 |
36546 | #define RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 |
36547 | #define RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 |
36548 | #define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xa |
36549 | #define RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0xb |
36550 | #define RLC_PACE_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L |
36551 | #define RLC_PACE_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L |
36552 | #define RLC_PACE_TIMER_STAT__RESERVED_MASK 0x000000FCL |
36553 | #define RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L |
36554 | #define RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L |
36555 | #define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00000400L |
36556 | #define RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00000800L |
36557 | //RLC_GPU_IOV_SCH_BLOCK |
36558 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0 |
36559 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4 |
36560 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8 |
36561 | #define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10 |
36562 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL |
36563 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L |
36564 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L |
36565 | #define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L |
36566 | //RLC_GPU_IOV_CFG_REG1 |
36567 | #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 |
36568 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 |
36569 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 |
36570 | #define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 |
36571 | #define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 |
36572 | #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 |
36573 | #define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 |
36574 | #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL |
36575 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L |
36576 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L |
36577 | #define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L |
36578 | #define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L |
36579 | #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L |
36580 | #define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L |
36581 | //RLC_GPU_IOV_CFG_REG2 |
36582 | #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 |
36583 | #define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4 |
36584 | #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL |
36585 | #define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L |
36586 | //RLC_GPU_IOV_VM_BUSY_STATUS |
36587 | #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36588 | #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36589 | //RLC_GPU_IOV_SCH_0 |
36590 | #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0 |
36591 | #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL |
36592 | //RLC_GPU_IOV_ACTIVE_FCN_ID |
36593 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 |
36594 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x5 |
36595 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f |
36596 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000001FL |
36597 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFE0L |
36598 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L |
36599 | //RLC_GPU_IOV_SCH_3 |
36600 | #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0 |
36601 | #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL |
36602 | //RLC_GPU_IOV_SCH_1 |
36603 | #define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 |
36604 | #define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL |
36605 | //RLC_GPU_IOV_SCH_2 |
36606 | #define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 |
36607 | #define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL |
36608 | //RLC_PACE_INT_FORCE |
36609 | #define RLC_PACE_INT_FORCE__FORCE_INT__SHIFT 0x0 |
36610 | #define RLC_PACE_INT_FORCE__FORCE_INT_MASK 0xFFFFFFFFL |
36611 | //RLC_PACE_INT_CLEAR |
36612 | #define RLC_PACE_INT_CLEAR__SMU_STRETCH_PCC_CLEAR__SHIFT 0x0 |
36613 | #define RLC_PACE_INT_CLEAR__SMU_PCC_CLEAR__SHIFT 0x1 |
36614 | #define RLC_PACE_INT_CLEAR__SMU_STRETCH_PCC_CLEAR_MASK 0x00000001L |
36615 | #define RLC_PACE_INT_CLEAR__SMU_PCC_CLEAR_MASK 0x00000002L |
36616 | //RLC_GPU_IOV_INT_STAT |
36617 | #define RLC_GPU_IOV_INT_STAT__STATUS__SHIFT 0x0 |
36618 | #define RLC_GPU_IOV_INT_STAT__STATUS_MASK 0xFFFFFFFFL |
36619 | //RLC_RLCV_TIMER_INT_1 |
36620 | #define RLC_RLCV_TIMER_INT_1__TIMER__SHIFT 0x0 |
36621 | #define RLC_RLCV_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL |
36622 | //RLC_IH_COOKIE |
36623 | #define RLC_IH_COOKIE__DATA__SHIFT 0x0 |
36624 | #define RLC_IH_COOKIE__DATA_MASK 0xFFFFFFFFL |
36625 | //RLC_IH_COOKIE_CNTL |
36626 | #define RLC_IH_COOKIE_CNTL__CREDIT__SHIFT 0x0 |
36627 | #define RLC_IH_COOKIE_CNTL__RESET_COUNTER__SHIFT 0x2 |
36628 | #define RLC_IH_COOKIE_CNTL__CREDIT_MASK 0x00000003L |
36629 | #define RLC_IH_COOKIE_CNTL__RESET_COUNTER_MASK 0x00000004L |
36630 | //RLC_HYP_RLCG_UCODE_CHKSUM |
36631 | #define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 |
36632 | #define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL |
36633 | //RLC_HYP_RLCP_UCODE_CHKSUM |
36634 | #define RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 |
36635 | #define RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL |
36636 | //RLC_HYP_RLCV_UCODE_CHKSUM |
36637 | #define RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 |
36638 | #define RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL |
36639 | //RLC_GPU_IOV_F32_CNTL |
36640 | #define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0 |
36641 | #define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L |
36642 | //RLC_GPU_IOV_F32_RESET |
36643 | #define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0 |
36644 | #define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L |
36645 | //RLC_GPU_IOV_SMU_RESPONSE |
36646 | #define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0 |
36647 | #define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL |
36648 | //RLC_GPU_IOV_VIRT_RESET_REQ |
36649 | #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 |
36650 | #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f |
36651 | #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL |
36652 | #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L |
36653 | //RLC_GPU_IOV_RLC_RESPONSE |
36654 | #define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 |
36655 | #define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL |
36656 | //RLC_GPU_IOV_INT_DISABLE |
36657 | #define RLC_GPU_IOV_INT_DISABLE__DISABLE_INT__SHIFT 0x0 |
36658 | #define RLC_GPU_IOV_INT_DISABLE__DISABLE_INT_MASK 0xFFFFFFFFL |
36659 | //RLC_GPU_IOV_INT_FORCE |
36660 | #define RLC_GPU_IOV_INT_FORCE__FORCE_INT__SHIFT 0x0 |
36661 | #define RLC_GPU_IOV_INT_FORCE__FORCE_INT_MASK 0xFFFFFFFFL |
36662 | //RLC_HYP_SEMAPHORE_2 |
36663 | #define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 |
36664 | #define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5 |
36665 | #define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL |
36666 | #define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L |
36667 | //RLC_HYP_SEMAPHORE_3 |
36668 | #define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 |
36669 | #define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5 |
36670 | #define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL |
36671 | #define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L |
36672 | //RLC_HYP_RESET_VECTOR |
36673 | #define RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT__SHIFT 0x0 |
36674 | #define RLC_HYP_RESET_VECTOR__VDDGFX_EXIT__SHIFT 0x1 |
36675 | #define RLC_HYP_RESET_VECTOR__WARM_RESET_EXIT__SHIFT 0x2 |
36676 | #define RLC_HYP_RESET_VECTOR__VF_FLR_EXIT__SHIFT 0x3 |
36677 | #define RLC_HYP_RESET_VECTOR__RESERVED_4__SHIFT 0x4 |
36678 | #define RLC_HYP_RESET_VECTOR__RESERVED_5__SHIFT 0x5 |
36679 | #define RLC_HYP_RESET_VECTOR__RESERVED_6__SHIFT 0x6 |
36680 | #define RLC_HYP_RESET_VECTOR__RESERVED_7__SHIFT 0x7 |
36681 | #define RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK 0x00000001L |
36682 | #define RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK 0x00000002L |
36683 | #define RLC_HYP_RESET_VECTOR__WARM_RESET_EXIT_MASK 0x00000004L |
36684 | #define RLC_HYP_RESET_VECTOR__VF_FLR_EXIT_MASK 0x00000008L |
36685 | #define RLC_HYP_RESET_VECTOR__RESERVED_4_MASK 0x00000010L |
36686 | #define RLC_HYP_RESET_VECTOR__RESERVED_5_MASK 0x00000020L |
36687 | #define RLC_HYP_RESET_VECTOR__RESERVED_6_MASK 0x00000040L |
36688 | #define RLC_HYP_RESET_VECTOR__RESERVED_7_MASK 0x00000080L |
36689 | //RLC_HYP_BOOTLOAD_SIZE |
36690 | #define RLC_HYP_BOOTLOAD_SIZE__SIZE__SHIFT 0x0 |
36691 | #define RLC_HYP_BOOTLOAD_SIZE__SIZE_MASK 0x03FFFFFFL |
36692 | //RLC_HYP_BOOTLOAD_ADDR_LO |
36693 | #define RLC_HYP_BOOTLOAD_ADDR_LO__ADDR_LO__SHIFT 0x0 |
36694 | #define RLC_HYP_BOOTLOAD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL |
36695 | //RLC_HYP_BOOTLOAD_ADDR_HI |
36696 | #define RLC_HYP_BOOTLOAD_ADDR_HI__ADDR_HI__SHIFT 0x0 |
36697 | #define RLC_HYP_BOOTLOAD_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL |
36698 | //RLC_GPM_IRAM_ADDR |
36699 | #define RLC_GPM_IRAM_ADDR__ADDR__SHIFT 0x0 |
36700 | #define RLC_GPM_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL |
36701 | //RLC_GPM_IRAM_DATA |
36702 | #define RLC_GPM_IRAM_DATA__DATA__SHIFT 0x0 |
36703 | #define RLC_GPM_IRAM_DATA__DATA_MASK 0xFFFFFFFFL |
36704 | //RLC_GPM_UCODE_ADDR |
36705 | #define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36706 | #define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe |
36707 | #define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL |
36708 | #define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L |
36709 | //RLC_GPM_UCODE_DATA |
36710 | #define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36711 | #define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36712 | //RLC_PACE_UCODE_ADDR |
36713 | #define RLC_PACE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36714 | #define RLC_PACE_UCODE_ADDR__RESERVED__SHIFT 0xc |
36715 | #define RLC_PACE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL |
36716 | #define RLC_PACE_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L |
36717 | //RLC_PACE_UCODE_DATA |
36718 | #define RLC_PACE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36719 | #define RLC_PACE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36720 | //RLC_GPU_IOV_UCODE_ADDR |
36721 | #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36722 | #define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc |
36723 | #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL |
36724 | #define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L |
36725 | //RLC_GPU_IOV_UCODE_DATA |
36726 | #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36727 | #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36728 | //RLC_GPU_IOV_SCRATCH_ADDR |
36729 | #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0 |
36730 | #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x0000FFFFL |
36731 | //RLC_GPU_IOV_SCRATCH_DATA |
36732 | #define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0 |
36733 | #define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL |
36734 | //RLC_RLCV_IRAM_ADDR |
36735 | #define RLC_RLCV_IRAM_ADDR__ADDR__SHIFT 0x0 |
36736 | #define RLC_RLCV_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL |
36737 | //RLC_RLCV_IRAM_DATA |
36738 | #define RLC_RLCV_IRAM_DATA__DATA__SHIFT 0x0 |
36739 | #define RLC_RLCV_IRAM_DATA__DATA_MASK 0xFFFFFFFFL |
36740 | //RLC_RLCP_IRAM_ADDR |
36741 | #define RLC_RLCP_IRAM_ADDR__ADDR__SHIFT 0x0 |
36742 | #define RLC_RLCP_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL |
36743 | //RLC_RLCP_IRAM_DATA |
36744 | #define RLC_RLCP_IRAM_DATA__DATA__SHIFT 0x0 |
36745 | #define RLC_RLCP_IRAM_DATA__DATA_MASK 0xFFFFFFFFL |
36746 | //RLC_SRM_DRAM_ADDR |
36747 | #define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 |
36748 | #define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc |
36749 | #define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL |
36750 | #define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L |
36751 | //RLC_SRM_DRAM_DATA |
36752 | #define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 |
36753 | #define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL |
36754 | //RLC_SRM_ARAM_ADDR |
36755 | #define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 |
36756 | #define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc |
36757 | #define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL |
36758 | #define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L |
36759 | //RLC_SRM_ARAM_DATA |
36760 | #define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 |
36761 | #define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL |
36762 | //RLC_GPM_SCRATCH_ADDR |
36763 | #define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 |
36764 | #define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x0000FFFFL |
36765 | //RLC_GPM_SCRATCH_DATA |
36766 | #define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 |
36767 | #define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL |
36768 | //RLC_GTS_OFFSET_LSB |
36769 | #define RLC_GTS_OFFSET_LSB__DATA__SHIFT 0x0 |
36770 | #define RLC_GTS_OFFSET_LSB__DATA_MASK 0xFFFFFFFFL |
36771 | //RLC_GTS_OFFSET_MSB |
36772 | #define RLC_GTS_OFFSET_MSB__DATA__SHIFT 0x0 |
36773 | #define RLC_GTS_OFFSET_MSB__DATA_MASK 0xFFFFFFFFL |
36774 | //RLC_GPU_IOV_SDMA0_STATUS |
36775 | #define RLC_GPU_IOV_SDMA0_STATUS__STATUS__SHIFT 0x0 |
36776 | #define RLC_GPU_IOV_SDMA0_STATUS__STATUS_MASK 0xFFFFFFFFL |
36777 | //RLC_GPU_IOV_SDMA1_STATUS |
36778 | #define RLC_GPU_IOV_SDMA1_STATUS__STATUS__SHIFT 0x0 |
36779 | #define RLC_GPU_IOV_SDMA1_STATUS__STATUS_MASK 0xFFFFFFFFL |
36780 | //RLC_GPU_IOV_SDMA2_STATUS |
36781 | #define RLC_GPU_IOV_SDMA2_STATUS__STATUS__SHIFT 0x0 |
36782 | #define RLC_GPU_IOV_SDMA2_STATUS__STATUS_MASK 0xFFFFFFFFL |
36783 | //RLC_GPU_IOV_SDMA3_STATUS |
36784 | #define RLC_GPU_IOV_SDMA3_STATUS__STATUS__SHIFT 0x0 |
36785 | #define RLC_GPU_IOV_SDMA3_STATUS__STATUS_MASK 0xFFFFFFFFL |
36786 | //RLC_GPU_IOV_SDMA4_STATUS |
36787 | #define RLC_GPU_IOV_SDMA4_STATUS__STATUS__SHIFT 0x0 |
36788 | #define RLC_GPU_IOV_SDMA4_STATUS__STATUS_MASK 0xFFFFFFFFL |
36789 | //RLC_GPU_IOV_SDMA5_STATUS |
36790 | #define RLC_GPU_IOV_SDMA5_STATUS__STATUS__SHIFT 0x0 |
36791 | #define RLC_GPU_IOV_SDMA5_STATUS__STATUS_MASK 0xFFFFFFFFL |
36792 | //RLC_GPU_IOV_SDMA6_STATUS |
36793 | #define RLC_GPU_IOV_SDMA6_STATUS__STATUS__SHIFT 0x0 |
36794 | #define RLC_GPU_IOV_SDMA6_STATUS__STATUS_MASK 0xFFFFFFFFL |
36795 | //RLC_GPU_IOV_SDMA7_STATUS |
36796 | #define RLC_GPU_IOV_SDMA7_STATUS__STATUS__SHIFT 0x0 |
36797 | #define RLC_GPU_IOV_SDMA7_STATUS__STATUS_MASK 0xFFFFFFFFL |
36798 | //RLC_GPU_IOV_SDMA0_BUSY_STATUS |
36799 | #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36800 | #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36801 | //RLC_GPU_IOV_SDMA1_BUSY_STATUS |
36802 | #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36803 | #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36804 | //RLC_GPU_IOV_SDMA2_BUSY_STATUS |
36805 | #define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36806 | #define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36807 | //RLC_GPU_IOV_SDMA3_BUSY_STATUS |
36808 | #define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36809 | #define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36810 | //RLC_GPU_IOV_SDMA4_BUSY_STATUS |
36811 | #define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36812 | #define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36813 | //RLC_GPU_IOV_SDMA5_BUSY_STATUS |
36814 | #define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36815 | #define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36816 | //RLC_GPU_IOV_SDMA6_BUSY_STATUS |
36817 | #define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36818 | #define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36819 | //RLC_GPU_IOV_SDMA7_BUSY_STATUS |
36820 | #define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36821 | #define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36822 | |
36823 | |
36824 | // addressBlock: gc_sdma0_sdma0hypdec |
36825 | //SDMA0_UCODE_ADDR |
36826 | #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 |
36827 | #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00003FFFL |
36828 | //SDMA0_UCODE_DATA |
36829 | #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 |
36830 | #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL |
36831 | //SDMA0_VM_CTX_LO |
36832 | #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 |
36833 | #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL |
36834 | //SDMA0_VM_CTX_HI |
36835 | #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 |
36836 | #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL |
36837 | //SDMA0_ACTIVE_FCN_ID |
36838 | #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
36839 | #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x5 |
36840 | #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f |
36841 | #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL |
36842 | #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFE0L |
36843 | #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L |
36844 | //SDMA0_VM_CTX_CNTL |
36845 | #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 |
36846 | #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 |
36847 | #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L |
36848 | #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L |
36849 | //SDMA0_VIRT_RESET_REQ |
36850 | #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 |
36851 | #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f |
36852 | #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL |
36853 | #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L |
36854 | //SDMA0_VF_ENABLE |
36855 | #define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 |
36856 | #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L |
36857 | //SDMA0_CONTEXT_REG_TYPE0 |
36858 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 |
36859 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 |
36860 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 |
36861 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 |
36862 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 |
36863 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 |
36864 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 |
36865 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 |
36866 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 |
36867 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 |
36868 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa |
36869 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb |
36870 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc |
36871 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd |
36872 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe |
36873 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf |
36874 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 |
36875 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 |
36876 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 |
36877 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 |
36878 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L |
36879 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L |
36880 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L |
36881 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L |
36882 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L |
36883 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L |
36884 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L |
36885 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L |
36886 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L |
36887 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L |
36888 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L |
36889 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L |
36890 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L |
36891 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L |
36892 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L |
36893 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L |
36894 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L |
36895 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L |
36896 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L |
36897 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L |
36898 | //SDMA0_CONTEXT_REG_TYPE1 |
36899 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 |
36900 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 |
36901 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa |
36902 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb |
36903 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc |
36904 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd |
36905 | #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe |
36906 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf |
36907 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 |
36908 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 |
36909 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 |
36910 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 |
36911 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 |
36912 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 |
36913 | #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x18 |
36914 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L |
36915 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L |
36916 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L |
36917 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L |
36918 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L |
36919 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L |
36920 | #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L |
36921 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L |
36922 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L |
36923 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L |
36924 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L |
36925 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L |
36926 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L |
36927 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L |
36928 | #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFF000000L |
36929 | //SDMA0_CONTEXT_REG_TYPE2 |
36930 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 |
36931 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 |
36932 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 |
36933 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 |
36934 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 |
36935 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 |
36936 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 |
36937 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 |
36938 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 |
36939 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA9__SHIFT 0x9 |
36940 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA10__SHIFT 0xa |
36941 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0xb |
36942 | #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xc |
36943 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L |
36944 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L |
36945 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L |
36946 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L |
36947 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L |
36948 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L |
36949 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L |
36950 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L |
36951 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L |
36952 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA9_MASK 0x00000200L |
36953 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA10_MASK 0x00000400L |
36954 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000800L |
36955 | #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFF000L |
36956 | //SDMA0_CONTEXT_REG_TYPE3 |
36957 | #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 |
36958 | #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL |
36959 | //SDMA0_PUB_REG_TYPE0 |
36960 | #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 |
36961 | #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 |
36962 | #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x2 |
36963 | #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x3 |
36964 | #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x4 |
36965 | #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x5 |
36966 | #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x6 |
36967 | #define SDMA0_PUB_REG_TYPE0__SDMA0_VF_ENABLE__SHIFT 0x7 |
36968 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0x8 |
36969 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0x9 |
36970 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xa |
36971 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xb |
36972 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xc |
36973 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0xd |
36974 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0xe |
36975 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0xf |
36976 | #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x13 |
36977 | #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 |
36978 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CNTL__SHIFT 0x16 |
36979 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CTX_LO__SHIFT 0x17 |
36980 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CTX_HI__SHIFT 0x18 |
36981 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CTX_CNTL__SHIFT 0x19 |
36982 | #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a |
36983 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b |
36984 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c |
36985 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d |
36986 | #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e |
36987 | #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f |
36988 | #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L |
36989 | #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L |
36990 | #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000004L |
36991 | #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000008L |
36992 | #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000010L |
36993 | #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000020L |
36994 | #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000040L |
36995 | #define SDMA0_PUB_REG_TYPE0__SDMA0_VF_ENABLE_MASK 0x00000080L |
36996 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000100L |
36997 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00000200L |
36998 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00000400L |
36999 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00000800L |
37000 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00001000L |
37001 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00002000L |
37002 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00004000L |
37003 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00008000L |
37004 | #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00080000L |
37005 | #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x00300000L |
37006 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CNTL_MASK 0x00400000L |
37007 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CTX_LO_MASK 0x00800000L |
37008 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CTX_HI_MASK 0x01000000L |
37009 | #define SDMA0_PUB_REG_TYPE0__SDMA0_PG_CTX_CNTL_MASK 0x02000000L |
37010 | #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L |
37011 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L |
37012 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L |
37013 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L |
37014 | #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L |
37015 | #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L |
37016 | //SDMA0_PUB_REG_TYPE1 |
37017 | #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 |
37018 | #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 |
37019 | #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 |
37020 | #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 |
37021 | #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 |
37022 | #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 |
37023 | #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 |
37024 | #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 |
37025 | #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 |
37026 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 |
37027 | #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa |
37028 | #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb |
37029 | #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc |
37030 | #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd |
37031 | #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 |
37032 | #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 |
37033 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 |
37034 | #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 |
37035 | #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 |
37036 | #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 |
37037 | #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 |
37038 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 |
37039 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a |
37040 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b |
37041 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c |
37042 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d |
37043 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e |
37044 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f |
37045 | #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L |
37046 | #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L |
37047 | #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L |
37048 | #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L |
37049 | #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L |
37050 | #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L |
37051 | #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L |
37052 | #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L |
37053 | #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L |
37054 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L |
37055 | #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L |
37056 | #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L |
37057 | #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L |
37058 | #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L |
37059 | #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L |
37060 | #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L |
37061 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L |
37062 | #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L |
37063 | #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L |
37064 | #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L |
37065 | #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L |
37066 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L |
37067 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L |
37068 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L |
37069 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L |
37070 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L |
37071 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L |
37072 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L |
37073 | //SDMA0_PUB_REG_TYPE2 |
37074 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 |
37075 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 |
37076 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 |
37077 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 |
37078 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 |
37079 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 |
37080 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 |
37081 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 |
37082 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 |
37083 | #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa |
37084 | #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb |
37085 | #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc |
37086 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd |
37087 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe |
37088 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf |
37089 | #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 |
37090 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 |
37091 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 |
37092 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 |
37093 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 |
37094 | #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 |
37095 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_PERFCOUNTER0_CFG__SHIFT 0x17 |
37096 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_PERFCOUNTER1_CFG__SHIFT 0x18 |
37097 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__SHIFT 0x19 |
37098 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_MISC_CNTL__SHIFT 0x1a |
37099 | #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b |
37100 | #define SDMA0_PUB_REG_TYPE2__SDMA0_AQL_STATUS__SHIFT 0x1f |
37101 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L |
37102 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L |
37103 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L |
37104 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L |
37105 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L |
37106 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L |
37107 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L |
37108 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L |
37109 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L |
37110 | #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L |
37111 | #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L |
37112 | #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L |
37113 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L |
37114 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L |
37115 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L |
37116 | #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L |
37117 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L |
37118 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L |
37119 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L |
37120 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L |
37121 | #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L |
37122 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_PERFCOUNTER0_CFG_MASK 0x00800000L |
37123 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_PERFCOUNTER1_CFG_MASK 0x01000000L |
37124 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL_MASK 0x02000000L |
37125 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCNT_MISC_CNTL_MASK 0x04000000L |
37126 | #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L |
37127 | #define SDMA0_PUB_REG_TYPE2__SDMA0_AQL_STATUS_MASK 0x80000000L |
37128 | //SDMA0_PUB_REG_TYPE3 |
37129 | #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 |
37130 | #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 |
37131 | #define SDMA0_PUB_REG_TYPE3__SDMA0_TLBI_GCR_CNTL__SHIFT 0x2 |
37132 | #define SDMA0_PUB_REG_TYPE3__SDMA0_TILING_CONFIG__SHIFT 0x3 |
37133 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_SELECT__SHIFT 0x8 |
37134 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_SELECT1__SHIFT 0x9 |
37135 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_LO__SHIFT 0xa |
37136 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_HI__SHIFT 0xb |
37137 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_SELECT__SHIFT 0xc |
37138 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_SELECT1__SHIFT 0xd |
37139 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_LO__SHIFT 0xe |
37140 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_HI__SHIFT 0xf |
37141 | #define SDMA0_PUB_REG_TYPE3__SDMA0_INT_STATUS__SHIFT 0x10 |
37142 | #define SDMA0_PUB_REG_TYPE3__SDMA0_HOLE_ADDR_LO__SHIFT 0x12 |
37143 | #define SDMA0_PUB_REG_TYPE3__SDMA0_HOLE_ADDR_HI__SHIFT 0x13 |
37144 | #define SDMA0_PUB_REG_TYPE3__SDMA0_CLOCK_GATING_REG__SHIFT 0x15 |
37145 | #define SDMA0_PUB_REG_TYPE3__SDMA0_STATUS4_REG__SHIFT 0x16 |
37146 | #define SDMA0_PUB_REG_TYPE3__SDMA0_SCRATCH_RAM_DATA__SHIFT 0x17 |
37147 | #define SDMA0_PUB_REG_TYPE3__SDMA0_SCRATCH_RAM_ADDR__SHIFT 0x18 |
37148 | #define SDMA0_PUB_REG_TYPE3__SDMA0_TIMESTAMP_CNTL__SHIFT 0x19 |
37149 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCNT_PERFCOUNTER_LO__SHIFT 0x1a |
37150 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCNT_PERFCOUNTER_HI__SHIFT 0x1b |
37151 | #define SDMA0_PUB_REG_TYPE3__SDMA0_STATUS5_REG__SHIFT 0x1c |
37152 | #define SDMA0_PUB_REG_TYPE3__SDMA0_QUEUE_RESET_REQ__SHIFT 0x1d |
37153 | #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x1e |
37154 | #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L |
37155 | #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L |
37156 | #define SDMA0_PUB_REG_TYPE3__SDMA0_TLBI_GCR_CNTL_MASK 0x00000004L |
37157 | #define SDMA0_PUB_REG_TYPE3__SDMA0_TILING_CONFIG_MASK 0x00000008L |
37158 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_SELECT_MASK 0x00000100L |
37159 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_SELECT1_MASK 0x00000200L |
37160 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_LO_MASK 0x00000400L |
37161 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER0_HI_MASK 0x00000800L |
37162 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_SELECT_MASK 0x00001000L |
37163 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_SELECT1_MASK 0x00002000L |
37164 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_LO_MASK 0x00004000L |
37165 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCOUNTER1_HI_MASK 0x00008000L |
37166 | #define SDMA0_PUB_REG_TYPE3__SDMA0_INT_STATUS_MASK 0x00010000L |
37167 | #define SDMA0_PUB_REG_TYPE3__SDMA0_HOLE_ADDR_LO_MASK 0x00040000L |
37168 | #define SDMA0_PUB_REG_TYPE3__SDMA0_HOLE_ADDR_HI_MASK 0x00080000L |
37169 | #define SDMA0_PUB_REG_TYPE3__SDMA0_CLOCK_GATING_REG_MASK 0x00200000L |
37170 | #define SDMA0_PUB_REG_TYPE3__SDMA0_STATUS4_REG_MASK 0x00400000L |
37171 | #define SDMA0_PUB_REG_TYPE3__SDMA0_SCRATCH_RAM_DATA_MASK 0x00800000L |
37172 | #define SDMA0_PUB_REG_TYPE3__SDMA0_SCRATCH_RAM_ADDR_MASK 0x01000000L |
37173 | #define SDMA0_PUB_REG_TYPE3__SDMA0_TIMESTAMP_CNTL_MASK 0x02000000L |
37174 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCNT_PERFCOUNTER_LO_MASK 0x04000000L |
37175 | #define SDMA0_PUB_REG_TYPE3__SDMA0_PERFCNT_PERFCOUNTER_HI_MASK 0x08000000L |
37176 | #define SDMA0_PUB_REG_TYPE3__SDMA0_STATUS5_REG_MASK 0x10000000L |
37177 | #define SDMA0_PUB_REG_TYPE3__SDMA0_QUEUE_RESET_REQ_MASK 0x20000000L |
37178 | #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xC0000000L |
37179 | //SDMA0_VM_CNTL |
37180 | #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 |
37181 | #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL |
37182 | //SDMA0_BROADCAST_UCODE_ADDR |
37183 | #define SDMA0_BROADCAST_UCODE_ADDR__VALUE__SHIFT 0x0 |
37184 | #define SDMA0_BROADCAST_UCODE_ADDR__VALUE_MASK 0x00003FFFL |
37185 | //SDMA0_BROADCAST_UCODE_DATA |
37186 | #define SDMA0_BROADCAST_UCODE_DATA__VALUE__SHIFT 0x0 |
37187 | #define SDMA0_BROADCAST_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL |
37188 | |
37189 | |
37190 | // addressBlock: gc_sdma1_sdma1hypdec |
37191 | //SDMA1_UCODE_ADDR |
37192 | #define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 |
37193 | #define SDMA1_UCODE_ADDR__VALUE_MASK 0x00003FFFL |
37194 | //SDMA1_UCODE_DATA |
37195 | #define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 |
37196 | #define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL |
37197 | //SDMA1_VM_CTX_LO |
37198 | #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 |
37199 | #define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL |
37200 | //SDMA1_VM_CTX_HI |
37201 | #define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 |
37202 | #define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL |
37203 | //SDMA1_ACTIVE_FCN_ID |
37204 | #define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
37205 | #define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x5 |
37206 | #define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f |
37207 | #define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL |
37208 | #define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFE0L |
37209 | #define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L |
37210 | //SDMA1_VM_CTX_CNTL |
37211 | #define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 |
37212 | #define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 |
37213 | #define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L |
37214 | #define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L |
37215 | //SDMA1_VIRT_RESET_REQ |
37216 | #define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 |
37217 | #define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f |
37218 | #define SDMA1_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL |
37219 | #define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L |
37220 | //SDMA1_VF_ENABLE |
37221 | #define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 |
37222 | #define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L |
37223 | //SDMA1_CONTEXT_REG_TYPE0 |
37224 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 |
37225 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 |
37226 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 |
37227 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 |
37228 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 |
37229 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 |
37230 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 |
37231 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 |
37232 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 |
37233 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 |
37234 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa |
37235 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb |
37236 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc |
37237 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd |
37238 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe |
37239 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf |
37240 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 |
37241 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 |
37242 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 |
37243 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 |
37244 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L |
37245 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L |
37246 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L |
37247 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L |
37248 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L |
37249 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L |
37250 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L |
37251 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L |
37252 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L |
37253 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L |
37254 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L |
37255 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L |
37256 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L |
37257 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L |
37258 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L |
37259 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L |
37260 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L |
37261 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L |
37262 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L |
37263 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L |
37264 | //SDMA1_CONTEXT_REG_TYPE1 |
37265 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 |
37266 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 |
37267 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa |
37268 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb |
37269 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc |
37270 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd |
37271 | #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe |
37272 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf |
37273 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 |
37274 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 |
37275 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 |
37276 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 |
37277 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 |
37278 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 |
37279 | #define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x18 |
37280 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L |
37281 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L |
37282 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L |
37283 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L |
37284 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L |
37285 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L |
37286 | #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L |
37287 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L |
37288 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L |
37289 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L |
37290 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L |
37291 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L |
37292 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L |
37293 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L |
37294 | #define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFF000000L |
37295 | //SDMA1_CONTEXT_REG_TYPE2 |
37296 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 |
37297 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 |
37298 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 |
37299 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 |
37300 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 |
37301 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 |
37302 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 |
37303 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 |
37304 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 |
37305 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA9__SHIFT 0x9 |
37306 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA10__SHIFT 0xa |
37307 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0xb |
37308 | #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xc |
37309 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L |
37310 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L |
37311 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L |
37312 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L |
37313 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L |
37314 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L |
37315 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L |
37316 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L |
37317 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L |
37318 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA9_MASK 0x00000200L |
37319 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA10_MASK 0x00000400L |
37320 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000800L |
37321 | #define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFF000L |
37322 | //SDMA1_CONTEXT_REG_TYPE3 |
37323 | #define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 |
37324 | #define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL |
37325 | //SDMA1_PUB_REG_TYPE0 |
37326 | #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 |
37327 | #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 |
37328 | #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x2 |
37329 | #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x3 |
37330 | #define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x4 |
37331 | #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x5 |
37332 | #define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x6 |
37333 | #define SDMA1_PUB_REG_TYPE0__SDMA1_VF_ENABLE__SHIFT 0x7 |
37334 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0x8 |
37335 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0x9 |
37336 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xa |
37337 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xb |
37338 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xc |
37339 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0xd |
37340 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0xe |
37341 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0xf |
37342 | #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x13 |
37343 | #define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 |
37344 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CNTL__SHIFT 0x16 |
37345 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CTX_LO__SHIFT 0x17 |
37346 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CTX_HI__SHIFT 0x18 |
37347 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CTX_CNTL__SHIFT 0x19 |
37348 | #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a |
37349 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b |
37350 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c |
37351 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d |
37352 | #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e |
37353 | #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f |
37354 | #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L |
37355 | #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L |
37356 | #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000004L |
37357 | #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000008L |
37358 | #define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000010L |
37359 | #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000020L |
37360 | #define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000040L |
37361 | #define SDMA1_PUB_REG_TYPE0__SDMA1_VF_ENABLE_MASK 0x00000080L |
37362 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000100L |
37363 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00000200L |
37364 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00000400L |
37365 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00000800L |
37366 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00001000L |
37367 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00002000L |
37368 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00004000L |
37369 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00008000L |
37370 | #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00080000L |
37371 | #define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x00300000L |
37372 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CNTL_MASK 0x00400000L |
37373 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CTX_LO_MASK 0x00800000L |
37374 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CTX_HI_MASK 0x01000000L |
37375 | #define SDMA1_PUB_REG_TYPE0__SDMA1_PG_CTX_CNTL_MASK 0x02000000L |
37376 | #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L |
37377 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L |
37378 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L |
37379 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L |
37380 | #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L |
37381 | #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L |
37382 | //SDMA1_PUB_REG_TYPE1 |
37383 | #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 |
37384 | #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 |
37385 | #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 |
37386 | #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 |
37387 | #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 |
37388 | #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 |
37389 | #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 |
37390 | #define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 |
37391 | #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 |
37392 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 |
37393 | #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa |
37394 | #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb |
37395 | #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc |
37396 | #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd |
37397 | #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 |
37398 | #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 |
37399 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 |
37400 | #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 |
37401 | #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 |
37402 | #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 |
37403 | #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 |
37404 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 |
37405 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a |
37406 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b |
37407 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c |
37408 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d |
37409 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e |
37410 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f |
37411 | #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L |
37412 | #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L |
37413 | #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L |
37414 | #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L |
37415 | #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L |
37416 | #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L |
37417 | #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L |
37418 | #define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L |
37419 | #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L |
37420 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L |
37421 | #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L |
37422 | #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L |
37423 | #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L |
37424 | #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L |
37425 | #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L |
37426 | #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L |
37427 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L |
37428 | #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L |
37429 | #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L |
37430 | #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L |
37431 | #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L |
37432 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L |
37433 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L |
37434 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L |
37435 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L |
37436 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L |
37437 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L |
37438 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L |
37439 | //SDMA1_PUB_REG_TYPE2 |
37440 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 |
37441 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 |
37442 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 |
37443 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 |
37444 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 |
37445 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 |
37446 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 |
37447 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 |
37448 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 |
37449 | #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa |
37450 | #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb |
37451 | #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc |
37452 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd |
37453 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe |
37454 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf |
37455 | #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 |
37456 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 |
37457 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 |
37458 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 |
37459 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 |
37460 | #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 |
37461 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_PERFCOUNTER0_CFG__SHIFT 0x17 |
37462 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_PERFCOUNTER1_CFG__SHIFT 0x18 |
37463 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__SHIFT 0x19 |
37464 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_MISC_CNTL__SHIFT 0x1a |
37465 | #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b |
37466 | #define SDMA1_PUB_REG_TYPE2__SDMA1_AQL_STATUS__SHIFT 0x1f |
37467 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L |
37468 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L |
37469 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L |
37470 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L |
37471 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L |
37472 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L |
37473 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L |
37474 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L |
37475 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L |
37476 | #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L |
37477 | #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L |
37478 | #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L |
37479 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L |
37480 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L |
37481 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L |
37482 | #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L |
37483 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L |
37484 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L |
37485 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L |
37486 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L |
37487 | #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L |
37488 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_PERFCOUNTER0_CFG_MASK 0x00800000L |
37489 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_PERFCOUNTER1_CFG_MASK 0x01000000L |
37490 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL_MASK 0x02000000L |
37491 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCNT_MISC_CNTL_MASK 0x04000000L |
37492 | #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L |
37493 | #define SDMA1_PUB_REG_TYPE2__SDMA1_AQL_STATUS_MASK 0x80000000L |
37494 | //SDMA1_PUB_REG_TYPE3 |
37495 | #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 |
37496 | #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 |
37497 | #define SDMA1_PUB_REG_TYPE3__SDMA1_TLBI_GCR_CNTL__SHIFT 0x2 |
37498 | #define SDMA1_PUB_REG_TYPE3__SDMA1_TILING_CONFIG__SHIFT 0x3 |
37499 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_SELECT__SHIFT 0x8 |
37500 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_SELECT1__SHIFT 0x9 |
37501 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_LO__SHIFT 0xa |
37502 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_HI__SHIFT 0xb |
37503 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_SELECT__SHIFT 0xc |
37504 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_SELECT1__SHIFT 0xd |
37505 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_LO__SHIFT 0xe |
37506 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_HI__SHIFT 0xf |
37507 | #define SDMA1_PUB_REG_TYPE3__SDMA1_INT_STATUS__SHIFT 0x10 |
37508 | #define SDMA1_PUB_REG_TYPE3__SDMA1_HOLE_ADDR_LO__SHIFT 0x12 |
37509 | #define SDMA1_PUB_REG_TYPE3__SDMA1_HOLE_ADDR_HI__SHIFT 0x13 |
37510 | #define SDMA1_PUB_REG_TYPE3__SDMA1_CLOCK_GATING_REG__SHIFT 0x15 |
37511 | #define SDMA1_PUB_REG_TYPE3__SDMA1_STATUS4_REG__SHIFT 0x16 |
37512 | #define SDMA1_PUB_REG_TYPE3__SDMA1_SCRATCH_RAM_DATA__SHIFT 0x17 |
37513 | #define SDMA1_PUB_REG_TYPE3__SDMA1_SCRATCH_RAM_ADDR__SHIFT 0x18 |
37514 | #define SDMA1_PUB_REG_TYPE3__SDMA1_TIMESTAMP_CNTL__SHIFT 0x19 |
37515 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCNT_PERFCOUNTER_LO__SHIFT 0x1a |
37516 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCNT_PERFCOUNTER_HI__SHIFT 0x1b |
37517 | #define SDMA1_PUB_REG_TYPE3__SDMA1_STATUS5_REG__SHIFT 0x1c |
37518 | #define SDMA1_PUB_REG_TYPE3__SDMA1_QUEUE_RESET_REQ__SHIFT 0x1d |
37519 | #define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x1e |
37520 | #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L |
37521 | #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L |
37522 | #define SDMA1_PUB_REG_TYPE3__SDMA1_TLBI_GCR_CNTL_MASK 0x00000004L |
37523 | #define SDMA1_PUB_REG_TYPE3__SDMA1_TILING_CONFIG_MASK 0x00000008L |
37524 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_SELECT_MASK 0x00000100L |
37525 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_SELECT1_MASK 0x00000200L |
37526 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_LO_MASK 0x00000400L |
37527 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER0_HI_MASK 0x00000800L |
37528 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_SELECT_MASK 0x00001000L |
37529 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_SELECT1_MASK 0x00002000L |
37530 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_LO_MASK 0x00004000L |
37531 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCOUNTER1_HI_MASK 0x00008000L |
37532 | #define SDMA1_PUB_REG_TYPE3__SDMA1_INT_STATUS_MASK 0x00010000L |
37533 | #define SDMA1_PUB_REG_TYPE3__SDMA1_HOLE_ADDR_LO_MASK 0x00040000L |
37534 | #define SDMA1_PUB_REG_TYPE3__SDMA1_HOLE_ADDR_HI_MASK 0x00080000L |
37535 | #define SDMA1_PUB_REG_TYPE3__SDMA1_CLOCK_GATING_REG_MASK 0x00200000L |
37536 | #define SDMA1_PUB_REG_TYPE3__SDMA1_STATUS4_REG_MASK 0x00400000L |
37537 | #define SDMA1_PUB_REG_TYPE3__SDMA1_SCRATCH_RAM_DATA_MASK 0x00800000L |
37538 | #define SDMA1_PUB_REG_TYPE3__SDMA1_SCRATCH_RAM_ADDR_MASK 0x01000000L |
37539 | #define SDMA1_PUB_REG_TYPE3__SDMA1_TIMESTAMP_CNTL_MASK 0x02000000L |
37540 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCNT_PERFCOUNTER_LO_MASK 0x04000000L |
37541 | #define SDMA1_PUB_REG_TYPE3__SDMA1_PERFCNT_PERFCOUNTER_HI_MASK 0x08000000L |
37542 | #define SDMA1_PUB_REG_TYPE3__SDMA1_STATUS5_REG_MASK 0x10000000L |
37543 | #define SDMA1_PUB_REG_TYPE3__SDMA1_QUEUE_RESET_REQ_MASK 0x20000000L |
37544 | #define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xC0000000L |
37545 | //SDMA1_VM_CNTL |
37546 | #define SDMA1_VM_CNTL__CMD__SHIFT 0x0 |
37547 | #define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL |
37548 | |
37549 | |
37550 | // addressBlock: gc_sdma2_sdma2hypdec |
37551 | //SDMA2_UCODE_ADDR |
37552 | #define SDMA2_UCODE_ADDR__VALUE__SHIFT 0x0 |
37553 | #define SDMA2_UCODE_ADDR__VALUE_MASK 0x00003FFFL |
37554 | //SDMA2_UCODE_DATA |
37555 | #define SDMA2_UCODE_DATA__VALUE__SHIFT 0x0 |
37556 | #define SDMA2_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL |
37557 | //SDMA2_VM_CTX_LO |
37558 | #define SDMA2_VM_CTX_LO__ADDR__SHIFT 0x2 |
37559 | #define SDMA2_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL |
37560 | //SDMA2_VM_CTX_HI |
37561 | #define SDMA2_VM_CTX_HI__ADDR__SHIFT 0x0 |
37562 | #define SDMA2_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL |
37563 | //SDMA2_ACTIVE_FCN_ID |
37564 | #define SDMA2_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
37565 | #define SDMA2_ACTIVE_FCN_ID__RESERVED__SHIFT 0x5 |
37566 | #define SDMA2_ACTIVE_FCN_ID__VF__SHIFT 0x1f |
37567 | #define SDMA2_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL |
37568 | #define SDMA2_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFE0L |
37569 | #define SDMA2_ACTIVE_FCN_ID__VF_MASK 0x80000000L |
37570 | //SDMA2_VM_CTX_CNTL |
37571 | #define SDMA2_VM_CTX_CNTL__PRIV__SHIFT 0x0 |
37572 | #define SDMA2_VM_CTX_CNTL__VMID__SHIFT 0x4 |
37573 | #define SDMA2_VM_CTX_CNTL__PRIV_MASK 0x00000001L |
37574 | #define SDMA2_VM_CTX_CNTL__VMID_MASK 0x000000F0L |
37575 | //SDMA2_VIRT_RESET_REQ |
37576 | #define SDMA2_VIRT_RESET_REQ__VF__SHIFT 0x0 |
37577 | #define SDMA2_VIRT_RESET_REQ__PF__SHIFT 0x1f |
37578 | #define SDMA2_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL |
37579 | #define SDMA2_VIRT_RESET_REQ__PF_MASK 0x80000000L |
37580 | //SDMA2_VF_ENABLE |
37581 | #define SDMA2_VF_ENABLE__VF_ENABLE__SHIFT 0x0 |
37582 | #define SDMA2_VF_ENABLE__VF_ENABLE_MASK 0x00000001L |
37583 | //SDMA2_CONTEXT_REG_TYPE0 |
37584 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_CNTL__SHIFT 0x0 |
37585 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE__SHIFT 0x1 |
37586 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_HI__SHIFT 0x2 |
37587 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR__SHIFT 0x3 |
37588 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_HI__SHIFT 0x4 |
37589 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR__SHIFT 0x5 |
37590 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_HI__SHIFT 0x6 |
37591 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 |
37592 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 |
37593 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 |
37594 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_CNTL__SHIFT 0xa |
37595 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_RPTR__SHIFT 0xb |
37596 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_OFFSET__SHIFT 0xc |
37597 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_LO__SHIFT 0xd |
37598 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_HI__SHIFT 0xe |
37599 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_SIZE__SHIFT 0xf |
37600 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_SKIP_CNTL__SHIFT 0x10 |
37601 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_STATUS__SHIFT 0x11 |
37602 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_DOORBELL__SHIFT 0x12 |
37603 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_CNTL__SHIFT 0x13 |
37604 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_CNTL_MASK 0x00000001L |
37605 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_MASK 0x00000002L |
37606 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_BASE_HI_MASK 0x00000004L |
37607 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_MASK 0x00000008L |
37608 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_HI_MASK 0x00000010L |
37609 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_MASK 0x00000020L |
37610 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_HI_MASK 0x00000040L |
37611 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L |
37612 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L |
37613 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L |
37614 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_CNTL_MASK 0x00000400L |
37615 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_RPTR_MASK 0x00000800L |
37616 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_OFFSET_MASK 0x00001000L |
37617 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_LO_MASK 0x00002000L |
37618 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_BASE_HI_MASK 0x00004000L |
37619 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_IB_SIZE_MASK 0x00008000L |
37620 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_SKIP_CNTL_MASK 0x00010000L |
37621 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_STATUS_MASK 0x00020000L |
37622 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_DOORBELL_MASK 0x00040000L |
37623 | #define SDMA2_CONTEXT_REG_TYPE0__SDMA2_GFX_CONTEXT_CNTL_MASK 0x00080000L |
37624 | //SDMA2_CONTEXT_REG_TYPE1 |
37625 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_STATUS__SHIFT 0x8 |
37626 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_LOG__SHIFT 0x9 |
37627 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_WATERMARK__SHIFT 0xa |
37628 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_OFFSET__SHIFT 0xb |
37629 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_LO__SHIFT 0xc |
37630 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_HI__SHIFT 0xd |
37631 | #define SDMA2_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe |
37632 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_IB_SUB_REMAIN__SHIFT 0xf |
37633 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_PREEMPT__SHIFT 0x10 |
37634 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DUMMY_REG__SHIFT 0x11 |
37635 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 |
37636 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 |
37637 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_AQL_CNTL__SHIFT 0x14 |
37638 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 |
37639 | #define SDMA2_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x18 |
37640 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_STATUS_MASK 0x00000100L |
37641 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_LOG_MASK 0x00000200L |
37642 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_WATERMARK_MASK 0x00000400L |
37643 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DOORBELL_OFFSET_MASK 0x00000800L |
37644 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_LO_MASK 0x00001000L |
37645 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_CSA_ADDR_HI_MASK 0x00002000L |
37646 | #define SDMA2_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L |
37647 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_IB_SUB_REMAIN_MASK 0x00008000L |
37648 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_PREEMPT_MASK 0x00010000L |
37649 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_DUMMY_REG_MASK 0x00020000L |
37650 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L |
37651 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L |
37652 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_RB_AQL_CNTL_MASK 0x00100000L |
37653 | #define SDMA2_CONTEXT_REG_TYPE1__SDMA2_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L |
37654 | #define SDMA2_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFF000000L |
37655 | //SDMA2_CONTEXT_REG_TYPE2 |
37656 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA0__SHIFT 0x0 |
37657 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA1__SHIFT 0x1 |
37658 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA2__SHIFT 0x2 |
37659 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA3__SHIFT 0x3 |
37660 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA4__SHIFT 0x4 |
37661 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA5__SHIFT 0x5 |
37662 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA6__SHIFT 0x6 |
37663 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA7__SHIFT 0x7 |
37664 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA8__SHIFT 0x8 |
37665 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA9__SHIFT 0x9 |
37666 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA10__SHIFT 0xa |
37667 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_CNTL__SHIFT 0xb |
37668 | #define SDMA2_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xc |
37669 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA0_MASK 0x00000001L |
37670 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA1_MASK 0x00000002L |
37671 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA2_MASK 0x00000004L |
37672 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA3_MASK 0x00000008L |
37673 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA4_MASK 0x00000010L |
37674 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA5_MASK 0x00000020L |
37675 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA6_MASK 0x00000040L |
37676 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA7_MASK 0x00000080L |
37677 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA8_MASK 0x00000100L |
37678 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA9_MASK 0x00000200L |
37679 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_DATA10_MASK 0x00000400L |
37680 | #define SDMA2_CONTEXT_REG_TYPE2__SDMA2_GFX_MIDCMD_CNTL_MASK 0x00000800L |
37681 | #define SDMA2_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFF000L |
37682 | //SDMA2_CONTEXT_REG_TYPE3 |
37683 | #define SDMA2_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 |
37684 | #define SDMA2_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL |
37685 | //SDMA2_PUB_REG_TYPE0 |
37686 | #define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR__SHIFT 0x0 |
37687 | #define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA__SHIFT 0x1 |
37688 | #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_LO__SHIFT 0x2 |
37689 | #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_HI__SHIFT 0x3 |
37690 | #define SDMA2_PUB_REG_TYPE0__SDMA2_ACTIVE_FCN_ID__SHIFT 0x4 |
37691 | #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_CNTL__SHIFT 0x5 |
37692 | #define SDMA2_PUB_REG_TYPE0__SDMA2_VIRT_RESET_REQ__SHIFT 0x6 |
37693 | #define SDMA2_PUB_REG_TYPE0__SDMA2_VF_ENABLE__SHIFT 0x7 |
37694 | #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE0__SHIFT 0x8 |
37695 | #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE1__SHIFT 0x9 |
37696 | #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE2__SHIFT 0xa |
37697 | #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE3__SHIFT 0xb |
37698 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE0__SHIFT 0xc |
37699 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE1__SHIFT 0xd |
37700 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE2__SHIFT 0xe |
37701 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE3__SHIFT 0xf |
37702 | #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CNTL__SHIFT 0x13 |
37703 | #define SDMA2_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 |
37704 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CNTL__SHIFT 0x16 |
37705 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CTX_LO__SHIFT 0x17 |
37706 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CTX_HI__SHIFT 0x18 |
37707 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CTX_CNTL__SHIFT 0x19 |
37708 | #define SDMA2_PUB_REG_TYPE0__SDMA2_POWER_CNTL__SHIFT 0x1a |
37709 | #define SDMA2_PUB_REG_TYPE0__SDMA2_CLK_CTRL__SHIFT 0x1b |
37710 | #define SDMA2_PUB_REG_TYPE0__SDMA2_CNTL__SHIFT 0x1c |
37711 | #define SDMA2_PUB_REG_TYPE0__SDMA2_CHICKEN_BITS__SHIFT 0x1d |
37712 | #define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG__SHIFT 0x1e |
37713 | #define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_READ__SHIFT 0x1f |
37714 | #define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_ADDR_MASK 0x00000001L |
37715 | #define SDMA2_PUB_REG_TYPE0__SDMA2_UCODE_DATA_MASK 0x00000002L |
37716 | #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_LO_MASK 0x00000004L |
37717 | #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_HI_MASK 0x00000008L |
37718 | #define SDMA2_PUB_REG_TYPE0__SDMA2_ACTIVE_FCN_ID_MASK 0x00000010L |
37719 | #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CTX_CNTL_MASK 0x00000020L |
37720 | #define SDMA2_PUB_REG_TYPE0__SDMA2_VIRT_RESET_REQ_MASK 0x00000040L |
37721 | #define SDMA2_PUB_REG_TYPE0__SDMA2_VF_ENABLE_MASK 0x00000080L |
37722 | #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE0_MASK 0x00000100L |
37723 | #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE1_MASK 0x00000200L |
37724 | #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE2_MASK 0x00000400L |
37725 | #define SDMA2_PUB_REG_TYPE0__SDMA2_CONTEXT_REG_TYPE3_MASK 0x00000800L |
37726 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE0_MASK 0x00001000L |
37727 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE1_MASK 0x00002000L |
37728 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE2_MASK 0x00004000L |
37729 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PUB_REG_TYPE3_MASK 0x00008000L |
37730 | #define SDMA2_PUB_REG_TYPE0__SDMA2_VM_CNTL_MASK 0x00080000L |
37731 | #define SDMA2_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x00300000L |
37732 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CNTL_MASK 0x00400000L |
37733 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CTX_LO_MASK 0x00800000L |
37734 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CTX_HI_MASK 0x01000000L |
37735 | #define SDMA2_PUB_REG_TYPE0__SDMA2_PG_CTX_CNTL_MASK 0x02000000L |
37736 | #define SDMA2_PUB_REG_TYPE0__SDMA2_POWER_CNTL_MASK 0x04000000L |
37737 | #define SDMA2_PUB_REG_TYPE0__SDMA2_CLK_CTRL_MASK 0x08000000L |
37738 | #define SDMA2_PUB_REG_TYPE0__SDMA2_CNTL_MASK 0x10000000L |
37739 | #define SDMA2_PUB_REG_TYPE0__SDMA2_CHICKEN_BITS_MASK 0x20000000L |
37740 | #define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_MASK 0x40000000L |
37741 | #define SDMA2_PUB_REG_TYPE0__SDMA2_GB_ADDR_CONFIG_READ_MASK 0x80000000L |
37742 | //SDMA2_PUB_REG_TYPE1 |
37743 | #define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_HI__SHIFT 0x0 |
37744 | #define SDMA2_PUB_REG_TYPE1__SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 |
37745 | #define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH__SHIFT 0x2 |
37746 | #define SDMA2_PUB_REG_TYPE1__SDMA2_IB_OFFSET_FETCH__SHIFT 0x3 |
37747 | #define SDMA2_PUB_REG_TYPE1__SDMA2_PROGRAM__SHIFT 0x4 |
37748 | #define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS_REG__SHIFT 0x5 |
37749 | #define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS1_REG__SHIFT 0x6 |
37750 | #define SDMA2_PUB_REG_TYPE1__SDMA2_RD_BURST_CNTL__SHIFT 0x7 |
37751 | #define SDMA2_PUB_REG_TYPE1__SDMA2_HBM_PAGE_CONFIG__SHIFT 0x8 |
37752 | #define SDMA2_PUB_REG_TYPE1__SDMA2_UCODE_CHECKSUM__SHIFT 0x9 |
37753 | #define SDMA2_PUB_REG_TYPE1__SDMA2_F32_CNTL__SHIFT 0xa |
37754 | #define SDMA2_PUB_REG_TYPE1__SDMA2_FREEZE__SHIFT 0xb |
37755 | #define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE0_QUANTUM__SHIFT 0xc |
37756 | #define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE1_QUANTUM__SHIFT 0xd |
37757 | #define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_CONFIG__SHIFT 0x12 |
37758 | #define SDMA2_PUB_REG_TYPE1__SDMA2_BA_THRESHOLD__SHIFT 0x13 |
37759 | #define SDMA2_PUB_REG_TYPE1__SDMA2_ID__SHIFT 0x14 |
37760 | #define SDMA2_PUB_REG_TYPE1__SDMA2_VERSION__SHIFT 0x15 |
37761 | #define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER__SHIFT 0x16 |
37762 | #define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_CLEAR__SHIFT 0x17 |
37763 | #define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS2_REG__SHIFT 0x18 |
37764 | #define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_CNTL__SHIFT 0x19 |
37765 | #define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_LO__SHIFT 0x1a |
37766 | #define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_HI__SHIFT 0x1b |
37767 | #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_CNTL__SHIFT 0x1c |
37768 | #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WATERMK__SHIFT 0x1d |
37769 | #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_RD_STATUS__SHIFT 0x1e |
37770 | #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WR_STATUS__SHIFT 0x1f |
37771 | #define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_HI_MASK 0x00000001L |
37772 | #define SDMA2_PUB_REG_TYPE1__SDMA2_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L |
37773 | #define SDMA2_PUB_REG_TYPE1__SDMA2_RB_RPTR_FETCH_MASK 0x00000004L |
37774 | #define SDMA2_PUB_REG_TYPE1__SDMA2_IB_OFFSET_FETCH_MASK 0x00000008L |
37775 | #define SDMA2_PUB_REG_TYPE1__SDMA2_PROGRAM_MASK 0x00000010L |
37776 | #define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS_REG_MASK 0x00000020L |
37777 | #define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS1_REG_MASK 0x00000040L |
37778 | #define SDMA2_PUB_REG_TYPE1__SDMA2_RD_BURST_CNTL_MASK 0x00000080L |
37779 | #define SDMA2_PUB_REG_TYPE1__SDMA2_HBM_PAGE_CONFIG_MASK 0x00000100L |
37780 | #define SDMA2_PUB_REG_TYPE1__SDMA2_UCODE_CHECKSUM_MASK 0x00000200L |
37781 | #define SDMA2_PUB_REG_TYPE1__SDMA2_F32_CNTL_MASK 0x00000400L |
37782 | #define SDMA2_PUB_REG_TYPE1__SDMA2_FREEZE_MASK 0x00000800L |
37783 | #define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE0_QUANTUM_MASK 0x00001000L |
37784 | #define SDMA2_PUB_REG_TYPE1__SDMA2_PHASE1_QUANTUM_MASK 0x00002000L |
37785 | #define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_CONFIG_MASK 0x00040000L |
37786 | #define SDMA2_PUB_REG_TYPE1__SDMA2_BA_THRESHOLD_MASK 0x00080000L |
37787 | #define SDMA2_PUB_REG_TYPE1__SDMA2_ID_MASK 0x00100000L |
37788 | #define SDMA2_PUB_REG_TYPE1__SDMA2_VERSION_MASK 0x00200000L |
37789 | #define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_MASK 0x00400000L |
37790 | #define SDMA2_PUB_REG_TYPE1__SDMA2_EDC_COUNTER_CLEAR_MASK 0x00800000L |
37791 | #define SDMA2_PUB_REG_TYPE1__SDMA2_STATUS2_REG_MASK 0x01000000L |
37792 | #define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_CNTL_MASK 0x02000000L |
37793 | #define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_LO_MASK 0x04000000L |
37794 | #define SDMA2_PUB_REG_TYPE1__SDMA2_ATOMIC_PREOP_HI_MASK 0x08000000L |
37795 | #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_CNTL_MASK 0x10000000L |
37796 | #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WATERMK_MASK 0x20000000L |
37797 | #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_RD_STATUS_MASK 0x40000000L |
37798 | #define SDMA2_PUB_REG_TYPE1__SDMA2_UTCL1_WR_STATUS_MASK 0x80000000L |
37799 | //SDMA2_PUB_REG_TYPE2 |
37800 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV0__SHIFT 0x0 |
37801 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV1__SHIFT 0x1 |
37802 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV2__SHIFT 0x2 |
37803 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK0__SHIFT 0x3 |
37804 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK1__SHIFT 0x4 |
37805 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK0__SHIFT 0x5 |
37806 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK1__SHIFT 0x6 |
37807 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_TIMEOUT__SHIFT 0x7 |
37808 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_PAGE__SHIFT 0x8 |
37809 | #define SDMA2_PUB_REG_TYPE2__SDMA2_RELAX_ORDERING_LUT__SHIFT 0xa |
37810 | #define SDMA2_PUB_REG_TYPE2__SDMA2_CHICKEN_BITS_2__SHIFT 0xb |
37811 | #define SDMA2_PUB_REG_TYPE2__SDMA2_STATUS3_REG__SHIFT 0xc |
37812 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_LO__SHIFT 0xd |
37813 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_HI__SHIFT 0xe |
37814 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PHASE2_QUANTUM__SHIFT 0xf |
37815 | #define SDMA2_PUB_REG_TYPE2__SDMA2_ERROR_LOG__SHIFT 0x10 |
37816 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG0__SHIFT 0x11 |
37817 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG1__SHIFT 0x12 |
37818 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG2__SHIFT 0x13 |
37819 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG3__SHIFT 0x14 |
37820 | #define SDMA2_PUB_REG_TYPE2__SDMA2_F32_COUNTER__SHIFT 0x15 |
37821 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_PERFCOUNTER0_CFG__SHIFT 0x17 |
37822 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_PERFCOUNTER1_CFG__SHIFT 0x18 |
37823 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL__SHIFT 0x19 |
37824 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_MISC_CNTL__SHIFT 0x1a |
37825 | #define SDMA2_PUB_REG_TYPE2__SDMA2_CRD_CNTL__SHIFT 0x1b |
37826 | #define SDMA2_PUB_REG_TYPE2__SDMA2_AQL_STATUS__SHIFT 0x1f |
37827 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV0_MASK 0x00000001L |
37828 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV1_MASK 0x00000002L |
37829 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_INV2_MASK 0x00000004L |
37830 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK0_MASK 0x00000008L |
37831 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_RD_XNACK1_MASK 0x00000010L |
37832 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK0_MASK 0x00000020L |
37833 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_WR_XNACK1_MASK 0x00000040L |
37834 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_TIMEOUT_MASK 0x00000080L |
37835 | #define SDMA2_PUB_REG_TYPE2__SDMA2_UTCL1_PAGE_MASK 0x00000100L |
37836 | #define SDMA2_PUB_REG_TYPE2__SDMA2_RELAX_ORDERING_LUT_MASK 0x00000400L |
37837 | #define SDMA2_PUB_REG_TYPE2__SDMA2_CHICKEN_BITS_2_MASK 0x00000800L |
37838 | #define SDMA2_PUB_REG_TYPE2__SDMA2_STATUS3_REG_MASK 0x00001000L |
37839 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_LO_MASK 0x00002000L |
37840 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PHYSICAL_ADDR_HI_MASK 0x00004000L |
37841 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PHASE2_QUANTUM_MASK 0x00008000L |
37842 | #define SDMA2_PUB_REG_TYPE2__SDMA2_ERROR_LOG_MASK 0x00010000L |
37843 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG0_MASK 0x00020000L |
37844 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG1_MASK 0x00040000L |
37845 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG2_MASK 0x00080000L |
37846 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PUB_DUMMY_REG3_MASK 0x00100000L |
37847 | #define SDMA2_PUB_REG_TYPE2__SDMA2_F32_COUNTER_MASK 0x00200000L |
37848 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_PERFCOUNTER0_CFG_MASK 0x00800000L |
37849 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_PERFCOUNTER1_CFG_MASK 0x01000000L |
37850 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_PERFCOUNTER_RSLT_CNTL_MASK 0x02000000L |
37851 | #define SDMA2_PUB_REG_TYPE2__SDMA2_PERFCNT_MISC_CNTL_MASK 0x04000000L |
37852 | #define SDMA2_PUB_REG_TYPE2__SDMA2_CRD_CNTL_MASK 0x08000000L |
37853 | #define SDMA2_PUB_REG_TYPE2__SDMA2_AQL_STATUS_MASK 0x80000000L |
37854 | //SDMA2_PUB_REG_TYPE3 |
37855 | #define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_DATA__SHIFT 0x0 |
37856 | #define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_INDEX__SHIFT 0x1 |
37857 | #define SDMA2_PUB_REG_TYPE3__SDMA2_TLBI_GCR_CNTL__SHIFT 0x2 |
37858 | #define SDMA2_PUB_REG_TYPE3__SDMA2_TILING_CONFIG__SHIFT 0x3 |
37859 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_SELECT__SHIFT 0x8 |
37860 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_SELECT1__SHIFT 0x9 |
37861 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_LO__SHIFT 0xa |
37862 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_HI__SHIFT 0xb |
37863 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_SELECT__SHIFT 0xc |
37864 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_SELECT1__SHIFT 0xd |
37865 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_LO__SHIFT 0xe |
37866 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_HI__SHIFT 0xf |
37867 | #define SDMA2_PUB_REG_TYPE3__SDMA2_INT_STATUS__SHIFT 0x10 |
37868 | #define SDMA2_PUB_REG_TYPE3__SDMA2_HOLE_ADDR_LO__SHIFT 0x12 |
37869 | #define SDMA2_PUB_REG_TYPE3__SDMA2_HOLE_ADDR_HI__SHIFT 0x13 |
37870 | #define SDMA2_PUB_REG_TYPE3__SDMA2_CLOCK_GATING_REG__SHIFT 0x15 |
37871 | #define SDMA2_PUB_REG_TYPE3__SDMA2_STATUS4_REG__SHIFT 0x16 |
37872 | #define SDMA2_PUB_REG_TYPE3__SDMA2_SCRATCH_RAM_DATA__SHIFT 0x17 |
37873 | #define SDMA2_PUB_REG_TYPE3__SDMA2_SCRATCH_RAM_ADDR__SHIFT 0x18 |
37874 | #define SDMA2_PUB_REG_TYPE3__SDMA2_TIMESTAMP_CNTL__SHIFT 0x19 |
37875 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCNT_PERFCOUNTER_LO__SHIFT 0x1a |
37876 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCNT_PERFCOUNTER_HI__SHIFT 0x1b |
37877 | #define SDMA2_PUB_REG_TYPE3__SDMA2_STATUS5_REG__SHIFT 0x1c |
37878 | #define SDMA2_PUB_REG_TYPE3__SDMA2_QUEUE_RESET_REQ__SHIFT 0x1d |
37879 | #define SDMA2_PUB_REG_TYPE3__RESERVED__SHIFT 0x1e |
37880 | #define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_DATA_MASK 0x00000001L |
37881 | #define SDMA2_PUB_REG_TYPE3__SDMA2_EA_DBIT_ADDR_INDEX_MASK 0x00000002L |
37882 | #define SDMA2_PUB_REG_TYPE3__SDMA2_TLBI_GCR_CNTL_MASK 0x00000004L |
37883 | #define SDMA2_PUB_REG_TYPE3__SDMA2_TILING_CONFIG_MASK 0x00000008L |
37884 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_SELECT_MASK 0x00000100L |
37885 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_SELECT1_MASK 0x00000200L |
37886 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_LO_MASK 0x00000400L |
37887 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER0_HI_MASK 0x00000800L |
37888 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_SELECT_MASK 0x00001000L |
37889 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_SELECT1_MASK 0x00002000L |
37890 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_LO_MASK 0x00004000L |
37891 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCOUNTER1_HI_MASK 0x00008000L |
37892 | #define SDMA2_PUB_REG_TYPE3__SDMA2_INT_STATUS_MASK 0x00010000L |
37893 | #define SDMA2_PUB_REG_TYPE3__SDMA2_HOLE_ADDR_LO_MASK 0x00040000L |
37894 | #define SDMA2_PUB_REG_TYPE3__SDMA2_HOLE_ADDR_HI_MASK 0x00080000L |
37895 | #define SDMA2_PUB_REG_TYPE3__SDMA2_CLOCK_GATING_REG_MASK 0x00200000L |
37896 | #define SDMA2_PUB_REG_TYPE3__SDMA2_STATUS4_REG_MASK 0x00400000L |
37897 | #define SDMA2_PUB_REG_TYPE3__SDMA2_SCRATCH_RAM_DATA_MASK 0x00800000L |
37898 | #define SDMA2_PUB_REG_TYPE3__SDMA2_SCRATCH_RAM_ADDR_MASK 0x01000000L |
37899 | #define SDMA2_PUB_REG_TYPE3__SDMA2_TIMESTAMP_CNTL_MASK 0x02000000L |
37900 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCNT_PERFCOUNTER_LO_MASK 0x04000000L |
37901 | #define SDMA2_PUB_REG_TYPE3__SDMA2_PERFCNT_PERFCOUNTER_HI_MASK 0x08000000L |
37902 | #define SDMA2_PUB_REG_TYPE3__SDMA2_STATUS5_REG_MASK 0x10000000L |
37903 | #define SDMA2_PUB_REG_TYPE3__SDMA2_QUEUE_RESET_REQ_MASK 0x20000000L |
37904 | #define SDMA2_PUB_REG_TYPE3__RESERVED_MASK 0xC0000000L |
37905 | //SDMA2_VM_CNTL |
37906 | #define SDMA2_VM_CNTL__CMD__SHIFT 0x0 |
37907 | #define SDMA2_VM_CNTL__CMD_MASK 0x0000000FL |
37908 | |
37909 | |
37910 | // addressBlock: gc_sdma3_sdma3hypdec |
37911 | //SDMA3_UCODE_ADDR |
37912 | #define SDMA3_UCODE_ADDR__VALUE__SHIFT 0x0 |
37913 | #define SDMA3_UCODE_ADDR__VALUE_MASK 0x00003FFFL |
37914 | //SDMA3_UCODE_DATA |
37915 | #define SDMA3_UCODE_DATA__VALUE__SHIFT 0x0 |
37916 | #define SDMA3_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL |
37917 | //SDMA3_VM_CTX_LO |
37918 | #define SDMA3_VM_CTX_LO__ADDR__SHIFT 0x2 |
37919 | #define SDMA3_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL |
37920 | //SDMA3_VM_CTX_HI |
37921 | #define SDMA3_VM_CTX_HI__ADDR__SHIFT 0x0 |
37922 | #define SDMA3_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL |
37923 | //SDMA3_ACTIVE_FCN_ID |
37924 | #define SDMA3_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
37925 | #define SDMA3_ACTIVE_FCN_ID__RESERVED__SHIFT 0x5 |
37926 | #define SDMA3_ACTIVE_FCN_ID__VF__SHIFT 0x1f |
37927 | #define SDMA3_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL |
37928 | #define SDMA3_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFE0L |
37929 | #define SDMA3_ACTIVE_FCN_ID__VF_MASK 0x80000000L |
37930 | //SDMA3_VM_CTX_CNTL |
37931 | #define SDMA3_VM_CTX_CNTL__PRIV__SHIFT 0x0 |
37932 | #define SDMA3_VM_CTX_CNTL__VMID__SHIFT 0x4 |
37933 | #define SDMA3_VM_CTX_CNTL__PRIV_MASK 0x00000001L |
37934 | #define SDMA3_VM_CTX_CNTL__VMID_MASK 0x000000F0L |
37935 | //SDMA3_VIRT_RESET_REQ |
37936 | #define SDMA3_VIRT_RESET_REQ__VF__SHIFT 0x0 |
37937 | #define SDMA3_VIRT_RESET_REQ__PF__SHIFT 0x1f |
37938 | #define SDMA3_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL |
37939 | #define SDMA3_VIRT_RESET_REQ__PF_MASK 0x80000000L |
37940 | //SDMA3_VF_ENABLE |
37941 | #define SDMA3_VF_ENABLE__VF_ENABLE__SHIFT 0x0 |
37942 | #define SDMA3_VF_ENABLE__VF_ENABLE_MASK 0x00000001L |
37943 | //SDMA3_CONTEXT_REG_TYPE0 |
37944 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_CNTL__SHIFT 0x0 |
37945 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE__SHIFT 0x1 |
37946 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_HI__SHIFT 0x2 |
37947 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR__SHIFT 0x3 |
37948 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_HI__SHIFT 0x4 |
37949 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR__SHIFT 0x5 |
37950 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_HI__SHIFT 0x6 |
37951 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 |
37952 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 |
37953 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 |
37954 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_CNTL__SHIFT 0xa |
37955 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_RPTR__SHIFT 0xb |
37956 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_OFFSET__SHIFT 0xc |
37957 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_LO__SHIFT 0xd |
37958 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_HI__SHIFT 0xe |
37959 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_SIZE__SHIFT 0xf |
37960 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_SKIP_CNTL__SHIFT 0x10 |
37961 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_STATUS__SHIFT 0x11 |
37962 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_DOORBELL__SHIFT 0x12 |
37963 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_CNTL__SHIFT 0x13 |
37964 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_CNTL_MASK 0x00000001L |
37965 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_MASK 0x00000002L |
37966 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_BASE_HI_MASK 0x00000004L |
37967 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_MASK 0x00000008L |
37968 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_HI_MASK 0x00000010L |
37969 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_MASK 0x00000020L |
37970 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_HI_MASK 0x00000040L |
37971 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L |
37972 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L |
37973 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L |
37974 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_CNTL_MASK 0x00000400L |
37975 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_RPTR_MASK 0x00000800L |
37976 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_OFFSET_MASK 0x00001000L |
37977 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_LO_MASK 0x00002000L |
37978 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_BASE_HI_MASK 0x00004000L |
37979 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_IB_SIZE_MASK 0x00008000L |
37980 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_SKIP_CNTL_MASK 0x00010000L |
37981 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_STATUS_MASK 0x00020000L |
37982 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_DOORBELL_MASK 0x00040000L |
37983 | #define SDMA3_CONTEXT_REG_TYPE0__SDMA3_GFX_CONTEXT_CNTL_MASK 0x00080000L |
37984 | //SDMA3_CONTEXT_REG_TYPE1 |
37985 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_STATUS__SHIFT 0x8 |
37986 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_LOG__SHIFT 0x9 |
37987 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_WATERMARK__SHIFT 0xa |
37988 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_OFFSET__SHIFT 0xb |
37989 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_LO__SHIFT 0xc |
37990 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_HI__SHIFT 0xd |
37991 | #define SDMA3_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe |
37992 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_IB_SUB_REMAIN__SHIFT 0xf |
37993 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_PREEMPT__SHIFT 0x10 |
37994 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DUMMY_REG__SHIFT 0x11 |
37995 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 |
37996 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 |
37997 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_AQL_CNTL__SHIFT 0x14 |
37998 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 |
37999 | #define SDMA3_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x18 |
38000 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_STATUS_MASK 0x00000100L |
38001 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_LOG_MASK 0x00000200L |
38002 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_WATERMARK_MASK 0x00000400L |
38003 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DOORBELL_OFFSET_MASK 0x00000800L |
38004 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_LO_MASK 0x00001000L |
38005 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_CSA_ADDR_HI_MASK 0x00002000L |
38006 | #define SDMA3_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L |
38007 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_IB_SUB_REMAIN_MASK 0x00008000L |
38008 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_PREEMPT_MASK 0x00010000L |
38009 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_DUMMY_REG_MASK 0x00020000L |
38010 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L |
38011 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L |
38012 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_RB_AQL_CNTL_MASK 0x00100000L |
38013 | #define SDMA3_CONTEXT_REG_TYPE1__SDMA3_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L |
38014 | #define SDMA3_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFF000000L |
38015 | //SDMA3_CONTEXT_REG_TYPE2 |
38016 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA0__SHIFT 0x0 |
38017 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA1__SHIFT 0x1 |
38018 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA2__SHIFT 0x2 |
38019 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA3__SHIFT 0x3 |
38020 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA4__SHIFT 0x4 |
38021 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA5__SHIFT 0x5 |
38022 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA6__SHIFT 0x6 |
38023 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA7__SHIFT 0x7 |
38024 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA8__SHIFT 0x8 |
38025 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA9__SHIFT 0x9 |
38026 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA10__SHIFT 0xa |
38027 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_CNTL__SHIFT 0xb |
38028 | #define SDMA3_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xc |
38029 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA0_MASK 0x00000001L |
38030 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA1_MASK 0x00000002L |
38031 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA2_MASK 0x00000004L |
38032 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA3_MASK 0x00000008L |
38033 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA4_MASK 0x00000010L |
38034 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA5_MASK 0x00000020L |
38035 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA6_MASK 0x00000040L |
38036 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA7_MASK 0x00000080L |
38037 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA8_MASK 0x00000100L |
38038 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA9_MASK 0x00000200L |
38039 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_DATA10_MASK 0x00000400L |
38040 | #define SDMA3_CONTEXT_REG_TYPE2__SDMA3_GFX_MIDCMD_CNTL_MASK 0x00000800L |
38041 | #define SDMA3_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFF000L |
38042 | //SDMA3_CONTEXT_REG_TYPE3 |
38043 | #define SDMA3_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 |
38044 | #define SDMA3_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL |
38045 | //SDMA3_PUB_REG_TYPE0 |
38046 | #define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR__SHIFT 0x0 |
38047 | #define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA__SHIFT 0x1 |
38048 | #define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_LO__SHIFT 0x2 |
38049 | #define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_HI__SHIFT 0x3 |
38050 | #define SDMA3_PUB_REG_TYPE0__SDMA3_ACTIVE_FCN_ID__SHIFT 0x4 |
38051 | #define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_CNTL__SHIFT 0x5 |
38052 | #define SDMA3_PUB_REG_TYPE0__SDMA3_VIRT_RESET_REQ__SHIFT 0x6 |
38053 | #define SDMA3_PUB_REG_TYPE0__SDMA3_VF_ENABLE__SHIFT 0x7 |
38054 | #define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE0__SHIFT 0x8 |
38055 | #define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE1__SHIFT 0x9 |
38056 | #define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE2__SHIFT 0xa |
38057 | #define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE3__SHIFT 0xb |
38058 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE0__SHIFT 0xc |
38059 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE1__SHIFT 0xd |
38060 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE2__SHIFT 0xe |
38061 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE3__SHIFT 0xf |
38062 | #define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CNTL__SHIFT 0x13 |
38063 | #define SDMA3_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 |
38064 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CNTL__SHIFT 0x16 |
38065 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CTX_LO__SHIFT 0x17 |
38066 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CTX_HI__SHIFT 0x18 |
38067 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CTX_CNTL__SHIFT 0x19 |
38068 | #define SDMA3_PUB_REG_TYPE0__SDMA3_POWER_CNTL__SHIFT 0x1a |
38069 | #define SDMA3_PUB_REG_TYPE0__SDMA3_CLK_CTRL__SHIFT 0x1b |
38070 | #define SDMA3_PUB_REG_TYPE0__SDMA3_CNTL__SHIFT 0x1c |
38071 | #define SDMA3_PUB_REG_TYPE0__SDMA3_CHICKEN_BITS__SHIFT 0x1d |
38072 | #define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG__SHIFT 0x1e |
38073 | #define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_READ__SHIFT 0x1f |
38074 | #define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_ADDR_MASK 0x00000001L |
38075 | #define SDMA3_PUB_REG_TYPE0__SDMA3_UCODE_DATA_MASK 0x00000002L |
38076 | #define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_LO_MASK 0x00000004L |
38077 | #define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_HI_MASK 0x00000008L |
38078 | #define SDMA3_PUB_REG_TYPE0__SDMA3_ACTIVE_FCN_ID_MASK 0x00000010L |
38079 | #define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CTX_CNTL_MASK 0x00000020L |
38080 | #define SDMA3_PUB_REG_TYPE0__SDMA3_VIRT_RESET_REQ_MASK 0x00000040L |
38081 | #define SDMA3_PUB_REG_TYPE0__SDMA3_VF_ENABLE_MASK 0x00000080L |
38082 | #define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE0_MASK 0x00000100L |
38083 | #define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE1_MASK 0x00000200L |
38084 | #define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE2_MASK 0x00000400L |
38085 | #define SDMA3_PUB_REG_TYPE0__SDMA3_CONTEXT_REG_TYPE3_MASK 0x00000800L |
38086 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE0_MASK 0x00001000L |
38087 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE1_MASK 0x00002000L |
38088 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE2_MASK 0x00004000L |
38089 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PUB_REG_TYPE3_MASK 0x00008000L |
38090 | #define SDMA3_PUB_REG_TYPE0__SDMA3_VM_CNTL_MASK 0x00080000L |
38091 | #define SDMA3_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x00300000L |
38092 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CNTL_MASK 0x00400000L |
38093 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CTX_LO_MASK 0x00800000L |
38094 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CTX_HI_MASK 0x01000000L |
38095 | #define SDMA3_PUB_REG_TYPE0__SDMA3_PG_CTX_CNTL_MASK 0x02000000L |
38096 | #define SDMA3_PUB_REG_TYPE0__SDMA3_POWER_CNTL_MASK 0x04000000L |
38097 | #define SDMA3_PUB_REG_TYPE0__SDMA3_CLK_CTRL_MASK 0x08000000L |
38098 | #define SDMA3_PUB_REG_TYPE0__SDMA3_CNTL_MASK 0x10000000L |
38099 | #define SDMA3_PUB_REG_TYPE0__SDMA3_CHICKEN_BITS_MASK 0x20000000L |
38100 | #define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_MASK 0x40000000L |
38101 | #define SDMA3_PUB_REG_TYPE0__SDMA3_GB_ADDR_CONFIG_READ_MASK 0x80000000L |
38102 | //SDMA3_PUB_REG_TYPE1 |
38103 | #define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_HI__SHIFT 0x0 |
38104 | #define SDMA3_PUB_REG_TYPE1__SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 |
38105 | #define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH__SHIFT 0x2 |
38106 | #define SDMA3_PUB_REG_TYPE1__SDMA3_IB_OFFSET_FETCH__SHIFT 0x3 |
38107 | #define SDMA3_PUB_REG_TYPE1__SDMA3_PROGRAM__SHIFT 0x4 |
38108 | #define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS_REG__SHIFT 0x5 |
38109 | #define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS1_REG__SHIFT 0x6 |
38110 | #define SDMA3_PUB_REG_TYPE1__SDMA3_RD_BURST_CNTL__SHIFT 0x7 |
38111 | #define SDMA3_PUB_REG_TYPE1__SDMA3_HBM_PAGE_CONFIG__SHIFT 0x8 |
38112 | #define SDMA3_PUB_REG_TYPE1__SDMA3_UCODE_CHECKSUM__SHIFT 0x9 |
38113 | #define SDMA3_PUB_REG_TYPE1__SDMA3_F32_CNTL__SHIFT 0xa |
38114 | #define SDMA3_PUB_REG_TYPE1__SDMA3_FREEZE__SHIFT 0xb |
38115 | #define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE0_QUANTUM__SHIFT 0xc |
38116 | #define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE1_QUANTUM__SHIFT 0xd |
38117 | #define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_CONFIG__SHIFT 0x12 |
38118 | #define SDMA3_PUB_REG_TYPE1__SDMA3_BA_THRESHOLD__SHIFT 0x13 |
38119 | #define SDMA3_PUB_REG_TYPE1__SDMA3_ID__SHIFT 0x14 |
38120 | #define SDMA3_PUB_REG_TYPE1__SDMA3_VERSION__SHIFT 0x15 |
38121 | #define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER__SHIFT 0x16 |
38122 | #define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_CLEAR__SHIFT 0x17 |
38123 | #define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS2_REG__SHIFT 0x18 |
38124 | #define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_CNTL__SHIFT 0x19 |
38125 | #define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_LO__SHIFT 0x1a |
38126 | #define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_HI__SHIFT 0x1b |
38127 | #define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_CNTL__SHIFT 0x1c |
38128 | #define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WATERMK__SHIFT 0x1d |
38129 | #define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_RD_STATUS__SHIFT 0x1e |
38130 | #define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WR_STATUS__SHIFT 0x1f |
38131 | #define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_HI_MASK 0x00000001L |
38132 | #define SDMA3_PUB_REG_TYPE1__SDMA3_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L |
38133 | #define SDMA3_PUB_REG_TYPE1__SDMA3_RB_RPTR_FETCH_MASK 0x00000004L |
38134 | #define SDMA3_PUB_REG_TYPE1__SDMA3_IB_OFFSET_FETCH_MASK 0x00000008L |
38135 | #define SDMA3_PUB_REG_TYPE1__SDMA3_PROGRAM_MASK 0x00000010L |
38136 | #define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS_REG_MASK 0x00000020L |
38137 | #define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS1_REG_MASK 0x00000040L |
38138 | #define SDMA3_PUB_REG_TYPE1__SDMA3_RD_BURST_CNTL_MASK 0x00000080L |
38139 | #define SDMA3_PUB_REG_TYPE1__SDMA3_HBM_PAGE_CONFIG_MASK 0x00000100L |
38140 | #define SDMA3_PUB_REG_TYPE1__SDMA3_UCODE_CHECKSUM_MASK 0x00000200L |
38141 | #define SDMA3_PUB_REG_TYPE1__SDMA3_F32_CNTL_MASK 0x00000400L |
38142 | #define SDMA3_PUB_REG_TYPE1__SDMA3_FREEZE_MASK 0x00000800L |
38143 | #define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE0_QUANTUM_MASK 0x00001000L |
38144 | #define SDMA3_PUB_REG_TYPE1__SDMA3_PHASE1_QUANTUM_MASK 0x00002000L |
38145 | #define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_CONFIG_MASK 0x00040000L |
38146 | #define SDMA3_PUB_REG_TYPE1__SDMA3_BA_THRESHOLD_MASK 0x00080000L |
38147 | #define SDMA3_PUB_REG_TYPE1__SDMA3_ID_MASK 0x00100000L |
38148 | #define SDMA3_PUB_REG_TYPE1__SDMA3_VERSION_MASK 0x00200000L |
38149 | #define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_MASK 0x00400000L |
38150 | #define SDMA3_PUB_REG_TYPE1__SDMA3_EDC_COUNTER_CLEAR_MASK 0x00800000L |
38151 | #define SDMA3_PUB_REG_TYPE1__SDMA3_STATUS2_REG_MASK 0x01000000L |
38152 | #define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_CNTL_MASK 0x02000000L |
38153 | #define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_LO_MASK 0x04000000L |
38154 | #define SDMA3_PUB_REG_TYPE1__SDMA3_ATOMIC_PREOP_HI_MASK 0x08000000L |
38155 | #define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_CNTL_MASK 0x10000000L |
38156 | #define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WATERMK_MASK 0x20000000L |
38157 | #define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_RD_STATUS_MASK 0x40000000L |
38158 | #define SDMA3_PUB_REG_TYPE1__SDMA3_UTCL1_WR_STATUS_MASK 0x80000000L |
38159 | //SDMA3_PUB_REG_TYPE2 |
38160 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV0__SHIFT 0x0 |
38161 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV1__SHIFT 0x1 |
38162 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV2__SHIFT 0x2 |
38163 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK0__SHIFT 0x3 |
38164 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK1__SHIFT 0x4 |
38165 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK0__SHIFT 0x5 |
38166 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK1__SHIFT 0x6 |
38167 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_TIMEOUT__SHIFT 0x7 |
38168 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_PAGE__SHIFT 0x8 |
38169 | #define SDMA3_PUB_REG_TYPE2__SDMA3_RELAX_ORDERING_LUT__SHIFT 0xa |
38170 | #define SDMA3_PUB_REG_TYPE2__SDMA3_CHICKEN_BITS_2__SHIFT 0xb |
38171 | #define SDMA3_PUB_REG_TYPE2__SDMA3_STATUS3_REG__SHIFT 0xc |
38172 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_LO__SHIFT 0xd |
38173 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_HI__SHIFT 0xe |
38174 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PHASE2_QUANTUM__SHIFT 0xf |
38175 | #define SDMA3_PUB_REG_TYPE2__SDMA3_ERROR_LOG__SHIFT 0x10 |
38176 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG0__SHIFT 0x11 |
38177 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG1__SHIFT 0x12 |
38178 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG2__SHIFT 0x13 |
38179 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG3__SHIFT 0x14 |
38180 | #define SDMA3_PUB_REG_TYPE2__SDMA3_F32_COUNTER__SHIFT 0x15 |
38181 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_PERFCOUNTER0_CFG__SHIFT 0x17 |
38182 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_PERFCOUNTER1_CFG__SHIFT 0x18 |
38183 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL__SHIFT 0x19 |
38184 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_MISC_CNTL__SHIFT 0x1a |
38185 | #define SDMA3_PUB_REG_TYPE2__SDMA3_CRD_CNTL__SHIFT 0x1b |
38186 | #define SDMA3_PUB_REG_TYPE2__SDMA3_AQL_STATUS__SHIFT 0x1f |
38187 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV0_MASK 0x00000001L |
38188 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV1_MASK 0x00000002L |
38189 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_INV2_MASK 0x00000004L |
38190 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK0_MASK 0x00000008L |
38191 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_RD_XNACK1_MASK 0x00000010L |
38192 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK0_MASK 0x00000020L |
38193 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_WR_XNACK1_MASK 0x00000040L |
38194 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_TIMEOUT_MASK 0x00000080L |
38195 | #define SDMA3_PUB_REG_TYPE2__SDMA3_UTCL1_PAGE_MASK 0x00000100L |
38196 | #define SDMA3_PUB_REG_TYPE2__SDMA3_RELAX_ORDERING_LUT_MASK 0x00000400L |
38197 | #define SDMA3_PUB_REG_TYPE2__SDMA3_CHICKEN_BITS_2_MASK 0x00000800L |
38198 | #define SDMA3_PUB_REG_TYPE2__SDMA3_STATUS3_REG_MASK 0x00001000L |
38199 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_LO_MASK 0x00002000L |
38200 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PHYSICAL_ADDR_HI_MASK 0x00004000L |
38201 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PHASE2_QUANTUM_MASK 0x00008000L |
38202 | #define SDMA3_PUB_REG_TYPE2__SDMA3_ERROR_LOG_MASK 0x00010000L |
38203 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG0_MASK 0x00020000L |
38204 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG1_MASK 0x00040000L |
38205 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG2_MASK 0x00080000L |
38206 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PUB_DUMMY_REG3_MASK 0x00100000L |
38207 | #define SDMA3_PUB_REG_TYPE2__SDMA3_F32_COUNTER_MASK 0x00200000L |
38208 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_PERFCOUNTER0_CFG_MASK 0x00800000L |
38209 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_PERFCOUNTER1_CFG_MASK 0x01000000L |
38210 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_PERFCOUNTER_RSLT_CNTL_MASK 0x02000000L |
38211 | #define SDMA3_PUB_REG_TYPE2__SDMA3_PERFCNT_MISC_CNTL_MASK 0x04000000L |
38212 | #define SDMA3_PUB_REG_TYPE2__SDMA3_CRD_CNTL_MASK 0x08000000L |
38213 | #define SDMA3_PUB_REG_TYPE2__SDMA3_AQL_STATUS_MASK 0x80000000L |
38214 | //SDMA3_PUB_REG_TYPE3 |
38215 | #define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_DATA__SHIFT 0x0 |
38216 | #define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_INDEX__SHIFT 0x1 |
38217 | #define SDMA3_PUB_REG_TYPE3__SDMA3_TLBI_GCR_CNTL__SHIFT 0x2 |
38218 | #define SDMA3_PUB_REG_TYPE3__SDMA3_TILING_CONFIG__SHIFT 0x3 |
38219 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_SELECT__SHIFT 0x8 |
38220 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_SELECT1__SHIFT 0x9 |
38221 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_LO__SHIFT 0xa |
38222 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_HI__SHIFT 0xb |
38223 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_SELECT__SHIFT 0xc |
38224 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_SELECT1__SHIFT 0xd |
38225 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_LO__SHIFT 0xe |
38226 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_HI__SHIFT 0xf |
38227 | #define SDMA3_PUB_REG_TYPE3__SDMA3_INT_STATUS__SHIFT 0x10 |
38228 | #define SDMA3_PUB_REG_TYPE3__SDMA3_HOLE_ADDR_LO__SHIFT 0x12 |
38229 | #define SDMA3_PUB_REG_TYPE3__SDMA3_HOLE_ADDR_HI__SHIFT 0x13 |
38230 | #define SDMA3_PUB_REG_TYPE3__SDMA3_CLOCK_GATING_REG__SHIFT 0x15 |
38231 | #define SDMA3_PUB_REG_TYPE3__SDMA3_STATUS4_REG__SHIFT 0x16 |
38232 | #define SDMA3_PUB_REG_TYPE3__SDMA3_SCRATCH_RAM_DATA__SHIFT 0x17 |
38233 | #define SDMA3_PUB_REG_TYPE3__SDMA3_SCRATCH_RAM_ADDR__SHIFT 0x18 |
38234 | #define SDMA3_PUB_REG_TYPE3__SDMA3_TIMESTAMP_CNTL__SHIFT 0x19 |
38235 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCNT_PERFCOUNTER_LO__SHIFT 0x1a |
38236 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCNT_PERFCOUNTER_HI__SHIFT 0x1b |
38237 | #define SDMA3_PUB_REG_TYPE3__SDMA3_STATUS5_REG__SHIFT 0x1c |
38238 | #define SDMA3_PUB_REG_TYPE3__SDMA3_QUEUE_RESET_REQ__SHIFT 0x1d |
38239 | #define SDMA3_PUB_REG_TYPE3__RESERVED__SHIFT 0x1e |
38240 | #define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_DATA_MASK 0x00000001L |
38241 | #define SDMA3_PUB_REG_TYPE3__SDMA3_EA_DBIT_ADDR_INDEX_MASK 0x00000002L |
38242 | #define SDMA3_PUB_REG_TYPE3__SDMA3_TLBI_GCR_CNTL_MASK 0x00000004L |
38243 | #define SDMA3_PUB_REG_TYPE3__SDMA3_TILING_CONFIG_MASK 0x00000008L |
38244 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_SELECT_MASK 0x00000100L |
38245 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_SELECT1_MASK 0x00000200L |
38246 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_LO_MASK 0x00000400L |
38247 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER0_HI_MASK 0x00000800L |
38248 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_SELECT_MASK 0x00001000L |
38249 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_SELECT1_MASK 0x00002000L |
38250 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_LO_MASK 0x00004000L |
38251 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCOUNTER1_HI_MASK 0x00008000L |
38252 | #define SDMA3_PUB_REG_TYPE3__SDMA3_INT_STATUS_MASK 0x00010000L |
38253 | #define SDMA3_PUB_REG_TYPE3__SDMA3_HOLE_ADDR_LO_MASK 0x00040000L |
38254 | #define SDMA3_PUB_REG_TYPE3__SDMA3_HOLE_ADDR_HI_MASK 0x00080000L |
38255 | #define SDMA3_PUB_REG_TYPE3__SDMA3_CLOCK_GATING_REG_MASK 0x00200000L |
38256 | #define SDMA3_PUB_REG_TYPE3__SDMA3_STATUS4_REG_MASK 0x00400000L |
38257 | #define SDMA3_PUB_REG_TYPE3__SDMA3_SCRATCH_RAM_DATA_MASK 0x00800000L |
38258 | #define SDMA3_PUB_REG_TYPE3__SDMA3_SCRATCH_RAM_ADDR_MASK 0x01000000L |
38259 | #define SDMA3_PUB_REG_TYPE3__SDMA3_TIMESTAMP_CNTL_MASK 0x02000000L |
38260 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCNT_PERFCOUNTER_LO_MASK 0x04000000L |
38261 | #define SDMA3_PUB_REG_TYPE3__SDMA3_PERFCNT_PERFCOUNTER_HI_MASK 0x08000000L |
38262 | #define SDMA3_PUB_REG_TYPE3__SDMA3_STATUS5_REG_MASK 0x10000000L |
38263 | #define SDMA3_PUB_REG_TYPE3__SDMA3_QUEUE_RESET_REQ_MASK 0x20000000L |
38264 | #define SDMA3_PUB_REG_TYPE3__RESERVED_MASK 0xC0000000L |
38265 | //SDMA3_VM_CNTL |
38266 | #define SDMA3_VM_CNTL__CMD__SHIFT 0x0 |
38267 | #define SDMA3_VM_CNTL__CMD_MASK 0x0000000FL |
38268 | |
38269 | |
38270 | // addressBlock: gc_gcvmsharedhvdec |
38271 | //GCMC_VM_FB_SIZE_OFFSET_VF0 |
38272 | #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 |
38273 | #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 |
38274 | #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL |
38275 | #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L |
38276 | //GCMC_VM_FB_SIZE_OFFSET_VF1 |
38277 | #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 |
38278 | #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 |
38279 | #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL |
38280 | #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L |
38281 | //GCMC_VM_FB_SIZE_OFFSET_VF2 |
38282 | #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 |
38283 | #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 |
38284 | #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL |
38285 | #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L |
38286 | //GCMC_VM_FB_SIZE_OFFSET_VF3 |
38287 | #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 |
38288 | #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 |
38289 | #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL |
38290 | #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L |
38291 | //GCMC_VM_FB_SIZE_OFFSET_VF4 |
38292 | #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 |
38293 | #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 |
38294 | #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL |
38295 | #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L |
38296 | //GCMC_VM_FB_SIZE_OFFSET_VF5 |
38297 | #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 |
38298 | #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 |
38299 | #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL |
38300 | #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L |
38301 | //GCMC_VM_FB_SIZE_OFFSET_VF6 |
38302 | #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 |
38303 | #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 |
38304 | #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL |
38305 | #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L |
38306 | //GCMC_VM_FB_SIZE_OFFSET_VF7 |
38307 | #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 |
38308 | #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 |
38309 | #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL |
38310 | #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L |
38311 | //GCMC_VM_FB_SIZE_OFFSET_VF8 |
38312 | #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 |
38313 | #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 |
38314 | #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL |
38315 | #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L |
38316 | //GCMC_VM_FB_SIZE_OFFSET_VF9 |
38317 | #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 |
38318 | #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 |
38319 | #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL |
38320 | #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L |
38321 | //GCMC_VM_FB_SIZE_OFFSET_VF10 |
38322 | #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 |
38323 | #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 |
38324 | #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL |
38325 | #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L |
38326 | //GCMC_VM_FB_SIZE_OFFSET_VF11 |
38327 | #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 |
38328 | #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 |
38329 | #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL |
38330 | #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L |
38331 | //GCMC_VM_FB_SIZE_OFFSET_VF12 |
38332 | #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 |
38333 | #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 |
38334 | #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL |
38335 | #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L |
38336 | //GCMC_VM_FB_SIZE_OFFSET_VF13 |
38337 | #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 |
38338 | #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 |
38339 | #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL |
38340 | #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L |
38341 | //GCMC_VM_FB_SIZE_OFFSET_VF14 |
38342 | #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 |
38343 | #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 |
38344 | #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL |
38345 | #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L |
38346 | //GCMC_VM_FB_SIZE_OFFSET_VF15 |
38347 | #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 |
38348 | #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 |
38349 | #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL |
38350 | #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L |
38351 | //GCMC_VM_FB_SIZE_OFFSET_VF16 |
38352 | #define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE__SHIFT 0x0 |
38353 | #define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET__SHIFT 0x10 |
38354 | #define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_SIZE_MASK 0x0000FFFFL |
38355 | #define GCMC_VM_FB_SIZE_OFFSET_VF16__VF_FB_OFFSET_MASK 0xFFFF0000L |
38356 | //GCMC_VM_FB_SIZE_OFFSET_VF17 |
38357 | #define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE__SHIFT 0x0 |
38358 | #define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET__SHIFT 0x10 |
38359 | #define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_SIZE_MASK 0x0000FFFFL |
38360 | #define GCMC_VM_FB_SIZE_OFFSET_VF17__VF_FB_OFFSET_MASK 0xFFFF0000L |
38361 | //GCMC_VM_FB_SIZE_OFFSET_VF18 |
38362 | #define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE__SHIFT 0x0 |
38363 | #define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET__SHIFT 0x10 |
38364 | #define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_SIZE_MASK 0x0000FFFFL |
38365 | #define GCMC_VM_FB_SIZE_OFFSET_VF18__VF_FB_OFFSET_MASK 0xFFFF0000L |
38366 | //GCMC_VM_FB_SIZE_OFFSET_VF19 |
38367 | #define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE__SHIFT 0x0 |
38368 | #define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET__SHIFT 0x10 |
38369 | #define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_SIZE_MASK 0x0000FFFFL |
38370 | #define GCMC_VM_FB_SIZE_OFFSET_VF19__VF_FB_OFFSET_MASK 0xFFFF0000L |
38371 | //GCMC_VM_FB_SIZE_OFFSET_VF20 |
38372 | #define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE__SHIFT 0x0 |
38373 | #define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET__SHIFT 0x10 |
38374 | #define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_SIZE_MASK 0x0000FFFFL |
38375 | #define GCMC_VM_FB_SIZE_OFFSET_VF20__VF_FB_OFFSET_MASK 0xFFFF0000L |
38376 | //GCMC_VM_FB_SIZE_OFFSET_VF21 |
38377 | #define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE__SHIFT 0x0 |
38378 | #define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET__SHIFT 0x10 |
38379 | #define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_SIZE_MASK 0x0000FFFFL |
38380 | #define GCMC_VM_FB_SIZE_OFFSET_VF21__VF_FB_OFFSET_MASK 0xFFFF0000L |
38381 | //GCMC_VM_FB_SIZE_OFFSET_VF22 |
38382 | #define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE__SHIFT 0x0 |
38383 | #define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET__SHIFT 0x10 |
38384 | #define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_SIZE_MASK 0x0000FFFFL |
38385 | #define GCMC_VM_FB_SIZE_OFFSET_VF22__VF_FB_OFFSET_MASK 0xFFFF0000L |
38386 | //GCMC_VM_FB_SIZE_OFFSET_VF23 |
38387 | #define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE__SHIFT 0x0 |
38388 | #define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET__SHIFT 0x10 |
38389 | #define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_SIZE_MASK 0x0000FFFFL |
38390 | #define GCMC_VM_FB_SIZE_OFFSET_VF23__VF_FB_OFFSET_MASK 0xFFFF0000L |
38391 | //GCMC_VM_FB_SIZE_OFFSET_VF24 |
38392 | #define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE__SHIFT 0x0 |
38393 | #define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET__SHIFT 0x10 |
38394 | #define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_SIZE_MASK 0x0000FFFFL |
38395 | #define GCMC_VM_FB_SIZE_OFFSET_VF24__VF_FB_OFFSET_MASK 0xFFFF0000L |
38396 | //GCMC_VM_FB_SIZE_OFFSET_VF25 |
38397 | #define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE__SHIFT 0x0 |
38398 | #define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET__SHIFT 0x10 |
38399 | #define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_SIZE_MASK 0x0000FFFFL |
38400 | #define GCMC_VM_FB_SIZE_OFFSET_VF25__VF_FB_OFFSET_MASK 0xFFFF0000L |
38401 | //GCMC_VM_FB_SIZE_OFFSET_VF26 |
38402 | #define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE__SHIFT 0x0 |
38403 | #define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET__SHIFT 0x10 |
38404 | #define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_SIZE_MASK 0x0000FFFFL |
38405 | #define GCMC_VM_FB_SIZE_OFFSET_VF26__VF_FB_OFFSET_MASK 0xFFFF0000L |
38406 | //GCMC_VM_FB_SIZE_OFFSET_VF27 |
38407 | #define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE__SHIFT 0x0 |
38408 | #define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET__SHIFT 0x10 |
38409 | #define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_SIZE_MASK 0x0000FFFFL |
38410 | #define GCMC_VM_FB_SIZE_OFFSET_VF27__VF_FB_OFFSET_MASK 0xFFFF0000L |
38411 | //GCMC_VM_FB_SIZE_OFFSET_VF28 |
38412 | #define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE__SHIFT 0x0 |
38413 | #define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET__SHIFT 0x10 |
38414 | #define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_SIZE_MASK 0x0000FFFFL |
38415 | #define GCMC_VM_FB_SIZE_OFFSET_VF28__VF_FB_OFFSET_MASK 0xFFFF0000L |
38416 | //GCMC_VM_FB_SIZE_OFFSET_VF29 |
38417 | #define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE__SHIFT 0x0 |
38418 | #define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET__SHIFT 0x10 |
38419 | #define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_SIZE_MASK 0x0000FFFFL |
38420 | #define GCMC_VM_FB_SIZE_OFFSET_VF29__VF_FB_OFFSET_MASK 0xFFFF0000L |
38421 | //GCMC_VM_FB_SIZE_OFFSET_VF30 |
38422 | #define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE__SHIFT 0x0 |
38423 | #define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET__SHIFT 0x10 |
38424 | #define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_SIZE_MASK 0x0000FFFFL |
38425 | #define GCMC_VM_FB_SIZE_OFFSET_VF30__VF_FB_OFFSET_MASK 0xFFFF0000L |
38426 | //GCMC_VM_FB_SIZE_OFFSET_VF31 |
38427 | #define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE__SHIFT 0x0 |
38428 | #define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET__SHIFT 0x10 |
38429 | #define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_SIZE_MASK 0x0000FFFFL |
38430 | #define GCMC_VM_FB_SIZE_OFFSET_VF31__VF_FB_OFFSET_MASK 0xFFFF0000L |
38431 | //GCVM_IOMMU_MMIO_CNTRL_1 |
38432 | #define GCVM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 |
38433 | #define GCVM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L |
38434 | //GCMC_VM_MARC_BASE_LO_0 |
38435 | #define GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc |
38436 | #define GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L |
38437 | //GCMC_VM_MARC_BASE_LO_1 |
38438 | #define GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc |
38439 | #define GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L |
38440 | //GCMC_VM_MARC_BASE_LO_2 |
38441 | #define GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc |
38442 | #define GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L |
38443 | //GCMC_VM_MARC_BASE_LO_3 |
38444 | #define GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc |
38445 | #define GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L |
38446 | //GCMC_VM_MARC_BASE_HI_0 |
38447 | #define GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 |
38448 | #define GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL |
38449 | //GCMC_VM_MARC_BASE_HI_1 |
38450 | #define GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 |
38451 | #define GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL |
38452 | //GCMC_VM_MARC_BASE_HI_2 |
38453 | #define GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 |
38454 | #define GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL |
38455 | //GCMC_VM_MARC_BASE_HI_3 |
38456 | #define GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 |
38457 | #define GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL |
38458 | //GCMC_VM_MARC_RELOC_LO_0 |
38459 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 |
38460 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 |
38461 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc |
38462 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L |
38463 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L |
38464 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L |
38465 | //GCMC_VM_MARC_RELOC_LO_1 |
38466 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 |
38467 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 |
38468 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc |
38469 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L |
38470 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L |
38471 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L |
38472 | //GCMC_VM_MARC_RELOC_LO_2 |
38473 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 |
38474 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 |
38475 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc |
38476 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L |
38477 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L |
38478 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L |
38479 | //GCMC_VM_MARC_RELOC_LO_3 |
38480 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 |
38481 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 |
38482 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc |
38483 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L |
38484 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L |
38485 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L |
38486 | //GCMC_VM_MARC_RELOC_HI_0 |
38487 | #define GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 |
38488 | #define GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL |
38489 | //GCMC_VM_MARC_RELOC_HI_1 |
38490 | #define GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 |
38491 | #define GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL |
38492 | //GCMC_VM_MARC_RELOC_HI_2 |
38493 | #define GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 |
38494 | #define GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL |
38495 | //GCMC_VM_MARC_RELOC_HI_3 |
38496 | #define GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 |
38497 | #define GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL |
38498 | //GCMC_VM_MARC_LEN_LO_0 |
38499 | #define GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc |
38500 | #define GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L |
38501 | //GCMC_VM_MARC_LEN_LO_1 |
38502 | #define GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc |
38503 | #define GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L |
38504 | //GCMC_VM_MARC_LEN_LO_2 |
38505 | #define GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc |
38506 | #define GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L |
38507 | //GCMC_VM_MARC_LEN_LO_3 |
38508 | #define GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc |
38509 | #define GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L |
38510 | //GCMC_VM_MARC_LEN_HI_0 |
38511 | #define GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 |
38512 | #define GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL |
38513 | //GCMC_VM_MARC_LEN_HI_1 |
38514 | #define GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 |
38515 | #define GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL |
38516 | //GCMC_VM_MARC_LEN_HI_2 |
38517 | #define GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 |
38518 | #define GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL |
38519 | //GCMC_VM_MARC_LEN_HI_3 |
38520 | #define GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 |
38521 | #define GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL |
38522 | //GCVM_IOMMU_CONTROL_REGISTER |
38523 | #define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 |
38524 | #define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L |
38525 | //GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER |
38526 | #define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd |
38527 | #define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L |
38528 | //GCMC_VM_XGMI_GPUIOV_ENABLE |
38529 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 |
38530 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 |
38531 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 |
38532 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 |
38533 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 |
38534 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 |
38535 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 |
38536 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 |
38537 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8 |
38538 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9 |
38539 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa |
38540 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb |
38541 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc |
38542 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd |
38543 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe |
38544 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf |
38545 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF16__SHIFT 0x10 |
38546 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF17__SHIFT 0x11 |
38547 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF18__SHIFT 0x12 |
38548 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF19__SHIFT 0x13 |
38549 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF20__SHIFT 0x14 |
38550 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF21__SHIFT 0x15 |
38551 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF22__SHIFT 0x16 |
38552 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF23__SHIFT 0x17 |
38553 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF24__SHIFT 0x18 |
38554 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF25__SHIFT 0x19 |
38555 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF26__SHIFT 0x1a |
38556 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF27__SHIFT 0x1b |
38557 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF28__SHIFT 0x1c |
38558 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF29__SHIFT 0x1d |
38559 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF30__SHIFT 0x1e |
38560 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f |
38561 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L |
38562 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L |
38563 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L |
38564 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L |
38565 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L |
38566 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L |
38567 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L |
38568 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L |
38569 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L |
38570 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L |
38571 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L |
38572 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L |
38573 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L |
38574 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L |
38575 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L |
38576 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L |
38577 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF16_MASK 0x00010000L |
38578 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF17_MASK 0x00020000L |
38579 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF18_MASK 0x00040000L |
38580 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF19_MASK 0x00080000L |
38581 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF20_MASK 0x00100000L |
38582 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF21_MASK 0x00200000L |
38583 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF22_MASK 0x00400000L |
38584 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF23_MASK 0x00800000L |
38585 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF24_MASK 0x01000000L |
38586 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF25_MASK 0x02000000L |
38587 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF26_MASK 0x04000000L |
38588 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF27_MASK 0x08000000L |
38589 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF28_MASK 0x10000000L |
38590 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF29_MASK 0x20000000L |
38591 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF30_MASK 0x40000000L |
38592 | #define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L |
38593 | |
38594 | |
38595 | // addressBlock: gc_pspdec |
38596 | #define CPG_PSP_DEBUG__GPA_OVERRIDE__SHIFT 0x3 |
38597 | #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L |
38598 | #define CPC_PSP_DEBUG__GPA_OVERRIDE__SHIFT 0x3 |
38599 | #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L |
38600 | //GRBM_SEC_CNTL |
38601 | //RLC_FWL_FIRST_VIOL_ADDR |
38602 | #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT 0x0 |
38603 | #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID__SHIFT 0x12 |
38604 | #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT 0x1e |
38605 | #define RLC_FWL_FIRST_VIOL_ADDR__RESERVED__SHIFT 0x1f |
38606 | #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK 0x0003FFFFL |
38607 | #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID_MASK 0x3FFC0000L |
38608 | #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK 0x40000000L |
38609 | #define RLC_FWL_FIRST_VIOL_ADDR__RESERVED_MASK 0x80000000L |
38610 | //RLC_SRM_FWL_FIRST_VIOL_ADDR |
38611 | #define RLC_SRM_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT 0x0 |
38612 | #define RLC_SRM_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT 0x12 |
38613 | #define RLC_SRM_FWL_FIRST_VIOL_ADDR__RESERVED__SHIFT 0x13 |
38614 | #define RLC_SRM_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK 0x0003FFFFL |
38615 | #define RLC_SRM_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK 0x00040000L |
38616 | #define RLC_SRM_FWL_FIRST_VIOL_ADDR__RESERVED_MASK 0xFFF80000L |
38617 | |
38618 | |
38619 | // addressBlock: gc_gcvml2pspdec |
38620 | //GCVM_L2_ID_CTRL0 |
38621 | #define GCVM_L2_ID_CTRL0__VMID0_EN__SHIFT 0x0 |
38622 | #define GCVM_L2_ID_CTRL0__VMID1_EN__SHIFT 0x10 |
38623 | #define GCVM_L2_ID_CTRL0__VMID0_EN_MASK 0x0000FFFFL |
38624 | #define GCVM_L2_ID_CTRL0__VMID1_EN_MASK 0xFFFF0000L |
38625 | //GCVM_L2_ID_CTRL1 |
38626 | #define GCVM_L2_ID_CTRL1__VMID0_EN__SHIFT 0x0 |
38627 | #define GCVM_L2_ID_CTRL1__VMID1_EN__SHIFT 0x10 |
38628 | #define GCVM_L2_ID_CTRL1__VMID0_EN_MASK 0x0000FFFFL |
38629 | #define GCVM_L2_ID_CTRL1__VMID1_EN_MASK 0xFFFF0000L |
38630 | //GCVM_L2_ID_CTRL2 |
38631 | #define GCVM_L2_ID_CTRL2__VMID0_EN__SHIFT 0x0 |
38632 | #define GCVM_L2_ID_CTRL2__VMID1_EN__SHIFT 0x10 |
38633 | #define GCVM_L2_ID_CTRL2__VMID0_EN_MASK 0x0000FFFFL |
38634 | #define GCVM_L2_ID_CTRL2__VMID1_EN_MASK 0xFFFF0000L |
38635 | //GCVM_L2_ID_CTRL3 |
38636 | #define GCVM_L2_ID_CTRL3__VMID0_EN__SHIFT 0x0 |
38637 | #define GCVM_L2_ID_CTRL3__VMID1_EN__SHIFT 0x10 |
38638 | #define GCVM_L2_ID_CTRL3__VMID0_EN_MASK 0x0000FFFFL |
38639 | #define GCVM_L2_ID_CTRL3__VMID1_EN_MASK 0xFFFF0000L |
38640 | //GCVM_L2_ID_CTRL4 |
38641 | #define GCVM_L2_ID_CTRL4__VMID0_EN__SHIFT 0x0 |
38642 | #define GCVM_L2_ID_CTRL4__VMID1_EN__SHIFT 0x10 |
38643 | #define GCVM_L2_ID_CTRL4__VMID0_EN_MASK 0x0000FFFFL |
38644 | #define GCVM_L2_ID_CTRL4__VMID1_EN_MASK 0xFFFF0000L |
38645 | //GCVM_L2_ID_CTRL5 |
38646 | #define GCVM_L2_ID_CTRL5__VMID0_EN__SHIFT 0x0 |
38647 | #define GCVM_L2_ID_CTRL5__VMID1_EN__SHIFT 0x10 |
38648 | #define GCVM_L2_ID_CTRL5__VMID0_EN_MASK 0x0000FFFFL |
38649 | #define GCVM_L2_ID_CTRL5__VMID1_EN_MASK 0xFFFF0000L |
38650 | //GCVM_L2_ID_CTRL6 |
38651 | #define GCVM_L2_ID_CTRL6__VMID0_EN__SHIFT 0x0 |
38652 | #define GCVM_L2_ID_CTRL6__VMID1_EN__SHIFT 0x10 |
38653 | #define GCVM_L2_ID_CTRL6__VMID0_EN_MASK 0x0000FFFFL |
38654 | #define GCVM_L2_ID_CTRL6__VMID1_EN_MASK 0xFFFF0000L |
38655 | //GCVM_L2_ID_CTRL7 |
38656 | #define GCVM_L2_ID_CTRL7__VMID0_EN__SHIFT 0x0 |
38657 | #define GCVM_L2_ID_CTRL7__VMID1_EN__SHIFT 0x10 |
38658 | #define GCVM_L2_ID_CTRL7__VMID0_EN_MASK 0x0000FFFFL |
38659 | #define GCVM_L2_ID_CTRL7__VMID1_EN_MASK 0xFFFF0000L |
38660 | //GCVM_L2_ID_CTRL_HI |
38661 | #define GCVM_L2_ID_CTRL_HI__VMID_EN_HI__SHIFT 0x0 |
38662 | #define GCVM_L2_ID_CTRL_HI__VMID_EN_HI_MASK 0x0000FFFFL |
38663 | //GCVM_L2_ID_STATUS |
38664 | #define GCVM_L2_ID_STATUS__VMID_FAULT__SHIFT 0x0 |
38665 | #define GCVM_L2_ID_STATUS__CLIENTID_FAULT__SHIFT 0x4 |
38666 | #define GCVM_L2_ID_STATUS__GRPID_FAULT__SHIFT 0xd |
38667 | #define GCVM_L2_ID_STATUS__VMID_INTR_ON__SHIFT 0x1f |
38668 | #define GCVM_L2_ID_STATUS__VMID_FAULT_MASK 0x0000000FL |
38669 | #define GCVM_L2_ID_STATUS__CLIENTID_FAULT_MASK 0x00001FF0L |
38670 | #define GCVM_L2_ID_STATUS__GRPID_FAULT_MASK 0x0001E000L |
38671 | #define GCVM_L2_ID_STATUS__VMID_INTR_ON_MASK 0x80000000L |
38672 | //GCUTCL2_TRANSLATION_BYPASS_BY_VMID |
38673 | #define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0 |
38674 | #define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10 |
38675 | #define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL |
38676 | #define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L |
38677 | //GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE |
38678 | #define GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE__SHIFT 0x0 |
38679 | #define GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE_MASK 0x00000001L |
38680 | //GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO |
38681 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 |
38682 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL |
38683 | //GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI |
38684 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 |
38685 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 |
38686 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x8 |
38687 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xd |
38688 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xe |
38689 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0x10 |
38690 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x11 |
38691 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x12 |
38692 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x13 |
38693 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1f |
38694 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL |
38695 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L |
38696 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00001F00L |
38697 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00002000L |
38698 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x0000C000L |
38699 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00010000L |
38700 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00020000L |
38701 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00040000L |
38702 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x0FF80000L |
38703 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x80000000L |
38704 | //GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO |
38705 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 |
38706 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL |
38707 | //GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI |
38708 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 |
38709 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 |
38710 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 |
38711 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd |
38712 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe |
38713 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf |
38714 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 |
38715 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 |
38716 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x15 |
38717 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x16 |
38718 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT 0x18 |
38719 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1f |
38720 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL |
38721 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L |
38722 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L |
38723 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L |
38724 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L |
38725 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L |
38726 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L |
38727 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x001C0000L |
38728 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00200000L |
38729 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00C00000L |
38730 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK 0x01000000L |
38731 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x80000000L |
38732 | |
38733 | |
38734 | // addressBlock: gc_sdma2_sdma2dec |
38735 | //SDMA2_DEC_START |
38736 | #define SDMA2_DEC_START__START__SHIFT 0x0 |
38737 | #define SDMA2_DEC_START__START_MASK 0xFFFFFFFFL |
38738 | //SDMA2_GLOBAL_TIMESTAMP_LO |
38739 | #define SDMA2_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 |
38740 | #define SDMA2_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL |
38741 | //SDMA2_GLOBAL_TIMESTAMP_HI |
38742 | #define SDMA2_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 |
38743 | #define SDMA2_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL |
38744 | //SDMA2_PG_CNTL |
38745 | #define SDMA2_PG_CNTL__CMD__SHIFT 0x0 |
38746 | #define SDMA2_PG_CNTL__STATUS__SHIFT 0x10 |
38747 | #define SDMA2_PG_CNTL__CMD_MASK 0x0000000FL |
38748 | #define SDMA2_PG_CNTL__STATUS_MASK 0x000F0000L |
38749 | //SDMA2_PG_CTX_LO |
38750 | #define SDMA2_PG_CTX_LO__ADDR__SHIFT 0x0 |
38751 | #define SDMA2_PG_CTX_LO__ADDR_MASK 0xFFFFFFFFL |
38752 | //SDMA2_PG_CTX_HI |
38753 | #define SDMA2_PG_CTX_HI__ADDR__SHIFT 0x0 |
38754 | #define SDMA2_PG_CTX_HI__ADDR_MASK 0xFFFFFFFFL |
38755 | //SDMA2_PG_CTX_CNTL |
38756 | #define SDMA2_PG_CTX_CNTL__VMID__SHIFT 0x4 |
38757 | #define SDMA2_PG_CTX_CNTL__VMID_MASK 0x000000F0L |
38758 | //SDMA2_POWER_CNTL |
38759 | #define SDMA2_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 |
38760 | #define SDMA2_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 |
38761 | #define SDMA2_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 |
38762 | #define SDMA2_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 |
38763 | #define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 |
38764 | #define SDMA2_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a |
38765 | #define SDMA2_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L |
38766 | #define SDMA2_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L |
38767 | #define SDMA2_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L |
38768 | #define SDMA2_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L |
38769 | #define SDMA2_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L |
38770 | #define SDMA2_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L |
38771 | //SDMA2_CLK_CTRL |
38772 | #define SDMA2_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
38773 | #define SDMA2_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
38774 | #define SDMA2_CLK_CTRL__RESERVED_24_12__SHIFT 0xc |
38775 | #define SDMA2_CLK_CTRL__CGCG_EN_OVERRIDE__SHIFT 0x19 |
38776 | #define SDMA2_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1a |
38777 | #define SDMA2_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1b |
38778 | #define SDMA2_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1c |
38779 | #define SDMA2_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1d |
38780 | #define SDMA2_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1e |
38781 | #define SDMA2_CLK_CTRL__SOFT_OVERRIDER_REG__SHIFT 0x1f |
38782 | #define SDMA2_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
38783 | #define SDMA2_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
38784 | #define SDMA2_CLK_CTRL__RESERVED_24_12_MASK 0x01FFF000L |
38785 | #define SDMA2_CLK_CTRL__CGCG_EN_OVERRIDE_MASK 0x02000000L |
38786 | #define SDMA2_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x04000000L |
38787 | #define SDMA2_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x08000000L |
38788 | #define SDMA2_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x10000000L |
38789 | #define SDMA2_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x20000000L |
38790 | #define SDMA2_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x40000000L |
38791 | #define SDMA2_CLK_CTRL__SOFT_OVERRIDER_REG_MASK 0x80000000L |
38792 | //SDMA2_CNTL |
38793 | #define SDMA2_CNTL__TRAP_ENABLE__SHIFT 0x0 |
38794 | #define SDMA2_CNTL__UTC_L1_ENABLE__SHIFT 0x1 |
38795 | #define SDMA2_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 |
38796 | #define SDMA2_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 |
38797 | #define SDMA2_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 |
38798 | #define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 |
38799 | #define SDMA2_CNTL__PAGE_INT_ENABLE__SHIFT 0x7 |
38800 | #define SDMA2_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10 |
38801 | #define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 |
38802 | #define SDMA2_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 |
38803 | #define SDMA2_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c |
38804 | #define SDMA2_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d |
38805 | #define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e |
38806 | #define SDMA2_CNTL__TRAP_ENABLE_MASK 0x00000001L |
38807 | #define SDMA2_CNTL__UTC_L1_ENABLE_MASK 0x00000002L |
38808 | #define SDMA2_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L |
38809 | #define SDMA2_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L |
38810 | #define SDMA2_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L |
38811 | #define SDMA2_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L |
38812 | #define SDMA2_CNTL__PAGE_INT_ENABLE_MASK 0x00000080L |
38813 | #define SDMA2_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L |
38814 | #define SDMA2_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L |
38815 | #define SDMA2_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L |
38816 | #define SDMA2_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L |
38817 | #define SDMA2_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L |
38818 | #define SDMA2_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L |
38819 | //SDMA2_CHICKEN_BITS |
38820 | #define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 |
38821 | #define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 |
38822 | #define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 |
38823 | #define SDMA2_CHICKEN_BITS__SOFT_OVERRIDE_DCGE__SHIFT 0x4 |
38824 | #define SDMA2_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG__SHIFT 0x5 |
38825 | #define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 |
38826 | #define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa |
38827 | #define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 |
38828 | #define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 |
38829 | #define SDMA2_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 |
38830 | #define SDMA2_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT 0x13 |
38831 | #define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 |
38832 | #define SDMA2_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT 0x15 |
38833 | #define SDMA2_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE__SHIFT 0x16 |
38834 | #define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 |
38835 | #define SDMA2_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT 0x18 |
38836 | #define SDMA2_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 |
38837 | #define SDMA2_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a |
38838 | #define SDMA2_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c |
38839 | #define SDMA2_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e |
38840 | #define SDMA2_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L |
38841 | #define SDMA2_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L |
38842 | #define SDMA2_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L |
38843 | #define SDMA2_CHICKEN_BITS__SOFT_OVERRIDE_DCGE_MASK 0x00000010L |
38844 | #define SDMA2_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG_MASK 0x00000020L |
38845 | #define SDMA2_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L |
38846 | #define SDMA2_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L |
38847 | #define SDMA2_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L |
38848 | #define SDMA2_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L |
38849 | #define SDMA2_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L |
38850 | #define SDMA2_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK 0x00080000L |
38851 | #define SDMA2_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L |
38852 | #define SDMA2_CHICKEN_BITS__CH_FGCG_ENABLE_MASK 0x00200000L |
38853 | #define SDMA2_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE_MASK 0x00400000L |
38854 | #define SDMA2_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L |
38855 | #define SDMA2_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK 0x01000000L |
38856 | #define SDMA2_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L |
38857 | #define SDMA2_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L |
38858 | #define SDMA2_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L |
38859 | #define SDMA2_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L |
38860 | //SDMA2_GB_ADDR_CONFIG |
38861 | #define SDMA2_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
38862 | #define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
38863 | #define SDMA2_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
38864 | #define SDMA2_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 |
38865 | #define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
38866 | #define SDMA2_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a |
38867 | #define SDMA2_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
38868 | #define SDMA2_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
38869 | #define SDMA2_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
38870 | #define SDMA2_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L |
38871 | #define SDMA2_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
38872 | #define SDMA2_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L |
38873 | //SDMA2_GB_ADDR_CONFIG_READ |
38874 | #define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 |
38875 | #define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
38876 | #define SDMA2_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
38877 | #define SDMA2_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 |
38878 | #define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 |
38879 | #define SDMA2_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a |
38880 | #define SDMA2_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L |
38881 | #define SDMA2_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
38882 | #define SDMA2_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
38883 | #define SDMA2_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L |
38884 | #define SDMA2_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L |
38885 | #define SDMA2_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L |
38886 | //SDMA2_RB_RPTR_FETCH_HI |
38887 | #define SDMA2_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 |
38888 | #define SDMA2_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL |
38889 | //SDMA2_SEM_WAIT_FAIL_TIMER_CNTL |
38890 | #define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 |
38891 | #define SDMA2_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL |
38892 | //SDMA2_RB_RPTR_FETCH |
38893 | #define SDMA2_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 |
38894 | #define SDMA2_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL |
38895 | //SDMA2_IB_OFFSET_FETCH |
38896 | #define SDMA2_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 |
38897 | #define SDMA2_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL |
38898 | //SDMA2_PROGRAM |
38899 | #define SDMA2_PROGRAM__STREAM__SHIFT 0x0 |
38900 | #define SDMA2_PROGRAM__STREAM_MASK 0xFFFFFFFFL |
38901 | //SDMA2_STATUS_REG |
38902 | #define SDMA2_STATUS_REG__IDLE__SHIFT 0x0 |
38903 | #define SDMA2_STATUS_REG__REG_IDLE__SHIFT 0x1 |
38904 | #define SDMA2_STATUS_REG__RB_EMPTY__SHIFT 0x2 |
38905 | #define SDMA2_STATUS_REG__RB_FULL__SHIFT 0x3 |
38906 | #define SDMA2_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 |
38907 | #define SDMA2_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 |
38908 | #define SDMA2_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 |
38909 | #define SDMA2_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 |
38910 | #define SDMA2_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 |
38911 | #define SDMA2_STATUS_REG__INSIDE_IB__SHIFT 0x9 |
38912 | #define SDMA2_STATUS_REG__EX_IDLE__SHIFT 0xa |
38913 | #define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb |
38914 | #define SDMA2_STATUS_REG__PACKET_READY__SHIFT 0xc |
38915 | #define SDMA2_STATUS_REG__MC_WR_IDLE__SHIFT 0xd |
38916 | #define SDMA2_STATUS_REG__SRBM_IDLE__SHIFT 0xe |
38917 | #define SDMA2_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf |
38918 | #define SDMA2_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 |
38919 | #define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 |
38920 | #define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 |
38921 | #define SDMA2_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 |
38922 | #define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 |
38923 | #define SDMA2_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 |
38924 | #define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 |
38925 | #define SDMA2_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 |
38926 | #define SDMA2_STATUS_REG__SEM_IDLE__SHIFT 0x1a |
38927 | #define SDMA2_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b |
38928 | #define SDMA2_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c |
38929 | #define SDMA2_STATUS_REG__INT_IDLE__SHIFT 0x1e |
38930 | #define SDMA2_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f |
38931 | #define SDMA2_STATUS_REG__IDLE_MASK 0x00000001L |
38932 | #define SDMA2_STATUS_REG__REG_IDLE_MASK 0x00000002L |
38933 | #define SDMA2_STATUS_REG__RB_EMPTY_MASK 0x00000004L |
38934 | #define SDMA2_STATUS_REG__RB_FULL_MASK 0x00000008L |
38935 | #define SDMA2_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L |
38936 | #define SDMA2_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L |
38937 | #define SDMA2_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L |
38938 | #define SDMA2_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L |
38939 | #define SDMA2_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L |
38940 | #define SDMA2_STATUS_REG__INSIDE_IB_MASK 0x00000200L |
38941 | #define SDMA2_STATUS_REG__EX_IDLE_MASK 0x00000400L |
38942 | #define SDMA2_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L |
38943 | #define SDMA2_STATUS_REG__PACKET_READY_MASK 0x00001000L |
38944 | #define SDMA2_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L |
38945 | #define SDMA2_STATUS_REG__SRBM_IDLE_MASK 0x00004000L |
38946 | #define SDMA2_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L |
38947 | #define SDMA2_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L |
38948 | #define SDMA2_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L |
38949 | #define SDMA2_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L |
38950 | #define SDMA2_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L |
38951 | #define SDMA2_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L |
38952 | #define SDMA2_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L |
38953 | #define SDMA2_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L |
38954 | #define SDMA2_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L |
38955 | #define SDMA2_STATUS_REG__SEM_IDLE_MASK 0x04000000L |
38956 | #define SDMA2_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L |
38957 | #define SDMA2_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L |
38958 | #define SDMA2_STATUS_REG__INT_IDLE_MASK 0x40000000L |
38959 | #define SDMA2_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L |
38960 | //SDMA2_STATUS1_REG |
38961 | #define SDMA2_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 |
38962 | #define SDMA2_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 |
38963 | #define SDMA2_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 |
38964 | #define SDMA2_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 |
38965 | #define SDMA2_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 |
38966 | #define SDMA2_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 |
38967 | #define SDMA2_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 |
38968 | #define SDMA2_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 |
38969 | #define SDMA2_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa |
38970 | #define SDMA2_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd |
38971 | #define SDMA2_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe |
38972 | #define SDMA2_STATUS1_REG__EX_START__SHIFT 0xf |
38973 | #define SDMA2_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 |
38974 | #define SDMA2_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 |
38975 | #define SDMA2_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L |
38976 | #define SDMA2_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L |
38977 | #define SDMA2_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L |
38978 | #define SDMA2_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L |
38979 | #define SDMA2_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L |
38980 | #define SDMA2_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L |
38981 | #define SDMA2_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L |
38982 | #define SDMA2_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L |
38983 | #define SDMA2_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L |
38984 | #define SDMA2_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L |
38985 | #define SDMA2_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L |
38986 | #define SDMA2_STATUS1_REG__EX_START_MASK 0x00008000L |
38987 | #define SDMA2_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L |
38988 | #define SDMA2_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L |
38989 | //SDMA2_RD_BURST_CNTL |
38990 | #define SDMA2_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 |
38991 | #define SDMA2_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L |
38992 | //SDMA2_HBM_PAGE_CONFIG |
38993 | #define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 |
38994 | #define SDMA2_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L |
38995 | //SDMA2_UCODE_CHECKSUM |
38996 | #define SDMA2_UCODE_CHECKSUM__DATA__SHIFT 0x0 |
38997 | #define SDMA2_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL |
38998 | //SDMA2_F32_CNTL |
38999 | #define SDMA2_F32_CNTL__HALT__SHIFT 0x0 |
39000 | #define SDMA2_F32_CNTL__STEP__SHIFT 0x1 |
39001 | #define SDMA2_F32_CNTL__CHECKSUM_CLR__SHIFT 0x8 |
39002 | #define SDMA2_F32_CNTL__RESET__SHIFT 0x9 |
39003 | #define SDMA2_F32_CNTL__HALT_MASK 0x00000001L |
39004 | #define SDMA2_F32_CNTL__STEP_MASK 0x00000002L |
39005 | #define SDMA2_F32_CNTL__CHECKSUM_CLR_MASK 0x00000100L |
39006 | #define SDMA2_F32_CNTL__RESET_MASK 0x00000200L |
39007 | //SDMA2_FREEZE |
39008 | #define SDMA2_FREEZE__PREEMPT__SHIFT 0x0 |
39009 | #define SDMA2_FREEZE__FORCE_PREEMPT__SHIFT 0x1 |
39010 | #define SDMA2_FREEZE__FREEZE__SHIFT 0x4 |
39011 | #define SDMA2_FREEZE__FROZEN__SHIFT 0x5 |
39012 | #define SDMA2_FREEZE__F32_FREEZE__SHIFT 0x6 |
39013 | #define SDMA2_FREEZE__PREEMPT_MASK 0x00000001L |
39014 | #define SDMA2_FREEZE__FORCE_PREEMPT_MASK 0x00000002L |
39015 | #define SDMA2_FREEZE__FREEZE_MASK 0x00000010L |
39016 | #define SDMA2_FREEZE__FROZEN_MASK 0x00000020L |
39017 | #define SDMA2_FREEZE__F32_FREEZE_MASK 0x00000040L |
39018 | //SDMA2_PHASE0_QUANTUM |
39019 | #define SDMA2_PHASE0_QUANTUM__UNIT__SHIFT 0x0 |
39020 | #define SDMA2_PHASE0_QUANTUM__VALUE__SHIFT 0x8 |
39021 | #define SDMA2_PHASE0_QUANTUM__PREFER__SHIFT 0x1e |
39022 | #define SDMA2_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL |
39023 | #define SDMA2_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L |
39024 | #define SDMA2_PHASE0_QUANTUM__PREFER_MASK 0x40000000L |
39025 | //SDMA2_PHASE1_QUANTUM |
39026 | #define SDMA2_PHASE1_QUANTUM__UNIT__SHIFT 0x0 |
39027 | #define SDMA2_PHASE1_QUANTUM__VALUE__SHIFT 0x8 |
39028 | #define SDMA2_PHASE1_QUANTUM__PREFER__SHIFT 0x1e |
39029 | #define SDMA2_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL |
39030 | #define SDMA2_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L |
39031 | #define SDMA2_PHASE1_QUANTUM__PREFER_MASK 0x40000000L |
39032 | //SDMA2_EDC_CONFIG |
39033 | #define SDMA2_EDC_CONFIG__DIS_EDC__SHIFT 0x1 |
39034 | #define SDMA2_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 |
39035 | #define SDMA2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L |
39036 | #define SDMA2_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L |
39037 | //SDMA2_BA_THRESHOLD |
39038 | #define SDMA2_BA_THRESHOLD__READ_THRES__SHIFT 0x0 |
39039 | #define SDMA2_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 |
39040 | #define SDMA2_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL |
39041 | #define SDMA2_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L |
39042 | //SDMA2_ID |
39043 | #define SDMA2_ID__DEVICE_ID__SHIFT 0x0 |
39044 | #define SDMA2_ID__DEVICE_ID_MASK 0x000000FFL |
39045 | //SDMA2_VERSION |
39046 | #define SDMA2_VERSION__MINVER__SHIFT 0x0 |
39047 | #define SDMA2_VERSION__MAJVER__SHIFT 0x8 |
39048 | #define SDMA2_VERSION__REV__SHIFT 0x10 |
39049 | #define SDMA2_VERSION__MINVER_MASK 0x0000007FL |
39050 | #define SDMA2_VERSION__MAJVER_MASK 0x00007F00L |
39051 | #define SDMA2_VERSION__REV_MASK 0x003F0000L |
39052 | //SDMA2_EDC_COUNTER |
39053 | #define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 |
39054 | #define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 |
39055 | #define SDMA2_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 |
39056 | #define SDMA2_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 |
39057 | #define SDMA2_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 |
39058 | #define SDMA2_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 |
39059 | #define SDMA2_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 |
39060 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 |
39061 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 |
39062 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 |
39063 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa |
39064 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb |
39065 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc |
39066 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd |
39067 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe |
39068 | #define SDMA2_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf |
39069 | #define SDMA2_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 |
39070 | #define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L |
39071 | #define SDMA2_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L |
39072 | #define SDMA2_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L |
39073 | #define SDMA2_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L |
39074 | #define SDMA2_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L |
39075 | #define SDMA2_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L |
39076 | #define SDMA2_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L |
39077 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L |
39078 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L |
39079 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L |
39080 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L |
39081 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L |
39082 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L |
39083 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L |
39084 | #define SDMA2_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L |
39085 | #define SDMA2_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L |
39086 | #define SDMA2_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L |
39087 | //SDMA2_EDC_COUNTER_CLEAR |
39088 | #define SDMA2_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 |
39089 | #define SDMA2_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L |
39090 | //SDMA2_STATUS2_REG |
39091 | #define SDMA2_STATUS2_REG__ID__SHIFT 0x0 |
39092 | #define SDMA2_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 |
39093 | #define SDMA2_STATUS2_REG__CMD_OP__SHIFT 0x10 |
39094 | #define SDMA2_STATUS2_REG__ID_MASK 0x00000003L |
39095 | #define SDMA2_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFFCL |
39096 | #define SDMA2_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L |
39097 | //SDMA2_ATOMIC_CNTL |
39098 | #define SDMA2_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 |
39099 | #define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f |
39100 | #define SDMA2_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL |
39101 | #define SDMA2_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L |
39102 | //SDMA2_ATOMIC_PREOP_LO |
39103 | #define SDMA2_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 |
39104 | #define SDMA2_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL |
39105 | //SDMA2_ATOMIC_PREOP_HI |
39106 | #define SDMA2_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 |
39107 | #define SDMA2_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL |
39108 | //SDMA2_UTCL1_CNTL |
39109 | #define SDMA2_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 |
39110 | #define SDMA2_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 |
39111 | #define SDMA2_UTCL1_CNTL__REDO_WATERMK__SHIFT 0x6 |
39112 | #define SDMA2_UTCL1_CNTL__RESP_MODE__SHIFT 0x9 |
39113 | #define SDMA2_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe |
39114 | #define SDMA2_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xf |
39115 | #define SDMA2_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x10 |
39116 | #define SDMA2_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 |
39117 | #define SDMA2_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d |
39118 | #define SDMA2_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L |
39119 | #define SDMA2_UTCL1_CNTL__REDO_DELAY_MASK 0x0000003EL |
39120 | #define SDMA2_UTCL1_CNTL__REDO_WATERMK_MASK 0x000001C0L |
39121 | #define SDMA2_UTCL1_CNTL__RESP_MODE_MASK 0x00000E00L |
39122 | #define SDMA2_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00004000L |
39123 | #define SDMA2_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00008000L |
39124 | #define SDMA2_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FF0000L |
39125 | #define SDMA2_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L |
39126 | #define SDMA2_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L |
39127 | //SDMA2_UTCL1_WATERMK |
39128 | #define SDMA2_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 |
39129 | #define SDMA2_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa |
39130 | #define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 |
39131 | #define SDMA2_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a |
39132 | #define SDMA2_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL |
39133 | #define SDMA2_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L |
39134 | #define SDMA2_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L |
39135 | #define SDMA2_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L |
39136 | //SDMA2_UTCL1_RD_STATUS |
39137 | #define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 |
39138 | #define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1 |
39139 | #define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2 |
39140 | #define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3 |
39141 | #define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4 |
39142 | #define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5 |
39143 | #define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6 |
39144 | #define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7 |
39145 | #define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8 |
39146 | #define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9 |
39147 | #define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa |
39148 | #define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb |
39149 | #define SDMA2_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT 0xc |
39150 | #define SDMA2_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT 0xd |
39151 | #define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0xe |
39152 | #define SDMA2_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0xf |
39153 | #define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x10 |
39154 | #define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x11 |
39155 | #define SDMA2_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x15 |
39156 | #define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x18 |
39157 | #define SDMA2_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT 0x19 |
39158 | #define SDMA2_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT 0x1a |
39159 | #define SDMA2_UTCL1_RD_STATUS__HIT_CACHE__SHIFT 0x1b |
39160 | #define SDMA2_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT 0x1c |
39161 | #define SDMA2_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT 0x1d |
39162 | #define SDMA2_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT 0x1e |
39163 | #define SDMA2_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT 0x1f |
39164 | #define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L |
39165 | #define SDMA2_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L |
39166 | #define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L |
39167 | #define SDMA2_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L |
39168 | #define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L |
39169 | #define SDMA2_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L |
39170 | #define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L |
39171 | #define SDMA2_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L |
39172 | #define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L |
39173 | #define SDMA2_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L |
39174 | #define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L |
39175 | #define SDMA2_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L |
39176 | #define SDMA2_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L |
39177 | #define SDMA2_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK 0x00002000L |
39178 | #define SDMA2_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00004000L |
39179 | #define SDMA2_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00008000L |
39180 | #define SDMA2_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00010000L |
39181 | #define SDMA2_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x001E0000L |
39182 | #define SDMA2_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x00E00000L |
39183 | #define SDMA2_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x01000000L |
39184 | #define SDMA2_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK 0x02000000L |
39185 | #define SDMA2_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK 0x04000000L |
39186 | #define SDMA2_UTCL1_RD_STATUS__HIT_CACHE_MASK 0x08000000L |
39187 | #define SDMA2_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK 0x10000000L |
39188 | #define SDMA2_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK 0x20000000L |
39189 | #define SDMA2_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK 0x40000000L |
39190 | #define SDMA2_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK 0x80000000L |
39191 | //SDMA2_UTCL1_WR_STATUS |
39192 | #define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 |
39193 | #define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1 |
39194 | #define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2 |
39195 | #define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3 |
39196 | #define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4 |
39197 | #define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5 |
39198 | #define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6 |
39199 | #define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7 |
39200 | #define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8 |
39201 | #define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9 |
39202 | #define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa |
39203 | #define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb |
39204 | #define SDMA2_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT 0xc |
39205 | #define SDMA2_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT 0xd |
39206 | #define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0xe |
39207 | #define SDMA2_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0xf |
39208 | #define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x10 |
39209 | #define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x11 |
39210 | #define SDMA2_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x15 |
39211 | #define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x18 |
39212 | #define SDMA2_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT 0x19 |
39213 | #define SDMA2_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT 0x1a |
39214 | #define SDMA2_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT 0x1b |
39215 | #define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c |
39216 | #define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d |
39217 | #define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e |
39218 | #define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f |
39219 | #define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L |
39220 | #define SDMA2_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L |
39221 | #define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L |
39222 | #define SDMA2_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L |
39223 | #define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L |
39224 | #define SDMA2_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L |
39225 | #define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L |
39226 | #define SDMA2_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L |
39227 | #define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L |
39228 | #define SDMA2_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L |
39229 | #define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L |
39230 | #define SDMA2_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L |
39231 | #define SDMA2_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L |
39232 | #define SDMA2_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK 0x00002000L |
39233 | #define SDMA2_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00004000L |
39234 | #define SDMA2_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00008000L |
39235 | #define SDMA2_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00010000L |
39236 | #define SDMA2_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x001E0000L |
39237 | #define SDMA2_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x00E00000L |
39238 | #define SDMA2_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x01000000L |
39239 | #define SDMA2_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK 0x02000000L |
39240 | #define SDMA2_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK 0x04000000L |
39241 | #define SDMA2_UTCL1_WR_STATUS__ATOMIC_OP_MASK 0x08000000L |
39242 | #define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L |
39243 | #define SDMA2_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L |
39244 | #define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L |
39245 | #define SDMA2_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L |
39246 | //SDMA2_UTCL1_INV0 |
39247 | #define SDMA2_UTCL1_INV0__CPF_INVREQ_EN__SHIFT 0x0 |
39248 | #define SDMA2_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT 0x1 |
39249 | #define SDMA2_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT 0x2 |
39250 | #define SDMA2_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT 0x3 |
39251 | #define SDMA2_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT 0x4 |
39252 | #define SDMA2_UTCL1_INV0__INVREQ_SIZE__SHIFT 0x5 |
39253 | #define SDMA2_UTCL1_INV0__INVREQ_IDLE__SHIFT 0xb |
39254 | #define SDMA2_UTCL1_INV0__VMINV_PEND_CNT__SHIFT 0xc |
39255 | #define SDMA2_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT 0x10 |
39256 | #define SDMA2_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT 0x14 |
39257 | #define SDMA2_UTCL1_INV0__GPUVM_INV_MODE__SHIFT 0x18 |
39258 | #define SDMA2_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT 0x1a |
39259 | #define SDMA2_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT 0x1b |
39260 | #define SDMA2_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT 0x1c |
39261 | #define SDMA2_UTCL1_INV0__CPF_INVREQ_EN_MASK 0x00000001L |
39262 | #define SDMA2_UTCL1_INV0__GPUVM_INVREQ_EN_MASK 0x00000002L |
39263 | #define SDMA2_UTCL1_INV0__CPF_GPA_INVREQ_MASK 0x00000004L |
39264 | #define SDMA2_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK 0x00000008L |
39265 | #define SDMA2_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK 0x00000010L |
39266 | #define SDMA2_UTCL1_INV0__INVREQ_SIZE_MASK 0x000007E0L |
39267 | #define SDMA2_UTCL1_INV0__INVREQ_IDLE_MASK 0x00000800L |
39268 | #define SDMA2_UTCL1_INV0__VMINV_PEND_CNT_MASK 0x0000F000L |
39269 | #define SDMA2_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK 0x000F0000L |
39270 | #define SDMA2_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK 0x00F00000L |
39271 | #define SDMA2_UTCL1_INV0__GPUVM_INV_MODE_MASK 0x03000000L |
39272 | #define SDMA2_UTCL1_INV0__INVREQ_IS_HEAVY_MASK 0x04000000L |
39273 | #define SDMA2_UTCL1_INV0__INVREQ_FROM_CPF_MASK 0x08000000L |
39274 | #define SDMA2_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK 0xF0000000L |
39275 | //SDMA2_UTCL1_INV1 |
39276 | #define SDMA2_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 |
39277 | #define SDMA2_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL |
39278 | //SDMA2_UTCL1_INV2 |
39279 | #define SDMA2_UTCL1_INV2__INV_VMID_VEC__SHIFT 0x0 |
39280 | #define SDMA2_UTCL1_INV2__RESERVED__SHIFT 0x10 |
39281 | #define SDMA2_UTCL1_INV2__INV_VMID_VEC_MASK 0x0000FFFFL |
39282 | #define SDMA2_UTCL1_INV2__RESERVED_MASK 0xFFFF0000L |
39283 | //SDMA2_UTCL1_RD_XNACK0 |
39284 | #define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 |
39285 | #define SDMA2_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL |
39286 | //SDMA2_UTCL1_RD_XNACK1 |
39287 | #define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 |
39288 | #define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 |
39289 | #define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 |
39290 | #define SDMA2_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a |
39291 | #define SDMA2_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL |
39292 | #define SDMA2_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L |
39293 | #define SDMA2_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L |
39294 | #define SDMA2_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L |
39295 | //SDMA2_UTCL1_WR_XNACK0 |
39296 | #define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 |
39297 | #define SDMA2_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL |
39298 | //SDMA2_UTCL1_WR_XNACK1 |
39299 | #define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 |
39300 | #define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 |
39301 | #define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 |
39302 | #define SDMA2_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a |
39303 | #define SDMA2_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL |
39304 | #define SDMA2_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L |
39305 | #define SDMA2_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L |
39306 | #define SDMA2_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L |
39307 | //SDMA2_UTCL1_TIMEOUT |
39308 | #define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 |
39309 | #define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 |
39310 | #define SDMA2_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL |
39311 | #define SDMA2_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L |
39312 | //SDMA2_UTCL1_PAGE |
39313 | #define SDMA2_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 |
39314 | #define SDMA2_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 |
39315 | #define SDMA2_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 |
39316 | #define SDMA2_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa |
39317 | #define SDMA2_UTCL1_PAGE__USE_IO__SHIFT 0xb |
39318 | #define SDMA2_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc |
39319 | #define SDMA2_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe |
39320 | #define SDMA2_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT 0x10 |
39321 | #define SDMA2_UTCL1_PAGE__USE_BC__SHIFT 0x16 |
39322 | #define SDMA2_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17 |
39323 | #define SDMA2_UTCL1_PAGE__LLC_NOALLOC__SHIFT 0x18 |
39324 | #define SDMA2_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L |
39325 | #define SDMA2_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL |
39326 | #define SDMA2_UTCL1_PAGE__USE_MTYPE_MASK 0x000003C0L |
39327 | #define SDMA2_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L |
39328 | #define SDMA2_UTCL1_PAGE__USE_IO_MASK 0x00000800L |
39329 | #define SDMA2_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L |
39330 | #define SDMA2_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L |
39331 | #define SDMA2_UTCL1_PAGE__DMA_PAGE_SIZE_MASK 0x003F0000L |
39332 | #define SDMA2_UTCL1_PAGE__USE_BC_MASK 0x00400000L |
39333 | #define SDMA2_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L |
39334 | #define SDMA2_UTCL1_PAGE__LLC_NOALLOC_MASK 0x01000000L |
39335 | //SDMA2_RELAX_ORDERING_LUT |
39336 | #define SDMA2_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 |
39337 | #define SDMA2_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 |
39338 | #define SDMA2_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 |
39339 | #define SDMA2_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 |
39340 | #define SDMA2_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 |
39341 | #define SDMA2_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 |
39342 | #define SDMA2_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 |
39343 | #define SDMA2_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 |
39344 | #define SDMA2_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 |
39345 | #define SDMA2_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa |
39346 | #define SDMA2_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb |
39347 | #define SDMA2_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc |
39348 | #define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd |
39349 | #define SDMA2_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe |
39350 | #define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b |
39351 | #define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c |
39352 | #define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d |
39353 | #define SDMA2_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e |
39354 | #define SDMA2_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f |
39355 | #define SDMA2_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L |
39356 | #define SDMA2_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L |
39357 | #define SDMA2_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L |
39358 | #define SDMA2_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L |
39359 | #define SDMA2_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L |
39360 | #define SDMA2_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L |
39361 | #define SDMA2_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L |
39362 | #define SDMA2_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L |
39363 | #define SDMA2_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L |
39364 | #define SDMA2_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L |
39365 | #define SDMA2_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L |
39366 | #define SDMA2_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L |
39367 | #define SDMA2_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L |
39368 | #define SDMA2_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L |
39369 | #define SDMA2_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L |
39370 | #define SDMA2_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L |
39371 | #define SDMA2_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L |
39372 | #define SDMA2_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L |
39373 | #define SDMA2_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L |
39374 | //SDMA2_CHICKEN_BITS_2 |
39375 | #define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 |
39376 | #define SDMA2_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT 0x4 |
39377 | #define SDMA2_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE__SHIFT 0x5 |
39378 | #define SDMA2_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT 0x6 |
39379 | #define SDMA2_CHICKEN_BITS_2__RESERVED0__SHIFT 0x7 |
39380 | #define SDMA2_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN__SHIFT 0xb |
39381 | #define SDMA2_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR__SHIFT 0xf |
39382 | #define SDMA2_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT 0x10 |
39383 | #define SDMA2_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT 0x12 |
39384 | #define SDMA2_CHICKEN_BITS_2__REPEATER_FGCG_EN__SHIFT 0x14 |
39385 | #define SDMA2_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x15 |
39386 | #define SDMA2_CHICKEN_BITS_2__RESERVED__SHIFT 0x16 |
39387 | #define SDMA2_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL |
39388 | #define SDMA2_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK 0x00000010L |
39389 | #define SDMA2_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE_MASK 0x00000020L |
39390 | #define SDMA2_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK 0x00000040L |
39391 | #define SDMA2_CHICKEN_BITS_2__RESERVED0_MASK 0x00000780L |
39392 | #define SDMA2_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN_MASK 0x00007800L |
39393 | #define SDMA2_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR_MASK 0x00008000L |
39394 | #define SDMA2_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK 0x00030000L |
39395 | #define SDMA2_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK 0x000C0000L |
39396 | #define SDMA2_CHICKEN_BITS_2__REPEATER_FGCG_EN_MASK 0x00100000L |
39397 | #define SDMA2_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00200000L |
39398 | #define SDMA2_CHICKEN_BITS_2__RESERVED_MASK 0xFFC00000L |
39399 | //SDMA2_STATUS3_REG |
39400 | #define SDMA2_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 |
39401 | #define SDMA2_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 |
39402 | #define SDMA2_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 |
39403 | #define SDMA2_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15 |
39404 | #define SDMA2_STATUS3_REG__TLBI_IDLE__SHIFT 0x16 |
39405 | #define SDMA2_STATUS3_REG__GCR_IDLE__SHIFT 0x17 |
39406 | #define SDMA2_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18 |
39407 | #define SDMA2_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19 |
39408 | #define SDMA2_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a |
39409 | #define SDMA2_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL |
39410 | #define SDMA2_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L |
39411 | #define SDMA2_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L |
39412 | #define SDMA2_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L |
39413 | #define SDMA2_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L |
39414 | #define SDMA2_STATUS3_REG__GCR_IDLE_MASK 0x00800000L |
39415 | #define SDMA2_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L |
39416 | #define SDMA2_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L |
39417 | #define SDMA2_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L |
39418 | //SDMA2_PHYSICAL_ADDR_LO |
39419 | #define SDMA2_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 |
39420 | #define SDMA2_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 |
39421 | #define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 |
39422 | #define SDMA2_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc |
39423 | #define SDMA2_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L |
39424 | #define SDMA2_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L |
39425 | #define SDMA2_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L |
39426 | #define SDMA2_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L |
39427 | //SDMA2_PHYSICAL_ADDR_HI |
39428 | #define SDMA2_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 |
39429 | #define SDMA2_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL |
39430 | //SDMA2_PHASE2_QUANTUM |
39431 | #define SDMA2_PHASE2_QUANTUM__UNIT__SHIFT 0x0 |
39432 | #define SDMA2_PHASE2_QUANTUM__VALUE__SHIFT 0x8 |
39433 | #define SDMA2_PHASE2_QUANTUM__PREFER__SHIFT 0x1e |
39434 | #define SDMA2_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL |
39435 | #define SDMA2_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L |
39436 | #define SDMA2_PHASE2_QUANTUM__PREFER_MASK 0x40000000L |
39437 | //SDMA2_ERROR_LOG |
39438 | #define SDMA2_ERROR_LOG__OVERRIDE__SHIFT 0x0 |
39439 | #define SDMA2_ERROR_LOG__STATUS__SHIFT 0x10 |
39440 | #define SDMA2_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL |
39441 | #define SDMA2_ERROR_LOG__STATUS_MASK 0xFFFF0000L |
39442 | //SDMA2_PUB_DUMMY_REG0 |
39443 | #define SDMA2_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 |
39444 | #define SDMA2_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL |
39445 | //SDMA2_PUB_DUMMY_REG1 |
39446 | #define SDMA2_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 |
39447 | #define SDMA2_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL |
39448 | //SDMA2_PUB_DUMMY_REG2 |
39449 | #define SDMA2_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 |
39450 | #define SDMA2_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL |
39451 | //SDMA2_PUB_DUMMY_REG3 |
39452 | #define SDMA2_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 |
39453 | #define SDMA2_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL |
39454 | //SDMA2_F32_COUNTER |
39455 | #define SDMA2_F32_COUNTER__VALUE__SHIFT 0x0 |
39456 | #define SDMA2_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL |
39457 | //SDMA2_CRD_CNTL |
39458 | #define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 |
39459 | #define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd |
39460 | #define SDMA2_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13 |
39461 | #define SDMA2_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19 |
39462 | #define SDMA2_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L |
39463 | #define SDMA2_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L |
39464 | #define SDMA2_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L |
39465 | #define SDMA2_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L |
39466 | //SDMA2_AQL_STATUS |
39467 | #define SDMA2_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0 |
39468 | #define SDMA2_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1 |
39469 | #define SDMA2_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L |
39470 | #define SDMA2_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L |
39471 | //SDMA2_EA_DBIT_ADDR_DATA |
39472 | #define SDMA2_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 |
39473 | #define SDMA2_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL |
39474 | //SDMA2_EA_DBIT_ADDR_INDEX |
39475 | #define SDMA2_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 |
39476 | #define SDMA2_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L |
39477 | //SDMA2_TLBI_GCR_CNTL |
39478 | #define SDMA2_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0 |
39479 | #define SDMA2_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4 |
39480 | #define SDMA2_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT 0x8 |
39481 | #define SDMA2_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10 |
39482 | #define SDMA2_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18 |
39483 | #define SDMA2_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL |
39484 | #define SDMA2_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L |
39485 | #define SDMA2_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK 0x00000F00L |
39486 | #define SDMA2_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L |
39487 | #define SDMA2_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L |
39488 | //SDMA2_TILING_CONFIG |
39489 | #define SDMA2_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
39490 | #define SDMA2_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L |
39491 | //SDMA2_INT_STATUS |
39492 | #define SDMA2_INT_STATUS__DATA__SHIFT 0x0 |
39493 | #define SDMA2_INT_STATUS__DATA_MASK 0xFFFFFFFFL |
39494 | //SDMA2_HOLE_ADDR_LO |
39495 | #define SDMA2_HOLE_ADDR_LO__VALUE__SHIFT 0x0 |
39496 | #define SDMA2_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL |
39497 | //SDMA2_HOLE_ADDR_HI |
39498 | #define SDMA2_HOLE_ADDR_HI__VALUE__SHIFT 0x0 |
39499 | #define SDMA2_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL |
39500 | //SDMA2_CLOCK_GATING_REG |
39501 | #define SDMA2_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS__SHIFT 0x0 |
39502 | #define SDMA2_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS__SHIFT 0x1 |
39503 | #define SDMA2_CLOCK_GATING_REG__CE_CLK_GATE_STATUS__SHIFT 0x2 |
39504 | #define SDMA2_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS__SHIFT 0x3 |
39505 | #define SDMA2_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS__SHIFT 0x4 |
39506 | #define SDMA2_CLOCK_GATING_REG__REG_CLK_GATE_STATUS__SHIFT 0x5 |
39507 | #define SDMA2_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS_MASK 0x00000001L |
39508 | #define SDMA2_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS_MASK 0x00000002L |
39509 | #define SDMA2_CLOCK_GATING_REG__CE_CLK_GATE_STATUS_MASK 0x00000004L |
39510 | #define SDMA2_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS_MASK 0x00000008L |
39511 | #define SDMA2_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS_MASK 0x00000010L |
39512 | #define SDMA2_CLOCK_GATING_REG__REG_CLK_GATE_STATUS_MASK 0x00000020L |
39513 | //SDMA2_STATUS4_REG |
39514 | #define SDMA2_STATUS4_REG__IDLE__SHIFT 0x0 |
39515 | #define SDMA2_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 |
39516 | #define SDMA2_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 |
39517 | #define SDMA2_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT 0x4 |
39518 | #define SDMA2_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT 0x5 |
39519 | #define SDMA2_STATUS4_REG__GCR_OUTSTANDING__SHIFT 0x6 |
39520 | #define SDMA2_STATUS4_REG__TLBI_OUTSTANDING__SHIFT 0x7 |
39521 | #define SDMA2_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x8 |
39522 | #define SDMA2_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x9 |
39523 | #define SDMA2_STATUS4_REG__REG_POLLING__SHIFT 0xa |
39524 | #define SDMA2_STATUS4_REG__MEM_POLLING__SHIFT 0xb |
39525 | #define SDMA2_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xc |
39526 | #define SDMA2_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xe |
39527 | #define SDMA2_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 |
39528 | #define SDMA2_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x14 |
39529 | #define SDMA2_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x15 |
39530 | #define SDMA2_STATUS4_REG__IDLE_MASK 0x00000001L |
39531 | #define SDMA2_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L |
39532 | #define SDMA2_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L |
39533 | #define SDMA2_STATUS4_REG__CH_RD_OUTSTANDING_MASK 0x00000010L |
39534 | #define SDMA2_STATUS4_REG__CH_WR_OUTSTANDING_MASK 0x00000020L |
39535 | #define SDMA2_STATUS4_REG__GCR_OUTSTANDING_MASK 0x00000040L |
39536 | #define SDMA2_STATUS4_REG__TLBI_OUTSTANDING_MASK 0x00000080L |
39537 | #define SDMA2_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000100L |
39538 | #define SDMA2_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000200L |
39539 | #define SDMA2_STATUS4_REG__REG_POLLING_MASK 0x00000400L |
39540 | #define SDMA2_STATUS4_REG__MEM_POLLING_MASK 0x00000800L |
39541 | #define SDMA2_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00003000L |
39542 | #define SDMA2_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x0000C000L |
39543 | #define SDMA2_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L |
39544 | #define SDMA2_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00100000L |
39545 | #define SDMA2_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00200000L |
39546 | //SDMA2_SCRATCH_RAM_DATA |
39547 | #define SDMA2_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 |
39548 | #define SDMA2_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL |
39549 | //SDMA2_SCRATCH_RAM_ADDR |
39550 | #define SDMA2_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 |
39551 | #define SDMA2_SCRATCH_RAM_ADDR__ADDR_MASK 0x000003FFL |
39552 | //SDMA2_TIMESTAMP_CNTL |
39553 | #define SDMA2_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 |
39554 | #define SDMA2_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L |
39555 | //SDMA2_STATUS5_REG |
39556 | #define SDMA2_STATUS5_REG__GFX_RB_ENABLE_STATUS__SHIFT 0x0 |
39557 | #define SDMA2_STATUS5_REG__PAGE_RB_ENABLE_STATUS__SHIFT 0x1 |
39558 | #define SDMA2_STATUS5_REG__RLC0_RB_ENABLE_STATUS__SHIFT 0x2 |
39559 | #define SDMA2_STATUS5_REG__RLC1_RB_ENABLE_STATUS__SHIFT 0x3 |
39560 | #define SDMA2_STATUS5_REG__RLC2_RB_ENABLE_STATUS__SHIFT 0x4 |
39561 | #define SDMA2_STATUS5_REG__RLC3_RB_ENABLE_STATUS__SHIFT 0x5 |
39562 | #define SDMA2_STATUS5_REG__RLC4_RB_ENABLE_STATUS__SHIFT 0x6 |
39563 | #define SDMA2_STATUS5_REG__RLC5_RB_ENABLE_STATUS__SHIFT 0x7 |
39564 | #define SDMA2_STATUS5_REG__RLC6_RB_ENABLE_STATUS__SHIFT 0x8 |
39565 | #define SDMA2_STATUS5_REG__RLC7_RB_ENABLE_STATUS__SHIFT 0x9 |
39566 | #define SDMA2_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 |
39567 | #define SDMA2_STATUS5_REG__GFX_RB_ENABLE_STATUS_MASK 0x00000001L |
39568 | #define SDMA2_STATUS5_REG__PAGE_RB_ENABLE_STATUS_MASK 0x00000002L |
39569 | #define SDMA2_STATUS5_REG__RLC0_RB_ENABLE_STATUS_MASK 0x00000004L |
39570 | #define SDMA2_STATUS5_REG__RLC1_RB_ENABLE_STATUS_MASK 0x00000008L |
39571 | #define SDMA2_STATUS5_REG__RLC2_RB_ENABLE_STATUS_MASK 0x00000010L |
39572 | #define SDMA2_STATUS5_REG__RLC3_RB_ENABLE_STATUS_MASK 0x00000020L |
39573 | #define SDMA2_STATUS5_REG__RLC4_RB_ENABLE_STATUS_MASK 0x00000040L |
39574 | #define SDMA2_STATUS5_REG__RLC5_RB_ENABLE_STATUS_MASK 0x00000080L |
39575 | #define SDMA2_STATUS5_REG__RLC6_RB_ENABLE_STATUS_MASK 0x00000100L |
39576 | #define SDMA2_STATUS5_REG__RLC7_RB_ENABLE_STATUS_MASK 0x00000200L |
39577 | #define SDMA2_STATUS5_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L |
39578 | //SDMA2_QUEUE_RESET_REQ |
39579 | #define SDMA2_QUEUE_RESET_REQ__GFX_QUEUE_RESET__SHIFT 0x0 |
39580 | #define SDMA2_QUEUE_RESET_REQ__PAGE_QUEUE_RESET__SHIFT 0x1 |
39581 | #define SDMA2_QUEUE_RESET_REQ__RLC0_QUEUE_RESET__SHIFT 0x2 |
39582 | #define SDMA2_QUEUE_RESET_REQ__RLC1_QUEUE_RESET__SHIFT 0x3 |
39583 | #define SDMA2_QUEUE_RESET_REQ__RLC2_QUEUE_RESET__SHIFT 0x4 |
39584 | #define SDMA2_QUEUE_RESET_REQ__RLC3_QUEUE_RESET__SHIFT 0x5 |
39585 | #define SDMA2_QUEUE_RESET_REQ__RLC4_QUEUE_RESET__SHIFT 0x6 |
39586 | #define SDMA2_QUEUE_RESET_REQ__RLC5_QUEUE_RESET__SHIFT 0x7 |
39587 | #define SDMA2_QUEUE_RESET_REQ__RLC6_QUEUE_RESET__SHIFT 0x8 |
39588 | #define SDMA2_QUEUE_RESET_REQ__RLC7_QUEUE_RESET__SHIFT 0x9 |
39589 | #define SDMA2_QUEUE_RESET_REQ__RESERVED__SHIFT 0xa |
39590 | #define SDMA2_QUEUE_RESET_REQ__GFX_QUEUE_RESET_MASK 0x00000001L |
39591 | #define SDMA2_QUEUE_RESET_REQ__PAGE_QUEUE_RESET_MASK 0x00000002L |
39592 | #define SDMA2_QUEUE_RESET_REQ__RLC0_QUEUE_RESET_MASK 0x00000004L |
39593 | #define SDMA2_QUEUE_RESET_REQ__RLC1_QUEUE_RESET_MASK 0x00000008L |
39594 | #define SDMA2_QUEUE_RESET_REQ__RLC2_QUEUE_RESET_MASK 0x00000010L |
39595 | #define SDMA2_QUEUE_RESET_REQ__RLC3_QUEUE_RESET_MASK 0x00000020L |
39596 | #define SDMA2_QUEUE_RESET_REQ__RLC4_QUEUE_RESET_MASK 0x00000040L |
39597 | #define SDMA2_QUEUE_RESET_REQ__RLC5_QUEUE_RESET_MASK 0x00000080L |
39598 | #define SDMA2_QUEUE_RESET_REQ__RLC6_QUEUE_RESET_MASK 0x00000100L |
39599 | #define SDMA2_QUEUE_RESET_REQ__RLC7_QUEUE_RESET_MASK 0x00000200L |
39600 | #define SDMA2_QUEUE_RESET_REQ__RESERVED_MASK 0xFFFFFC00L |
39601 | //SDMA2_GFX_RB_CNTL |
39602 | #define SDMA2_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
39603 | #define SDMA2_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 |
39604 | #define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
39605 | #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
39606 | #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
39607 | #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
39608 | #define SDMA2_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 |
39609 | #define SDMA2_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 |
39610 | #define SDMA2_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
39611 | #define SDMA2_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
39612 | #define SDMA2_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
39613 | #define SDMA2_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
39614 | #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
39615 | #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
39616 | #define SDMA2_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
39617 | #define SDMA2_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L |
39618 | #define SDMA2_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L |
39619 | #define SDMA2_GFX_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
39620 | //SDMA2_GFX_RB_BASE |
39621 | #define SDMA2_GFX_RB_BASE__ADDR__SHIFT 0x0 |
39622 | #define SDMA2_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
39623 | //SDMA2_GFX_RB_BASE_HI |
39624 | #define SDMA2_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 |
39625 | #define SDMA2_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
39626 | //SDMA2_GFX_RB_RPTR |
39627 | #define SDMA2_GFX_RB_RPTR__OFFSET__SHIFT 0x0 |
39628 | #define SDMA2_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
39629 | //SDMA2_GFX_RB_RPTR_HI |
39630 | #define SDMA2_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
39631 | #define SDMA2_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
39632 | //SDMA2_GFX_RB_WPTR |
39633 | #define SDMA2_GFX_RB_WPTR__OFFSET__SHIFT 0x0 |
39634 | #define SDMA2_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
39635 | //SDMA2_GFX_RB_WPTR_HI |
39636 | #define SDMA2_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
39637 | #define SDMA2_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
39638 | //SDMA2_GFX_RB_WPTR_POLL_CNTL |
39639 | #define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
39640 | #define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
39641 | #define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
39642 | #define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
39643 | #define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
39644 | #define SDMA2_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
39645 | #define SDMA2_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
39646 | #define SDMA2_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
39647 | #define SDMA2_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
39648 | #define SDMA2_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
39649 | //SDMA2_GFX_RB_RPTR_ADDR_HI |
39650 | #define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
39651 | #define SDMA2_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
39652 | //SDMA2_GFX_RB_RPTR_ADDR_LO |
39653 | #define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
39654 | #define SDMA2_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
39655 | //SDMA2_GFX_IB_CNTL |
39656 | #define SDMA2_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
39657 | #define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
39658 | #define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
39659 | #define SDMA2_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 |
39660 | #define SDMA2_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
39661 | #define SDMA2_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
39662 | #define SDMA2_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
39663 | #define SDMA2_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
39664 | //SDMA2_GFX_IB_RPTR |
39665 | #define SDMA2_GFX_IB_RPTR__OFFSET__SHIFT 0x2 |
39666 | #define SDMA2_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
39667 | //SDMA2_GFX_IB_OFFSET |
39668 | #define SDMA2_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 |
39669 | #define SDMA2_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
39670 | //SDMA2_GFX_IB_BASE_LO |
39671 | #define SDMA2_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 |
39672 | #define SDMA2_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
39673 | //SDMA2_GFX_IB_BASE_HI |
39674 | #define SDMA2_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 |
39675 | #define SDMA2_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
39676 | //SDMA2_GFX_IB_SIZE |
39677 | #define SDMA2_GFX_IB_SIZE__SIZE__SHIFT 0x0 |
39678 | #define SDMA2_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL |
39679 | //SDMA2_GFX_SKIP_CNTL |
39680 | #define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
39681 | #define SDMA2_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
39682 | //SDMA2_GFX_CONTEXT_STATUS |
39683 | #define SDMA2_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
39684 | #define SDMA2_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
39685 | #define SDMA2_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
39686 | #define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
39687 | #define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
39688 | #define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
39689 | #define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
39690 | #define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
39691 | #define SDMA2_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
39692 | #define SDMA2_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
39693 | #define SDMA2_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
39694 | #define SDMA2_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
39695 | #define SDMA2_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
39696 | #define SDMA2_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
39697 | #define SDMA2_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
39698 | #define SDMA2_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
39699 | //SDMA2_GFX_DOORBELL |
39700 | #define SDMA2_GFX_DOORBELL__ENABLE__SHIFT 0x1c |
39701 | #define SDMA2_GFX_DOORBELL__CAPTURED__SHIFT 0x1e |
39702 | #define SDMA2_GFX_DOORBELL__ENABLE_MASK 0x10000000L |
39703 | #define SDMA2_GFX_DOORBELL__CAPTURED_MASK 0x40000000L |
39704 | //SDMA2_GFX_CONTEXT_CNTL |
39705 | #define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 |
39706 | #define SDMA2_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 |
39707 | #define SDMA2_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L |
39708 | #define SDMA2_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L |
39709 | //SDMA2_GFX_STATUS |
39710 | #define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
39711 | #define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
39712 | #define SDMA2_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
39713 | #define SDMA2_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
39714 | //SDMA2_GFX_DOORBELL_LOG |
39715 | #define SDMA2_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
39716 | #define SDMA2_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 |
39717 | #define SDMA2_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
39718 | #define SDMA2_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
39719 | //SDMA2_GFX_WATERMARK |
39720 | #define SDMA2_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
39721 | #define SDMA2_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
39722 | #define SDMA2_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
39723 | #define SDMA2_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
39724 | //SDMA2_GFX_DOORBELL_OFFSET |
39725 | #define SDMA2_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
39726 | #define SDMA2_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
39727 | //SDMA2_GFX_CSA_ADDR_LO |
39728 | #define SDMA2_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
39729 | #define SDMA2_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
39730 | //SDMA2_GFX_CSA_ADDR_HI |
39731 | #define SDMA2_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
39732 | #define SDMA2_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
39733 | //SDMA2_GFX_IB_SUB_REMAIN |
39734 | #define SDMA2_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
39735 | #define SDMA2_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
39736 | //SDMA2_GFX_PREEMPT |
39737 | #define SDMA2_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
39738 | #define SDMA2_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
39739 | //SDMA2_GFX_DUMMY_REG |
39740 | #define SDMA2_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 |
39741 | #define SDMA2_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
39742 | //SDMA2_GFX_RB_WPTR_POLL_ADDR_HI |
39743 | #define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
39744 | #define SDMA2_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
39745 | //SDMA2_GFX_RB_WPTR_POLL_ADDR_LO |
39746 | #define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
39747 | #define SDMA2_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
39748 | //SDMA2_GFX_RB_AQL_CNTL |
39749 | #define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
39750 | #define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
39751 | #define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
39752 | #define SDMA2_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
39753 | #define SDMA2_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
39754 | #define SDMA2_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
39755 | #define SDMA2_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
39756 | #define SDMA2_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
39757 | #define SDMA2_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
39758 | #define SDMA2_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
39759 | #define SDMA2_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
39760 | #define SDMA2_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
39761 | //SDMA2_GFX_MINOR_PTR_UPDATE |
39762 | #define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
39763 | #define SDMA2_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
39764 | //SDMA2_GFX_MIDCMD_DATA0 |
39765 | #define SDMA2_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
39766 | #define SDMA2_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
39767 | //SDMA2_GFX_MIDCMD_DATA1 |
39768 | #define SDMA2_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
39769 | #define SDMA2_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
39770 | //SDMA2_GFX_MIDCMD_DATA2 |
39771 | #define SDMA2_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
39772 | #define SDMA2_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
39773 | //SDMA2_GFX_MIDCMD_DATA3 |
39774 | #define SDMA2_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
39775 | #define SDMA2_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
39776 | //SDMA2_GFX_MIDCMD_DATA4 |
39777 | #define SDMA2_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
39778 | #define SDMA2_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
39779 | //SDMA2_GFX_MIDCMD_DATA5 |
39780 | #define SDMA2_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
39781 | #define SDMA2_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
39782 | //SDMA2_GFX_MIDCMD_DATA6 |
39783 | #define SDMA2_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
39784 | #define SDMA2_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
39785 | //SDMA2_GFX_MIDCMD_DATA7 |
39786 | #define SDMA2_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
39787 | #define SDMA2_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
39788 | //SDMA2_GFX_MIDCMD_DATA8 |
39789 | #define SDMA2_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
39790 | #define SDMA2_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
39791 | //SDMA2_GFX_MIDCMD_DATA9 |
39792 | #define SDMA2_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
39793 | #define SDMA2_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
39794 | //SDMA2_GFX_MIDCMD_DATA10 |
39795 | #define SDMA2_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
39796 | #define SDMA2_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
39797 | //SDMA2_GFX_MIDCMD_CNTL |
39798 | #define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
39799 | #define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
39800 | #define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
39801 | #define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
39802 | #define SDMA2_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
39803 | #define SDMA2_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
39804 | #define SDMA2_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
39805 | #define SDMA2_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
39806 | //SDMA2_PAGE_RB_CNTL |
39807 | #define SDMA2_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
39808 | #define SDMA2_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 |
39809 | #define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
39810 | #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
39811 | #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
39812 | #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
39813 | #define SDMA2_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 |
39814 | #define SDMA2_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 |
39815 | #define SDMA2_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
39816 | #define SDMA2_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
39817 | #define SDMA2_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
39818 | #define SDMA2_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
39819 | #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
39820 | #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
39821 | #define SDMA2_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
39822 | #define SDMA2_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L |
39823 | #define SDMA2_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L |
39824 | #define SDMA2_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
39825 | //SDMA2_PAGE_RB_BASE |
39826 | #define SDMA2_PAGE_RB_BASE__ADDR__SHIFT 0x0 |
39827 | #define SDMA2_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
39828 | //SDMA2_PAGE_RB_BASE_HI |
39829 | #define SDMA2_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 |
39830 | #define SDMA2_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
39831 | //SDMA2_PAGE_RB_RPTR |
39832 | #define SDMA2_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 |
39833 | #define SDMA2_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
39834 | //SDMA2_PAGE_RB_RPTR_HI |
39835 | #define SDMA2_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
39836 | #define SDMA2_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
39837 | //SDMA2_PAGE_RB_WPTR |
39838 | #define SDMA2_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 |
39839 | #define SDMA2_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
39840 | //SDMA2_PAGE_RB_WPTR_HI |
39841 | #define SDMA2_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
39842 | #define SDMA2_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
39843 | //SDMA2_PAGE_RB_WPTR_POLL_CNTL |
39844 | #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
39845 | #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
39846 | #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
39847 | #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
39848 | #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
39849 | #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
39850 | #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
39851 | #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
39852 | #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
39853 | #define SDMA2_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
39854 | //SDMA2_PAGE_RB_RPTR_ADDR_HI |
39855 | #define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
39856 | #define SDMA2_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
39857 | //SDMA2_PAGE_RB_RPTR_ADDR_LO |
39858 | #define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
39859 | #define SDMA2_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
39860 | //SDMA2_PAGE_IB_CNTL |
39861 | #define SDMA2_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
39862 | #define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
39863 | #define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
39864 | #define SDMA2_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 |
39865 | #define SDMA2_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
39866 | #define SDMA2_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
39867 | #define SDMA2_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
39868 | #define SDMA2_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
39869 | //SDMA2_PAGE_IB_RPTR |
39870 | #define SDMA2_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 |
39871 | #define SDMA2_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
39872 | //SDMA2_PAGE_IB_OFFSET |
39873 | #define SDMA2_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 |
39874 | #define SDMA2_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
39875 | //SDMA2_PAGE_IB_BASE_LO |
39876 | #define SDMA2_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 |
39877 | #define SDMA2_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
39878 | //SDMA2_PAGE_IB_BASE_HI |
39879 | #define SDMA2_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 |
39880 | #define SDMA2_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
39881 | //SDMA2_PAGE_IB_SIZE |
39882 | #define SDMA2_PAGE_IB_SIZE__SIZE__SHIFT 0x0 |
39883 | #define SDMA2_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL |
39884 | //SDMA2_PAGE_SKIP_CNTL |
39885 | #define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
39886 | #define SDMA2_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
39887 | //SDMA2_PAGE_CONTEXT_STATUS |
39888 | #define SDMA2_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
39889 | #define SDMA2_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
39890 | #define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
39891 | #define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
39892 | #define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
39893 | #define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
39894 | #define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
39895 | #define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
39896 | #define SDMA2_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
39897 | #define SDMA2_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
39898 | #define SDMA2_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
39899 | #define SDMA2_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
39900 | #define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
39901 | #define SDMA2_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
39902 | #define SDMA2_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
39903 | #define SDMA2_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
39904 | //SDMA2_PAGE_DOORBELL |
39905 | #define SDMA2_PAGE_DOORBELL__ENABLE__SHIFT 0x1c |
39906 | #define SDMA2_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e |
39907 | #define SDMA2_PAGE_DOORBELL__ENABLE_MASK 0x10000000L |
39908 | #define SDMA2_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L |
39909 | //SDMA2_PAGE_STATUS |
39910 | #define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
39911 | #define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
39912 | #define SDMA2_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
39913 | #define SDMA2_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
39914 | //SDMA2_PAGE_DOORBELL_LOG |
39915 | #define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
39916 | #define SDMA2_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 |
39917 | #define SDMA2_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
39918 | #define SDMA2_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
39919 | //SDMA2_PAGE_WATERMARK |
39920 | #define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
39921 | #define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
39922 | #define SDMA2_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
39923 | #define SDMA2_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
39924 | //SDMA2_PAGE_DOORBELL_OFFSET |
39925 | #define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
39926 | #define SDMA2_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
39927 | //SDMA2_PAGE_CSA_ADDR_LO |
39928 | #define SDMA2_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
39929 | #define SDMA2_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
39930 | //SDMA2_PAGE_CSA_ADDR_HI |
39931 | #define SDMA2_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
39932 | #define SDMA2_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
39933 | //SDMA2_PAGE_IB_SUB_REMAIN |
39934 | #define SDMA2_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
39935 | #define SDMA2_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
39936 | //SDMA2_PAGE_PREEMPT |
39937 | #define SDMA2_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
39938 | #define SDMA2_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
39939 | //SDMA2_PAGE_DUMMY_REG |
39940 | #define SDMA2_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 |
39941 | #define SDMA2_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
39942 | //SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI |
39943 | #define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
39944 | #define SDMA2_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
39945 | //SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO |
39946 | #define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
39947 | #define SDMA2_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
39948 | //SDMA2_PAGE_RB_AQL_CNTL |
39949 | #define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
39950 | #define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
39951 | #define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
39952 | #define SDMA2_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
39953 | #define SDMA2_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
39954 | #define SDMA2_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
39955 | #define SDMA2_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
39956 | #define SDMA2_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
39957 | #define SDMA2_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
39958 | #define SDMA2_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
39959 | #define SDMA2_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
39960 | #define SDMA2_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
39961 | //SDMA2_PAGE_MINOR_PTR_UPDATE |
39962 | #define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
39963 | #define SDMA2_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
39964 | //SDMA2_PAGE_MIDCMD_DATA0 |
39965 | #define SDMA2_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
39966 | #define SDMA2_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
39967 | //SDMA2_PAGE_MIDCMD_DATA1 |
39968 | #define SDMA2_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
39969 | #define SDMA2_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
39970 | //SDMA2_PAGE_MIDCMD_DATA2 |
39971 | #define SDMA2_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
39972 | #define SDMA2_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
39973 | //SDMA2_PAGE_MIDCMD_DATA3 |
39974 | #define SDMA2_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
39975 | #define SDMA2_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
39976 | //SDMA2_PAGE_MIDCMD_DATA4 |
39977 | #define SDMA2_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
39978 | #define SDMA2_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
39979 | //SDMA2_PAGE_MIDCMD_DATA5 |
39980 | #define SDMA2_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
39981 | #define SDMA2_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
39982 | //SDMA2_PAGE_MIDCMD_DATA6 |
39983 | #define SDMA2_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
39984 | #define SDMA2_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
39985 | //SDMA2_PAGE_MIDCMD_DATA7 |
39986 | #define SDMA2_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
39987 | #define SDMA2_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
39988 | //SDMA2_PAGE_MIDCMD_DATA8 |
39989 | #define SDMA2_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
39990 | #define SDMA2_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
39991 | //SDMA2_PAGE_MIDCMD_DATA9 |
39992 | #define SDMA2_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
39993 | #define SDMA2_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
39994 | //SDMA2_PAGE_MIDCMD_DATA10 |
39995 | #define SDMA2_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
39996 | #define SDMA2_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
39997 | //SDMA2_PAGE_MIDCMD_CNTL |
39998 | #define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
39999 | #define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
40000 | #define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
40001 | #define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
40002 | #define SDMA2_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
40003 | #define SDMA2_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
40004 | #define SDMA2_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
40005 | #define SDMA2_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
40006 | //SDMA2_RLC0_RB_CNTL |
40007 | #define SDMA2_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
40008 | #define SDMA2_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 |
40009 | #define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
40010 | #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
40011 | #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
40012 | #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
40013 | #define SDMA2_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 |
40014 | #define SDMA2_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 |
40015 | #define SDMA2_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
40016 | #define SDMA2_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
40017 | #define SDMA2_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
40018 | #define SDMA2_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
40019 | #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
40020 | #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
40021 | #define SDMA2_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
40022 | #define SDMA2_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L |
40023 | #define SDMA2_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L |
40024 | #define SDMA2_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
40025 | //SDMA2_RLC0_RB_BASE |
40026 | #define SDMA2_RLC0_RB_BASE__ADDR__SHIFT 0x0 |
40027 | #define SDMA2_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
40028 | //SDMA2_RLC0_RB_BASE_HI |
40029 | #define SDMA2_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 |
40030 | #define SDMA2_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
40031 | //SDMA2_RLC0_RB_RPTR |
40032 | #define SDMA2_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 |
40033 | #define SDMA2_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
40034 | //SDMA2_RLC0_RB_RPTR_HI |
40035 | #define SDMA2_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
40036 | #define SDMA2_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
40037 | //SDMA2_RLC0_RB_WPTR |
40038 | #define SDMA2_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 |
40039 | #define SDMA2_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
40040 | //SDMA2_RLC0_RB_WPTR_HI |
40041 | #define SDMA2_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
40042 | #define SDMA2_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
40043 | //SDMA2_RLC0_RB_WPTR_POLL_CNTL |
40044 | #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
40045 | #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
40046 | #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
40047 | #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
40048 | #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
40049 | #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
40050 | #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
40051 | #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
40052 | #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
40053 | #define SDMA2_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
40054 | //SDMA2_RLC0_RB_RPTR_ADDR_HI |
40055 | #define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
40056 | #define SDMA2_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40057 | //SDMA2_RLC0_RB_RPTR_ADDR_LO |
40058 | #define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
40059 | #define SDMA2_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40060 | //SDMA2_RLC0_IB_CNTL |
40061 | #define SDMA2_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
40062 | #define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
40063 | #define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
40064 | #define SDMA2_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 |
40065 | #define SDMA2_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
40066 | #define SDMA2_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
40067 | #define SDMA2_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
40068 | #define SDMA2_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
40069 | //SDMA2_RLC0_IB_RPTR |
40070 | #define SDMA2_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 |
40071 | #define SDMA2_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
40072 | //SDMA2_RLC0_IB_OFFSET |
40073 | #define SDMA2_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 |
40074 | #define SDMA2_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
40075 | //SDMA2_RLC0_IB_BASE_LO |
40076 | #define SDMA2_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 |
40077 | #define SDMA2_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
40078 | //SDMA2_RLC0_IB_BASE_HI |
40079 | #define SDMA2_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 |
40080 | #define SDMA2_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
40081 | //SDMA2_RLC0_IB_SIZE |
40082 | #define SDMA2_RLC0_IB_SIZE__SIZE__SHIFT 0x0 |
40083 | #define SDMA2_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL |
40084 | //SDMA2_RLC0_SKIP_CNTL |
40085 | #define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
40086 | #define SDMA2_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
40087 | //SDMA2_RLC0_CONTEXT_STATUS |
40088 | #define SDMA2_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
40089 | #define SDMA2_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
40090 | #define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
40091 | #define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
40092 | #define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
40093 | #define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
40094 | #define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
40095 | #define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
40096 | #define SDMA2_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
40097 | #define SDMA2_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
40098 | #define SDMA2_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
40099 | #define SDMA2_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
40100 | #define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
40101 | #define SDMA2_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
40102 | #define SDMA2_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
40103 | #define SDMA2_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
40104 | //SDMA2_RLC0_DOORBELL |
40105 | #define SDMA2_RLC0_DOORBELL__ENABLE__SHIFT 0x1c |
40106 | #define SDMA2_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e |
40107 | #define SDMA2_RLC0_DOORBELL__ENABLE_MASK 0x10000000L |
40108 | #define SDMA2_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L |
40109 | //SDMA2_RLC0_STATUS |
40110 | #define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
40111 | #define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
40112 | #define SDMA2_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
40113 | #define SDMA2_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
40114 | //SDMA2_RLC0_DOORBELL_LOG |
40115 | #define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
40116 | #define SDMA2_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 |
40117 | #define SDMA2_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
40118 | #define SDMA2_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
40119 | //SDMA2_RLC0_WATERMARK |
40120 | #define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
40121 | #define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
40122 | #define SDMA2_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
40123 | #define SDMA2_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
40124 | //SDMA2_RLC0_DOORBELL_OFFSET |
40125 | #define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
40126 | #define SDMA2_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
40127 | //SDMA2_RLC0_CSA_ADDR_LO |
40128 | #define SDMA2_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
40129 | #define SDMA2_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40130 | //SDMA2_RLC0_CSA_ADDR_HI |
40131 | #define SDMA2_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
40132 | #define SDMA2_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40133 | //SDMA2_RLC0_IB_SUB_REMAIN |
40134 | #define SDMA2_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
40135 | #define SDMA2_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
40136 | //SDMA2_RLC0_PREEMPT |
40137 | #define SDMA2_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
40138 | #define SDMA2_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
40139 | //SDMA2_RLC0_DUMMY_REG |
40140 | #define SDMA2_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 |
40141 | #define SDMA2_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
40142 | //SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI |
40143 | #define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
40144 | #define SDMA2_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40145 | //SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO |
40146 | #define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
40147 | #define SDMA2_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40148 | //SDMA2_RLC0_RB_AQL_CNTL |
40149 | #define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
40150 | #define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
40151 | #define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
40152 | #define SDMA2_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
40153 | #define SDMA2_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
40154 | #define SDMA2_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
40155 | #define SDMA2_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
40156 | #define SDMA2_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
40157 | #define SDMA2_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
40158 | #define SDMA2_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
40159 | #define SDMA2_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
40160 | #define SDMA2_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
40161 | //SDMA2_RLC0_MINOR_PTR_UPDATE |
40162 | #define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
40163 | #define SDMA2_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
40164 | //SDMA2_RLC0_MIDCMD_DATA0 |
40165 | #define SDMA2_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
40166 | #define SDMA2_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
40167 | //SDMA2_RLC0_MIDCMD_DATA1 |
40168 | #define SDMA2_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
40169 | #define SDMA2_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
40170 | //SDMA2_RLC0_MIDCMD_DATA2 |
40171 | #define SDMA2_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
40172 | #define SDMA2_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
40173 | //SDMA2_RLC0_MIDCMD_DATA3 |
40174 | #define SDMA2_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
40175 | #define SDMA2_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
40176 | //SDMA2_RLC0_MIDCMD_DATA4 |
40177 | #define SDMA2_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
40178 | #define SDMA2_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
40179 | //SDMA2_RLC0_MIDCMD_DATA5 |
40180 | #define SDMA2_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
40181 | #define SDMA2_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
40182 | //SDMA2_RLC0_MIDCMD_DATA6 |
40183 | #define SDMA2_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
40184 | #define SDMA2_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
40185 | //SDMA2_RLC0_MIDCMD_DATA7 |
40186 | #define SDMA2_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
40187 | #define SDMA2_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
40188 | //SDMA2_RLC0_MIDCMD_DATA8 |
40189 | #define SDMA2_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
40190 | #define SDMA2_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
40191 | //SDMA2_RLC0_MIDCMD_DATA9 |
40192 | #define SDMA2_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
40193 | #define SDMA2_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
40194 | //SDMA2_RLC0_MIDCMD_DATA10 |
40195 | #define SDMA2_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
40196 | #define SDMA2_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
40197 | //SDMA2_RLC0_MIDCMD_CNTL |
40198 | #define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
40199 | #define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
40200 | #define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
40201 | #define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
40202 | #define SDMA2_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
40203 | #define SDMA2_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
40204 | #define SDMA2_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
40205 | #define SDMA2_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
40206 | //SDMA2_RLC1_RB_CNTL |
40207 | #define SDMA2_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
40208 | #define SDMA2_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 |
40209 | #define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
40210 | #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
40211 | #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
40212 | #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
40213 | #define SDMA2_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 |
40214 | #define SDMA2_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 |
40215 | #define SDMA2_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
40216 | #define SDMA2_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
40217 | #define SDMA2_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
40218 | #define SDMA2_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
40219 | #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
40220 | #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
40221 | #define SDMA2_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
40222 | #define SDMA2_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L |
40223 | #define SDMA2_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L |
40224 | #define SDMA2_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
40225 | //SDMA2_RLC1_RB_BASE |
40226 | #define SDMA2_RLC1_RB_BASE__ADDR__SHIFT 0x0 |
40227 | #define SDMA2_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
40228 | //SDMA2_RLC1_RB_BASE_HI |
40229 | #define SDMA2_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 |
40230 | #define SDMA2_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
40231 | //SDMA2_RLC1_RB_RPTR |
40232 | #define SDMA2_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 |
40233 | #define SDMA2_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
40234 | //SDMA2_RLC1_RB_RPTR_HI |
40235 | #define SDMA2_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
40236 | #define SDMA2_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
40237 | //SDMA2_RLC1_RB_WPTR |
40238 | #define SDMA2_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 |
40239 | #define SDMA2_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
40240 | //SDMA2_RLC1_RB_WPTR_HI |
40241 | #define SDMA2_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
40242 | #define SDMA2_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
40243 | //SDMA2_RLC1_RB_WPTR_POLL_CNTL |
40244 | #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
40245 | #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
40246 | #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
40247 | #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
40248 | #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
40249 | #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
40250 | #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
40251 | #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
40252 | #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
40253 | #define SDMA2_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
40254 | //SDMA2_RLC1_RB_RPTR_ADDR_HI |
40255 | #define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
40256 | #define SDMA2_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40257 | //SDMA2_RLC1_RB_RPTR_ADDR_LO |
40258 | #define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
40259 | #define SDMA2_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40260 | //SDMA2_RLC1_IB_CNTL |
40261 | #define SDMA2_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
40262 | #define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
40263 | #define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
40264 | #define SDMA2_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 |
40265 | #define SDMA2_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
40266 | #define SDMA2_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
40267 | #define SDMA2_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
40268 | #define SDMA2_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
40269 | //SDMA2_RLC1_IB_RPTR |
40270 | #define SDMA2_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 |
40271 | #define SDMA2_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
40272 | //SDMA2_RLC1_IB_OFFSET |
40273 | #define SDMA2_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 |
40274 | #define SDMA2_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
40275 | //SDMA2_RLC1_IB_BASE_LO |
40276 | #define SDMA2_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 |
40277 | #define SDMA2_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
40278 | //SDMA2_RLC1_IB_BASE_HI |
40279 | #define SDMA2_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 |
40280 | #define SDMA2_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
40281 | //SDMA2_RLC1_IB_SIZE |
40282 | #define SDMA2_RLC1_IB_SIZE__SIZE__SHIFT 0x0 |
40283 | #define SDMA2_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL |
40284 | //SDMA2_RLC1_SKIP_CNTL |
40285 | #define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
40286 | #define SDMA2_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
40287 | //SDMA2_RLC1_CONTEXT_STATUS |
40288 | #define SDMA2_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
40289 | #define SDMA2_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
40290 | #define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
40291 | #define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
40292 | #define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
40293 | #define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
40294 | #define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
40295 | #define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
40296 | #define SDMA2_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
40297 | #define SDMA2_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
40298 | #define SDMA2_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
40299 | #define SDMA2_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
40300 | #define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
40301 | #define SDMA2_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
40302 | #define SDMA2_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
40303 | #define SDMA2_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
40304 | //SDMA2_RLC1_DOORBELL |
40305 | #define SDMA2_RLC1_DOORBELL__ENABLE__SHIFT 0x1c |
40306 | #define SDMA2_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e |
40307 | #define SDMA2_RLC1_DOORBELL__ENABLE_MASK 0x10000000L |
40308 | #define SDMA2_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L |
40309 | //SDMA2_RLC1_STATUS |
40310 | #define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
40311 | #define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
40312 | #define SDMA2_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
40313 | #define SDMA2_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
40314 | //SDMA2_RLC1_DOORBELL_LOG |
40315 | #define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
40316 | #define SDMA2_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 |
40317 | #define SDMA2_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
40318 | #define SDMA2_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
40319 | //SDMA2_RLC1_WATERMARK |
40320 | #define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
40321 | #define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
40322 | #define SDMA2_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
40323 | #define SDMA2_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
40324 | //SDMA2_RLC1_DOORBELL_OFFSET |
40325 | #define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
40326 | #define SDMA2_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
40327 | //SDMA2_RLC1_CSA_ADDR_LO |
40328 | #define SDMA2_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
40329 | #define SDMA2_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40330 | //SDMA2_RLC1_CSA_ADDR_HI |
40331 | #define SDMA2_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
40332 | #define SDMA2_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40333 | //SDMA2_RLC1_IB_SUB_REMAIN |
40334 | #define SDMA2_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
40335 | #define SDMA2_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
40336 | //SDMA2_RLC1_PREEMPT |
40337 | #define SDMA2_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
40338 | #define SDMA2_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
40339 | //SDMA2_RLC1_DUMMY_REG |
40340 | #define SDMA2_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 |
40341 | #define SDMA2_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
40342 | //SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI |
40343 | #define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
40344 | #define SDMA2_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40345 | //SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO |
40346 | #define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
40347 | #define SDMA2_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40348 | //SDMA2_RLC1_RB_AQL_CNTL |
40349 | #define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
40350 | #define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
40351 | #define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
40352 | #define SDMA2_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
40353 | #define SDMA2_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
40354 | #define SDMA2_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
40355 | #define SDMA2_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
40356 | #define SDMA2_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
40357 | #define SDMA2_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
40358 | #define SDMA2_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
40359 | #define SDMA2_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
40360 | #define SDMA2_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
40361 | //SDMA2_RLC1_MINOR_PTR_UPDATE |
40362 | #define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
40363 | #define SDMA2_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
40364 | //SDMA2_RLC1_MIDCMD_DATA0 |
40365 | #define SDMA2_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
40366 | #define SDMA2_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
40367 | //SDMA2_RLC1_MIDCMD_DATA1 |
40368 | #define SDMA2_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
40369 | #define SDMA2_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
40370 | //SDMA2_RLC1_MIDCMD_DATA2 |
40371 | #define SDMA2_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
40372 | #define SDMA2_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
40373 | //SDMA2_RLC1_MIDCMD_DATA3 |
40374 | #define SDMA2_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
40375 | #define SDMA2_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
40376 | //SDMA2_RLC1_MIDCMD_DATA4 |
40377 | #define SDMA2_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
40378 | #define SDMA2_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
40379 | //SDMA2_RLC1_MIDCMD_DATA5 |
40380 | #define SDMA2_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
40381 | #define SDMA2_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
40382 | //SDMA2_RLC1_MIDCMD_DATA6 |
40383 | #define SDMA2_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
40384 | #define SDMA2_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
40385 | //SDMA2_RLC1_MIDCMD_DATA7 |
40386 | #define SDMA2_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
40387 | #define SDMA2_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
40388 | //SDMA2_RLC1_MIDCMD_DATA8 |
40389 | #define SDMA2_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
40390 | #define SDMA2_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
40391 | //SDMA2_RLC1_MIDCMD_DATA9 |
40392 | #define SDMA2_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
40393 | #define SDMA2_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
40394 | //SDMA2_RLC1_MIDCMD_DATA10 |
40395 | #define SDMA2_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
40396 | #define SDMA2_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
40397 | //SDMA2_RLC1_MIDCMD_CNTL |
40398 | #define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
40399 | #define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
40400 | #define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
40401 | #define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
40402 | #define SDMA2_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
40403 | #define SDMA2_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
40404 | #define SDMA2_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
40405 | #define SDMA2_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
40406 | //SDMA2_RLC2_RB_CNTL |
40407 | #define SDMA2_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
40408 | #define SDMA2_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 |
40409 | #define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
40410 | #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
40411 | #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
40412 | #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
40413 | #define SDMA2_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 |
40414 | #define SDMA2_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 |
40415 | #define SDMA2_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
40416 | #define SDMA2_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
40417 | #define SDMA2_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
40418 | #define SDMA2_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
40419 | #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
40420 | #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
40421 | #define SDMA2_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
40422 | #define SDMA2_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L |
40423 | #define SDMA2_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L |
40424 | #define SDMA2_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
40425 | //SDMA2_RLC2_RB_BASE |
40426 | #define SDMA2_RLC2_RB_BASE__ADDR__SHIFT 0x0 |
40427 | #define SDMA2_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
40428 | //SDMA2_RLC2_RB_BASE_HI |
40429 | #define SDMA2_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 |
40430 | #define SDMA2_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
40431 | //SDMA2_RLC2_RB_RPTR |
40432 | #define SDMA2_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 |
40433 | #define SDMA2_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
40434 | //SDMA2_RLC2_RB_RPTR_HI |
40435 | #define SDMA2_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
40436 | #define SDMA2_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
40437 | //SDMA2_RLC2_RB_WPTR |
40438 | #define SDMA2_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 |
40439 | #define SDMA2_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
40440 | //SDMA2_RLC2_RB_WPTR_HI |
40441 | #define SDMA2_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
40442 | #define SDMA2_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
40443 | //SDMA2_RLC2_RB_WPTR_POLL_CNTL |
40444 | #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
40445 | #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
40446 | #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
40447 | #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
40448 | #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
40449 | #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
40450 | #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
40451 | #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
40452 | #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
40453 | #define SDMA2_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
40454 | //SDMA2_RLC2_RB_RPTR_ADDR_HI |
40455 | #define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
40456 | #define SDMA2_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40457 | //SDMA2_RLC2_RB_RPTR_ADDR_LO |
40458 | #define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
40459 | #define SDMA2_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40460 | //SDMA2_RLC2_IB_CNTL |
40461 | #define SDMA2_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
40462 | #define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
40463 | #define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
40464 | #define SDMA2_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 |
40465 | #define SDMA2_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
40466 | #define SDMA2_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
40467 | #define SDMA2_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
40468 | #define SDMA2_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
40469 | //SDMA2_RLC2_IB_RPTR |
40470 | #define SDMA2_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 |
40471 | #define SDMA2_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
40472 | //SDMA2_RLC2_IB_OFFSET |
40473 | #define SDMA2_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 |
40474 | #define SDMA2_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
40475 | //SDMA2_RLC2_IB_BASE_LO |
40476 | #define SDMA2_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 |
40477 | #define SDMA2_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
40478 | //SDMA2_RLC2_IB_BASE_HI |
40479 | #define SDMA2_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 |
40480 | #define SDMA2_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
40481 | //SDMA2_RLC2_IB_SIZE |
40482 | #define SDMA2_RLC2_IB_SIZE__SIZE__SHIFT 0x0 |
40483 | #define SDMA2_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL |
40484 | //SDMA2_RLC2_SKIP_CNTL |
40485 | #define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
40486 | #define SDMA2_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
40487 | //SDMA2_RLC2_CONTEXT_STATUS |
40488 | #define SDMA2_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
40489 | #define SDMA2_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
40490 | #define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
40491 | #define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
40492 | #define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
40493 | #define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
40494 | #define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
40495 | #define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
40496 | #define SDMA2_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
40497 | #define SDMA2_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
40498 | #define SDMA2_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
40499 | #define SDMA2_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
40500 | #define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
40501 | #define SDMA2_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
40502 | #define SDMA2_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
40503 | #define SDMA2_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
40504 | //SDMA2_RLC2_DOORBELL |
40505 | #define SDMA2_RLC2_DOORBELL__ENABLE__SHIFT 0x1c |
40506 | #define SDMA2_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e |
40507 | #define SDMA2_RLC2_DOORBELL__ENABLE_MASK 0x10000000L |
40508 | #define SDMA2_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L |
40509 | //SDMA2_RLC2_STATUS |
40510 | #define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
40511 | #define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
40512 | #define SDMA2_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
40513 | #define SDMA2_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
40514 | //SDMA2_RLC2_DOORBELL_LOG |
40515 | #define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
40516 | #define SDMA2_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 |
40517 | #define SDMA2_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
40518 | #define SDMA2_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
40519 | //SDMA2_RLC2_WATERMARK |
40520 | #define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
40521 | #define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
40522 | #define SDMA2_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
40523 | #define SDMA2_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
40524 | //SDMA2_RLC2_DOORBELL_OFFSET |
40525 | #define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
40526 | #define SDMA2_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
40527 | //SDMA2_RLC2_CSA_ADDR_LO |
40528 | #define SDMA2_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
40529 | #define SDMA2_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40530 | //SDMA2_RLC2_CSA_ADDR_HI |
40531 | #define SDMA2_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
40532 | #define SDMA2_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40533 | //SDMA2_RLC2_IB_SUB_REMAIN |
40534 | #define SDMA2_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
40535 | #define SDMA2_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
40536 | //SDMA2_RLC2_PREEMPT |
40537 | #define SDMA2_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
40538 | #define SDMA2_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
40539 | //SDMA2_RLC2_DUMMY_REG |
40540 | #define SDMA2_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 |
40541 | #define SDMA2_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
40542 | //SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI |
40543 | #define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
40544 | #define SDMA2_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40545 | //SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO |
40546 | #define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
40547 | #define SDMA2_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40548 | //SDMA2_RLC2_RB_AQL_CNTL |
40549 | #define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
40550 | #define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
40551 | #define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
40552 | #define SDMA2_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
40553 | #define SDMA2_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
40554 | #define SDMA2_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
40555 | #define SDMA2_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
40556 | #define SDMA2_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
40557 | #define SDMA2_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
40558 | #define SDMA2_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
40559 | #define SDMA2_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
40560 | #define SDMA2_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
40561 | //SDMA2_RLC2_MINOR_PTR_UPDATE |
40562 | #define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
40563 | #define SDMA2_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
40564 | //SDMA2_RLC2_MIDCMD_DATA0 |
40565 | #define SDMA2_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
40566 | #define SDMA2_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
40567 | //SDMA2_RLC2_MIDCMD_DATA1 |
40568 | #define SDMA2_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
40569 | #define SDMA2_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
40570 | //SDMA2_RLC2_MIDCMD_DATA2 |
40571 | #define SDMA2_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
40572 | #define SDMA2_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
40573 | //SDMA2_RLC2_MIDCMD_DATA3 |
40574 | #define SDMA2_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
40575 | #define SDMA2_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
40576 | //SDMA2_RLC2_MIDCMD_DATA4 |
40577 | #define SDMA2_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
40578 | #define SDMA2_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
40579 | //SDMA2_RLC2_MIDCMD_DATA5 |
40580 | #define SDMA2_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
40581 | #define SDMA2_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
40582 | //SDMA2_RLC2_MIDCMD_DATA6 |
40583 | #define SDMA2_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
40584 | #define SDMA2_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
40585 | //SDMA2_RLC2_MIDCMD_DATA7 |
40586 | #define SDMA2_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
40587 | #define SDMA2_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
40588 | //SDMA2_RLC2_MIDCMD_DATA8 |
40589 | #define SDMA2_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
40590 | #define SDMA2_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
40591 | //SDMA2_RLC2_MIDCMD_DATA9 |
40592 | #define SDMA2_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
40593 | #define SDMA2_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
40594 | //SDMA2_RLC2_MIDCMD_DATA10 |
40595 | #define SDMA2_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
40596 | #define SDMA2_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
40597 | //SDMA2_RLC2_MIDCMD_CNTL |
40598 | #define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
40599 | #define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
40600 | #define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
40601 | #define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
40602 | #define SDMA2_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
40603 | #define SDMA2_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
40604 | #define SDMA2_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
40605 | #define SDMA2_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
40606 | //SDMA2_RLC3_RB_CNTL |
40607 | #define SDMA2_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
40608 | #define SDMA2_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 |
40609 | #define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
40610 | #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
40611 | #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
40612 | #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
40613 | #define SDMA2_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 |
40614 | #define SDMA2_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 |
40615 | #define SDMA2_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
40616 | #define SDMA2_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
40617 | #define SDMA2_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
40618 | #define SDMA2_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
40619 | #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
40620 | #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
40621 | #define SDMA2_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
40622 | #define SDMA2_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L |
40623 | #define SDMA2_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L |
40624 | #define SDMA2_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
40625 | //SDMA2_RLC3_RB_BASE |
40626 | #define SDMA2_RLC3_RB_BASE__ADDR__SHIFT 0x0 |
40627 | #define SDMA2_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
40628 | //SDMA2_RLC3_RB_BASE_HI |
40629 | #define SDMA2_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 |
40630 | #define SDMA2_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
40631 | //SDMA2_RLC3_RB_RPTR |
40632 | #define SDMA2_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 |
40633 | #define SDMA2_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
40634 | //SDMA2_RLC3_RB_RPTR_HI |
40635 | #define SDMA2_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
40636 | #define SDMA2_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
40637 | //SDMA2_RLC3_RB_WPTR |
40638 | #define SDMA2_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 |
40639 | #define SDMA2_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
40640 | //SDMA2_RLC3_RB_WPTR_HI |
40641 | #define SDMA2_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
40642 | #define SDMA2_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
40643 | //SDMA2_RLC3_RB_WPTR_POLL_CNTL |
40644 | #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
40645 | #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
40646 | #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
40647 | #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
40648 | #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
40649 | #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
40650 | #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
40651 | #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
40652 | #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
40653 | #define SDMA2_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
40654 | //SDMA2_RLC3_RB_RPTR_ADDR_HI |
40655 | #define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
40656 | #define SDMA2_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40657 | //SDMA2_RLC3_RB_RPTR_ADDR_LO |
40658 | #define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
40659 | #define SDMA2_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40660 | //SDMA2_RLC3_IB_CNTL |
40661 | #define SDMA2_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
40662 | #define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
40663 | #define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
40664 | #define SDMA2_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 |
40665 | #define SDMA2_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
40666 | #define SDMA2_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
40667 | #define SDMA2_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
40668 | #define SDMA2_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
40669 | //SDMA2_RLC3_IB_RPTR |
40670 | #define SDMA2_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 |
40671 | #define SDMA2_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
40672 | //SDMA2_RLC3_IB_OFFSET |
40673 | #define SDMA2_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 |
40674 | #define SDMA2_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
40675 | //SDMA2_RLC3_IB_BASE_LO |
40676 | #define SDMA2_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 |
40677 | #define SDMA2_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
40678 | //SDMA2_RLC3_IB_BASE_HI |
40679 | #define SDMA2_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 |
40680 | #define SDMA2_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
40681 | //SDMA2_RLC3_IB_SIZE |
40682 | #define SDMA2_RLC3_IB_SIZE__SIZE__SHIFT 0x0 |
40683 | #define SDMA2_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL |
40684 | //SDMA2_RLC3_SKIP_CNTL |
40685 | #define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
40686 | #define SDMA2_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
40687 | //SDMA2_RLC3_CONTEXT_STATUS |
40688 | #define SDMA2_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
40689 | #define SDMA2_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
40690 | #define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
40691 | #define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
40692 | #define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
40693 | #define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
40694 | #define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
40695 | #define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
40696 | #define SDMA2_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
40697 | #define SDMA2_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
40698 | #define SDMA2_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
40699 | #define SDMA2_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
40700 | #define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
40701 | #define SDMA2_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
40702 | #define SDMA2_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
40703 | #define SDMA2_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
40704 | //SDMA2_RLC3_DOORBELL |
40705 | #define SDMA2_RLC3_DOORBELL__ENABLE__SHIFT 0x1c |
40706 | #define SDMA2_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e |
40707 | #define SDMA2_RLC3_DOORBELL__ENABLE_MASK 0x10000000L |
40708 | #define SDMA2_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L |
40709 | //SDMA2_RLC3_STATUS |
40710 | #define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
40711 | #define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
40712 | #define SDMA2_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
40713 | #define SDMA2_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
40714 | //SDMA2_RLC3_DOORBELL_LOG |
40715 | #define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
40716 | #define SDMA2_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 |
40717 | #define SDMA2_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
40718 | #define SDMA2_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
40719 | //SDMA2_RLC3_WATERMARK |
40720 | #define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
40721 | #define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
40722 | #define SDMA2_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
40723 | #define SDMA2_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
40724 | //SDMA2_RLC3_DOORBELL_OFFSET |
40725 | #define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
40726 | #define SDMA2_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
40727 | //SDMA2_RLC3_CSA_ADDR_LO |
40728 | #define SDMA2_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
40729 | #define SDMA2_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40730 | //SDMA2_RLC3_CSA_ADDR_HI |
40731 | #define SDMA2_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
40732 | #define SDMA2_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40733 | //SDMA2_RLC3_IB_SUB_REMAIN |
40734 | #define SDMA2_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
40735 | #define SDMA2_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
40736 | //SDMA2_RLC3_PREEMPT |
40737 | #define SDMA2_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
40738 | #define SDMA2_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
40739 | //SDMA2_RLC3_DUMMY_REG |
40740 | #define SDMA2_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 |
40741 | #define SDMA2_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
40742 | //SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI |
40743 | #define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
40744 | #define SDMA2_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40745 | //SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO |
40746 | #define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
40747 | #define SDMA2_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40748 | //SDMA2_RLC3_RB_AQL_CNTL |
40749 | #define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
40750 | #define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
40751 | #define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
40752 | #define SDMA2_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
40753 | #define SDMA2_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
40754 | #define SDMA2_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
40755 | #define SDMA2_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
40756 | #define SDMA2_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
40757 | #define SDMA2_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
40758 | #define SDMA2_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
40759 | #define SDMA2_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
40760 | #define SDMA2_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
40761 | //SDMA2_RLC3_MINOR_PTR_UPDATE |
40762 | #define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
40763 | #define SDMA2_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
40764 | //SDMA2_RLC3_MIDCMD_DATA0 |
40765 | #define SDMA2_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
40766 | #define SDMA2_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
40767 | //SDMA2_RLC3_MIDCMD_DATA1 |
40768 | #define SDMA2_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
40769 | #define SDMA2_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
40770 | //SDMA2_RLC3_MIDCMD_DATA2 |
40771 | #define SDMA2_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
40772 | #define SDMA2_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
40773 | //SDMA2_RLC3_MIDCMD_DATA3 |
40774 | #define SDMA2_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
40775 | #define SDMA2_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
40776 | //SDMA2_RLC3_MIDCMD_DATA4 |
40777 | #define SDMA2_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
40778 | #define SDMA2_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
40779 | //SDMA2_RLC3_MIDCMD_DATA5 |
40780 | #define SDMA2_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
40781 | #define SDMA2_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
40782 | //SDMA2_RLC3_MIDCMD_DATA6 |
40783 | #define SDMA2_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
40784 | #define SDMA2_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
40785 | //SDMA2_RLC3_MIDCMD_DATA7 |
40786 | #define SDMA2_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
40787 | #define SDMA2_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
40788 | //SDMA2_RLC3_MIDCMD_DATA8 |
40789 | #define SDMA2_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
40790 | #define SDMA2_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
40791 | //SDMA2_RLC3_MIDCMD_DATA9 |
40792 | #define SDMA2_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
40793 | #define SDMA2_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
40794 | //SDMA2_RLC3_MIDCMD_DATA10 |
40795 | #define SDMA2_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
40796 | #define SDMA2_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
40797 | //SDMA2_RLC3_MIDCMD_CNTL |
40798 | #define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
40799 | #define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
40800 | #define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
40801 | #define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
40802 | #define SDMA2_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
40803 | #define SDMA2_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
40804 | #define SDMA2_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
40805 | #define SDMA2_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
40806 | //SDMA2_RLC4_RB_CNTL |
40807 | #define SDMA2_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
40808 | #define SDMA2_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 |
40809 | #define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
40810 | #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
40811 | #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
40812 | #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
40813 | #define SDMA2_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 |
40814 | #define SDMA2_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 |
40815 | #define SDMA2_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
40816 | #define SDMA2_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
40817 | #define SDMA2_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
40818 | #define SDMA2_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
40819 | #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
40820 | #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
40821 | #define SDMA2_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
40822 | #define SDMA2_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L |
40823 | #define SDMA2_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L |
40824 | #define SDMA2_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
40825 | //SDMA2_RLC4_RB_BASE |
40826 | #define SDMA2_RLC4_RB_BASE__ADDR__SHIFT 0x0 |
40827 | #define SDMA2_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
40828 | //SDMA2_RLC4_RB_BASE_HI |
40829 | #define SDMA2_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 |
40830 | #define SDMA2_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
40831 | //SDMA2_RLC4_RB_RPTR |
40832 | #define SDMA2_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 |
40833 | #define SDMA2_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
40834 | //SDMA2_RLC4_RB_RPTR_HI |
40835 | #define SDMA2_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
40836 | #define SDMA2_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
40837 | //SDMA2_RLC4_RB_WPTR |
40838 | #define SDMA2_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 |
40839 | #define SDMA2_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
40840 | //SDMA2_RLC4_RB_WPTR_HI |
40841 | #define SDMA2_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
40842 | #define SDMA2_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
40843 | //SDMA2_RLC4_RB_WPTR_POLL_CNTL |
40844 | #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
40845 | #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
40846 | #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
40847 | #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
40848 | #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
40849 | #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
40850 | #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
40851 | #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
40852 | #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
40853 | #define SDMA2_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
40854 | //SDMA2_RLC4_RB_RPTR_ADDR_HI |
40855 | #define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
40856 | #define SDMA2_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40857 | //SDMA2_RLC4_RB_RPTR_ADDR_LO |
40858 | #define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
40859 | #define SDMA2_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40860 | //SDMA2_RLC4_IB_CNTL |
40861 | #define SDMA2_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
40862 | #define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
40863 | #define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
40864 | #define SDMA2_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 |
40865 | #define SDMA2_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
40866 | #define SDMA2_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
40867 | #define SDMA2_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
40868 | #define SDMA2_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
40869 | //SDMA2_RLC4_IB_RPTR |
40870 | #define SDMA2_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 |
40871 | #define SDMA2_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
40872 | //SDMA2_RLC4_IB_OFFSET |
40873 | #define SDMA2_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 |
40874 | #define SDMA2_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
40875 | //SDMA2_RLC4_IB_BASE_LO |
40876 | #define SDMA2_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 |
40877 | #define SDMA2_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
40878 | //SDMA2_RLC4_IB_BASE_HI |
40879 | #define SDMA2_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 |
40880 | #define SDMA2_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
40881 | //SDMA2_RLC4_IB_SIZE |
40882 | #define SDMA2_RLC4_IB_SIZE__SIZE__SHIFT 0x0 |
40883 | #define SDMA2_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL |
40884 | //SDMA2_RLC4_SKIP_CNTL |
40885 | #define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
40886 | #define SDMA2_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
40887 | //SDMA2_RLC4_CONTEXT_STATUS |
40888 | #define SDMA2_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
40889 | #define SDMA2_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
40890 | #define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
40891 | #define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
40892 | #define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
40893 | #define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
40894 | #define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
40895 | #define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
40896 | #define SDMA2_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
40897 | #define SDMA2_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
40898 | #define SDMA2_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
40899 | #define SDMA2_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
40900 | #define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
40901 | #define SDMA2_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
40902 | #define SDMA2_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
40903 | #define SDMA2_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
40904 | //SDMA2_RLC4_DOORBELL |
40905 | #define SDMA2_RLC4_DOORBELL__ENABLE__SHIFT 0x1c |
40906 | #define SDMA2_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e |
40907 | #define SDMA2_RLC4_DOORBELL__ENABLE_MASK 0x10000000L |
40908 | #define SDMA2_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L |
40909 | //SDMA2_RLC4_STATUS |
40910 | #define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
40911 | #define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
40912 | #define SDMA2_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
40913 | #define SDMA2_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
40914 | //SDMA2_RLC4_DOORBELL_LOG |
40915 | #define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
40916 | #define SDMA2_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 |
40917 | #define SDMA2_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
40918 | #define SDMA2_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
40919 | //SDMA2_RLC4_WATERMARK |
40920 | #define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
40921 | #define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
40922 | #define SDMA2_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
40923 | #define SDMA2_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
40924 | //SDMA2_RLC4_DOORBELL_OFFSET |
40925 | #define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
40926 | #define SDMA2_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
40927 | //SDMA2_RLC4_CSA_ADDR_LO |
40928 | #define SDMA2_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
40929 | #define SDMA2_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40930 | //SDMA2_RLC4_CSA_ADDR_HI |
40931 | #define SDMA2_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
40932 | #define SDMA2_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40933 | //SDMA2_RLC4_IB_SUB_REMAIN |
40934 | #define SDMA2_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
40935 | #define SDMA2_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
40936 | //SDMA2_RLC4_PREEMPT |
40937 | #define SDMA2_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
40938 | #define SDMA2_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
40939 | //SDMA2_RLC4_DUMMY_REG |
40940 | #define SDMA2_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 |
40941 | #define SDMA2_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
40942 | //SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI |
40943 | #define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
40944 | #define SDMA2_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
40945 | //SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO |
40946 | #define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
40947 | #define SDMA2_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
40948 | //SDMA2_RLC4_RB_AQL_CNTL |
40949 | #define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
40950 | #define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
40951 | #define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
40952 | #define SDMA2_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
40953 | #define SDMA2_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
40954 | #define SDMA2_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
40955 | #define SDMA2_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
40956 | #define SDMA2_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
40957 | #define SDMA2_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
40958 | #define SDMA2_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
40959 | #define SDMA2_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
40960 | #define SDMA2_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
40961 | //SDMA2_RLC4_MINOR_PTR_UPDATE |
40962 | #define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
40963 | #define SDMA2_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
40964 | //SDMA2_RLC4_MIDCMD_DATA0 |
40965 | #define SDMA2_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
40966 | #define SDMA2_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
40967 | //SDMA2_RLC4_MIDCMD_DATA1 |
40968 | #define SDMA2_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
40969 | #define SDMA2_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
40970 | //SDMA2_RLC4_MIDCMD_DATA2 |
40971 | #define SDMA2_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
40972 | #define SDMA2_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
40973 | //SDMA2_RLC4_MIDCMD_DATA3 |
40974 | #define SDMA2_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
40975 | #define SDMA2_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
40976 | //SDMA2_RLC4_MIDCMD_DATA4 |
40977 | #define SDMA2_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
40978 | #define SDMA2_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
40979 | //SDMA2_RLC4_MIDCMD_DATA5 |
40980 | #define SDMA2_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
40981 | #define SDMA2_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
40982 | //SDMA2_RLC4_MIDCMD_DATA6 |
40983 | #define SDMA2_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
40984 | #define SDMA2_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
40985 | //SDMA2_RLC4_MIDCMD_DATA7 |
40986 | #define SDMA2_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
40987 | #define SDMA2_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
40988 | //SDMA2_RLC4_MIDCMD_DATA8 |
40989 | #define SDMA2_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
40990 | #define SDMA2_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
40991 | //SDMA2_RLC4_MIDCMD_DATA9 |
40992 | #define SDMA2_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
40993 | #define SDMA2_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
40994 | //SDMA2_RLC4_MIDCMD_DATA10 |
40995 | #define SDMA2_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
40996 | #define SDMA2_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
40997 | //SDMA2_RLC4_MIDCMD_CNTL |
40998 | #define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
40999 | #define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
41000 | #define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
41001 | #define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
41002 | #define SDMA2_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
41003 | #define SDMA2_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
41004 | #define SDMA2_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
41005 | #define SDMA2_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
41006 | //SDMA2_RLC5_RB_CNTL |
41007 | #define SDMA2_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
41008 | #define SDMA2_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 |
41009 | #define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
41010 | #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
41011 | #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
41012 | #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
41013 | #define SDMA2_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 |
41014 | #define SDMA2_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 |
41015 | #define SDMA2_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
41016 | #define SDMA2_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
41017 | #define SDMA2_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
41018 | #define SDMA2_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
41019 | #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
41020 | #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
41021 | #define SDMA2_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
41022 | #define SDMA2_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L |
41023 | #define SDMA2_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L |
41024 | #define SDMA2_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
41025 | //SDMA2_RLC5_RB_BASE |
41026 | #define SDMA2_RLC5_RB_BASE__ADDR__SHIFT 0x0 |
41027 | #define SDMA2_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
41028 | //SDMA2_RLC5_RB_BASE_HI |
41029 | #define SDMA2_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 |
41030 | #define SDMA2_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
41031 | //SDMA2_RLC5_RB_RPTR |
41032 | #define SDMA2_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 |
41033 | #define SDMA2_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
41034 | //SDMA2_RLC5_RB_RPTR_HI |
41035 | #define SDMA2_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
41036 | #define SDMA2_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
41037 | //SDMA2_RLC5_RB_WPTR |
41038 | #define SDMA2_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 |
41039 | #define SDMA2_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
41040 | //SDMA2_RLC5_RB_WPTR_HI |
41041 | #define SDMA2_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
41042 | #define SDMA2_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
41043 | //SDMA2_RLC5_RB_WPTR_POLL_CNTL |
41044 | #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
41045 | #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
41046 | #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
41047 | #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
41048 | #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
41049 | #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
41050 | #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
41051 | #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
41052 | #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
41053 | #define SDMA2_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
41054 | //SDMA2_RLC5_RB_RPTR_ADDR_HI |
41055 | #define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
41056 | #define SDMA2_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
41057 | //SDMA2_RLC5_RB_RPTR_ADDR_LO |
41058 | #define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
41059 | #define SDMA2_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
41060 | //SDMA2_RLC5_IB_CNTL |
41061 | #define SDMA2_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
41062 | #define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
41063 | #define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
41064 | #define SDMA2_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 |
41065 | #define SDMA2_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
41066 | #define SDMA2_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
41067 | #define SDMA2_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
41068 | #define SDMA2_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
41069 | //SDMA2_RLC5_IB_RPTR |
41070 | #define SDMA2_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 |
41071 | #define SDMA2_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
41072 | //SDMA2_RLC5_IB_OFFSET |
41073 | #define SDMA2_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 |
41074 | #define SDMA2_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
41075 | //SDMA2_RLC5_IB_BASE_LO |
41076 | #define SDMA2_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 |
41077 | #define SDMA2_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
41078 | //SDMA2_RLC5_IB_BASE_HI |
41079 | #define SDMA2_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 |
41080 | #define SDMA2_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
41081 | //SDMA2_RLC5_IB_SIZE |
41082 | #define SDMA2_RLC5_IB_SIZE__SIZE__SHIFT 0x0 |
41083 | #define SDMA2_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL |
41084 | //SDMA2_RLC5_SKIP_CNTL |
41085 | #define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
41086 | #define SDMA2_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
41087 | //SDMA2_RLC5_CONTEXT_STATUS |
41088 | #define SDMA2_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
41089 | #define SDMA2_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
41090 | #define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
41091 | #define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
41092 | #define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
41093 | #define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
41094 | #define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
41095 | #define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
41096 | #define SDMA2_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
41097 | #define SDMA2_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
41098 | #define SDMA2_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
41099 | #define SDMA2_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
41100 | #define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
41101 | #define SDMA2_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
41102 | #define SDMA2_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
41103 | #define SDMA2_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
41104 | //SDMA2_RLC5_DOORBELL |
41105 | #define SDMA2_RLC5_DOORBELL__ENABLE__SHIFT 0x1c |
41106 | #define SDMA2_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e |
41107 | #define SDMA2_RLC5_DOORBELL__ENABLE_MASK 0x10000000L |
41108 | #define SDMA2_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L |
41109 | //SDMA2_RLC5_STATUS |
41110 | #define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
41111 | #define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
41112 | #define SDMA2_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
41113 | #define SDMA2_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
41114 | //SDMA2_RLC5_DOORBELL_LOG |
41115 | #define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
41116 | #define SDMA2_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 |
41117 | #define SDMA2_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
41118 | #define SDMA2_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
41119 | //SDMA2_RLC5_WATERMARK |
41120 | #define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
41121 | #define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
41122 | #define SDMA2_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
41123 | #define SDMA2_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
41124 | //SDMA2_RLC5_DOORBELL_OFFSET |
41125 | #define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
41126 | #define SDMA2_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
41127 | //SDMA2_RLC5_CSA_ADDR_LO |
41128 | #define SDMA2_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
41129 | #define SDMA2_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
41130 | //SDMA2_RLC5_CSA_ADDR_HI |
41131 | #define SDMA2_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
41132 | #define SDMA2_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
41133 | //SDMA2_RLC5_IB_SUB_REMAIN |
41134 | #define SDMA2_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
41135 | #define SDMA2_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
41136 | //SDMA2_RLC5_PREEMPT |
41137 | #define SDMA2_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
41138 | #define SDMA2_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
41139 | //SDMA2_RLC5_DUMMY_REG |
41140 | #define SDMA2_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 |
41141 | #define SDMA2_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
41142 | //SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI |
41143 | #define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
41144 | #define SDMA2_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
41145 | //SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO |
41146 | #define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
41147 | #define SDMA2_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
41148 | //SDMA2_RLC5_RB_AQL_CNTL |
41149 | #define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
41150 | #define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
41151 | #define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
41152 | #define SDMA2_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
41153 | #define SDMA2_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
41154 | #define SDMA2_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
41155 | #define SDMA2_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
41156 | #define SDMA2_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
41157 | #define SDMA2_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
41158 | #define SDMA2_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
41159 | #define SDMA2_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
41160 | #define SDMA2_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
41161 | //SDMA2_RLC5_MINOR_PTR_UPDATE |
41162 | #define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
41163 | #define SDMA2_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
41164 | //SDMA2_RLC5_MIDCMD_DATA0 |
41165 | #define SDMA2_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
41166 | #define SDMA2_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
41167 | //SDMA2_RLC5_MIDCMD_DATA1 |
41168 | #define SDMA2_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
41169 | #define SDMA2_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
41170 | //SDMA2_RLC5_MIDCMD_DATA2 |
41171 | #define SDMA2_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
41172 | #define SDMA2_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
41173 | //SDMA2_RLC5_MIDCMD_DATA3 |
41174 | #define SDMA2_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
41175 | #define SDMA2_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
41176 | //SDMA2_RLC5_MIDCMD_DATA4 |
41177 | #define SDMA2_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
41178 | #define SDMA2_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
41179 | //SDMA2_RLC5_MIDCMD_DATA5 |
41180 | #define SDMA2_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
41181 | #define SDMA2_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
41182 | //SDMA2_RLC5_MIDCMD_DATA6 |
41183 | #define SDMA2_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
41184 | #define SDMA2_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
41185 | //SDMA2_RLC5_MIDCMD_DATA7 |
41186 | #define SDMA2_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
41187 | #define SDMA2_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
41188 | //SDMA2_RLC5_MIDCMD_DATA8 |
41189 | #define SDMA2_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
41190 | #define SDMA2_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
41191 | //SDMA2_RLC5_MIDCMD_DATA9 |
41192 | #define SDMA2_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
41193 | #define SDMA2_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
41194 | //SDMA2_RLC5_MIDCMD_DATA10 |
41195 | #define SDMA2_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
41196 | #define SDMA2_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
41197 | //SDMA2_RLC5_MIDCMD_CNTL |
41198 | #define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
41199 | #define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
41200 | #define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
41201 | #define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
41202 | #define SDMA2_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
41203 | #define SDMA2_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
41204 | #define SDMA2_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
41205 | #define SDMA2_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
41206 | //SDMA2_RLC6_RB_CNTL |
41207 | #define SDMA2_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
41208 | #define SDMA2_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 |
41209 | #define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
41210 | #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
41211 | #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
41212 | #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
41213 | #define SDMA2_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 |
41214 | #define SDMA2_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 |
41215 | #define SDMA2_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
41216 | #define SDMA2_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
41217 | #define SDMA2_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
41218 | #define SDMA2_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
41219 | #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
41220 | #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
41221 | #define SDMA2_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
41222 | #define SDMA2_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L |
41223 | #define SDMA2_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L |
41224 | #define SDMA2_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
41225 | //SDMA2_RLC6_RB_BASE |
41226 | #define SDMA2_RLC6_RB_BASE__ADDR__SHIFT 0x0 |
41227 | #define SDMA2_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
41228 | //SDMA2_RLC6_RB_BASE_HI |
41229 | #define SDMA2_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 |
41230 | #define SDMA2_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
41231 | //SDMA2_RLC6_RB_RPTR |
41232 | #define SDMA2_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 |
41233 | #define SDMA2_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
41234 | //SDMA2_RLC6_RB_RPTR_HI |
41235 | #define SDMA2_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
41236 | #define SDMA2_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
41237 | //SDMA2_RLC6_RB_WPTR |
41238 | #define SDMA2_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 |
41239 | #define SDMA2_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
41240 | //SDMA2_RLC6_RB_WPTR_HI |
41241 | #define SDMA2_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
41242 | #define SDMA2_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
41243 | //SDMA2_RLC6_RB_WPTR_POLL_CNTL |
41244 | #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
41245 | #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
41246 | #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
41247 | #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
41248 | #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
41249 | #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
41250 | #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
41251 | #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
41252 | #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
41253 | #define SDMA2_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
41254 | //SDMA2_RLC6_RB_RPTR_ADDR_HI |
41255 | #define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
41256 | #define SDMA2_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
41257 | //SDMA2_RLC6_RB_RPTR_ADDR_LO |
41258 | #define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
41259 | #define SDMA2_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
41260 | //SDMA2_RLC6_IB_CNTL |
41261 | #define SDMA2_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
41262 | #define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
41263 | #define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
41264 | #define SDMA2_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 |
41265 | #define SDMA2_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
41266 | #define SDMA2_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
41267 | #define SDMA2_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
41268 | #define SDMA2_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
41269 | //SDMA2_RLC6_IB_RPTR |
41270 | #define SDMA2_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 |
41271 | #define SDMA2_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
41272 | //SDMA2_RLC6_IB_OFFSET |
41273 | #define SDMA2_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 |
41274 | #define SDMA2_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
41275 | //SDMA2_RLC6_IB_BASE_LO |
41276 | #define SDMA2_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 |
41277 | #define SDMA2_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
41278 | //SDMA2_RLC6_IB_BASE_HI |
41279 | #define SDMA2_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 |
41280 | #define SDMA2_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
41281 | //SDMA2_RLC6_IB_SIZE |
41282 | #define SDMA2_RLC6_IB_SIZE__SIZE__SHIFT 0x0 |
41283 | #define SDMA2_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL |
41284 | //SDMA2_RLC6_SKIP_CNTL |
41285 | #define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
41286 | #define SDMA2_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
41287 | //SDMA2_RLC6_CONTEXT_STATUS |
41288 | #define SDMA2_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
41289 | #define SDMA2_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
41290 | #define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
41291 | #define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
41292 | #define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
41293 | #define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
41294 | #define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
41295 | #define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
41296 | #define SDMA2_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
41297 | #define SDMA2_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
41298 | #define SDMA2_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
41299 | #define SDMA2_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
41300 | #define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
41301 | #define SDMA2_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
41302 | #define SDMA2_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
41303 | #define SDMA2_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
41304 | //SDMA2_RLC6_DOORBELL |
41305 | #define SDMA2_RLC6_DOORBELL__ENABLE__SHIFT 0x1c |
41306 | #define SDMA2_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e |
41307 | #define SDMA2_RLC6_DOORBELL__ENABLE_MASK 0x10000000L |
41308 | #define SDMA2_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L |
41309 | //SDMA2_RLC6_STATUS |
41310 | #define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
41311 | #define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
41312 | #define SDMA2_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
41313 | #define SDMA2_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
41314 | //SDMA2_RLC6_DOORBELL_LOG |
41315 | #define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
41316 | #define SDMA2_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 |
41317 | #define SDMA2_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
41318 | #define SDMA2_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
41319 | //SDMA2_RLC6_WATERMARK |
41320 | #define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
41321 | #define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
41322 | #define SDMA2_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
41323 | #define SDMA2_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
41324 | //SDMA2_RLC6_DOORBELL_OFFSET |
41325 | #define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
41326 | #define SDMA2_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
41327 | //SDMA2_RLC6_CSA_ADDR_LO |
41328 | #define SDMA2_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
41329 | #define SDMA2_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
41330 | //SDMA2_RLC6_CSA_ADDR_HI |
41331 | #define SDMA2_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
41332 | #define SDMA2_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
41333 | //SDMA2_RLC6_IB_SUB_REMAIN |
41334 | #define SDMA2_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
41335 | #define SDMA2_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
41336 | //SDMA2_RLC6_PREEMPT |
41337 | #define SDMA2_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
41338 | #define SDMA2_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
41339 | //SDMA2_RLC6_DUMMY_REG |
41340 | #define SDMA2_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 |
41341 | #define SDMA2_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
41342 | //SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI |
41343 | #define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
41344 | #define SDMA2_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
41345 | //SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO |
41346 | #define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
41347 | #define SDMA2_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
41348 | //SDMA2_RLC6_RB_AQL_CNTL |
41349 | #define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
41350 | #define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
41351 | #define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
41352 | #define SDMA2_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
41353 | #define SDMA2_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
41354 | #define SDMA2_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
41355 | #define SDMA2_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
41356 | #define SDMA2_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
41357 | #define SDMA2_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
41358 | #define SDMA2_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
41359 | #define SDMA2_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
41360 | #define SDMA2_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
41361 | //SDMA2_RLC6_MINOR_PTR_UPDATE |
41362 | #define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
41363 | #define SDMA2_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
41364 | //SDMA2_RLC6_MIDCMD_DATA0 |
41365 | #define SDMA2_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
41366 | #define SDMA2_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
41367 | //SDMA2_RLC6_MIDCMD_DATA1 |
41368 | #define SDMA2_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
41369 | #define SDMA2_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
41370 | //SDMA2_RLC6_MIDCMD_DATA2 |
41371 | #define SDMA2_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
41372 | #define SDMA2_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
41373 | //SDMA2_RLC6_MIDCMD_DATA3 |
41374 | #define SDMA2_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
41375 | #define SDMA2_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
41376 | //SDMA2_RLC6_MIDCMD_DATA4 |
41377 | #define SDMA2_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
41378 | #define SDMA2_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
41379 | //SDMA2_RLC6_MIDCMD_DATA5 |
41380 | #define SDMA2_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
41381 | #define SDMA2_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
41382 | //SDMA2_RLC6_MIDCMD_DATA6 |
41383 | #define SDMA2_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
41384 | #define SDMA2_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
41385 | //SDMA2_RLC6_MIDCMD_DATA7 |
41386 | #define SDMA2_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
41387 | #define SDMA2_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
41388 | //SDMA2_RLC6_MIDCMD_DATA8 |
41389 | #define SDMA2_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
41390 | #define SDMA2_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
41391 | //SDMA2_RLC6_MIDCMD_DATA9 |
41392 | #define SDMA2_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
41393 | #define SDMA2_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
41394 | //SDMA2_RLC6_MIDCMD_DATA10 |
41395 | #define SDMA2_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
41396 | #define SDMA2_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
41397 | //SDMA2_RLC6_MIDCMD_CNTL |
41398 | #define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
41399 | #define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
41400 | #define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
41401 | #define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
41402 | #define SDMA2_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
41403 | #define SDMA2_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
41404 | #define SDMA2_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
41405 | #define SDMA2_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
41406 | //SDMA2_RLC7_RB_CNTL |
41407 | #define SDMA2_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
41408 | #define SDMA2_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 |
41409 | #define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
41410 | #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
41411 | #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
41412 | #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
41413 | #define SDMA2_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 |
41414 | #define SDMA2_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 |
41415 | #define SDMA2_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
41416 | #define SDMA2_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
41417 | #define SDMA2_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
41418 | #define SDMA2_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
41419 | #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
41420 | #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
41421 | #define SDMA2_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
41422 | #define SDMA2_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L |
41423 | #define SDMA2_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L |
41424 | #define SDMA2_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
41425 | //SDMA2_RLC7_RB_BASE |
41426 | #define SDMA2_RLC7_RB_BASE__ADDR__SHIFT 0x0 |
41427 | #define SDMA2_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
41428 | //SDMA2_RLC7_RB_BASE_HI |
41429 | #define SDMA2_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 |
41430 | #define SDMA2_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
41431 | //SDMA2_RLC7_RB_RPTR |
41432 | #define SDMA2_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 |
41433 | #define SDMA2_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
41434 | //SDMA2_RLC7_RB_RPTR_HI |
41435 | #define SDMA2_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
41436 | #define SDMA2_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
41437 | //SDMA2_RLC7_RB_WPTR |
41438 | #define SDMA2_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 |
41439 | #define SDMA2_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
41440 | //SDMA2_RLC7_RB_WPTR_HI |
41441 | #define SDMA2_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
41442 | #define SDMA2_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
41443 | //SDMA2_RLC7_RB_WPTR_POLL_CNTL |
41444 | #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
41445 | #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
41446 | #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
41447 | #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
41448 | #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
41449 | #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
41450 | #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
41451 | #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
41452 | #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
41453 | #define SDMA2_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
41454 | //SDMA2_RLC7_RB_RPTR_ADDR_HI |
41455 | #define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
41456 | #define SDMA2_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
41457 | //SDMA2_RLC7_RB_RPTR_ADDR_LO |
41458 | #define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
41459 | #define SDMA2_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
41460 | //SDMA2_RLC7_IB_CNTL |
41461 | #define SDMA2_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
41462 | #define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
41463 | #define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
41464 | #define SDMA2_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 |
41465 | #define SDMA2_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
41466 | #define SDMA2_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
41467 | #define SDMA2_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
41468 | #define SDMA2_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
41469 | //SDMA2_RLC7_IB_RPTR |
41470 | #define SDMA2_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 |
41471 | #define SDMA2_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
41472 | //SDMA2_RLC7_IB_OFFSET |
41473 | #define SDMA2_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 |
41474 | #define SDMA2_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
41475 | //SDMA2_RLC7_IB_BASE_LO |
41476 | #define SDMA2_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 |
41477 | #define SDMA2_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
41478 | //SDMA2_RLC7_IB_BASE_HI |
41479 | #define SDMA2_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 |
41480 | #define SDMA2_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
41481 | //SDMA2_RLC7_IB_SIZE |
41482 | #define SDMA2_RLC7_IB_SIZE__SIZE__SHIFT 0x0 |
41483 | #define SDMA2_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL |
41484 | //SDMA2_RLC7_SKIP_CNTL |
41485 | #define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
41486 | #define SDMA2_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
41487 | //SDMA2_RLC7_CONTEXT_STATUS |
41488 | #define SDMA2_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
41489 | #define SDMA2_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
41490 | #define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
41491 | #define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
41492 | #define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
41493 | #define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
41494 | #define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
41495 | #define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
41496 | #define SDMA2_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
41497 | #define SDMA2_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
41498 | #define SDMA2_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
41499 | #define SDMA2_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
41500 | #define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
41501 | #define SDMA2_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
41502 | #define SDMA2_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
41503 | #define SDMA2_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
41504 | //SDMA2_RLC7_DOORBELL |
41505 | #define SDMA2_RLC7_DOORBELL__ENABLE__SHIFT 0x1c |
41506 | #define SDMA2_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e |
41507 | #define SDMA2_RLC7_DOORBELL__ENABLE_MASK 0x10000000L |
41508 | #define SDMA2_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L |
41509 | //SDMA2_RLC7_STATUS |
41510 | #define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
41511 | #define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
41512 | #define SDMA2_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
41513 | #define SDMA2_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
41514 | //SDMA2_RLC7_DOORBELL_LOG |
41515 | #define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
41516 | #define SDMA2_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 |
41517 | #define SDMA2_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
41518 | #define SDMA2_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
41519 | //SDMA2_RLC7_WATERMARK |
41520 | #define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
41521 | #define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
41522 | #define SDMA2_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
41523 | #define SDMA2_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
41524 | //SDMA2_RLC7_DOORBELL_OFFSET |
41525 | #define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
41526 | #define SDMA2_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
41527 | //SDMA2_RLC7_CSA_ADDR_LO |
41528 | #define SDMA2_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
41529 | #define SDMA2_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
41530 | //SDMA2_RLC7_CSA_ADDR_HI |
41531 | #define SDMA2_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
41532 | #define SDMA2_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
41533 | //SDMA2_RLC7_IB_SUB_REMAIN |
41534 | #define SDMA2_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
41535 | #define SDMA2_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
41536 | //SDMA2_RLC7_PREEMPT |
41537 | #define SDMA2_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
41538 | #define SDMA2_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
41539 | //SDMA2_RLC7_DUMMY_REG |
41540 | #define SDMA2_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 |
41541 | #define SDMA2_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
41542 | //SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI |
41543 | #define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
41544 | #define SDMA2_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
41545 | //SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO |
41546 | #define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
41547 | #define SDMA2_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
41548 | //SDMA2_RLC7_RB_AQL_CNTL |
41549 | #define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
41550 | #define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
41551 | #define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
41552 | #define SDMA2_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
41553 | #define SDMA2_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
41554 | #define SDMA2_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
41555 | #define SDMA2_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
41556 | #define SDMA2_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
41557 | #define SDMA2_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
41558 | #define SDMA2_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
41559 | #define SDMA2_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
41560 | #define SDMA2_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
41561 | //SDMA2_RLC7_MINOR_PTR_UPDATE |
41562 | #define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
41563 | #define SDMA2_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
41564 | //SDMA2_RLC7_MIDCMD_DATA0 |
41565 | #define SDMA2_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
41566 | #define SDMA2_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
41567 | //SDMA2_RLC7_MIDCMD_DATA1 |
41568 | #define SDMA2_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
41569 | #define SDMA2_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
41570 | //SDMA2_RLC7_MIDCMD_DATA2 |
41571 | #define SDMA2_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
41572 | #define SDMA2_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
41573 | //SDMA2_RLC7_MIDCMD_DATA3 |
41574 | #define SDMA2_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
41575 | #define SDMA2_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
41576 | //SDMA2_RLC7_MIDCMD_DATA4 |
41577 | #define SDMA2_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
41578 | #define SDMA2_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
41579 | //SDMA2_RLC7_MIDCMD_DATA5 |
41580 | #define SDMA2_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
41581 | #define SDMA2_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
41582 | //SDMA2_RLC7_MIDCMD_DATA6 |
41583 | #define SDMA2_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
41584 | #define SDMA2_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
41585 | //SDMA2_RLC7_MIDCMD_DATA7 |
41586 | #define SDMA2_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
41587 | #define SDMA2_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
41588 | //SDMA2_RLC7_MIDCMD_DATA8 |
41589 | #define SDMA2_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
41590 | #define SDMA2_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
41591 | //SDMA2_RLC7_MIDCMD_DATA9 |
41592 | #define SDMA2_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
41593 | #define SDMA2_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
41594 | //SDMA2_RLC7_MIDCMD_DATA10 |
41595 | #define SDMA2_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
41596 | #define SDMA2_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
41597 | //SDMA2_RLC7_MIDCMD_CNTL |
41598 | #define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
41599 | #define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
41600 | #define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
41601 | #define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
41602 | #define SDMA2_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
41603 | #define SDMA2_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
41604 | #define SDMA2_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
41605 | #define SDMA2_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
41606 | |
41607 | |
41608 | // addressBlock: gc_sdma3_sdma3dec |
41609 | //SDMA3_DEC_START |
41610 | #define SDMA3_DEC_START__START__SHIFT 0x0 |
41611 | #define SDMA3_DEC_START__START_MASK 0xFFFFFFFFL |
41612 | //SDMA3_GLOBAL_TIMESTAMP_LO |
41613 | #define SDMA3_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 |
41614 | #define SDMA3_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL |
41615 | //SDMA3_GLOBAL_TIMESTAMP_HI |
41616 | #define SDMA3_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 |
41617 | #define SDMA3_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL |
41618 | //SDMA3_PG_CNTL |
41619 | #define SDMA3_PG_CNTL__CMD__SHIFT 0x0 |
41620 | #define SDMA3_PG_CNTL__STATUS__SHIFT 0x10 |
41621 | #define SDMA3_PG_CNTL__CMD_MASK 0x0000000FL |
41622 | #define SDMA3_PG_CNTL__STATUS_MASK 0x000F0000L |
41623 | //SDMA3_PG_CTX_LO |
41624 | #define SDMA3_PG_CTX_LO__ADDR__SHIFT 0x0 |
41625 | #define SDMA3_PG_CTX_LO__ADDR_MASK 0xFFFFFFFFL |
41626 | //SDMA3_PG_CTX_HI |
41627 | #define SDMA3_PG_CTX_HI__ADDR__SHIFT 0x0 |
41628 | #define SDMA3_PG_CTX_HI__ADDR_MASK 0xFFFFFFFFL |
41629 | //SDMA3_PG_CTX_CNTL |
41630 | #define SDMA3_PG_CTX_CNTL__VMID__SHIFT 0x4 |
41631 | #define SDMA3_PG_CTX_CNTL__VMID_MASK 0x000000F0L |
41632 | //SDMA3_POWER_CNTL |
41633 | #define SDMA3_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 |
41634 | #define SDMA3_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 |
41635 | #define SDMA3_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 |
41636 | #define SDMA3_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 |
41637 | #define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 |
41638 | #define SDMA3_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a |
41639 | #define SDMA3_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L |
41640 | #define SDMA3_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L |
41641 | #define SDMA3_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L |
41642 | #define SDMA3_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L |
41643 | #define SDMA3_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L |
41644 | #define SDMA3_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L |
41645 | //SDMA3_CLK_CTRL |
41646 | #define SDMA3_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
41647 | #define SDMA3_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
41648 | #define SDMA3_CLK_CTRL__RESERVED_24_12__SHIFT 0xc |
41649 | #define SDMA3_CLK_CTRL__CGCG_EN_OVERRIDE__SHIFT 0x19 |
41650 | #define SDMA3_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1a |
41651 | #define SDMA3_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1b |
41652 | #define SDMA3_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1c |
41653 | #define SDMA3_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1d |
41654 | #define SDMA3_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1e |
41655 | #define SDMA3_CLK_CTRL__SOFT_OVERRIDER_REG__SHIFT 0x1f |
41656 | #define SDMA3_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
41657 | #define SDMA3_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
41658 | #define SDMA3_CLK_CTRL__RESERVED_24_12_MASK 0x01FFF000L |
41659 | #define SDMA3_CLK_CTRL__CGCG_EN_OVERRIDE_MASK 0x02000000L |
41660 | #define SDMA3_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x04000000L |
41661 | #define SDMA3_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x08000000L |
41662 | #define SDMA3_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x10000000L |
41663 | #define SDMA3_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x20000000L |
41664 | #define SDMA3_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x40000000L |
41665 | #define SDMA3_CLK_CTRL__SOFT_OVERRIDER_REG_MASK 0x80000000L |
41666 | //SDMA3_CNTL |
41667 | #define SDMA3_CNTL__TRAP_ENABLE__SHIFT 0x0 |
41668 | #define SDMA3_CNTL__UTC_L1_ENABLE__SHIFT 0x1 |
41669 | #define SDMA3_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 |
41670 | #define SDMA3_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 |
41671 | #define SDMA3_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 |
41672 | #define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 |
41673 | #define SDMA3_CNTL__PAGE_INT_ENABLE__SHIFT 0x7 |
41674 | #define SDMA3_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10 |
41675 | #define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 |
41676 | #define SDMA3_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 |
41677 | #define SDMA3_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c |
41678 | #define SDMA3_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d |
41679 | #define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e |
41680 | #define SDMA3_CNTL__TRAP_ENABLE_MASK 0x00000001L |
41681 | #define SDMA3_CNTL__UTC_L1_ENABLE_MASK 0x00000002L |
41682 | #define SDMA3_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L |
41683 | #define SDMA3_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L |
41684 | #define SDMA3_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L |
41685 | #define SDMA3_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L |
41686 | #define SDMA3_CNTL__PAGE_INT_ENABLE_MASK 0x00000080L |
41687 | #define SDMA3_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L |
41688 | #define SDMA3_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L |
41689 | #define SDMA3_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L |
41690 | #define SDMA3_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L |
41691 | #define SDMA3_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L |
41692 | #define SDMA3_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L |
41693 | //SDMA3_CHICKEN_BITS |
41694 | #define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 |
41695 | #define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 |
41696 | #define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 |
41697 | #define SDMA3_CHICKEN_BITS__SOFT_OVERRIDE_DCGE__SHIFT 0x4 |
41698 | #define SDMA3_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG__SHIFT 0x5 |
41699 | #define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 |
41700 | #define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa |
41701 | #define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 |
41702 | #define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 |
41703 | #define SDMA3_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 |
41704 | #define SDMA3_CHICKEN_BITS__GCR_FGCG_ENABLE__SHIFT 0x13 |
41705 | #define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 |
41706 | #define SDMA3_CHICKEN_BITS__CH_FGCG_ENABLE__SHIFT 0x15 |
41707 | #define SDMA3_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE__SHIFT 0x16 |
41708 | #define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 |
41709 | #define SDMA3_CHICKEN_BITS__UTCL1_FGCG_ENABLE__SHIFT 0x18 |
41710 | #define SDMA3_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 |
41711 | #define SDMA3_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a |
41712 | #define SDMA3_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c |
41713 | #define SDMA3_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e |
41714 | #define SDMA3_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L |
41715 | #define SDMA3_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L |
41716 | #define SDMA3_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L |
41717 | #define SDMA3_CHICKEN_BITS__SOFT_OVERRIDE_DCGE_MASK 0x00000010L |
41718 | #define SDMA3_CHICKEN_BITS__SOFT_OVERRIDE_SDMA_GRBM_FGCG_MASK 0x00000020L |
41719 | #define SDMA3_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L |
41720 | #define SDMA3_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L |
41721 | #define SDMA3_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L |
41722 | #define SDMA3_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L |
41723 | #define SDMA3_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L |
41724 | #define SDMA3_CHICKEN_BITS__GCR_FGCG_ENABLE_MASK 0x00080000L |
41725 | #define SDMA3_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L |
41726 | #define SDMA3_CHICKEN_BITS__CH_FGCG_ENABLE_MASK 0x00200000L |
41727 | #define SDMA3_CHICKEN_BITS__UTCL2_INVREQ_FGCG_ENABLE_MASK 0x00400000L |
41728 | #define SDMA3_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L |
41729 | #define SDMA3_CHICKEN_BITS__UTCL1_FGCG_ENABLE_MASK 0x01000000L |
41730 | #define SDMA3_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L |
41731 | #define SDMA3_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L |
41732 | #define SDMA3_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L |
41733 | #define SDMA3_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L |
41734 | //SDMA3_GB_ADDR_CONFIG |
41735 | #define SDMA3_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
41736 | #define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
41737 | #define SDMA3_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
41738 | #define SDMA3_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 |
41739 | #define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
41740 | #define SDMA3_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a |
41741 | #define SDMA3_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
41742 | #define SDMA3_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
41743 | #define SDMA3_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
41744 | #define SDMA3_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L |
41745 | #define SDMA3_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
41746 | #define SDMA3_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L |
41747 | //SDMA3_GB_ADDR_CONFIG_READ |
41748 | #define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 |
41749 | #define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
41750 | #define SDMA3_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
41751 | #define SDMA3_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 |
41752 | #define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 |
41753 | #define SDMA3_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a |
41754 | #define SDMA3_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L |
41755 | #define SDMA3_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
41756 | #define SDMA3_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
41757 | #define SDMA3_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L |
41758 | #define SDMA3_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L |
41759 | #define SDMA3_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L |
41760 | //SDMA3_RB_RPTR_FETCH_HI |
41761 | #define SDMA3_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 |
41762 | #define SDMA3_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL |
41763 | //SDMA3_SEM_WAIT_FAIL_TIMER_CNTL |
41764 | #define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 |
41765 | #define SDMA3_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL |
41766 | //SDMA3_RB_RPTR_FETCH |
41767 | #define SDMA3_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 |
41768 | #define SDMA3_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL |
41769 | //SDMA3_IB_OFFSET_FETCH |
41770 | #define SDMA3_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 |
41771 | #define SDMA3_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL |
41772 | //SDMA3_PROGRAM |
41773 | #define SDMA3_PROGRAM__STREAM__SHIFT 0x0 |
41774 | #define SDMA3_PROGRAM__STREAM_MASK 0xFFFFFFFFL |
41775 | //SDMA3_STATUS_REG |
41776 | #define SDMA3_STATUS_REG__IDLE__SHIFT 0x0 |
41777 | #define SDMA3_STATUS_REG__REG_IDLE__SHIFT 0x1 |
41778 | #define SDMA3_STATUS_REG__RB_EMPTY__SHIFT 0x2 |
41779 | #define SDMA3_STATUS_REG__RB_FULL__SHIFT 0x3 |
41780 | #define SDMA3_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 |
41781 | #define SDMA3_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 |
41782 | #define SDMA3_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 |
41783 | #define SDMA3_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 |
41784 | #define SDMA3_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 |
41785 | #define SDMA3_STATUS_REG__INSIDE_IB__SHIFT 0x9 |
41786 | #define SDMA3_STATUS_REG__EX_IDLE__SHIFT 0xa |
41787 | #define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb |
41788 | #define SDMA3_STATUS_REG__PACKET_READY__SHIFT 0xc |
41789 | #define SDMA3_STATUS_REG__MC_WR_IDLE__SHIFT 0xd |
41790 | #define SDMA3_STATUS_REG__SRBM_IDLE__SHIFT 0xe |
41791 | #define SDMA3_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf |
41792 | #define SDMA3_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 |
41793 | #define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 |
41794 | #define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 |
41795 | #define SDMA3_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 |
41796 | #define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 |
41797 | #define SDMA3_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 |
41798 | #define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 |
41799 | #define SDMA3_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 |
41800 | #define SDMA3_STATUS_REG__SEM_IDLE__SHIFT 0x1a |
41801 | #define SDMA3_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b |
41802 | #define SDMA3_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c |
41803 | #define SDMA3_STATUS_REG__INT_IDLE__SHIFT 0x1e |
41804 | #define SDMA3_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f |
41805 | #define SDMA3_STATUS_REG__IDLE_MASK 0x00000001L |
41806 | #define SDMA3_STATUS_REG__REG_IDLE_MASK 0x00000002L |
41807 | #define SDMA3_STATUS_REG__RB_EMPTY_MASK 0x00000004L |
41808 | #define SDMA3_STATUS_REG__RB_FULL_MASK 0x00000008L |
41809 | #define SDMA3_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L |
41810 | #define SDMA3_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L |
41811 | #define SDMA3_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L |
41812 | #define SDMA3_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L |
41813 | #define SDMA3_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L |
41814 | #define SDMA3_STATUS_REG__INSIDE_IB_MASK 0x00000200L |
41815 | #define SDMA3_STATUS_REG__EX_IDLE_MASK 0x00000400L |
41816 | #define SDMA3_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L |
41817 | #define SDMA3_STATUS_REG__PACKET_READY_MASK 0x00001000L |
41818 | #define SDMA3_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L |
41819 | #define SDMA3_STATUS_REG__SRBM_IDLE_MASK 0x00004000L |
41820 | #define SDMA3_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L |
41821 | #define SDMA3_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L |
41822 | #define SDMA3_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L |
41823 | #define SDMA3_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L |
41824 | #define SDMA3_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L |
41825 | #define SDMA3_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L |
41826 | #define SDMA3_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L |
41827 | #define SDMA3_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L |
41828 | #define SDMA3_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L |
41829 | #define SDMA3_STATUS_REG__SEM_IDLE_MASK 0x04000000L |
41830 | #define SDMA3_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L |
41831 | #define SDMA3_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L |
41832 | #define SDMA3_STATUS_REG__INT_IDLE_MASK 0x40000000L |
41833 | #define SDMA3_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L |
41834 | //SDMA3_STATUS1_REG |
41835 | #define SDMA3_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 |
41836 | #define SDMA3_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 |
41837 | #define SDMA3_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 |
41838 | #define SDMA3_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 |
41839 | #define SDMA3_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 |
41840 | #define SDMA3_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 |
41841 | #define SDMA3_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 |
41842 | #define SDMA3_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 |
41843 | #define SDMA3_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa |
41844 | #define SDMA3_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd |
41845 | #define SDMA3_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe |
41846 | #define SDMA3_STATUS1_REG__EX_START__SHIFT 0xf |
41847 | #define SDMA3_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 |
41848 | #define SDMA3_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 |
41849 | #define SDMA3_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L |
41850 | #define SDMA3_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L |
41851 | #define SDMA3_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L |
41852 | #define SDMA3_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L |
41853 | #define SDMA3_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L |
41854 | #define SDMA3_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L |
41855 | #define SDMA3_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L |
41856 | #define SDMA3_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L |
41857 | #define SDMA3_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L |
41858 | #define SDMA3_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L |
41859 | #define SDMA3_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L |
41860 | #define SDMA3_STATUS1_REG__EX_START_MASK 0x00008000L |
41861 | #define SDMA3_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L |
41862 | #define SDMA3_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L |
41863 | //SDMA3_RD_BURST_CNTL |
41864 | #define SDMA3_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 |
41865 | #define SDMA3_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L |
41866 | //SDMA3_HBM_PAGE_CONFIG |
41867 | #define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 |
41868 | #define SDMA3_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L |
41869 | //SDMA3_UCODE_CHECKSUM |
41870 | #define SDMA3_UCODE_CHECKSUM__DATA__SHIFT 0x0 |
41871 | #define SDMA3_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL |
41872 | //SDMA3_F32_CNTL |
41873 | #define SDMA3_F32_CNTL__HALT__SHIFT 0x0 |
41874 | #define SDMA3_F32_CNTL__STEP__SHIFT 0x1 |
41875 | #define SDMA3_F32_CNTL__CHECKSUM_CLR__SHIFT 0x8 |
41876 | #define SDMA3_F32_CNTL__RESET__SHIFT 0x9 |
41877 | #define SDMA3_F32_CNTL__HALT_MASK 0x00000001L |
41878 | #define SDMA3_F32_CNTL__STEP_MASK 0x00000002L |
41879 | #define SDMA3_F32_CNTL__CHECKSUM_CLR_MASK 0x00000100L |
41880 | #define SDMA3_F32_CNTL__RESET_MASK 0x00000200L |
41881 | //SDMA3_FREEZE |
41882 | #define SDMA3_FREEZE__PREEMPT__SHIFT 0x0 |
41883 | #define SDMA3_FREEZE__FORCE_PREEMPT__SHIFT 0x1 |
41884 | #define SDMA3_FREEZE__FREEZE__SHIFT 0x4 |
41885 | #define SDMA3_FREEZE__FROZEN__SHIFT 0x5 |
41886 | #define SDMA3_FREEZE__F32_FREEZE__SHIFT 0x6 |
41887 | #define SDMA3_FREEZE__PREEMPT_MASK 0x00000001L |
41888 | #define SDMA3_FREEZE__FORCE_PREEMPT_MASK 0x00000002L |
41889 | #define SDMA3_FREEZE__FREEZE_MASK 0x00000010L |
41890 | #define SDMA3_FREEZE__FROZEN_MASK 0x00000020L |
41891 | #define SDMA3_FREEZE__F32_FREEZE_MASK 0x00000040L |
41892 | //SDMA3_PHASE0_QUANTUM |
41893 | #define SDMA3_PHASE0_QUANTUM__UNIT__SHIFT 0x0 |
41894 | #define SDMA3_PHASE0_QUANTUM__VALUE__SHIFT 0x8 |
41895 | #define SDMA3_PHASE0_QUANTUM__PREFER__SHIFT 0x1e |
41896 | #define SDMA3_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL |
41897 | #define SDMA3_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L |
41898 | #define SDMA3_PHASE0_QUANTUM__PREFER_MASK 0x40000000L |
41899 | //SDMA3_PHASE1_QUANTUM |
41900 | #define SDMA3_PHASE1_QUANTUM__UNIT__SHIFT 0x0 |
41901 | #define SDMA3_PHASE1_QUANTUM__VALUE__SHIFT 0x8 |
41902 | #define SDMA3_PHASE1_QUANTUM__PREFER__SHIFT 0x1e |
41903 | #define SDMA3_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL |
41904 | #define SDMA3_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L |
41905 | #define SDMA3_PHASE1_QUANTUM__PREFER_MASK 0x40000000L |
41906 | //SDMA3_EDC_CONFIG |
41907 | #define SDMA3_EDC_CONFIG__DIS_EDC__SHIFT 0x1 |
41908 | #define SDMA3_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 |
41909 | #define SDMA3_EDC_CONFIG__DIS_EDC_MASK 0x00000002L |
41910 | #define SDMA3_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L |
41911 | //SDMA3_BA_THRESHOLD |
41912 | #define SDMA3_BA_THRESHOLD__READ_THRES__SHIFT 0x0 |
41913 | #define SDMA3_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 |
41914 | #define SDMA3_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL |
41915 | #define SDMA3_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L |
41916 | //SDMA3_ID |
41917 | #define SDMA3_ID__DEVICE_ID__SHIFT 0x0 |
41918 | #define SDMA3_ID__DEVICE_ID_MASK 0x000000FFL |
41919 | //SDMA3_VERSION |
41920 | #define SDMA3_VERSION__MINVER__SHIFT 0x0 |
41921 | #define SDMA3_VERSION__MAJVER__SHIFT 0x8 |
41922 | #define SDMA3_VERSION__REV__SHIFT 0x10 |
41923 | #define SDMA3_VERSION__MINVER_MASK 0x0000007FL |
41924 | #define SDMA3_VERSION__MAJVER_MASK 0x00007F00L |
41925 | #define SDMA3_VERSION__REV_MASK 0x003F0000L |
41926 | //SDMA3_EDC_COUNTER |
41927 | #define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 |
41928 | #define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 |
41929 | #define SDMA3_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 |
41930 | #define SDMA3_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 |
41931 | #define SDMA3_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 |
41932 | #define SDMA3_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 |
41933 | #define SDMA3_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 |
41934 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 |
41935 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 |
41936 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 |
41937 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa |
41938 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb |
41939 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc |
41940 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd |
41941 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe |
41942 | #define SDMA3_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf |
41943 | #define SDMA3_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 |
41944 | #define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L |
41945 | #define SDMA3_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L |
41946 | #define SDMA3_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L |
41947 | #define SDMA3_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L |
41948 | #define SDMA3_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L |
41949 | #define SDMA3_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L |
41950 | #define SDMA3_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L |
41951 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L |
41952 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L |
41953 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L |
41954 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L |
41955 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L |
41956 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L |
41957 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L |
41958 | #define SDMA3_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L |
41959 | #define SDMA3_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L |
41960 | #define SDMA3_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L |
41961 | //SDMA3_EDC_COUNTER_CLEAR |
41962 | #define SDMA3_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 |
41963 | #define SDMA3_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L |
41964 | //SDMA3_STATUS2_REG |
41965 | #define SDMA3_STATUS2_REG__ID__SHIFT 0x0 |
41966 | #define SDMA3_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 |
41967 | #define SDMA3_STATUS2_REG__CMD_OP__SHIFT 0x10 |
41968 | #define SDMA3_STATUS2_REG__ID_MASK 0x00000003L |
41969 | #define SDMA3_STATUS2_REG__F32_INSTR_PTR_MASK 0x0000FFFCL |
41970 | #define SDMA3_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L |
41971 | //SDMA3_ATOMIC_CNTL |
41972 | #define SDMA3_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 |
41973 | #define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f |
41974 | #define SDMA3_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL |
41975 | #define SDMA3_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L |
41976 | //SDMA3_ATOMIC_PREOP_LO |
41977 | #define SDMA3_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 |
41978 | #define SDMA3_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL |
41979 | //SDMA3_ATOMIC_PREOP_HI |
41980 | #define SDMA3_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 |
41981 | #define SDMA3_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL |
41982 | //SDMA3_UTCL1_CNTL |
41983 | #define SDMA3_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 |
41984 | #define SDMA3_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 |
41985 | #define SDMA3_UTCL1_CNTL__REDO_WATERMK__SHIFT 0x6 |
41986 | #define SDMA3_UTCL1_CNTL__RESP_MODE__SHIFT 0x9 |
41987 | #define SDMA3_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe |
41988 | #define SDMA3_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xf |
41989 | #define SDMA3_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x10 |
41990 | #define SDMA3_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 |
41991 | #define SDMA3_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d |
41992 | #define SDMA3_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L |
41993 | #define SDMA3_UTCL1_CNTL__REDO_DELAY_MASK 0x0000003EL |
41994 | #define SDMA3_UTCL1_CNTL__REDO_WATERMK_MASK 0x000001C0L |
41995 | #define SDMA3_UTCL1_CNTL__RESP_MODE_MASK 0x00000E00L |
41996 | #define SDMA3_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00004000L |
41997 | #define SDMA3_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00008000L |
41998 | #define SDMA3_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FF0000L |
41999 | #define SDMA3_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L |
42000 | #define SDMA3_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L |
42001 | //SDMA3_UTCL1_WATERMK |
42002 | #define SDMA3_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 |
42003 | #define SDMA3_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa |
42004 | #define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 |
42005 | #define SDMA3_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a |
42006 | #define SDMA3_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL |
42007 | #define SDMA3_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L |
42008 | #define SDMA3_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L |
42009 | #define SDMA3_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L |
42010 | //SDMA3_UTCL1_RD_STATUS |
42011 | #define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 |
42012 | #define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1 |
42013 | #define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2 |
42014 | #define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3 |
42015 | #define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4 |
42016 | #define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5 |
42017 | #define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6 |
42018 | #define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7 |
42019 | #define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8 |
42020 | #define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9 |
42021 | #define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa |
42022 | #define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb |
42023 | #define SDMA3_UTCL1_RD_STATUS__REDO_ARR_EMPTY__SHIFT 0xc |
42024 | #define SDMA3_UTCL1_RD_STATUS__REDO_ARR_FULL__SHIFT 0xd |
42025 | #define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0xe |
42026 | #define SDMA3_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0xf |
42027 | #define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x10 |
42028 | #define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x11 |
42029 | #define SDMA3_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x15 |
42030 | #define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x18 |
42031 | #define SDMA3_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT__SHIFT 0x19 |
42032 | #define SDMA3_UTCL1_RD_STATUS__PAGE_NULL_SW__SHIFT 0x1a |
42033 | #define SDMA3_UTCL1_RD_STATUS__HIT_CACHE__SHIFT 0x1b |
42034 | #define SDMA3_UTCL1_RD_STATUS__RD_DCC_ENABLE__SHIFT 0x1c |
42035 | #define SDMA3_UTCL1_RD_STATUS__NACK_TIMEOUT_SW__SHIFT 0x1d |
42036 | #define SDMA3_UTCL1_RD_STATUS__DCC_PAGE_FAULT__SHIFT 0x1e |
42037 | #define SDMA3_UTCL1_RD_STATUS__DCC_PAGE_NULL__SHIFT 0x1f |
42038 | #define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L |
42039 | #define SDMA3_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L |
42040 | #define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L |
42041 | #define SDMA3_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L |
42042 | #define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L |
42043 | #define SDMA3_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L |
42044 | #define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L |
42045 | #define SDMA3_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L |
42046 | #define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L |
42047 | #define SDMA3_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L |
42048 | #define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L |
42049 | #define SDMA3_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L |
42050 | #define SDMA3_UTCL1_RD_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L |
42051 | #define SDMA3_UTCL1_RD_STATUS__REDO_ARR_FULL_MASK 0x00002000L |
42052 | #define SDMA3_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00004000L |
42053 | #define SDMA3_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00008000L |
42054 | #define SDMA3_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00010000L |
42055 | #define SDMA3_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x001E0000L |
42056 | #define SDMA3_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x00E00000L |
42057 | #define SDMA3_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x01000000L |
42058 | #define SDMA3_UTCL1_RD_STATUS__RD_XNACK_TIMEOUT_MASK 0x02000000L |
42059 | #define SDMA3_UTCL1_RD_STATUS__PAGE_NULL_SW_MASK 0x04000000L |
42060 | #define SDMA3_UTCL1_RD_STATUS__HIT_CACHE_MASK 0x08000000L |
42061 | #define SDMA3_UTCL1_RD_STATUS__RD_DCC_ENABLE_MASK 0x10000000L |
42062 | #define SDMA3_UTCL1_RD_STATUS__NACK_TIMEOUT_SW_MASK 0x20000000L |
42063 | #define SDMA3_UTCL1_RD_STATUS__DCC_PAGE_FAULT_MASK 0x40000000L |
42064 | #define SDMA3_UTCL1_RD_STATUS__DCC_PAGE_NULL_MASK 0x80000000L |
42065 | //SDMA3_UTCL1_WR_STATUS |
42066 | #define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 |
42067 | #define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x1 |
42068 | #define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x2 |
42069 | #define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0x3 |
42070 | #define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x4 |
42071 | #define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0x5 |
42072 | #define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x6 |
42073 | #define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0x7 |
42074 | #define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x8 |
42075 | #define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0x9 |
42076 | #define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0xa |
42077 | #define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xb |
42078 | #define SDMA3_UTCL1_WR_STATUS__REDO_ARR_EMPTY__SHIFT 0xc |
42079 | #define SDMA3_UTCL1_WR_STATUS__REDO_ARR_FULL__SHIFT 0xd |
42080 | #define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0xe |
42081 | #define SDMA3_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0xf |
42082 | #define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x10 |
42083 | #define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x11 |
42084 | #define SDMA3_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x15 |
42085 | #define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x18 |
42086 | #define SDMA3_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT__SHIFT 0x19 |
42087 | #define SDMA3_UTCL1_WR_STATUS__PAGE_NULL_SW__SHIFT 0x1a |
42088 | #define SDMA3_UTCL1_WR_STATUS__ATOMIC_OP__SHIFT 0x1b |
42089 | #define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c |
42090 | #define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d |
42091 | #define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e |
42092 | #define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f |
42093 | #define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L |
42094 | #define SDMA3_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000002L |
42095 | #define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000004L |
42096 | #define SDMA3_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000008L |
42097 | #define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000010L |
42098 | #define SDMA3_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000020L |
42099 | #define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000040L |
42100 | #define SDMA3_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00000080L |
42101 | #define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000100L |
42102 | #define SDMA3_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00000200L |
42103 | #define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000400L |
42104 | #define SDMA3_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00000800L |
42105 | #define SDMA3_UTCL1_WR_STATUS__REDO_ARR_EMPTY_MASK 0x00001000L |
42106 | #define SDMA3_UTCL1_WR_STATUS__REDO_ARR_FULL_MASK 0x00002000L |
42107 | #define SDMA3_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00004000L |
42108 | #define SDMA3_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00008000L |
42109 | #define SDMA3_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00010000L |
42110 | #define SDMA3_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x001E0000L |
42111 | #define SDMA3_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x00E00000L |
42112 | #define SDMA3_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x01000000L |
42113 | #define SDMA3_UTCL1_WR_STATUS__WR_XNACK_TIMEOUT_MASK 0x02000000L |
42114 | #define SDMA3_UTCL1_WR_STATUS__PAGE_NULL_SW_MASK 0x04000000L |
42115 | #define SDMA3_UTCL1_WR_STATUS__ATOMIC_OP_MASK 0x08000000L |
42116 | #define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L |
42117 | #define SDMA3_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L |
42118 | #define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L |
42119 | #define SDMA3_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L |
42120 | //SDMA3_UTCL1_INV0 |
42121 | #define SDMA3_UTCL1_INV0__CPF_INVREQ_EN__SHIFT 0x0 |
42122 | #define SDMA3_UTCL1_INV0__GPUVM_INVREQ_EN__SHIFT 0x1 |
42123 | #define SDMA3_UTCL1_INV0__CPF_GPA_INVREQ__SHIFT 0x2 |
42124 | #define SDMA3_UTCL1_INV0__GPUVM_INVREQ_LOW__SHIFT 0x3 |
42125 | #define SDMA3_UTCL1_INV0__GPUVM_INVREQ_HIGH__SHIFT 0x4 |
42126 | #define SDMA3_UTCL1_INV0__INVREQ_SIZE__SHIFT 0x5 |
42127 | #define SDMA3_UTCL1_INV0__INVREQ_IDLE__SHIFT 0xb |
42128 | #define SDMA3_UTCL1_INV0__VMINV_PEND_CNT__SHIFT 0xc |
42129 | #define SDMA3_UTCL1_INV0__GPUVM_LO_INV_VMID__SHIFT 0x10 |
42130 | #define SDMA3_UTCL1_INV0__GPUVM_HI_INV_VMID__SHIFT 0x14 |
42131 | #define SDMA3_UTCL1_INV0__GPUVM_INV_MODE__SHIFT 0x18 |
42132 | #define SDMA3_UTCL1_INV0__INVREQ_IS_HEAVY__SHIFT 0x1a |
42133 | #define SDMA3_UTCL1_INV0__INVREQ_FROM_CPF__SHIFT 0x1b |
42134 | #define SDMA3_UTCL1_INV0__GPUVM_INVREQ_TAG__SHIFT 0x1c |
42135 | #define SDMA3_UTCL1_INV0__CPF_INVREQ_EN_MASK 0x00000001L |
42136 | #define SDMA3_UTCL1_INV0__GPUVM_INVREQ_EN_MASK 0x00000002L |
42137 | #define SDMA3_UTCL1_INV0__CPF_GPA_INVREQ_MASK 0x00000004L |
42138 | #define SDMA3_UTCL1_INV0__GPUVM_INVREQ_LOW_MASK 0x00000008L |
42139 | #define SDMA3_UTCL1_INV0__GPUVM_INVREQ_HIGH_MASK 0x00000010L |
42140 | #define SDMA3_UTCL1_INV0__INVREQ_SIZE_MASK 0x000007E0L |
42141 | #define SDMA3_UTCL1_INV0__INVREQ_IDLE_MASK 0x00000800L |
42142 | #define SDMA3_UTCL1_INV0__VMINV_PEND_CNT_MASK 0x0000F000L |
42143 | #define SDMA3_UTCL1_INV0__GPUVM_LO_INV_VMID_MASK 0x000F0000L |
42144 | #define SDMA3_UTCL1_INV0__GPUVM_HI_INV_VMID_MASK 0x00F00000L |
42145 | #define SDMA3_UTCL1_INV0__GPUVM_INV_MODE_MASK 0x03000000L |
42146 | #define SDMA3_UTCL1_INV0__INVREQ_IS_HEAVY_MASK 0x04000000L |
42147 | #define SDMA3_UTCL1_INV0__INVREQ_FROM_CPF_MASK 0x08000000L |
42148 | #define SDMA3_UTCL1_INV0__GPUVM_INVREQ_TAG_MASK 0xF0000000L |
42149 | //SDMA3_UTCL1_INV1 |
42150 | #define SDMA3_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 |
42151 | #define SDMA3_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL |
42152 | //SDMA3_UTCL1_INV2 |
42153 | #define SDMA3_UTCL1_INV2__INV_VMID_VEC__SHIFT 0x0 |
42154 | #define SDMA3_UTCL1_INV2__RESERVED__SHIFT 0x10 |
42155 | #define SDMA3_UTCL1_INV2__INV_VMID_VEC_MASK 0x0000FFFFL |
42156 | #define SDMA3_UTCL1_INV2__RESERVED_MASK 0xFFFF0000L |
42157 | //SDMA3_UTCL1_RD_XNACK0 |
42158 | #define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 |
42159 | #define SDMA3_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL |
42160 | //SDMA3_UTCL1_RD_XNACK1 |
42161 | #define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 |
42162 | #define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 |
42163 | #define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 |
42164 | #define SDMA3_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a |
42165 | #define SDMA3_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL |
42166 | #define SDMA3_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L |
42167 | #define SDMA3_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L |
42168 | #define SDMA3_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L |
42169 | //SDMA3_UTCL1_WR_XNACK0 |
42170 | #define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 |
42171 | #define SDMA3_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL |
42172 | //SDMA3_UTCL1_WR_XNACK1 |
42173 | #define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 |
42174 | #define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 |
42175 | #define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 |
42176 | #define SDMA3_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a |
42177 | #define SDMA3_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL |
42178 | #define SDMA3_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L |
42179 | #define SDMA3_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L |
42180 | #define SDMA3_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L |
42181 | //SDMA3_UTCL1_TIMEOUT |
42182 | #define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 |
42183 | #define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 |
42184 | #define SDMA3_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL |
42185 | #define SDMA3_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L |
42186 | //SDMA3_UTCL1_PAGE |
42187 | #define SDMA3_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 |
42188 | #define SDMA3_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 |
42189 | #define SDMA3_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 |
42190 | #define SDMA3_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa |
42191 | #define SDMA3_UTCL1_PAGE__USE_IO__SHIFT 0xb |
42192 | #define SDMA3_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc |
42193 | #define SDMA3_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe |
42194 | #define SDMA3_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT 0x10 |
42195 | #define SDMA3_UTCL1_PAGE__USE_BC__SHIFT 0x16 |
42196 | #define SDMA3_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17 |
42197 | #define SDMA3_UTCL1_PAGE__LLC_NOALLOC__SHIFT 0x18 |
42198 | #define SDMA3_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L |
42199 | #define SDMA3_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL |
42200 | #define SDMA3_UTCL1_PAGE__USE_MTYPE_MASK 0x000003C0L |
42201 | #define SDMA3_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L |
42202 | #define SDMA3_UTCL1_PAGE__USE_IO_MASK 0x00000800L |
42203 | #define SDMA3_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L |
42204 | #define SDMA3_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L |
42205 | #define SDMA3_UTCL1_PAGE__DMA_PAGE_SIZE_MASK 0x003F0000L |
42206 | #define SDMA3_UTCL1_PAGE__USE_BC_MASK 0x00400000L |
42207 | #define SDMA3_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L |
42208 | #define SDMA3_UTCL1_PAGE__LLC_NOALLOC_MASK 0x01000000L |
42209 | //SDMA3_RELAX_ORDERING_LUT |
42210 | #define SDMA3_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 |
42211 | #define SDMA3_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 |
42212 | #define SDMA3_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 |
42213 | #define SDMA3_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 |
42214 | #define SDMA3_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 |
42215 | #define SDMA3_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 |
42216 | #define SDMA3_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 |
42217 | #define SDMA3_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 |
42218 | #define SDMA3_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 |
42219 | #define SDMA3_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa |
42220 | #define SDMA3_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb |
42221 | #define SDMA3_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc |
42222 | #define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd |
42223 | #define SDMA3_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe |
42224 | #define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b |
42225 | #define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c |
42226 | #define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d |
42227 | #define SDMA3_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e |
42228 | #define SDMA3_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f |
42229 | #define SDMA3_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L |
42230 | #define SDMA3_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L |
42231 | #define SDMA3_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L |
42232 | #define SDMA3_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L |
42233 | #define SDMA3_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L |
42234 | #define SDMA3_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L |
42235 | #define SDMA3_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L |
42236 | #define SDMA3_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L |
42237 | #define SDMA3_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L |
42238 | #define SDMA3_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L |
42239 | #define SDMA3_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L |
42240 | #define SDMA3_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L |
42241 | #define SDMA3_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L |
42242 | #define SDMA3_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L |
42243 | #define SDMA3_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L |
42244 | #define SDMA3_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L |
42245 | #define SDMA3_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L |
42246 | #define SDMA3_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L |
42247 | #define SDMA3_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L |
42248 | //SDMA3_CHICKEN_BITS_2 |
42249 | #define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 |
42250 | #define SDMA3_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL__SHIFT 0x4 |
42251 | #define SDMA3_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE__SHIFT 0x5 |
42252 | #define SDMA3_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT 0x6 |
42253 | #define SDMA3_CHICKEN_BITS_2__RESERVED0__SHIFT 0x7 |
42254 | #define SDMA3_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN__SHIFT 0xb |
42255 | #define SDMA3_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR__SHIFT 0xf |
42256 | #define SDMA3_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT 0x10 |
42257 | #define SDMA3_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT 0x12 |
42258 | #define SDMA3_CHICKEN_BITS_2__REPEATER_FGCG_EN__SHIFT 0x14 |
42259 | #define SDMA3_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x15 |
42260 | #define SDMA3_CHICKEN_BITS_2__RESERVED__SHIFT 0x16 |
42261 | #define SDMA3_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL |
42262 | #define SDMA3_CHICKEN_BITS_2__CE_BACKWARDS_SIZE_SEL_MASK 0x00000010L |
42263 | #define SDMA3_CHICKEN_BITS_2__CE_DCC_READ_128B_ENABLE_MASK 0x00000020L |
42264 | #define SDMA3_CHICKEN_BITS_2__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK 0x00000040L |
42265 | #define SDMA3_CHICKEN_BITS_2__RESERVED0_MASK 0x00000780L |
42266 | #define SDMA3_CHICKEN_BITS_2__LUT_FIFO_AFULL_MARGIN_MASK 0x00007800L |
42267 | #define SDMA3_CHICKEN_BITS_2__LEGACY_WPTR_POLL_BEHAVIOR_MASK 0x00008000L |
42268 | #define SDMA3_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK 0x00030000L |
42269 | #define SDMA3_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK 0x000C0000L |
42270 | #define SDMA3_CHICKEN_BITS_2__REPEATER_FGCG_EN_MASK 0x00100000L |
42271 | #define SDMA3_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00200000L |
42272 | #define SDMA3_CHICKEN_BITS_2__RESERVED_MASK 0xFFC00000L |
42273 | //SDMA3_STATUS3_REG |
42274 | #define SDMA3_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 |
42275 | #define SDMA3_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 |
42276 | #define SDMA3_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 |
42277 | #define SDMA3_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15 |
42278 | #define SDMA3_STATUS3_REG__TLBI_IDLE__SHIFT 0x16 |
42279 | #define SDMA3_STATUS3_REG__GCR_IDLE__SHIFT 0x17 |
42280 | #define SDMA3_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18 |
42281 | #define SDMA3_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19 |
42282 | #define SDMA3_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a |
42283 | #define SDMA3_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL |
42284 | #define SDMA3_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L |
42285 | #define SDMA3_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L |
42286 | #define SDMA3_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L |
42287 | #define SDMA3_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L |
42288 | #define SDMA3_STATUS3_REG__GCR_IDLE_MASK 0x00800000L |
42289 | #define SDMA3_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L |
42290 | #define SDMA3_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L |
42291 | #define SDMA3_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L |
42292 | //SDMA3_PHYSICAL_ADDR_LO |
42293 | #define SDMA3_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 |
42294 | #define SDMA3_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 |
42295 | #define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 |
42296 | #define SDMA3_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc |
42297 | #define SDMA3_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L |
42298 | #define SDMA3_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L |
42299 | #define SDMA3_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L |
42300 | #define SDMA3_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L |
42301 | //SDMA3_PHYSICAL_ADDR_HI |
42302 | #define SDMA3_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 |
42303 | #define SDMA3_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL |
42304 | //SDMA3_PHASE2_QUANTUM |
42305 | #define SDMA3_PHASE2_QUANTUM__UNIT__SHIFT 0x0 |
42306 | #define SDMA3_PHASE2_QUANTUM__VALUE__SHIFT 0x8 |
42307 | #define SDMA3_PHASE2_QUANTUM__PREFER__SHIFT 0x1e |
42308 | #define SDMA3_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL |
42309 | #define SDMA3_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L |
42310 | #define SDMA3_PHASE2_QUANTUM__PREFER_MASK 0x40000000L |
42311 | //SDMA3_ERROR_LOG |
42312 | #define SDMA3_ERROR_LOG__OVERRIDE__SHIFT 0x0 |
42313 | #define SDMA3_ERROR_LOG__STATUS__SHIFT 0x10 |
42314 | #define SDMA3_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL |
42315 | #define SDMA3_ERROR_LOG__STATUS_MASK 0xFFFF0000L |
42316 | //SDMA3_PUB_DUMMY_REG0 |
42317 | #define SDMA3_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 |
42318 | #define SDMA3_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL |
42319 | //SDMA3_PUB_DUMMY_REG1 |
42320 | #define SDMA3_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 |
42321 | #define SDMA3_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL |
42322 | //SDMA3_PUB_DUMMY_REG2 |
42323 | #define SDMA3_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 |
42324 | #define SDMA3_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL |
42325 | //SDMA3_PUB_DUMMY_REG3 |
42326 | #define SDMA3_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 |
42327 | #define SDMA3_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL |
42328 | //SDMA3_F32_COUNTER |
42329 | #define SDMA3_F32_COUNTER__VALUE__SHIFT 0x0 |
42330 | #define SDMA3_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL |
42331 | //SDMA3_CRD_CNTL |
42332 | #define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 |
42333 | #define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd |
42334 | #define SDMA3_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13 |
42335 | #define SDMA3_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19 |
42336 | #define SDMA3_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L |
42337 | #define SDMA3_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L |
42338 | #define SDMA3_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L |
42339 | #define SDMA3_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L |
42340 | //SDMA3_AQL_STATUS |
42341 | #define SDMA3_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0 |
42342 | #define SDMA3_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1 |
42343 | #define SDMA3_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L |
42344 | #define SDMA3_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L |
42345 | //SDMA3_EA_DBIT_ADDR_DATA |
42346 | #define SDMA3_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 |
42347 | #define SDMA3_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL |
42348 | //SDMA3_EA_DBIT_ADDR_INDEX |
42349 | #define SDMA3_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 |
42350 | #define SDMA3_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L |
42351 | //SDMA3_TLBI_GCR_CNTL |
42352 | #define SDMA3_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0 |
42353 | #define SDMA3_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4 |
42354 | #define SDMA3_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT 0x8 |
42355 | #define SDMA3_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10 |
42356 | #define SDMA3_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18 |
42357 | #define SDMA3_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL |
42358 | #define SDMA3_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L |
42359 | #define SDMA3_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK 0x00000F00L |
42360 | #define SDMA3_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L |
42361 | #define SDMA3_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L |
42362 | //SDMA3_TILING_CONFIG |
42363 | #define SDMA3_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
42364 | #define SDMA3_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L |
42365 | //SDMA3_INT_STATUS |
42366 | #define SDMA3_INT_STATUS__DATA__SHIFT 0x0 |
42367 | #define SDMA3_INT_STATUS__DATA_MASK 0xFFFFFFFFL |
42368 | //SDMA3_HOLE_ADDR_LO |
42369 | #define SDMA3_HOLE_ADDR_LO__VALUE__SHIFT 0x0 |
42370 | #define SDMA3_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL |
42371 | //SDMA3_HOLE_ADDR_HI |
42372 | #define SDMA3_HOLE_ADDR_HI__VALUE__SHIFT 0x0 |
42373 | #define SDMA3_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL |
42374 | //SDMA3_CLOCK_GATING_REG |
42375 | #define SDMA3_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS__SHIFT 0x0 |
42376 | #define SDMA3_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS__SHIFT 0x1 |
42377 | #define SDMA3_CLOCK_GATING_REG__CE_CLK_GATE_STATUS__SHIFT 0x2 |
42378 | #define SDMA3_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS__SHIFT 0x3 |
42379 | #define SDMA3_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS__SHIFT 0x4 |
42380 | #define SDMA3_CLOCK_GATING_REG__REG_CLK_GATE_STATUS__SHIFT 0x5 |
42381 | #define SDMA3_CLOCK_GATING_REG__DYN_CLK_GATE_STATUS_MASK 0x00000001L |
42382 | #define SDMA3_CLOCK_GATING_REG__PTR_CLK_GATE_STATUS_MASK 0x00000002L |
42383 | #define SDMA3_CLOCK_GATING_REG__CE_CLK_GATE_STATUS_MASK 0x00000004L |
42384 | #define SDMA3_CLOCK_GATING_REG__CE_BC_CLK_GATE_STATUS_MASK 0x00000008L |
42385 | #define SDMA3_CLOCK_GATING_REG__CE_NBC_CLK_GATE_STATUS_MASK 0x00000010L |
42386 | #define SDMA3_CLOCK_GATING_REG__REG_CLK_GATE_STATUS_MASK 0x00000020L |
42387 | //SDMA3_STATUS4_REG |
42388 | #define SDMA3_STATUS4_REG__IDLE__SHIFT 0x0 |
42389 | #define SDMA3_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 |
42390 | #define SDMA3_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 |
42391 | #define SDMA3_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT 0x4 |
42392 | #define SDMA3_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT 0x5 |
42393 | #define SDMA3_STATUS4_REG__GCR_OUTSTANDING__SHIFT 0x6 |
42394 | #define SDMA3_STATUS4_REG__TLBI_OUTSTANDING__SHIFT 0x7 |
42395 | #define SDMA3_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x8 |
42396 | #define SDMA3_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x9 |
42397 | #define SDMA3_STATUS4_REG__REG_POLLING__SHIFT 0xa |
42398 | #define SDMA3_STATUS4_REG__MEM_POLLING__SHIFT 0xb |
42399 | #define SDMA3_STATUS4_REG__UTCL2_RD_XNACK__SHIFT 0xc |
42400 | #define SDMA3_STATUS4_REG__UTCL2_WR_XNACK__SHIFT 0xe |
42401 | #define SDMA3_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 |
42402 | #define SDMA3_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x14 |
42403 | #define SDMA3_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x15 |
42404 | #define SDMA3_STATUS4_REG__IDLE_MASK 0x00000001L |
42405 | #define SDMA3_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L |
42406 | #define SDMA3_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L |
42407 | #define SDMA3_STATUS4_REG__CH_RD_OUTSTANDING_MASK 0x00000010L |
42408 | #define SDMA3_STATUS4_REG__CH_WR_OUTSTANDING_MASK 0x00000020L |
42409 | #define SDMA3_STATUS4_REG__GCR_OUTSTANDING_MASK 0x00000040L |
42410 | #define SDMA3_STATUS4_REG__TLBI_OUTSTANDING_MASK 0x00000080L |
42411 | #define SDMA3_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000100L |
42412 | #define SDMA3_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000200L |
42413 | #define SDMA3_STATUS4_REG__REG_POLLING_MASK 0x00000400L |
42414 | #define SDMA3_STATUS4_REG__MEM_POLLING_MASK 0x00000800L |
42415 | #define SDMA3_STATUS4_REG__UTCL2_RD_XNACK_MASK 0x00003000L |
42416 | #define SDMA3_STATUS4_REG__UTCL2_WR_XNACK_MASK 0x0000C000L |
42417 | #define SDMA3_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L |
42418 | #define SDMA3_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00100000L |
42419 | #define SDMA3_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00200000L |
42420 | //SDMA3_SCRATCH_RAM_DATA |
42421 | #define SDMA3_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 |
42422 | #define SDMA3_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL |
42423 | //SDMA3_SCRATCH_RAM_ADDR |
42424 | #define SDMA3_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 |
42425 | #define SDMA3_SCRATCH_RAM_ADDR__ADDR_MASK 0x000003FFL |
42426 | //SDMA3_TIMESTAMP_CNTL |
42427 | #define SDMA3_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 |
42428 | #define SDMA3_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L |
42429 | //SDMA3_STATUS5_REG |
42430 | #define SDMA3_STATUS5_REG__GFX_RB_ENABLE_STATUS__SHIFT 0x0 |
42431 | #define SDMA3_STATUS5_REG__PAGE_RB_ENABLE_STATUS__SHIFT 0x1 |
42432 | #define SDMA3_STATUS5_REG__RLC0_RB_ENABLE_STATUS__SHIFT 0x2 |
42433 | #define SDMA3_STATUS5_REG__RLC1_RB_ENABLE_STATUS__SHIFT 0x3 |
42434 | #define SDMA3_STATUS5_REG__RLC2_RB_ENABLE_STATUS__SHIFT 0x4 |
42435 | #define SDMA3_STATUS5_REG__RLC3_RB_ENABLE_STATUS__SHIFT 0x5 |
42436 | #define SDMA3_STATUS5_REG__RLC4_RB_ENABLE_STATUS__SHIFT 0x6 |
42437 | #define SDMA3_STATUS5_REG__RLC5_RB_ENABLE_STATUS__SHIFT 0x7 |
42438 | #define SDMA3_STATUS5_REG__RLC6_RB_ENABLE_STATUS__SHIFT 0x8 |
42439 | #define SDMA3_STATUS5_REG__RLC7_RB_ENABLE_STATUS__SHIFT 0x9 |
42440 | #define SDMA3_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 |
42441 | #define SDMA3_STATUS5_REG__GFX_RB_ENABLE_STATUS_MASK 0x00000001L |
42442 | #define SDMA3_STATUS5_REG__PAGE_RB_ENABLE_STATUS_MASK 0x00000002L |
42443 | #define SDMA3_STATUS5_REG__RLC0_RB_ENABLE_STATUS_MASK 0x00000004L |
42444 | #define SDMA3_STATUS5_REG__RLC1_RB_ENABLE_STATUS_MASK 0x00000008L |
42445 | #define SDMA3_STATUS5_REG__RLC2_RB_ENABLE_STATUS_MASK 0x00000010L |
42446 | #define SDMA3_STATUS5_REG__RLC3_RB_ENABLE_STATUS_MASK 0x00000020L |
42447 | #define SDMA3_STATUS5_REG__RLC4_RB_ENABLE_STATUS_MASK 0x00000040L |
42448 | #define SDMA3_STATUS5_REG__RLC5_RB_ENABLE_STATUS_MASK 0x00000080L |
42449 | #define SDMA3_STATUS5_REG__RLC6_RB_ENABLE_STATUS_MASK 0x00000100L |
42450 | #define SDMA3_STATUS5_REG__RLC7_RB_ENABLE_STATUS_MASK 0x00000200L |
42451 | #define SDMA3_STATUS5_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L |
42452 | //SDMA3_QUEUE_RESET_REQ |
42453 | #define SDMA3_QUEUE_RESET_REQ__GFX_QUEUE_RESET__SHIFT 0x0 |
42454 | #define SDMA3_QUEUE_RESET_REQ__PAGE_QUEUE_RESET__SHIFT 0x1 |
42455 | #define SDMA3_QUEUE_RESET_REQ__RLC0_QUEUE_RESET__SHIFT 0x2 |
42456 | #define SDMA3_QUEUE_RESET_REQ__RLC1_QUEUE_RESET__SHIFT 0x3 |
42457 | #define SDMA3_QUEUE_RESET_REQ__RLC2_QUEUE_RESET__SHIFT 0x4 |
42458 | #define SDMA3_QUEUE_RESET_REQ__RLC3_QUEUE_RESET__SHIFT 0x5 |
42459 | #define SDMA3_QUEUE_RESET_REQ__RLC4_QUEUE_RESET__SHIFT 0x6 |
42460 | #define SDMA3_QUEUE_RESET_REQ__RLC5_QUEUE_RESET__SHIFT 0x7 |
42461 | #define SDMA3_QUEUE_RESET_REQ__RLC6_QUEUE_RESET__SHIFT 0x8 |
42462 | #define SDMA3_QUEUE_RESET_REQ__RLC7_QUEUE_RESET__SHIFT 0x9 |
42463 | #define SDMA3_QUEUE_RESET_REQ__RESERVED__SHIFT 0xa |
42464 | #define SDMA3_QUEUE_RESET_REQ__GFX_QUEUE_RESET_MASK 0x00000001L |
42465 | #define SDMA3_QUEUE_RESET_REQ__PAGE_QUEUE_RESET_MASK 0x00000002L |
42466 | #define SDMA3_QUEUE_RESET_REQ__RLC0_QUEUE_RESET_MASK 0x00000004L |
42467 | #define SDMA3_QUEUE_RESET_REQ__RLC1_QUEUE_RESET_MASK 0x00000008L |
42468 | #define SDMA3_QUEUE_RESET_REQ__RLC2_QUEUE_RESET_MASK 0x00000010L |
42469 | #define SDMA3_QUEUE_RESET_REQ__RLC3_QUEUE_RESET_MASK 0x00000020L |
42470 | #define SDMA3_QUEUE_RESET_REQ__RLC4_QUEUE_RESET_MASK 0x00000040L |
42471 | #define SDMA3_QUEUE_RESET_REQ__RLC5_QUEUE_RESET_MASK 0x00000080L |
42472 | #define SDMA3_QUEUE_RESET_REQ__RLC6_QUEUE_RESET_MASK 0x00000100L |
42473 | #define SDMA3_QUEUE_RESET_REQ__RLC7_QUEUE_RESET_MASK 0x00000200L |
42474 | #define SDMA3_QUEUE_RESET_REQ__RESERVED_MASK 0xFFFFFC00L |
42475 | //SDMA3_GFX_RB_CNTL |
42476 | #define SDMA3_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
42477 | #define SDMA3_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 |
42478 | #define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
42479 | #define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
42480 | #define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
42481 | #define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
42482 | #define SDMA3_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 |
42483 | #define SDMA3_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 |
42484 | #define SDMA3_GFX_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
42485 | #define SDMA3_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
42486 | #define SDMA3_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
42487 | #define SDMA3_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
42488 | #define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
42489 | #define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
42490 | #define SDMA3_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
42491 | #define SDMA3_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L |
42492 | #define SDMA3_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L |
42493 | #define SDMA3_GFX_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
42494 | //SDMA3_GFX_RB_BASE |
42495 | #define SDMA3_GFX_RB_BASE__ADDR__SHIFT 0x0 |
42496 | #define SDMA3_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
42497 | //SDMA3_GFX_RB_BASE_HI |
42498 | #define SDMA3_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 |
42499 | #define SDMA3_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
42500 | //SDMA3_GFX_RB_RPTR |
42501 | #define SDMA3_GFX_RB_RPTR__OFFSET__SHIFT 0x0 |
42502 | #define SDMA3_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
42503 | //SDMA3_GFX_RB_RPTR_HI |
42504 | #define SDMA3_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
42505 | #define SDMA3_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
42506 | //SDMA3_GFX_RB_WPTR |
42507 | #define SDMA3_GFX_RB_WPTR__OFFSET__SHIFT 0x0 |
42508 | #define SDMA3_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
42509 | //SDMA3_GFX_RB_WPTR_HI |
42510 | #define SDMA3_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
42511 | #define SDMA3_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
42512 | //SDMA3_GFX_RB_WPTR_POLL_CNTL |
42513 | #define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
42514 | #define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
42515 | #define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
42516 | #define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
42517 | #define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
42518 | #define SDMA3_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
42519 | #define SDMA3_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
42520 | #define SDMA3_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
42521 | #define SDMA3_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
42522 | #define SDMA3_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
42523 | //SDMA3_GFX_RB_RPTR_ADDR_HI |
42524 | #define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
42525 | #define SDMA3_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
42526 | //SDMA3_GFX_RB_RPTR_ADDR_LO |
42527 | #define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
42528 | #define SDMA3_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
42529 | //SDMA3_GFX_IB_CNTL |
42530 | #define SDMA3_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
42531 | #define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
42532 | #define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
42533 | #define SDMA3_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 |
42534 | #define SDMA3_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
42535 | #define SDMA3_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
42536 | #define SDMA3_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
42537 | #define SDMA3_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
42538 | //SDMA3_GFX_IB_RPTR |
42539 | #define SDMA3_GFX_IB_RPTR__OFFSET__SHIFT 0x2 |
42540 | #define SDMA3_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
42541 | //SDMA3_GFX_IB_OFFSET |
42542 | #define SDMA3_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 |
42543 | #define SDMA3_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
42544 | //SDMA3_GFX_IB_BASE_LO |
42545 | #define SDMA3_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 |
42546 | #define SDMA3_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
42547 | //SDMA3_GFX_IB_BASE_HI |
42548 | #define SDMA3_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 |
42549 | #define SDMA3_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
42550 | //SDMA3_GFX_IB_SIZE |
42551 | #define SDMA3_GFX_IB_SIZE__SIZE__SHIFT 0x0 |
42552 | #define SDMA3_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL |
42553 | //SDMA3_GFX_SKIP_CNTL |
42554 | #define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
42555 | #define SDMA3_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
42556 | //SDMA3_GFX_CONTEXT_STATUS |
42557 | #define SDMA3_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
42558 | #define SDMA3_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
42559 | #define SDMA3_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
42560 | #define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
42561 | #define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
42562 | #define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
42563 | #define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
42564 | #define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
42565 | #define SDMA3_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
42566 | #define SDMA3_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
42567 | #define SDMA3_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
42568 | #define SDMA3_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
42569 | #define SDMA3_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
42570 | #define SDMA3_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
42571 | #define SDMA3_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
42572 | #define SDMA3_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
42573 | //SDMA3_GFX_DOORBELL |
42574 | #define SDMA3_GFX_DOORBELL__ENABLE__SHIFT 0x1c |
42575 | #define SDMA3_GFX_DOORBELL__CAPTURED__SHIFT 0x1e |
42576 | #define SDMA3_GFX_DOORBELL__ENABLE_MASK 0x10000000L |
42577 | #define SDMA3_GFX_DOORBELL__CAPTURED_MASK 0x40000000L |
42578 | //SDMA3_GFX_CONTEXT_CNTL |
42579 | #define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 |
42580 | #define SDMA3_GFX_CONTEXT_CNTL__SESSION_SEL__SHIFT 0x18 |
42581 | #define SDMA3_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L |
42582 | #define SDMA3_GFX_CONTEXT_CNTL__SESSION_SEL_MASK 0x0F000000L |
42583 | //SDMA3_GFX_STATUS |
42584 | #define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
42585 | #define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
42586 | #define SDMA3_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
42587 | #define SDMA3_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
42588 | //SDMA3_GFX_DOORBELL_LOG |
42589 | #define SDMA3_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
42590 | #define SDMA3_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 |
42591 | #define SDMA3_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
42592 | #define SDMA3_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
42593 | //SDMA3_GFX_WATERMARK |
42594 | #define SDMA3_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
42595 | #define SDMA3_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
42596 | #define SDMA3_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
42597 | #define SDMA3_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
42598 | //SDMA3_GFX_DOORBELL_OFFSET |
42599 | #define SDMA3_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
42600 | #define SDMA3_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
42601 | //SDMA3_GFX_CSA_ADDR_LO |
42602 | #define SDMA3_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
42603 | #define SDMA3_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
42604 | //SDMA3_GFX_CSA_ADDR_HI |
42605 | #define SDMA3_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
42606 | #define SDMA3_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
42607 | //SDMA3_GFX_IB_SUB_REMAIN |
42608 | #define SDMA3_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
42609 | #define SDMA3_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
42610 | //SDMA3_GFX_PREEMPT |
42611 | #define SDMA3_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
42612 | #define SDMA3_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
42613 | //SDMA3_GFX_DUMMY_REG |
42614 | #define SDMA3_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 |
42615 | #define SDMA3_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
42616 | //SDMA3_GFX_RB_WPTR_POLL_ADDR_HI |
42617 | #define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
42618 | #define SDMA3_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
42619 | //SDMA3_GFX_RB_WPTR_POLL_ADDR_LO |
42620 | #define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
42621 | #define SDMA3_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
42622 | //SDMA3_GFX_RB_AQL_CNTL |
42623 | #define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
42624 | #define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
42625 | #define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
42626 | #define SDMA3_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
42627 | #define SDMA3_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
42628 | #define SDMA3_GFX_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
42629 | #define SDMA3_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
42630 | #define SDMA3_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
42631 | #define SDMA3_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
42632 | #define SDMA3_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
42633 | #define SDMA3_GFX_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
42634 | #define SDMA3_GFX_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
42635 | //SDMA3_GFX_MINOR_PTR_UPDATE |
42636 | #define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
42637 | #define SDMA3_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
42638 | //SDMA3_GFX_MIDCMD_DATA0 |
42639 | #define SDMA3_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
42640 | #define SDMA3_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
42641 | //SDMA3_GFX_MIDCMD_DATA1 |
42642 | #define SDMA3_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
42643 | #define SDMA3_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
42644 | //SDMA3_GFX_MIDCMD_DATA2 |
42645 | #define SDMA3_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
42646 | #define SDMA3_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
42647 | //SDMA3_GFX_MIDCMD_DATA3 |
42648 | #define SDMA3_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
42649 | #define SDMA3_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
42650 | //SDMA3_GFX_MIDCMD_DATA4 |
42651 | #define SDMA3_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
42652 | #define SDMA3_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
42653 | //SDMA3_GFX_MIDCMD_DATA5 |
42654 | #define SDMA3_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
42655 | #define SDMA3_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
42656 | //SDMA3_GFX_MIDCMD_DATA6 |
42657 | #define SDMA3_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
42658 | #define SDMA3_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
42659 | //SDMA3_GFX_MIDCMD_DATA7 |
42660 | #define SDMA3_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
42661 | #define SDMA3_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
42662 | //SDMA3_GFX_MIDCMD_DATA8 |
42663 | #define SDMA3_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
42664 | #define SDMA3_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
42665 | //SDMA3_GFX_MIDCMD_DATA9 |
42666 | #define SDMA3_GFX_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
42667 | #define SDMA3_GFX_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
42668 | //SDMA3_GFX_MIDCMD_DATA10 |
42669 | #define SDMA3_GFX_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
42670 | #define SDMA3_GFX_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
42671 | //SDMA3_GFX_MIDCMD_CNTL |
42672 | #define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
42673 | #define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
42674 | #define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
42675 | #define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
42676 | #define SDMA3_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
42677 | #define SDMA3_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
42678 | #define SDMA3_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
42679 | #define SDMA3_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
42680 | //SDMA3_PAGE_RB_CNTL |
42681 | #define SDMA3_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
42682 | #define SDMA3_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 |
42683 | #define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
42684 | #define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
42685 | #define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
42686 | #define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
42687 | #define SDMA3_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 |
42688 | #define SDMA3_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 |
42689 | #define SDMA3_PAGE_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
42690 | #define SDMA3_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
42691 | #define SDMA3_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
42692 | #define SDMA3_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
42693 | #define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
42694 | #define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
42695 | #define SDMA3_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
42696 | #define SDMA3_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L |
42697 | #define SDMA3_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L |
42698 | #define SDMA3_PAGE_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
42699 | //SDMA3_PAGE_RB_BASE |
42700 | #define SDMA3_PAGE_RB_BASE__ADDR__SHIFT 0x0 |
42701 | #define SDMA3_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
42702 | //SDMA3_PAGE_RB_BASE_HI |
42703 | #define SDMA3_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 |
42704 | #define SDMA3_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
42705 | //SDMA3_PAGE_RB_RPTR |
42706 | #define SDMA3_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 |
42707 | #define SDMA3_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
42708 | //SDMA3_PAGE_RB_RPTR_HI |
42709 | #define SDMA3_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
42710 | #define SDMA3_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
42711 | //SDMA3_PAGE_RB_WPTR |
42712 | #define SDMA3_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 |
42713 | #define SDMA3_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
42714 | //SDMA3_PAGE_RB_WPTR_HI |
42715 | #define SDMA3_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
42716 | #define SDMA3_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
42717 | //SDMA3_PAGE_RB_WPTR_POLL_CNTL |
42718 | #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
42719 | #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
42720 | #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
42721 | #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
42722 | #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
42723 | #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
42724 | #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
42725 | #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
42726 | #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
42727 | #define SDMA3_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
42728 | //SDMA3_PAGE_RB_RPTR_ADDR_HI |
42729 | #define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
42730 | #define SDMA3_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
42731 | //SDMA3_PAGE_RB_RPTR_ADDR_LO |
42732 | #define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
42733 | #define SDMA3_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
42734 | //SDMA3_PAGE_IB_CNTL |
42735 | #define SDMA3_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
42736 | #define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
42737 | #define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
42738 | #define SDMA3_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 |
42739 | #define SDMA3_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
42740 | #define SDMA3_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
42741 | #define SDMA3_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
42742 | #define SDMA3_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
42743 | //SDMA3_PAGE_IB_RPTR |
42744 | #define SDMA3_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 |
42745 | #define SDMA3_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
42746 | //SDMA3_PAGE_IB_OFFSET |
42747 | #define SDMA3_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 |
42748 | #define SDMA3_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
42749 | //SDMA3_PAGE_IB_BASE_LO |
42750 | #define SDMA3_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 |
42751 | #define SDMA3_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
42752 | //SDMA3_PAGE_IB_BASE_HI |
42753 | #define SDMA3_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 |
42754 | #define SDMA3_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
42755 | //SDMA3_PAGE_IB_SIZE |
42756 | #define SDMA3_PAGE_IB_SIZE__SIZE__SHIFT 0x0 |
42757 | #define SDMA3_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL |
42758 | //SDMA3_PAGE_SKIP_CNTL |
42759 | #define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
42760 | #define SDMA3_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
42761 | //SDMA3_PAGE_CONTEXT_STATUS |
42762 | #define SDMA3_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
42763 | #define SDMA3_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
42764 | #define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
42765 | #define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
42766 | #define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
42767 | #define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
42768 | #define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
42769 | #define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
42770 | #define SDMA3_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
42771 | #define SDMA3_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
42772 | #define SDMA3_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
42773 | #define SDMA3_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
42774 | #define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
42775 | #define SDMA3_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
42776 | #define SDMA3_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
42777 | #define SDMA3_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
42778 | //SDMA3_PAGE_DOORBELL |
42779 | #define SDMA3_PAGE_DOORBELL__ENABLE__SHIFT 0x1c |
42780 | #define SDMA3_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e |
42781 | #define SDMA3_PAGE_DOORBELL__ENABLE_MASK 0x10000000L |
42782 | #define SDMA3_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L |
42783 | //SDMA3_PAGE_STATUS |
42784 | #define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
42785 | #define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
42786 | #define SDMA3_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
42787 | #define SDMA3_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
42788 | //SDMA3_PAGE_DOORBELL_LOG |
42789 | #define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
42790 | #define SDMA3_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 |
42791 | #define SDMA3_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
42792 | #define SDMA3_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
42793 | //SDMA3_PAGE_WATERMARK |
42794 | #define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
42795 | #define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
42796 | #define SDMA3_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
42797 | #define SDMA3_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
42798 | //SDMA3_PAGE_DOORBELL_OFFSET |
42799 | #define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
42800 | #define SDMA3_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
42801 | //SDMA3_PAGE_CSA_ADDR_LO |
42802 | #define SDMA3_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
42803 | #define SDMA3_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
42804 | //SDMA3_PAGE_CSA_ADDR_HI |
42805 | #define SDMA3_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
42806 | #define SDMA3_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
42807 | //SDMA3_PAGE_IB_SUB_REMAIN |
42808 | #define SDMA3_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
42809 | #define SDMA3_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
42810 | //SDMA3_PAGE_PREEMPT |
42811 | #define SDMA3_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
42812 | #define SDMA3_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
42813 | //SDMA3_PAGE_DUMMY_REG |
42814 | #define SDMA3_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 |
42815 | #define SDMA3_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
42816 | //SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI |
42817 | #define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
42818 | #define SDMA3_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
42819 | //SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO |
42820 | #define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
42821 | #define SDMA3_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
42822 | //SDMA3_PAGE_RB_AQL_CNTL |
42823 | #define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
42824 | #define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
42825 | #define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
42826 | #define SDMA3_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
42827 | #define SDMA3_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
42828 | #define SDMA3_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
42829 | #define SDMA3_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
42830 | #define SDMA3_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
42831 | #define SDMA3_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
42832 | #define SDMA3_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
42833 | #define SDMA3_PAGE_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
42834 | #define SDMA3_PAGE_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
42835 | //SDMA3_PAGE_MINOR_PTR_UPDATE |
42836 | #define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
42837 | #define SDMA3_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
42838 | //SDMA3_PAGE_MIDCMD_DATA0 |
42839 | #define SDMA3_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
42840 | #define SDMA3_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
42841 | //SDMA3_PAGE_MIDCMD_DATA1 |
42842 | #define SDMA3_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
42843 | #define SDMA3_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
42844 | //SDMA3_PAGE_MIDCMD_DATA2 |
42845 | #define SDMA3_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
42846 | #define SDMA3_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
42847 | //SDMA3_PAGE_MIDCMD_DATA3 |
42848 | #define SDMA3_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
42849 | #define SDMA3_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
42850 | //SDMA3_PAGE_MIDCMD_DATA4 |
42851 | #define SDMA3_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
42852 | #define SDMA3_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
42853 | //SDMA3_PAGE_MIDCMD_DATA5 |
42854 | #define SDMA3_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
42855 | #define SDMA3_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
42856 | //SDMA3_PAGE_MIDCMD_DATA6 |
42857 | #define SDMA3_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
42858 | #define SDMA3_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
42859 | //SDMA3_PAGE_MIDCMD_DATA7 |
42860 | #define SDMA3_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
42861 | #define SDMA3_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
42862 | //SDMA3_PAGE_MIDCMD_DATA8 |
42863 | #define SDMA3_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
42864 | #define SDMA3_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
42865 | //SDMA3_PAGE_MIDCMD_DATA9 |
42866 | #define SDMA3_PAGE_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
42867 | #define SDMA3_PAGE_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
42868 | //SDMA3_PAGE_MIDCMD_DATA10 |
42869 | #define SDMA3_PAGE_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
42870 | #define SDMA3_PAGE_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
42871 | //SDMA3_PAGE_MIDCMD_CNTL |
42872 | #define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
42873 | #define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
42874 | #define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
42875 | #define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
42876 | #define SDMA3_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
42877 | #define SDMA3_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
42878 | #define SDMA3_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
42879 | #define SDMA3_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
42880 | //SDMA3_RLC0_RB_CNTL |
42881 | #define SDMA3_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
42882 | #define SDMA3_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 |
42883 | #define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
42884 | #define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
42885 | #define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
42886 | #define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
42887 | #define SDMA3_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 |
42888 | #define SDMA3_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 |
42889 | #define SDMA3_RLC0_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
42890 | #define SDMA3_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
42891 | #define SDMA3_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
42892 | #define SDMA3_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
42893 | #define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
42894 | #define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
42895 | #define SDMA3_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
42896 | #define SDMA3_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L |
42897 | #define SDMA3_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L |
42898 | #define SDMA3_RLC0_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
42899 | //SDMA3_RLC0_RB_BASE |
42900 | #define SDMA3_RLC0_RB_BASE__ADDR__SHIFT 0x0 |
42901 | #define SDMA3_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
42902 | //SDMA3_RLC0_RB_BASE_HI |
42903 | #define SDMA3_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 |
42904 | #define SDMA3_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
42905 | //SDMA3_RLC0_RB_RPTR |
42906 | #define SDMA3_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 |
42907 | #define SDMA3_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
42908 | //SDMA3_RLC0_RB_RPTR_HI |
42909 | #define SDMA3_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
42910 | #define SDMA3_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
42911 | //SDMA3_RLC0_RB_WPTR |
42912 | #define SDMA3_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 |
42913 | #define SDMA3_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
42914 | //SDMA3_RLC0_RB_WPTR_HI |
42915 | #define SDMA3_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
42916 | #define SDMA3_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
42917 | //SDMA3_RLC0_RB_WPTR_POLL_CNTL |
42918 | #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
42919 | #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
42920 | #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
42921 | #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
42922 | #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
42923 | #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
42924 | #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
42925 | #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
42926 | #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
42927 | #define SDMA3_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
42928 | //SDMA3_RLC0_RB_RPTR_ADDR_HI |
42929 | #define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
42930 | #define SDMA3_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
42931 | //SDMA3_RLC0_RB_RPTR_ADDR_LO |
42932 | #define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
42933 | #define SDMA3_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
42934 | //SDMA3_RLC0_IB_CNTL |
42935 | #define SDMA3_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
42936 | #define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
42937 | #define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
42938 | #define SDMA3_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 |
42939 | #define SDMA3_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
42940 | #define SDMA3_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
42941 | #define SDMA3_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
42942 | #define SDMA3_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
42943 | //SDMA3_RLC0_IB_RPTR |
42944 | #define SDMA3_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 |
42945 | #define SDMA3_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
42946 | //SDMA3_RLC0_IB_OFFSET |
42947 | #define SDMA3_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 |
42948 | #define SDMA3_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
42949 | //SDMA3_RLC0_IB_BASE_LO |
42950 | #define SDMA3_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 |
42951 | #define SDMA3_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
42952 | //SDMA3_RLC0_IB_BASE_HI |
42953 | #define SDMA3_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 |
42954 | #define SDMA3_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
42955 | //SDMA3_RLC0_IB_SIZE |
42956 | #define SDMA3_RLC0_IB_SIZE__SIZE__SHIFT 0x0 |
42957 | #define SDMA3_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL |
42958 | //SDMA3_RLC0_SKIP_CNTL |
42959 | #define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
42960 | #define SDMA3_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
42961 | //SDMA3_RLC0_CONTEXT_STATUS |
42962 | #define SDMA3_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
42963 | #define SDMA3_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
42964 | #define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
42965 | #define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
42966 | #define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
42967 | #define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
42968 | #define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
42969 | #define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
42970 | #define SDMA3_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
42971 | #define SDMA3_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
42972 | #define SDMA3_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
42973 | #define SDMA3_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
42974 | #define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
42975 | #define SDMA3_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
42976 | #define SDMA3_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
42977 | #define SDMA3_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
42978 | //SDMA3_RLC0_DOORBELL |
42979 | #define SDMA3_RLC0_DOORBELL__ENABLE__SHIFT 0x1c |
42980 | #define SDMA3_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e |
42981 | #define SDMA3_RLC0_DOORBELL__ENABLE_MASK 0x10000000L |
42982 | #define SDMA3_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L |
42983 | //SDMA3_RLC0_STATUS |
42984 | #define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
42985 | #define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
42986 | #define SDMA3_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
42987 | #define SDMA3_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
42988 | //SDMA3_RLC0_DOORBELL_LOG |
42989 | #define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
42990 | #define SDMA3_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 |
42991 | #define SDMA3_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
42992 | #define SDMA3_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
42993 | //SDMA3_RLC0_WATERMARK |
42994 | #define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
42995 | #define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
42996 | #define SDMA3_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
42997 | #define SDMA3_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
42998 | //SDMA3_RLC0_DOORBELL_OFFSET |
42999 | #define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
43000 | #define SDMA3_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
43001 | //SDMA3_RLC0_CSA_ADDR_LO |
43002 | #define SDMA3_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
43003 | #define SDMA3_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43004 | //SDMA3_RLC0_CSA_ADDR_HI |
43005 | #define SDMA3_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
43006 | #define SDMA3_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43007 | //SDMA3_RLC0_IB_SUB_REMAIN |
43008 | #define SDMA3_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
43009 | #define SDMA3_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
43010 | //SDMA3_RLC0_PREEMPT |
43011 | #define SDMA3_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
43012 | #define SDMA3_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
43013 | //SDMA3_RLC0_DUMMY_REG |
43014 | #define SDMA3_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 |
43015 | #define SDMA3_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
43016 | //SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI |
43017 | #define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
43018 | #define SDMA3_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43019 | //SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO |
43020 | #define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
43021 | #define SDMA3_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43022 | //SDMA3_RLC0_RB_AQL_CNTL |
43023 | #define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
43024 | #define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
43025 | #define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
43026 | #define SDMA3_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
43027 | #define SDMA3_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
43028 | #define SDMA3_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
43029 | #define SDMA3_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
43030 | #define SDMA3_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
43031 | #define SDMA3_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
43032 | #define SDMA3_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
43033 | #define SDMA3_RLC0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
43034 | #define SDMA3_RLC0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
43035 | //SDMA3_RLC0_MINOR_PTR_UPDATE |
43036 | #define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
43037 | #define SDMA3_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
43038 | //SDMA3_RLC0_MIDCMD_DATA0 |
43039 | #define SDMA3_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
43040 | #define SDMA3_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
43041 | //SDMA3_RLC0_MIDCMD_DATA1 |
43042 | #define SDMA3_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
43043 | #define SDMA3_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
43044 | //SDMA3_RLC0_MIDCMD_DATA2 |
43045 | #define SDMA3_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
43046 | #define SDMA3_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
43047 | //SDMA3_RLC0_MIDCMD_DATA3 |
43048 | #define SDMA3_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
43049 | #define SDMA3_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
43050 | //SDMA3_RLC0_MIDCMD_DATA4 |
43051 | #define SDMA3_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
43052 | #define SDMA3_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
43053 | //SDMA3_RLC0_MIDCMD_DATA5 |
43054 | #define SDMA3_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
43055 | #define SDMA3_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
43056 | //SDMA3_RLC0_MIDCMD_DATA6 |
43057 | #define SDMA3_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
43058 | #define SDMA3_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
43059 | //SDMA3_RLC0_MIDCMD_DATA7 |
43060 | #define SDMA3_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
43061 | #define SDMA3_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
43062 | //SDMA3_RLC0_MIDCMD_DATA8 |
43063 | #define SDMA3_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
43064 | #define SDMA3_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
43065 | //SDMA3_RLC0_MIDCMD_DATA9 |
43066 | #define SDMA3_RLC0_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
43067 | #define SDMA3_RLC0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
43068 | //SDMA3_RLC0_MIDCMD_DATA10 |
43069 | #define SDMA3_RLC0_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
43070 | #define SDMA3_RLC0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
43071 | //SDMA3_RLC0_MIDCMD_CNTL |
43072 | #define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
43073 | #define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
43074 | #define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
43075 | #define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
43076 | #define SDMA3_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
43077 | #define SDMA3_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
43078 | #define SDMA3_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
43079 | #define SDMA3_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
43080 | //SDMA3_RLC1_RB_CNTL |
43081 | #define SDMA3_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
43082 | #define SDMA3_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 |
43083 | #define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
43084 | #define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
43085 | #define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
43086 | #define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
43087 | #define SDMA3_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 |
43088 | #define SDMA3_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 |
43089 | #define SDMA3_RLC1_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
43090 | #define SDMA3_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
43091 | #define SDMA3_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
43092 | #define SDMA3_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
43093 | #define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
43094 | #define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
43095 | #define SDMA3_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
43096 | #define SDMA3_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L |
43097 | #define SDMA3_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L |
43098 | #define SDMA3_RLC1_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
43099 | //SDMA3_RLC1_RB_BASE |
43100 | #define SDMA3_RLC1_RB_BASE__ADDR__SHIFT 0x0 |
43101 | #define SDMA3_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
43102 | //SDMA3_RLC1_RB_BASE_HI |
43103 | #define SDMA3_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 |
43104 | #define SDMA3_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
43105 | //SDMA3_RLC1_RB_RPTR |
43106 | #define SDMA3_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 |
43107 | #define SDMA3_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
43108 | //SDMA3_RLC1_RB_RPTR_HI |
43109 | #define SDMA3_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
43110 | #define SDMA3_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
43111 | //SDMA3_RLC1_RB_WPTR |
43112 | #define SDMA3_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 |
43113 | #define SDMA3_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
43114 | //SDMA3_RLC1_RB_WPTR_HI |
43115 | #define SDMA3_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
43116 | #define SDMA3_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
43117 | //SDMA3_RLC1_RB_WPTR_POLL_CNTL |
43118 | #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
43119 | #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
43120 | #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
43121 | #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
43122 | #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
43123 | #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
43124 | #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
43125 | #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
43126 | #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
43127 | #define SDMA3_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
43128 | //SDMA3_RLC1_RB_RPTR_ADDR_HI |
43129 | #define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
43130 | #define SDMA3_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43131 | //SDMA3_RLC1_RB_RPTR_ADDR_LO |
43132 | #define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
43133 | #define SDMA3_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43134 | //SDMA3_RLC1_IB_CNTL |
43135 | #define SDMA3_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
43136 | #define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
43137 | #define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
43138 | #define SDMA3_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 |
43139 | #define SDMA3_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
43140 | #define SDMA3_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
43141 | #define SDMA3_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
43142 | #define SDMA3_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
43143 | //SDMA3_RLC1_IB_RPTR |
43144 | #define SDMA3_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 |
43145 | #define SDMA3_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
43146 | //SDMA3_RLC1_IB_OFFSET |
43147 | #define SDMA3_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 |
43148 | #define SDMA3_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
43149 | //SDMA3_RLC1_IB_BASE_LO |
43150 | #define SDMA3_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 |
43151 | #define SDMA3_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
43152 | //SDMA3_RLC1_IB_BASE_HI |
43153 | #define SDMA3_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 |
43154 | #define SDMA3_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
43155 | //SDMA3_RLC1_IB_SIZE |
43156 | #define SDMA3_RLC1_IB_SIZE__SIZE__SHIFT 0x0 |
43157 | #define SDMA3_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL |
43158 | //SDMA3_RLC1_SKIP_CNTL |
43159 | #define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
43160 | #define SDMA3_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
43161 | //SDMA3_RLC1_CONTEXT_STATUS |
43162 | #define SDMA3_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
43163 | #define SDMA3_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
43164 | #define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
43165 | #define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
43166 | #define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
43167 | #define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
43168 | #define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
43169 | #define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
43170 | #define SDMA3_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
43171 | #define SDMA3_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
43172 | #define SDMA3_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
43173 | #define SDMA3_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
43174 | #define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
43175 | #define SDMA3_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
43176 | #define SDMA3_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
43177 | #define SDMA3_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
43178 | //SDMA3_RLC1_DOORBELL |
43179 | #define SDMA3_RLC1_DOORBELL__ENABLE__SHIFT 0x1c |
43180 | #define SDMA3_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e |
43181 | #define SDMA3_RLC1_DOORBELL__ENABLE_MASK 0x10000000L |
43182 | #define SDMA3_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L |
43183 | //SDMA3_RLC1_STATUS |
43184 | #define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
43185 | #define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
43186 | #define SDMA3_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
43187 | #define SDMA3_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
43188 | //SDMA3_RLC1_DOORBELL_LOG |
43189 | #define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
43190 | #define SDMA3_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 |
43191 | #define SDMA3_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
43192 | #define SDMA3_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
43193 | //SDMA3_RLC1_WATERMARK |
43194 | #define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
43195 | #define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
43196 | #define SDMA3_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
43197 | #define SDMA3_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
43198 | //SDMA3_RLC1_DOORBELL_OFFSET |
43199 | #define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
43200 | #define SDMA3_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
43201 | //SDMA3_RLC1_CSA_ADDR_LO |
43202 | #define SDMA3_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
43203 | #define SDMA3_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43204 | //SDMA3_RLC1_CSA_ADDR_HI |
43205 | #define SDMA3_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
43206 | #define SDMA3_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43207 | //SDMA3_RLC1_IB_SUB_REMAIN |
43208 | #define SDMA3_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
43209 | #define SDMA3_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
43210 | //SDMA3_RLC1_PREEMPT |
43211 | #define SDMA3_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
43212 | #define SDMA3_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
43213 | //SDMA3_RLC1_DUMMY_REG |
43214 | #define SDMA3_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 |
43215 | #define SDMA3_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
43216 | //SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI |
43217 | #define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
43218 | #define SDMA3_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43219 | //SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO |
43220 | #define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
43221 | #define SDMA3_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43222 | //SDMA3_RLC1_RB_AQL_CNTL |
43223 | #define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
43224 | #define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
43225 | #define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
43226 | #define SDMA3_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
43227 | #define SDMA3_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
43228 | #define SDMA3_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
43229 | #define SDMA3_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
43230 | #define SDMA3_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
43231 | #define SDMA3_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
43232 | #define SDMA3_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
43233 | #define SDMA3_RLC1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
43234 | #define SDMA3_RLC1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
43235 | //SDMA3_RLC1_MINOR_PTR_UPDATE |
43236 | #define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
43237 | #define SDMA3_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
43238 | //SDMA3_RLC1_MIDCMD_DATA0 |
43239 | #define SDMA3_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
43240 | #define SDMA3_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
43241 | //SDMA3_RLC1_MIDCMD_DATA1 |
43242 | #define SDMA3_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
43243 | #define SDMA3_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
43244 | //SDMA3_RLC1_MIDCMD_DATA2 |
43245 | #define SDMA3_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
43246 | #define SDMA3_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
43247 | //SDMA3_RLC1_MIDCMD_DATA3 |
43248 | #define SDMA3_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
43249 | #define SDMA3_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
43250 | //SDMA3_RLC1_MIDCMD_DATA4 |
43251 | #define SDMA3_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
43252 | #define SDMA3_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
43253 | //SDMA3_RLC1_MIDCMD_DATA5 |
43254 | #define SDMA3_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
43255 | #define SDMA3_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
43256 | //SDMA3_RLC1_MIDCMD_DATA6 |
43257 | #define SDMA3_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
43258 | #define SDMA3_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
43259 | //SDMA3_RLC1_MIDCMD_DATA7 |
43260 | #define SDMA3_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
43261 | #define SDMA3_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
43262 | //SDMA3_RLC1_MIDCMD_DATA8 |
43263 | #define SDMA3_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
43264 | #define SDMA3_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
43265 | //SDMA3_RLC1_MIDCMD_DATA9 |
43266 | #define SDMA3_RLC1_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
43267 | #define SDMA3_RLC1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
43268 | //SDMA3_RLC1_MIDCMD_DATA10 |
43269 | #define SDMA3_RLC1_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
43270 | #define SDMA3_RLC1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
43271 | //SDMA3_RLC1_MIDCMD_CNTL |
43272 | #define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
43273 | #define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
43274 | #define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
43275 | #define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
43276 | #define SDMA3_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
43277 | #define SDMA3_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
43278 | #define SDMA3_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
43279 | #define SDMA3_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
43280 | //SDMA3_RLC2_RB_CNTL |
43281 | #define SDMA3_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
43282 | #define SDMA3_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 |
43283 | #define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
43284 | #define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
43285 | #define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
43286 | #define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
43287 | #define SDMA3_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 |
43288 | #define SDMA3_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 |
43289 | #define SDMA3_RLC2_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
43290 | #define SDMA3_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
43291 | #define SDMA3_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
43292 | #define SDMA3_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
43293 | #define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
43294 | #define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
43295 | #define SDMA3_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
43296 | #define SDMA3_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L |
43297 | #define SDMA3_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L |
43298 | #define SDMA3_RLC2_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
43299 | //SDMA3_RLC2_RB_BASE |
43300 | #define SDMA3_RLC2_RB_BASE__ADDR__SHIFT 0x0 |
43301 | #define SDMA3_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
43302 | //SDMA3_RLC2_RB_BASE_HI |
43303 | #define SDMA3_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 |
43304 | #define SDMA3_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
43305 | //SDMA3_RLC2_RB_RPTR |
43306 | #define SDMA3_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 |
43307 | #define SDMA3_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
43308 | //SDMA3_RLC2_RB_RPTR_HI |
43309 | #define SDMA3_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
43310 | #define SDMA3_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
43311 | //SDMA3_RLC2_RB_WPTR |
43312 | #define SDMA3_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 |
43313 | #define SDMA3_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
43314 | //SDMA3_RLC2_RB_WPTR_HI |
43315 | #define SDMA3_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
43316 | #define SDMA3_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
43317 | //SDMA3_RLC2_RB_WPTR_POLL_CNTL |
43318 | #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
43319 | #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
43320 | #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
43321 | #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
43322 | #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
43323 | #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
43324 | #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
43325 | #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
43326 | #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
43327 | #define SDMA3_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
43328 | //SDMA3_RLC2_RB_RPTR_ADDR_HI |
43329 | #define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
43330 | #define SDMA3_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43331 | //SDMA3_RLC2_RB_RPTR_ADDR_LO |
43332 | #define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
43333 | #define SDMA3_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43334 | //SDMA3_RLC2_IB_CNTL |
43335 | #define SDMA3_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
43336 | #define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
43337 | #define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
43338 | #define SDMA3_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 |
43339 | #define SDMA3_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
43340 | #define SDMA3_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
43341 | #define SDMA3_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
43342 | #define SDMA3_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
43343 | //SDMA3_RLC2_IB_RPTR |
43344 | #define SDMA3_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 |
43345 | #define SDMA3_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
43346 | //SDMA3_RLC2_IB_OFFSET |
43347 | #define SDMA3_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 |
43348 | #define SDMA3_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
43349 | //SDMA3_RLC2_IB_BASE_LO |
43350 | #define SDMA3_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 |
43351 | #define SDMA3_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
43352 | //SDMA3_RLC2_IB_BASE_HI |
43353 | #define SDMA3_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 |
43354 | #define SDMA3_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
43355 | //SDMA3_RLC2_IB_SIZE |
43356 | #define SDMA3_RLC2_IB_SIZE__SIZE__SHIFT 0x0 |
43357 | #define SDMA3_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL |
43358 | //SDMA3_RLC2_SKIP_CNTL |
43359 | #define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
43360 | #define SDMA3_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
43361 | //SDMA3_RLC2_CONTEXT_STATUS |
43362 | #define SDMA3_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
43363 | #define SDMA3_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
43364 | #define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
43365 | #define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
43366 | #define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
43367 | #define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
43368 | #define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
43369 | #define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
43370 | #define SDMA3_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
43371 | #define SDMA3_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
43372 | #define SDMA3_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
43373 | #define SDMA3_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
43374 | #define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
43375 | #define SDMA3_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
43376 | #define SDMA3_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
43377 | #define SDMA3_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
43378 | //SDMA3_RLC2_DOORBELL |
43379 | #define SDMA3_RLC2_DOORBELL__ENABLE__SHIFT 0x1c |
43380 | #define SDMA3_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e |
43381 | #define SDMA3_RLC2_DOORBELL__ENABLE_MASK 0x10000000L |
43382 | #define SDMA3_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L |
43383 | //SDMA3_RLC2_STATUS |
43384 | #define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
43385 | #define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
43386 | #define SDMA3_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
43387 | #define SDMA3_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
43388 | //SDMA3_RLC2_DOORBELL_LOG |
43389 | #define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
43390 | #define SDMA3_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 |
43391 | #define SDMA3_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
43392 | #define SDMA3_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
43393 | //SDMA3_RLC2_WATERMARK |
43394 | #define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
43395 | #define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
43396 | #define SDMA3_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
43397 | #define SDMA3_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
43398 | //SDMA3_RLC2_DOORBELL_OFFSET |
43399 | #define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
43400 | #define SDMA3_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
43401 | //SDMA3_RLC2_CSA_ADDR_LO |
43402 | #define SDMA3_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
43403 | #define SDMA3_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43404 | //SDMA3_RLC2_CSA_ADDR_HI |
43405 | #define SDMA3_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
43406 | #define SDMA3_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43407 | //SDMA3_RLC2_IB_SUB_REMAIN |
43408 | #define SDMA3_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
43409 | #define SDMA3_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
43410 | //SDMA3_RLC2_PREEMPT |
43411 | #define SDMA3_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
43412 | #define SDMA3_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
43413 | //SDMA3_RLC2_DUMMY_REG |
43414 | #define SDMA3_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 |
43415 | #define SDMA3_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
43416 | //SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI |
43417 | #define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
43418 | #define SDMA3_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43419 | //SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO |
43420 | #define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
43421 | #define SDMA3_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43422 | //SDMA3_RLC2_RB_AQL_CNTL |
43423 | #define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
43424 | #define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
43425 | #define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
43426 | #define SDMA3_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
43427 | #define SDMA3_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
43428 | #define SDMA3_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
43429 | #define SDMA3_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
43430 | #define SDMA3_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
43431 | #define SDMA3_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
43432 | #define SDMA3_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
43433 | #define SDMA3_RLC2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
43434 | #define SDMA3_RLC2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
43435 | //SDMA3_RLC2_MINOR_PTR_UPDATE |
43436 | #define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
43437 | #define SDMA3_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
43438 | //SDMA3_RLC2_MIDCMD_DATA0 |
43439 | #define SDMA3_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
43440 | #define SDMA3_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
43441 | //SDMA3_RLC2_MIDCMD_DATA1 |
43442 | #define SDMA3_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
43443 | #define SDMA3_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
43444 | //SDMA3_RLC2_MIDCMD_DATA2 |
43445 | #define SDMA3_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
43446 | #define SDMA3_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
43447 | //SDMA3_RLC2_MIDCMD_DATA3 |
43448 | #define SDMA3_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
43449 | #define SDMA3_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
43450 | //SDMA3_RLC2_MIDCMD_DATA4 |
43451 | #define SDMA3_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
43452 | #define SDMA3_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
43453 | //SDMA3_RLC2_MIDCMD_DATA5 |
43454 | #define SDMA3_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
43455 | #define SDMA3_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
43456 | //SDMA3_RLC2_MIDCMD_DATA6 |
43457 | #define SDMA3_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
43458 | #define SDMA3_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
43459 | //SDMA3_RLC2_MIDCMD_DATA7 |
43460 | #define SDMA3_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
43461 | #define SDMA3_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
43462 | //SDMA3_RLC2_MIDCMD_DATA8 |
43463 | #define SDMA3_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
43464 | #define SDMA3_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
43465 | //SDMA3_RLC2_MIDCMD_DATA9 |
43466 | #define SDMA3_RLC2_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
43467 | #define SDMA3_RLC2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
43468 | //SDMA3_RLC2_MIDCMD_DATA10 |
43469 | #define SDMA3_RLC2_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
43470 | #define SDMA3_RLC2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
43471 | //SDMA3_RLC2_MIDCMD_CNTL |
43472 | #define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
43473 | #define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
43474 | #define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
43475 | #define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
43476 | #define SDMA3_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
43477 | #define SDMA3_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
43478 | #define SDMA3_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
43479 | #define SDMA3_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
43480 | //SDMA3_RLC3_RB_CNTL |
43481 | #define SDMA3_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
43482 | #define SDMA3_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 |
43483 | #define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
43484 | #define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
43485 | #define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
43486 | #define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
43487 | #define SDMA3_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 |
43488 | #define SDMA3_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 |
43489 | #define SDMA3_RLC3_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
43490 | #define SDMA3_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
43491 | #define SDMA3_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
43492 | #define SDMA3_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
43493 | #define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
43494 | #define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
43495 | #define SDMA3_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
43496 | #define SDMA3_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L |
43497 | #define SDMA3_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L |
43498 | #define SDMA3_RLC3_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
43499 | //SDMA3_RLC3_RB_BASE |
43500 | #define SDMA3_RLC3_RB_BASE__ADDR__SHIFT 0x0 |
43501 | #define SDMA3_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
43502 | //SDMA3_RLC3_RB_BASE_HI |
43503 | #define SDMA3_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 |
43504 | #define SDMA3_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
43505 | //SDMA3_RLC3_RB_RPTR |
43506 | #define SDMA3_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 |
43507 | #define SDMA3_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
43508 | //SDMA3_RLC3_RB_RPTR_HI |
43509 | #define SDMA3_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
43510 | #define SDMA3_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
43511 | //SDMA3_RLC3_RB_WPTR |
43512 | #define SDMA3_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 |
43513 | #define SDMA3_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
43514 | //SDMA3_RLC3_RB_WPTR_HI |
43515 | #define SDMA3_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
43516 | #define SDMA3_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
43517 | //SDMA3_RLC3_RB_WPTR_POLL_CNTL |
43518 | #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
43519 | #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
43520 | #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
43521 | #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
43522 | #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
43523 | #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
43524 | #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
43525 | #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
43526 | #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
43527 | #define SDMA3_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
43528 | //SDMA3_RLC3_RB_RPTR_ADDR_HI |
43529 | #define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
43530 | #define SDMA3_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43531 | //SDMA3_RLC3_RB_RPTR_ADDR_LO |
43532 | #define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
43533 | #define SDMA3_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43534 | //SDMA3_RLC3_IB_CNTL |
43535 | #define SDMA3_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
43536 | #define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
43537 | #define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
43538 | #define SDMA3_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 |
43539 | #define SDMA3_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
43540 | #define SDMA3_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
43541 | #define SDMA3_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
43542 | #define SDMA3_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
43543 | //SDMA3_RLC3_IB_RPTR |
43544 | #define SDMA3_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 |
43545 | #define SDMA3_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
43546 | //SDMA3_RLC3_IB_OFFSET |
43547 | #define SDMA3_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 |
43548 | #define SDMA3_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
43549 | //SDMA3_RLC3_IB_BASE_LO |
43550 | #define SDMA3_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 |
43551 | #define SDMA3_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
43552 | //SDMA3_RLC3_IB_BASE_HI |
43553 | #define SDMA3_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 |
43554 | #define SDMA3_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
43555 | //SDMA3_RLC3_IB_SIZE |
43556 | #define SDMA3_RLC3_IB_SIZE__SIZE__SHIFT 0x0 |
43557 | #define SDMA3_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL |
43558 | //SDMA3_RLC3_SKIP_CNTL |
43559 | #define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
43560 | #define SDMA3_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
43561 | //SDMA3_RLC3_CONTEXT_STATUS |
43562 | #define SDMA3_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
43563 | #define SDMA3_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
43564 | #define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
43565 | #define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
43566 | #define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
43567 | #define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
43568 | #define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
43569 | #define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
43570 | #define SDMA3_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
43571 | #define SDMA3_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
43572 | #define SDMA3_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
43573 | #define SDMA3_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
43574 | #define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
43575 | #define SDMA3_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
43576 | #define SDMA3_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
43577 | #define SDMA3_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
43578 | //SDMA3_RLC3_DOORBELL |
43579 | #define SDMA3_RLC3_DOORBELL__ENABLE__SHIFT 0x1c |
43580 | #define SDMA3_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e |
43581 | #define SDMA3_RLC3_DOORBELL__ENABLE_MASK 0x10000000L |
43582 | #define SDMA3_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L |
43583 | //SDMA3_RLC3_STATUS |
43584 | #define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
43585 | #define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
43586 | #define SDMA3_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
43587 | #define SDMA3_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
43588 | //SDMA3_RLC3_DOORBELL_LOG |
43589 | #define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
43590 | #define SDMA3_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 |
43591 | #define SDMA3_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
43592 | #define SDMA3_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
43593 | //SDMA3_RLC3_WATERMARK |
43594 | #define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
43595 | #define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
43596 | #define SDMA3_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
43597 | #define SDMA3_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
43598 | //SDMA3_RLC3_DOORBELL_OFFSET |
43599 | #define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
43600 | #define SDMA3_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
43601 | //SDMA3_RLC3_CSA_ADDR_LO |
43602 | #define SDMA3_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
43603 | #define SDMA3_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43604 | //SDMA3_RLC3_CSA_ADDR_HI |
43605 | #define SDMA3_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
43606 | #define SDMA3_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43607 | //SDMA3_RLC3_IB_SUB_REMAIN |
43608 | #define SDMA3_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
43609 | #define SDMA3_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
43610 | //SDMA3_RLC3_PREEMPT |
43611 | #define SDMA3_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
43612 | #define SDMA3_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
43613 | //SDMA3_RLC3_DUMMY_REG |
43614 | #define SDMA3_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 |
43615 | #define SDMA3_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
43616 | //SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI |
43617 | #define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
43618 | #define SDMA3_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43619 | //SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO |
43620 | #define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
43621 | #define SDMA3_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43622 | //SDMA3_RLC3_RB_AQL_CNTL |
43623 | #define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
43624 | #define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
43625 | #define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
43626 | #define SDMA3_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
43627 | #define SDMA3_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
43628 | #define SDMA3_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
43629 | #define SDMA3_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
43630 | #define SDMA3_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
43631 | #define SDMA3_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
43632 | #define SDMA3_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
43633 | #define SDMA3_RLC3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
43634 | #define SDMA3_RLC3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
43635 | //SDMA3_RLC3_MINOR_PTR_UPDATE |
43636 | #define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
43637 | #define SDMA3_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
43638 | //SDMA3_RLC3_MIDCMD_DATA0 |
43639 | #define SDMA3_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
43640 | #define SDMA3_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
43641 | //SDMA3_RLC3_MIDCMD_DATA1 |
43642 | #define SDMA3_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
43643 | #define SDMA3_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
43644 | //SDMA3_RLC3_MIDCMD_DATA2 |
43645 | #define SDMA3_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
43646 | #define SDMA3_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
43647 | //SDMA3_RLC3_MIDCMD_DATA3 |
43648 | #define SDMA3_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
43649 | #define SDMA3_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
43650 | //SDMA3_RLC3_MIDCMD_DATA4 |
43651 | #define SDMA3_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
43652 | #define SDMA3_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
43653 | //SDMA3_RLC3_MIDCMD_DATA5 |
43654 | #define SDMA3_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
43655 | #define SDMA3_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
43656 | //SDMA3_RLC3_MIDCMD_DATA6 |
43657 | #define SDMA3_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
43658 | #define SDMA3_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
43659 | //SDMA3_RLC3_MIDCMD_DATA7 |
43660 | #define SDMA3_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
43661 | #define SDMA3_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
43662 | //SDMA3_RLC3_MIDCMD_DATA8 |
43663 | #define SDMA3_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
43664 | #define SDMA3_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
43665 | //SDMA3_RLC3_MIDCMD_DATA9 |
43666 | #define SDMA3_RLC3_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
43667 | #define SDMA3_RLC3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
43668 | //SDMA3_RLC3_MIDCMD_DATA10 |
43669 | #define SDMA3_RLC3_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
43670 | #define SDMA3_RLC3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
43671 | //SDMA3_RLC3_MIDCMD_CNTL |
43672 | #define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
43673 | #define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
43674 | #define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
43675 | #define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
43676 | #define SDMA3_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
43677 | #define SDMA3_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
43678 | #define SDMA3_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
43679 | #define SDMA3_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
43680 | //SDMA3_RLC4_RB_CNTL |
43681 | #define SDMA3_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
43682 | #define SDMA3_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 |
43683 | #define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
43684 | #define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
43685 | #define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
43686 | #define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
43687 | #define SDMA3_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 |
43688 | #define SDMA3_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 |
43689 | #define SDMA3_RLC4_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
43690 | #define SDMA3_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
43691 | #define SDMA3_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
43692 | #define SDMA3_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
43693 | #define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
43694 | #define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
43695 | #define SDMA3_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
43696 | #define SDMA3_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L |
43697 | #define SDMA3_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L |
43698 | #define SDMA3_RLC4_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
43699 | //SDMA3_RLC4_RB_BASE |
43700 | #define SDMA3_RLC4_RB_BASE__ADDR__SHIFT 0x0 |
43701 | #define SDMA3_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
43702 | //SDMA3_RLC4_RB_BASE_HI |
43703 | #define SDMA3_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 |
43704 | #define SDMA3_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
43705 | //SDMA3_RLC4_RB_RPTR |
43706 | #define SDMA3_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 |
43707 | #define SDMA3_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
43708 | //SDMA3_RLC4_RB_RPTR_HI |
43709 | #define SDMA3_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
43710 | #define SDMA3_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
43711 | //SDMA3_RLC4_RB_WPTR |
43712 | #define SDMA3_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 |
43713 | #define SDMA3_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
43714 | //SDMA3_RLC4_RB_WPTR_HI |
43715 | #define SDMA3_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
43716 | #define SDMA3_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
43717 | //SDMA3_RLC4_RB_WPTR_POLL_CNTL |
43718 | #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
43719 | #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
43720 | #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
43721 | #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
43722 | #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
43723 | #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
43724 | #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
43725 | #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
43726 | #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
43727 | #define SDMA3_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
43728 | //SDMA3_RLC4_RB_RPTR_ADDR_HI |
43729 | #define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
43730 | #define SDMA3_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43731 | //SDMA3_RLC4_RB_RPTR_ADDR_LO |
43732 | #define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
43733 | #define SDMA3_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43734 | //SDMA3_RLC4_IB_CNTL |
43735 | #define SDMA3_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
43736 | #define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
43737 | #define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
43738 | #define SDMA3_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 |
43739 | #define SDMA3_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
43740 | #define SDMA3_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
43741 | #define SDMA3_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
43742 | #define SDMA3_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
43743 | //SDMA3_RLC4_IB_RPTR |
43744 | #define SDMA3_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 |
43745 | #define SDMA3_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
43746 | //SDMA3_RLC4_IB_OFFSET |
43747 | #define SDMA3_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 |
43748 | #define SDMA3_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
43749 | //SDMA3_RLC4_IB_BASE_LO |
43750 | #define SDMA3_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 |
43751 | #define SDMA3_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
43752 | //SDMA3_RLC4_IB_BASE_HI |
43753 | #define SDMA3_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 |
43754 | #define SDMA3_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
43755 | //SDMA3_RLC4_IB_SIZE |
43756 | #define SDMA3_RLC4_IB_SIZE__SIZE__SHIFT 0x0 |
43757 | #define SDMA3_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL |
43758 | //SDMA3_RLC4_SKIP_CNTL |
43759 | #define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
43760 | #define SDMA3_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
43761 | //SDMA3_RLC4_CONTEXT_STATUS |
43762 | #define SDMA3_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
43763 | #define SDMA3_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
43764 | #define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
43765 | #define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
43766 | #define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
43767 | #define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
43768 | #define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
43769 | #define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
43770 | #define SDMA3_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
43771 | #define SDMA3_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
43772 | #define SDMA3_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
43773 | #define SDMA3_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
43774 | #define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
43775 | #define SDMA3_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
43776 | #define SDMA3_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
43777 | #define SDMA3_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
43778 | //SDMA3_RLC4_DOORBELL |
43779 | #define SDMA3_RLC4_DOORBELL__ENABLE__SHIFT 0x1c |
43780 | #define SDMA3_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e |
43781 | #define SDMA3_RLC4_DOORBELL__ENABLE_MASK 0x10000000L |
43782 | #define SDMA3_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L |
43783 | //SDMA3_RLC4_STATUS |
43784 | #define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
43785 | #define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
43786 | #define SDMA3_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
43787 | #define SDMA3_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
43788 | //SDMA3_RLC4_DOORBELL_LOG |
43789 | #define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
43790 | #define SDMA3_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 |
43791 | #define SDMA3_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
43792 | #define SDMA3_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
43793 | //SDMA3_RLC4_WATERMARK |
43794 | #define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
43795 | #define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
43796 | #define SDMA3_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
43797 | #define SDMA3_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
43798 | //SDMA3_RLC4_DOORBELL_OFFSET |
43799 | #define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
43800 | #define SDMA3_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
43801 | //SDMA3_RLC4_CSA_ADDR_LO |
43802 | #define SDMA3_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
43803 | #define SDMA3_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43804 | //SDMA3_RLC4_CSA_ADDR_HI |
43805 | #define SDMA3_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
43806 | #define SDMA3_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43807 | //SDMA3_RLC4_IB_SUB_REMAIN |
43808 | #define SDMA3_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
43809 | #define SDMA3_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
43810 | //SDMA3_RLC4_PREEMPT |
43811 | #define SDMA3_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
43812 | #define SDMA3_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
43813 | //SDMA3_RLC4_DUMMY_REG |
43814 | #define SDMA3_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 |
43815 | #define SDMA3_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
43816 | //SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI |
43817 | #define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
43818 | #define SDMA3_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43819 | //SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO |
43820 | #define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
43821 | #define SDMA3_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43822 | //SDMA3_RLC4_RB_AQL_CNTL |
43823 | #define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
43824 | #define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
43825 | #define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
43826 | #define SDMA3_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
43827 | #define SDMA3_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
43828 | #define SDMA3_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
43829 | #define SDMA3_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
43830 | #define SDMA3_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
43831 | #define SDMA3_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
43832 | #define SDMA3_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
43833 | #define SDMA3_RLC4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
43834 | #define SDMA3_RLC4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
43835 | //SDMA3_RLC4_MINOR_PTR_UPDATE |
43836 | #define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
43837 | #define SDMA3_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
43838 | //SDMA3_RLC4_MIDCMD_DATA0 |
43839 | #define SDMA3_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
43840 | #define SDMA3_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
43841 | //SDMA3_RLC4_MIDCMD_DATA1 |
43842 | #define SDMA3_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
43843 | #define SDMA3_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
43844 | //SDMA3_RLC4_MIDCMD_DATA2 |
43845 | #define SDMA3_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
43846 | #define SDMA3_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
43847 | //SDMA3_RLC4_MIDCMD_DATA3 |
43848 | #define SDMA3_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
43849 | #define SDMA3_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
43850 | //SDMA3_RLC4_MIDCMD_DATA4 |
43851 | #define SDMA3_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
43852 | #define SDMA3_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
43853 | //SDMA3_RLC4_MIDCMD_DATA5 |
43854 | #define SDMA3_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
43855 | #define SDMA3_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
43856 | //SDMA3_RLC4_MIDCMD_DATA6 |
43857 | #define SDMA3_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
43858 | #define SDMA3_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
43859 | //SDMA3_RLC4_MIDCMD_DATA7 |
43860 | #define SDMA3_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
43861 | #define SDMA3_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
43862 | //SDMA3_RLC4_MIDCMD_DATA8 |
43863 | #define SDMA3_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
43864 | #define SDMA3_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
43865 | //SDMA3_RLC4_MIDCMD_DATA9 |
43866 | #define SDMA3_RLC4_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
43867 | #define SDMA3_RLC4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
43868 | //SDMA3_RLC4_MIDCMD_DATA10 |
43869 | #define SDMA3_RLC4_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
43870 | #define SDMA3_RLC4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
43871 | //SDMA3_RLC4_MIDCMD_CNTL |
43872 | #define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
43873 | #define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
43874 | #define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
43875 | #define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
43876 | #define SDMA3_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
43877 | #define SDMA3_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
43878 | #define SDMA3_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
43879 | #define SDMA3_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
43880 | //SDMA3_RLC5_RB_CNTL |
43881 | #define SDMA3_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
43882 | #define SDMA3_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 |
43883 | #define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
43884 | #define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
43885 | #define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
43886 | #define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
43887 | #define SDMA3_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 |
43888 | #define SDMA3_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 |
43889 | #define SDMA3_RLC5_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
43890 | #define SDMA3_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
43891 | #define SDMA3_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
43892 | #define SDMA3_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
43893 | #define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
43894 | #define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
43895 | #define SDMA3_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
43896 | #define SDMA3_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L |
43897 | #define SDMA3_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L |
43898 | #define SDMA3_RLC5_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
43899 | //SDMA3_RLC5_RB_BASE |
43900 | #define SDMA3_RLC5_RB_BASE__ADDR__SHIFT 0x0 |
43901 | #define SDMA3_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
43902 | //SDMA3_RLC5_RB_BASE_HI |
43903 | #define SDMA3_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 |
43904 | #define SDMA3_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
43905 | //SDMA3_RLC5_RB_RPTR |
43906 | #define SDMA3_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 |
43907 | #define SDMA3_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
43908 | //SDMA3_RLC5_RB_RPTR_HI |
43909 | #define SDMA3_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
43910 | #define SDMA3_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
43911 | //SDMA3_RLC5_RB_WPTR |
43912 | #define SDMA3_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 |
43913 | #define SDMA3_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
43914 | //SDMA3_RLC5_RB_WPTR_HI |
43915 | #define SDMA3_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
43916 | #define SDMA3_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
43917 | //SDMA3_RLC5_RB_WPTR_POLL_CNTL |
43918 | #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
43919 | #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
43920 | #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
43921 | #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
43922 | #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
43923 | #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
43924 | #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
43925 | #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
43926 | #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
43927 | #define SDMA3_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
43928 | //SDMA3_RLC5_RB_RPTR_ADDR_HI |
43929 | #define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
43930 | #define SDMA3_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
43931 | //SDMA3_RLC5_RB_RPTR_ADDR_LO |
43932 | #define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
43933 | #define SDMA3_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
43934 | //SDMA3_RLC5_IB_CNTL |
43935 | #define SDMA3_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
43936 | #define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
43937 | #define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
43938 | #define SDMA3_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 |
43939 | #define SDMA3_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
43940 | #define SDMA3_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
43941 | #define SDMA3_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
43942 | #define SDMA3_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
43943 | //SDMA3_RLC5_IB_RPTR |
43944 | #define SDMA3_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 |
43945 | #define SDMA3_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
43946 | //SDMA3_RLC5_IB_OFFSET |
43947 | #define SDMA3_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 |
43948 | #define SDMA3_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
43949 | //SDMA3_RLC5_IB_BASE_LO |
43950 | #define SDMA3_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 |
43951 | #define SDMA3_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
43952 | //SDMA3_RLC5_IB_BASE_HI |
43953 | #define SDMA3_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 |
43954 | #define SDMA3_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
43955 | //SDMA3_RLC5_IB_SIZE |
43956 | #define SDMA3_RLC5_IB_SIZE__SIZE__SHIFT 0x0 |
43957 | #define SDMA3_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL |
43958 | //SDMA3_RLC5_SKIP_CNTL |
43959 | #define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
43960 | #define SDMA3_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
43961 | //SDMA3_RLC5_CONTEXT_STATUS |
43962 | #define SDMA3_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
43963 | #define SDMA3_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
43964 | #define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
43965 | #define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
43966 | #define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
43967 | #define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
43968 | #define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
43969 | #define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
43970 | #define SDMA3_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
43971 | #define SDMA3_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
43972 | #define SDMA3_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
43973 | #define SDMA3_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
43974 | #define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
43975 | #define SDMA3_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
43976 | #define SDMA3_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
43977 | #define SDMA3_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
43978 | //SDMA3_RLC5_DOORBELL |
43979 | #define SDMA3_RLC5_DOORBELL__ENABLE__SHIFT 0x1c |
43980 | #define SDMA3_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e |
43981 | #define SDMA3_RLC5_DOORBELL__ENABLE_MASK 0x10000000L |
43982 | #define SDMA3_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L |
43983 | //SDMA3_RLC5_STATUS |
43984 | #define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
43985 | #define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
43986 | #define SDMA3_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
43987 | #define SDMA3_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
43988 | //SDMA3_RLC5_DOORBELL_LOG |
43989 | #define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
43990 | #define SDMA3_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 |
43991 | #define SDMA3_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
43992 | #define SDMA3_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
43993 | //SDMA3_RLC5_WATERMARK |
43994 | #define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
43995 | #define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
43996 | #define SDMA3_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
43997 | #define SDMA3_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
43998 | //SDMA3_RLC5_DOORBELL_OFFSET |
43999 | #define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
44000 | #define SDMA3_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
44001 | //SDMA3_RLC5_CSA_ADDR_LO |
44002 | #define SDMA3_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
44003 | #define SDMA3_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
44004 | //SDMA3_RLC5_CSA_ADDR_HI |
44005 | #define SDMA3_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
44006 | #define SDMA3_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
44007 | //SDMA3_RLC5_IB_SUB_REMAIN |
44008 | #define SDMA3_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
44009 | #define SDMA3_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
44010 | //SDMA3_RLC5_PREEMPT |
44011 | #define SDMA3_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
44012 | #define SDMA3_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
44013 | //SDMA3_RLC5_DUMMY_REG |
44014 | #define SDMA3_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 |
44015 | #define SDMA3_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
44016 | //SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI |
44017 | #define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
44018 | #define SDMA3_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
44019 | //SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO |
44020 | #define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
44021 | #define SDMA3_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
44022 | //SDMA3_RLC5_RB_AQL_CNTL |
44023 | #define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
44024 | #define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
44025 | #define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
44026 | #define SDMA3_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
44027 | #define SDMA3_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
44028 | #define SDMA3_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
44029 | #define SDMA3_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
44030 | #define SDMA3_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
44031 | #define SDMA3_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
44032 | #define SDMA3_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
44033 | #define SDMA3_RLC5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
44034 | #define SDMA3_RLC5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
44035 | //SDMA3_RLC5_MINOR_PTR_UPDATE |
44036 | #define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
44037 | #define SDMA3_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
44038 | //SDMA3_RLC5_MIDCMD_DATA0 |
44039 | #define SDMA3_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
44040 | #define SDMA3_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
44041 | //SDMA3_RLC5_MIDCMD_DATA1 |
44042 | #define SDMA3_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
44043 | #define SDMA3_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
44044 | //SDMA3_RLC5_MIDCMD_DATA2 |
44045 | #define SDMA3_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
44046 | #define SDMA3_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
44047 | //SDMA3_RLC5_MIDCMD_DATA3 |
44048 | #define SDMA3_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
44049 | #define SDMA3_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
44050 | //SDMA3_RLC5_MIDCMD_DATA4 |
44051 | #define SDMA3_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
44052 | #define SDMA3_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
44053 | //SDMA3_RLC5_MIDCMD_DATA5 |
44054 | #define SDMA3_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
44055 | #define SDMA3_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
44056 | //SDMA3_RLC5_MIDCMD_DATA6 |
44057 | #define SDMA3_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
44058 | #define SDMA3_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
44059 | //SDMA3_RLC5_MIDCMD_DATA7 |
44060 | #define SDMA3_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
44061 | #define SDMA3_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
44062 | //SDMA3_RLC5_MIDCMD_DATA8 |
44063 | #define SDMA3_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
44064 | #define SDMA3_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
44065 | //SDMA3_RLC5_MIDCMD_DATA9 |
44066 | #define SDMA3_RLC5_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
44067 | #define SDMA3_RLC5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
44068 | //SDMA3_RLC5_MIDCMD_DATA10 |
44069 | #define SDMA3_RLC5_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
44070 | #define SDMA3_RLC5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
44071 | //SDMA3_RLC5_MIDCMD_CNTL |
44072 | #define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
44073 | #define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
44074 | #define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
44075 | #define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
44076 | #define SDMA3_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
44077 | #define SDMA3_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
44078 | #define SDMA3_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
44079 | #define SDMA3_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
44080 | //SDMA3_RLC6_RB_CNTL |
44081 | #define SDMA3_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
44082 | #define SDMA3_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 |
44083 | #define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
44084 | #define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
44085 | #define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
44086 | #define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
44087 | #define SDMA3_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 |
44088 | #define SDMA3_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 |
44089 | #define SDMA3_RLC6_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
44090 | #define SDMA3_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
44091 | #define SDMA3_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
44092 | #define SDMA3_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
44093 | #define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
44094 | #define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
44095 | #define SDMA3_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
44096 | #define SDMA3_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L |
44097 | #define SDMA3_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L |
44098 | #define SDMA3_RLC6_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
44099 | //SDMA3_RLC6_RB_BASE |
44100 | #define SDMA3_RLC6_RB_BASE__ADDR__SHIFT 0x0 |
44101 | #define SDMA3_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
44102 | //SDMA3_RLC6_RB_BASE_HI |
44103 | #define SDMA3_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 |
44104 | #define SDMA3_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
44105 | //SDMA3_RLC6_RB_RPTR |
44106 | #define SDMA3_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 |
44107 | #define SDMA3_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
44108 | //SDMA3_RLC6_RB_RPTR_HI |
44109 | #define SDMA3_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
44110 | #define SDMA3_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
44111 | //SDMA3_RLC6_RB_WPTR |
44112 | #define SDMA3_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 |
44113 | #define SDMA3_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
44114 | //SDMA3_RLC6_RB_WPTR_HI |
44115 | #define SDMA3_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
44116 | #define SDMA3_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
44117 | //SDMA3_RLC6_RB_WPTR_POLL_CNTL |
44118 | #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
44119 | #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
44120 | #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
44121 | #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
44122 | #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
44123 | #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
44124 | #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
44125 | #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
44126 | #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
44127 | #define SDMA3_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
44128 | //SDMA3_RLC6_RB_RPTR_ADDR_HI |
44129 | #define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
44130 | #define SDMA3_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
44131 | //SDMA3_RLC6_RB_RPTR_ADDR_LO |
44132 | #define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
44133 | #define SDMA3_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
44134 | //SDMA3_RLC6_IB_CNTL |
44135 | #define SDMA3_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
44136 | #define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
44137 | #define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
44138 | #define SDMA3_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 |
44139 | #define SDMA3_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
44140 | #define SDMA3_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
44141 | #define SDMA3_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
44142 | #define SDMA3_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
44143 | //SDMA3_RLC6_IB_RPTR |
44144 | #define SDMA3_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 |
44145 | #define SDMA3_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
44146 | //SDMA3_RLC6_IB_OFFSET |
44147 | #define SDMA3_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 |
44148 | #define SDMA3_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
44149 | //SDMA3_RLC6_IB_BASE_LO |
44150 | #define SDMA3_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 |
44151 | #define SDMA3_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
44152 | //SDMA3_RLC6_IB_BASE_HI |
44153 | #define SDMA3_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 |
44154 | #define SDMA3_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
44155 | //SDMA3_RLC6_IB_SIZE |
44156 | #define SDMA3_RLC6_IB_SIZE__SIZE__SHIFT 0x0 |
44157 | #define SDMA3_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL |
44158 | //SDMA3_RLC6_SKIP_CNTL |
44159 | #define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
44160 | #define SDMA3_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
44161 | //SDMA3_RLC6_CONTEXT_STATUS |
44162 | #define SDMA3_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
44163 | #define SDMA3_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
44164 | #define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
44165 | #define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
44166 | #define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
44167 | #define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
44168 | #define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
44169 | #define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
44170 | #define SDMA3_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
44171 | #define SDMA3_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
44172 | #define SDMA3_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
44173 | #define SDMA3_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
44174 | #define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
44175 | #define SDMA3_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
44176 | #define SDMA3_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
44177 | #define SDMA3_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
44178 | //SDMA3_RLC6_DOORBELL |
44179 | #define SDMA3_RLC6_DOORBELL__ENABLE__SHIFT 0x1c |
44180 | #define SDMA3_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e |
44181 | #define SDMA3_RLC6_DOORBELL__ENABLE_MASK 0x10000000L |
44182 | #define SDMA3_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L |
44183 | //SDMA3_RLC6_STATUS |
44184 | #define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
44185 | #define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
44186 | #define SDMA3_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
44187 | #define SDMA3_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
44188 | //SDMA3_RLC6_DOORBELL_LOG |
44189 | #define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
44190 | #define SDMA3_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 |
44191 | #define SDMA3_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
44192 | #define SDMA3_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
44193 | //SDMA3_RLC6_WATERMARK |
44194 | #define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
44195 | #define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
44196 | #define SDMA3_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
44197 | #define SDMA3_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
44198 | //SDMA3_RLC6_DOORBELL_OFFSET |
44199 | #define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
44200 | #define SDMA3_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
44201 | //SDMA3_RLC6_CSA_ADDR_LO |
44202 | #define SDMA3_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
44203 | #define SDMA3_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
44204 | //SDMA3_RLC6_CSA_ADDR_HI |
44205 | #define SDMA3_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
44206 | #define SDMA3_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
44207 | //SDMA3_RLC6_IB_SUB_REMAIN |
44208 | #define SDMA3_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
44209 | #define SDMA3_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
44210 | //SDMA3_RLC6_PREEMPT |
44211 | #define SDMA3_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
44212 | #define SDMA3_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
44213 | //SDMA3_RLC6_DUMMY_REG |
44214 | #define SDMA3_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 |
44215 | #define SDMA3_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
44216 | //SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI |
44217 | #define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
44218 | #define SDMA3_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
44219 | //SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO |
44220 | #define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
44221 | #define SDMA3_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
44222 | //SDMA3_RLC6_RB_AQL_CNTL |
44223 | #define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
44224 | #define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
44225 | #define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
44226 | #define SDMA3_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
44227 | #define SDMA3_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
44228 | #define SDMA3_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
44229 | #define SDMA3_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
44230 | #define SDMA3_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
44231 | #define SDMA3_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
44232 | #define SDMA3_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
44233 | #define SDMA3_RLC6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
44234 | #define SDMA3_RLC6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
44235 | //SDMA3_RLC6_MINOR_PTR_UPDATE |
44236 | #define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
44237 | #define SDMA3_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
44238 | //SDMA3_RLC6_MIDCMD_DATA0 |
44239 | #define SDMA3_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
44240 | #define SDMA3_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
44241 | //SDMA3_RLC6_MIDCMD_DATA1 |
44242 | #define SDMA3_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
44243 | #define SDMA3_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
44244 | //SDMA3_RLC6_MIDCMD_DATA2 |
44245 | #define SDMA3_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
44246 | #define SDMA3_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
44247 | //SDMA3_RLC6_MIDCMD_DATA3 |
44248 | #define SDMA3_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
44249 | #define SDMA3_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
44250 | //SDMA3_RLC6_MIDCMD_DATA4 |
44251 | #define SDMA3_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
44252 | #define SDMA3_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
44253 | //SDMA3_RLC6_MIDCMD_DATA5 |
44254 | #define SDMA3_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
44255 | #define SDMA3_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
44256 | //SDMA3_RLC6_MIDCMD_DATA6 |
44257 | #define SDMA3_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
44258 | #define SDMA3_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
44259 | //SDMA3_RLC6_MIDCMD_DATA7 |
44260 | #define SDMA3_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
44261 | #define SDMA3_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
44262 | //SDMA3_RLC6_MIDCMD_DATA8 |
44263 | #define SDMA3_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
44264 | #define SDMA3_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
44265 | //SDMA3_RLC6_MIDCMD_DATA9 |
44266 | #define SDMA3_RLC6_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
44267 | #define SDMA3_RLC6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
44268 | //SDMA3_RLC6_MIDCMD_DATA10 |
44269 | #define SDMA3_RLC6_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
44270 | #define SDMA3_RLC6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
44271 | //SDMA3_RLC6_MIDCMD_CNTL |
44272 | #define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
44273 | #define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
44274 | #define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
44275 | #define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
44276 | #define SDMA3_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
44277 | #define SDMA3_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
44278 | #define SDMA3_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
44279 | #define SDMA3_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
44280 | //SDMA3_RLC7_RB_CNTL |
44281 | #define SDMA3_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
44282 | #define SDMA3_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 |
44283 | #define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
44284 | #define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
44285 | #define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
44286 | #define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
44287 | #define SDMA3_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 |
44288 | #define SDMA3_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 |
44289 | #define SDMA3_RLC7_RB_CNTL__RPTR_WB_IDLE__SHIFT 0x1f |
44290 | #define SDMA3_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
44291 | #define SDMA3_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
44292 | #define SDMA3_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
44293 | #define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
44294 | #define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
44295 | #define SDMA3_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
44296 | #define SDMA3_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L |
44297 | #define SDMA3_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L |
44298 | #define SDMA3_RLC7_RB_CNTL__RPTR_WB_IDLE_MASK 0x80000000L |
44299 | //SDMA3_RLC7_RB_BASE |
44300 | #define SDMA3_RLC7_RB_BASE__ADDR__SHIFT 0x0 |
44301 | #define SDMA3_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
44302 | //SDMA3_RLC7_RB_BASE_HI |
44303 | #define SDMA3_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 |
44304 | #define SDMA3_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
44305 | //SDMA3_RLC7_RB_RPTR |
44306 | #define SDMA3_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 |
44307 | #define SDMA3_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
44308 | //SDMA3_RLC7_RB_RPTR_HI |
44309 | #define SDMA3_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
44310 | #define SDMA3_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
44311 | //SDMA3_RLC7_RB_WPTR |
44312 | #define SDMA3_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 |
44313 | #define SDMA3_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
44314 | //SDMA3_RLC7_RB_WPTR_HI |
44315 | #define SDMA3_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
44316 | #define SDMA3_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
44317 | //SDMA3_RLC7_RB_WPTR_POLL_CNTL |
44318 | #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 |
44319 | #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 |
44320 | #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 |
44321 | #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 |
44322 | #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
44323 | #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L |
44324 | #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L |
44325 | #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L |
44326 | #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L |
44327 | #define SDMA3_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
44328 | //SDMA3_RLC7_RB_RPTR_ADDR_HI |
44329 | #define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
44330 | #define SDMA3_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
44331 | //SDMA3_RLC7_RB_RPTR_ADDR_LO |
44332 | #define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
44333 | #define SDMA3_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
44334 | //SDMA3_RLC7_IB_CNTL |
44335 | #define SDMA3_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
44336 | #define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
44337 | #define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
44338 | #define SDMA3_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 |
44339 | #define SDMA3_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
44340 | #define SDMA3_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
44341 | #define SDMA3_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
44342 | #define SDMA3_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
44343 | //SDMA3_RLC7_IB_RPTR |
44344 | #define SDMA3_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 |
44345 | #define SDMA3_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
44346 | //SDMA3_RLC7_IB_OFFSET |
44347 | #define SDMA3_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 |
44348 | #define SDMA3_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
44349 | //SDMA3_RLC7_IB_BASE_LO |
44350 | #define SDMA3_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 |
44351 | #define SDMA3_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
44352 | //SDMA3_RLC7_IB_BASE_HI |
44353 | #define SDMA3_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 |
44354 | #define SDMA3_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
44355 | //SDMA3_RLC7_IB_SIZE |
44356 | #define SDMA3_RLC7_IB_SIZE__SIZE__SHIFT 0x0 |
44357 | #define SDMA3_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL |
44358 | //SDMA3_RLC7_SKIP_CNTL |
44359 | #define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
44360 | #define SDMA3_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
44361 | //SDMA3_RLC7_CONTEXT_STATUS |
44362 | #define SDMA3_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
44363 | #define SDMA3_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
44364 | #define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
44365 | #define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
44366 | #define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
44367 | #define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 |
44368 | #define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 |
44369 | #define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
44370 | #define SDMA3_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
44371 | #define SDMA3_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
44372 | #define SDMA3_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
44373 | #define SDMA3_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
44374 | #define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
44375 | #define SDMA3_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L |
44376 | #define SDMA3_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L |
44377 | #define SDMA3_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
44378 | //SDMA3_RLC7_DOORBELL |
44379 | #define SDMA3_RLC7_DOORBELL__ENABLE__SHIFT 0x1c |
44380 | #define SDMA3_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e |
44381 | #define SDMA3_RLC7_DOORBELL__ENABLE_MASK 0x10000000L |
44382 | #define SDMA3_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L |
44383 | //SDMA3_RLC7_STATUS |
44384 | #define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 |
44385 | #define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 |
44386 | #define SDMA3_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL |
44387 | #define SDMA3_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L |
44388 | //SDMA3_RLC7_DOORBELL_LOG |
44389 | #define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
44390 | #define SDMA3_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 |
44391 | #define SDMA3_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
44392 | #define SDMA3_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
44393 | //SDMA3_RLC7_WATERMARK |
44394 | #define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 |
44395 | #define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 |
44396 | #define SDMA3_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL |
44397 | #define SDMA3_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L |
44398 | //SDMA3_RLC7_DOORBELL_OFFSET |
44399 | #define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
44400 | #define SDMA3_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
44401 | //SDMA3_RLC7_CSA_ADDR_LO |
44402 | #define SDMA3_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
44403 | #define SDMA3_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
44404 | //SDMA3_RLC7_CSA_ADDR_HI |
44405 | #define SDMA3_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
44406 | #define SDMA3_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
44407 | //SDMA3_RLC7_IB_SUB_REMAIN |
44408 | #define SDMA3_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
44409 | #define SDMA3_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
44410 | //SDMA3_RLC7_PREEMPT |
44411 | #define SDMA3_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
44412 | #define SDMA3_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
44413 | //SDMA3_RLC7_DUMMY_REG |
44414 | #define SDMA3_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 |
44415 | #define SDMA3_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
44416 | //SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI |
44417 | #define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
44418 | #define SDMA3_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
44419 | //SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO |
44420 | #define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
44421 | #define SDMA3_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
44422 | //SDMA3_RLC7_RB_AQL_CNTL |
44423 | #define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
44424 | #define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
44425 | #define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
44426 | #define SDMA3_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
44427 | #define SDMA3_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
44428 | #define SDMA3_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
44429 | #define SDMA3_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
44430 | #define SDMA3_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
44431 | #define SDMA3_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
44432 | #define SDMA3_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
44433 | #define SDMA3_RLC7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
44434 | #define SDMA3_RLC7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
44435 | //SDMA3_RLC7_MINOR_PTR_UPDATE |
44436 | #define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
44437 | #define SDMA3_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
44438 | //SDMA3_RLC7_MIDCMD_DATA0 |
44439 | #define SDMA3_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
44440 | #define SDMA3_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
44441 | //SDMA3_RLC7_MIDCMD_DATA1 |
44442 | #define SDMA3_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
44443 | #define SDMA3_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
44444 | //SDMA3_RLC7_MIDCMD_DATA2 |
44445 | #define SDMA3_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
44446 | #define SDMA3_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
44447 | //SDMA3_RLC7_MIDCMD_DATA3 |
44448 | #define SDMA3_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
44449 | #define SDMA3_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
44450 | //SDMA3_RLC7_MIDCMD_DATA4 |
44451 | #define SDMA3_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
44452 | #define SDMA3_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
44453 | //SDMA3_RLC7_MIDCMD_DATA5 |
44454 | #define SDMA3_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
44455 | #define SDMA3_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
44456 | //SDMA3_RLC7_MIDCMD_DATA6 |
44457 | #define SDMA3_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
44458 | #define SDMA3_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
44459 | //SDMA3_RLC7_MIDCMD_DATA7 |
44460 | #define SDMA3_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
44461 | #define SDMA3_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
44462 | //SDMA3_RLC7_MIDCMD_DATA8 |
44463 | #define SDMA3_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
44464 | #define SDMA3_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
44465 | //SDMA3_RLC7_MIDCMD_DATA9 |
44466 | #define SDMA3_RLC7_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
44467 | #define SDMA3_RLC7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
44468 | //SDMA3_RLC7_MIDCMD_DATA10 |
44469 | #define SDMA3_RLC7_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
44470 | #define SDMA3_RLC7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
44471 | //SDMA3_RLC7_MIDCMD_CNTL |
44472 | #define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
44473 | #define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
44474 | #define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
44475 | #define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
44476 | #define SDMA3_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
44477 | #define SDMA3_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
44478 | #define SDMA3_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
44479 | #define SDMA3_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
44480 | |
44481 | |
44482 | // addressBlock: gccacind |
44483 | //PCC_STALL_PATTERN_CTRL |
44484 | #define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL__SHIFT 0x0 |
44485 | #define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP__SHIFT 0xa |
44486 | #define PCC_STALL_PATTERN_CTRL__PCC_END_STEP__SHIFT 0xf |
44487 | #define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14 |
44488 | #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR__SHIFT 0x18 |
44489 | #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR__SHIFT 0x19 |
44490 | #define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE__SHIFT 0x1a |
44491 | #define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL_MASK 0x000003FFL |
44492 | #define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP_MASK 0x00007C00L |
44493 | #define PCC_STALL_PATTERN_CTRL__PCC_END_STEP_MASK 0x000F8000L |
44494 | #define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L |
44495 | #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR_MASK 0x01000000L |
44496 | #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR_MASK 0x02000000L |
44497 | #define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE_MASK 0x04000000L |
44498 | //PWRBRK_STALL_PATTERN_CTRL |
44499 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT 0x0 |
44500 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT 0xa |
44501 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT 0xf |
44502 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14 |
44503 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK 0x000003FFL |
44504 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK 0x00007C00L |
44505 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK 0x000F8000L |
44506 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L |
44507 | //PCC_STALL_PATTERN_1_2 |
44508 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT 0x0 |
44509 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT 0x10 |
44510 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK 0x00007FFFL |
44511 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK 0x7FFF0000L |
44512 | //PCC_STALL_PATTERN_3_4 |
44513 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT 0x0 |
44514 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT 0x10 |
44515 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK 0x00007FFFL |
44516 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK 0x7FFF0000L |
44517 | //PCC_STALL_PATTERN_5_6 |
44518 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT 0x0 |
44519 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT 0x10 |
44520 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK 0x00007FFFL |
44521 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK 0x7FFF0000L |
44522 | //PCC_STALL_PATTERN_7 |
44523 | #define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT 0x0 |
44524 | #define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK 0x00007FFFL |
44525 | //PWRBRK_STALL_PATTERN_1_2 |
44526 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT 0x0 |
44527 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT 0x10 |
44528 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK 0x00007FFFL |
44529 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK 0x7FFF0000L |
44530 | //PWRBRK_STALL_PATTERN_3_4 |
44531 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT 0x0 |
44532 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT 0x10 |
44533 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK 0x00007FFFL |
44534 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK 0x7FFF0000L |
44535 | //PWRBRK_STALL_PATTERN_5_6 |
44536 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT 0x0 |
44537 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT 0x10 |
44538 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK 0x00007FFFL |
44539 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK 0x7FFF0000L |
44540 | //PWRBRK_STALL_PATTERN_7 |
44541 | #define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT 0x0 |
44542 | #define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK 0x00007FFFL |
44543 | //PCC_PWRBRK_HYSTERESIS_CTRL |
44544 | #define PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS__SHIFT 0x0 |
44545 | #define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS__SHIFT 0x8 |
44546 | #define PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS_MASK 0x000000FFL |
44547 | #define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS_MASK 0x0000FF00L |
44548 | //EDC_STRETCH_PERF_COUNTER |
44549 | #define EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER__SHIFT 0x0 |
44550 | #define EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER_MASK 0xFFFFFFFFL |
44551 | //EDC_UNSTRETCH_PERF_COUNTER |
44552 | #define EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER__SHIFT 0x0 |
44553 | #define EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER_MASK 0xFFFFFFFFL |
44554 | //EDC_STRETCH_NUM_PERF_COUNTER |
44555 | #define EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER__SHIFT 0x0 |
44556 | #define EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER_MASK 0xFFFFFFFFL |
44557 | //GC_CAC_ID |
44558 | #define GC_CAC_ID__CAC_BLOCK_ID__SHIFT 0x0 |
44559 | #define GC_CAC_ID__CAC_SIGNAL_ID__SHIFT 0x6 |
44560 | #define GC_CAC_ID__UNUSED_0__SHIFT 0xe |
44561 | #define GC_CAC_ID__CAC_BLOCK_ID_MASK 0x0000003FL |
44562 | #define GC_CAC_ID__CAC_SIGNAL_ID_MASK 0x00003FC0L |
44563 | #define GC_CAC_ID__UNUSED_0_MASK 0xFFFFC000L |
44564 | //GC_CAC_CNTL |
44565 | #define GC_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0 |
44566 | #define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 |
44567 | #define GC_CAC_CNTL__UNUSED_0__SHIFT 0x11 |
44568 | #define GC_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L |
44569 | #define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL |
44570 | #define GC_CAC_CNTL__UNUSED_0_MASK 0xFFFE0000L |
44571 | //GC_CAC_OVR_SEL |
44572 | #define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 |
44573 | #define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL |
44574 | //GC_CAC_OVR_VAL |
44575 | #define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 |
44576 | #define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL |
44577 | //GC_CAC_WEIGHT_BCI_0 |
44578 | #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0 |
44579 | #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10 |
44580 | #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL |
44581 | #define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L |
44582 | //GC_CAC_WEIGHT_CB_0 |
44583 | #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0 |
44584 | #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10 |
44585 | #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL |
44586 | #define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L |
44587 | //GC_CAC_WEIGHT_CB_1 |
44588 | #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0 |
44589 | #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10 |
44590 | #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL |
44591 | #define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L |
44592 | //GC_CAC_WEIGHT_CB_2 |
44593 | #define GC_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG4__SHIFT 0x0 |
44594 | #define GC_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG5__SHIFT 0x10 |
44595 | #define GC_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG4_MASK 0x0000FFFFL |
44596 | #define GC_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG5_MASK 0xFFFF0000L |
44597 | //GC_CAC_WEIGHT_CB_3 |
44598 | #define GC_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG6__SHIFT 0x0 |
44599 | #define GC_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG7__SHIFT 0x10 |
44600 | #define GC_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG6_MASK 0x0000FFFFL |
44601 | #define GC_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG7_MASK 0xFFFF0000L |
44602 | //GC_CAC_WEIGHT_CB_4 |
44603 | #define GC_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG8__SHIFT 0x0 |
44604 | #define GC_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG9__SHIFT 0x10 |
44605 | #define GC_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG8_MASK 0x0000FFFFL |
44606 | #define GC_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG9_MASK 0xFFFF0000L |
44607 | //GC_CAC_WEIGHT_CP_0 |
44608 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0 |
44609 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10 |
44610 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL |
44611 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L |
44612 | //GC_CAC_WEIGHT_CP_1 |
44613 | #define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0 |
44614 | #define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT 0x10 |
44615 | #define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL |
44616 | #define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK 0xFFFF0000L |
44617 | //GC_CAC_WEIGHT_DB_0 |
44618 | #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0 |
44619 | #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10 |
44620 | #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL |
44621 | #define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L |
44622 | //GC_CAC_WEIGHT_DB_1 |
44623 | #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0 |
44624 | #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10 |
44625 | #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL |
44626 | #define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L |
44627 | //GC_CAC_WEIGHT_DB_2 |
44628 | #define GC_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG4__SHIFT 0x0 |
44629 | #define GC_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG5__SHIFT 0x10 |
44630 | #define GC_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG4_MASK 0x0000FFFFL |
44631 | #define GC_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG5_MASK 0xFFFF0000L |
44632 | //GC_CAC_WEIGHT_DB_3 |
44633 | #define GC_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG6__SHIFT 0x0 |
44634 | #define GC_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG7__SHIFT 0x10 |
44635 | #define GC_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG6_MASK 0x0000FFFFL |
44636 | #define GC_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG7_MASK 0xFFFF0000L |
44637 | //GC_CAC_WEIGHT_DB_4 |
44638 | #define GC_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG8__SHIFT 0x0 |
44639 | #define GC_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG9__SHIFT 0x10 |
44640 | #define GC_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG8_MASK 0x0000FFFFL |
44641 | #define GC_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG9_MASK 0xFFFF0000L |
44642 | //GC_CAC_WEIGHT_GDS_0 |
44643 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0 |
44644 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10 |
44645 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL |
44646 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L |
44647 | //GC_CAC_WEIGHT_GDS_1 |
44648 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0 |
44649 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10 |
44650 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL |
44651 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L |
44652 | //GC_CAC_WEIGHT_GDS_2 |
44653 | #define GC_CAC_WEIGHT_GDS_2__WEIGHT_GDS_SIG4__SHIFT 0x0 |
44654 | #define GC_CAC_WEIGHT_GDS_2__WEIGHT_GDS_SIG4_MASK 0x0000FFFFL |
44655 | //GC_CAC_WEIGHT_LDS_0 |
44656 | #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0 |
44657 | #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10 |
44658 | #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL |
44659 | #define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L |
44660 | //GC_CAC_WEIGHT_LDS_1 |
44661 | #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0 |
44662 | #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10 |
44663 | #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL |
44664 | #define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L |
44665 | //GC_CAC_WEIGHT_LDS_2 |
44666 | #define GC_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG4__SHIFT 0x0 |
44667 | #define GC_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG5__SHIFT 0x10 |
44668 | #define GC_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG4_MASK 0x0000FFFFL |
44669 | #define GC_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG5_MASK 0xFFFF0000L |
44670 | //GC_CAC_WEIGHT_LDS_3 |
44671 | #define GC_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG6__SHIFT 0x0 |
44672 | #define GC_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG7__SHIFT 0x10 |
44673 | #define GC_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG6_MASK 0x0000FFFFL |
44674 | #define GC_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG7_MASK 0xFFFF0000L |
44675 | //GC_CAC_WEIGHT_LDS_4 |
44676 | #define GC_CAC_WEIGHT_LDS_4__WEIGHT_LDS_SIG8__SHIFT 0x0 |
44677 | #define GC_CAC_WEIGHT_LDS_4__UNUSED_0__SHIFT 0x10 |
44678 | #define GC_CAC_WEIGHT_LDS_4__WEIGHT_LDS_SIG8_MASK 0x0000FFFFL |
44679 | #define GC_CAC_WEIGHT_LDS_4__UNUSED_0_MASK 0xFFFF0000L |
44680 | //GC_CAC_WEIGHT_PA_0 |
44681 | #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0 |
44682 | #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10 |
44683 | #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL |
44684 | #define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L |
44685 | //GC_CAC_WEIGHT_PA_1 |
44686 | #define GC_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG2__SHIFT 0x0 |
44687 | #define GC_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG3__SHIFT 0x10 |
44688 | #define GC_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG2_MASK 0x0000FFFFL |
44689 | #define GC_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG3_MASK 0xFFFF0000L |
44690 | //GC_CAC_WEIGHT_PA_2 |
44691 | #define GC_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG4__SHIFT 0x0 |
44692 | #define GC_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG5__SHIFT 0x10 |
44693 | #define GC_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG4_MASK 0x0000FFFFL |
44694 | #define GC_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG5_MASK 0xFFFF0000L |
44695 | //GC_CAC_WEIGHT_PA_3 |
44696 | #define GC_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG6__SHIFT 0x0 |
44697 | #define GC_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG7__SHIFT 0x10 |
44698 | #define GC_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG6_MASK 0x0000FFFFL |
44699 | #define GC_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG7_MASK 0xFFFF0000L |
44700 | //GC_CAC_WEIGHT_PC_0 |
44701 | #define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0 |
44702 | #define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT 0x10 |
44703 | #define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL |
44704 | #define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK 0xFFFF0000L |
44705 | //GC_CAC_WEIGHT_SC_0 |
44706 | #define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0 |
44707 | #define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG1__SHIFT 0x10 |
44708 | #define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL |
44709 | #define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG1_MASK 0xFFFF0000L |
44710 | //GC_CAC_WEIGHT_SC_1 |
44711 | #define GC_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG2__SHIFT 0x0 |
44712 | #define GC_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG3__SHIFT 0x10 |
44713 | #define GC_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG2_MASK 0x0000FFFFL |
44714 | #define GC_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG3_MASK 0xFFFF0000L |
44715 | //GC_CAC_WEIGHT_SC_2 |
44716 | #define GC_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG4__SHIFT 0x0 |
44717 | #define GC_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG5__SHIFT 0x10 |
44718 | #define GC_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG4_MASK 0x0000FFFFL |
44719 | #define GC_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG5_MASK 0xFFFF0000L |
44720 | //GC_CAC_WEIGHT_SC_3 |
44721 | #define GC_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG6__SHIFT 0x0 |
44722 | #define GC_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG7__SHIFT 0x10 |
44723 | #define GC_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG6_MASK 0x0000FFFFL |
44724 | #define GC_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG7_MASK 0xFFFF0000L |
44725 | //GC_CAC_WEIGHT_SPI_0 |
44726 | #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0 |
44727 | #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10 |
44728 | #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL |
44729 | #define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L |
44730 | //GC_CAC_WEIGHT_SPI_1 |
44731 | #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0 |
44732 | #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10 |
44733 | #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL |
44734 | #define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L |
44735 | //GC_CAC_WEIGHT_SPI_2 |
44736 | #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0 |
44737 | #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10 |
44738 | #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL |
44739 | #define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L |
44740 | //GC_CAC_WEIGHT_SQ_0 |
44741 | #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0 |
44742 | #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10 |
44743 | #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL |
44744 | #define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L |
44745 | //GC_CAC_WEIGHT_SQ_1 |
44746 | #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0 |
44747 | #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10 |
44748 | #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL |
44749 | #define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L |
44750 | //GC_CAC_WEIGHT_SQ_2 |
44751 | #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0 |
44752 | #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10 |
44753 | #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL |
44754 | #define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L |
44755 | //GC_CAC_WEIGHT_SQ_3 |
44756 | #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x0 |
44757 | #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x10 |
44758 | #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000FFFFL |
44759 | #define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xFFFF0000L |
44760 | //GC_CAC_WEIGHT_SX_0 |
44761 | #define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0 |
44762 | #define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT 0x10 |
44763 | #define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL |
44764 | #define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK 0xFFFF0000L |
44765 | //GC_CAC_WEIGHT_SXRB_0 |
44766 | #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0 |
44767 | #define GC_CAC_WEIGHT_SXRB_0__UNUSED_0__SHIFT 0x10 |
44768 | #define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL |
44769 | #define GC_CAC_WEIGHT_SXRB_0__UNUSED_0_MASK 0xFFFF0000L |
44770 | //GC_CAC_WEIGHT_TA_0 |
44771 | #define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0 |
44772 | #define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT 0x10 |
44773 | #define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL |
44774 | #define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK 0xFFFF0000L |
44775 | //GC_CAC_WEIGHT_TCP_0 |
44776 | #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0 |
44777 | #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10 |
44778 | #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL |
44779 | #define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L |
44780 | //GC_CAC_WEIGHT_TCP_1 |
44781 | #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0 |
44782 | #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10 |
44783 | #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL |
44784 | #define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L |
44785 | //GC_CAC_WEIGHT_TCP_2 |
44786 | #define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0 |
44787 | #define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5__SHIFT 0x10 |
44788 | #define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL |
44789 | #define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5_MASK 0xFFFF0000L |
44790 | //GC_CAC_WEIGHT_TCP_3 |
44791 | #define GC_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6__SHIFT 0x0 |
44792 | #define GC_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7__SHIFT 0x10 |
44793 | #define GC_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6_MASK 0x0000FFFFL |
44794 | #define GC_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7_MASK 0xFFFF0000L |
44795 | //GC_CAC_WEIGHT_TD_0 |
44796 | #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0 |
44797 | #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10 |
44798 | #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL |
44799 | #define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L |
44800 | //GC_CAC_WEIGHT_TD_1 |
44801 | #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0 |
44802 | #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10 |
44803 | #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL |
44804 | #define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L |
44805 | //GC_CAC_WEIGHT_TD_2 |
44806 | #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0 |
44807 | #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10 |
44808 | #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL |
44809 | #define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L |
44810 | //GC_CAC_WEIGHT_TD_3 |
44811 | #define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6__SHIFT 0x0 |
44812 | #define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7__SHIFT 0x10 |
44813 | #define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6_MASK 0x0000FFFFL |
44814 | #define GC_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7_MASK 0xFFFF0000L |
44815 | //GC_CAC_WEIGHT_TD_4 |
44816 | #define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8__SHIFT 0x0 |
44817 | #define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9__SHIFT 0x10 |
44818 | #define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8_MASK 0x0000FFFFL |
44819 | #define GC_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9_MASK 0xFFFF0000L |
44820 | //GC_CAC_WEIGHT_TD_5 |
44821 | #define GC_CAC_WEIGHT_TD_5__WEIGHT_TD_SIG10__SHIFT 0x0 |
44822 | #define GC_CAC_WEIGHT_TD_5__WEIGHT_TD_SIG10_MASK 0x0000FFFFL |
44823 | //GC_CAC_WEIGHT_RMI_0 |
44824 | #define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0 |
44825 | #define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG1__SHIFT 0x10 |
44826 | #define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL |
44827 | #define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG1_MASK 0xFFFF0000L |
44828 | //GC_CAC_WEIGHT_RMI_1 |
44829 | #define GC_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG2__SHIFT 0x0 |
44830 | #define GC_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG3__SHIFT 0x10 |
44831 | #define GC_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG2_MASK 0x0000FFFFL |
44832 | #define GC_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG3_MASK 0xFFFF0000L |
44833 | //GC_CAC_WEIGHT_EA_0 |
44834 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0 |
44835 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10 |
44836 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL |
44837 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L |
44838 | //GC_CAC_WEIGHT_EA_1 |
44839 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0 |
44840 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10 |
44841 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL |
44842 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L |
44843 | //GC_CAC_WEIGHT_EA_2 |
44844 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0 |
44845 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10 |
44846 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL |
44847 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L |
44848 | //GC_CAC_WEIGHT_UTCL2_ATCL2_0 |
44849 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0 |
44850 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10 |
44851 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL |
44852 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L |
44853 | //GC_CAC_WEIGHT_UTCL2_ATCL2_1 |
44854 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0 |
44855 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10 |
44856 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL |
44857 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L |
44858 | //GC_CAC_WEIGHT_UTCL2_ATCL2_2 |
44859 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0 |
44860 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__UNUSED_0__SHIFT 0x10 |
44861 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL |
44862 | #define GC_CAC_WEIGHT_UTCL2_ATCL2_2__UNUSED_0_MASK 0xFFFF0000L |
44863 | //GC_CAC_WEIGHT_UTCL2_ROUTER_0 |
44864 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0 |
44865 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10 |
44866 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL |
44867 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L |
44868 | //GC_CAC_WEIGHT_UTCL2_ROUTER_1 |
44869 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0 |
44870 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10 |
44871 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL |
44872 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L |
44873 | //GC_CAC_WEIGHT_UTCL2_ROUTER_2 |
44874 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0 |
44875 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10 |
44876 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL |
44877 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L |
44878 | //GC_CAC_WEIGHT_UTCL2_ROUTER_3 |
44879 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0 |
44880 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10 |
44881 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL |
44882 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L |
44883 | //GC_CAC_WEIGHT_UTCL2_ROUTER_4 |
44884 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0 |
44885 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10 |
44886 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL |
44887 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L |
44888 | //GC_CAC_WEIGHT_UTCL2_VML2_0 |
44889 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0 |
44890 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10 |
44891 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL |
44892 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L |
44893 | //GC_CAC_WEIGHT_UTCL2_VML2_1 |
44894 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0 |
44895 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10 |
44896 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL |
44897 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L |
44898 | //GC_CAC_WEIGHT_UTCL2_VML2_2 |
44899 | #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0 |
44900 | #define GC_CAC_WEIGHT_UTCL2_VML2_2__UNUSED_0__SHIFT 0x10 |
44901 | #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL |
44902 | #define GC_CAC_WEIGHT_UTCL2_VML2_2__UNUSED_0_MASK 0xFFFF0000L |
44903 | //GC_CAC_WEIGHT_UTCL2_WALKER_0 |
44904 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0 |
44905 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10 |
44906 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL |
44907 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L |
44908 | //GC_CAC_WEIGHT_UTCL2_WALKER_1 |
44909 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0 |
44910 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10 |
44911 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL |
44912 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L |
44913 | //GC_CAC_WEIGHT_UTCL2_WALKER_2 |
44914 | #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0 |
44915 | #define GC_CAC_WEIGHT_UTCL2_WALKER_2__UNUSED_0__SHIFT 0x10 |
44916 | #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL |
44917 | #define GC_CAC_WEIGHT_UTCL2_WALKER_2__UNUSED_0_MASK 0xFFFF0000L |
44918 | //GC_CAC_WEIGHT_CU_0 |
44919 | #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 |
44920 | #define GC_CAC_WEIGHT_CU_0__UNUSED_0__SHIFT 0x10 |
44921 | #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL |
44922 | #define GC_CAC_WEIGHT_CU_0__UNUSED_0_MASK 0xFFFF0000L |
44923 | //GC_CAC_WEIGHT_UTCL1_0 |
44924 | #define GC_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0__SHIFT 0x0 |
44925 | #define GC_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0_MASK 0x0000FFFFL |
44926 | //GC_CAC_WEIGHT_GE_0 |
44927 | #define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0__SHIFT 0x0 |
44928 | #define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG1__SHIFT 0x10 |
44929 | #define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0_MASK 0x0000FFFFL |
44930 | #define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG1_MASK 0xFFFF0000L |
44931 | //GC_CAC_WEIGHT_GE_1 |
44932 | #define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG2__SHIFT 0x0 |
44933 | #define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG3__SHIFT 0x10 |
44934 | #define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG2_MASK 0x0000FFFFL |
44935 | #define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG3_MASK 0xFFFF0000L |
44936 | //GC_CAC_WEIGHT_GE_2 |
44937 | #define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG4__SHIFT 0x0 |
44938 | #define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG5__SHIFT 0x10 |
44939 | #define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG4_MASK 0x0000FFFFL |
44940 | #define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG5_MASK 0xFFFF0000L |
44941 | //GC_CAC_WEIGHT_GE_3 |
44942 | #define GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG6__SHIFT 0x0 |
44943 | #define GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG7__SHIFT 0x10 |
44944 | #define GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG6_MASK 0x0000FFFFL |
44945 | #define GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG7_MASK 0xFFFF0000L |
44946 | //GC_CAC_WEIGHT_GE_4 |
44947 | #define GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG8__SHIFT 0x0 |
44948 | #define GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG9__SHIFT 0x10 |
44949 | #define GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG8_MASK 0x0000FFFFL |
44950 | #define GC_CAC_WEIGHT_GE_4__WEIGHT_GE_SIG9_MASK 0xFFFF0000L |
44951 | //GC_CAC_WEIGHT_GE_5 |
44952 | #define GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG10__SHIFT 0x0 |
44953 | #define GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG11__SHIFT 0x10 |
44954 | #define GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG10_MASK 0x0000FFFFL |
44955 | #define GC_CAC_WEIGHT_GE_5__WEIGHT_GE_SIG11_MASK 0xFFFF0000L |
44956 | //GC_CAC_WEIGHT_GE_6 |
44957 | #define GC_CAC_WEIGHT_GE_6__WEIGHT_GE_SIG12__SHIFT 0x0 |
44958 | #define GC_CAC_WEIGHT_GE_6__WEIGHT_GE_SIG13__SHIFT 0x10 |
44959 | #define GC_CAC_WEIGHT_GE_6__WEIGHT_GE_SIG12_MASK 0x0000FFFFL |
44960 | #define GC_CAC_WEIGHT_GE_6__WEIGHT_GE_SIG13_MASK 0xFFFF0000L |
44961 | //GC_CAC_WEIGHT_GE_7 |
44962 | #define GC_CAC_WEIGHT_GE_7__WEIGHT_GE_SIG14__SHIFT 0x0 |
44963 | #define GC_CAC_WEIGHT_GE_7__WEIGHT_GE_SIG15__SHIFT 0x10 |
44964 | #define GC_CAC_WEIGHT_GE_7__WEIGHT_GE_SIG14_MASK 0x0000FFFFL |
44965 | #define GC_CAC_WEIGHT_GE_7__WEIGHT_GE_SIG15_MASK 0xFFFF0000L |
44966 | //GC_CAC_WEIGHT_GE_8 |
44967 | #define GC_CAC_WEIGHT_GE_8__WEIGHT_GE_SIG16__SHIFT 0x0 |
44968 | #define GC_CAC_WEIGHT_GE_8__WEIGHT_GE_SIG17__SHIFT 0x10 |
44969 | #define GC_CAC_WEIGHT_GE_8__WEIGHT_GE_SIG16_MASK 0x0000FFFFL |
44970 | #define GC_CAC_WEIGHT_GE_8__WEIGHT_GE_SIG17_MASK 0xFFFF0000L |
44971 | //GC_CAC_WEIGHT_GE_9 |
44972 | #define GC_CAC_WEIGHT_GE_9__WEIGHT_GE_SIG18__SHIFT 0x0 |
44973 | #define GC_CAC_WEIGHT_GE_9__WEIGHT_GE_SIG19__SHIFT 0x10 |
44974 | #define GC_CAC_WEIGHT_GE_9__WEIGHT_GE_SIG18_MASK 0x0000FFFFL |
44975 | #define GC_CAC_WEIGHT_GE_9__WEIGHT_GE_SIG19_MASK 0xFFFF0000L |
44976 | //GC_CAC_WEIGHT_GE_10 |
44977 | #define GC_CAC_WEIGHT_GE_10__WEIGHT_GE_SIG20__SHIFT 0x0 |
44978 | #define GC_CAC_WEIGHT_GE_10__WEIGHT_GE_SIG20_MASK 0x0000FFFFL |
44979 | //GC_CAC_WEIGHT_PMM_0 |
44980 | #define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0__SHIFT 0x0 |
44981 | #define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0_MASK 0x0000FFFFL |
44982 | //GC_CAC_WEIGHT_GL2C_0 |
44983 | #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0__SHIFT 0x0 |
44984 | #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1__SHIFT 0x10 |
44985 | #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0_MASK 0x0000FFFFL |
44986 | #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1_MASK 0xFFFF0000L |
44987 | //GC_CAC_WEIGHT_GL2C_1 |
44988 | #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2__SHIFT 0x0 |
44989 | #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3__SHIFT 0x10 |
44990 | #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2_MASK 0x0000FFFFL |
44991 | #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3_MASK 0xFFFF0000L |
44992 | //GC_CAC_WEIGHT_GL2C_2 |
44993 | #define GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4__SHIFT 0x0 |
44994 | #define GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4_MASK 0x0000FFFFL |
44995 | //GC_CAC_WEIGHT_GUS_0 |
44996 | #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0__SHIFT 0x0 |
44997 | #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1__SHIFT 0x10 |
44998 | #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0_MASK 0x0000FFFFL |
44999 | #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1_MASK 0xFFFF0000L |
45000 | //GC_CAC_WEIGHT_GUS_1 |
45001 | #define GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2__SHIFT 0x0 |
45002 | #define GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2_MASK 0x0000FFFFL |
45003 | //GC_CAC_WEIGHT_PH_0 |
45004 | #define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0__SHIFT 0x0 |
45005 | #define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG1__SHIFT 0x10 |
45006 | #define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0_MASK 0x0000FFFFL |
45007 | #define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG1_MASK 0xFFFF0000L |
45008 | //GC_CAC_WEIGHT_PH_1 |
45009 | #define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG2__SHIFT 0x0 |
45010 | #define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG3__SHIFT 0x10 |
45011 | #define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG2_MASK 0x0000FFFFL |
45012 | #define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG3_MASK 0xFFFF0000L |
45013 | //GC_CAC_WEIGHT_PH_2 |
45014 | #define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG4__SHIFT 0x0 |
45015 | #define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG5__SHIFT 0x10 |
45016 | #define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG4_MASK 0x0000FFFFL |
45017 | #define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG5_MASK 0xFFFF0000L |
45018 | //GC_CAC_WEIGHT_PH_3 |
45019 | #define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG6__SHIFT 0x0 |
45020 | #define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG7__SHIFT 0x10 |
45021 | #define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG6_MASK 0x0000FFFFL |
45022 | #define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG7_MASK 0xFFFF0000L |
45023 | //GC_CAC_WEIGHT_SDMA_0 |
45024 | #define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0__SHIFT 0x0 |
45025 | #define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1__SHIFT 0x10 |
45026 | #define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0_MASK 0x0000FFFFL |
45027 | #define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1_MASK 0xFFFF0000L |
45028 | //GC_CAC_WEIGHT_SDMA_1 |
45029 | #define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2__SHIFT 0x0 |
45030 | #define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3__SHIFT 0x10 |
45031 | #define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2_MASK 0x0000FFFFL |
45032 | #define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3_MASK 0xFFFF0000L |
45033 | //GC_CAC_WEIGHT_SDMA_2 |
45034 | #define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4__SHIFT 0x0 |
45035 | #define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5__SHIFT 0x10 |
45036 | #define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4_MASK 0x0000FFFFL |
45037 | #define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5_MASK 0xFFFF0000L |
45038 | //GC_CAC_WEIGHT_SDMA_3 |
45039 | #define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6__SHIFT 0x0 |
45040 | #define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7__SHIFT 0x10 |
45041 | #define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6_MASK 0x0000FFFFL |
45042 | #define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7_MASK 0xFFFF0000L |
45043 | //GC_CAC_WEIGHT_SDMA_4 |
45044 | #define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8__SHIFT 0x0 |
45045 | #define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9__SHIFT 0x10 |
45046 | #define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8_MASK 0x0000FFFFL |
45047 | #define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9_MASK 0xFFFF0000L |
45048 | //GC_CAC_WEIGHT_SDMA_5 |
45049 | #define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10__SHIFT 0x0 |
45050 | #define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11__SHIFT 0x10 |
45051 | #define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10_MASK 0x0000FFFFL |
45052 | #define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11_MASK 0xFFFF0000L |
45053 | //GC_CAC_WEIGHT_SP_0 |
45054 | #define GC_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0__SHIFT 0x0 |
45055 | #define GC_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1__SHIFT 0x10 |
45056 | #define GC_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0_MASK 0x0000FFFFL |
45057 | #define GC_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1_MASK 0xFFFF0000L |
45058 | //GC_CAC_WEIGHT_SP_1 |
45059 | #define GC_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2__SHIFT 0x0 |
45060 | #define GC_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2_MASK 0x0000FFFFL |
45061 | //GC_CAC_WEIGHT_GL1C_0 |
45062 | #define GC_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0__SHIFT 0x0 |
45063 | #define GC_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1__SHIFT 0x10 |
45064 | #define GC_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0_MASK 0x0000FFFFL |
45065 | #define GC_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1_MASK 0xFFFF0000L |
45066 | //GC_CAC_WEIGHT_GL1C_1 |
45067 | #define GC_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2__SHIFT 0x0 |
45068 | #define GC_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3__SHIFT 0x10 |
45069 | #define GC_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2_MASK 0x0000FFFFL |
45070 | #define GC_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3_MASK 0xFFFF0000L |
45071 | //GC_CAC_WEIGHT_GL1C_2 |
45072 | #define GC_CAC_WEIGHT_GL1C_2__WEIGHT_GL1C_SIG4__SHIFT 0x0 |
45073 | #define GC_CAC_WEIGHT_GL1C_2__WEIGHT_GL1C_SIG4_MASK 0x0000FFFFL |
45074 | //GC_CAC_WEIGHT_CHC_0 |
45075 | #define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0__SHIFT 0x0 |
45076 | #define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1__SHIFT 0x10 |
45077 | #define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0_MASK 0x0000FFFFL |
45078 | #define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1_MASK 0xFFFF0000L |
45079 | //GC_CAC_WEIGHT_CHC_1 |
45080 | #define GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2__SHIFT 0x0 |
45081 | #define GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2_MASK 0x0000FFFFL |
45082 | //GC_CAC_WEIGHT_SQC_0 |
45083 | #define GC_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0__SHIFT 0x0 |
45084 | #define GC_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1__SHIFT 0x10 |
45085 | #define GC_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0_MASK 0x0000FFFFL |
45086 | #define GC_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1_MASK 0xFFFF0000L |
45087 | //GC_CAC_WEIGHT_SQC_1 |
45088 | #define GC_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2__SHIFT 0x0 |
45089 | #define GC_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2_MASK 0x0000FFFFL |
45090 | //GC_CAC_WEIGHT_RLC_0 |
45091 | #define GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0__SHIFT 0x0 |
45092 | #define GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0_MASK 0x0000FFFFL |
45093 | //GC_CAC_ACC_LDS0 |
45094 | #define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0 |
45095 | #define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45096 | //GC_CAC_ACC_LDS1 |
45097 | #define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0 |
45098 | #define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45099 | //GC_CAC_ACC_LDS2 |
45100 | #define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0 |
45101 | #define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45102 | //GC_CAC_ACC_LDS3 |
45103 | #define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0 |
45104 | #define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45105 | //GC_CAC_ACC_LDS4 |
45106 | #define GC_CAC_ACC_LDS4__ACCUMULATOR_31_0__SHIFT 0x0 |
45107 | #define GC_CAC_ACC_LDS4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45108 | //GC_CAC_ACC_LDS5 |
45109 | #define GC_CAC_ACC_LDS5__ACCUMULATOR_31_0__SHIFT 0x0 |
45110 | #define GC_CAC_ACC_LDS5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45111 | //GC_CAC_ACC_LDS6 |
45112 | #define GC_CAC_ACC_LDS6__ACCUMULATOR_31_0__SHIFT 0x0 |
45113 | #define GC_CAC_ACC_LDS6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45114 | //GC_CAC_ACC_LDS7 |
45115 | #define GC_CAC_ACC_LDS7__ACCUMULATOR_31_0__SHIFT 0x0 |
45116 | #define GC_CAC_ACC_LDS7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45117 | //GC_CAC_ACC_LDS8 |
45118 | #define GC_CAC_ACC_LDS8__ACCUMULATOR_31_0__SHIFT 0x0 |
45119 | #define GC_CAC_ACC_LDS8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45120 | //GC_CAC_ACC_BCI0 |
45121 | #define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0 |
45122 | #define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45123 | //GC_CAC_ACC_BCI1 |
45124 | #define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0 |
45125 | #define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45126 | //GC_CAC_ACC_CB0 |
45127 | #define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0 |
45128 | #define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45129 | //GC_CAC_ACC_CB1 |
45130 | #define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0 |
45131 | #define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45132 | //GC_CAC_ACC_CB2 |
45133 | #define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0 |
45134 | #define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45135 | //GC_CAC_ACC_CB3 |
45136 | #define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0 |
45137 | #define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45138 | //GC_CAC_ACC_CB4 |
45139 | #define GC_CAC_ACC_CB4__ACCUMULATOR_31_0__SHIFT 0x0 |
45140 | #define GC_CAC_ACC_CB4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45141 | //GC_CAC_ACC_CB5 |
45142 | #define GC_CAC_ACC_CB5__ACCUMULATOR_31_0__SHIFT 0x0 |
45143 | #define GC_CAC_ACC_CB5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45144 | //GC_CAC_ACC_CB6 |
45145 | #define GC_CAC_ACC_CB6__ACCUMULATOR_31_0__SHIFT 0x0 |
45146 | #define GC_CAC_ACC_CB6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45147 | //GC_CAC_ACC_CB7 |
45148 | #define GC_CAC_ACC_CB7__ACCUMULATOR_31_0__SHIFT 0x0 |
45149 | #define GC_CAC_ACC_CB7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45150 | //GC_CAC_ACC_CB8 |
45151 | #define GC_CAC_ACC_CB8__ACCUMULATOR_31_0__SHIFT 0x0 |
45152 | #define GC_CAC_ACC_CB8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45153 | //GC_CAC_ACC_CB9 |
45154 | #define GC_CAC_ACC_CB9__ACCUMULATOR_31_0__SHIFT 0x0 |
45155 | #define GC_CAC_ACC_CB9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45156 | //GC_CAC_ACC_CP0 |
45157 | #define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0 |
45158 | #define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45159 | //GC_CAC_ACC_CP1 |
45160 | #define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0 |
45161 | #define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45162 | //GC_CAC_ACC_CP2 |
45163 | #define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0 |
45164 | #define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45165 | //GC_CAC_ACC_DB0 |
45166 | #define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0 |
45167 | #define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45168 | //GC_CAC_ACC_DB1 |
45169 | #define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0 |
45170 | #define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45171 | //GC_CAC_ACC_DB2 |
45172 | #define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0 |
45173 | #define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45174 | //GC_CAC_ACC_DB3 |
45175 | #define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0 |
45176 | #define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45177 | //GC_CAC_ACC_DB4 |
45178 | #define GC_CAC_ACC_DB4__ACCUMULATOR_31_0__SHIFT 0x0 |
45179 | #define GC_CAC_ACC_DB4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45180 | //GC_CAC_ACC_DB5 |
45181 | #define GC_CAC_ACC_DB5__ACCUMULATOR_31_0__SHIFT 0x0 |
45182 | #define GC_CAC_ACC_DB5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45183 | //GC_CAC_ACC_DB6 |
45184 | #define GC_CAC_ACC_DB6__ACCUMULATOR_31_0__SHIFT 0x0 |
45185 | #define GC_CAC_ACC_DB6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45186 | //GC_CAC_ACC_DB7 |
45187 | #define GC_CAC_ACC_DB7__ACCUMULATOR_31_0__SHIFT 0x0 |
45188 | #define GC_CAC_ACC_DB7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45189 | //GC_CAC_ACC_DB8 |
45190 | #define GC_CAC_ACC_DB8__ACCUMULATOR_31_0__SHIFT 0x0 |
45191 | #define GC_CAC_ACC_DB8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45192 | //GC_CAC_ACC_DB9 |
45193 | #define GC_CAC_ACC_DB9__ACCUMULATOR_31_0__SHIFT 0x0 |
45194 | #define GC_CAC_ACC_DB9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45195 | //GC_CAC_ACC_GDS0 |
45196 | #define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0 |
45197 | #define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45198 | //GC_CAC_ACC_GDS1 |
45199 | #define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0 |
45200 | #define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45201 | //GC_CAC_ACC_GDS2 |
45202 | #define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0 |
45203 | #define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45204 | //GC_CAC_ACC_GDS3 |
45205 | #define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0 |
45206 | #define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45207 | //GC_CAC_ACC_GDS4 |
45208 | #define GC_CAC_ACC_GDS4__ACCUMULATOR_31_0__SHIFT 0x0 |
45209 | #define GC_CAC_ACC_GDS4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45210 | //GC_CAC_ACC_GDS5 |
45211 | #define GC_CAC_ACC_GDS5__ACCUMULATOR_31_0__SHIFT 0x0 |
45212 | #define GC_CAC_ACC_GDS5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45213 | //GC_CAC_ACC_GDS6 |
45214 | #define GC_CAC_ACC_GDS6__ACCUMULATOR_31_0__SHIFT 0x0 |
45215 | #define GC_CAC_ACC_GDS6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45216 | //GC_CAC_ACC_PA0 |
45217 | #define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0 |
45218 | #define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45219 | //GC_CAC_ACC_PA1 |
45220 | #define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0 |
45221 | #define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45222 | //GC_CAC_ACC_PA2 |
45223 | #define GC_CAC_ACC_PA2__ACCUMULATOR_31_0__SHIFT 0x0 |
45224 | #define GC_CAC_ACC_PA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45225 | //GC_CAC_ACC_PA3 |
45226 | #define GC_CAC_ACC_PA3__ACCUMULATOR_31_0__SHIFT 0x0 |
45227 | #define GC_CAC_ACC_PA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45228 | //GC_CAC_ACC_PA4 |
45229 | #define GC_CAC_ACC_PA4__ACCUMULATOR_31_0__SHIFT 0x0 |
45230 | #define GC_CAC_ACC_PA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45231 | //GC_CAC_ACC_PA5 |
45232 | #define GC_CAC_ACC_PA5__ACCUMULATOR_31_0__SHIFT 0x0 |
45233 | #define GC_CAC_ACC_PA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45234 | //GC_CAC_ACC_PA6 |
45235 | #define GC_CAC_ACC_PA6__ACCUMULATOR_31_0__SHIFT 0x0 |
45236 | #define GC_CAC_ACC_PA6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45237 | //GC_CAC_ACC_PA7 |
45238 | #define GC_CAC_ACC_PA7__ACCUMULATOR_31_0__SHIFT 0x0 |
45239 | #define GC_CAC_ACC_PA7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45240 | //GC_CAC_ACC_PC0 |
45241 | #define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0 |
45242 | #define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45243 | //GC_CAC_ACC_SC0 |
45244 | #define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0 |
45245 | #define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45246 | //GC_CAC_ACC_SC1 |
45247 | #define GC_CAC_ACC_SC1__ACCUMULATOR_31_0__SHIFT 0x0 |
45248 | #define GC_CAC_ACC_SC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45249 | //GC_CAC_ACC_SC2 |
45250 | #define GC_CAC_ACC_SC2__ACCUMULATOR_31_0__SHIFT 0x0 |
45251 | #define GC_CAC_ACC_SC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45252 | //GC_CAC_ACC_SC3 |
45253 | #define GC_CAC_ACC_SC3__ACCUMULATOR_31_0__SHIFT 0x0 |
45254 | #define GC_CAC_ACC_SC3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45255 | //GC_CAC_ACC_SC4 |
45256 | #define GC_CAC_ACC_SC4__ACCUMULATOR_31_0__SHIFT 0x0 |
45257 | #define GC_CAC_ACC_SC4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45258 | //GC_CAC_ACC_SC5 |
45259 | #define GC_CAC_ACC_SC5__ACCUMULATOR_31_0__SHIFT 0x0 |
45260 | #define GC_CAC_ACC_SC5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45261 | //GC_CAC_ACC_SC6 |
45262 | #define GC_CAC_ACC_SC6__ACCUMULATOR_31_0__SHIFT 0x0 |
45263 | #define GC_CAC_ACC_SC6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45264 | //GC_CAC_ACC_SC7 |
45265 | #define GC_CAC_ACC_SC7__ACCUMULATOR_31_0__SHIFT 0x0 |
45266 | #define GC_CAC_ACC_SC7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45267 | //GC_CAC_ACC_SPI0 |
45268 | #define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0 |
45269 | #define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45270 | //GC_CAC_ACC_SPI1 |
45271 | #define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0 |
45272 | #define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45273 | //GC_CAC_ACC_SPI2 |
45274 | #define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0 |
45275 | #define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45276 | //GC_CAC_ACC_SPI3 |
45277 | #define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0 |
45278 | #define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45279 | //GC_CAC_ACC_SPI4 |
45280 | #define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0 |
45281 | #define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45282 | //GC_CAC_ACC_SPI5 |
45283 | #define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0 |
45284 | #define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45285 | //GC_CAC_ACC_SQ0_LOWER |
45286 | #define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
45287 | #define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45288 | //GC_CAC_ACC_SQ0_UPPER |
45289 | #define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
45290 | #define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT 0x8 |
45291 | #define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
45292 | #define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
45293 | //GC_CAC_ACC_SQ1_LOWER |
45294 | #define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
45295 | #define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45296 | //GC_CAC_ACC_SQ1_UPPER |
45297 | #define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
45298 | #define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT 0x8 |
45299 | #define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
45300 | #define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
45301 | //GC_CAC_ACC_SQ2_LOWER |
45302 | #define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
45303 | #define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45304 | //GC_CAC_ACC_SQ2_UPPER |
45305 | #define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
45306 | #define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT 0x8 |
45307 | #define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
45308 | #define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
45309 | //GC_CAC_ACC_SQ3_LOWER |
45310 | #define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
45311 | #define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45312 | //GC_CAC_ACC_SQ3_UPPER |
45313 | #define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
45314 | #define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT 0x8 |
45315 | #define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
45316 | #define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
45317 | //GC_CAC_ACC_SQ4_LOWER |
45318 | #define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
45319 | #define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45320 | //GC_CAC_ACC_SQ4_UPPER |
45321 | #define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
45322 | #define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT 0x8 |
45323 | #define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
45324 | #define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
45325 | //GC_CAC_ACC_SQ5_LOWER |
45326 | #define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
45327 | #define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45328 | //GC_CAC_ACC_SQ5_UPPER |
45329 | #define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
45330 | #define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT 0x8 |
45331 | #define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
45332 | #define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
45333 | //GC_CAC_ACC_SQ6_LOWER |
45334 | #define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
45335 | #define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45336 | //GC_CAC_ACC_SQ6_UPPER |
45337 | #define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
45338 | #define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT 0x8 |
45339 | #define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
45340 | #define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
45341 | //GC_CAC_ACC_SQ7_LOWER |
45342 | #define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
45343 | #define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45344 | //GC_CAC_ACC_SQ7_UPPER |
45345 | #define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
45346 | #define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT 0x8 |
45347 | #define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
45348 | #define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
45349 | //GC_CAC_ACC_SQ8_LOWER |
45350 | #define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
45351 | #define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45352 | //GC_CAC_ACC_SQ8_UPPER |
45353 | #define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
45354 | #define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT 0x8 |
45355 | #define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
45356 | #define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
45357 | //GC_CAC_ACC_SX0 |
45358 | #define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0 |
45359 | #define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45360 | //GC_CAC_ACC_SXRB0 |
45361 | #define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0 |
45362 | #define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45363 | //GC_CAC_ACC_TA0 |
45364 | #define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0 |
45365 | #define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45366 | //GC_CAC_ACC_TCP0 |
45367 | #define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0 |
45368 | #define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45369 | //GC_CAC_ACC_TCP1 |
45370 | #define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0 |
45371 | #define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45372 | //GC_CAC_ACC_TCP2 |
45373 | #define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0 |
45374 | #define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45375 | //GC_CAC_ACC_TCP3 |
45376 | #define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0 |
45377 | #define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45378 | //GC_CAC_ACC_TCP4 |
45379 | #define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0 |
45380 | #define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45381 | //GC_CAC_ACC_TCP5 |
45382 | #define GC_CAC_ACC_TCP5__ACCUMULATOR_31_0__SHIFT 0x0 |
45383 | #define GC_CAC_ACC_TCP5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45384 | //GC_CAC_ACC_TCP6 |
45385 | #define GC_CAC_ACC_TCP6__ACCUMULATOR_31_0__SHIFT 0x0 |
45386 | #define GC_CAC_ACC_TCP6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45387 | //GC_CAC_ACC_TCP7 |
45388 | #define GC_CAC_ACC_TCP7__ACCUMULATOR_31_0__SHIFT 0x0 |
45389 | #define GC_CAC_ACC_TCP7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45390 | //GC_CAC_ACC_TD0 |
45391 | #define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0 |
45392 | #define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45393 | //GC_CAC_ACC_TD1 |
45394 | #define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0 |
45395 | #define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45396 | //GC_CAC_ACC_TD2 |
45397 | #define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0 |
45398 | #define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45399 | //GC_CAC_ACC_TD3 |
45400 | #define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0 |
45401 | #define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45402 | //GC_CAC_ACC_TD4 |
45403 | #define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0 |
45404 | #define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45405 | //GC_CAC_ACC_TD5 |
45406 | #define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0 |
45407 | #define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45408 | //GC_CAC_ACC_TD6 |
45409 | #define GC_CAC_ACC_TD6__ACCUMULATOR_31_0__SHIFT 0x0 |
45410 | #define GC_CAC_ACC_TD6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45411 | //GC_CAC_ACC_TD7 |
45412 | #define GC_CAC_ACC_TD7__ACCUMULATOR_31_0__SHIFT 0x0 |
45413 | #define GC_CAC_ACC_TD7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45414 | //GC_CAC_ACC_TD8 |
45415 | #define GC_CAC_ACC_TD8__ACCUMULATOR_31_0__SHIFT 0x0 |
45416 | #define GC_CAC_ACC_TD8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45417 | //GC_CAC_ACC_TD9 |
45418 | #define GC_CAC_ACC_TD9__ACCUMULATOR_31_0__SHIFT 0x0 |
45419 | #define GC_CAC_ACC_TD9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45420 | //GC_CAC_ACC_TD10 |
45421 | #define GC_CAC_ACC_TD10__ACCUMULATOR_31_0__SHIFT 0x0 |
45422 | #define GC_CAC_ACC_TD10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45423 | //GC_CAC_ACC_RMI0 |
45424 | #define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0 |
45425 | #define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45426 | //GC_CAC_ACC_RMI1 |
45427 | #define GC_CAC_ACC_RMI1__ACCUMULATOR_31_0__SHIFT 0x0 |
45428 | #define GC_CAC_ACC_RMI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45429 | //GC_CAC_ACC_RMI2 |
45430 | #define GC_CAC_ACC_RMI2__ACCUMULATOR_31_0__SHIFT 0x0 |
45431 | #define GC_CAC_ACC_RMI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45432 | //GC_CAC_ACC_RMI3 |
45433 | #define GC_CAC_ACC_RMI3__ACCUMULATOR_31_0__SHIFT 0x0 |
45434 | #define GC_CAC_ACC_RMI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45435 | //GC_CAC_ACC_EA0 |
45436 | #define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0 |
45437 | #define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45438 | //GC_CAC_ACC_EA1 |
45439 | #define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0 |
45440 | #define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45441 | //GC_CAC_ACC_EA2 |
45442 | #define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0 |
45443 | #define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45444 | //GC_CAC_ACC_EA3 |
45445 | #define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0 |
45446 | #define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45447 | //GC_CAC_ACC_EA4 |
45448 | #define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0 |
45449 | #define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45450 | //GC_CAC_ACC_EA5 |
45451 | #define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0 |
45452 | #define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45453 | //GC_CAC_ACC_UTCL2_ATCL20 |
45454 | #define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0 |
45455 | #define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45456 | //GC_CAC_ACC_UTCL2_ATCL21 |
45457 | #define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0 |
45458 | #define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45459 | //GC_CAC_ACC_UTCL2_ATCL22 |
45460 | #define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0 |
45461 | #define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45462 | //GC_CAC_ACC_UTCL2_ATCL23 |
45463 | #define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0 |
45464 | #define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45465 | //GC_CAC_ACC_UTCL2_ATCL24 |
45466 | #define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0 |
45467 | #define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45468 | //GC_CAC_ACC_UTCL2_ROUTER0 |
45469 | #define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0 |
45470 | #define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45471 | //GC_CAC_ACC_UTCL2_ROUTER1 |
45472 | #define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0 |
45473 | #define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45474 | //GC_CAC_ACC_UTCL2_ROUTER2 |
45475 | #define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0 |
45476 | #define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45477 | //GC_CAC_ACC_UTCL2_ROUTER3 |
45478 | #define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0 |
45479 | #define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45480 | //GC_CAC_ACC_UTCL2_ROUTER4 |
45481 | #define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0 |
45482 | #define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45483 | //GC_CAC_ACC_UTCL2_ROUTER5 |
45484 | #define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0 |
45485 | #define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45486 | //GC_CAC_ACC_UTCL2_ROUTER6 |
45487 | #define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0 |
45488 | #define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45489 | //GC_CAC_ACC_UTCL2_ROUTER7 |
45490 | #define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0 |
45491 | #define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45492 | //GC_CAC_ACC_UTCL2_ROUTER8 |
45493 | #define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0 |
45494 | #define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45495 | //GC_CAC_ACC_UTCL2_ROUTER9 |
45496 | #define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0 |
45497 | #define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45498 | //GC_CAC_ACC_UTCL2_VML20 |
45499 | #define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0 |
45500 | #define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45501 | //GC_CAC_ACC_UTCL2_VML21 |
45502 | #define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0 |
45503 | #define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45504 | //GC_CAC_ACC_UTCL2_VML22 |
45505 | #define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0 |
45506 | #define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45507 | //GC_CAC_ACC_UTCL2_VML23 |
45508 | #define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0 |
45509 | #define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45510 | //GC_CAC_ACC_UTCL2_VML24 |
45511 | #define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0 |
45512 | #define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45513 | //GC_CAC_ACC_UTCL2_WALKER0 |
45514 | #define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0 |
45515 | #define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45516 | //GC_CAC_ACC_UTCL2_WALKER1 |
45517 | #define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0 |
45518 | #define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45519 | //GC_CAC_ACC_UTCL2_WALKER2 |
45520 | #define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0 |
45521 | #define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45522 | //GC_CAC_ACC_UTCL2_WALKER3 |
45523 | #define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0 |
45524 | #define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45525 | //GC_CAC_ACC_UTCL2_WALKER4 |
45526 | #define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0 |
45527 | #define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45528 | //GC_CAC_ACC_CU0 |
45529 | #define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0 |
45530 | #define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45531 | //GC_CAC_ACC_UTCL10 |
45532 | #define GC_CAC_ACC_UTCL10__ACCUMULATOR_31_0__SHIFT 0x0 |
45533 | #define GC_CAC_ACC_UTCL10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45534 | //GC_CAC_ACC_CHC0 |
45535 | #define GC_CAC_ACC_CHC0__ACCUMULATOR_31_0__SHIFT 0x0 |
45536 | #define GC_CAC_ACC_CHC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45537 | //GC_CAC_ACC_CHC1 |
45538 | #define GC_CAC_ACC_CHC1__ACCUMULATOR_31_0__SHIFT 0x0 |
45539 | #define GC_CAC_ACC_CHC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45540 | //GC_CAC_ACC_CHC2 |
45541 | #define GC_CAC_ACC_CHC2__ACCUMULATOR_31_0__SHIFT 0x0 |
45542 | #define GC_CAC_ACC_CHC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45543 | //GC_CAC_ACC_GE0 |
45544 | #define GC_CAC_ACC_GE0__ACCUMULATOR_31_0__SHIFT 0x0 |
45545 | #define GC_CAC_ACC_GE0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45546 | //GC_CAC_ACC_GE1 |
45547 | #define GC_CAC_ACC_GE1__ACCUMULATOR_31_0__SHIFT 0x0 |
45548 | #define GC_CAC_ACC_GE1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45549 | //GC_CAC_ACC_GE2 |
45550 | #define GC_CAC_ACC_GE2__ACCUMULATOR_31_0__SHIFT 0x0 |
45551 | #define GC_CAC_ACC_GE2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45552 | //GC_CAC_ACC_GE3 |
45553 | #define GC_CAC_ACC_GE3__ACCUMULATOR_31_0__SHIFT 0x0 |
45554 | #define GC_CAC_ACC_GE3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45555 | //GC_CAC_ACC_GE4 |
45556 | #define GC_CAC_ACC_GE4__ACCUMULATOR_31_0__SHIFT 0x0 |
45557 | #define GC_CAC_ACC_GE4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45558 | //GC_CAC_ACC_GE5 |
45559 | #define GC_CAC_ACC_GE5__ACCUMULATOR_31_0__SHIFT 0x0 |
45560 | #define GC_CAC_ACC_GE5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45561 | //GC_CAC_ACC_GE6 |
45562 | #define GC_CAC_ACC_GE6__ACCUMULATOR_31_0__SHIFT 0x0 |
45563 | #define GC_CAC_ACC_GE6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45564 | //GC_CAC_ACC_GE7 |
45565 | #define GC_CAC_ACC_GE7__ACCUMULATOR_31_0__SHIFT 0x0 |
45566 | #define GC_CAC_ACC_GE7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45567 | //GC_CAC_ACC_GE8 |
45568 | #define GC_CAC_ACC_GE8__ACCUMULATOR_31_0__SHIFT 0x0 |
45569 | #define GC_CAC_ACC_GE8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45570 | //GC_CAC_ACC_GE9 |
45571 | #define GC_CAC_ACC_GE9__ACCUMULATOR_31_0__SHIFT 0x0 |
45572 | #define GC_CAC_ACC_GE9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45573 | //GC_CAC_ACC_GE10 |
45574 | #define GC_CAC_ACC_GE10__ACCUMULATOR_31_0__SHIFT 0x0 |
45575 | #define GC_CAC_ACC_GE10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45576 | //GC_CAC_ACC_GE11 |
45577 | #define GC_CAC_ACC_GE11__ACCUMULATOR_31_0__SHIFT 0x0 |
45578 | #define GC_CAC_ACC_GE11__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45579 | //GC_CAC_ACC_GE12 |
45580 | #define GC_CAC_ACC_GE12__ACCUMULATOR_31_0__SHIFT 0x0 |
45581 | #define GC_CAC_ACC_GE12__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45582 | //GC_CAC_ACC_GE13 |
45583 | #define GC_CAC_ACC_GE13__ACCUMULATOR_31_0__SHIFT 0x0 |
45584 | #define GC_CAC_ACC_GE13__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45585 | //GC_CAC_ACC_GE14 |
45586 | #define GC_CAC_ACC_GE14__ACCUMULATOR_31_0__SHIFT 0x0 |
45587 | #define GC_CAC_ACC_GE14__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45588 | //GC_CAC_ACC_GE15 |
45589 | #define GC_CAC_ACC_GE15__ACCUMULATOR_31_0__SHIFT 0x0 |
45590 | #define GC_CAC_ACC_GE15__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45591 | //GC_CAC_ACC_GE16 |
45592 | #define GC_CAC_ACC_GE16__ACCUMULATOR_31_0__SHIFT 0x0 |
45593 | #define GC_CAC_ACC_GE16__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45594 | //GC_CAC_ACC_GE17 |
45595 | #define GC_CAC_ACC_GE17__ACCUMULATOR_31_0__SHIFT 0x0 |
45596 | #define GC_CAC_ACC_GE17__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45597 | //GC_CAC_ACC_GE18 |
45598 | #define GC_CAC_ACC_GE18__ACCUMULATOR_31_0__SHIFT 0x0 |
45599 | #define GC_CAC_ACC_GE18__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45600 | //GC_CAC_ACC_GE19 |
45601 | #define GC_CAC_ACC_GE19__ACCUMULATOR_31_0__SHIFT 0x0 |
45602 | #define GC_CAC_ACC_GE19__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45603 | //GC_CAC_ACC_GE20 |
45604 | #define GC_CAC_ACC_GE20__ACCUMULATOR_31_0__SHIFT 0x0 |
45605 | #define GC_CAC_ACC_GE20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45606 | //GC_CAC_ACC_PMM0 |
45607 | #define GC_CAC_ACC_PMM0__ACCUMULATOR_31_0__SHIFT 0x0 |
45608 | #define GC_CAC_ACC_PMM0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45609 | //GC_CAC_ACC_GL2C0 |
45610 | #define GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0__SHIFT 0x0 |
45611 | #define GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45612 | //GC_CAC_ACC_GL2C1 |
45613 | #define GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0__SHIFT 0x0 |
45614 | #define GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45615 | //GC_CAC_ACC_GL2C2 |
45616 | #define GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0__SHIFT 0x0 |
45617 | #define GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45618 | //GC_CAC_ACC_GL2C3 |
45619 | #define GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0__SHIFT 0x0 |
45620 | #define GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45621 | //GC_CAC_ACC_GL2C4 |
45622 | #define GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0__SHIFT 0x0 |
45623 | #define GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45624 | //GC_CAC_ACC_GUS0 |
45625 | #define GC_CAC_ACC_GUS0__ACCUMULATOR_31_0__SHIFT 0x0 |
45626 | #define GC_CAC_ACC_GUS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45627 | //GC_CAC_ACC_GUS1 |
45628 | #define GC_CAC_ACC_GUS1__ACCUMULATOR_31_0__SHIFT 0x0 |
45629 | #define GC_CAC_ACC_GUS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45630 | //GC_CAC_ACC_GUS2 |
45631 | #define GC_CAC_ACC_GUS2__ACCUMULATOR_31_0__SHIFT 0x0 |
45632 | #define GC_CAC_ACC_GUS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45633 | //GC_CAC_ACC_PH0 |
45634 | #define GC_CAC_ACC_PH0__ACCUMULATOR_31_0__SHIFT 0x0 |
45635 | #define GC_CAC_ACC_PH0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45636 | //GC_CAC_ACC_PH1 |
45637 | #define GC_CAC_ACC_PH1__ACCUMULATOR_31_0__SHIFT 0x0 |
45638 | #define GC_CAC_ACC_PH1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45639 | //GC_CAC_ACC_PH2 |
45640 | #define GC_CAC_ACC_PH2__ACCUMULATOR_31_0__SHIFT 0x0 |
45641 | #define GC_CAC_ACC_PH2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45642 | //GC_CAC_ACC_PH3 |
45643 | #define GC_CAC_ACC_PH3__ACCUMULATOR_31_0__SHIFT 0x0 |
45644 | #define GC_CAC_ACC_PH3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45645 | //GC_CAC_ACC_PH4 |
45646 | #define GC_CAC_ACC_PH4__ACCUMULATOR_31_0__SHIFT 0x0 |
45647 | #define GC_CAC_ACC_PH4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45648 | //GC_CAC_ACC_PH5 |
45649 | #define GC_CAC_ACC_PH5__ACCUMULATOR_31_0__SHIFT 0x0 |
45650 | #define GC_CAC_ACC_PH5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45651 | //GC_CAC_ACC_PH6 |
45652 | #define GC_CAC_ACC_PH6__ACCUMULATOR_31_0__SHIFT 0x0 |
45653 | #define GC_CAC_ACC_PH6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45654 | //GC_CAC_ACC_PH7 |
45655 | #define GC_CAC_ACC_PH7__ACCUMULATOR_31_0__SHIFT 0x0 |
45656 | #define GC_CAC_ACC_PH7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45657 | //GC_CAC_ACC_SDMA0 |
45658 | #define GC_CAC_ACC_SDMA0__ACCUMULATOR_31_0__SHIFT 0x0 |
45659 | #define GC_CAC_ACC_SDMA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45660 | //GC_CAC_ACC_SDMA1 |
45661 | #define GC_CAC_ACC_SDMA1__ACCUMULATOR_31_0__SHIFT 0x0 |
45662 | #define GC_CAC_ACC_SDMA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45663 | //GC_CAC_ACC_SDMA2 |
45664 | #define GC_CAC_ACC_SDMA2__ACCUMULATOR_31_0__SHIFT 0x0 |
45665 | #define GC_CAC_ACC_SDMA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45666 | //GC_CAC_ACC_SDMA3 |
45667 | #define GC_CAC_ACC_SDMA3__ACCUMULATOR_31_0__SHIFT 0x0 |
45668 | #define GC_CAC_ACC_SDMA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45669 | //GC_CAC_ACC_SDMA4 |
45670 | #define GC_CAC_ACC_SDMA4__ACCUMULATOR_31_0__SHIFT 0x0 |
45671 | #define GC_CAC_ACC_SDMA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45672 | //GC_CAC_ACC_SDMA5 |
45673 | #define GC_CAC_ACC_SDMA5__ACCUMULATOR_31_0__SHIFT 0x0 |
45674 | #define GC_CAC_ACC_SDMA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45675 | //GC_CAC_ACC_SDMA6 |
45676 | #define GC_CAC_ACC_SDMA6__ACCUMULATOR_31_0__SHIFT 0x0 |
45677 | #define GC_CAC_ACC_SDMA6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45678 | //GC_CAC_ACC_SDMA7 |
45679 | #define GC_CAC_ACC_SDMA7__ACCUMULATOR_31_0__SHIFT 0x0 |
45680 | #define GC_CAC_ACC_SDMA7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45681 | //GC_CAC_ACC_SDMA8 |
45682 | #define GC_CAC_ACC_SDMA8__ACCUMULATOR_31_0__SHIFT 0x0 |
45683 | #define GC_CAC_ACC_SDMA8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45684 | //GC_CAC_ACC_SDMA9 |
45685 | #define GC_CAC_ACC_SDMA9__ACCUMULATOR_31_0__SHIFT 0x0 |
45686 | #define GC_CAC_ACC_SDMA9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45687 | //GC_CAC_ACC_SDMA10 |
45688 | #define GC_CAC_ACC_SDMA10__ACCUMULATOR_31_0__SHIFT 0x0 |
45689 | #define GC_CAC_ACC_SDMA10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45690 | //GC_CAC_ACC_SDMA11 |
45691 | #define GC_CAC_ACC_SDMA11__ACCUMULATOR_31_0__SHIFT 0x0 |
45692 | #define GC_CAC_ACC_SDMA11__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45693 | //GC_CAC_ACC_SP0_LOWER |
45694 | #define GC_CAC_ACC_SP0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
45695 | #define GC_CAC_ACC_SP0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45696 | //GC_CAC_ACC_SP0_UPPER |
45697 | #define GC_CAC_ACC_SP0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
45698 | #define GC_CAC_ACC_SP0_UPPER__UNUSED_0__SHIFT 0x8 |
45699 | #define GC_CAC_ACC_SP0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
45700 | #define GC_CAC_ACC_SP0_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
45701 | //GC_CAC_ACC_SP1_LOWER |
45702 | #define GC_CAC_ACC_SP1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
45703 | #define GC_CAC_ACC_SP1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45704 | //GC_CAC_ACC_SP1_UPPER |
45705 | #define GC_CAC_ACC_SP1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
45706 | #define GC_CAC_ACC_SP1_UPPER__UNUSED_0__SHIFT 0x8 |
45707 | #define GC_CAC_ACC_SP1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
45708 | #define GC_CAC_ACC_SP1_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
45709 | //GC_CAC_ACC_SP2_LOWER |
45710 | #define GC_CAC_ACC_SP2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 |
45711 | #define GC_CAC_ACC_SP2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45712 | //GC_CAC_ACC_SP2_UPPER |
45713 | #define GC_CAC_ACC_SP2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 |
45714 | #define GC_CAC_ACC_SP2_UPPER__UNUSED_0__SHIFT 0x8 |
45715 | #define GC_CAC_ACC_SP2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL |
45716 | #define GC_CAC_ACC_SP2_UPPER__UNUSED_0_MASK 0xFFFFFF00L |
45717 | //GC_CAC_ACC_GL1C0 |
45718 | #define GC_CAC_ACC_GL1C0__ACCUMULATOR_31_0__SHIFT 0x0 |
45719 | #define GC_CAC_ACC_GL1C0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45720 | //GC_CAC_ACC_GL1C1 |
45721 | #define GC_CAC_ACC_GL1C1__ACCUMULATOR_31_0__SHIFT 0x0 |
45722 | #define GC_CAC_ACC_GL1C1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45723 | //GC_CAC_ACC_GL1C2 |
45724 | #define GC_CAC_ACC_GL1C2__ACCUMULATOR_31_0__SHIFT 0x0 |
45725 | #define GC_CAC_ACC_GL1C2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45726 | //GC_CAC_ACC_GL1C3 |
45727 | #define GC_CAC_ACC_GL1C3__ACCUMULATOR_31_0__SHIFT 0x0 |
45728 | #define GC_CAC_ACC_GL1C3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45729 | //GC_CAC_ACC_GL1C4 |
45730 | #define GC_CAC_ACC_GL1C4__ACCUMULATOR_31_0__SHIFT 0x0 |
45731 | #define GC_CAC_ACC_GL1C4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45732 | //GC_CAC_ACC_SQC0 |
45733 | #define GC_CAC_ACC_SQC0__ACCUMULATOR_31_0__SHIFT 0x0 |
45734 | #define GC_CAC_ACC_SQC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45735 | //GC_CAC_ACC_SQC1 |
45736 | #define GC_CAC_ACC_SQC1__ACCUMULATOR_31_0__SHIFT 0x0 |
45737 | #define GC_CAC_ACC_SQC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45738 | //GC_CAC_ACC_SQC2 |
45739 | #define GC_CAC_ACC_SQC2__ACCUMULATOR_31_0__SHIFT 0x0 |
45740 | #define GC_CAC_ACC_SQC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45741 | //GC_CAC_ACC_RLC0 |
45742 | #define GC_CAC_ACC_RLC0__ACCUMULATOR_31_0__SHIFT 0x0 |
45743 | #define GC_CAC_ACC_RLC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
45744 | //GC_CAC_OVRD_BCI |
45745 | #define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0 |
45746 | #define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2 |
45747 | #define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L |
45748 | #define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL |
45749 | //GC_CAC_OVRD_CB |
45750 | #define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0 |
45751 | #define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0xa |
45752 | #define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x000003FFL |
45753 | #define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000FFC00L |
45754 | //GC_CAC_OVRD_CP |
45755 | #define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0 |
45756 | #define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3 |
45757 | #define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L |
45758 | #define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L |
45759 | //GC_CAC_OVRD_DB |
45760 | #define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0 |
45761 | #define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0xa |
45762 | #define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x000003FFL |
45763 | #define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000FFC00L |
45764 | //GC_CAC_OVRD_GDS |
45765 | #define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0 |
45766 | #define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x5 |
45767 | #define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000001FL |
45768 | #define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000003E0L |
45769 | //GC_CAC_OVRD_LDS |
45770 | #define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0 |
45771 | #define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x9 |
45772 | #define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x000001FFL |
45773 | #define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x0003FE00L |
45774 | //GC_CAC_OVRD_PA |
45775 | #define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0 |
45776 | #define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x8 |
45777 | #define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x000000FFL |
45778 | #define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000FF00L |
45779 | //GC_CAC_OVRD_PC |
45780 | #define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0 |
45781 | #define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1 |
45782 | #define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L |
45783 | #define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L |
45784 | //GC_CAC_OVRD_SC |
45785 | #define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0 |
45786 | #define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x8 |
45787 | #define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x000000FFL |
45788 | #define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x0000FF00L |
45789 | //GC_CAC_OVRD_SPI |
45790 | #define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0 |
45791 | #define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6 |
45792 | #define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL |
45793 | #define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L |
45794 | //GC_CAC_OVRD_CU |
45795 | #define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0 |
45796 | #define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1 |
45797 | #define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L |
45798 | #define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L |
45799 | //GC_CAC_OVRD_SQ |
45800 | #define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0 |
45801 | #define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x8 |
45802 | #define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000000FFL |
45803 | #define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0000FF00L |
45804 | //GC_CAC_OVRD_SX |
45805 | #define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0 |
45806 | #define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1 |
45807 | #define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L |
45808 | #define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L |
45809 | //GC_CAC_OVRD_SXRB |
45810 | #define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0 |
45811 | #define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1 |
45812 | #define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L |
45813 | #define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L |
45814 | //GC_CAC_OVRD_TA |
45815 | #define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0 |
45816 | #define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1 |
45817 | #define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L |
45818 | #define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L |
45819 | //GC_CAC_OVRD_TCP |
45820 | #define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0 |
45821 | #define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x8 |
45822 | #define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x000000FFL |
45823 | #define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x0000FF00L |
45824 | //GC_CAC_OVRD_TD |
45825 | #define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0 |
45826 | #define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0xb |
45827 | #define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x000007FFL |
45828 | #define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x003FF800L |
45829 | //GC_CAC_OVRD_RMI |
45830 | #define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0 |
45831 | #define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x4 |
45832 | #define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x0000000FL |
45833 | #define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x000000F0L |
45834 | //GC_CAC_OVRD_EA |
45835 | #define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0 |
45836 | #define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6 |
45837 | #define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL |
45838 | #define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L |
45839 | //GC_CAC_OVRD_UTCL2_ATCL2 |
45840 | #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0 |
45841 | #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5 |
45842 | #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL |
45843 | #define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L |
45844 | //GC_CAC_OVRD_UTCL2_ROUTER |
45845 | #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0 |
45846 | #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa |
45847 | #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL |
45848 | #define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L |
45849 | //GC_CAC_OVRD_UTCL2_VML2 |
45850 | #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0 |
45851 | #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5 |
45852 | #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL |
45853 | #define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L |
45854 | //GC_CAC_OVRD_UTCL2_WALKER |
45855 | #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0 |
45856 | #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5 |
45857 | #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL |
45858 | #define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L |
45859 | //GC_CAC_OVRD_SP |
45860 | #define GC_CAC_OVRD_SP__OVRRD_SELECT__SHIFT 0x0 |
45861 | #define GC_CAC_OVRD_SP__OVRRD_VALUE__SHIFT 0x3 |
45862 | #define GC_CAC_OVRD_SP__OVRRD_SELECT_MASK 0x00000007L |
45863 | #define GC_CAC_OVRD_SP__OVRRD_VALUE_MASK 0x00000038L |
45864 | //GC_CAC_OVRD_UTCL1 |
45865 | #define GC_CAC_OVRD_UTCL1__OVRRD_SELECT__SHIFT 0x0 |
45866 | #define GC_CAC_OVRD_UTCL1__OVRRD_VALUE__SHIFT 0x1 |
45867 | #define GC_CAC_OVRD_UTCL1__OVRRD_SELECT_MASK 0x00000001L |
45868 | #define GC_CAC_OVRD_UTCL1__OVRRD_VALUE_MASK 0x00000002L |
45869 | //GC_CAC_OVRD_CHC |
45870 | #define GC_CAC_OVRD_CHC__OVRRD_SELECT__SHIFT 0x0 |
45871 | #define GC_CAC_OVRD_CHC__OVRRD_VALUE__SHIFT 0x3 |
45872 | #define GC_CAC_OVRD_CHC__OVRRD_SELECT_MASK 0x00000007L |
45873 | #define GC_CAC_OVRD_CHC__OVRRD_VALUE_MASK 0x00000038L |
45874 | //GC_CAC_OVRD_GE |
45875 | #define GC_CAC_OVRD_GE__OVRRD_SELECT__SHIFT 0x0 |
45876 | #define GC_CAC_OVRD_GE__OVRRD_VALUE__SHIFT 0x10 |
45877 | #define GC_CAC_OVRD_GE__OVRRD_SELECT_MASK 0x0000FFFFL |
45878 | #define GC_CAC_OVRD_GE__OVRRD_VALUE_MASK 0xFFFF0000L |
45879 | //GC_CAC_OVRD_PMM |
45880 | #define GC_CAC_OVRD_PMM__OVRRD_SELECT__SHIFT 0x0 |
45881 | #define GC_CAC_OVRD_PMM__OVRRD_VALUE__SHIFT 0x1 |
45882 | #define GC_CAC_OVRD_PMM__OVRRD_SELECT_MASK 0x00000001L |
45883 | #define GC_CAC_OVRD_PMM__OVRRD_VALUE_MASK 0x00000002L |
45884 | //GC_CAC_OVRD_GL2C |
45885 | #define GC_CAC_OVRD_GL2C__OVRRD_SELECT__SHIFT 0x0 |
45886 | #define GC_CAC_OVRD_GL2C__OVRRD_VALUE__SHIFT 0x5 |
45887 | #define GC_CAC_OVRD_GL2C__OVRRD_SELECT_MASK 0x0000001FL |
45888 | #define GC_CAC_OVRD_GL2C__OVRRD_VALUE_MASK 0x000003E0L |
45889 | //GC_CAC_OVRD_GUS |
45890 | #define GC_CAC_OVRD_GUS__OVRRD_SELECT__SHIFT 0x0 |
45891 | #define GC_CAC_OVRD_GUS__OVRRD_VALUE__SHIFT 0x3 |
45892 | #define GC_CAC_OVRD_GUS__OVRRD_SELECT_MASK 0x00000007L |
45893 | #define GC_CAC_OVRD_GUS__OVRRD_VALUE_MASK 0x00000038L |
45894 | //GC_CAC_OVRD_PH |
45895 | #define GC_CAC_OVRD_PH__OVRRD_SELECT__SHIFT 0x0 |
45896 | #define GC_CAC_OVRD_PH__OVRRD_VALUE__SHIFT 0x8 |
45897 | #define GC_CAC_OVRD_PH__OVRRD_SELECT_MASK 0x000000FFL |
45898 | #define GC_CAC_OVRD_PH__OVRRD_VALUE_MASK 0x0000FF00L |
45899 | //GC_CAC_OVRD_SDMA |
45900 | #define GC_CAC_OVRD_SDMA__OVRRD_SELECT__SHIFT 0x0 |
45901 | #define GC_CAC_OVRD_SDMA__OVRRD_VALUE__SHIFT 0xc |
45902 | #define GC_CAC_OVRD_SDMA__OVRRD_SELECT_MASK 0x00000FFFL |
45903 | #define GC_CAC_OVRD_SDMA__OVRRD_VALUE_MASK 0x00FFF000L |
45904 | //GC_CAC_OVRD_GL1C |
45905 | #define GC_CAC_OVRD_GL1C__OVRRD_SELECT__SHIFT 0x0 |
45906 | #define GC_CAC_OVRD_GL1C__OVRRD_VALUE__SHIFT 0x5 |
45907 | #define GC_CAC_OVRD_GL1C__OVRRD_SELECT_MASK 0x0000001FL |
45908 | #define GC_CAC_OVRD_GL1C__OVRRD_VALUE_MASK 0x000003E0L |
45909 | //GC_CAC_OVRD_SQC |
45910 | #define GC_CAC_OVRD_SQC__OVRRD_SELECT__SHIFT 0x0 |
45911 | #define GC_CAC_OVRD_SQC__OVRRD_VALUE__SHIFT 0x3 |
45912 | #define GC_CAC_OVRD_SQC__OVRRD_SELECT_MASK 0x00000007L |
45913 | #define GC_CAC_OVRD_SQC__OVRRD_VALUE_MASK 0x00000038L |
45914 | //GC_CAC_OVRD_RLC |
45915 | #define GC_CAC_OVRD_RLC__OVRRD_SELECT__SHIFT 0x0 |
45916 | #define GC_CAC_OVRD_RLC__OVRRD_VALUE__SHIFT 0x1 |
45917 | #define GC_CAC_OVRD_RLC__OVRRD_SELECT_MASK 0x00000001L |
45918 | #define GC_CAC_OVRD_RLC__OVRRD_VALUE_MASK 0x00000002L |
45919 | //GC_CAC_OVRD_GE_HI |
45920 | #define GC_CAC_OVRD_GE_HI__OVRRD_SELECT__SHIFT 0x0 |
45921 | #define GC_CAC_OVRD_GE_HI__OVRRD_VALUE__SHIFT 0x10 |
45922 | #define GC_CAC_OVRD_GE_HI__OVRRD_SELECT_MASK 0x0000FFFFL |
45923 | #define GC_CAC_OVRD_GE_HI__OVRRD_VALUE_MASK 0xFFFF0000L |
45924 | //RELEASE_TO_STALL_LUT_1_8 |
45925 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT 0x0 |
45926 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT 0x4 |
45927 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT 0x8 |
45928 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT 0xc |
45929 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT 0x10 |
45930 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT 0x14 |
45931 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT 0x18 |
45932 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT 0x1c |
45933 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK 0x00000007L |
45934 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK 0x00000070L |
45935 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK 0x00000700L |
45936 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK 0x00007000L |
45937 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK 0x00070000L |
45938 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK 0x00700000L |
45939 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK 0x07000000L |
45940 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK 0x70000000L |
45941 | //RELEASE_TO_STALL_LUT_9_16 |
45942 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT 0x0 |
45943 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT 0x4 |
45944 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT 0x8 |
45945 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT 0xc |
45946 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT 0x10 |
45947 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT 0x14 |
45948 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT 0x18 |
45949 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT 0x1c |
45950 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK 0x00000007L |
45951 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK 0x00000070L |
45952 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK 0x00000700L |
45953 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK 0x00007000L |
45954 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK 0x00070000L |
45955 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK 0x00700000L |
45956 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK 0x07000000L |
45957 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK 0x70000000L |
45958 | //RELEASE_TO_STALL_LUT_17_20 |
45959 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT 0x0 |
45960 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT 0x4 |
45961 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT 0x8 |
45962 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT 0xc |
45963 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK 0x00000007L |
45964 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK 0x00000070L |
45965 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK 0x00000700L |
45966 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK 0x00007000L |
45967 | //STALL_TO_RELEASE_LUT_1_4 |
45968 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0 |
45969 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8 |
45970 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10 |
45971 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18 |
45972 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK 0x0000001FL |
45973 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK 0x00001F00L |
45974 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK 0x001F0000L |
45975 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK 0x1F000000L |
45976 | //STALL_TO_RELEASE_LUT_5_7 |
45977 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0 |
45978 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8 |
45979 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10 |
45980 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK 0x0000001FL |
45981 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK 0x00001F00L |
45982 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK 0x001F0000L |
45983 | //STALL_TO_PWRBRK_LUT_1_4 |
45984 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0 |
45985 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8 |
45986 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10 |
45987 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18 |
45988 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1_MASK 0x00000007L |
45989 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2_MASK 0x00000700L |
45990 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3_MASK 0x00070000L |
45991 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4_MASK 0x07000000L |
45992 | //STALL_TO_PWRBRK_LUT_5_7 |
45993 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0 |
45994 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8 |
45995 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10 |
45996 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5_MASK 0x00000007L |
45997 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6_MASK 0x00000700L |
45998 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7_MASK 0x00070000L |
45999 | //PWRBRK_STALL_TO_RELEASE_LUT_1_4 |
46000 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0 |
46001 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8 |
46002 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10 |
46003 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18 |
46004 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK 0x0000001FL |
46005 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK 0x00001F00L |
46006 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK 0x001F0000L |
46007 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK 0x1F000000L |
46008 | //PWRBRK_STALL_TO_RELEASE_LUT_5_7 |
46009 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0 |
46010 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8 |
46011 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10 |
46012 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK 0x0000001FL |
46013 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK 0x00001F00L |
46014 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK 0x001F0000L |
46015 | //PWRBRK_RELEASE_TO_STALL_LUT_1_8 |
46016 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT 0x0 |
46017 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT 0x4 |
46018 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT 0x8 |
46019 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT 0xc |
46020 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT 0x10 |
46021 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT 0x14 |
46022 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT 0x18 |
46023 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT 0x1c |
46024 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK 0x00000007L |
46025 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK 0x00000070L |
46026 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK 0x00000700L |
46027 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK 0x00007000L |
46028 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK 0x00070000L |
46029 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK 0x00700000L |
46030 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK 0x07000000L |
46031 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK 0x70000000L |
46032 | //PWRBRK_RELEASE_TO_STALL_LUT_9_16 |
46033 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT 0x0 |
46034 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT 0x4 |
46035 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT 0x8 |
46036 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT 0xc |
46037 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT 0x10 |
46038 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT 0x14 |
46039 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT 0x18 |
46040 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT 0x1c |
46041 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK 0x00000007L |
46042 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK 0x00000070L |
46043 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK 0x00000700L |
46044 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK 0x00007000L |
46045 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK 0x00070000L |
46046 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK 0x00700000L |
46047 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK 0x07000000L |
46048 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK 0x70000000L |
46049 | //PWRBRK_RELEASE_TO_STALL_LUT_17_20 |
46050 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT 0x0 |
46051 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT 0x4 |
46052 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT 0x8 |
46053 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT 0xc |
46054 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK 0x00000007L |
46055 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK 0x00000070L |
46056 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK 0x00000700L |
46057 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK 0x00007000L |
46058 | //FIXED_PATTERN_PERF_COUNTER_1 |
46059 | #define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER__SHIFT 0x0 |
46060 | #define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER_MASK 0x0001FFFFL |
46061 | //FIXED_PATTERN_PERF_COUNTER_2 |
46062 | #define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER__SHIFT 0x0 |
46063 | #define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER_MASK 0x0001FFFFL |
46064 | //FIXED_PATTERN_PERF_COUNTER_3 |
46065 | #define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER__SHIFT 0x0 |
46066 | #define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER_MASK 0x0001FFFFL |
46067 | //FIXED_PATTERN_PERF_COUNTER_4 |
46068 | #define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER__SHIFT 0x0 |
46069 | #define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER_MASK 0x0001FFFFL |
46070 | //FIXED_PATTERN_PERF_COUNTER_5 |
46071 | #define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER__SHIFT 0x0 |
46072 | #define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER_MASK 0x0001FFFFL |
46073 | //FIXED_PATTERN_PERF_COUNTER_6 |
46074 | #define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER__SHIFT 0x0 |
46075 | #define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER_MASK 0x0001FFFFL |
46076 | //FIXED_PATTERN_PERF_COUNTER_7 |
46077 | #define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER__SHIFT 0x0 |
46078 | #define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER_MASK 0x0001FFFFL |
46079 | //FIXED_PATTERN_PERF_COUNTER_8 |
46080 | #define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER__SHIFT 0x0 |
46081 | #define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER_MASK 0x0001FFFFL |
46082 | //FIXED_PATTERN_PERF_COUNTER_9 |
46083 | #define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER__SHIFT 0x0 |
46084 | #define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER_MASK 0x0001FFFFL |
46085 | //FIXED_PATTERN_PERF_COUNTER_10 |
46086 | #define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER__SHIFT 0x0 |
46087 | #define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER_MASK 0x0001FFFFL |
46088 | //HW_LUT_UPDATE_STATUS |
46089 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE__SHIFT 0x0 |
46090 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR__SHIFT 0x1 |
46091 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP__SHIFT 0x2 |
46092 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE__SHIFT 0x5 |
46093 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR__SHIFT 0x6 |
46094 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP__SHIFT 0x7 |
46095 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE__SHIFT 0xa |
46096 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR__SHIFT 0xb |
46097 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP__SHIFT 0xc |
46098 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE__SHIFT 0x11 |
46099 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR__SHIFT 0x12 |
46100 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP__SHIFT 0x13 |
46101 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE__SHIFT 0x16 |
46102 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR__SHIFT 0x17 |
46103 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP__SHIFT 0x18 |
46104 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE_MASK 0x00000001L |
46105 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_MASK 0x00000002L |
46106 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP_MASK 0x0000001CL |
46107 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE_MASK 0x00000020L |
46108 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_MASK 0x00000040L |
46109 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP_MASK 0x00000380L |
46110 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE_MASK 0x00000400L |
46111 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_MASK 0x00000800L |
46112 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP_MASK 0x0001F000L |
46113 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE_MASK 0x00020000L |
46114 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_MASK 0x00040000L |
46115 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP_MASK 0x00380000L |
46116 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE_MASK 0x00400000L |
46117 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_MASK 0x00800000L |
46118 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP_MASK 0x1F000000L |
46119 | |
46120 | |
46121 | // addressBlock: secacind |
46122 | //SE_CAC_ID |
46123 | #define SE_CAC_ID__CAC_BLOCK_ID__SHIFT 0x0 |
46124 | #define SE_CAC_ID__CAC_SIGNAL_ID__SHIFT 0x6 |
46125 | #define SE_CAC_ID__UNUSED_0__SHIFT 0xe |
46126 | #define SE_CAC_ID__CAC_BLOCK_ID_MASK 0x0000003FL |
46127 | #define SE_CAC_ID__CAC_SIGNAL_ID_MASK 0x00003FC0L |
46128 | #define SE_CAC_ID__UNUSED_0_MASK 0xFFFFC000L |
46129 | //SE_CAC_CNTL |
46130 | #define SE_CAC_CNTL__CAC_FORCE_DISABLE__SHIFT 0x0 |
46131 | #define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 |
46132 | #define SE_CAC_CNTL__UNUSED_0__SHIFT 0x11 |
46133 | #define SE_CAC_CNTL__CAC_FORCE_DISABLE_MASK 0x00000001L |
46134 | #define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL |
46135 | #define SE_CAC_CNTL__UNUSED_0_MASK 0xFFFE0000L |
46136 | //SE_CAC_OVR_SEL |
46137 | #define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 |
46138 | #define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL |
46139 | //SE_CAC_OVR_VAL |
46140 | #define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 |
46141 | #define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL |
46142 | |
46143 | |
46144 | // addressBlock: spmglbind |
46145 | //GLB_CPG_SAMPLEDELAY |
46146 | #define GLB_CPG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46147 | #define GLB_CPG_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46148 | #define GLB_CPG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46149 | #define GLB_CPG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46150 | //GLB_CPC_SAMPLEDELAY |
46151 | #define GLB_CPC_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46152 | #define GLB_CPC_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46153 | #define GLB_CPC_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46154 | #define GLB_CPC_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46155 | //GLB_CPF_SAMPLEDELAY |
46156 | #define GLB_CPF_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46157 | #define GLB_CPF_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46158 | #define GLB_CPF_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46159 | #define GLB_CPF_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46160 | //GLB_GDS_SAMPLEDELAY |
46161 | #define GLB_GDS_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46162 | #define GLB_GDS_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46163 | #define GLB_GDS_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46164 | #define GLB_GDS_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46165 | //GLB_GCR_SAMPLEDELAY |
46166 | #define GLB_GCR_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46167 | #define GLB_GCR_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46168 | #define GLB_GCR_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46169 | #define GLB_GCR_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46170 | //GLB_PH_SAMPLEDELAY |
46171 | #define GLB_PH_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46172 | #define GLB_PH_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46173 | #define GLB_PH_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46174 | #define GLB_PH_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46175 | //GLB_GE1_SAMPLEDELAY |
46176 | #define GLB_GE1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46177 | #define GLB_GE1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46178 | #define GLB_GE1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46179 | #define GLB_GE1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46180 | //GLB_GE2DIST_SAMPLEDELAY |
46181 | #define GLB_GE2DIST_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46182 | #define GLB_GE2DIST_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46183 | #define GLB_GE2DIST_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46184 | #define GLB_GE2DIST_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46185 | //GLB_GUS_SAMPLEDELAY |
46186 | #define GLB_GUS_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46187 | #define GLB_GUS_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46188 | #define GLB_GUS_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46189 | #define GLB_GUS_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46190 | //GLB_CHA_SAMPLEDELAY |
46191 | #define GLB_CHA_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46192 | #define GLB_CHA_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46193 | #define GLB_CHA_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46194 | #define GLB_CHA_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46195 | //GLB_CHCG_SAMPLEDELAY |
46196 | #define GLB_CHCG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46197 | #define GLB_CHCG_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46198 | #define GLB_CHCG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46199 | #define GLB_CHCG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46200 | //GLB_ATCL2_SAMPLEDELAY |
46201 | #define GLB_ATCL2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46202 | #define GLB_ATCL2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46203 | #define GLB_ATCL2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46204 | #define GLB_ATCL2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46205 | //GLB_VML2_SAMPLEDELAY |
46206 | #define GLB_VML2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46207 | #define GLB_VML2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46208 | #define GLB_VML2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46209 | #define GLB_VML2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46210 | //GLB_SDMA0_SAMPLEDELAY |
46211 | #define GLB_SDMA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46212 | #define GLB_SDMA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46213 | #define GLB_SDMA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46214 | #define GLB_SDMA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46215 | //GLB_SDMA1_SAMPLEDELAY |
46216 | #define GLB_SDMA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46217 | #define GLB_SDMA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46218 | #define GLB_SDMA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46219 | #define GLB_SDMA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46220 | //GLB_SDMA2_SAMPLEDELAY |
46221 | #define GLB_SDMA2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46222 | #define GLB_SDMA2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46223 | #define GLB_SDMA2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46224 | #define GLB_SDMA2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46225 | //GLB_SDMA3_SAMPLEDELAY |
46226 | #define GLB_SDMA3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46227 | #define GLB_SDMA3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46228 | #define GLB_SDMA3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46229 | #define GLB_SDMA3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46230 | //GLB_GL2A0_SAMPLEDELAY |
46231 | #define GLB_GL2A0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46232 | #define GLB_GL2A0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46233 | #define GLB_GL2A0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46234 | #define GLB_GL2A0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46235 | //GLB_GL2A1_SAMPLEDELAY |
46236 | #define GLB_GL2A1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46237 | #define GLB_GL2A1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46238 | #define GLB_GL2A1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46239 | #define GLB_GL2A1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46240 | //GLB_GL2A2_SAMPLEDELAY |
46241 | #define GLB_GL2A2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46242 | #define GLB_GL2A2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46243 | #define GLB_GL2A2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46244 | #define GLB_GL2A2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46245 | //GLB_GL2A3_SAMPLEDELAY |
46246 | #define GLB_GL2A3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46247 | #define GLB_GL2A3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46248 | #define GLB_GL2A3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46249 | #define GLB_GL2A3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46250 | //GLB_GL2C0_SAMPLEDELAY |
46251 | #define GLB_GL2C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46252 | #define GLB_GL2C0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46253 | #define GLB_GL2C0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46254 | #define GLB_GL2C0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46255 | //GLB_GL2C1_SAMPLEDELAY |
46256 | #define GLB_GL2C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46257 | #define GLB_GL2C1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46258 | #define GLB_GL2C1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46259 | #define GLB_GL2C1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46260 | //GLB_GL2C2_SAMPLEDELAY |
46261 | #define GLB_GL2C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46262 | #define GLB_GL2C2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46263 | #define GLB_GL2C2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46264 | #define GLB_GL2C2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46265 | //GLB_GL2C3_SAMPLEDELAY |
46266 | #define GLB_GL2C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46267 | #define GLB_GL2C3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46268 | #define GLB_GL2C3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46269 | #define GLB_GL2C3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46270 | //GLB_GL2C4_SAMPLEDELAY |
46271 | #define GLB_GL2C4_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46272 | #define GLB_GL2C4_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46273 | #define GLB_GL2C4_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46274 | #define GLB_GL2C4_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46275 | //GLB_GL2C5_SAMPLEDELAY |
46276 | #define GLB_GL2C5_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46277 | #define GLB_GL2C5_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46278 | #define GLB_GL2C5_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46279 | #define GLB_GL2C5_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46280 | //GLB_GL2C6_SAMPLEDELAY |
46281 | #define GLB_GL2C6_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46282 | #define GLB_GL2C6_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46283 | #define GLB_GL2C6_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46284 | #define GLB_GL2C6_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46285 | //GLB_GL2C7_SAMPLEDELAY |
46286 | #define GLB_GL2C7_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46287 | #define GLB_GL2C7_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46288 | #define GLB_GL2C7_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46289 | #define GLB_GL2C7_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46290 | //GLB_GL2C8_SAMPLEDELAY |
46291 | #define GLB_GL2C8_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46292 | #define GLB_GL2C8_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46293 | #define GLB_GL2C8_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46294 | #define GLB_GL2C8_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46295 | //GLB_GL2C9_SAMPLEDELAY |
46296 | #define GLB_GL2C9_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46297 | #define GLB_GL2C9_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46298 | #define GLB_GL2C9_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46299 | #define GLB_GL2C9_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46300 | //GLB_GL2C10_SAMPLEDELAY |
46301 | #define GLB_GL2C10_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46302 | #define GLB_GL2C10_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46303 | #define GLB_GL2C10_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46304 | #define GLB_GL2C10_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46305 | //GLB_GL2C11_SAMPLEDELAY |
46306 | #define GLB_GL2C11_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46307 | #define GLB_GL2C11_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46308 | #define GLB_GL2C11_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46309 | #define GLB_GL2C11_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46310 | //GLB_GL2C12_SAMPLEDELAY |
46311 | #define GLB_GL2C12_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46312 | #define GLB_GL2C12_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46313 | #define GLB_GL2C12_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46314 | #define GLB_GL2C12_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46315 | //GLB_GL2C13_SAMPLEDELAY |
46316 | #define GLB_GL2C13_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46317 | #define GLB_GL2C13_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46318 | #define GLB_GL2C13_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46319 | #define GLB_GL2C13_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46320 | //GLB_GL2C14_SAMPLEDELAY |
46321 | #define GLB_GL2C14_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46322 | #define GLB_GL2C14_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46323 | #define GLB_GL2C14_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46324 | #define GLB_GL2C14_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46325 | //GLB_GL2C15_SAMPLEDELAY |
46326 | #define GLB_GL2C15_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46327 | #define GLB_GL2C15_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46328 | #define GLB_GL2C15_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46329 | #define GLB_GL2C15_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46330 | //GLB_EA0_SAMPLEDELAY |
46331 | #define GLB_EA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46332 | #define GLB_EA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46333 | #define GLB_EA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46334 | #define GLB_EA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46335 | //GLB_EA1_SAMPLEDELAY |
46336 | #define GLB_EA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46337 | #define GLB_EA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46338 | #define GLB_EA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46339 | #define GLB_EA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46340 | //GLB_EA2_SAMPLEDELAY |
46341 | #define GLB_EA2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46342 | #define GLB_EA2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46343 | #define GLB_EA2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46344 | #define GLB_EA2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46345 | //GLB_EA3_SAMPLEDELAY |
46346 | #define GLB_EA3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46347 | #define GLB_EA3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46348 | #define GLB_EA3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46349 | #define GLB_EA3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46350 | //GLB_EA4_SAMPLEDELAY |
46351 | #define GLB_EA4_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46352 | #define GLB_EA4_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46353 | #define GLB_EA4_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46354 | #define GLB_EA4_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46355 | //GLB_EA5_SAMPLEDELAY |
46356 | #define GLB_EA5_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46357 | #define GLB_EA5_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46358 | #define GLB_EA5_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46359 | #define GLB_EA5_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46360 | //GLB_EA6_SAMPLEDELAY |
46361 | #define GLB_EA6_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46362 | #define GLB_EA6_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46363 | #define GLB_EA6_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46364 | #define GLB_EA6_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46365 | //GLB_EA7_SAMPLEDELAY |
46366 | #define GLB_EA7_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46367 | #define GLB_EA7_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46368 | #define GLB_EA7_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46369 | #define GLB_EA7_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46370 | //GLB_EA8_SAMPLEDELAY |
46371 | #define GLB_EA8_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46372 | #define GLB_EA8_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46373 | #define GLB_EA8_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46374 | #define GLB_EA8_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46375 | //GLB_EA9_SAMPLEDELAY |
46376 | #define GLB_EA9_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46377 | #define GLB_EA9_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46378 | #define GLB_EA9_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46379 | #define GLB_EA9_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46380 | //GLB_EA10_SAMPLEDELAY |
46381 | #define GLB_EA10_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46382 | #define GLB_EA10_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46383 | #define GLB_EA10_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46384 | #define GLB_EA10_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46385 | //GLB_EA11_SAMPLEDELAY |
46386 | #define GLB_EA11_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46387 | #define GLB_EA11_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46388 | #define GLB_EA11_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46389 | #define GLB_EA11_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46390 | //GLB_EA12_SAMPLEDELAY |
46391 | #define GLB_EA12_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46392 | #define GLB_EA12_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46393 | #define GLB_EA12_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46394 | #define GLB_EA12_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46395 | //GLB_EA13_SAMPLEDELAY |
46396 | #define GLB_EA13_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46397 | #define GLB_EA13_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46398 | #define GLB_EA13_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46399 | #define GLB_EA13_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46400 | //GLB_EA14_SAMPLEDELAY |
46401 | #define GLB_EA14_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46402 | #define GLB_EA14_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46403 | #define GLB_EA14_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46404 | #define GLB_EA14_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46405 | //GLB_EA15_SAMPLEDELAY |
46406 | #define GLB_EA15_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46407 | #define GLB_EA15_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46408 | #define GLB_EA15_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46409 | #define GLB_EA15_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46410 | //GLB_CHC0_SAMPLEDELAY |
46411 | #define GLB_CHC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46412 | #define GLB_CHC0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46413 | #define GLB_CHC0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46414 | #define GLB_CHC0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46415 | //GLB_CHC1_SAMPLEDELAY |
46416 | #define GLB_CHC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46417 | #define GLB_CHC1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46418 | #define GLB_CHC1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46419 | #define GLB_CHC1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46420 | //GLB_CHC2_SAMPLEDELAY |
46421 | #define GLB_CHC2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46422 | #define GLB_CHC2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46423 | #define GLB_CHC2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46424 | #define GLB_CHC2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46425 | //GLB_CHC3_SAMPLEDELAY |
46426 | #define GLB_CHC3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46427 | #define GLB_CHC3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46428 | #define GLB_CHC3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46429 | #define GLB_CHC3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46430 | //GLB_GE2SE0_SAMPLEDELAY |
46431 | #define GLB_GE2SE0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46432 | #define GLB_GE2SE0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46433 | #define GLB_GE2SE0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46434 | #define GLB_GE2SE0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46435 | //GLB_GE2SE1_SAMPLEDELAY |
46436 | #define GLB_GE2SE1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46437 | #define GLB_GE2SE1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46438 | #define GLB_GE2SE1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46439 | #define GLB_GE2SE1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46440 | //GLB_GE2SE2_SAMPLEDELAY |
46441 | #define GLB_GE2SE2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46442 | #define GLB_GE2SE2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46443 | #define GLB_GE2SE2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46444 | #define GLB_GE2SE2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46445 | //GLB_GE2SE3_SAMPLEDELAY |
46446 | #define GLB_GE2SE3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46447 | #define GLB_GE2SE3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46448 | #define GLB_GE2SE3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46449 | #define GLB_GE2SE3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46450 | |
46451 | |
46452 | // addressBlock: spmind |
46453 | //SE_SPI_SAMPLEDELAY |
46454 | #define SE_SPI_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46455 | #define SE_SPI_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46456 | #define SE_SPI_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46457 | #define SE_SPI_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46458 | //SE_SQG_SAMPLEDELAY |
46459 | #define SE_SQG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46460 | #define SE_SQG_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46461 | #define SE_SQG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46462 | #define SE_SQG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46463 | //SE_CBR_SAMPLEDELAY |
46464 | #define SE_CBR_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46465 | #define SE_CBR_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46466 | #define SE_CBR_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46467 | #define SE_CBR_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46468 | //SE_DBR_SAMPLEDELAY |
46469 | #define SE_DBR_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46470 | #define SE_DBR_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46471 | #define SE_DBR_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46472 | #define SE_DBR_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46473 | //SE_PA_SAMPLEDELAY |
46474 | #define SE_PA_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46475 | #define SE_PA_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46476 | #define SE_PA_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46477 | #define SE_PA_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46478 | //SE_SA0SX_SAMPLEDELAY |
46479 | #define SE_SA0SX_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46480 | #define SE_SA0SX_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46481 | #define SE_SA0SX_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46482 | #define SE_SA0SX_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46483 | //SE_SA0GL1A_SAMPLEDELAY |
46484 | #define SE_SA0GL1A_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46485 | #define SE_SA0GL1A_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46486 | #define SE_SA0GL1A_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46487 | #define SE_SA0GL1A_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46488 | //SE_SA0GL1CG_SAMPLEDELAY |
46489 | #define SE_SA0GL1CG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46490 | #define SE_SA0GL1CG_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46491 | #define SE_SA0GL1CG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46492 | #define SE_SA0GL1CG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46493 | //SE_SA0CB0_SAMPLEDELAY |
46494 | #define SE_SA0CB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46495 | #define SE_SA0CB0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46496 | #define SE_SA0CB0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46497 | #define SE_SA0CB0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46498 | //SE_SA0CB1_SAMPLEDELAY |
46499 | #define SE_SA0CB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46500 | #define SE_SA0CB1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46501 | #define SE_SA0CB1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46502 | #define SE_SA0CB1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46503 | //SE_SA0DB0_SAMPLEDELAY |
46504 | #define SE_SA0DB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46505 | #define SE_SA0DB0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46506 | #define SE_SA0DB0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46507 | #define SE_SA0DB0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46508 | //SE_SA0DB1_SAMPLEDELAY |
46509 | #define SE_SA0DB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46510 | #define SE_SA0DB1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46511 | #define SE_SA0DB1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46512 | #define SE_SA0DB1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46513 | //SE_SA0SC0_SAMPLEDELAY |
46514 | #define SE_SA0SC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46515 | #define SE_SA0SC0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46516 | #define SE_SA0SC0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46517 | #define SE_SA0SC0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46518 | //SE_SA0SC1_SAMPLEDELAY |
46519 | #define SE_SA0SC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46520 | #define SE_SA0SC1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46521 | #define SE_SA0SC1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46522 | #define SE_SA0SC1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46523 | //SE_SA0RMI0_SAMPLEDELAY |
46524 | #define SE_SA0RMI0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46525 | #define SE_SA0RMI0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46526 | #define SE_SA0RMI0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46527 | #define SE_SA0RMI0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46528 | //SE_SA0RMI1_SAMPLEDELAY |
46529 | #define SE_SA0RMI1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46530 | #define SE_SA0RMI1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46531 | #define SE_SA0RMI1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46532 | #define SE_SA0RMI1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46533 | //SE_SA0GL1C0_SAMPLEDELAY |
46534 | #define SE_SA0GL1C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46535 | #define SE_SA0GL1C0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46536 | #define SE_SA0GL1C0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46537 | #define SE_SA0GL1C0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46538 | //SE_SA0GL1C1_SAMPLEDELAY |
46539 | #define SE_SA0GL1C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46540 | #define SE_SA0GL1C1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46541 | #define SE_SA0GL1C1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46542 | #define SE_SA0GL1C1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46543 | //SE_SA0GL1C2_SAMPLEDELAY |
46544 | #define SE_SA0GL1C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46545 | #define SE_SA0GL1C2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46546 | #define SE_SA0GL1C2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46547 | #define SE_SA0GL1C2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46548 | //SE_SA0GL1C3_SAMPLEDELAY |
46549 | #define SE_SA0GL1C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46550 | #define SE_SA0GL1C3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46551 | #define SE_SA0GL1C3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46552 | #define SE_SA0GL1C3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46553 | //SE_SA0WGP00TA0_SAMPLEDELAY |
46554 | #define SE_SA0WGP00TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46555 | #define SE_SA0WGP00TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46556 | #define SE_SA0WGP00TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46557 | #define SE_SA0WGP00TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46558 | //SE_SA0WGP00TA1_SAMPLEDELAY |
46559 | #define SE_SA0WGP00TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46560 | #define SE_SA0WGP00TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46561 | #define SE_SA0WGP00TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46562 | #define SE_SA0WGP00TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46563 | //SE_SA0WGP00TD0_SAMPLEDELAY |
46564 | #define SE_SA0WGP00TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46565 | #define SE_SA0WGP00TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46566 | #define SE_SA0WGP00TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46567 | #define SE_SA0WGP00TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46568 | //SE_SA0WGP00TD1_SAMPLEDELAY |
46569 | #define SE_SA0WGP00TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46570 | #define SE_SA0WGP00TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46571 | #define SE_SA0WGP00TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46572 | #define SE_SA0WGP00TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46573 | //SE_SA0WGP00TCP0_SAMPLEDELAY |
46574 | #define SE_SA0WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46575 | #define SE_SA0WGP00TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46576 | #define SE_SA0WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46577 | #define SE_SA0WGP00TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46578 | //SE_SA0WGP00TCP1_SAMPLEDELAY |
46579 | #define SE_SA0WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46580 | #define SE_SA0WGP00TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46581 | #define SE_SA0WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46582 | #define SE_SA0WGP00TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46583 | //SE_SA0WGP01TA0_SAMPLEDELAY |
46584 | #define SE_SA0WGP01TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46585 | #define SE_SA0WGP01TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46586 | #define SE_SA0WGP01TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46587 | #define SE_SA0WGP01TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46588 | //SE_SA0WGP01TA1_SAMPLEDELAY |
46589 | #define SE_SA0WGP01TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46590 | #define SE_SA0WGP01TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46591 | #define SE_SA0WGP01TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46592 | #define SE_SA0WGP01TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46593 | //SE_SA0WGP01TD0_SAMPLEDELAY |
46594 | #define SE_SA0WGP01TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46595 | #define SE_SA0WGP01TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46596 | #define SE_SA0WGP01TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46597 | #define SE_SA0WGP01TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46598 | //SE_SA0WGP01TD1_SAMPLEDELAY |
46599 | #define SE_SA0WGP01TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46600 | #define SE_SA0WGP01TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46601 | #define SE_SA0WGP01TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46602 | #define SE_SA0WGP01TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46603 | //SE_SA0WGP01TCP0_SAMPLEDELAY |
46604 | #define SE_SA0WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46605 | #define SE_SA0WGP01TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46606 | #define SE_SA0WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46607 | #define SE_SA0WGP01TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46608 | //SE_SA0WGP01TCP1_SAMPLEDELAY |
46609 | #define SE_SA0WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46610 | #define SE_SA0WGP01TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46611 | #define SE_SA0WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46612 | #define SE_SA0WGP01TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46613 | //SE_SA0WGP02TA0_SAMPLEDELAY |
46614 | #define SE_SA0WGP02TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46615 | #define SE_SA0WGP02TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46616 | #define SE_SA0WGP02TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46617 | #define SE_SA0WGP02TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46618 | //SE_SA0WGP02TA1_SAMPLEDELAY |
46619 | #define SE_SA0WGP02TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46620 | #define SE_SA0WGP02TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46621 | #define SE_SA0WGP02TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46622 | #define SE_SA0WGP02TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46623 | //SE_SA0WGP02TD0_SAMPLEDELAY |
46624 | #define SE_SA0WGP02TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46625 | #define SE_SA0WGP02TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46626 | #define SE_SA0WGP02TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46627 | #define SE_SA0WGP02TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46628 | //SE_SA0WGP02TD1_SAMPLEDELAY |
46629 | #define SE_SA0WGP02TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46630 | #define SE_SA0WGP02TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46631 | #define SE_SA0WGP02TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46632 | #define SE_SA0WGP02TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46633 | //SE_SA0WGP02TCP0_SAMPLEDELAY |
46634 | #define SE_SA0WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46635 | #define SE_SA0WGP02TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46636 | #define SE_SA0WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46637 | #define SE_SA0WGP02TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46638 | //SE_SA0WGP02TCP1_SAMPLEDELAY |
46639 | #define SE_SA0WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46640 | #define SE_SA0WGP02TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46641 | #define SE_SA0WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46642 | #define SE_SA0WGP02TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46643 | //SE_SA0WGP03TA0_SAMPLEDELAY |
46644 | #define SE_SA0WGP03TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46645 | #define SE_SA0WGP03TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46646 | #define SE_SA0WGP03TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46647 | #define SE_SA0WGP03TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46648 | //SE_SA0WGP03TA1_SAMPLEDELAY |
46649 | #define SE_SA0WGP03TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46650 | #define SE_SA0WGP03TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46651 | #define SE_SA0WGP03TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46652 | #define SE_SA0WGP03TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46653 | //SE_SA0WGP03TD0_SAMPLEDELAY |
46654 | #define SE_SA0WGP03TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46655 | #define SE_SA0WGP03TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46656 | #define SE_SA0WGP03TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46657 | #define SE_SA0WGP03TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46658 | //SE_SA0WGP03TD1_SAMPLEDELAY |
46659 | #define SE_SA0WGP03TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46660 | #define SE_SA0WGP03TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46661 | #define SE_SA0WGP03TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46662 | #define SE_SA0WGP03TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46663 | //SE_SA0WGP03TCP0_SAMPLEDELAY |
46664 | #define SE_SA0WGP03TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46665 | #define SE_SA0WGP03TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46666 | #define SE_SA0WGP03TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46667 | #define SE_SA0WGP03TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46668 | //SE_SA0WGP03TCP1_SAMPLEDELAY |
46669 | #define SE_SA0WGP03TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46670 | #define SE_SA0WGP03TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46671 | #define SE_SA0WGP03TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46672 | #define SE_SA0WGP03TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46673 | //SE_SA0WGP04TA0_SAMPLEDELAY |
46674 | #define SE_SA0WGP04TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46675 | #define SE_SA0WGP04TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46676 | #define SE_SA0WGP04TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46677 | #define SE_SA0WGP04TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46678 | //SE_SA0WGP04TA1_SAMPLEDELAY |
46679 | #define SE_SA0WGP04TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46680 | #define SE_SA0WGP04TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46681 | #define SE_SA0WGP04TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46682 | #define SE_SA0WGP04TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46683 | //SE_SA0WGP04TD0_SAMPLEDELAY |
46684 | #define SE_SA0WGP04TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46685 | #define SE_SA0WGP04TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46686 | #define SE_SA0WGP04TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46687 | #define SE_SA0WGP04TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46688 | //SE_SA0WGP04TD1_SAMPLEDELAY |
46689 | #define SE_SA0WGP04TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46690 | #define SE_SA0WGP04TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46691 | #define SE_SA0WGP04TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46692 | #define SE_SA0WGP04TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46693 | //SE_SA0WGP04TCP0_SAMPLEDELAY |
46694 | #define SE_SA0WGP04TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46695 | #define SE_SA0WGP04TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46696 | #define SE_SA0WGP04TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46697 | #define SE_SA0WGP04TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46698 | //SE_SA0WGP04TCP1_SAMPLEDELAY |
46699 | #define SE_SA0WGP04TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46700 | #define SE_SA0WGP04TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46701 | #define SE_SA0WGP04TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46702 | #define SE_SA0WGP04TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46703 | //SE_SA1SX_SAMPLEDELAY |
46704 | #define SE_SA1SX_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46705 | #define SE_SA1SX_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46706 | #define SE_SA1SX_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46707 | #define SE_SA1SX_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46708 | //SE_SA1GL1A_SAMPLEDELAY |
46709 | #define SE_SA1GL1A_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46710 | #define SE_SA1GL1A_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46711 | #define SE_SA1GL1A_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46712 | #define SE_SA1GL1A_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46713 | //SE_SA1GL1CG_SAMPLEDELAY |
46714 | #define SE_SA1GL1CG_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46715 | #define SE_SA1GL1CG_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46716 | #define SE_SA1GL1CG_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46717 | #define SE_SA1GL1CG_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46718 | //SE_SA1CB0_SAMPLEDELAY |
46719 | #define SE_SA1CB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46720 | #define SE_SA1CB0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46721 | #define SE_SA1CB0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46722 | #define SE_SA1CB0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46723 | //SE_SA1CB1_SAMPLEDELAY |
46724 | #define SE_SA1CB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46725 | #define SE_SA1CB1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46726 | #define SE_SA1CB1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46727 | #define SE_SA1CB1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46728 | //SE_SA1DB0_SAMPLEDELAY |
46729 | #define SE_SA1DB0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46730 | #define SE_SA1DB0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46731 | #define SE_SA1DB0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46732 | #define SE_SA1DB0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46733 | //SE_SA1DB1_SAMPLEDELAY |
46734 | #define SE_SA1DB1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46735 | #define SE_SA1DB1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46736 | #define SE_SA1DB1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46737 | #define SE_SA1DB1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46738 | //SE_SA1SC0_SAMPLEDELAY |
46739 | #define SE_SA1SC0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46740 | #define SE_SA1SC0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46741 | #define SE_SA1SC0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46742 | #define SE_SA1SC0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46743 | //SE_SA1SC1_SAMPLEDELAY |
46744 | #define SE_SA1SC1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46745 | #define SE_SA1SC1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46746 | #define SE_SA1SC1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46747 | #define SE_SA1SC1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46748 | //SE_SA1RMI0_SAMPLEDELAY |
46749 | #define SE_SA1RMI0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46750 | #define SE_SA1RMI0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46751 | #define SE_SA1RMI0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46752 | #define SE_SA1RMI0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46753 | //SE_SA1RMI1_SAMPLEDELAY |
46754 | #define SE_SA1RMI1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46755 | #define SE_SA1RMI1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46756 | #define SE_SA1RMI1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46757 | #define SE_SA1RMI1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46758 | //SE_SA1GL1C0_SAMPLEDELAY |
46759 | #define SE_SA1GL1C0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46760 | #define SE_SA1GL1C0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46761 | #define SE_SA1GL1C0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46762 | #define SE_SA1GL1C0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46763 | //SE_SA1GL1C1_SAMPLEDELAY |
46764 | #define SE_SA1GL1C1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46765 | #define SE_SA1GL1C1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46766 | #define SE_SA1GL1C1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46767 | #define SE_SA1GL1C1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46768 | //SE_SA1GL1C2_SAMPLEDELAY |
46769 | #define SE_SA1GL1C2_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46770 | #define SE_SA1GL1C2_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46771 | #define SE_SA1GL1C2_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46772 | #define SE_SA1GL1C2_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46773 | //SE_SA1GL1C3_SAMPLEDELAY |
46774 | #define SE_SA1GL1C3_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46775 | #define SE_SA1GL1C3_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46776 | #define SE_SA1GL1C3_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46777 | #define SE_SA1GL1C3_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46778 | //SE_SA1WGP00TA0_SAMPLEDELAY |
46779 | #define SE_SA1WGP00TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46780 | #define SE_SA1WGP00TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46781 | #define SE_SA1WGP00TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46782 | #define SE_SA1WGP00TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46783 | //SE_SA1WGP00TA1_SAMPLEDELAY |
46784 | #define SE_SA1WGP00TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46785 | #define SE_SA1WGP00TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46786 | #define SE_SA1WGP00TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46787 | #define SE_SA1WGP00TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46788 | //SE_SA1WGP00TD0_SAMPLEDELAY |
46789 | #define SE_SA1WGP00TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46790 | #define SE_SA1WGP00TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46791 | #define SE_SA1WGP00TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46792 | #define SE_SA1WGP00TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46793 | //SE_SA1WGP00TD1_SAMPLEDELAY |
46794 | #define SE_SA1WGP00TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46795 | #define SE_SA1WGP00TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46796 | #define SE_SA1WGP00TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46797 | #define SE_SA1WGP00TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46798 | //SE_SA1WGP00TCP0_SAMPLEDELAY |
46799 | #define SE_SA1WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46800 | #define SE_SA1WGP00TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46801 | #define SE_SA1WGP00TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46802 | #define SE_SA1WGP00TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46803 | //SE_SA1WGP00TCP1_SAMPLEDELAY |
46804 | #define SE_SA1WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46805 | #define SE_SA1WGP00TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46806 | #define SE_SA1WGP00TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46807 | #define SE_SA1WGP00TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46808 | //SE_SA1WGP01TA0_SAMPLEDELAY |
46809 | #define SE_SA1WGP01TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46810 | #define SE_SA1WGP01TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46811 | #define SE_SA1WGP01TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46812 | #define SE_SA1WGP01TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46813 | //SE_SA1WGP01TA1_SAMPLEDELAY |
46814 | #define SE_SA1WGP01TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46815 | #define SE_SA1WGP01TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46816 | #define SE_SA1WGP01TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46817 | #define SE_SA1WGP01TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46818 | //SE_SA1WGP01TD0_SAMPLEDELAY |
46819 | #define SE_SA1WGP01TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46820 | #define SE_SA1WGP01TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46821 | #define SE_SA1WGP01TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46822 | #define SE_SA1WGP01TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46823 | //SE_SA1WGP01TD1_SAMPLEDELAY |
46824 | #define SE_SA1WGP01TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46825 | #define SE_SA1WGP01TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46826 | #define SE_SA1WGP01TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46827 | #define SE_SA1WGP01TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46828 | //SE_SA1WGP01TCP0_SAMPLEDELAY |
46829 | #define SE_SA1WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46830 | #define SE_SA1WGP01TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46831 | #define SE_SA1WGP01TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46832 | #define SE_SA1WGP01TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46833 | //SE_SA1WGP01TCP1_SAMPLEDELAY |
46834 | #define SE_SA1WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46835 | #define SE_SA1WGP01TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46836 | #define SE_SA1WGP01TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46837 | #define SE_SA1WGP01TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46838 | //SE_SA1WGP02TA0_SAMPLEDELAY |
46839 | #define SE_SA1WGP02TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46840 | #define SE_SA1WGP02TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46841 | #define SE_SA1WGP02TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46842 | #define SE_SA1WGP02TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46843 | //SE_SA1WGP02TA1_SAMPLEDELAY |
46844 | #define SE_SA1WGP02TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46845 | #define SE_SA1WGP02TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46846 | #define SE_SA1WGP02TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46847 | #define SE_SA1WGP02TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46848 | //SE_SA1WGP02TD0_SAMPLEDELAY |
46849 | #define SE_SA1WGP02TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46850 | #define SE_SA1WGP02TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46851 | #define SE_SA1WGP02TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46852 | #define SE_SA1WGP02TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46853 | //SE_SA1WGP02TD1_SAMPLEDELAY |
46854 | #define SE_SA1WGP02TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46855 | #define SE_SA1WGP02TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46856 | #define SE_SA1WGP02TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46857 | #define SE_SA1WGP02TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46858 | //SE_SA1WGP02TCP0_SAMPLEDELAY |
46859 | #define SE_SA1WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46860 | #define SE_SA1WGP02TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46861 | #define SE_SA1WGP02TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46862 | #define SE_SA1WGP02TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46863 | //SE_SA1WGP02TCP1_SAMPLEDELAY |
46864 | #define SE_SA1WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46865 | #define SE_SA1WGP02TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46866 | #define SE_SA1WGP02TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46867 | #define SE_SA1WGP02TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46868 | //SE_SA1WGP03TA0_SAMPLEDELAY |
46869 | #define SE_SA1WGP03TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46870 | #define SE_SA1WGP03TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46871 | #define SE_SA1WGP03TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46872 | #define SE_SA1WGP03TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46873 | //SE_SA1WGP03TA1_SAMPLEDELAY |
46874 | #define SE_SA1WGP03TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46875 | #define SE_SA1WGP03TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46876 | #define SE_SA1WGP03TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46877 | #define SE_SA1WGP03TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46878 | //SE_SA1WGP03TD0_SAMPLEDELAY |
46879 | #define SE_SA1WGP03TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46880 | #define SE_SA1WGP03TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46881 | #define SE_SA1WGP03TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46882 | #define SE_SA1WGP03TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46883 | //SE_SA1WGP03TD1_SAMPLEDELAY |
46884 | #define SE_SA1WGP03TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46885 | #define SE_SA1WGP03TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46886 | #define SE_SA1WGP03TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46887 | #define SE_SA1WGP03TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46888 | //SE_SA1WGP03TCP0_SAMPLEDELAY |
46889 | #define SE_SA1WGP03TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46890 | #define SE_SA1WGP03TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46891 | #define SE_SA1WGP03TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46892 | #define SE_SA1WGP03TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46893 | //SE_SA1WGP03TCP1_SAMPLEDELAY |
46894 | #define SE_SA1WGP03TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46895 | #define SE_SA1WGP03TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46896 | #define SE_SA1WGP03TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46897 | #define SE_SA1WGP03TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46898 | //SE_SA1WGP04TA0_SAMPLEDELAY |
46899 | #define SE_SA1WGP04TA0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46900 | #define SE_SA1WGP04TA0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46901 | #define SE_SA1WGP04TA0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46902 | #define SE_SA1WGP04TA0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46903 | //SE_SA1WGP04TA1_SAMPLEDELAY |
46904 | #define SE_SA1WGP04TA1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46905 | #define SE_SA1WGP04TA1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46906 | #define SE_SA1WGP04TA1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46907 | #define SE_SA1WGP04TA1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46908 | //SE_SA1WGP04TD0_SAMPLEDELAY |
46909 | #define SE_SA1WGP04TD0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46910 | #define SE_SA1WGP04TD0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46911 | #define SE_SA1WGP04TD0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46912 | #define SE_SA1WGP04TD0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46913 | //SE_SA1WGP04TD1_SAMPLEDELAY |
46914 | #define SE_SA1WGP04TD1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46915 | #define SE_SA1WGP04TD1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46916 | #define SE_SA1WGP04TD1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46917 | #define SE_SA1WGP04TD1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46918 | //SE_SA1WGP04TCP0_SAMPLEDELAY |
46919 | #define SE_SA1WGP04TCP0_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46920 | #define SE_SA1WGP04TCP0_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46921 | #define SE_SA1WGP04TCP0_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46922 | #define SE_SA1WGP04TCP0_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46923 | //SE_SA1WGP04TCP1_SAMPLEDELAY |
46924 | #define SE_SA1WGP04TCP1_SAMPLEDELAY__SAMPLEDELAY__SHIFT 0x0 |
46925 | #define SE_SA1WGP04TCP1_SAMPLEDELAY__RESERVED__SHIFT 0x6 |
46926 | #define SE_SA1WGP04TCP1_SAMPLEDELAY__SAMPLEDELAY_MASK 0x0000003FL |
46927 | #define SE_SA1WGP04TCP1_SAMPLEDELAY__RESERVED_MASK 0xFFFFFFC0L |
46928 | |
46929 | |
46930 | |
46931 | |
46932 | // addressBlock: grtavfsind |
46933 | //RTAVFS_REG0 |
46934 | #define RTAVFS_REG0__RTAVFSCPO0_STARTCNT__SHIFT 0x0 |
46935 | #define RTAVFS_REG0__RTAVFSCPO0_STOPCNT__SHIFT 0x10 |
46936 | #define RTAVFS_REG0__RTAVFSCPO0_STARTCNT_MASK 0x0000FFFFL |
46937 | #define RTAVFS_REG0__RTAVFSCPO0_STOPCNT_MASK 0xFFFF0000L |
46938 | //RTAVFS_REG1 |
46939 | #define RTAVFS_REG1__RTAVFSCPO0_RIPPLECNT__SHIFT 0x0 |
46940 | #define RTAVFS_REG1__RESERVED__SHIFT 0x10 |
46941 | #define RTAVFS_REG1__RTAVFSCPO0_RIPPLECNT_MASK 0x0000FFFFL |
46942 | #define RTAVFS_REG1__RESERVED_MASK 0xFFFF0000L |
46943 | //RTAVFS_REG2 |
46944 | #define RTAVFS_REG2__RTAVFSCPO1_STARTCNT__SHIFT 0x0 |
46945 | #define RTAVFS_REG2__RTAVFSCPO1_STOPCNT__SHIFT 0x10 |
46946 | #define RTAVFS_REG2__RTAVFSCPO1_STARTCNT_MASK 0x0000FFFFL |
46947 | #define RTAVFS_REG2__RTAVFSCPO1_STOPCNT_MASK 0xFFFF0000L |
46948 | //RTAVFS_REG3 |
46949 | #define RTAVFS_REG3__RTAVFSCPO1_RIPPLECNT__SHIFT 0x0 |
46950 | #define RTAVFS_REG3__RESERVED__SHIFT 0x10 |
46951 | #define RTAVFS_REG3__RTAVFSCPO1_RIPPLECNT_MASK 0x0000FFFFL |
46952 | #define RTAVFS_REG3__RESERVED_MASK 0xFFFF0000L |
46953 | //RTAVFS_REG4 |
46954 | #define RTAVFS_REG4__RTAVFSCPO2_STARTCNT__SHIFT 0x0 |
46955 | #define RTAVFS_REG4__RTAVFSCPO2_STOPCNT__SHIFT 0x10 |
46956 | #define RTAVFS_REG4__RTAVFSCPO2_STARTCNT_MASK 0x0000FFFFL |
46957 | #define RTAVFS_REG4__RTAVFSCPO2_STOPCNT_MASK 0xFFFF0000L |
46958 | //RTAVFS_REG5 |
46959 | #define RTAVFS_REG5__RTAVFSCPO2_RIPPLECNT__SHIFT 0x0 |
46960 | #define RTAVFS_REG5__RESERVED__SHIFT 0x10 |
46961 | #define RTAVFS_REG5__RTAVFSCPO2_RIPPLECNT_MASK 0x0000FFFFL |
46962 | #define RTAVFS_REG5__RESERVED_MASK 0xFFFF0000L |
46963 | //RTAVFS_REG6 |
46964 | #define RTAVFS_REG6__RTAVFSCPO3_STARTCNT__SHIFT 0x0 |
46965 | #define RTAVFS_REG6__RTAVFSCPO3_STOPCNT__SHIFT 0x10 |
46966 | #define RTAVFS_REG6__RTAVFSCPO3_STARTCNT_MASK 0x0000FFFFL |
46967 | #define RTAVFS_REG6__RTAVFSCPO3_STOPCNT_MASK 0xFFFF0000L |
46968 | //RTAVFS_REG7 |
46969 | #define RTAVFS_REG7__RTAVFSCPO3_RIPPLECNT__SHIFT 0x0 |
46970 | #define RTAVFS_REG7__RESERVED__SHIFT 0x10 |
46971 | #define RTAVFS_REG7__RTAVFSCPO3_RIPPLECNT_MASK 0x0000FFFFL |
46972 | #define RTAVFS_REG7__RESERVED_MASK 0xFFFF0000L |
46973 | //RTAVFS_REG8 |
46974 | #define RTAVFS_REG8__RTAVFSCPO4_STARTCNT__SHIFT 0x0 |
46975 | #define RTAVFS_REG8__RTAVFSCPO4_STOPCNT__SHIFT 0x10 |
46976 | #define RTAVFS_REG8__RTAVFSCPO4_STARTCNT_MASK 0x0000FFFFL |
46977 | #define RTAVFS_REG8__RTAVFSCPO4_STOPCNT_MASK 0xFFFF0000L |
46978 | //RTAVFS_REG9 |
46979 | #define RTAVFS_REG9__RTAVFSCPO4_RIPPLECNT__SHIFT 0x0 |
46980 | #define RTAVFS_REG9__RESERVED__SHIFT 0x10 |
46981 | #define RTAVFS_REG9__RTAVFSCPO4_RIPPLECNT_MASK 0x0000FFFFL |
46982 | #define RTAVFS_REG9__RESERVED_MASK 0xFFFF0000L |
46983 | //RTAVFS_REG10 |
46984 | #define RTAVFS_REG10__RTAVFSCPO5_STARTCNT__SHIFT 0x0 |
46985 | #define RTAVFS_REG10__RTAVFSCPO5_STOPCNT__SHIFT 0x10 |
46986 | #define RTAVFS_REG10__RTAVFSCPO5_STARTCNT_MASK 0x0000FFFFL |
46987 | #define RTAVFS_REG10__RTAVFSCPO5_STOPCNT_MASK 0xFFFF0000L |
46988 | //RTAVFS_REG11 |
46989 | #define RTAVFS_REG11__RTAVFSCPO5_RIPPLECNT__SHIFT 0x0 |
46990 | #define RTAVFS_REG11__RESERVED__SHIFT 0x10 |
46991 | #define RTAVFS_REG11__RTAVFSCPO5_RIPPLECNT_MASK 0x0000FFFFL |
46992 | #define RTAVFS_REG11__RESERVED_MASK 0xFFFF0000L |
46993 | //RTAVFS_REG12 |
46994 | #define RTAVFS_REG12__RTAVFSCPO6_STARTCNT__SHIFT 0x0 |
46995 | #define RTAVFS_REG12__RTAVFSCPO6_STOPCNT__SHIFT 0x10 |
46996 | #define RTAVFS_REG12__RTAVFSCPO6_STARTCNT_MASK 0x0000FFFFL |
46997 | #define RTAVFS_REG12__RTAVFSCPO6_STOPCNT_MASK 0xFFFF0000L |
46998 | //RTAVFS_REG13 |
46999 | #define RTAVFS_REG13__RTAVFSCPO6_RIPPLECNT__SHIFT 0x0 |
47000 | #define RTAVFS_REG13__RESERVED__SHIFT 0x10 |
47001 | #define RTAVFS_REG13__RTAVFSCPO6_RIPPLECNT_MASK 0x0000FFFFL |
47002 | #define RTAVFS_REG13__RESERVED_MASK 0xFFFF0000L |
47003 | //RTAVFS_REG14 |
47004 | #define RTAVFS_REG14__RTAVFSCPO7_STARTCNT__SHIFT 0x0 |
47005 | #define RTAVFS_REG14__RTAVFSCPO7_STOPCNT__SHIFT 0x10 |
47006 | #define RTAVFS_REG14__RTAVFSCPO7_STARTCNT_MASK 0x0000FFFFL |
47007 | #define RTAVFS_REG14__RTAVFSCPO7_STOPCNT_MASK 0xFFFF0000L |
47008 | //RTAVFS_REG15 |
47009 | #define RTAVFS_REG15__RTAVFSCPO7_RIPPLECNT__SHIFT 0x0 |
47010 | #define RTAVFS_REG15__RESERVED__SHIFT 0x10 |
47011 | #define RTAVFS_REG15__RTAVFSCPO7_RIPPLECNT_MASK 0x0000FFFFL |
47012 | #define RTAVFS_REG15__RESERVED_MASK 0xFFFF0000L |
47013 | //RTAVFS_REG16 |
47014 | #define RTAVFS_REG16__RTAVFSCPO8_STARTCNT__SHIFT 0x0 |
47015 | #define RTAVFS_REG16__RTAVFSCPO8_STOPCNT__SHIFT 0x10 |
47016 | #define RTAVFS_REG16__RTAVFSCPO8_STARTCNT_MASK 0x0000FFFFL |
47017 | #define RTAVFS_REG16__RTAVFSCPO8_STOPCNT_MASK 0xFFFF0000L |
47018 | //RTAVFS_REG17 |
47019 | #define RTAVFS_REG17__RTAVFSCPO8_RIPPLECNT__SHIFT 0x0 |
47020 | #define RTAVFS_REG17__RESERVED__SHIFT 0x10 |
47021 | #define RTAVFS_REG17__RTAVFSCPO8_RIPPLECNT_MASK 0x0000FFFFL |
47022 | #define RTAVFS_REG17__RESERVED_MASK 0xFFFF0000L |
47023 | //RTAVFS_REG18 |
47024 | #define RTAVFS_REG18__RTAVFSCPO9_STARTCNT__SHIFT 0x0 |
47025 | #define RTAVFS_REG18__RTAVFSCPO9_STOPCNT__SHIFT 0x10 |
47026 | #define RTAVFS_REG18__RTAVFSCPO9_STARTCNT_MASK 0x0000FFFFL |
47027 | #define RTAVFS_REG18__RTAVFSCPO9_STOPCNT_MASK 0xFFFF0000L |
47028 | //RTAVFS_REG19 |
47029 | #define RTAVFS_REG19__RTAVFSCPO9_RIPPLECNT__SHIFT 0x0 |
47030 | #define RTAVFS_REG19__RESERVED__SHIFT 0x10 |
47031 | #define RTAVFS_REG19__RTAVFSCPO9_RIPPLECNT_MASK 0x0000FFFFL |
47032 | #define RTAVFS_REG19__RESERVED_MASK 0xFFFF0000L |
47033 | //RTAVFS_REG20 |
47034 | #define RTAVFS_REG20__RTAVFSCPO10_STARTCNT__SHIFT 0x0 |
47035 | #define RTAVFS_REG20__RTAVFSCPO10_STOPCNT__SHIFT 0x10 |
47036 | #define RTAVFS_REG20__RTAVFSCPO10_STARTCNT_MASK 0x0000FFFFL |
47037 | #define RTAVFS_REG20__RTAVFSCPO10_STOPCNT_MASK 0xFFFF0000L |
47038 | //RTAVFS_REG21 |
47039 | #define RTAVFS_REG21__RTAVFSCPO10_RIPPLECNT__SHIFT 0x0 |
47040 | #define RTAVFS_REG21__RESERVED__SHIFT 0x10 |
47041 | #define RTAVFS_REG21__RTAVFSCPO10_RIPPLECNT_MASK 0x0000FFFFL |
47042 | #define RTAVFS_REG21__RESERVED_MASK 0xFFFF0000L |
47043 | //RTAVFS_REG22 |
47044 | #define RTAVFS_REG22__RTAVFSCPO11_STARTCNT__SHIFT 0x0 |
47045 | #define RTAVFS_REG22__RTAVFSCPO11_STOPCNT__SHIFT 0x10 |
47046 | #define RTAVFS_REG22__RTAVFSCPO11_STARTCNT_MASK 0x0000FFFFL |
47047 | #define RTAVFS_REG22__RTAVFSCPO11_STOPCNT_MASK 0xFFFF0000L |
47048 | //RTAVFS_REG23 |
47049 | #define RTAVFS_REG23__RTAVFSCPO11_RIPPLECNT__SHIFT 0x0 |
47050 | #define RTAVFS_REG23__RESERVED__SHIFT 0x10 |
47051 | #define RTAVFS_REG23__RTAVFSCPO11_RIPPLECNT_MASK 0x0000FFFFL |
47052 | #define RTAVFS_REG23__RESERVED_MASK 0xFFFF0000L |
47053 | //RTAVFS_REG24 |
47054 | #define RTAVFS_REG24__RTAVFSCPO12_STARTCNT__SHIFT 0x0 |
47055 | #define RTAVFS_REG24__RTAVFSCPO12_STOPCNT__SHIFT 0x10 |
47056 | #define RTAVFS_REG24__RTAVFSCPO12_STARTCNT_MASK 0x0000FFFFL |
47057 | #define RTAVFS_REG24__RTAVFSCPO12_STOPCNT_MASK 0xFFFF0000L |
47058 | //RTAVFS_REG25 |
47059 | #define RTAVFS_REG25__RTAVFSCPO12_RIPPLECNT__SHIFT 0x0 |
47060 | #define RTAVFS_REG25__RESERVED__SHIFT 0x10 |
47061 | #define RTAVFS_REG25__RTAVFSCPO12_RIPPLECNT_MASK 0x0000FFFFL |
47062 | #define RTAVFS_REG25__RESERVED_MASK 0xFFFF0000L |
47063 | //RTAVFS_REG26 |
47064 | #define RTAVFS_REG26__RTAVFSCPO13_STARTCNT__SHIFT 0x0 |
47065 | #define RTAVFS_REG26__RTAVFSCPO13_STOPCNT__SHIFT 0x10 |
47066 | #define RTAVFS_REG26__RTAVFSCPO13_STARTCNT_MASK 0x0000FFFFL |
47067 | #define RTAVFS_REG26__RTAVFSCPO13_STOPCNT_MASK 0xFFFF0000L |
47068 | //RTAVFS_REG27 |
47069 | #define RTAVFS_REG27__RTAVFSCPO13_RIPPLECNT__SHIFT 0x0 |
47070 | #define RTAVFS_REG27__RESERVED__SHIFT 0x10 |
47071 | #define RTAVFS_REG27__RTAVFSCPO13_RIPPLECNT_MASK 0x0000FFFFL |
47072 | #define RTAVFS_REG27__RESERVED_MASK 0xFFFF0000L |
47073 | //RTAVFS_REG28 |
47074 | #define RTAVFS_REG28__RTAVFSCPO14_STARTCNT__SHIFT 0x0 |
47075 | #define RTAVFS_REG28__RTAVFSCPO14_STOPCNT__SHIFT 0x10 |
47076 | #define RTAVFS_REG28__RTAVFSCPO14_STARTCNT_MASK 0x0000FFFFL |
47077 | #define RTAVFS_REG28__RTAVFSCPO14_STOPCNT_MASK 0xFFFF0000L |
47078 | //RTAVFS_REG29 |
47079 | #define RTAVFS_REG29__RTAVFSCPO14_RIPPLECNT__SHIFT 0x0 |
47080 | #define RTAVFS_REG29__RESERVED__SHIFT 0x10 |
47081 | #define RTAVFS_REG29__RTAVFSCPO14_RIPPLECNT_MASK 0x0000FFFFL |
47082 | #define RTAVFS_REG29__RESERVED_MASK 0xFFFF0000L |
47083 | //RTAVFS_REG30 |
47084 | #define RTAVFS_REG30__RTAVFSCPO15_STARTCNT__SHIFT 0x0 |
47085 | #define RTAVFS_REG30__RTAVFSCPO15_STOPCNT__SHIFT 0x10 |
47086 | #define RTAVFS_REG30__RTAVFSCPO15_STARTCNT_MASK 0x0000FFFFL |
47087 | #define RTAVFS_REG30__RTAVFSCPO15_STOPCNT_MASK 0xFFFF0000L |
47088 | //RTAVFS_REG31 |
47089 | #define RTAVFS_REG31__RTAVFSCPO15_RIPPLECNT__SHIFT 0x0 |
47090 | #define RTAVFS_REG31__RESERVED__SHIFT 0x10 |
47091 | #define RTAVFS_REG31__RTAVFSCPO15_RIPPLECNT_MASK 0x0000FFFFL |
47092 | #define RTAVFS_REG31__RESERVED_MASK 0xFFFF0000L |
47093 | //RTAVFS_REG32 |
47094 | #define RTAVFS_REG32__RTAVFSCPO16_STARTCNT__SHIFT 0x0 |
47095 | #define RTAVFS_REG32__RTAVFSCPO16_STOPCNT__SHIFT 0x10 |
47096 | #define RTAVFS_REG32__RTAVFSCPO16_STARTCNT_MASK 0x0000FFFFL |
47097 | #define RTAVFS_REG32__RTAVFSCPO16_STOPCNT_MASK 0xFFFF0000L |
47098 | //RTAVFS_REG33 |
47099 | #define RTAVFS_REG33__RTAVFSCPO16_RIPPLECNT__SHIFT 0x0 |
47100 | #define RTAVFS_REG33__RESERVED__SHIFT 0x10 |
47101 | #define RTAVFS_REG33__RTAVFSCPO16_RIPPLECNT_MASK 0x0000FFFFL |
47102 | #define RTAVFS_REG33__RESERVED_MASK 0xFFFF0000L |
47103 | //RTAVFS_REG34 |
47104 | #define RTAVFS_REG34__RTAVFSCPO17_STARTCNT__SHIFT 0x0 |
47105 | #define RTAVFS_REG34__RTAVFSCPO17_STOPCNT__SHIFT 0x10 |
47106 | #define RTAVFS_REG34__RTAVFSCPO17_STARTCNT_MASK 0x0000FFFFL |
47107 | #define RTAVFS_REG34__RTAVFSCPO17_STOPCNT_MASK 0xFFFF0000L |
47108 | //RTAVFS_REG35 |
47109 | #define RTAVFS_REG35__RTAVFSCPO17_RIPPLECNT__SHIFT 0x0 |
47110 | #define RTAVFS_REG35__RESERVED__SHIFT 0x10 |
47111 | #define RTAVFS_REG35__RTAVFSCPO17_RIPPLECNT_MASK 0x0000FFFFL |
47112 | #define RTAVFS_REG35__RESERVED_MASK 0xFFFF0000L |
47113 | //RTAVFS_REG36 |
47114 | #define RTAVFS_REG36__RTAVFSCPO18_STARTCNT__SHIFT 0x0 |
47115 | #define RTAVFS_REG36__RTAVFSCPO18_STOPCNT__SHIFT 0x10 |
47116 | #define RTAVFS_REG36__RTAVFSCPO18_STARTCNT_MASK 0x0000FFFFL |
47117 | #define RTAVFS_REG36__RTAVFSCPO18_STOPCNT_MASK 0xFFFF0000L |
47118 | //RTAVFS_REG37 |
47119 | #define RTAVFS_REG37__RTAVFSCPO18_RIPPLECNT__SHIFT 0x0 |
47120 | #define RTAVFS_REG37__RESERVED__SHIFT 0x10 |
47121 | #define RTAVFS_REG37__RTAVFSCPO18_RIPPLECNT_MASK 0x0000FFFFL |
47122 | #define RTAVFS_REG37__RESERVED_MASK 0xFFFF0000L |
47123 | //RTAVFS_REG38 |
47124 | #define RTAVFS_REG38__RTAVFSCPO19_STARTCNT__SHIFT 0x0 |
47125 | #define RTAVFS_REG38__RTAVFSCPO19_STOPCNT__SHIFT 0x10 |
47126 | #define RTAVFS_REG38__RTAVFSCPO19_STARTCNT_MASK 0x0000FFFFL |
47127 | #define RTAVFS_REG38__RTAVFSCPO19_STOPCNT_MASK 0xFFFF0000L |
47128 | //RTAVFS_REG39 |
47129 | #define RTAVFS_REG39__RTAVFSCPO19_RIPPLECNT__SHIFT 0x0 |
47130 | #define RTAVFS_REG39__RESERVED__SHIFT 0x10 |
47131 | #define RTAVFS_REG39__RTAVFSCPO19_RIPPLECNT_MASK 0x0000FFFFL |
47132 | #define RTAVFS_REG39__RESERVED_MASK 0xFFFF0000L |
47133 | //RTAVFS_REG40 |
47134 | #define RTAVFS_REG40__RTAVFSCPO20_STARTCNT__SHIFT 0x0 |
47135 | #define RTAVFS_REG40__RTAVFSCPO20_STOPCNT__SHIFT 0x10 |
47136 | #define RTAVFS_REG40__RTAVFSCPO20_STARTCNT_MASK 0x0000FFFFL |
47137 | #define RTAVFS_REG40__RTAVFSCPO20_STOPCNT_MASK 0xFFFF0000L |
47138 | //RTAVFS_REG41 |
47139 | #define RTAVFS_REG41__RTAVFSCPO20_RIPPLECNT__SHIFT 0x0 |
47140 | #define RTAVFS_REG41__RESERVED__SHIFT 0x10 |
47141 | #define RTAVFS_REG41__RTAVFSCPO20_RIPPLECNT_MASK 0x0000FFFFL |
47142 | #define RTAVFS_REG41__RESERVED_MASK 0xFFFF0000L |
47143 | //RTAVFS_REG42 |
47144 | #define RTAVFS_REG42__RTAVFSCPO21_STARTCNT__SHIFT 0x0 |
47145 | #define RTAVFS_REG42__RTAVFSCPO21_STOPCNT__SHIFT 0x10 |
47146 | #define RTAVFS_REG42__RTAVFSCPO21_STARTCNT_MASK 0x0000FFFFL |
47147 | #define RTAVFS_REG42__RTAVFSCPO21_STOPCNT_MASK 0xFFFF0000L |
47148 | //RTAVFS_REG43 |
47149 | #define RTAVFS_REG43__RTAVFSCPO21_RIPPLECNT__SHIFT 0x0 |
47150 | #define RTAVFS_REG43__RESERVED__SHIFT 0x10 |
47151 | #define RTAVFS_REG43__RTAVFSCPO21_RIPPLECNT_MASK 0x0000FFFFL |
47152 | #define RTAVFS_REG43__RESERVED_MASK 0xFFFF0000L |
47153 | //RTAVFS_REG44 |
47154 | #define RTAVFS_REG44__RTAVFSCPO22_STARTCNT__SHIFT 0x0 |
47155 | #define RTAVFS_REG44__RTAVFSCPO22_STOPCNT__SHIFT 0x10 |
47156 | #define RTAVFS_REG44__RTAVFSCPO22_STARTCNT_MASK 0x0000FFFFL |
47157 | #define RTAVFS_REG44__RTAVFSCPO22_STOPCNT_MASK 0xFFFF0000L |
47158 | //RTAVFS_REG45 |
47159 | #define RTAVFS_REG45__RTAVFSCPO22_RIPPLECNT__SHIFT 0x0 |
47160 | #define RTAVFS_REG45__RESERVED__SHIFT 0x10 |
47161 | #define RTAVFS_REG45__RTAVFSCPO22_RIPPLECNT_MASK 0x0000FFFFL |
47162 | #define RTAVFS_REG45__RESERVED_MASK 0xFFFF0000L |
47163 | //RTAVFS_REG46 |
47164 | #define RTAVFS_REG46__RTAVFSCPO23_STARTCNT__SHIFT 0x0 |
47165 | #define RTAVFS_REG46__RTAVFSCPO23_STOPCNT__SHIFT 0x10 |
47166 | #define RTAVFS_REG46__RTAVFSCPO23_STARTCNT_MASK 0x0000FFFFL |
47167 | #define RTAVFS_REG46__RTAVFSCPO23_STOPCNT_MASK 0xFFFF0000L |
47168 | //RTAVFS_REG47 |
47169 | #define RTAVFS_REG47__RTAVFSCPO23_RIPPLECNT__SHIFT 0x0 |
47170 | #define RTAVFS_REG47__RESERVED__SHIFT 0x10 |
47171 | #define RTAVFS_REG47__RTAVFSCPO23_RIPPLECNT_MASK 0x0000FFFFL |
47172 | #define RTAVFS_REG47__RESERVED_MASK 0xFFFF0000L |
47173 | //RTAVFS_REG48 |
47174 | #define RTAVFS_REG48__RTAVFSCPO24_STARTCNT__SHIFT 0x0 |
47175 | #define RTAVFS_REG48__RTAVFSCPO24_STOPCNT__SHIFT 0x10 |
47176 | #define RTAVFS_REG48__RTAVFSCPO24_STARTCNT_MASK 0x0000FFFFL |
47177 | #define RTAVFS_REG48__RTAVFSCPO24_STOPCNT_MASK 0xFFFF0000L |
47178 | //RTAVFS_REG49 |
47179 | #define RTAVFS_REG49__RTAVFSCPO24_RIPPLECNT__SHIFT 0x0 |
47180 | #define RTAVFS_REG49__RESERVED__SHIFT 0x10 |
47181 | #define RTAVFS_REG49__RTAVFSCPO24_RIPPLECNT_MASK 0x0000FFFFL |
47182 | #define RTAVFS_REG49__RESERVED_MASK 0xFFFF0000L |
47183 | //RTAVFS_REG50 |
47184 | #define RTAVFS_REG50__RTAVFSCPO25_STARTCNT__SHIFT 0x0 |
47185 | #define RTAVFS_REG50__RTAVFSCPO25_STOPCNT__SHIFT 0x10 |
47186 | #define RTAVFS_REG50__RTAVFSCPO25_STARTCNT_MASK 0x0000FFFFL |
47187 | #define RTAVFS_REG50__RTAVFSCPO25_STOPCNT_MASK 0xFFFF0000L |
47188 | //RTAVFS_REG51 |
47189 | #define RTAVFS_REG51__RTAVFSCPO25_RIPPLECNT__SHIFT 0x0 |
47190 | #define RTAVFS_REG51__RESERVED__SHIFT 0x10 |
47191 | #define RTAVFS_REG51__RTAVFSCPO25_RIPPLECNT_MASK 0x0000FFFFL |
47192 | #define RTAVFS_REG51__RESERVED_MASK 0xFFFF0000L |
47193 | //RTAVFS_REG52 |
47194 | #define RTAVFS_REG52__RTAVFSCPO26_STARTCNT__SHIFT 0x0 |
47195 | #define RTAVFS_REG52__RTAVFSCPO26_STOPCNT__SHIFT 0x10 |
47196 | #define RTAVFS_REG52__RTAVFSCPO26_STARTCNT_MASK 0x0000FFFFL |
47197 | #define RTAVFS_REG52__RTAVFSCPO26_STOPCNT_MASK 0xFFFF0000L |
47198 | //RTAVFS_REG53 |
47199 | #define RTAVFS_REG53__RTAVFSCPO26_RIPPLECNT__SHIFT 0x0 |
47200 | #define RTAVFS_REG53__RESERVED__SHIFT 0x10 |
47201 | #define RTAVFS_REG53__RTAVFSCPO26_RIPPLECNT_MASK 0x0000FFFFL |
47202 | #define RTAVFS_REG53__RESERVED_MASK 0xFFFF0000L |
47203 | //RTAVFS_REG54 |
47204 | #define RTAVFS_REG54__RTAVFSCPO27_STARTCNT__SHIFT 0x0 |
47205 | #define RTAVFS_REG54__RTAVFSCPO27_STOPCNT__SHIFT 0x10 |
47206 | #define RTAVFS_REG54__RTAVFSCPO27_STARTCNT_MASK 0x0000FFFFL |
47207 | #define RTAVFS_REG54__RTAVFSCPO27_STOPCNT_MASK 0xFFFF0000L |
47208 | //RTAVFS_REG55 |
47209 | #define RTAVFS_REG55__RTAVFSCPO27_RIPPLECNT__SHIFT 0x0 |
47210 | #define RTAVFS_REG55__RESERVED__SHIFT 0x10 |
47211 | #define RTAVFS_REG55__RTAVFSCPO27_RIPPLECNT_MASK 0x0000FFFFL |
47212 | #define RTAVFS_REG55__RESERVED_MASK 0xFFFF0000L |
47213 | //RTAVFS_REG56 |
47214 | #define RTAVFS_REG56__RTAVFSCPO28_STARTCNT__SHIFT 0x0 |
47215 | #define RTAVFS_REG56__RTAVFSCPO28_STOPCNT__SHIFT 0x10 |
47216 | #define RTAVFS_REG56__RTAVFSCPO28_STARTCNT_MASK 0x0000FFFFL |
47217 | #define RTAVFS_REG56__RTAVFSCPO28_STOPCNT_MASK 0xFFFF0000L |
47218 | //RTAVFS_REG57 |
47219 | #define RTAVFS_REG57__RTAVFSCPO28_RIPPLECNT__SHIFT 0x0 |
47220 | #define RTAVFS_REG57__RESERVED__SHIFT 0x10 |
47221 | #define RTAVFS_REG57__RTAVFSCPO28_RIPPLECNT_MASK 0x0000FFFFL |
47222 | #define RTAVFS_REG57__RESERVED_MASK 0xFFFF0000L |
47223 | //RTAVFS_REG58 |
47224 | #define RTAVFS_REG58__RTAVFSCPO29_STARTCNT__SHIFT 0x0 |
47225 | #define RTAVFS_REG58__RTAVFSCPO29_STOPCNT__SHIFT 0x10 |
47226 | #define RTAVFS_REG58__RTAVFSCPO29_STARTCNT_MASK 0x0000FFFFL |
47227 | #define RTAVFS_REG58__RTAVFSCPO29_STOPCNT_MASK 0xFFFF0000L |
47228 | //RTAVFS_REG59 |
47229 | #define RTAVFS_REG59__RTAVFSCPO29_RIPPLECNT__SHIFT 0x0 |
47230 | #define RTAVFS_REG59__RESERVED__SHIFT 0x10 |
47231 | #define RTAVFS_REG59__RTAVFSCPO29_RIPPLECNT_MASK 0x0000FFFFL |
47232 | #define RTAVFS_REG59__RESERVED_MASK 0xFFFF0000L |
47233 | //RTAVFS_REG60 |
47234 | #define RTAVFS_REG60__RTAVFSCPO30_STARTCNT__SHIFT 0x0 |
47235 | #define RTAVFS_REG60__RTAVFSCPO30_STOPCNT__SHIFT 0x10 |
47236 | #define RTAVFS_REG60__RTAVFSCPO30_STARTCNT_MASK 0x0000FFFFL |
47237 | #define RTAVFS_REG60__RTAVFSCPO30_STOPCNT_MASK 0xFFFF0000L |
47238 | //RTAVFS_REG61 |
47239 | #define RTAVFS_REG61__RTAVFSCPO30_RIPPLECNT__SHIFT 0x0 |
47240 | #define RTAVFS_REG61__RESERVED__SHIFT 0x10 |
47241 | #define RTAVFS_REG61__RTAVFSCPO30_RIPPLECNT_MASK 0x0000FFFFL |
47242 | #define RTAVFS_REG61__RESERVED_MASK 0xFFFF0000L |
47243 | //RTAVFS_REG62 |
47244 | #define RTAVFS_REG62__RTAVFSCPO31_STARTCNT__SHIFT 0x0 |
47245 | #define RTAVFS_REG62__RTAVFSCPO31_STOPCNT__SHIFT 0x10 |
47246 | #define RTAVFS_REG62__RTAVFSCPO31_STARTCNT_MASK 0x0000FFFFL |
47247 | #define RTAVFS_REG62__RTAVFSCPO31_STOPCNT_MASK 0xFFFF0000L |
47248 | //RTAVFS_REG63 |
47249 | #define RTAVFS_REG63__RTAVFSCPO31_RIPPLECNT__SHIFT 0x0 |
47250 | #define RTAVFS_REG63__RESERVED__SHIFT 0x10 |
47251 | #define RTAVFS_REG63__RTAVFSCPO31_RIPPLECNT_MASK 0x0000FFFFL |
47252 | #define RTAVFS_REG63__RESERVED_MASK 0xFFFF0000L |
47253 | //RTAVFS_REG64 |
47254 | #define RTAVFS_REG64__RTAVFSCPO32_STARTCNT__SHIFT 0x0 |
47255 | #define RTAVFS_REG64__RTAVFSCPO32_STOPCNT__SHIFT 0x10 |
47256 | #define RTAVFS_REG64__RTAVFSCPO32_STARTCNT_MASK 0x0000FFFFL |
47257 | #define RTAVFS_REG64__RTAVFSCPO32_STOPCNT_MASK 0xFFFF0000L |
47258 | //RTAVFS_REG65 |
47259 | #define RTAVFS_REG65__RTAVFSCPO32_RIPPLECNT__SHIFT 0x0 |
47260 | #define RTAVFS_REG65__RESERVED__SHIFT 0x10 |
47261 | #define RTAVFS_REG65__RTAVFSCPO32_RIPPLECNT_MASK 0x0000FFFFL |
47262 | #define RTAVFS_REG65__RESERVED_MASK 0xFFFF0000L |
47263 | //RTAVFS_REG66 |
47264 | #define RTAVFS_REG66__RTAVFSCPO33_STARTCNT__SHIFT 0x0 |
47265 | #define RTAVFS_REG66__RTAVFSCPO33_STOPCNT__SHIFT 0x10 |
47266 | #define RTAVFS_REG66__RTAVFSCPO33_STARTCNT_MASK 0x0000FFFFL |
47267 | #define RTAVFS_REG66__RTAVFSCPO33_STOPCNT_MASK 0xFFFF0000L |
47268 | //RTAVFS_REG67 |
47269 | #define RTAVFS_REG67__RTAVFSCPO33_RIPPLECNT__SHIFT 0x0 |
47270 | #define RTAVFS_REG67__RESERVED__SHIFT 0x10 |
47271 | #define RTAVFS_REG67__RTAVFSCPO33_RIPPLECNT_MASK 0x0000FFFFL |
47272 | #define RTAVFS_REG67__RESERVED_MASK 0xFFFF0000L |
47273 | //RTAVFS_REG68 |
47274 | #define RTAVFS_REG68__RTAVFSCPO34_STARTCNT__SHIFT 0x0 |
47275 | #define RTAVFS_REG68__RTAVFSCPO34_STOPCNT__SHIFT 0x10 |
47276 | #define RTAVFS_REG68__RTAVFSCPO34_STARTCNT_MASK 0x0000FFFFL |
47277 | #define RTAVFS_REG68__RTAVFSCPO34_STOPCNT_MASK 0xFFFF0000L |
47278 | //RTAVFS_REG69 |
47279 | #define RTAVFS_REG69__RTAVFSCPO34_RIPPLECNT__SHIFT 0x0 |
47280 | #define RTAVFS_REG69__RESERVED__SHIFT 0x10 |
47281 | #define RTAVFS_REG69__RTAVFSCPO34_RIPPLECNT_MASK 0x0000FFFFL |
47282 | #define RTAVFS_REG69__RESERVED_MASK 0xFFFF0000L |
47283 | //RTAVFS_REG70 |
47284 | #define RTAVFS_REG70__RTAVFSCPO35_STARTCNT__SHIFT 0x0 |
47285 | #define RTAVFS_REG70__RTAVFSCPO35_STOPCNT__SHIFT 0x10 |
47286 | #define RTAVFS_REG70__RTAVFSCPO35_STARTCNT_MASK 0x0000FFFFL |
47287 | #define RTAVFS_REG70__RTAVFSCPO35_STOPCNT_MASK 0xFFFF0000L |
47288 | //RTAVFS_REG71 |
47289 | #define RTAVFS_REG71__RTAVFSCPO35_RIPPLECNT__SHIFT 0x0 |
47290 | #define RTAVFS_REG71__RESERVED__SHIFT 0x10 |
47291 | #define RTAVFS_REG71__RTAVFSCPO35_RIPPLECNT_MASK 0x0000FFFFL |
47292 | #define RTAVFS_REG71__RESERVED_MASK 0xFFFF0000L |
47293 | //RTAVFS_REG72 |
47294 | #define RTAVFS_REG72__RTAVFSCPO36_STARTCNT__SHIFT 0x0 |
47295 | #define RTAVFS_REG72__RTAVFSCPO36_STOPCNT__SHIFT 0x10 |
47296 | #define RTAVFS_REG72__RTAVFSCPO36_STARTCNT_MASK 0x0000FFFFL |
47297 | #define RTAVFS_REG72__RTAVFSCPO36_STOPCNT_MASK 0xFFFF0000L |
47298 | //RTAVFS_REG73 |
47299 | #define RTAVFS_REG73__RTAVFSCPO36_RIPPLECNT__SHIFT 0x0 |
47300 | #define RTAVFS_REG73__RESERVED__SHIFT 0x10 |
47301 | #define RTAVFS_REG73__RTAVFSCPO36_RIPPLECNT_MASK 0x0000FFFFL |
47302 | #define RTAVFS_REG73__RESERVED_MASK 0xFFFF0000L |
47303 | //RTAVFS_REG74 |
47304 | #define RTAVFS_REG74__RTAVFSCPO37_STARTCNT__SHIFT 0x0 |
47305 | #define RTAVFS_REG74__RTAVFSCPO37_STOPCNT__SHIFT 0x10 |
47306 | #define RTAVFS_REG74__RTAVFSCPO37_STARTCNT_MASK 0x0000FFFFL |
47307 | #define RTAVFS_REG74__RTAVFSCPO37_STOPCNT_MASK 0xFFFF0000L |
47308 | //RTAVFS_REG75 |
47309 | #define RTAVFS_REG75__RTAVFSCPO37_RIPPLECNT__SHIFT 0x0 |
47310 | #define RTAVFS_REG75__RESERVED__SHIFT 0x10 |
47311 | #define RTAVFS_REG75__RTAVFSCPO37_RIPPLECNT_MASK 0x0000FFFFL |
47312 | #define RTAVFS_REG75__RESERVED_MASK 0xFFFF0000L |
47313 | //RTAVFS_REG76 |
47314 | #define RTAVFS_REG76__RTAVFSCPO38_STARTCNT__SHIFT 0x0 |
47315 | #define RTAVFS_REG76__RTAVFSCPO38_STOPCNT__SHIFT 0x10 |
47316 | #define RTAVFS_REG76__RTAVFSCPO38_STARTCNT_MASK 0x0000FFFFL |
47317 | #define RTAVFS_REG76__RTAVFSCPO38_STOPCNT_MASK 0xFFFF0000L |
47318 | //RTAVFS_REG77 |
47319 | #define RTAVFS_REG77__RTAVFSCPO38_RIPPLECNT__SHIFT 0x0 |
47320 | #define RTAVFS_REG77__RESERVED__SHIFT 0x10 |
47321 | #define RTAVFS_REG77__RTAVFSCPO38_RIPPLECNT_MASK 0x0000FFFFL |
47322 | #define RTAVFS_REG77__RESERVED_MASK 0xFFFF0000L |
47323 | //RTAVFS_REG78 |
47324 | #define RTAVFS_REG78__RTAVFSCPO39_STARTCNT__SHIFT 0x0 |
47325 | #define RTAVFS_REG78__RTAVFSCPO39_STOPCNT__SHIFT 0x10 |
47326 | #define RTAVFS_REG78__RTAVFSCPO39_STARTCNT_MASK 0x0000FFFFL |
47327 | #define RTAVFS_REG78__RTAVFSCPO39_STOPCNT_MASK 0xFFFF0000L |
47328 | //RTAVFS_REG79 |
47329 | #define RTAVFS_REG79__RTAVFSCPO39_RIPPLECNT__SHIFT 0x0 |
47330 | #define RTAVFS_REG79__RESERVED__SHIFT 0x10 |
47331 | #define RTAVFS_REG79__RTAVFSCPO39_RIPPLECNT_MASK 0x0000FFFFL |
47332 | #define RTAVFS_REG79__RESERVED_MASK 0xFFFF0000L |
47333 | //RTAVFS_REG80 |
47334 | #define RTAVFS_REG80__RTAVFSCPO40_STARTCNT__SHIFT 0x0 |
47335 | #define RTAVFS_REG80__RTAVFSCPO40_STOPCNT__SHIFT 0x10 |
47336 | #define RTAVFS_REG80__RTAVFSCPO40_STARTCNT_MASK 0x0000FFFFL |
47337 | #define RTAVFS_REG80__RTAVFSCPO40_STOPCNT_MASK 0xFFFF0000L |
47338 | //RTAVFS_REG81 |
47339 | #define RTAVFS_REG81__RTAVFSCPO40_RIPPLECNT__SHIFT 0x0 |
47340 | #define RTAVFS_REG81__RESERVED__SHIFT 0x10 |
47341 | #define RTAVFS_REG81__RTAVFSCPO40_RIPPLECNT_MASK 0x0000FFFFL |
47342 | #define RTAVFS_REG81__RESERVED_MASK 0xFFFF0000L |
47343 | //RTAVFS_REG82 |
47344 | #define RTAVFS_REG82__RTAVFSCPO41_STARTCNT__SHIFT 0x0 |
47345 | #define RTAVFS_REG82__RTAVFSCPO41_STOPCNT__SHIFT 0x10 |
47346 | #define RTAVFS_REG82__RTAVFSCPO41_STARTCNT_MASK 0x0000FFFFL |
47347 | #define RTAVFS_REG82__RTAVFSCPO41_STOPCNT_MASK 0xFFFF0000L |
47348 | //RTAVFS_REG83 |
47349 | #define RTAVFS_REG83__RTAVFSCPO41_RIPPLECNT__SHIFT 0x0 |
47350 | #define RTAVFS_REG83__RESERVED__SHIFT 0x10 |
47351 | #define RTAVFS_REG83__RTAVFSCPO41_RIPPLECNT_MASK 0x0000FFFFL |
47352 | #define RTAVFS_REG83__RESERVED_MASK 0xFFFF0000L |
47353 | //RTAVFS_REG84 |
47354 | #define RTAVFS_REG84__RTAVFSCPO42_STARTCNT__SHIFT 0x0 |
47355 | #define RTAVFS_REG84__RTAVFSCPO42_STOPCNT__SHIFT 0x10 |
47356 | #define RTAVFS_REG84__RTAVFSCPO42_STARTCNT_MASK 0x0000FFFFL |
47357 | #define RTAVFS_REG84__RTAVFSCPO42_STOPCNT_MASK 0xFFFF0000L |
47358 | //RTAVFS_REG85 |
47359 | #define RTAVFS_REG85__RTAVFSCPO42_RIPPLECNT__SHIFT 0x0 |
47360 | #define RTAVFS_REG85__RESERVED__SHIFT 0x10 |
47361 | #define RTAVFS_REG85__RTAVFSCPO42_RIPPLECNT_MASK 0x0000FFFFL |
47362 | #define RTAVFS_REG85__RESERVED_MASK 0xFFFF0000L |
47363 | //RTAVFS_REG86 |
47364 | #define RTAVFS_REG86__RTAVFSCPO43_STARTCNT__SHIFT 0x0 |
47365 | #define RTAVFS_REG86__RTAVFSCPO43_STOPCNT__SHIFT 0x10 |
47366 | #define RTAVFS_REG86__RTAVFSCPO43_STARTCNT_MASK 0x0000FFFFL |
47367 | #define RTAVFS_REG86__RTAVFSCPO43_STOPCNT_MASK 0xFFFF0000L |
47368 | //RTAVFS_REG87 |
47369 | #define RTAVFS_REG87__RTAVFSCPO43_RIPPLECNT__SHIFT 0x0 |
47370 | #define RTAVFS_REG87__RESERVED__SHIFT 0x10 |
47371 | #define RTAVFS_REG87__RTAVFSCPO43_RIPPLECNT_MASK 0x0000FFFFL |
47372 | #define RTAVFS_REG87__RESERVED_MASK 0xFFFF0000L |
47373 | //RTAVFS_REG88 |
47374 | #define RTAVFS_REG88__RTAVFSCPO44_STARTCNT__SHIFT 0x0 |
47375 | #define RTAVFS_REG88__RTAVFSCPO44_STOPCNT__SHIFT 0x10 |
47376 | #define RTAVFS_REG88__RTAVFSCPO44_STARTCNT_MASK 0x0000FFFFL |
47377 | #define RTAVFS_REG88__RTAVFSCPO44_STOPCNT_MASK 0xFFFF0000L |
47378 | //RTAVFS_REG89 |
47379 | #define RTAVFS_REG89__RTAVFSCPO44_RIPPLECNT__SHIFT 0x0 |
47380 | #define RTAVFS_REG89__RESERVED__SHIFT 0x10 |
47381 | #define RTAVFS_REG89__RTAVFSCPO44_RIPPLECNT_MASK 0x0000FFFFL |
47382 | #define RTAVFS_REG89__RESERVED_MASK 0xFFFF0000L |
47383 | //RTAVFS_REG90 |
47384 | #define RTAVFS_REG90__RTAVFSCPO45_STARTCNT__SHIFT 0x0 |
47385 | #define RTAVFS_REG90__RTAVFSCPO45_STOPCNT__SHIFT 0x10 |
47386 | #define RTAVFS_REG90__RTAVFSCPO45_STARTCNT_MASK 0x0000FFFFL |
47387 | #define RTAVFS_REG90__RTAVFSCPO45_STOPCNT_MASK 0xFFFF0000L |
47388 | //RTAVFS_REG91 |
47389 | #define RTAVFS_REG91__RTAVFSCPO45_RIPPLECNT__SHIFT 0x0 |
47390 | #define RTAVFS_REG91__RESERVED__SHIFT 0x10 |
47391 | #define RTAVFS_REG91__RTAVFSCPO45_RIPPLECNT_MASK 0x0000FFFFL |
47392 | #define RTAVFS_REG91__RESERVED_MASK 0xFFFF0000L |
47393 | //RTAVFS_REG92 |
47394 | #define RTAVFS_REG92__RTAVFSCPO46_STARTCNT__SHIFT 0x0 |
47395 | #define RTAVFS_REG92__RTAVFSCPO46_STOPCNT__SHIFT 0x10 |
47396 | #define RTAVFS_REG92__RTAVFSCPO46_STARTCNT_MASK 0x0000FFFFL |
47397 | #define RTAVFS_REG92__RTAVFSCPO46_STOPCNT_MASK 0xFFFF0000L |
47398 | //RTAVFS_REG93 |
47399 | #define RTAVFS_REG93__RTAVFSCPO46_RIPPLECNT__SHIFT 0x0 |
47400 | #define RTAVFS_REG93__RESERVED__SHIFT 0x10 |
47401 | #define RTAVFS_REG93__RTAVFSCPO46_RIPPLECNT_MASK 0x0000FFFFL |
47402 | #define RTAVFS_REG93__RESERVED_MASK 0xFFFF0000L |
47403 | //RTAVFS_REG94 |
47404 | #define RTAVFS_REG94__RTAVFSCPO47_STARTCNT__SHIFT 0x0 |
47405 | #define RTAVFS_REG94__RTAVFSCPO47_STOPCNT__SHIFT 0x10 |
47406 | #define RTAVFS_REG94__RTAVFSCPO47_STARTCNT_MASK 0x0000FFFFL |
47407 | #define RTAVFS_REG94__RTAVFSCPO47_STOPCNT_MASK 0xFFFF0000L |
47408 | //RTAVFS_REG95 |
47409 | #define RTAVFS_REG95__RTAVFSCPO47_RIPPLECNT__SHIFT 0x0 |
47410 | #define RTAVFS_REG95__RESERVED__SHIFT 0x10 |
47411 | #define RTAVFS_REG95__RTAVFSCPO47_RIPPLECNT_MASK 0x0000FFFFL |
47412 | #define RTAVFS_REG95__RESERVED_MASK 0xFFFF0000L |
47413 | //RTAVFS_REG96 |
47414 | #define RTAVFS_REG96__RTAVFSCPO48_STARTCNT__SHIFT 0x0 |
47415 | #define RTAVFS_REG96__RTAVFSCPO48_STOPCNT__SHIFT 0x10 |
47416 | #define RTAVFS_REG96__RTAVFSCPO48_STARTCNT_MASK 0x0000FFFFL |
47417 | #define RTAVFS_REG96__RTAVFSCPO48_STOPCNT_MASK 0xFFFF0000L |
47418 | //RTAVFS_REG97 |
47419 | #define RTAVFS_REG97__RTAVFSCPO48_RIPPLECNT__SHIFT 0x0 |
47420 | #define RTAVFS_REG97__RESERVED__SHIFT 0x10 |
47421 | #define RTAVFS_REG97__RTAVFSCPO48_RIPPLECNT_MASK 0x0000FFFFL |
47422 | #define RTAVFS_REG97__RESERVED_MASK 0xFFFF0000L |
47423 | //RTAVFS_REG98 |
47424 | #define RTAVFS_REG98__RTAVFSCPO49_STARTCNT__SHIFT 0x0 |
47425 | #define RTAVFS_REG98__RTAVFSCPO49_STOPCNT__SHIFT 0x10 |
47426 | #define RTAVFS_REG98__RTAVFSCPO49_STARTCNT_MASK 0x0000FFFFL |
47427 | #define RTAVFS_REG98__RTAVFSCPO49_STOPCNT_MASK 0xFFFF0000L |
47428 | //RTAVFS_REG99 |
47429 | #define RTAVFS_REG99__RTAVFSCPO49_RIPPLECNT__SHIFT 0x0 |
47430 | #define RTAVFS_REG99__RESERVED__SHIFT 0x10 |
47431 | #define RTAVFS_REG99__RTAVFSCPO49_RIPPLECNT_MASK 0x0000FFFFL |
47432 | #define RTAVFS_REG99__RESERVED_MASK 0xFFFF0000L |
47433 | //RTAVFS_REG100 |
47434 | #define RTAVFS_REG100__RTAVFSCPO50_STARTCNT__SHIFT 0x0 |
47435 | #define RTAVFS_REG100__RTAVFSCPO50_STOPCNT__SHIFT 0x10 |
47436 | #define RTAVFS_REG100__RTAVFSCPO50_STARTCNT_MASK 0x0000FFFFL |
47437 | #define RTAVFS_REG100__RTAVFSCPO50_STOPCNT_MASK 0xFFFF0000L |
47438 | //RTAVFS_REG101 |
47439 | #define RTAVFS_REG101__RTAVFSCPO50_RIPPLECNT__SHIFT 0x0 |
47440 | #define RTAVFS_REG101__RESERVED__SHIFT 0x10 |
47441 | #define RTAVFS_REG101__RTAVFSCPO50_RIPPLECNT_MASK 0x0000FFFFL |
47442 | #define RTAVFS_REG101__RESERVED_MASK 0xFFFF0000L |
47443 | //RTAVFS_REG102 |
47444 | #define RTAVFS_REG102__RTAVFSCPO51_STARTCNT__SHIFT 0x0 |
47445 | #define RTAVFS_REG102__RTAVFSCPO51_STOPCNT__SHIFT 0x10 |
47446 | #define RTAVFS_REG102__RTAVFSCPO51_STARTCNT_MASK 0x0000FFFFL |
47447 | #define RTAVFS_REG102__RTAVFSCPO51_STOPCNT_MASK 0xFFFF0000L |
47448 | //RTAVFS_REG103 |
47449 | #define RTAVFS_REG103__RTAVFSCPO51_RIPPLECNT__SHIFT 0x0 |
47450 | #define RTAVFS_REG103__RESERVED__SHIFT 0x10 |
47451 | #define RTAVFS_REG103__RTAVFSCPO51_RIPPLECNT_MASK 0x0000FFFFL |
47452 | #define RTAVFS_REG103__RESERVED_MASK 0xFFFF0000L |
47453 | //RTAVFS_REG104 |
47454 | #define RTAVFS_REG104__RTAVFSCPO52_STARTCNT__SHIFT 0x0 |
47455 | #define RTAVFS_REG104__RTAVFSCPO52_STOPCNT__SHIFT 0x10 |
47456 | #define RTAVFS_REG104__RTAVFSCPO52_STARTCNT_MASK 0x0000FFFFL |
47457 | #define RTAVFS_REG104__RTAVFSCPO52_STOPCNT_MASK 0xFFFF0000L |
47458 | //RTAVFS_REG105 |
47459 | #define RTAVFS_REG105__RTAVFSCPO52_RIPPLECNT__SHIFT 0x0 |
47460 | #define RTAVFS_REG105__RESERVED__SHIFT 0x10 |
47461 | #define RTAVFS_REG105__RTAVFSCPO52_RIPPLECNT_MASK 0x0000FFFFL |
47462 | #define RTAVFS_REG105__RESERVED_MASK 0xFFFF0000L |
47463 | //RTAVFS_REG106 |
47464 | #define RTAVFS_REG106__RTAVFSCPO53_STARTCNT__SHIFT 0x0 |
47465 | #define RTAVFS_REG106__RTAVFSCPO53_STOPCNT__SHIFT 0x10 |
47466 | #define RTAVFS_REG106__RTAVFSCPO53_STARTCNT_MASK 0x0000FFFFL |
47467 | #define RTAVFS_REG106__RTAVFSCPO53_STOPCNT_MASK 0xFFFF0000L |
47468 | //RTAVFS_REG107 |
47469 | #define RTAVFS_REG107__RTAVFSCPO53_RIPPLECNT__SHIFT 0x0 |
47470 | #define RTAVFS_REG107__RESERVED__SHIFT 0x10 |
47471 | #define RTAVFS_REG107__RTAVFSCPO53_RIPPLECNT_MASK 0x0000FFFFL |
47472 | #define RTAVFS_REG107__RESERVED_MASK 0xFFFF0000L |
47473 | //RTAVFS_REG108 |
47474 | #define RTAVFS_REG108__RTAVFSCPO54_STARTCNT__SHIFT 0x0 |
47475 | #define RTAVFS_REG108__RTAVFSCPO54_STOPCNT__SHIFT 0x10 |
47476 | #define RTAVFS_REG108__RTAVFSCPO54_STARTCNT_MASK 0x0000FFFFL |
47477 | #define RTAVFS_REG108__RTAVFSCPO54_STOPCNT_MASK 0xFFFF0000L |
47478 | //RTAVFS_REG109 |
47479 | #define RTAVFS_REG109__RTAVFSCPO54_RIPPLECNT__SHIFT 0x0 |
47480 | #define RTAVFS_REG109__RESERVED__SHIFT 0x10 |
47481 | #define RTAVFS_REG109__RTAVFSCPO54_RIPPLECNT_MASK 0x0000FFFFL |
47482 | #define RTAVFS_REG109__RESERVED_MASK 0xFFFF0000L |
47483 | //RTAVFS_REG110 |
47484 | #define RTAVFS_REG110__RTAVFSCPO55_STARTCNT__SHIFT 0x0 |
47485 | #define RTAVFS_REG110__RTAVFSCPO55_STOPCNT__SHIFT 0x10 |
47486 | #define RTAVFS_REG110__RTAVFSCPO55_STARTCNT_MASK 0x0000FFFFL |
47487 | #define RTAVFS_REG110__RTAVFSCPO55_STOPCNT_MASK 0xFFFF0000L |
47488 | //RTAVFS_REG111 |
47489 | #define RTAVFS_REG111__RTAVFSCPO55_RIPPLECNT__SHIFT 0x0 |
47490 | #define RTAVFS_REG111__RESERVED__SHIFT 0x10 |
47491 | #define RTAVFS_REG111__RTAVFSCPO55_RIPPLECNT_MASK 0x0000FFFFL |
47492 | #define RTAVFS_REG111__RESERVED_MASK 0xFFFF0000L |
47493 | //RTAVFS_REG112 |
47494 | #define RTAVFS_REG112__RTAVFSCPO56_STARTCNT__SHIFT 0x0 |
47495 | #define RTAVFS_REG112__RTAVFSCPO56_STOPCNT__SHIFT 0x10 |
47496 | #define RTAVFS_REG112__RTAVFSCPO56_STARTCNT_MASK 0x0000FFFFL |
47497 | #define RTAVFS_REG112__RTAVFSCPO56_STOPCNT_MASK 0xFFFF0000L |
47498 | //RTAVFS_REG113 |
47499 | #define RTAVFS_REG113__RTAVFSCPO56_RIPPLECNT__SHIFT 0x0 |
47500 | #define RTAVFS_REG113__RESERVED__SHIFT 0x10 |
47501 | #define RTAVFS_REG113__RTAVFSCPO56_RIPPLECNT_MASK 0x0000FFFFL |
47502 | #define RTAVFS_REG113__RESERVED_MASK 0xFFFF0000L |
47503 | //RTAVFS_REG114 |
47504 | #define RTAVFS_REG114__RTAVFSCPO57_STARTCNT__SHIFT 0x0 |
47505 | #define RTAVFS_REG114__RTAVFSCPO57_STOPCNT__SHIFT 0x10 |
47506 | #define RTAVFS_REG114__RTAVFSCPO57_STARTCNT_MASK 0x0000FFFFL |
47507 | #define RTAVFS_REG114__RTAVFSCPO57_STOPCNT_MASK 0xFFFF0000L |
47508 | //RTAVFS_REG115 |
47509 | #define RTAVFS_REG115__RTAVFSCPO57_RIPPLECNT__SHIFT 0x0 |
47510 | #define RTAVFS_REG115__RESERVED__SHIFT 0x10 |
47511 | #define RTAVFS_REG115__RTAVFSCPO57_RIPPLECNT_MASK 0x0000FFFFL |
47512 | #define RTAVFS_REG115__RESERVED_MASK 0xFFFF0000L |
47513 | //RTAVFS_REG116 |
47514 | #define RTAVFS_REG116__RTAVFSCPO58_STARTCNT__SHIFT 0x0 |
47515 | #define RTAVFS_REG116__RTAVFSCPO58_STOPCNT__SHIFT 0x10 |
47516 | #define RTAVFS_REG116__RTAVFSCPO58_STARTCNT_MASK 0x0000FFFFL |
47517 | #define RTAVFS_REG116__RTAVFSCPO58_STOPCNT_MASK 0xFFFF0000L |
47518 | //RTAVFS_REG117 |
47519 | #define RTAVFS_REG117__RTAVFSCPO58_RIPPLECNT__SHIFT 0x0 |
47520 | #define RTAVFS_REG117__RESERVED__SHIFT 0x10 |
47521 | #define RTAVFS_REG117__RTAVFSCPO58_RIPPLECNT_MASK 0x0000FFFFL |
47522 | #define RTAVFS_REG117__RESERVED_MASK 0xFFFF0000L |
47523 | //RTAVFS_REG118 |
47524 | #define RTAVFS_REG118__RTAVFSCPO59_STARTCNT__SHIFT 0x0 |
47525 | #define RTAVFS_REG118__RTAVFSCPO59_STOPCNT__SHIFT 0x10 |
47526 | #define RTAVFS_REG118__RTAVFSCPO59_STARTCNT_MASK 0x0000FFFFL |
47527 | #define RTAVFS_REG118__RTAVFSCPO59_STOPCNT_MASK 0xFFFF0000L |
47528 | //RTAVFS_REG119 |
47529 | #define RTAVFS_REG119__RTAVFSCPO59_RIPPLECNT__SHIFT 0x0 |
47530 | #define RTAVFS_REG119__RESERVED__SHIFT 0x10 |
47531 | #define RTAVFS_REG119__RTAVFSCPO59_RIPPLECNT_MASK 0x0000FFFFL |
47532 | #define RTAVFS_REG119__RESERVED_MASK 0xFFFF0000L |
47533 | //RTAVFS_REG120 |
47534 | #define RTAVFS_REG120__RTAVFSCPO60_STARTCNT__SHIFT 0x0 |
47535 | #define RTAVFS_REG120__RTAVFSCPO60_STOPCNT__SHIFT 0x10 |
47536 | #define RTAVFS_REG120__RTAVFSCPO60_STARTCNT_MASK 0x0000FFFFL |
47537 | #define RTAVFS_REG120__RTAVFSCPO60_STOPCNT_MASK 0xFFFF0000L |
47538 | //RTAVFS_REG121 |
47539 | #define RTAVFS_REG121__RTAVFSCPO60_RIPPLECNT__SHIFT 0x0 |
47540 | #define RTAVFS_REG121__RESERVED__SHIFT 0x10 |
47541 | #define RTAVFS_REG121__RTAVFSCPO60_RIPPLECNT_MASK 0x0000FFFFL |
47542 | #define RTAVFS_REG121__RESERVED_MASK 0xFFFF0000L |
47543 | //RTAVFS_REG122 |
47544 | #define RTAVFS_REG122__RTAVFSCPO61_STARTCNT__SHIFT 0x0 |
47545 | #define RTAVFS_REG122__RTAVFSCPO61_STOPCNT__SHIFT 0x10 |
47546 | #define RTAVFS_REG122__RTAVFSCPO61_STARTCNT_MASK 0x0000FFFFL |
47547 | #define RTAVFS_REG122__RTAVFSCPO61_STOPCNT_MASK 0xFFFF0000L |
47548 | //RTAVFS_REG123 |
47549 | #define RTAVFS_REG123__RTAVFSCPO61_RIPPLECNT__SHIFT 0x0 |
47550 | #define RTAVFS_REG123__RESERVED__SHIFT 0x10 |
47551 | #define RTAVFS_REG123__RTAVFSCPO61_RIPPLECNT_MASK 0x0000FFFFL |
47552 | #define RTAVFS_REG123__RESERVED_MASK 0xFFFF0000L |
47553 | //RTAVFS_REG124 |
47554 | #define RTAVFS_REG124__RTAVFSCPO62_STARTCNT__SHIFT 0x0 |
47555 | #define RTAVFS_REG124__RTAVFSCPO62_STOPCNT__SHIFT 0x10 |
47556 | #define RTAVFS_REG124__RTAVFSCPO62_STARTCNT_MASK 0x0000FFFFL |
47557 | #define RTAVFS_REG124__RTAVFSCPO62_STOPCNT_MASK 0xFFFF0000L |
47558 | //RTAVFS_REG125 |
47559 | #define RTAVFS_REG125__RTAVFSCPO62_RIPPLECNT__SHIFT 0x0 |
47560 | #define RTAVFS_REG125__RESERVED__SHIFT 0x10 |
47561 | #define RTAVFS_REG125__RTAVFSCPO62_RIPPLECNT_MASK 0x0000FFFFL |
47562 | #define RTAVFS_REG125__RESERVED_MASK 0xFFFF0000L |
47563 | //RTAVFS_REG126 |
47564 | #define RTAVFS_REG126__RTAVFSCPO63_STARTCNT__SHIFT 0x0 |
47565 | #define RTAVFS_REG126__RTAVFSCPO63_STOPCNT__SHIFT 0x10 |
47566 | #define RTAVFS_REG126__RTAVFSCPO63_STARTCNT_MASK 0x0000FFFFL |
47567 | #define RTAVFS_REG126__RTAVFSCPO63_STOPCNT_MASK 0xFFFF0000L |
47568 | //RTAVFS_REG127 |
47569 | #define RTAVFS_REG127__RTAVFSCPO63_RIPPLECNT__SHIFT 0x0 |
47570 | #define RTAVFS_REG127__RESERVED__SHIFT 0x10 |
47571 | #define RTAVFS_REG127__RTAVFSCPO63_RIPPLECNT_MASK 0x0000FFFFL |
47572 | #define RTAVFS_REG127__RESERVED_MASK 0xFFFF0000L |
47573 | //RTAVFS_REG128 |
47574 | #define RTAVFS_REG128__RTAVFSCPOEN0__SHIFT 0x0 |
47575 | #define RTAVFS_REG128__RTAVFSCPOEN0_MASK 0xFFFFFFFFL |
47576 | //RTAVFS_REG129 |
47577 | #define RTAVFS_REG129__RTAVFSCPOEN1__SHIFT 0x0 |
47578 | #define RTAVFS_REG129__RTAVFSCPOEN1_MASK 0xFFFFFFFFL |
47579 | //RTAVFS_REG130 |
47580 | #define RTAVFS_REG130__RTAVFSVRBLEEDCNTRL__SHIFT 0x0 |
47581 | #define RTAVFS_REG130__RTAVFSVRENABLE__SHIFT 0x1 |
47582 | #define RTAVFS_REG130__RTAVFSVOLTCODEOVERRIDE__SHIFT 0x2 |
47583 | #define RTAVFS_REG130__RTAVFSVOLTCODEOVERRIDESEL__SHIFT 0xc |
47584 | #define RTAVFS_REG130__RTAVFSLOWPWREN__SHIFT 0xd |
47585 | #define RTAVFS_REG130__RESERVED__SHIFT 0xe |
47586 | #define RTAVFS_REG130__RTAVFSVRBLEEDCNTRL_MASK 0x00000001L |
47587 | #define RTAVFS_REG130__RTAVFSVRENABLE_MASK 0x00000002L |
47588 | #define RTAVFS_REG130__RTAVFSVOLTCODEOVERRIDE_MASK 0x00000FFCL |
47589 | #define RTAVFS_REG130__RTAVFSVOLTCODEOVERRIDESEL_MASK 0x00001000L |
47590 | #define RTAVFS_REG130__RTAVFSLOWPWREN_MASK 0x00002000L |
47591 | #define RTAVFS_REG130__RESERVED_MASK 0xFFFFC000L |
47592 | //RTAVFS_REG131 |
47593 | #define RTAVFS_REG131__RTAVFSTARGETFREQCNTOVERRIDE__SHIFT 0x0 |
47594 | #define RTAVFS_REG131__RTAVFSTARGETFREQCNTOVERRIDESEL__SHIFT 0x10 |
47595 | #define RTAVFS_REG131__RESERVED__SHIFT 0x11 |
47596 | #define RTAVFS_REG131__RTAVFSTARGETFREQCNTOVERRIDE_MASK 0x0000FFFFL |
47597 | #define RTAVFS_REG131__RTAVFSTARGETFREQCNTOVERRIDESEL_MASK 0x00010000L |
47598 | #define RTAVFS_REG131__RESERVED_MASK 0xFFFE0000L |
47599 | //RTAVFS_REG132 |
47600 | #define RTAVFS_REG132__RTAVFSCURRENTFREQCNTOVERRIDE__SHIFT 0x0 |
47601 | #define RTAVFS_REG132__RTAVFSCURRENTFREQCNTOVERRIDESEL__SHIFT 0x10 |
47602 | #define RTAVFS_REG132__RESERVED__SHIFT 0x11 |
47603 | #define RTAVFS_REG132__RTAVFSCURRENTFREQCNTOVERRIDE_MASK 0x0000FFFFL |
47604 | #define RTAVFS_REG132__RTAVFSCURRENTFREQCNTOVERRIDESEL_MASK 0x00010000L |
47605 | #define RTAVFS_REG132__RESERVED_MASK 0xFFFE0000L |
47606 | //RTAVFS_REG133 |
47607 | #define RTAVFS_REG133__RESERVED__SHIFT 0x16 |
47608 | #define RTAVFS_REG133__RESERVED_MASK 0xFFC00000L |
47609 | //RTAVFS_REG134 |
47610 | #define RTAVFS_REG134__RTAVFSKP__SHIFT 0x0 |
47611 | #define RTAVFS_REG134__RTAVFSKI__SHIFT 0x4 |
47612 | #define RTAVFS_REG134__RTAVFSPIENABLEANTIWINDUP__SHIFT 0x8 |
47613 | #define RTAVFS_REG134__RTAVFSPISHIFT__SHIFT 0x9 |
47614 | #define RTAVFS_REG134__RTAVFSPIERREN__SHIFT 0xd |
47615 | #define RTAVFS_REG134__RTAVFSPISHIFTOUT__SHIFT 0xe |
47616 | #define RTAVFS_REG134__RTAVFSUSELUTKPKI__SHIFT 0x12 |
47617 | #define RTAVFS_REG134__RESERVED__SHIFT 0x13 |
47618 | #define RTAVFS_REG134__RTAVFSKP_MASK 0x0000000FL |
47619 | #define RTAVFS_REG134__RTAVFSKI_MASK 0x000000F0L |
47620 | #define RTAVFS_REG134__RTAVFSPIENABLEANTIWINDUP_MASK 0x00000100L |
47621 | #define RTAVFS_REG134__RTAVFSPISHIFT_MASK 0x00001E00L |
47622 | #define RTAVFS_REG134__RTAVFSPIERREN_MASK 0x00002000L |
47623 | #define RTAVFS_REG134__RTAVFSPISHIFTOUT_MASK 0x0003C000L |
47624 | #define RTAVFS_REG134__RTAVFSUSELUTKPKI_MASK 0x00040000L |
47625 | #define RTAVFS_REG134__RESERVED_MASK 0xFFF80000L |
47626 | //RTAVFS_REG135 |
47627 | #define RTAVFS_REG135__RTAVFSVOLTCODEPIMIN__SHIFT 0x0 |
47628 | #define RTAVFS_REG135__RTAVFSVOLTCODEPIMAX__SHIFT 0xa |
47629 | #define RTAVFS_REG135__RTAVFSPIERRMASK__SHIFT 0x14 |
47630 | #define RTAVFS_REG135__RTAVFSFORCEDISABLEPI__SHIFT 0x1b |
47631 | #define RTAVFS_REG135__RESERVED__SHIFT 0x1c |
47632 | #define RTAVFS_REG135__RTAVFSVOLTCODEPIMIN_MASK 0x000003FFL |
47633 | #define RTAVFS_REG135__RTAVFSVOLTCODEPIMAX_MASK 0x000FFC00L |
47634 | #define RTAVFS_REG135__RTAVFSPIERRMASK_MASK 0x07F00000L |
47635 | #define RTAVFS_REG135__RTAVFSFORCEDISABLEPI_MASK 0x08000000L |
47636 | #define RTAVFS_REG135__RESERVED_MASK 0xF0000000L |
47637 | //RTAVFS_REG136 |
47638 | #define RTAVFS_REG136__RTAVFSPILOOPNITERATIONS__SHIFT 0x0 |
47639 | #define RTAVFS_REG136__RTAVFSPIERRTHRESHOLD__SHIFT 0x10 |
47640 | #define RTAVFS_REG136__RTAVFSPILOOPNITERATIONS_MASK 0x0000FFFFL |
47641 | #define RTAVFS_REG136__RTAVFSPIERRTHRESHOLD_MASK 0xFFFF0000L |
47642 | //RTAVFS_REG137 |
47643 | #define RTAVFS_REG137__RTAVFSVOLTCODEFROMPI__SHIFT 0x0 |
47644 | #define RTAVFS_REG137__RTAVFSVOLTCODEFROMBINARYSEARCH__SHIFT 0xa |
47645 | #define RTAVFS_REG137__RTAVFSVDDREGON__SHIFT 0x14 |
47646 | #define RTAVFS_REG137__RESERVED__SHIFT 0x15 |
47647 | #define RTAVFS_REG137__RTAVFSVOLTCODEFROMPI_MASK 0x000003FFL |
47648 | #define RTAVFS_REG137__RTAVFSVOLTCODEFROMBINARYSEARCH_MASK 0x000FFC00L |
47649 | #define RTAVFS_REG137__RTAVFSVDDREGON_MASK 0x00100000L |
47650 | #define RTAVFS_REG137__RESERVED_MASK 0xFFE00000L |
47651 | //RTAVFS_REG138 |
47652 | #define RTAVFS_REG138__RTAVFSAVFSENABLE__SHIFT 0x0 |
47653 | #define RTAVFS_REG138__RTAVFSCPOTURNONDELAY__SHIFT 0x1 |
47654 | #define RTAVFS_REG138__RTAVFSSELECTMINMAX__SHIFT 0x5 |
47655 | #define RTAVFS_REG138__RTAVFSIGNORERLCREQ__SHIFT 0x6 |
47656 | #define RTAVFS_REG138__RTAVFSRIPPLECOUNTEROUTSEL__SHIFT 0x7 |
47657 | #define RTAVFS_REG138__RTAVFSRUNLOOP__SHIFT 0xc |
47658 | #define RTAVFS_REG138__RESERVED__SHIFT 0xd |
47659 | #define RTAVFS_REG138__RTAVFSAVFSENABLE_MASK 0x00000001L |
47660 | #define RTAVFS_REG138__RTAVFSCPOTURNONDELAY_MASK 0x0000001EL |
47661 | #define RTAVFS_REG138__RTAVFSSELECTMINMAX_MASK 0x00000020L |
47662 | #define RTAVFS_REG138__RTAVFSIGNORERLCREQ_MASK 0x00000040L |
47663 | #define RTAVFS_REG138__RTAVFSRIPPLECOUNTEROUTSEL_MASK 0x00000F80L |
47664 | #define RTAVFS_REG138__RTAVFSRUNLOOP_MASK 0x00001000L |
47665 | #define RTAVFS_REG138__RESERVED_MASK 0xFFFFE000L |
47666 | //RTAVFS_REG139 |
47667 | #define RTAVFS_REG139__RTAVFSAVFSSCALEDCPOCOUNT__SHIFT 0x0 |
47668 | #define RTAVFS_REG139__RTAVFSAVFSFINALMINCPOCOUNT__SHIFT 0x10 |
47669 | #define RTAVFS_REG139__RTAVFSAVFSSCALEDCPOCOUNT_MASK 0x0000FFFFL |
47670 | #define RTAVFS_REG139__RTAVFSAVFSFINALMINCPOCOUNT_MASK 0xFFFF0000L |
47671 | //RTAVFS_REG140 |
47672 | #define RTAVFS_REG140__RTAVFSPSMRSTAVGVDD__SHIFT 0x0 |
47673 | #define RTAVFS_REG140__RTAVFSPSMMEASMAXVDD__SHIFT 0x1 |
47674 | #define RTAVFS_REG140__RTAVFSPSMCLKDIVVDD__SHIFT 0x2 |
47675 | #define RTAVFS_REG140__RTAVFSPSMAVGDIVVDD__SHIFT 0x4 |
47676 | #define RTAVFS_REG140__RTAVFSPSMOSCENVDD__SHIFT 0xa |
47677 | #define RTAVFS_REG140__RTAVFSPSMAVGENVDD__SHIFT 0xb |
47678 | #define RTAVFS_REG140__RTAVFSPSMRSTMINMAXVDD__SHIFT 0xc |
47679 | #define RTAVFS_REG140__RESERVED__SHIFT 0xd |
47680 | #define RTAVFS_REG140__RTAVFSPSMRSTAVGVDD_MASK 0x00000001L |
47681 | #define RTAVFS_REG140__RTAVFSPSMMEASMAXVDD_MASK 0x00000002L |
47682 | #define RTAVFS_REG140__RTAVFSPSMCLKDIVVDD_MASK 0x0000000CL |
47683 | #define RTAVFS_REG140__RTAVFSPSMAVGDIVVDD_MASK 0x000003F0L |
47684 | #define RTAVFS_REG140__RTAVFSPSMOSCENVDD_MASK 0x00000400L |
47685 | #define RTAVFS_REG140__RTAVFSPSMAVGENVDD_MASK 0x00000800L |
47686 | #define RTAVFS_REG140__RTAVFSPSMRSTMINMAXVDD_MASK 0x00001000L |
47687 | #define RTAVFS_REG140__RESERVED_MASK 0xFFFFE000L |
47688 | //RTAVFS_REG141 |
47689 | #define RTAVFS_REG141__RTAVFSMINMAXPSMVDD__SHIFT 0x0 |
47690 | #define RTAVFS_REG141__RTAVFSAVGPSMVDD__SHIFT 0xe |
47691 | #define RTAVFS_REG141__RESERVED__SHIFT 0x1c |
47692 | #define RTAVFS_REG141__RTAVFSMINMAXPSMVDD_MASK 0x00003FFFL |
47693 | #define RTAVFS_REG141__RTAVFSAVGPSMVDD_MASK 0x0FFFC000L |
47694 | #define RTAVFS_REG141__RESERVED_MASK 0xF0000000L |
47695 | //RTAVFS_REG142 |
47696 | #define RTAVFS_REG142__RTAVFSPSMRSTAVGVREG__SHIFT 0x0 |
47697 | #define RTAVFS_REG142__RTAVFSPSMMEASMAXVREG__SHIFT 0x1 |
47698 | #define RTAVFS_REG142__RTAVFSPSMCLKDIVVREG__SHIFT 0x2 |
47699 | #define RTAVFS_REG142__RTAVFSPSMAVGDIVVREG__SHIFT 0x4 |
47700 | #define RTAVFS_REG142__RTAVFSPSMOSCENVREG__SHIFT 0xa |
47701 | #define RTAVFS_REG142__RTAVFSPSMAVGENVREG__SHIFT 0xb |
47702 | #define RTAVFS_REG142__RTAVFSPSMRSTMINMAXVREG__SHIFT 0xc |
47703 | #define RTAVFS_REG142__RESERVED__SHIFT 0xd |
47704 | #define RTAVFS_REG142__RTAVFSPSMRSTAVGVREG_MASK 0x00000001L |
47705 | #define RTAVFS_REG142__RTAVFSPSMMEASMAXVREG_MASK 0x00000002L |
47706 | #define RTAVFS_REG142__RTAVFSPSMCLKDIVVREG_MASK 0x0000000CL |
47707 | #define RTAVFS_REG142__RTAVFSPSMAVGDIVVREG_MASK 0x000003F0L |
47708 | #define RTAVFS_REG142__RTAVFSPSMOSCENVREG_MASK 0x00000400L |
47709 | #define RTAVFS_REG142__RTAVFSPSMAVGENVREG_MASK 0x00000800L |
47710 | #define RTAVFS_REG142__RTAVFSPSMRSTMINMAXVREG_MASK 0x00001000L |
47711 | #define RTAVFS_REG142__RESERVED_MASK 0xFFFFE000L |
47712 | //RTAVFS_REG143 |
47713 | #define RTAVFS_REG143__RTAVFSMINMAXPSMVREG__SHIFT 0x0 |
47714 | #define RTAVFS_REG143__RTAVFSAVGPSMVREG__SHIFT 0xe |
47715 | #define RTAVFS_REG143__RESERVED__SHIFT 0x1c |
47716 | #define RTAVFS_REG143__RTAVFSMINMAXPSMVREG_MASK 0x00003FFFL |
47717 | #define RTAVFS_REG143__RTAVFSAVGPSMVREG_MASK 0x0FFFC000L |
47718 | #define RTAVFS_REG143__RESERVED_MASK 0xF0000000L |
47719 | //RTAVFS_REG144 |
47720 | #define RTAVFS_REG144__RTAVFSTROSAMPLESIZE__SHIFT 0x0 |
47721 | #define RTAVFS_REG144__RTAVFSTROSAMPLEDLY__SHIFT 0xc |
47722 | #define RTAVFS_REG144__RTAVFSTROCONTMODEEN__SHIFT 0xe |
47723 | #define RTAVFS_REG144__RTAVFSTROPWRSAVEEN__SHIFT 0xf |
47724 | #define RTAVFS_REG144__RTAVFSTROTMPAVEEN__SHIFT 0x10 |
47725 | #define RTAVFS_REG144__RTAVFSTROTMPAVEDIV__SHIFT 0x11 |
47726 | #define RTAVFS_REG144__RTAVFSTROCALIBDIS__SHIFT 0x17 |
47727 | #define RTAVFS_REG144__RTAVFSTROOUTVALSEL__SHIFT 0x18 |
47728 | #define RTAVFS_REG144__RTAVFSTROCMGAIN__SHIFT 0x1b |
47729 | #define RTAVFS_REG144__RTAVFSTROCLKDIVSEL__SHIFT 0x1d |
47730 | #define RTAVFS_REG144__RTAVFSTROTRODIS__SHIFT 0x1f |
47731 | #define RTAVFS_REG144__RTAVFSTROSAMPLESIZE_MASK 0x00000FFFL |
47732 | #define RTAVFS_REG144__RTAVFSTROSAMPLEDLY_MASK 0x00003000L |
47733 | #define RTAVFS_REG144__RTAVFSTROCONTMODEEN_MASK 0x00004000L |
47734 | #define RTAVFS_REG144__RTAVFSTROPWRSAVEEN_MASK 0x00008000L |
47735 | #define RTAVFS_REG144__RTAVFSTROTMPAVEEN_MASK 0x00010000L |
47736 | #define RTAVFS_REG144__RTAVFSTROTMPAVEDIV_MASK 0x007E0000L |
47737 | #define RTAVFS_REG144__RTAVFSTROCALIBDIS_MASK 0x00800000L |
47738 | #define RTAVFS_REG144__RTAVFSTROOUTVALSEL_MASK 0x07000000L |
47739 | #define RTAVFS_REG144__RTAVFSTROCMGAIN_MASK 0x18000000L |
47740 | #define RTAVFS_REG144__RTAVFSTROCLKDIVSEL_MASK 0x60000000L |
47741 | #define RTAVFS_REG144__RTAVFSTROTRODIS_MASK 0x80000000L |
47742 | //RTAVFS_REG145 |
47743 | #define RTAVFS_REG145__RTAVFSTROTEMPDATA__SHIFT 0x0 |
47744 | #define RTAVFS_REG145__RTAVFSTROSSTATE__SHIFT 0x10 |
47745 | #define RTAVFS_REG145__RTAVFSTROCALIBDONE__SHIFT 0x14 |
47746 | #define RTAVFS_REG145__RTAVFSTRORESERVED__SHIFT 0x15 |
47747 | #define RTAVFS_REG145__RTAVFSTROTEMPDATA_MASK 0x0000FFFFL |
47748 | #define RTAVFS_REG145__RTAVFSTROSSTATE_MASK 0x000F0000L |
47749 | #define RTAVFS_REG145__RTAVFSTROCALIBDONE_MASK 0x00100000L |
47750 | #define RTAVFS_REG145__RTAVFSTRORESERVED_MASK 0xFFE00000L |
47751 | //RTAVFS_REG146 |
47752 | #define RTAVFS_REG146__RTAVFSTROTMP_M__SHIFT 0x0 |
47753 | #define RTAVFS_REG146__RTAVFSTROTMP_C__SHIFT 0x10 |
47754 | #define RTAVFS_REG146__RTAVFSTROTMP_M_MASK 0x0000FFFFL |
47755 | #define RTAVFS_REG146__RTAVFSTROTMP_C_MASK 0xFFFF0000L |
47756 | //RTAVFS_REG147 |
47757 | #define RTAVFS_REG147__RTAVFSTROTMP_OFFSET__SHIFT 0x0 |
47758 | #define RTAVFS_REG147__RTAVFSTROTMPSAMPSIZE__SHIFT 0x5 |
47759 | #define RTAVFS_REG147__RTAVFSTROTMPREADSKIPSCALE__SHIFT 0x11 |
47760 | #define RTAVFS_REG147__RTAVFSTROTMPSKIPSCALEFIX__SHIFT 0x12 |
47761 | #define RTAVFS_REG147__RESERVED__SHIFT 0x13 |
47762 | #define RTAVFS_REG147__RTAVFSTROTMP_OFFSET_MASK 0x0000001FL |
47763 | #define RTAVFS_REG147__RTAVFSTROTMPSAMPSIZE_MASK 0x0001FFE0L |
47764 | #define RTAVFS_REG147__RTAVFSTROTMPREADSKIPSCALE_MASK 0x00020000L |
47765 | #define RTAVFS_REG147__RTAVFSTROTMPSKIPSCALEFIX_MASK 0x00040000L |
47766 | #define RTAVFS_REG147__RESERVED_MASK 0xFFF80000L |
47767 | //RTAVFS_REG148 |
47768 | #define RTAVFS_REG148__RTAVFSTROTMPOUT__SHIFT 0x0 |
47769 | #define RTAVFS_REG148__RTAVFSTROTMPOUTVAL__SHIFT 0xc |
47770 | #define RTAVFS_REG148__RTAVFSTROCURTMP__SHIFT 0xd |
47771 | #define RTAVFS_REG148__RESERVED__SHIFT 0x18 |
47772 | #define RTAVFS_REG148__RTAVFSTROTMPOUT_MASK 0x00000FFFL |
47773 | #define RTAVFS_REG148__RTAVFSTROTMPOUTVAL_MASK 0x00001000L |
47774 | #define RTAVFS_REG148__RTAVFSTROCURTMP_MASK 0x00FFE000L |
47775 | #define RTAVFS_REG148__RESERVED_MASK 0xFF000000L |
47776 | //RTAVFS_REG149 |
47777 | #define RTAVFS_REG149__RTAVFSFSMSTARTUPCNT__SHIFT 0x0 |
47778 | #define RTAVFS_REG149__RESERVED__SHIFT 0x10 |
47779 | #define RTAVFS_REG149__RTAVFSFSMSTARTUPCNT_MASK 0x0000FFFFL |
47780 | #define RTAVFS_REG149__RESERVED_MASK 0xFFFF0000L |
47781 | //RTAVFS_REG150 |
47782 | #define RTAVFS_REG150__RTAVFSFSMIDLECNT__SHIFT 0x0 |
47783 | #define RTAVFS_REG150__RESERVED__SHIFT 0x10 |
47784 | #define RTAVFS_REG150__RTAVFSFSMIDLECNT_MASK 0x0000FFFFL |
47785 | #define RTAVFS_REG150__RESERVED_MASK 0xFFFF0000L |
47786 | //RTAVFS_REG151 |
47787 | #define RTAVFS_REG151__RTAVFSFSMRESETCPORIPPLECOUNTERSCNT__SHIFT 0x0 |
47788 | #define RTAVFS_REG151__RESERVED__SHIFT 0x10 |
47789 | #define RTAVFS_REG151__RTAVFSFSMRESETCPORIPPLECOUNTERSCNT_MASK 0x0000FFFFL |
47790 | #define RTAVFS_REG151__RESERVED_MASK 0xFFFF0000L |
47791 | //RTAVFS_REG152 |
47792 | #define RTAVFS_REG152__RTAVFSFSMSTARTCPOSCNT__SHIFT 0x0 |
47793 | #define RTAVFS_REG152__RESERVED__SHIFT 0x10 |
47794 | #define RTAVFS_REG152__RTAVFSFSMSTARTCPOSCNT_MASK 0x0000FFFFL |
47795 | #define RTAVFS_REG152__RESERVED_MASK 0xFFFF0000L |
47796 | //RTAVFS_REG153 |
47797 | #define RTAVFS_REG153__RTAVFSFSMSTARTRIPPLECOUNTERSCNT__SHIFT 0x0 |
47798 | #define RTAVFS_REG153__RESERVED__SHIFT 0x10 |
47799 | #define RTAVFS_REG153__RTAVFSFSMSTARTRIPPLECOUNTERSCNT_MASK 0x0000FFFFL |
47800 | #define RTAVFS_REG153__RESERVED_MASK 0xFFFF0000L |
47801 | //RTAVFS_REG154 |
47802 | #define RTAVFS_REG154__RTAVFSFSMRIPPLECOUNTERSDONECNT__SHIFT 0x0 |
47803 | #define RTAVFS_REG154__RESERVED__SHIFT 0x10 |
47804 | #define RTAVFS_REG154__RTAVFSFSMRIPPLECOUNTERSDONECNT_MASK 0x0000FFFFL |
47805 | #define RTAVFS_REG154__RESERVED_MASK 0xFFFF0000L |
47806 | //RTAVFS_REG155 |
47807 | #define RTAVFS_REG155__RTAVFSFSMCPOFINALRESULTREADYCNT__SHIFT 0x0 |
47808 | #define RTAVFS_REG155__RESERVED__SHIFT 0x10 |
47809 | #define RTAVFS_REG155__RTAVFSFSMCPOFINALRESULTREADYCNT_MASK 0x0000FFFFL |
47810 | #define RTAVFS_REG155__RESERVED_MASK 0xFFFF0000L |
47811 | //RTAVFS_REG156 |
47812 | #define RTAVFS_REG156__RTAVFSFSMVOLTCODEREADYCNT__SHIFT 0x0 |
47813 | #define RTAVFS_REG156__RESERVED__SHIFT 0x10 |
47814 | #define RTAVFS_REG156__RTAVFSFSMVOLTCODEREADYCNT_MASK 0x0000FFFFL |
47815 | #define RTAVFS_REG156__RESERVED_MASK 0xFFFF0000L |
47816 | //RTAVFS_REG157 |
47817 | #define RTAVFS_REG157__RTAVFSFSMTARGETVOLTAGEREADYCNT__SHIFT 0x0 |
47818 | #define RTAVFS_REG157__RESERVED__SHIFT 0x10 |
47819 | #define RTAVFS_REG157__RTAVFSFSMTARGETVOLTAGEREADYCNT_MASK 0x0000FFFFL |
47820 | #define RTAVFS_REG157__RESERVED_MASK 0xFFFF0000L |
47821 | //RTAVFS_REG158 |
47822 | #define RTAVFS_REG158__RTAVFSFSMSTOPCPOSCNT__SHIFT 0x0 |
47823 | #define RTAVFS_REG158__RESERVED__SHIFT 0x10 |
47824 | #define RTAVFS_REG158__RTAVFSFSMSTOPCPOSCNT_MASK 0x0000FFFFL |
47825 | #define RTAVFS_REG158__RESERVED_MASK 0xFFFF0000L |
47826 | //RTAVFS_REG159 |
47827 | #define RTAVFS_REG159__RTAVFSFSMWAITFORACKCNT__SHIFT 0x0 |
47828 | #define RTAVFS_REG159__RESERVED__SHIFT 0x10 |
47829 | #define RTAVFS_REG159__RTAVFSFSMWAITFORACKCNT_MASK 0x0000FFFFL |
47830 | #define RTAVFS_REG159__RESERVED_MASK 0xFFFF0000L |
47831 | //RTAVFS_REG160 |
47832 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV0__SHIFT 0x0 |
47833 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV1__SHIFT 0x2 |
47834 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV2__SHIFT 0x4 |
47835 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV3__SHIFT 0x6 |
47836 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV4__SHIFT 0x8 |
47837 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV5__SHIFT 0xa |
47838 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV6__SHIFT 0xc |
47839 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV7__SHIFT 0xe |
47840 | #define RTAVFS_REG160__RTAVFSCPOAVGDIVFINAL__SHIFT 0x10 |
47841 | #define RTAVFS_REG160__RESERVED__SHIFT 0x12 |
47842 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV0_MASK 0x00000003L |
47843 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV1_MASK 0x0000000CL |
47844 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV2_MASK 0x00000030L |
47845 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV3_MASK 0x000000C0L |
47846 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV4_MASK 0x00000300L |
47847 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV5_MASK 0x00000C00L |
47848 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV6_MASK 0x00003000L |
47849 | #define RTAVFS_REG160__RTAVFSCPOAVGDIV7_MASK 0x0000C000L |
47850 | #define RTAVFS_REG160__RTAVFSCPOAVGDIVFINAL_MASK 0x00030000L |
47851 | #define RTAVFS_REG160__RESERVED_MASK 0xFFFC0000L |
47852 | //RTAVFS_REG161 |
47853 | #define RTAVFS_REG161__RTAVFSKP0__SHIFT 0x0 |
47854 | #define RTAVFS_REG161__RTAVFSKP1__SHIFT 0x4 |
47855 | #define RTAVFS_REG161__RTAVFSKP2__SHIFT 0x8 |
47856 | #define RTAVFS_REG161__RTAVFSKP3__SHIFT 0xc |
47857 | #define RTAVFS_REG161__RTAVFSKI0__SHIFT 0x10 |
47858 | #define RTAVFS_REG161__RTAVFSKI1__SHIFT 0x14 |
47859 | #define RTAVFS_REG161__RTAVFSKI2__SHIFT 0x18 |
47860 | #define RTAVFS_REG161__RTAVFSKI3__SHIFT 0x1c |
47861 | #define RTAVFS_REG161__RTAVFSKP0_MASK 0x0000000FL |
47862 | #define RTAVFS_REG161__RTAVFSKP1_MASK 0x000000F0L |
47863 | #define RTAVFS_REG161__RTAVFSKP2_MASK 0x00000F00L |
47864 | #define RTAVFS_REG161__RTAVFSKP3_MASK 0x0000F000L |
47865 | #define RTAVFS_REG161__RTAVFSKI0_MASK 0x000F0000L |
47866 | #define RTAVFS_REG161__RTAVFSKI1_MASK 0x00F00000L |
47867 | #define RTAVFS_REG161__RTAVFSKI2_MASK 0x0F000000L |
47868 | #define RTAVFS_REG161__RTAVFSKI3_MASK 0xF0000000L |
47869 | //RTAVFS_REG162 |
47870 | #define RTAVFS_REG162__RTAVFSV1__SHIFT 0x0 |
47871 | #define RTAVFS_REG162__RTAVFSV2__SHIFT 0xa |
47872 | #define RTAVFS_REG162__RTAVFSV3__SHIFT 0x14 |
47873 | #define RTAVFS_REG162__RTAVFSUSEBINARYSEARCH__SHIFT 0x1e |
47874 | #define RTAVFS_REG162__RTAVFSVOLTCODEHWCAL__SHIFT 0x1f |
47875 | #define RTAVFS_REG162__RTAVFSV1_MASK 0x000003FFL |
47876 | #define RTAVFS_REG162__RTAVFSV2_MASK 0x000FFC00L |
47877 | #define RTAVFS_REG162__RTAVFSV3_MASK 0x3FF00000L |
47878 | #define RTAVFS_REG162__RTAVFSUSEBINARYSEARCH_MASK 0x40000000L |
47879 | #define RTAVFS_REG162__RTAVFSVOLTCODEHWCAL_MASK 0x80000000L |
47880 | //RTAVFS_REG163 |
47881 | #define RTAVFS_REG163__RTAVFSFSMSTATE__SHIFT 0x0 |
47882 | #define RTAVFS_REG163__RESERVED__SHIFT 0x10 |
47883 | #define RTAVFS_REG163__RTAVFSFSMSTATE_MASK 0x0000FFFFL |
47884 | #define RTAVFS_REG163__RESERVED_MASK 0xFFFF0000L |
47885 | //RTAVFS_REG164 |
47886 | #define RTAVFS_REG164__RTAVFSGB_V1__SHIFT 0x0 |
47887 | #define RTAVFS_REG164__RTAVFSGB_V1V2__SHIFT 0x8 |
47888 | #define RTAVFS_REG164__RTAVFSGB_V2V3__SHIFT 0x10 |
47889 | #define RTAVFS_REG164__RTAVFSGB_V3__SHIFT 0x18 |
47890 | #define RTAVFS_REG164__RTAVFSGB_V1_MASK 0x000000FFL |
47891 | #define RTAVFS_REG164__RTAVFSGB_V1V2_MASK 0x0000FF00L |
47892 | #define RTAVFS_REG164__RTAVFSGB_V2V3_MASK 0x00FF0000L |
47893 | #define RTAVFS_REG164__RTAVFSGB_V3_MASK 0xFF000000L |
47894 | //RTAVFS_REG165 |
47895 | #define RTAVFS_REG165__RTAVFSRIPPLECNTREAD__SHIFT 0x0 |
47896 | #define RTAVFS_REG165__RTAVFSRIPPLECNTREAD_MASK 0xFFFFFFFFL |
47897 | |
47898 | |
47899 | // addressBlock: spiind |
47900 | //SA_WGP_BLK_ID |
47901 | #define SA_WGP_BLK_ID__BLK_ID__SHIFT 0x0 |
47902 | #define SA_WGP_BLK_ID__WGP_SIDE__SHIFT 0x4 |
47903 | #define SA_WGP_BLK_ID__SA_ID__SHIFT 0x5 |
47904 | #define SA_WGP_BLK_ID__BLK_ID_MASK 0x0000000FL |
47905 | #define SA_WGP_BLK_ID__WGP_SIDE_MASK 0x00000010L |
47906 | #define SA_WGP_BLK_ID__SA_ID_MASK 0x00000020L |
47907 | |
47908 | |
47909 | // addressBlock: sqind |
47910 | //SQ_DEBUG |
47911 | #define SQ_DEBUG__SINGLE_MEMOP_MASK 0x00000001L |
47912 | #define SQ_DEBUG__SINGLE_MEMOP__SHIFT 0x00000000 |
47913 | |
47914 | //SQ_DEBUG_STS_GLOBAL |
47915 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0x000000ffL |
47916 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x00000000 |
47917 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0x0000ff00L |
47918 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x00000008 |
47919 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE_MASK 0xff0000L |
47920 | #define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_COMPUTE__SHIFT 0x00000010 |
47921 | #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L |
47922 | #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x00000000 |
47923 | #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x00000002L |
47924 | #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x00000001 |
47925 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0x0000fff0L |
47926 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x00000004 |
47927 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0fff0000L |
47928 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT 0x00000010 |
47929 | |
47930 | //SQ_DEBUG_STS_LOCAL |
47931 | #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L |
47932 | #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x00000000 |
47933 | #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003f0L |
47934 | #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x00000004 |
47935 | #define SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK 0x00001000L |
47936 | #define SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT 0x0000000C |
47937 | #define SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK 0x00002000L |
47938 | #define SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT 0x0000000D |
47939 | #define SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK 0x00004000L |
47940 | #define SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT 0x0000000E |
47941 | #define SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK 0x00008000L |
47942 | #define SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT 0x0000000F |
47943 | #define SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK 0x00010000L |
47944 | #define SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT 0x00000010 |
47945 | #define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK 0x00020000L |
47946 | #define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT 0x00000011 |
47947 | #define SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK 0x00040000L |
47948 | #define SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT 0x00000018 |
47949 | //SQ_WAVE_ACTIVE |
47950 | #define SQ_WAVE_ACTIVE__WAVE_SLOT__SHIFT 0x0 |
47951 | #define SQ_WAVE_ACTIVE__WAVE_SLOT_MASK 0x000FFFFFL |
47952 | //SQ_WAVE_VALID_AND_IDLE |
47953 | #define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT 0x0 |
47954 | #define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK 0x000FFFFFL |
47955 | //SQ_WAVE_MODE |
47956 | #define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 |
47957 | #define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 |
47958 | #define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 |
47959 | #define SQ_WAVE_MODE__IEEE__SHIFT 0x9 |
47960 | #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa |
47961 | #define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc |
47962 | #define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17 |
47963 | #define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1b |
47964 | #define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL |
47965 | #define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L |
47966 | #define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L |
47967 | #define SQ_WAVE_MODE__IEEE_MASK 0x00000200L |
47968 | #define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L |
47969 | #define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L |
47970 | #define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L |
47971 | #define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x08000000L |
47972 | //SQ_WAVE_STATUS |
47973 | #define SQ_WAVE_STATUS__SCC__SHIFT 0x0 |
47974 | #define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 |
47975 | #define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 |
47976 | #define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 |
47977 | #define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 |
47978 | #define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 |
47979 | #define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 |
47980 | #define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 |
47981 | #define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa |
47982 | #define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb |
47983 | #define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc |
47984 | #define SQ_WAVE_STATUS__HALT__SHIFT 0xd |
47985 | #define SQ_WAVE_STATUS__TRAP__SHIFT 0xe |
47986 | #define SQ_WAVE_STATUS__TTRACE_SIMD_EN__SHIFT 0xf |
47987 | #define SQ_WAVE_STATUS__VALID__SHIFT 0x10 |
47988 | #define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 |
47989 | #define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 |
47990 | #define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 |
47991 | #define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17 |
47992 | #define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b |
47993 | #define SQ_WAVE_STATUS__SCC_MASK 0x00000001L |
47994 | #define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L |
47995 | #define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L |
47996 | #define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L |
47997 | #define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L |
47998 | #define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L |
47999 | #define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L |
48000 | #define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L |
48001 | #define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L |
48002 | #define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L |
48003 | #define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L |
48004 | #define SQ_WAVE_STATUS__HALT_MASK 0x00002000L |
48005 | #define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L |
48006 | #define SQ_WAVE_STATUS__TTRACE_SIMD_EN_MASK 0x00008000L |
48007 | #define SQ_WAVE_STATUS__VALID_MASK 0x00010000L |
48008 | #define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L |
48009 | #define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L |
48010 | #define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L |
48011 | #define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L |
48012 | #define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L |
48013 | //SQ_WAVE_TRAPSTS |
48014 | #define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 |
48015 | #define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa |
48016 | #define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb |
48017 | #define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc |
48018 | #define SQ_WAVE_TRAPSTS__BUFFER_OOB__SHIFT 0xf |
48019 | #define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 |
48020 | #define SQ_WAVE_TRAPSTS__EXCP_GROUP_MASK__SHIFT 0x14 |
48021 | #define SQ_WAVE_TRAPSTS__EXCP_WAVE64HI__SHIFT 0x18 |
48022 | #define SQ_WAVE_TRAPSTS__UTC_ERROR__SHIFT 0x1c |
48023 | #define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d |
48024 | #define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL |
48025 | #define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L |
48026 | #define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L |
48027 | #define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L |
48028 | #define SQ_WAVE_TRAPSTS__BUFFER_OOB_MASK 0x00008000L |
48029 | #define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x000F0000L |
48030 | #define SQ_WAVE_TRAPSTS__EXCP_GROUP_MASK_MASK 0x00F00000L |
48031 | #define SQ_WAVE_TRAPSTS__EXCP_WAVE64HI_MASK 0x01000000L |
48032 | #define SQ_WAVE_TRAPSTS__UTC_ERROR_MASK 0x10000000L |
48033 | #define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L |
48034 | //SQ_WAVE_HW_ID_LEGACY |
48035 | #define SQ_WAVE_HW_ID_LEGACY__WAVE_ID__SHIFT 0x0 |
48036 | #define SQ_WAVE_HW_ID_LEGACY__SIMD_ID__SHIFT 0x4 |
48037 | #define SQ_WAVE_HW_ID_LEGACY__PIPE_ID__SHIFT 0x6 |
48038 | #define SQ_WAVE_HW_ID_LEGACY__CU_ID__SHIFT 0x8 |
48039 | #define SQ_WAVE_HW_ID_LEGACY__SH_ID__SHIFT 0xc |
48040 | #define SQ_WAVE_HW_ID_LEGACY__SE_ID__SHIFT 0xd |
48041 | #define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MSB__SHIFT 0xf |
48042 | #define SQ_WAVE_HW_ID_LEGACY__TG_ID__SHIFT 0x10 |
48043 | #define SQ_WAVE_HW_ID_LEGACY__VM_ID__SHIFT 0x14 |
48044 | #define SQ_WAVE_HW_ID_LEGACY__QUEUE_ID__SHIFT 0x18 |
48045 | #define SQ_WAVE_HW_ID_LEGACY__STATE_ID__SHIFT 0x1b |
48046 | #define SQ_WAVE_HW_ID_LEGACY__ME_ID__SHIFT 0x1e |
48047 | #define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MASK 0x0000000FL |
48048 | #define SQ_WAVE_HW_ID_LEGACY__SIMD_ID_MASK 0x00000030L |
48049 | #define SQ_WAVE_HW_ID_LEGACY__PIPE_ID_MASK 0x000000C0L |
48050 | #define SQ_WAVE_HW_ID_LEGACY__CU_ID_MASK 0x00000F00L |
48051 | #define SQ_WAVE_HW_ID_LEGACY__SH_ID_MASK 0x00001000L |
48052 | #define SQ_WAVE_HW_ID_LEGACY__SE_ID_MASK 0x00006000L |
48053 | #define SQ_WAVE_HW_ID_LEGACY__WAVE_ID_MSB_MASK 0x00008000L |
48054 | #define SQ_WAVE_HW_ID_LEGACY__TG_ID_MASK 0x000F0000L |
48055 | #define SQ_WAVE_HW_ID_LEGACY__VM_ID_MASK 0x00F00000L |
48056 | #define SQ_WAVE_HW_ID_LEGACY__QUEUE_ID_MASK 0x07000000L |
48057 | #define SQ_WAVE_HW_ID_LEGACY__STATE_ID_MASK 0x38000000L |
48058 | #define SQ_WAVE_HW_ID_LEGACY__ME_ID_MASK 0xC0000000L |
48059 | //SQ_WAVE_GPR_ALLOC |
48060 | #define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 |
48061 | #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8 |
48062 | #define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10 |
48063 | #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 |
48064 | #define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x000000FFL |
48065 | #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x0000FF00L |
48066 | #define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x00FF0000L |
48067 | #define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L |
48068 | //SQ_WAVE_LDS_ALLOC |
48069 | #define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 |
48070 | #define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc |
48071 | #define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE__SHIFT 0x18 |
48072 | #define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000001FFL |
48073 | #define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L |
48074 | #define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE_MASK 0x0F000000L |
48075 | //SQ_WAVE_IB_STS |
48076 | #define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 |
48077 | #define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 |
48078 | #define SQ_WAVE_IB_STS__LGKM_CNT_BIT4__SHIFT 0x7 |
48079 | #define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 |
48080 | #define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc |
48081 | #define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16 |
48082 | #define SQ_WAVE_IB_STS__LGKM_CNT_BIT5__SHIFT 0x18 |
48083 | #define SQ_WAVE_IB_STS__VS_CNT__SHIFT 0x1a |
48084 | #define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL |
48085 | #define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L |
48086 | #define SQ_WAVE_IB_STS__LGKM_CNT_BIT4_MASK 0x00000080L |
48087 | #define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L |
48088 | #define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L |
48089 | #define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L |
48090 | #define SQ_WAVE_IB_STS__LGKM_CNT_BIT5_MASK 0x01000000L |
48091 | #define SQ_WAVE_IB_STS__VS_CNT_MASK 0xFC000000L |
48092 | //SQ_WAVE_PC_LO |
48093 | #define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 |
48094 | #define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL |
48095 | //SQ_WAVE_PC_HI |
48096 | #define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 |
48097 | #define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL |
48098 | //SQ_WAVE_INST_DW0 |
48099 | #define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 |
48100 | #define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL |
48101 | //SQ_WAVE_IB_DBG1 |
48102 | #define SQ_WAVE_IB_DBG1__WAVE_IDLE__SHIFT 0x18 |
48103 | #define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19 |
48104 | #define SQ_WAVE_IB_DBG1__WAVE_IDLE_MASK 0x01000000L |
48105 | #define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L |
48106 | //SQ_WAVE_FLUSH_IB |
48107 | #define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0 |
48108 | #define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL |
48109 | //SQ_WAVE_FLAT_SCRATCH_LO |
48110 | #define SQ_WAVE_FLAT_SCRATCH_LO__DATA__SHIFT 0x0 |
48111 | #define SQ_WAVE_FLAT_SCRATCH_LO__DATA_MASK 0xFFFFFFFFL |
48112 | //SQ_WAVE_FLAT_SCRATCH_HI |
48113 | #define SQ_WAVE_FLAT_SCRATCH_HI__DATA__SHIFT 0x0 |
48114 | #define SQ_WAVE_FLAT_SCRATCH_HI__DATA_MASK 0xFFFFFFFFL |
48115 | //SQ_WAVE_HW_ID1 |
48116 | #define SQ_WAVE_HW_ID1__WAVE_ID__SHIFT 0x0 |
48117 | #define SQ_WAVE_HW_ID1__SIMD_ID__SHIFT 0x8 |
48118 | #define SQ_WAVE_HW_ID1__WGP_ID__SHIFT 0xa |
48119 | #define SQ_WAVE_HW_ID1__SA_ID__SHIFT 0x10 |
48120 | #define SQ_WAVE_HW_ID1__SE_ID__SHIFT 0x12 |
48121 | #define SQ_WAVE_HW_ID1__WAVE_ID_MASK 0x0000001FL |
48122 | #define SQ_WAVE_HW_ID1__SIMD_ID_MASK 0x00000300L |
48123 | #define SQ_WAVE_HW_ID1__WGP_ID_MASK 0x00003C00L |
48124 | #define SQ_WAVE_HW_ID1__SA_ID_MASK 0x00010000L |
48125 | #define SQ_WAVE_HW_ID1__SE_ID_MASK 0x000C0000L |
48126 | //SQ_WAVE_HW_ID2 |
48127 | #define SQ_WAVE_HW_ID2__QUEUE_ID__SHIFT 0x0 |
48128 | #define SQ_WAVE_HW_ID2__PIPE_ID__SHIFT 0x4 |
48129 | #define SQ_WAVE_HW_ID2__ME_ID__SHIFT 0x8 |
48130 | #define SQ_WAVE_HW_ID2__STATE_ID__SHIFT 0xc |
48131 | #define SQ_WAVE_HW_ID2__WG_ID__SHIFT 0x10 |
48132 | #define SQ_WAVE_HW_ID2__VM_ID__SHIFT 0x18 |
48133 | #define SQ_WAVE_HW_ID2__QUEUE_ID_MASK 0x0000000FL |
48134 | #define SQ_WAVE_HW_ID2__PIPE_ID_MASK 0x00000030L |
48135 | #define SQ_WAVE_HW_ID2__ME_ID_MASK 0x00000300L |
48136 | #define SQ_WAVE_HW_ID2__STATE_ID_MASK 0x00007000L |
48137 | #define SQ_WAVE_HW_ID2__WG_ID_MASK 0x001F0000L |
48138 | #define SQ_WAVE_HW_ID2__VM_ID_MASK 0x0F000000L |
48139 | //SQ_WAVE_POPS_PACKER |
48140 | #define SQ_WAVE_POPS_PACKER__POPS_EN__SHIFT 0x0 |
48141 | #define SQ_WAVE_POPS_PACKER__POPS_PACKER_ID__SHIFT 0x1 |
48142 | #define SQ_WAVE_POPS_PACKER__POPS_EN_MASK 0x00000001L |
48143 | #define SQ_WAVE_POPS_PACKER__POPS_PACKER_ID_MASK 0x00000006L |
48144 | //SQ_WAVE_SCHED_MODE |
48145 | #define SQ_WAVE_SCHED_MODE__DEP_MODE__SHIFT 0x0 |
48146 | #define SQ_WAVE_SCHED_MODE__DEP_MODE_MASK 0x00000003L |
48147 | //SQ_WAVE_VGPR_OFFSET |
48148 | #define SQ_WAVE_VGPR_OFFSET__SRC0__SHIFT 0x0 |
48149 | #define SQ_WAVE_VGPR_OFFSET__SRC1__SHIFT 0x6 |
48150 | #define SQ_WAVE_VGPR_OFFSET__SRC2__SHIFT 0xc |
48151 | #define SQ_WAVE_VGPR_OFFSET__DST__SHIFT 0x12 |
48152 | #define SQ_WAVE_VGPR_OFFSET__SRC0_MASK 0x0000003FL |
48153 | #define SQ_WAVE_VGPR_OFFSET__SRC1_MASK 0x00000FC0L |
48154 | #define SQ_WAVE_VGPR_OFFSET__SRC2_MASK 0x0003F000L |
48155 | #define SQ_WAVE_VGPR_OFFSET__DST_MASK 0x00FC0000L |
48156 | //SQ_WAVE_IB_STS2 |
48157 | #define SQ_WAVE_IB_STS2__INST_PREFETCH__SHIFT 0x0 |
48158 | #define SQ_WAVE_IB_STS2__RESOURCE_OVERRIDE__SHIFT 0x7 |
48159 | #define SQ_WAVE_IB_STS2__MEM_ORDER__SHIFT 0x8 |
48160 | #define SQ_WAVE_IB_STS2__FWD_PROGRESS__SHIFT 0xa |
48161 | #define SQ_WAVE_IB_STS2__WAVE64__SHIFT 0xb |
48162 | #define SQ_WAVE_IB_STS2__INST_PREFETCH_MASK 0x00000003L |
48163 | #define SQ_WAVE_IB_STS2__RESOURCE_OVERRIDE_MASK 0x00000080L |
48164 | #define SQ_WAVE_IB_STS2__MEM_ORDER_MASK 0x00000300L |
48165 | #define SQ_WAVE_IB_STS2__FWD_PROGRESS_MASK 0x00000400L |
48166 | #define SQ_WAVE_IB_STS2__WAVE64_MASK 0x00000800L |
48167 | //SQ_WAVE_SHADER_CYCLES |
48168 | #define SQ_WAVE_SHADER_CYCLES__CYCLES__SHIFT 0x0 |
48169 | #define SQ_WAVE_SHADER_CYCLES__CYCLES_MASK 0x000FFFFFL |
48170 | //SQ_WAVE_TTMP0 |
48171 | #define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 |
48172 | #define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL |
48173 | //SQ_WAVE_TTMP1 |
48174 | #define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 |
48175 | #define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL |
48176 | //SQ_WAVE_TTMP2 |
48177 | #define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 |
48178 | #define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL |
48179 | //SQ_WAVE_TTMP3 |
48180 | #define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 |
48181 | #define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL |
48182 | //SQ_WAVE_TTMP4 |
48183 | #define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 |
48184 | #define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL |
48185 | //SQ_WAVE_TTMP5 |
48186 | #define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 |
48187 | #define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL |
48188 | //SQ_WAVE_TTMP6 |
48189 | #define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 |
48190 | #define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL |
48191 | //SQ_WAVE_TTMP7 |
48192 | #define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 |
48193 | #define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL |
48194 | //SQ_WAVE_TTMP8 |
48195 | #define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 |
48196 | #define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL |
48197 | //SQ_WAVE_TTMP9 |
48198 | #define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 |
48199 | #define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL |
48200 | //SQ_WAVE_TTMP10 |
48201 | #define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 |
48202 | #define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL |
48203 | //SQ_WAVE_TTMP11 |
48204 | #define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 |
48205 | #define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL |
48206 | //SQ_WAVE_TTMP12 |
48207 | #define SQ_WAVE_TTMP12__DATA__SHIFT 0x0 |
48208 | #define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL |
48209 | //SQ_WAVE_TTMP13 |
48210 | #define SQ_WAVE_TTMP13__DATA__SHIFT 0x0 |
48211 | #define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL |
48212 | //SQ_WAVE_TTMP14 |
48213 | #define SQ_WAVE_TTMP14__DATA__SHIFT 0x0 |
48214 | #define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL |
48215 | //SQ_WAVE_TTMP15 |
48216 | #define SQ_WAVE_TTMP15__DATA__SHIFT 0x0 |
48217 | #define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL |
48218 | //SQ_WAVE_M0 |
48219 | #define SQ_WAVE_M0__M0__SHIFT 0x0 |
48220 | #define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL |
48221 | //SQ_WAVE_EXEC_LO |
48222 | #define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 |
48223 | #define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL |
48224 | //SQ_WAVE_EXEC_HI |
48225 | #define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 |
48226 | #define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL |
48227 | //SQ_INTERRUPT_WORD_AUTO |
48228 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0 |
48229 | #define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1 |
48230 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF0_FULL__SHIFT 0x2 |
48231 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF1_FULL__SHIFT 0x3 |
48232 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 |
48233 | #define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x24 |
48234 | #define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x26 |
48235 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x0000000001L |
48236 | #define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x0000000002L |
48237 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF0_FULL_MASK 0x0000000004L |
48238 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF1_FULL_MASK 0x0000000008L |
48239 | #define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_UTC_ERROR_MASK 0x0000000100L |
48240 | #define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000000L |
48241 | #define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xC000000000L |
48242 | //SQ_INTERRUPT_WORD_ERROR |
48243 | #define SQ_INTERRUPT_WORD_ERROR__ERR_DETAIL__SHIFT 0x0 |
48244 | #define SQ_INTERRUPT_WORD_ERROR__ERR_TYPE__SHIFT 0x13 |
48245 | #define SQ_INTERRUPT_WORD_ERROR__SA_ID__SHIFT 0x17 |
48246 | #define SQ_INTERRUPT_WORD_ERROR__PRIV__SHIFT 0x18 |
48247 | #define SQ_INTERRUPT_WORD_ERROR__WAVE_ID__SHIFT 0x19 |
48248 | #define SQ_INTERRUPT_WORD_ERROR__SIMD_ID__SHIFT 0x1e |
48249 | #define SQ_INTERRUPT_WORD_ERROR__WGP_ID__SHIFT 0x20 |
48250 | #define SQ_INTERRUPT_WORD_ERROR__SE_ID__SHIFT 0x24 |
48251 | #define SQ_INTERRUPT_WORD_ERROR__ENCODING__SHIFT 0x26 |
48252 | #define SQ_INTERRUPT_WORD_ERROR__ERR_DETAIL_MASK 0x000007FFFFL |
48253 | #define SQ_INTERRUPT_WORD_ERROR__ERR_TYPE_MASK 0x0000780000L |
48254 | #define SQ_INTERRUPT_WORD_ERROR__SA_ID_MASK 0x0000800000L |
48255 | #define SQ_INTERRUPT_WORD_ERROR__PRIV_MASK 0x0001000000L |
48256 | #define SQ_INTERRUPT_WORD_ERROR__WAVE_ID_MASK 0x003E000000L |
48257 | #define SQ_INTERRUPT_WORD_ERROR__SIMD_ID_MASK 0x00C0000000L |
48258 | #define SQ_INTERRUPT_WORD_ERROR__WGP_ID_MASK 0x0F00000000L |
48259 | #define SQ_INTERRUPT_WORD_ERROR__SE_ID_MASK 0x3000000000L |
48260 | #define SQ_INTERRUPT_WORD_ERROR__ENCODING_MASK 0xC000000000L |
48261 | //SQ_INTERRUPT_WORD_WAVE |
48262 | #define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0 |
48263 | #define SQ_INTERRUPT_WORD_WAVE__SA_ID__SHIFT 0x17 |
48264 | #define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x18 |
48265 | #define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0x19 |
48266 | #define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x1e |
48267 | #define SQ_INTERRUPT_WORD_WAVE__WGP_ID__SHIFT 0x20 |
48268 | #define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x24 |
48269 | #define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x26 |
48270 | #define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0x00007FFFFFL |
48271 | #define SQ_INTERRUPT_WORD_WAVE__SA_ID_MASK 0x0000800000L |
48272 | #define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x0001000000L |
48273 | #define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x003E000000L |
48274 | #define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0x00C0000000L |
48275 | #define SQ_INTERRUPT_WORD_WAVE__WGP_ID_MASK 0x0F00000000L |
48276 | #define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000000L |
48277 | #define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xC000000000L |
48278 | |
48279 | |
48280 | // addressBlock: didtind |
48281 | //DIDT_SQ_CTRL0 |
48282 | #define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 |
48283 | #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1 |
48284 | #define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 |
48285 | #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 |
48286 | #define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 |
48287 | #define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 |
48288 | #define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 |
48289 | #define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 |
48290 | #define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 |
48291 | #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 |
48292 | #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a |
48293 | #define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b |
48294 | #define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c |
48295 | #define DIDT_SQ_CTRL0__DIDT_THROTTLE_MODE__SHIFT 0x1d |
48296 | #define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L |
48297 | #define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L |
48298 | #define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L |
48299 | #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L |
48300 | #define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L |
48301 | #define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L |
48302 | #define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L |
48303 | #define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L |
48304 | #define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L |
48305 | #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L |
48306 | #define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L |
48307 | #define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L |
48308 | #define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L |
48309 | #define DIDT_SQ_CTRL0__DIDT_THROTTLE_MODE_MASK 0x20000000L |
48310 | //DIDT_SQ_CTRL1 |
48311 | #define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 |
48312 | #define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 |
48313 | #define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL |
48314 | #define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L |
48315 | //DIDT_SQ_CTRL2 |
48316 | #define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 |
48317 | #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
48318 | #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
48319 | #define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL |
48320 | #define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
48321 | #define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
48322 | //DIDT_SQ_CTRL_OCP |
48323 | #define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x0 |
48324 | #define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK 0x0000FFFFL |
48325 | //DIDT_SQ_STALL_CTRL |
48326 | #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 |
48327 | #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 |
48328 | #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc |
48329 | #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 |
48330 | #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL |
48331 | #define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L |
48332 | #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L |
48333 | #define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L |
48334 | //DIDT_SQ_TUNING_CTRL |
48335 | #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 |
48336 | #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe |
48337 | #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL |
48338 | #define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L |
48339 | //DIDT_SQ_STALL_AUTO_RELEASE_CTRL |
48340 | #define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 |
48341 | #define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL |
48342 | //DIDT_SQ_CTRL3 |
48343 | #define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 |
48344 | #define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 |
48345 | #define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2 |
48346 | #define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
48347 | #define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 |
48348 | #define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe |
48349 | #define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 |
48350 | #define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 |
48351 | #define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 |
48352 | #define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 |
48353 | #define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b |
48354 | #define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c |
48355 | #define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L |
48356 | #define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L |
48357 | #define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL |
48358 | #define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
48359 | #define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L |
48360 | #define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L |
48361 | #define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L |
48362 | #define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L |
48363 | #define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L |
48364 | #define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L |
48365 | #define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L |
48366 | #define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L |
48367 | //DIDT_SQ_STALL_PATTERN_1_2 |
48368 | #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 |
48369 | #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 |
48370 | #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL |
48371 | #define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L |
48372 | //DIDT_SQ_STALL_PATTERN_3_4 |
48373 | #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 |
48374 | #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 |
48375 | #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL |
48376 | #define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L |
48377 | //DIDT_SQ_STALL_PATTERN_5_6 |
48378 | #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 |
48379 | #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 |
48380 | #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL |
48381 | #define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L |
48382 | //DIDT_SQ_STALL_PATTERN_7 |
48383 | #define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 |
48384 | #define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL |
48385 | //DIDT_SQ_MPD_SCALE_FACTOR |
48386 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 |
48387 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 |
48388 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 |
48389 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc |
48390 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 |
48391 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 |
48392 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 |
48393 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c |
48394 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL |
48395 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L |
48396 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L |
48397 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L |
48398 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L |
48399 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L |
48400 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L |
48401 | #define DIDT_SQ_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L |
48402 | //DIDT_SQ_STALL_RELEASE_CNTL0 |
48403 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT 0x0 |
48404 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 |
48405 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 |
48406 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd |
48407 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK 0x00000001L |
48408 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L |
48409 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL |
48410 | #define DIDT_SQ_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L |
48411 | //DIDT_SQ_STALL_RELEASE_CNTL1 |
48412 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 |
48413 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 |
48414 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa |
48415 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf |
48416 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL |
48417 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L |
48418 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L |
48419 | #define DIDT_SQ_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L |
48420 | //DIDT_SQ_STALL_RELEASE_CNTL_STATUS |
48421 | #define DIDT_SQ_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT 0x0 |
48422 | #define DIDT_SQ_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK 0x00000003L |
48423 | //DIDT_SQ_WEIGHT0_3 |
48424 | #define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 |
48425 | #define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 |
48426 | #define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 |
48427 | #define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 |
48428 | #define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL |
48429 | #define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L |
48430 | #define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L |
48431 | #define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L |
48432 | //DIDT_SQ_WEIGHT4_7 |
48433 | #define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 |
48434 | #define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 |
48435 | #define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 |
48436 | #define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 |
48437 | #define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL |
48438 | #define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L |
48439 | #define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L |
48440 | #define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L |
48441 | //DIDT_SQ_WEIGHT8_11 |
48442 | #define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 |
48443 | #define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 |
48444 | #define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 |
48445 | #define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 |
48446 | #define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL |
48447 | #define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L |
48448 | #define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L |
48449 | #define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L |
48450 | //DIDT_SQ_EDC_CTRL |
48451 | #define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0 |
48452 | #define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
48453 | #define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
48454 | #define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
48455 | #define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
48456 | #define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 |
48457 | #define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 |
48458 | #define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 |
48459 | #define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 |
48460 | #define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 |
48461 | #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 |
48462 | #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 |
48463 | #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT 0x18 |
48464 | #define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L |
48465 | #define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
48466 | #define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
48467 | #define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
48468 | #define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
48469 | #define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L |
48470 | #define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L |
48471 | #define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L |
48472 | #define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L |
48473 | #define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L |
48474 | #define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L |
48475 | #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L |
48476 | #define DIDT_SQ_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK 0x01000000L |
48477 | //DIDT_SQ_EDC_THRESHOLD |
48478 | #define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
48479 | #define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
48480 | //DIDT_SQ_EDC_STALL_PATTERN_1_2 |
48481 | #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 |
48482 | #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 |
48483 | #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL |
48484 | #define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L |
48485 | //DIDT_SQ_EDC_STALL_PATTERN_3_4 |
48486 | #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 |
48487 | #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 |
48488 | #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL |
48489 | #define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L |
48490 | //DIDT_SQ_EDC_STALL_PATTERN_5_6 |
48491 | #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 |
48492 | #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 |
48493 | #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL |
48494 | #define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L |
48495 | //DIDT_SQ_EDC_STALL_PATTERN_7 |
48496 | #define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 |
48497 | #define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL |
48498 | //DIDT_SQ_EDC_TIMER_PERIOD |
48499 | #define DIDT_SQ_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT 0x0 |
48500 | #define DIDT_SQ_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK 0x00003FFFL |
48501 | //DIDT_SQ_THROTTLE_CTRL |
48502 | #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 |
48503 | #define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 |
48504 | #define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
48505 | #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 |
48506 | #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L |
48507 | #define DIDT_SQ_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L |
48508 | #define DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
48509 | #define DIDT_SQ_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L |
48510 | //DIDT_SQ_EDC_STALL_DELAY_1 |
48511 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0 |
48512 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x6 |
48513 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0xc |
48514 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x12 |
48515 | #define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 |
48516 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x0000003FL |
48517 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x00000FC0L |
48518 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x0003F000L |
48519 | #define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0x00FC0000L |
48520 | #define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L |
48521 | //DIDT_SQ_EDC_STALL_DELAY_2 |
48522 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0 |
48523 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x6 |
48524 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0xc |
48525 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x12 |
48526 | #define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 |
48527 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x0000003FL |
48528 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x00000FC0L |
48529 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x0003F000L |
48530 | #define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0x00FC0000L |
48531 | #define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L |
48532 | //DIDT_SQ_EDC_STALL_DELAY_3 |
48533 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x0 |
48534 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x6 |
48535 | #define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED__SHIFT 0xc |
48536 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x0000003FL |
48537 | #define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x00000FC0L |
48538 | #define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFFF000L |
48539 | //DIDT_SQ_EDC_STATUS |
48540 | #define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 |
48541 | #define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 |
48542 | #define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L |
48543 | #define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL |
48544 | //DIDT_SQ_EDC_OVERFLOW |
48545 | #define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
48546 | #define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
48547 | #define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
48548 | #define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
48549 | //DIDT_SQ_EDC_ROLLING_POWER_DELTA |
48550 | #define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
48551 | #define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
48552 | //DIDT_SQ_EDC_PCC_PERF_COUNTER |
48553 | #define DIDT_SQ_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT 0x0 |
48554 | #define DIDT_SQ_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK 0xFFFFFFFFL |
48555 | //DIDT_DB_CTRL0 |
48556 | #define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 |
48557 | #define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1 |
48558 | #define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 |
48559 | #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 |
48560 | #define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 |
48561 | #define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 |
48562 | #define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 |
48563 | #define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 |
48564 | #define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 |
48565 | #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 |
48566 | #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a |
48567 | #define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b |
48568 | #define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c |
48569 | #define DIDT_DB_CTRL0__DIDT_THROTTLE_MODE__SHIFT 0x1d |
48570 | #define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L |
48571 | #define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L |
48572 | #define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L |
48573 | #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L |
48574 | #define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L |
48575 | #define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L |
48576 | #define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L |
48577 | #define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L |
48578 | #define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L |
48579 | #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L |
48580 | #define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L |
48581 | #define DIDT_DB_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L |
48582 | #define DIDT_DB_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L |
48583 | #define DIDT_DB_CTRL0__DIDT_THROTTLE_MODE_MASK 0x20000000L |
48584 | //DIDT_DB_CTRL1 |
48585 | #define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 |
48586 | #define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 |
48587 | #define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL |
48588 | #define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L |
48589 | //DIDT_DB_CTRL2 |
48590 | #define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 |
48591 | #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
48592 | #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
48593 | #define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL |
48594 | #define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
48595 | #define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
48596 | //DIDT_DB_CTRL_OCP |
48597 | #define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x0 |
48598 | #define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK 0x0000FFFFL |
48599 | //DIDT_DB_STALL_CTRL |
48600 | #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 |
48601 | #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 |
48602 | #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc |
48603 | #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 |
48604 | #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL |
48605 | #define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L |
48606 | #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L |
48607 | #define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L |
48608 | //DIDT_DB_TUNING_CTRL |
48609 | #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 |
48610 | #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe |
48611 | #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL |
48612 | #define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L |
48613 | //DIDT_DB_STALL_AUTO_RELEASE_CTRL |
48614 | #define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 |
48615 | #define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL |
48616 | //DIDT_DB_CTRL3 |
48617 | #define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 |
48618 | #define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 |
48619 | #define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2 |
48620 | #define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
48621 | #define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 |
48622 | #define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe |
48623 | #define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 |
48624 | #define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 |
48625 | #define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 |
48626 | #define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 |
48627 | #define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b |
48628 | #define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c |
48629 | #define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L |
48630 | #define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L |
48631 | #define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL |
48632 | #define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
48633 | #define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L |
48634 | #define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L |
48635 | #define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L |
48636 | #define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L |
48637 | #define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L |
48638 | #define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L |
48639 | #define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L |
48640 | #define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L |
48641 | //DIDT_DB_STALL_PATTERN_1_2 |
48642 | #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 |
48643 | #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 |
48644 | #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL |
48645 | #define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L |
48646 | //DIDT_DB_STALL_PATTERN_3_4 |
48647 | #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 |
48648 | #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 |
48649 | #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL |
48650 | #define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L |
48651 | //DIDT_DB_STALL_PATTERN_5_6 |
48652 | #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 |
48653 | #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 |
48654 | #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL |
48655 | #define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L |
48656 | //DIDT_DB_STALL_PATTERN_7 |
48657 | #define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 |
48658 | #define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL |
48659 | //DIDT_DB_MPD_SCALE_FACTOR |
48660 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 |
48661 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 |
48662 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 |
48663 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc |
48664 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 |
48665 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 |
48666 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 |
48667 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c |
48668 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL |
48669 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L |
48670 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L |
48671 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L |
48672 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L |
48673 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L |
48674 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L |
48675 | #define DIDT_DB_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L |
48676 | //DIDT_DB_STALL_RELEASE_CNTL0 |
48677 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT 0x0 |
48678 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 |
48679 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 |
48680 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd |
48681 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK 0x00000001L |
48682 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L |
48683 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL |
48684 | #define DIDT_DB_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L |
48685 | //DIDT_DB_STALL_RELEASE_CNTL1 |
48686 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 |
48687 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 |
48688 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa |
48689 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf |
48690 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL |
48691 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L |
48692 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L |
48693 | #define DIDT_DB_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L |
48694 | //DIDT_DB_STALL_RELEASE_CNTL_STATUS |
48695 | #define DIDT_DB_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT 0x0 |
48696 | #define DIDT_DB_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK 0x00000003L |
48697 | //DIDT_DB_WEIGHT0_3 |
48698 | #define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 |
48699 | #define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 |
48700 | #define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 |
48701 | #define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 |
48702 | #define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL |
48703 | #define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L |
48704 | #define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L |
48705 | #define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L |
48706 | //DIDT_DB_WEIGHT4_7 |
48707 | #define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 |
48708 | #define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 |
48709 | #define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 |
48710 | #define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 |
48711 | #define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL |
48712 | #define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L |
48713 | #define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L |
48714 | #define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L |
48715 | //DIDT_DB_WEIGHT8_11 |
48716 | #define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 |
48717 | #define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 |
48718 | #define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 |
48719 | #define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 |
48720 | #define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL |
48721 | #define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L |
48722 | #define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L |
48723 | #define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L |
48724 | //DIDT_DB_EDC_CTRL |
48725 | #define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0 |
48726 | #define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
48727 | #define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
48728 | #define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
48729 | #define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
48730 | #define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 |
48731 | #define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 |
48732 | #define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 |
48733 | #define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 |
48734 | #define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 |
48735 | #define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 |
48736 | #define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 |
48737 | #define DIDT_DB_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT 0x18 |
48738 | #define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L |
48739 | #define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
48740 | #define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
48741 | #define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
48742 | #define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
48743 | #define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L |
48744 | #define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L |
48745 | #define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L |
48746 | #define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L |
48747 | #define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L |
48748 | #define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L |
48749 | #define DIDT_DB_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L |
48750 | #define DIDT_DB_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK 0x01000000L |
48751 | //DIDT_DB_EDC_THRESHOLD |
48752 | #define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
48753 | #define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
48754 | //DIDT_DB_EDC_STALL_PATTERN_1_2 |
48755 | #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 |
48756 | #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 |
48757 | #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL |
48758 | #define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L |
48759 | //DIDT_DB_EDC_STALL_PATTERN_3_4 |
48760 | #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 |
48761 | #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 |
48762 | #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL |
48763 | #define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L |
48764 | //DIDT_DB_EDC_STALL_PATTERN_5_6 |
48765 | #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 |
48766 | #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 |
48767 | #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL |
48768 | #define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L |
48769 | //DIDT_DB_EDC_STALL_PATTERN_7 |
48770 | #define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 |
48771 | #define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL |
48772 | //DIDT_DB_EDC_TIMER_PERIOD |
48773 | #define DIDT_DB_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT 0x0 |
48774 | #define DIDT_DB_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK 0x00003FFFL |
48775 | //DIDT_DB_THROTTLE_CTRL |
48776 | #define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 |
48777 | #define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 |
48778 | #define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
48779 | #define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 |
48780 | #define DIDT_DB_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L |
48781 | #define DIDT_DB_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L |
48782 | #define DIDT_DB_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
48783 | #define DIDT_DB_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L |
48784 | //DIDT_DB_EDC_STALL_DELAY_1 |
48785 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0 |
48786 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x4 |
48787 | #define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x8 |
48788 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x0000000FL |
48789 | #define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x000000F0L |
48790 | #define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFF00L |
48791 | //DIDT_DB_EDC_STATUS |
48792 | #define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 |
48793 | #define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 |
48794 | #define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L |
48795 | #define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL |
48796 | //DIDT_DB_EDC_OVERFLOW |
48797 | #define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
48798 | #define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
48799 | #define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
48800 | #define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
48801 | //DIDT_DB_EDC_ROLLING_POWER_DELTA |
48802 | #define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
48803 | #define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
48804 | //DIDT_DB_EDC_PCC_PERF_COUNTER |
48805 | #define DIDT_DB_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT 0x0 |
48806 | #define DIDT_DB_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK 0xFFFFFFFFL |
48807 | //DIDT_TD_CTRL0 |
48808 | #define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 |
48809 | #define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1 |
48810 | #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 |
48811 | #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 |
48812 | #define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 |
48813 | #define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 |
48814 | #define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 |
48815 | #define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 |
48816 | #define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 |
48817 | #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 |
48818 | #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a |
48819 | #define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b |
48820 | #define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c |
48821 | #define DIDT_TD_CTRL0__DIDT_THROTTLE_MODE__SHIFT 0x1d |
48822 | #define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L |
48823 | #define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L |
48824 | #define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L |
48825 | #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L |
48826 | #define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L |
48827 | #define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L |
48828 | #define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L |
48829 | #define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L |
48830 | #define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L |
48831 | #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L |
48832 | #define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L |
48833 | #define DIDT_TD_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L |
48834 | #define DIDT_TD_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L |
48835 | #define DIDT_TD_CTRL0__DIDT_THROTTLE_MODE_MASK 0x20000000L |
48836 | //DIDT_TD_CTRL1 |
48837 | #define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 |
48838 | #define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 |
48839 | #define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL |
48840 | #define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L |
48841 | //DIDT_TD_CTRL2 |
48842 | #define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 |
48843 | #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
48844 | #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
48845 | #define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL |
48846 | #define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
48847 | #define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
48848 | //DIDT_TD_CTRL_OCP |
48849 | #define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x0 |
48850 | #define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK 0x0000FFFFL |
48851 | //DIDT_TD_STALL_CTRL |
48852 | #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 |
48853 | #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 |
48854 | #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc |
48855 | #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 |
48856 | #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL |
48857 | #define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L |
48858 | #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L |
48859 | #define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L |
48860 | //DIDT_TD_TUNING_CTRL |
48861 | #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 |
48862 | #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe |
48863 | #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL |
48864 | #define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L |
48865 | //DIDT_TD_STALL_AUTO_RELEASE_CTRL |
48866 | #define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 |
48867 | #define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL |
48868 | //DIDT_TD_CTRL3 |
48869 | #define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 |
48870 | #define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 |
48871 | #define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2 |
48872 | #define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
48873 | #define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 |
48874 | #define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe |
48875 | #define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 |
48876 | #define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 |
48877 | #define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 |
48878 | #define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 |
48879 | #define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b |
48880 | #define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c |
48881 | #define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L |
48882 | #define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L |
48883 | #define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL |
48884 | #define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
48885 | #define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L |
48886 | #define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L |
48887 | #define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L |
48888 | #define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L |
48889 | #define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L |
48890 | #define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L |
48891 | #define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L |
48892 | #define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L |
48893 | //DIDT_TD_STALL_PATTERN_1_2 |
48894 | #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 |
48895 | #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 |
48896 | #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL |
48897 | #define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L |
48898 | //DIDT_TD_STALL_PATTERN_3_4 |
48899 | #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 |
48900 | #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 |
48901 | #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL |
48902 | #define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L |
48903 | //DIDT_TD_STALL_PATTERN_5_6 |
48904 | #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 |
48905 | #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 |
48906 | #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL |
48907 | #define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L |
48908 | //DIDT_TD_STALL_PATTERN_7 |
48909 | #define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 |
48910 | #define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL |
48911 | //DIDT_TD_MPD_SCALE_FACTOR |
48912 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 |
48913 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 |
48914 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 |
48915 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc |
48916 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 |
48917 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 |
48918 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 |
48919 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c |
48920 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL |
48921 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L |
48922 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L |
48923 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L |
48924 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L |
48925 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L |
48926 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L |
48927 | #define DIDT_TD_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L |
48928 | //DIDT_TD_STALL_RELEASE_CNTL0 |
48929 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT 0x0 |
48930 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 |
48931 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 |
48932 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd |
48933 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK 0x00000001L |
48934 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L |
48935 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL |
48936 | #define DIDT_TD_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L |
48937 | //DIDT_TD_STALL_RELEASE_CNTL1 |
48938 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 |
48939 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 |
48940 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa |
48941 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf |
48942 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL |
48943 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L |
48944 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L |
48945 | #define DIDT_TD_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L |
48946 | //DIDT_TD_STALL_RELEASE_CNTL_STATUS |
48947 | #define DIDT_TD_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT 0x0 |
48948 | #define DIDT_TD_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK 0x00000003L |
48949 | //DIDT_TD_WEIGHT0_3 |
48950 | #define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 |
48951 | #define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 |
48952 | #define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 |
48953 | #define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 |
48954 | #define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL |
48955 | #define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L |
48956 | #define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L |
48957 | #define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L |
48958 | //DIDT_TD_WEIGHT4_7 |
48959 | #define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 |
48960 | #define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 |
48961 | #define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 |
48962 | #define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 |
48963 | #define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL |
48964 | #define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L |
48965 | #define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L |
48966 | #define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L |
48967 | //DIDT_TD_WEIGHT8_11 |
48968 | #define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 |
48969 | #define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 |
48970 | #define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 |
48971 | #define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 |
48972 | #define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL |
48973 | #define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L |
48974 | #define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L |
48975 | #define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L |
48976 | //DIDT_TD_EDC_CTRL |
48977 | #define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0 |
48978 | #define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
48979 | #define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
48980 | #define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
48981 | #define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
48982 | #define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 |
48983 | #define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 |
48984 | #define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 |
48985 | #define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 |
48986 | #define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 |
48987 | #define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 |
48988 | #define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 |
48989 | #define DIDT_TD_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT 0x18 |
48990 | #define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L |
48991 | #define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
48992 | #define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
48993 | #define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
48994 | #define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
48995 | #define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L |
48996 | #define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L |
48997 | #define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L |
48998 | #define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L |
48999 | #define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L |
49000 | #define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L |
49001 | #define DIDT_TD_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L |
49002 | #define DIDT_TD_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK 0x01000000L |
49003 | //DIDT_TD_EDC_THRESHOLD |
49004 | #define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
49005 | #define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
49006 | //DIDT_TD_EDC_STALL_PATTERN_1_2 |
49007 | #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 |
49008 | #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 |
49009 | #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL |
49010 | #define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L |
49011 | //DIDT_TD_EDC_STALL_PATTERN_3_4 |
49012 | #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 |
49013 | #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 |
49014 | #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL |
49015 | #define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L |
49016 | //DIDT_TD_EDC_STALL_PATTERN_5_6 |
49017 | #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 |
49018 | #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 |
49019 | #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL |
49020 | #define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L |
49021 | //DIDT_TD_EDC_STALL_PATTERN_7 |
49022 | #define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 |
49023 | #define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL |
49024 | //DIDT_TD_EDC_TIMER_PERIOD |
49025 | #define DIDT_TD_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT 0x0 |
49026 | #define DIDT_TD_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK 0x00003FFFL |
49027 | //DIDT_TD_THROTTLE_CTRL |
49028 | #define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 |
49029 | #define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 |
49030 | #define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
49031 | #define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 |
49032 | #define DIDT_TD_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L |
49033 | #define DIDT_TD_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L |
49034 | #define DIDT_TD_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
49035 | #define DIDT_TD_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L |
49036 | //DIDT_TD_EDC_STALL_DELAY_1 |
49037 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0 |
49038 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x6 |
49039 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0xc |
49040 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x12 |
49041 | #define DIDT_TD_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 |
49042 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x0000003FL |
49043 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x00000FC0L |
49044 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x0003F000L |
49045 | #define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0x00FC0000L |
49046 | #define DIDT_TD_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L |
49047 | //DIDT_TD_EDC_STALL_DELAY_2 |
49048 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0 |
49049 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x6 |
49050 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0xc |
49051 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x12 |
49052 | #define DIDT_TD_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 |
49053 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x0000003FL |
49054 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x00000FC0L |
49055 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x0003F000L |
49056 | #define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0x00FC0000L |
49057 | #define DIDT_TD_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L |
49058 | //DIDT_TD_EDC_STALL_DELAY_3 |
49059 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x0 |
49060 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x6 |
49061 | #define DIDT_TD_EDC_STALL_DELAY_3__UNUSED__SHIFT 0xc |
49062 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x0000003FL |
49063 | #define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x00000FC0L |
49064 | #define DIDT_TD_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFFF000L |
49065 | //DIDT_TD_EDC_STATUS |
49066 | #define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 |
49067 | #define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 |
49068 | #define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L |
49069 | #define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL |
49070 | //DIDT_TD_EDC_OVERFLOW |
49071 | #define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
49072 | #define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
49073 | #define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
49074 | #define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
49075 | //DIDT_TD_EDC_ROLLING_POWER_DELTA |
49076 | #define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
49077 | #define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
49078 | //DIDT_TD_EDC_PCC_PERF_COUNTER |
49079 | #define DIDT_TD_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT 0x0 |
49080 | #define DIDT_TD_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK 0xFFFFFFFFL |
49081 | //DIDT_TCP_CTRL0 |
49082 | #define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 |
49083 | #define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1 |
49084 | #define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 |
49085 | #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 |
49086 | #define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 |
49087 | #define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 |
49088 | #define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 |
49089 | #define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 |
49090 | #define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 |
49091 | #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 |
49092 | #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a |
49093 | #define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b |
49094 | #define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c |
49095 | #define DIDT_TCP_CTRL0__DIDT_THROTTLE_MODE__SHIFT 0x1d |
49096 | #define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L |
49097 | #define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L |
49098 | #define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L |
49099 | #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L |
49100 | #define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L |
49101 | #define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L |
49102 | #define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L |
49103 | #define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L |
49104 | #define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L |
49105 | #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L |
49106 | #define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L |
49107 | #define DIDT_TCP_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L |
49108 | #define DIDT_TCP_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L |
49109 | #define DIDT_TCP_CTRL0__DIDT_THROTTLE_MODE_MASK 0x20000000L |
49110 | //DIDT_TCP_CTRL1 |
49111 | #define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 |
49112 | #define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 |
49113 | #define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL |
49114 | #define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L |
49115 | //DIDT_TCP_CTRL2 |
49116 | #define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 |
49117 | #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 |
49118 | #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b |
49119 | #define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL |
49120 | #define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L |
49121 | #define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L |
49122 | //DIDT_TCP_CTRL_OCP |
49123 | #define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x0 |
49124 | #define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK 0x0000FFFFL |
49125 | //DIDT_TCP_STALL_CTRL |
49126 | #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 |
49127 | #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 |
49128 | #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc |
49129 | #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 |
49130 | #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL |
49131 | #define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L |
49132 | #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L |
49133 | #define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L |
49134 | //DIDT_TCP_TUNING_CTRL |
49135 | #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 |
49136 | #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe |
49137 | #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL |
49138 | #define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L |
49139 | //DIDT_TCP_STALL_AUTO_RELEASE_CTRL |
49140 | #define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 |
49141 | #define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL |
49142 | //DIDT_TCP_CTRL3 |
49143 | #define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 |
49144 | #define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 |
49145 | #define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2 |
49146 | #define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
49147 | #define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 |
49148 | #define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe |
49149 | #define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 |
49150 | #define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 |
49151 | #define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 |
49152 | #define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 |
49153 | #define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b |
49154 | #define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c |
49155 | #define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L |
49156 | #define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L |
49157 | #define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL |
49158 | #define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
49159 | #define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L |
49160 | #define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L |
49161 | #define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L |
49162 | #define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L |
49163 | #define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L |
49164 | #define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L |
49165 | #define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L |
49166 | #define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L |
49167 | //DIDT_TCP_STALL_PATTERN_1_2 |
49168 | #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 |
49169 | #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 |
49170 | #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL |
49171 | #define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L |
49172 | //DIDT_TCP_STALL_PATTERN_3_4 |
49173 | #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 |
49174 | #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 |
49175 | #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL |
49176 | #define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L |
49177 | //DIDT_TCP_STALL_PATTERN_5_6 |
49178 | #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 |
49179 | #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 |
49180 | #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL |
49181 | #define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L |
49182 | //DIDT_TCP_STALL_PATTERN_7 |
49183 | #define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 |
49184 | #define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL |
49185 | //DIDT_TCP_MPD_SCALE_FACTOR |
49186 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1__SHIFT 0x0 |
49187 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2__SHIFT 0x4 |
49188 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3__SHIFT 0x8 |
49189 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4__SHIFT 0xc |
49190 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0__SHIFT 0x10 |
49191 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1__SHIFT 0x14 |
49192 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2__SHIFT 0x18 |
49193 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3__SHIFT 0x1c |
49194 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL1_MASK 0x0000000FL |
49195 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL2_MASK 0x000000F0L |
49196 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL3_MASK 0x00000F00L |
49197 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_RATIO_SCALE_LEVEL4_MASK 0x0000F000L |
49198 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL0_MASK 0x000F0000L |
49199 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL1_MASK 0x00F00000L |
49200 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL2_MASK 0x0F000000L |
49201 | #define DIDT_TCP_MPD_SCALE_FACTOR__MPD_SCALE_LEVEL3_MASK 0xF0000000L |
49202 | //DIDT_TCP_STALL_RELEASE_CNTL0 |
49203 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN__SHIFT 0x0 |
49204 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL__SHIFT 0x1 |
49205 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI__SHIFT 0x2 |
49206 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO__SHIFT 0xd |
49207 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_RELEASE_CNTL_EN_MASK 0x00000001L |
49208 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_STALL_CNTL_SEL_MASK 0x00000002L |
49209 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_HI_MASK 0x00001FFCL |
49210 | #define DIDT_TCP_STALL_RELEASE_CNTL0__DIDT_RELEASE_DELAY_LO_MASK 0x00FFE000L |
49211 | //DIDT_TCP_STALL_RELEASE_CNTL1 |
49212 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI__SHIFT 0x0 |
49213 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI__SHIFT 0x5 |
49214 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO__SHIFT 0xa |
49215 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO__SHIFT 0xf |
49216 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_HI_MASK 0x0000001FL |
49217 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_HI_MASK 0x000003E0L |
49218 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_BASE_RELEASE_ALLOWED_LO_MASK 0x00007C00L |
49219 | #define DIDT_TCP_STALL_RELEASE_CNTL1__DIDT_INCR_RELEASE_ALLOWED_LO_MASK 0x000F8000L |
49220 | //DIDT_TCP_STALL_RELEASE_CNTL_STATUS |
49221 | #define DIDT_TCP_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE__SHIFT 0x0 |
49222 | #define DIDT_TCP_STALL_RELEASE_CNTL_STATUS__DIDT_STALL_RELEASE_CNTL_FSM_STATE_MASK 0x00000003L |
49223 | //DIDT_TCP_WEIGHT0_3 |
49224 | #define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 |
49225 | #define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 |
49226 | #define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 |
49227 | #define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 |
49228 | #define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL |
49229 | #define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L |
49230 | #define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L |
49231 | #define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L |
49232 | //DIDT_TCP_WEIGHT4_7 |
49233 | #define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 |
49234 | #define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 |
49235 | #define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 |
49236 | #define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 |
49237 | #define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL |
49238 | #define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L |
49239 | #define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L |
49240 | #define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L |
49241 | //DIDT_TCP_WEIGHT8_11 |
49242 | #define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 |
49243 | #define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 |
49244 | #define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 |
49245 | #define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 |
49246 | #define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL |
49247 | #define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L |
49248 | #define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L |
49249 | #define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L |
49250 | //DIDT_TCP_EDC_CTRL |
49251 | #define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0 |
49252 | #define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
49253 | #define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
49254 | #define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
49255 | #define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
49256 | #define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 |
49257 | #define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 |
49258 | #define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 |
49259 | #define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 |
49260 | #define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 |
49261 | #define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 |
49262 | #define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL__SHIFT 0x17 |
49263 | #define DIDT_TCP_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN__SHIFT 0x18 |
49264 | #define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L |
49265 | #define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
49266 | #define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
49267 | #define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
49268 | #define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L |
49269 | #define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L |
49270 | #define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L |
49271 | #define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L |
49272 | #define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L |
49273 | #define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L |
49274 | #define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L |
49275 | #define DIDT_TCP_EDC_CTRL__EDC_LEVEL_MODE_SEL_MASK 0x00800000L |
49276 | #define DIDT_TCP_EDC_CTRL__EDC_LEVEL_COMB_ADAPT_MODE_EN_MASK 0x01000000L |
49277 | //DIDT_TCP_EDC_THRESHOLD |
49278 | #define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
49279 | #define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
49280 | //DIDT_TCP_EDC_STALL_PATTERN_1_2 |
49281 | #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 |
49282 | #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 |
49283 | #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL |
49284 | #define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L |
49285 | //DIDT_TCP_EDC_STALL_PATTERN_3_4 |
49286 | #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 |
49287 | #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 |
49288 | #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL |
49289 | #define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L |
49290 | //DIDT_TCP_EDC_STALL_PATTERN_5_6 |
49291 | #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 |
49292 | #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 |
49293 | #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL |
49294 | #define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L |
49295 | //DIDT_TCP_EDC_STALL_PATTERN_7 |
49296 | #define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 |
49297 | #define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL |
49298 | //DIDT_TCP_EDC_TIMER_PERIOD |
49299 | #define DIDT_TCP_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD__SHIFT 0x0 |
49300 | #define DIDT_TCP_EDC_TIMER_PERIOD__EDC_TIMER_PERIOD_MASK 0x00003FFFL |
49301 | //DIDT_TCP_THROTTLE_CTRL |
49302 | #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x0 |
49303 | #define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x1 |
49304 | #define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
49305 | #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x3 |
49306 | #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000001L |
49307 | #define DIDT_TCP_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000002L |
49308 | #define DIDT_TCP_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
49309 | #define DIDT_TCP_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000008L |
49310 | //DIDT_TCP_EDC_STALL_DELAY_1 |
49311 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0 |
49312 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x6 |
49313 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0xc |
49314 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x12 |
49315 | #define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 |
49316 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x0000003FL |
49317 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x00000FC0L |
49318 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x0003F000L |
49319 | #define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0x00FC0000L |
49320 | #define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L |
49321 | //DIDT_TCP_EDC_STALL_DELAY_2 |
49322 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0 |
49323 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x6 |
49324 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0xc |
49325 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x12 |
49326 | #define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 |
49327 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x0000003FL |
49328 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x00000FC0L |
49329 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x0003F000L |
49330 | #define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0x00FC0000L |
49331 | #define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L |
49332 | //DIDT_TCP_EDC_STALL_DELAY_3 |
49333 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x0 |
49334 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x6 |
49335 | #define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED__SHIFT 0xc |
49336 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x0000003FL |
49337 | #define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x00000FC0L |
49338 | #define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFFF000L |
49339 | //DIDT_TCP_EDC_STATUS |
49340 | #define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 |
49341 | #define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 |
49342 | #define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L |
49343 | #define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL |
49344 | //DIDT_TCP_EDC_OVERFLOW |
49345 | #define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
49346 | #define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
49347 | #define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
49348 | #define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
49349 | //DIDT_TCP_EDC_ROLLING_POWER_DELTA |
49350 | #define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
49351 | #define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
49352 | //DIDT_TCP_EDC_PCC_PERF_COUNTER |
49353 | #define DIDT_TCP_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER__SHIFT 0x0 |
49354 | #define DIDT_TCP_EDC_PCC_PERF_COUNTER__EDC_PCC_PERF_COUNTER_MASK 0xFFFFFFFFL |
49355 | //DIDT_SQ_STALL_EVENT_COUNTER |
49356 | #define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 |
49357 | #define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL |
49358 | //DIDT_DB_STALL_EVENT_COUNTER |
49359 | #define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 |
49360 | #define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL |
49361 | //DIDT_TD_STALL_EVENT_COUNTER |
49362 | #define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 |
49363 | #define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL |
49364 | //DIDT_TCP_STALL_EVENT_COUNTER |
49365 | #define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 |
49366 | #define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL |
49367 | |
49368 | |
49369 | #endif |
49370 | |